2 * Copyright (c) 2006-2007 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written consent.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
30 * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
34 * The following controllers are supported by this driver:
42 * The following controllers are not supported by this driver:
48 * BCM5709S A0, A1, B0, B1, B2, C0
52 #include "opt_polling.h"
54 #include <sys/param.h>
56 #include <sys/endian.h>
57 #include <sys/kernel.h>
58 #include <sys/interrupt.h>
60 #include <sys/malloc.h>
61 #include <sys/queue.h>
63 #include <sys/random.h>
66 #include <sys/serialize.h>
67 #include <sys/socket.h>
68 #include <sys/sockio.h>
69 #include <sys/sysctl.h>
72 #include <net/ethernet.h>
74 #include <net/if_arp.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
77 #include <net/if_types.h>
78 #include <net/ifq_var.h>
79 #include <net/vlan/if_vlan_var.h>
80 #include <net/vlan/if_vlan_ether.h>
82 #include <dev/netif/mii_layer/mii.h>
83 #include <dev/netif/mii_layer/miivar.h>
85 #include <bus/pci/pcireg.h>
86 #include <bus/pci/pcivar.h>
88 #include "miibus_if.h"
90 #include <dev/netif/bce/if_bcereg.h>
91 #include <dev/netif/bce/if_bcefw.h>
93 /****************************************************************************/
94 /* BCE Debug Options */
95 /****************************************************************************/
98 static uint32_t bce_debug = BCE_WARN;
102 * 1 = 1 in 2,147,483,648
103 * 256 = 1 in 8,388,608
104 * 2048 = 1 in 1,048,576
105 * 65536 = 1 in 32,768
106 * 1048576 = 1 in 2,048
109 * 1073741824 = 1 in 2
111 * bce_debug_l2fhdr_status_check:
112 * How often the l2_fhdr frame error check will fail.
114 * bce_debug_unexpected_attention:
115 * How often the unexpected attention check will fail.
117 * bce_debug_mbuf_allocation_failure:
118 * How often to simulate an mbuf allocation failure.
120 * bce_debug_dma_map_addr_failure:
121 * How often to simulate a DMA mapping failure.
123 * bce_debug_bootcode_running_failure:
124 * How often to simulate a bootcode failure.
126 static int bce_debug_l2fhdr_status_check = 0;
127 static int bce_debug_unexpected_attention = 0;
128 static int bce_debug_mbuf_allocation_failure = 0;
129 static int bce_debug_dma_map_addr_failure = 0;
130 static int bce_debug_bootcode_running_failure = 0;
132 #endif /* BCE_DEBUG */
135 /****************************************************************************/
136 /* PCI Device ID Table */
138 /* Used by bce_probe() to identify the devices supported by this driver. */
139 /****************************************************************************/
140 #define BCE_DEVDESC_MAX 64
142 static struct bce_type bce_devs[] = {
143 /* BCM5706C Controllers and OEM boards. */
144 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101,
145 "HP NC370T Multifunction Gigabit Server Adapter" },
146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106,
147 "HP NC370i Multifunction Gigabit Server Adapter" },
148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070,
149 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709,
151 "HP NC371i Multifunction Gigabit Server Adapter" },
152 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID,
153 "Broadcom NetXtreme II BCM5706 1000Base-T" },
155 /* BCM5706S controllers and OEM boards. */
156 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
157 "HP NC370F Multifunction Gigabit Server Adapter" },
158 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID,
159 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
161 /* BCM5708C controllers and OEM boards. */
162 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037,
163 "HP NC373T PCIe Multifunction Gig Server Adapter" },
164 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038,
165 "HP NC373i Multifunction Gigabit Server Adapter" },
166 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045,
167 "HP NC374m PCIe Multifunction Adapter" },
168 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID,
169 "Broadcom NetXtreme II BCM5708 1000Base-T" },
171 /* BCM5708S controllers and OEM boards. */
172 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706,
173 "HP NC373m Multifunction Gigabit Server Adapter" },
174 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b,
175 "HP NC373i Multifunction Gigabit Server Adapter" },
176 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d,
177 "HP NC373F PCIe Multifunc Giga Server Adapter" },
178 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID,
179 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
181 /* BCM5709C controllers and OEM boards. */
182 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055,
183 "HP NC382i DP Multifunction Gigabit Server Adapter" },
184 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059,
185 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
186 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID,
187 "Broadcom NetXtreme II BCM5709 1000Base-T" },
189 /* BCM5709S controllers and OEM boards. */
190 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d,
191 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
192 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056,
193 "HP NC382i DP Multifunction Gigabit Server Adapter" },
194 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID,
195 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
197 /* BCM5716 controllers and OEM boards. */
198 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID,
199 "Broadcom NetXtreme II BCM5716 1000Base-T" },
205 /****************************************************************************/
206 /* Supported Flash NVRAM device data. */
207 /****************************************************************************/
208 static const struct flash_spec flash_table[] =
210 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
211 #define NONBUFFERED_FLAGS (BCE_NV_WREN)
214 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
215 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
216 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
218 /* Expansion entry 0001 */
219 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
220 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
221 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
223 /* Saifun SA25F010 (non-buffered flash) */
224 /* strap, cfg1, & write1 need updates */
225 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
226 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
227 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
228 "Non-buffered flash (128kB)"},
229 /* Saifun SA25F020 (non-buffered flash) */
230 /* strap, cfg1, & write1 need updates */
231 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
232 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
233 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
234 "Non-buffered flash (256kB)"},
235 /* Expansion entry 0100 */
236 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
237 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
238 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
240 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
241 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
242 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
243 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
244 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
245 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
246 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
247 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
248 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
249 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
250 /* Saifun SA25F005 (non-buffered flash) */
251 /* strap, cfg1, & write1 need updates */
252 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
253 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
254 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
255 "Non-buffered flash (64kB)"},
257 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
258 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
259 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
261 /* Expansion entry 1001 */
262 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
263 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
264 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
266 /* Expansion entry 1010 */
267 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
268 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
269 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
271 /* ATMEL AT45DB011B (buffered flash) */
272 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
273 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
274 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
275 "Buffered flash (128kB)"},
276 /* Expansion entry 1100 */
277 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
278 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
279 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
281 /* Expansion entry 1101 */
282 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
283 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
284 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
286 /* Ateml Expansion entry 1110 */
287 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
288 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
289 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
290 "Entry 1110 (Atmel)"},
291 /* ATMEL AT45DB021B (buffered flash) */
292 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
293 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
294 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
295 "Buffered flash (256kB)"},
299 * The BCM5709 controllers transparently handle the
300 * differences between Atmel 264 byte pages and all
301 * flash devices which use 256 byte pages, so no
302 * logical-to-physical mapping is required in the
305 static struct flash_spec flash_5709 = {
306 .flags = BCE_NV_BUFFERED,
307 .page_bits = BCM5709_FLASH_PAGE_BITS,
308 .page_size = BCM5709_FLASH_PAGE_SIZE,
309 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
310 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2,
311 .name = "5709/5716 buffered flash (256kB)",
315 /****************************************************************************/
316 /* DragonFly device entry points. */
317 /****************************************************************************/
318 static int bce_probe(device_t);
319 static int bce_attach(device_t);
320 static int bce_detach(device_t);
321 static void bce_shutdown(device_t);
323 /****************************************************************************/
324 /* BCE Debug Data Structure Dump Routines */
325 /****************************************************************************/
327 static void bce_dump_mbuf(struct bce_softc *, struct mbuf *);
328 static void bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
329 static void bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
330 static void bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
331 static void bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
332 static void bce_dump_l2fhdr(struct bce_softc *, int,
333 struct l2_fhdr *) __unused;
334 static void bce_dump_tx_chain(struct bce_softc *, int, int);
335 static void bce_dump_rx_chain(struct bce_softc *, int, int);
336 static void bce_dump_status_block(struct bce_softc *);
337 static void bce_dump_driver_state(struct bce_softc *);
338 static void bce_dump_stats_block(struct bce_softc *) __unused;
339 static void bce_dump_hw_state(struct bce_softc *);
340 static void bce_dump_txp_state(struct bce_softc *);
341 static void bce_dump_rxp_state(struct bce_softc *) __unused;
342 static void bce_dump_tpat_state(struct bce_softc *) __unused;
343 static void bce_freeze_controller(struct bce_softc *) __unused;
344 static void bce_unfreeze_controller(struct bce_softc *) __unused;
345 static void bce_breakpoint(struct bce_softc *);
346 #endif /* BCE_DEBUG */
349 /****************************************************************************/
350 /* BCE Register/Memory Access Routines */
351 /****************************************************************************/
352 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
353 static void bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
354 static void bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
355 static uint32_t bce_shmem_rd(struct bce_softc *, u32);
356 static void bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
357 static int bce_miibus_read_reg(device_t, int, int);
358 static int bce_miibus_write_reg(device_t, int, int, int);
359 static void bce_miibus_statchg(device_t);
362 /****************************************************************************/
363 /* BCE NVRAM Access Routines */
364 /****************************************************************************/
365 static int bce_acquire_nvram_lock(struct bce_softc *);
366 static int bce_release_nvram_lock(struct bce_softc *);
367 static void bce_enable_nvram_access(struct bce_softc *);
368 static void bce_disable_nvram_access(struct bce_softc *);
369 static int bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
371 static int bce_init_nvram(struct bce_softc *);
372 static int bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
373 static int bce_nvram_test(struct bce_softc *);
375 /****************************************************************************/
376 /* BCE DMA Allocate/Free Routines */
377 /****************************************************************************/
378 static int bce_dma_alloc(struct bce_softc *);
379 static void bce_dma_free(struct bce_softc *);
380 static void bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
382 /****************************************************************************/
383 /* BCE Firmware Synchronization and Load */
384 /****************************************************************************/
385 static int bce_fw_sync(struct bce_softc *, uint32_t);
386 static void bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
388 static void bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
390 static void bce_start_cpu(struct bce_softc *, struct cpu_reg *);
391 static void bce_halt_cpu(struct bce_softc *, struct cpu_reg *);
392 static void bce_start_rxp_cpu(struct bce_softc *);
393 static void bce_init_rxp_cpu(struct bce_softc *);
394 static void bce_init_txp_cpu(struct bce_softc *);
395 static void bce_init_tpat_cpu(struct bce_softc *);
396 static void bce_init_cp_cpu(struct bce_softc *);
397 static void bce_init_com_cpu(struct bce_softc *);
398 static void bce_init_cpus(struct bce_softc *);
400 static void bce_stop(struct bce_softc *);
401 static int bce_reset(struct bce_softc *, uint32_t);
402 static int bce_chipinit(struct bce_softc *);
403 static int bce_blockinit(struct bce_softc *);
404 static int bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
406 static void bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
407 static void bce_probe_pci_caps(struct bce_softc *);
408 static void bce_print_adapter_info(struct bce_softc *);
409 static void bce_get_media(struct bce_softc *);
411 static void bce_init_tx_context(struct bce_softc *);
412 static int bce_init_tx_chain(struct bce_softc *);
413 static void bce_init_rx_context(struct bce_softc *);
414 static int bce_init_rx_chain(struct bce_softc *);
415 static void bce_free_rx_chain(struct bce_softc *);
416 static void bce_free_tx_chain(struct bce_softc *);
418 static int bce_encap(struct bce_softc *, struct mbuf **);
419 static void bce_start(struct ifnet *);
420 static int bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
421 static void bce_watchdog(struct ifnet *);
422 static int bce_ifmedia_upd(struct ifnet *);
423 static void bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
424 static void bce_init(void *);
425 static void bce_mgmt_init(struct bce_softc *);
427 static int bce_init_ctx(struct bce_softc *);
428 static void bce_get_mac_addr(struct bce_softc *);
429 static void bce_set_mac_addr(struct bce_softc *);
430 static void bce_phy_intr(struct bce_softc *);
431 static void bce_rx_intr(struct bce_softc *, int);
432 static void bce_tx_intr(struct bce_softc *);
433 static void bce_disable_intr(struct bce_softc *);
434 static void bce_enable_intr(struct bce_softc *, int);
436 #ifdef DEVICE_POLLING
437 static void bce_poll(struct ifnet *, enum poll_cmd, int);
439 static void bce_intr(struct bce_softc *);
440 static void bce_intr_legacy(void *);
441 static void bce_intr_msi(void *);
442 static void bce_intr_msi_oneshot(void *);
443 static void bce_set_rx_mode(struct bce_softc *);
444 static void bce_stats_update(struct bce_softc *);
445 static void bce_tick(void *);
446 static void bce_tick_serialized(struct bce_softc *);
447 static void bce_pulse(void *);
448 static void bce_pulse_check_msi(struct bce_softc *);
449 static void bce_add_sysctls(struct bce_softc *);
451 static void bce_coal_change(struct bce_softc *);
452 static int bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
453 static int bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
454 static int bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
455 static int bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
456 static int bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
457 static int bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
458 static int bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
459 static int bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
460 static int bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
461 uint32_t *, uint32_t);
465 * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023. Linux's bnx2
466 * takes 1023 as the TX ticks limit. However, using 1023 will
467 * cause 5708(B2) to generate extra interrupts (~2000/s) even when
468 * there is _no_ network activity on the NIC.
470 static uint32_t bce_tx_bds_int = 255; /* bcm: 20 */
471 static uint32_t bce_tx_bds = 255; /* bcm: 20 */
472 static uint32_t bce_tx_ticks_int = 1022; /* bcm: 80 */
473 static uint32_t bce_tx_ticks = 1022; /* bcm: 80 */
474 static uint32_t bce_rx_bds_int = 128; /* bcm: 6 */
475 static uint32_t bce_rx_bds = 128; /* bcm: 6 */
476 static uint32_t bce_rx_ticks_int = 125; /* bcm: 18 */
477 static uint32_t bce_rx_ticks = 125; /* bcm: 18 */
479 static int bce_msi_enable = 1;
481 static int bce_rx_pages = RX_PAGES_DEFAULT;
482 static int bce_tx_pages = TX_PAGES_DEFAULT;
484 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
485 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
486 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
487 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
488 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
489 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
490 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
491 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
492 TUNABLE_INT("hw.bce.msi.enable", &bce_msi_enable);
493 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages);
494 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages);
496 /****************************************************************************/
497 /* DragonFly device dispatch table. */
498 /****************************************************************************/
499 static device_method_t bce_methods[] = {
500 /* Device interface */
501 DEVMETHOD(device_probe, bce_probe),
502 DEVMETHOD(device_attach, bce_attach),
503 DEVMETHOD(device_detach, bce_detach),
504 DEVMETHOD(device_shutdown, bce_shutdown),
507 DEVMETHOD(bus_print_child, bus_generic_print_child),
508 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
511 DEVMETHOD(miibus_readreg, bce_miibus_read_reg),
512 DEVMETHOD(miibus_writereg, bce_miibus_write_reg),
513 DEVMETHOD(miibus_statchg, bce_miibus_statchg),
518 static driver_t bce_driver = {
521 sizeof(struct bce_softc)
524 static devclass_t bce_devclass;
527 DECLARE_DUMMY_MODULE(if_bce);
528 MODULE_DEPEND(bce, miibus, 1, 1, 1);
529 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
530 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
533 /****************************************************************************/
534 /* Device probe function. */
536 /* Compares the device to the driver's list of supported devices and */
537 /* reports back to the OS whether this is the right driver for the device. */
540 /* BUS_PROBE_DEFAULT on success, positive value on failure. */
541 /****************************************************************************/
543 bce_probe(device_t dev)
546 uint16_t vid, did, svid, sdid;
548 /* Get the data for the device to be probed. */
549 vid = pci_get_vendor(dev);
550 did = pci_get_device(dev);
551 svid = pci_get_subvendor(dev);
552 sdid = pci_get_subdevice(dev);
554 /* Look through the list of known devices for a match. */
555 for (t = bce_devs; t->bce_name != NULL; ++t) {
556 if (vid == t->bce_vid && did == t->bce_did &&
557 (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
558 (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
559 uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
562 descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
564 /* Print out the device identity. */
565 ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
567 ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
569 device_set_desc_copy(dev, descbuf);
570 kfree(descbuf, M_TEMP);
578 /****************************************************************************/
579 /* PCI Capabilities Probe Function. */
581 /* Walks the PCI capabiites list for the device to find what features are */
586 /****************************************************************************/
588 bce_print_adapter_info(struct bce_softc *sc)
590 device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
592 kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
593 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
596 if (sc->bce_flags & BCE_PCIE_FLAG) {
597 kprintf("Bus (PCIe x%d, ", sc->link_width);
598 switch (sc->link_speed) {
600 kprintf("2.5Gbps); ");
606 kprintf("Unknown link speed); ");
610 kprintf("Bus (PCI%s, %s, %dMHz); ",
611 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
612 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
616 /* Firmware version and device features. */
617 kprintf("B/C (%s)", sc->bce_bc_ver);
619 if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
620 (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
622 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
623 kprintf("MFW[%s]", sc->bce_mfw_ver);
624 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
632 /****************************************************************************/
633 /* PCI Capabilities Probe Function. */
635 /* Walks the PCI capabiites list for the device to find what features are */
640 /****************************************************************************/
642 bce_probe_pci_caps(struct bce_softc *sc)
644 device_t dev = sc->bce_dev;
647 if (pci_is_pcix(dev))
648 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
650 ptr = pci_get_pciecap_ptr(dev);
652 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
654 sc->link_speed = link_status & 0xf;
655 sc->link_width = (link_status >> 4) & 0x3f;
656 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
657 sc->bce_flags |= BCE_PCIE_FLAG;
662 /****************************************************************************/
663 /* Device attach function. */
665 /* Allocates device resources, performs secondary chip identification, */
666 /* resets and initializes the hardware, and initializes driver instance */
670 /* 0 on success, positive value on failure. */
671 /****************************************************************************/
673 bce_attach(device_t dev)
675 struct bce_softc *sc = device_get_softc(dev);
676 struct ifnet *ifp = &sc->arpcom.ac_if;
679 void (*irq_handle)(void *);
684 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
686 pci_enable_busmaster(dev);
688 bce_probe_pci_caps(sc);
690 /* Allocate PCI memory resources. */
692 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
693 RF_ACTIVE | PCI_RF_DENSE);
694 if (sc->bce_res_mem == NULL) {
695 device_printf(dev, "PCI memory allocation failed\n");
698 sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
699 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
701 /* Allocate PCI IRQ resources. */
702 sc->bce_irq_type = pci_alloc_1intr(dev, bce_msi_enable,
703 &sc->bce_irq_rid, &irq_flags);
705 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
706 &sc->bce_irq_rid, irq_flags);
707 if (sc->bce_res_irq == NULL) {
708 device_printf(dev, "PCI map interrupt failed\n");
714 * Configure byte swap and enable indirect register access.
715 * Rely on CPU to do target byte swapping on big endian systems.
716 * Access to registers outside of PCI configurtion space are not
717 * valid until this is done.
719 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
720 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
721 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
723 /* Save ASIC revsion info. */
724 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID);
726 /* Weed out any non-production controller revisions. */
727 switch (BCE_CHIP_ID(sc)) {
728 case BCE_CHIP_ID_5706_A0:
729 case BCE_CHIP_ID_5706_A1:
730 case BCE_CHIP_ID_5708_A0:
731 case BCE_CHIP_ID_5708_B0:
732 case BCE_CHIP_ID_5709_A0:
733 case BCE_CHIP_ID_5709_B0:
734 case BCE_CHIP_ID_5709_B1:
736 /* 5709C B2 seems to work fine */
737 case BCE_CHIP_ID_5709_B2:
739 device_printf(dev, "Unsupported chip id 0x%08x!\n",
745 if (sc->bce_irq_type == PCI_INTR_TYPE_LEGACY) {
746 irq_handle = bce_intr_legacy;
747 } else if (sc->bce_irq_type == PCI_INTR_TYPE_MSI) {
748 irq_handle = bce_intr_msi;
749 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
750 irq_handle = bce_intr_msi_oneshot;
751 sc->bce_flags |= BCE_ONESHOT_MSI_FLAG;
754 panic("%s: unsupported intr type %d",
755 device_get_nameunit(dev), sc->bce_irq_type);
759 * Find the base address for shared memory access.
760 * Newer versions of bootcode use a signature and offset
761 * while older versions use a fixed address.
763 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
764 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
765 BCE_SHM_HDR_SIGNATURE_SIG) {
766 /* Multi-port devices use different offsets in shared memory. */
767 sc->bce_shmem_base = REG_RD_IND(sc,
768 BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
770 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
772 DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
774 /* Fetch the bootcode revision. */
775 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
776 for (i = 0, j = 0; i < 3; i++) {
780 num = (uint8_t)(val >> (24 - (i * 8)));
781 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
782 if (num >= k || !skip0 || k == 1) {
783 sc->bce_bc_ver[j++] = (num / k) + '0';
788 sc->bce_bc_ver[j++] = '.';
791 /* Check if any management firwmare is running. */
792 val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
793 if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
794 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
796 /* Allow time for firmware to enter the running state. */
797 for (i = 0; i < 30; i++) {
798 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
799 if (val & BCE_CONDITION_MFW_RUN_MASK)
805 /* Check the current bootcode state. */
806 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
807 BCE_CONDITION_MFW_RUN_MASK;
808 if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
809 val != BCE_CONDITION_MFW_RUN_NONE) {
810 uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
812 for (i = 0, j = 0; j < 3; j++) {
813 val = bce_reg_rd_ind(sc, addr + j * 4);
815 memcpy(&sc->bce_mfw_ver[i], &val, 4);
820 /* Get PCI bus information (speed and type). */
821 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
822 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
825 sc->bce_flags |= BCE_PCIX_FLAG;
827 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
828 BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
830 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
831 sc->bus_speed_mhz = 133;
834 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
835 sc->bus_speed_mhz = 100;
838 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
839 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
840 sc->bus_speed_mhz = 66;
843 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
844 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
845 sc->bus_speed_mhz = 50;
848 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
849 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
850 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
851 sc->bus_speed_mhz = 33;
855 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
856 sc->bus_speed_mhz = 66;
858 sc->bus_speed_mhz = 33;
861 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
862 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
864 /* Reset the controller. */
865 rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
869 /* Initialize the controller. */
870 rc = bce_chipinit(sc);
872 device_printf(dev, "Controller initialization failed!\n");
876 /* Perform NVRAM test. */
877 rc = bce_nvram_test(sc);
879 device_printf(dev, "NVRAM test failed!\n");
883 /* Fetch the permanent Ethernet MAC address. */
884 bce_get_mac_addr(sc);
887 * Trip points control how many BDs
888 * should be ready before generating an
889 * interrupt while ticks control how long
890 * a BD can sit in the chain before
891 * generating an interrupt. Set the default
892 * values for the RX and TX rings.
896 /* Force more frequent interrupts. */
897 sc->bce_tx_quick_cons_trip_int = 1;
898 sc->bce_tx_quick_cons_trip = 1;
899 sc->bce_tx_ticks_int = 0;
900 sc->bce_tx_ticks = 0;
902 sc->bce_rx_quick_cons_trip_int = 1;
903 sc->bce_rx_quick_cons_trip = 1;
904 sc->bce_rx_ticks_int = 0;
905 sc->bce_rx_ticks = 0;
907 sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
908 sc->bce_tx_quick_cons_trip = bce_tx_bds;
909 sc->bce_tx_ticks_int = bce_tx_ticks_int;
910 sc->bce_tx_ticks = bce_tx_ticks;
912 sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
913 sc->bce_rx_quick_cons_trip = bce_rx_bds;
914 sc->bce_rx_ticks_int = bce_rx_ticks_int;
915 sc->bce_rx_ticks = bce_rx_ticks;
918 /* Update statistics once every second. */
919 sc->bce_stats_ticks = 1000000 & 0xffff00;
921 /* Find the media type for the adapter. */
924 /* Allocate DMA memory resources. */
925 rc = bce_dma_alloc(sc);
927 device_printf(dev, "DMA resource allocation failed!\n");
931 /* Initialize the ifnet interface. */
933 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
934 ifp->if_ioctl = bce_ioctl;
935 ifp->if_start = bce_start;
936 ifp->if_init = bce_init;
937 ifp->if_watchdog = bce_watchdog;
938 #ifdef DEVICE_POLLING
939 ifp->if_poll = bce_poll;
941 ifp->if_mtu = ETHERMTU;
942 ifp->if_hwassist = BCE_IF_HWASSIST;
943 ifp->if_capabilities = BCE_IF_CAPABILITIES;
944 ifp->if_capenable = ifp->if_capabilities;
945 ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD(sc));
946 ifq_set_ready(&ifp->if_snd);
948 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
949 ifp->if_baudrate = IF_Gbps(2.5);
951 ifp->if_baudrate = IF_Gbps(1);
953 /* Assume a standard 1500 byte MTU size for mbuf allocations. */
954 sc->mbuf_alloc_size = MCLBYTES;
956 /* Look for our PHY. */
957 rc = mii_phy_probe(dev, &sc->bce_miibus,
958 bce_ifmedia_upd, bce_ifmedia_sts);
960 device_printf(dev, "PHY probe failed!\n");
964 /* Attach to the Ethernet interface list. */
965 ether_ifattach(ifp, sc->eaddr, NULL);
967 callout_init_mp(&sc->bce_tick_callout);
968 callout_init_mp(&sc->bce_pulse_callout);
970 /* Hookup IRQ last. */
971 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, irq_handle, sc,
972 &sc->bce_intrhand, ifp->if_serializer);
974 device_printf(dev, "Failed to setup IRQ!\n");
979 ifp->if_cpuid = rman_get_cpuid(sc->bce_res_irq);
980 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
982 /* Print some important debugging info. */
983 DBRUN(BCE_INFO, bce_dump_driver_state(sc));
985 /* Add the supported sysctls to the kernel. */
989 * The chip reset earlier notified the bootcode that
990 * a driver is present. We now need to start our pulse
991 * routine so that the bootcode is reminded that we're
996 /* Get the firmware running so IPMI still works */
1000 bce_print_adapter_info(sc);
1009 /****************************************************************************/
1010 /* Device detach function. */
1012 /* Stops the controller, resets the controller, and releases resources. */
1015 /* 0 on success, positive value on failure. */
1016 /****************************************************************************/
1018 bce_detach(device_t dev)
1020 struct bce_softc *sc = device_get_softc(dev);
1022 if (device_is_attached(dev)) {
1023 struct ifnet *ifp = &sc->arpcom.ac_if;
1026 /* Stop and reset the controller. */
1027 lwkt_serialize_enter(ifp->if_serializer);
1028 callout_stop(&sc->bce_pulse_callout);
1030 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1031 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1033 msg = BCE_DRV_MSG_CODE_UNLOAD;
1035 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
1036 lwkt_serialize_exit(ifp->if_serializer);
1038 ether_ifdetach(ifp);
1041 /* If we have a child device on the MII bus remove it too. */
1043 device_delete_child(dev, sc->bce_miibus);
1044 bus_generic_detach(dev);
1046 if (sc->bce_res_irq != NULL) {
1047 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
1051 if (sc->bce_irq_type == PCI_INTR_TYPE_MSI)
1052 pci_release_msi(dev);
1054 if (sc->bce_res_mem != NULL) {
1055 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
1061 if (sc->bce_sysctl_tree != NULL)
1062 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1068 /****************************************************************************/
1069 /* Device shutdown function. */
1071 /* Stops and resets the controller. */
1075 /****************************************************************************/
1077 bce_shutdown(device_t dev)
1079 struct bce_softc *sc = device_get_softc(dev);
1080 struct ifnet *ifp = &sc->arpcom.ac_if;
1083 lwkt_serialize_enter(ifp->if_serializer);
1085 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1086 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1088 msg = BCE_DRV_MSG_CODE_UNLOAD;
1090 lwkt_serialize_exit(ifp->if_serializer);
1094 /****************************************************************************/
1095 /* Indirect register read. */
1097 /* Reads NetXtreme II registers using an index/data register pair in PCI */
1098 /* configuration space. Using this mechanism avoids issues with posted */
1099 /* reads but is much slower than memory-mapped I/O. */
1102 /* The value of the register. */
1103 /****************************************************************************/
1105 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1107 device_t dev = sc->bce_dev;
1109 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1113 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1114 DBPRINT(sc, BCE_EXCESSIVE,
1115 "%s(); offset = 0x%08X, val = 0x%08X\n",
1116 __func__, offset, val);
1120 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1125 /****************************************************************************/
1126 /* Indirect register write. */
1128 /* Writes NetXtreme II registers using an index/data register pair in PCI */
1129 /* configuration space. Using this mechanism avoids issues with posted */
1130 /* writes but is muchh slower than memory-mapped I/O. */
1134 /****************************************************************************/
1136 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1138 device_t dev = sc->bce_dev;
1140 DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1141 __func__, offset, val);
1143 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1144 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1148 /****************************************************************************/
1149 /* Shared memory write. */
1151 /* Writes NetXtreme II shared memory region. */
1155 /****************************************************************************/
1157 bce_shmem_wr(struct bce_softc *sc, uint32_t offset, uint32_t val)
1159 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1163 /****************************************************************************/
1164 /* Shared memory read. */
1166 /* Reads NetXtreme II shared memory region. */
1169 /* The 32 bit value read. */
1170 /****************************************************************************/
1172 bce_shmem_rd(struct bce_softc *sc, uint32_t offset)
1174 return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1178 /****************************************************************************/
1179 /* Context memory write. */
1181 /* The NetXtreme II controller uses context memory to track connection */
1182 /* information for L2 and higher network protocols. */
1186 /****************************************************************************/
1188 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1191 uint32_t idx, offset = ctx_offset + cid_addr;
1192 uint32_t val, retry_cnt = 5;
1194 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1195 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1196 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1197 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1199 for (idx = 0; idx < retry_cnt; idx++) {
1200 val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1201 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1206 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1207 device_printf(sc->bce_dev,
1208 "Unable to write CTX memory: "
1209 "cid_addr = 0x%08X, offset = 0x%08X!\n",
1210 cid_addr, ctx_offset);
1213 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1214 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1219 /****************************************************************************/
1220 /* PHY register read. */
1222 /* Implements register reads on the MII bus. */
1225 /* The value of the register. */
1226 /****************************************************************************/
1228 bce_miibus_read_reg(device_t dev, int phy, int reg)
1230 struct bce_softc *sc = device_get_softc(dev);
1234 /* Make sure we are accessing the correct PHY address. */
1235 if (phy != sc->bce_phy_addr) {
1236 DBPRINT(sc, BCE_VERBOSE,
1237 "Invalid PHY address %d for PHY read!\n", phy);
1241 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1242 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1243 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1245 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1246 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1251 val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1252 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1253 BCE_EMAC_MDIO_COMM_START_BUSY;
1254 REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1256 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1259 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1260 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1263 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1264 val &= BCE_EMAC_MDIO_COMM_DATA;
1269 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1270 if_printf(&sc->arpcom.ac_if,
1271 "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1275 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1278 DBPRINT(sc, BCE_EXCESSIVE,
1279 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1280 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1282 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1283 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1284 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1286 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1287 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1291 return (val & 0xffff);
1295 /****************************************************************************/
1296 /* PHY register write. */
1298 /* Implements register writes on the MII bus. */
1301 /* The value of the register. */
1302 /****************************************************************************/
1304 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1306 struct bce_softc *sc = device_get_softc(dev);
1310 /* Make sure we are accessing the correct PHY address. */
1311 if (phy != sc->bce_phy_addr) {
1312 DBPRINT(sc, BCE_WARN,
1313 "Invalid PHY address %d for PHY write!\n", phy);
1317 DBPRINT(sc, BCE_EXCESSIVE,
1318 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1319 __func__, phy, (uint16_t)(reg & 0xffff),
1320 (uint16_t)(val & 0xffff));
1322 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1323 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1324 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1326 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1327 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1332 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1333 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1334 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1335 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1337 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1340 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1341 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1347 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1348 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1350 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1351 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1352 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1354 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1355 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1363 /****************************************************************************/
1364 /* MII bus status change. */
1366 /* Called by the MII bus driver when the PHY establishes link to set the */
1367 /* MAC interface registers. */
1371 /****************************************************************************/
1373 bce_miibus_statchg(device_t dev)
1375 struct bce_softc *sc = device_get_softc(dev);
1376 struct mii_data *mii = device_get_softc(sc->bce_miibus);
1378 DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1379 mii->mii_media_active);
1382 /* Decode the interface media flags. */
1383 if_printf(&sc->arpcom.ac_if, "Media: ( ");
1384 switch(IFM_TYPE(mii->mii_media_active)) {
1386 kprintf("Ethernet )");
1389 kprintf("Unknown )");
1393 kprintf(" Media Options: ( ");
1394 switch(IFM_SUBTYPE(mii->mii_media_active)) {
1396 kprintf("Autoselect )");
1399 kprintf("Manual )");
1405 kprintf("10Base-T )");
1408 kprintf("100Base-TX )");
1411 kprintf("1000Base-SX )");
1414 kprintf("1000Base-T )");
1421 kprintf(" Global Options: (");
1422 if (mii->mii_media_active & IFM_FDX)
1423 kprintf(" FullDuplex");
1424 if (mii->mii_media_active & IFM_HDX)
1425 kprintf(" HalfDuplex");
1426 if (mii->mii_media_active & IFM_LOOP)
1427 kprintf(" Loopback");
1428 if (mii->mii_media_active & IFM_FLAG0)
1430 if (mii->mii_media_active & IFM_FLAG1)
1432 if (mii->mii_media_active & IFM_FLAG2)
1437 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1440 * Set MII or GMII interface based on the speed negotiated
1443 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1444 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1445 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1446 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1448 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1449 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1453 * Set half or full duplex based on the duplicity negotiated
1456 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1457 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1458 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1460 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1461 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1466 /****************************************************************************/
1467 /* Acquire NVRAM lock. */
1469 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */
1470 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1471 /* for use by the driver. */
1474 /* 0 on success, positive value on failure. */
1475 /****************************************************************************/
1477 bce_acquire_nvram_lock(struct bce_softc *sc)
1482 DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1484 /* Request access to the flash interface. */
1485 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1486 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1487 val = REG_RD(sc, BCE_NVM_SW_ARB);
1488 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1494 if (j >= NVRAM_TIMEOUT_COUNT) {
1495 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1502 /****************************************************************************/
1503 /* Release NVRAM lock. */
1505 /* When the caller is finished accessing NVRAM the lock must be released. */
1506 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1507 /* for use by the driver. */
1510 /* 0 on success, positive value on failure. */
1511 /****************************************************************************/
1513 bce_release_nvram_lock(struct bce_softc *sc)
1518 DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1521 * Relinquish nvram interface.
1523 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1525 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1526 val = REG_RD(sc, BCE_NVM_SW_ARB);
1527 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1533 if (j >= NVRAM_TIMEOUT_COUNT) {
1534 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1541 /****************************************************************************/
1542 /* Enable NVRAM access. */
1544 /* Before accessing NVRAM for read or write operations the caller must */
1545 /* enabled NVRAM access. */
1549 /****************************************************************************/
1551 bce_enable_nvram_access(struct bce_softc *sc)
1555 DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1557 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1558 /* Enable both bits, even on read. */
1559 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1560 val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1564 /****************************************************************************/
1565 /* Disable NVRAM access. */
1567 /* When the caller is finished accessing NVRAM access must be disabled. */
1571 /****************************************************************************/
1573 bce_disable_nvram_access(struct bce_softc *sc)
1577 DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1579 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1581 /* Disable both bits, even after read. */
1582 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1583 val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1587 /****************************************************************************/
1588 /* Read a dword (32 bits) from NVRAM. */
1590 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */
1591 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */
1594 /* 0 on success and the 32 bit value read, positive value on failure. */
1595 /****************************************************************************/
1597 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1603 /* Build the command word. */
1604 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1606 /* Calculate the offset for buffered flash. */
1607 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1608 offset = ((offset / sc->bce_flash_info->page_size) <<
1609 sc->bce_flash_info->page_bits) +
1610 (offset % sc->bce_flash_info->page_size);
1614 * Clear the DONE bit separately, set the address to read,
1615 * and issue the read.
1617 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1618 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1619 REG_WR(sc, BCE_NVM_COMMAND, cmd);
1621 /* Wait for completion. */
1622 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1627 val = REG_RD(sc, BCE_NVM_COMMAND);
1628 if (val & BCE_NVM_COMMAND_DONE) {
1629 val = REG_RD(sc, BCE_NVM_READ);
1632 memcpy(ret_val, &val, 4);
1637 /* Check for errors. */
1638 if (i >= NVRAM_TIMEOUT_COUNT) {
1639 if_printf(&sc->arpcom.ac_if,
1640 "Timeout error reading NVRAM at offset 0x%08X!\n",
1648 /****************************************************************************/
1649 /* Initialize NVRAM access. */
1651 /* Identify the NVRAM device in use and prepare the NVRAM interface to */
1652 /* access that device. */
1655 /* 0 on success, positive value on failure. */
1656 /****************************************************************************/
1658 bce_init_nvram(struct bce_softc *sc)
1661 int j, entry_count, rc = 0;
1662 const struct flash_spec *flash;
1664 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1666 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1667 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1668 sc->bce_flash_info = &flash_5709;
1669 goto bce_init_nvram_get_flash_size;
1672 /* Determine the selected interface. */
1673 val = REG_RD(sc, BCE_NVM_CFG1);
1675 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1678 * Flash reconfiguration is required to support additional
1679 * NVRAM devices not directly supported in hardware.
1680 * Check if the flash interface was reconfigured
1684 if (val & 0x40000000) {
1685 /* Flash interface reconfigured by bootcode. */
1687 DBPRINT(sc, BCE_INFO_LOAD,
1688 "%s(): Flash WAS reconfigured.\n", __func__);
1690 for (j = 0, flash = flash_table; j < entry_count;
1692 if ((val & FLASH_BACKUP_STRAP_MASK) ==
1693 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1694 sc->bce_flash_info = flash;
1699 /* Flash interface not yet reconfigured. */
1702 DBPRINT(sc, BCE_INFO_LOAD,
1703 "%s(): Flash was NOT reconfigured.\n", __func__);
1705 if (val & (1 << 23))
1706 mask = FLASH_BACKUP_STRAP_MASK;
1708 mask = FLASH_STRAP_MASK;
1710 /* Look for the matching NVRAM device configuration data. */
1711 for (j = 0, flash = flash_table; j < entry_count;
1713 /* Check if the device matches any of the known devices. */
1714 if ((val & mask) == (flash->strapping & mask)) {
1715 /* Found a device match. */
1716 sc->bce_flash_info = flash;
1718 /* Request access to the flash interface. */
1719 rc = bce_acquire_nvram_lock(sc);
1723 /* Reconfigure the flash interface. */
1724 bce_enable_nvram_access(sc);
1725 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1726 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1727 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1728 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1729 bce_disable_nvram_access(sc);
1730 bce_release_nvram_lock(sc);
1736 /* Check if a matching device was found. */
1737 if (j == entry_count) {
1738 sc->bce_flash_info = NULL;
1739 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1743 bce_init_nvram_get_flash_size:
1744 /* Write the flash config data to the shared memory interface. */
1745 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2) &
1746 BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1748 sc->bce_flash_size = val;
1750 sc->bce_flash_size = sc->bce_flash_info->total_size;
1752 DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1753 __func__, sc->bce_flash_info->total_size);
1755 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1761 /****************************************************************************/
1762 /* Read an arbitrary range of data from NVRAM. */
1764 /* Prepares the NVRAM interface for access and reads the requested data */
1765 /* into the supplied buffer. */
1768 /* 0 on success and the data read, positive value on failure. */
1769 /****************************************************************************/
1771 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1774 uint32_t cmd_flags, offset32, len32, extra;
1780 /* Request access to the flash interface. */
1781 rc = bce_acquire_nvram_lock(sc);
1785 /* Enable access to flash interface */
1786 bce_enable_nvram_access(sc);
1794 /* XXX should we release nvram lock if read_dword() fails? */
1800 pre_len = 4 - (offset & 3);
1802 if (pre_len >= len32) {
1804 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1806 cmd_flags = BCE_NVM_COMMAND_FIRST;
1809 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1813 memcpy(ret_buf, buf + (offset & 3), pre_len);
1821 extra = 4 - (len32 & 3);
1822 len32 = (len32 + 4) & ~3;
1829 cmd_flags = BCE_NVM_COMMAND_LAST;
1831 cmd_flags = BCE_NVM_COMMAND_FIRST |
1832 BCE_NVM_COMMAND_LAST;
1834 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1836 memcpy(ret_buf, buf, 4 - extra);
1837 } else if (len32 > 0) {
1840 /* Read the first word. */
1844 cmd_flags = BCE_NVM_COMMAND_FIRST;
1846 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1848 /* Advance to the next dword. */
1853 while (len32 > 4 && rc == 0) {
1854 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1856 /* Advance to the next dword. */
1863 goto bce_nvram_read_locked_exit;
1865 cmd_flags = BCE_NVM_COMMAND_LAST;
1866 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1868 memcpy(ret_buf, buf, 4 - extra);
1871 bce_nvram_read_locked_exit:
1872 /* Disable access to flash interface and release the lock. */
1873 bce_disable_nvram_access(sc);
1874 bce_release_nvram_lock(sc);
1880 /****************************************************************************/
1881 /* Verifies that NVRAM is accessible and contains valid data. */
1883 /* Reads the configuration data from NVRAM and verifies that the CRC is */
1887 /* 0 on success, positive value on failure. */
1888 /****************************************************************************/
1890 bce_nvram_test(struct bce_softc *sc)
1892 uint32_t buf[BCE_NVRAM_SIZE / 4];
1893 uint32_t magic, csum;
1894 uint8_t *data = (uint8_t *)buf;
1898 * Check that the device NVRAM is valid by reading
1899 * the magic value at offset 0.
1901 rc = bce_nvram_read(sc, 0, data, 4);
1905 magic = be32toh(buf[0]);
1906 if (magic != BCE_NVRAM_MAGIC) {
1907 if_printf(&sc->arpcom.ac_if,
1908 "Invalid NVRAM magic value! Expected: 0x%08X, "
1909 "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1914 * Verify that the device NVRAM includes valid
1915 * configuration data.
1917 rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1921 csum = ether_crc32_le(data, 0x100);
1922 if (csum != BCE_CRC32_RESIDUAL) {
1923 if_printf(&sc->arpcom.ac_if,
1924 "Invalid Manufacturing Information NVRAM CRC! "
1925 "Expected: 0x%08X, Found: 0x%08X\n",
1926 BCE_CRC32_RESIDUAL, csum);
1930 csum = ether_crc32_le(data + 0x100, 0x100);
1931 if (csum != BCE_CRC32_RESIDUAL) {
1932 if_printf(&sc->arpcom.ac_if,
1933 "Invalid Feature Configuration Information "
1934 "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1935 BCE_CRC32_RESIDUAL, csum);
1942 /****************************************************************************/
1943 /* Identifies the current media type of the controller and sets the PHY */
1948 /****************************************************************************/
1950 bce_get_media(struct bce_softc *sc)
1954 sc->bce_phy_addr = 1;
1956 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1957 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1958 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1959 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1963 * The BCM5709S is software configurable
1964 * for Copper or SerDes operation.
1966 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1968 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1969 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1973 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1974 strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1977 (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1980 if (pci_get_function(sc->bce_dev) == 0) {
1985 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1993 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1997 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
1998 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2001 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
2002 sc->bce_flags |= BCE_NO_WOL_FLAG;
2003 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2004 sc->bce_phy_addr = 2;
2005 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
2006 if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
2007 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
2009 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
2010 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
2011 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
2016 /****************************************************************************/
2017 /* Free any DMA memory owned by the driver. */
2019 /* Scans through each data structre that requires DMA memory and frees */
2020 /* the memory if allocated. */
2024 /****************************************************************************/
2026 bce_dma_free(struct bce_softc *sc)
2030 /* Destroy the status block. */
2031 if (sc->status_tag != NULL) {
2032 if (sc->status_block != NULL) {
2033 bus_dmamap_unload(sc->status_tag, sc->status_map);
2034 bus_dmamem_free(sc->status_tag, sc->status_block,
2037 bus_dma_tag_destroy(sc->status_tag);
2040 /* Destroy the statistics block. */
2041 if (sc->stats_tag != NULL) {
2042 if (sc->stats_block != NULL) {
2043 bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2044 bus_dmamem_free(sc->stats_tag, sc->stats_block,
2047 bus_dma_tag_destroy(sc->stats_tag);
2050 /* Destroy the CTX DMA stuffs. */
2051 if (sc->ctx_tag != NULL) {
2052 for (i = 0; i < sc->ctx_pages; i++) {
2053 if (sc->ctx_block[i] != NULL) {
2054 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
2055 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2059 bus_dma_tag_destroy(sc->ctx_tag);
2062 /* Destroy the TX buffer descriptor DMA stuffs. */
2063 if (sc->tx_bd_chain_tag != NULL) {
2064 for (i = 0; i < sc->tx_pages; i++) {
2065 if (sc->tx_bd_chain[i] != NULL) {
2066 bus_dmamap_unload(sc->tx_bd_chain_tag,
2067 sc->tx_bd_chain_map[i]);
2068 bus_dmamem_free(sc->tx_bd_chain_tag,
2070 sc->tx_bd_chain_map[i]);
2073 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2076 /* Destroy the RX buffer descriptor DMA stuffs. */
2077 if (sc->rx_bd_chain_tag != NULL) {
2078 for (i = 0; i < sc->rx_pages; i++) {
2079 if (sc->rx_bd_chain[i] != NULL) {
2080 bus_dmamap_unload(sc->rx_bd_chain_tag,
2081 sc->rx_bd_chain_map[i]);
2082 bus_dmamem_free(sc->rx_bd_chain_tag,
2084 sc->rx_bd_chain_map[i]);
2087 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2090 /* Destroy the TX mbuf DMA stuffs. */
2091 if (sc->tx_mbuf_tag != NULL) {
2092 for (i = 0; i < TOTAL_TX_BD(sc); i++) {
2093 /* Must have been unloaded in bce_stop() */
2094 KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2095 bus_dmamap_destroy(sc->tx_mbuf_tag,
2096 sc->tx_mbuf_map[i]);
2098 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2101 /* Destroy the RX mbuf DMA stuffs. */
2102 if (sc->rx_mbuf_tag != NULL) {
2103 for (i = 0; i < TOTAL_RX_BD(sc); i++) {
2104 /* Must have been unloaded in bce_stop() */
2105 KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2106 bus_dmamap_destroy(sc->rx_mbuf_tag,
2107 sc->rx_mbuf_map[i]);
2109 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
2110 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2113 /* Destroy the parent tag */
2114 if (sc->parent_tag != NULL)
2115 bus_dma_tag_destroy(sc->parent_tag);
2117 if (sc->tx_bd_chain_map != NULL)
2118 kfree(sc->tx_bd_chain_map, M_DEVBUF);
2119 if (sc->tx_bd_chain != NULL)
2120 kfree(sc->tx_bd_chain, M_DEVBUF);
2121 if (sc->tx_bd_chain_paddr != NULL)
2122 kfree(sc->tx_bd_chain_paddr, M_DEVBUF);
2124 if (sc->rx_bd_chain_map != NULL)
2125 kfree(sc->rx_bd_chain_map, M_DEVBUF);
2126 if (sc->rx_bd_chain != NULL)
2127 kfree(sc->rx_bd_chain, M_DEVBUF);
2128 if (sc->rx_bd_chain_paddr != NULL)
2129 kfree(sc->rx_bd_chain_paddr, M_DEVBUF);
2131 if (sc->tx_mbuf_map != NULL)
2132 kfree(sc->tx_mbuf_map, M_DEVBUF);
2133 if (sc->tx_mbuf_ptr != NULL)
2134 kfree(sc->tx_mbuf_ptr, M_DEVBUF);
2136 if (sc->rx_mbuf_map != NULL)
2137 kfree(sc->rx_mbuf_map, M_DEVBUF);
2138 if (sc->rx_mbuf_ptr != NULL)
2139 kfree(sc->rx_mbuf_ptr, M_DEVBUF);
2140 if (sc->rx_mbuf_paddr != NULL)
2141 kfree(sc->rx_mbuf_paddr, M_DEVBUF);
2145 /****************************************************************************/
2146 /* Get DMA memory from the OS. */
2148 /* Validates that the OS has provided DMA buffers in response to a */
2149 /* bus_dmamap_load() call and saves the physical address of those buffers. */
2150 /* When the callback is used the OS will return 0 for the mapping function */
2151 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */
2152 /* failures back to the caller. */
2156 /****************************************************************************/
2158 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2160 bus_addr_t *busaddr = arg;
2163 * Simulate a mapping failure.
2166 DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2167 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2168 __FILE__, __LINE__);
2171 /* Check for an error and signal the caller that an error occurred. */
2175 KASSERT(nseg == 1, ("only one segment is allowed"));
2176 *busaddr = segs->ds_addr;
2180 /****************************************************************************/
2181 /* Allocate any DMA memory needed by the driver. */
2183 /* Allocates DMA memory needed for the various global structures needed by */
2186 /* Memory alignment requirements: */
2187 /* -----------------+----------+----------+----------+----------+ */
2188 /* Data Structure | 5706 | 5708 | 5709 | 5716 | */
2189 /* -----------------+----------+----------+----------+----------+ */
2190 /* Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
2191 /* Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
2192 /* RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */
2193 /* PG Buffers | none | none | none | none | */
2194 /* TX Buffers | none | none | none | none | */
2195 /* Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */
2196 /* Context Pages(1) | N/A | N/A | 4KiB | 4KiB | */
2197 /* -----------------+----------+----------+----------+----------+ */
2199 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */
2202 /* 0 for success, positive value for failure. */
2203 /****************************************************************************/
2205 bce_dma_alloc(struct bce_softc *sc)
2207 struct ifnet *ifp = &sc->arpcom.ac_if;
2208 int i, j, rc = 0, pages;
2209 bus_addr_t busaddr, max_busaddr;
2210 bus_size_t status_align, stats_align;
2212 pages = device_getenv_int(sc->bce_dev, "rx_pages", bce_rx_pages);
2213 if (pages <= 0 || pages > RX_PAGES_MAX || !powerof2(pages)) {
2214 device_printf(sc->bce_dev, "invalid # of RX pages\n");
2215 pages = RX_PAGES_DEFAULT;
2217 sc->rx_pages = pages;
2219 pages = device_getenv_int(sc->bce_dev, "tx_pages", bce_tx_pages);
2220 if (pages <= 0 || pages > TX_PAGES_MAX || !powerof2(pages)) {
2221 device_printf(sc->bce_dev, "invalid # of TX pages\n");
2222 pages = TX_PAGES_DEFAULT;
2224 sc->tx_pages = pages;
2226 sc->tx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * sc->tx_pages,
2227 M_DEVBUF, M_WAITOK | M_ZERO);
2228 sc->tx_bd_chain = kmalloc(sizeof(struct tx_bd *) * sc->tx_pages,
2229 M_DEVBUF, M_WAITOK | M_ZERO);
2230 sc->tx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * sc->tx_pages,
2231 M_DEVBUF, M_WAITOK | M_ZERO);
2233 sc->rx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * sc->rx_pages,
2234 M_DEVBUF, M_WAITOK | M_ZERO);
2235 sc->rx_bd_chain = kmalloc(sizeof(struct rx_bd *) * sc->rx_pages,
2236 M_DEVBUF, M_WAITOK | M_ZERO);
2237 sc->rx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * sc->rx_pages,
2238 M_DEVBUF, M_WAITOK | M_ZERO);
2240 sc->tx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_TX_BD(sc),
2241 M_DEVBUF, M_WAITOK | M_ZERO);
2242 sc->tx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_TX_BD(sc),
2243 M_DEVBUF, M_WAITOK | M_ZERO);
2245 sc->rx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_RX_BD(sc),
2246 M_DEVBUF, M_WAITOK | M_ZERO);
2247 sc->rx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_RX_BD(sc),
2248 M_DEVBUF, M_WAITOK | M_ZERO);
2249 sc->rx_mbuf_paddr = kmalloc(sizeof(bus_addr_t) * TOTAL_RX_BD(sc),
2250 M_DEVBUF, M_WAITOK | M_ZERO);
2253 * The embedded PCIe to PCI-X bridge (EPB)
2254 * in the 5708 cannot address memory above
2255 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
2257 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2258 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2260 max_busaddr = BUS_SPACE_MAXADDR;
2263 * BCM5709 and BCM5716 uses host memory as cache for context memory.
2265 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2266 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2267 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2268 if (sc->ctx_pages == 0)
2270 if (sc->ctx_pages > BCE_CTX_PAGES) {
2271 device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2283 * Allocate the parent bus DMA tag appropriate for PCI.
2285 rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2286 max_busaddr, BUS_SPACE_MAXADDR,
2288 BUS_SPACE_MAXSIZE_32BIT, 0,
2289 BUS_SPACE_MAXSIZE_32BIT,
2290 0, &sc->parent_tag);
2292 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2297 * Allocate status block.
2299 sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2300 status_align, BCE_STATUS_BLK_SZ,
2301 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2302 &sc->status_tag, &sc->status_map,
2303 &sc->status_block_paddr);
2304 if (sc->status_block == NULL) {
2305 if_printf(ifp, "Could not allocate status block!\n");
2310 * Allocate statistics block.
2312 sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2313 stats_align, BCE_STATS_BLK_SZ,
2314 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2315 &sc->stats_tag, &sc->stats_map,
2316 &sc->stats_block_paddr);
2317 if (sc->stats_block == NULL) {
2318 if_printf(ifp, "Could not allocate statistics block!\n");
2323 * Allocate context block, if needed
2325 if (sc->ctx_pages != 0) {
2326 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2327 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2329 BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2332 if_printf(ifp, "Could not allocate "
2333 "context block DMA tag!\n");
2337 for (i = 0; i < sc->ctx_pages; i++) {
2338 rc = bus_dmamem_alloc(sc->ctx_tag,
2339 (void **)&sc->ctx_block[i],
2340 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2344 if_printf(ifp, "Could not allocate %dth context "
2345 "DMA memory!\n", i);
2349 rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2350 sc->ctx_block[i], BCM_PAGE_SIZE,
2351 bce_dma_map_addr, &busaddr,
2354 if (rc == EINPROGRESS) {
2355 panic("%s coherent memory loading "
2356 "is still in progress!", ifp->if_xname);
2358 if_printf(ifp, "Could not map %dth context "
2359 "DMA memory!\n", i);
2360 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2362 sc->ctx_block[i] = NULL;
2365 sc->ctx_paddr[i] = busaddr;
2370 * Create a DMA tag for the TX buffer descriptor chain,
2371 * allocate and clear the memory, and fetch the
2372 * physical address of the block.
2374 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2375 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2377 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2378 0, &sc->tx_bd_chain_tag);
2380 if_printf(ifp, "Could not allocate "
2381 "TX descriptor chain DMA tag!\n");
2385 for (i = 0; i < sc->tx_pages; i++) {
2386 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2387 (void **)&sc->tx_bd_chain[i],
2388 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2390 &sc->tx_bd_chain_map[i]);
2392 if_printf(ifp, "Could not allocate %dth TX descriptor "
2393 "chain DMA memory!\n", i);
2397 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2398 sc->tx_bd_chain_map[i],
2399 sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2400 bce_dma_map_addr, &busaddr,
2403 if (rc == EINPROGRESS) {
2404 panic("%s coherent memory loading "
2405 "is still in progress!", ifp->if_xname);
2407 if_printf(ifp, "Could not map %dth TX descriptor "
2408 "chain DMA memory!\n", i);
2409 bus_dmamem_free(sc->tx_bd_chain_tag,
2411 sc->tx_bd_chain_map[i]);
2412 sc->tx_bd_chain[i] = NULL;
2416 sc->tx_bd_chain_paddr[i] = busaddr;
2417 /* DRC - Fix for 64 bit systems. */
2418 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2419 i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2422 /* Create a DMA tag for TX mbufs. */
2423 rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2424 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2426 /* BCE_MAX_JUMBO_ETHER_MTU_VLAN */MCLBYTES,
2427 BCE_MAX_SEGMENTS, MCLBYTES,
2428 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2432 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2436 /* Create DMA maps for the TX mbufs clusters. */
2437 for (i = 0; i < TOTAL_TX_BD(sc); i++) {
2438 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2439 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2440 &sc->tx_mbuf_map[i]);
2442 for (j = 0; j < i; ++j) {
2443 bus_dmamap_destroy(sc->tx_mbuf_tag,
2444 sc->tx_mbuf_map[i]);
2446 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2447 sc->tx_mbuf_tag = NULL;
2449 if_printf(ifp, "Unable to create "
2450 "%dth TX mbuf DMA map!\n", i);
2456 * Create a DMA tag for the RX buffer descriptor chain,
2457 * allocate and clear the memory, and fetch the physical
2458 * address of the blocks.
2460 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2461 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2463 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2464 0, &sc->rx_bd_chain_tag);
2466 if_printf(ifp, "Could not allocate "
2467 "RX descriptor chain DMA tag!\n");
2471 for (i = 0; i < sc->rx_pages; i++) {
2472 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2473 (void **)&sc->rx_bd_chain[i],
2474 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2476 &sc->rx_bd_chain_map[i]);
2478 if_printf(ifp, "Could not allocate %dth RX descriptor "
2479 "chain DMA memory!\n", i);
2483 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2484 sc->rx_bd_chain_map[i],
2485 sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2486 bce_dma_map_addr, &busaddr,
2489 if (rc == EINPROGRESS) {
2490 panic("%s coherent memory loading "
2491 "is still in progress!", ifp->if_xname);
2493 if_printf(ifp, "Could not map %dth RX descriptor "
2494 "chain DMA memory!\n", i);
2495 bus_dmamem_free(sc->rx_bd_chain_tag,
2497 sc->rx_bd_chain_map[i]);
2498 sc->rx_bd_chain[i] = NULL;
2502 sc->rx_bd_chain_paddr[i] = busaddr;
2503 /* DRC - Fix for 64 bit systems. */
2504 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2505 i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2508 /* Create a DMA tag for RX mbufs. */
2509 rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2510 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2512 MCLBYTES, 1, MCLBYTES,
2513 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2517 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2521 /* Create tmp DMA map for RX mbuf clusters. */
2522 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2523 &sc->rx_mbuf_tmpmap);
2525 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2526 sc->rx_mbuf_tag = NULL;
2528 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2532 /* Create DMA maps for the RX mbuf clusters. */
2533 for (i = 0; i < TOTAL_RX_BD(sc); i++) {
2534 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2535 &sc->rx_mbuf_map[i]);
2537 for (j = 0; j < i; ++j) {
2538 bus_dmamap_destroy(sc->rx_mbuf_tag,
2539 sc->rx_mbuf_map[j]);
2541 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2542 sc->rx_mbuf_tag = NULL;
2544 if_printf(ifp, "Unable to create "
2545 "%dth RX mbuf DMA map!\n", i);
2553 /****************************************************************************/
2554 /* Firmware synchronization. */
2556 /* Before performing certain events such as a chip reset, synchronize with */
2557 /* the firmware first. */
2560 /* 0 for success, positive value for failure. */
2561 /****************************************************************************/
2563 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2568 /* Don't waste any time if we've timed out before. */
2569 if (sc->bce_fw_timed_out)
2572 /* Increment the message sequence number. */
2573 sc->bce_fw_wr_seq++;
2574 msg_data |= sc->bce_fw_wr_seq;
2576 DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2578 /* Send the message to the bootcode driver mailbox. */
2579 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2581 /* Wait for the bootcode to acknowledge the message. */
2582 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2583 /* Check for a response in the bootcode firmware mailbox. */
2584 val = bce_shmem_rd(sc, BCE_FW_MB);
2585 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2590 /* If we've timed out, tell the bootcode that we've stopped waiting. */
2591 if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2592 (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2593 if_printf(&sc->arpcom.ac_if,
2594 "Firmware synchronization timeout! "
2595 "msg_data = 0x%08X\n", msg_data);
2597 msg_data &= ~BCE_DRV_MSG_CODE;
2598 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2600 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2602 sc->bce_fw_timed_out = 1;
2609 /****************************************************************************/
2610 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */
2614 /****************************************************************************/
2616 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2617 uint32_t rv2p_code_len, uint32_t rv2p_proc)
2622 for (i = 0; i < rv2p_code_len; i += 8) {
2623 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2625 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2628 if (rv2p_proc == RV2P_PROC1) {
2629 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2630 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2632 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2633 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2637 /* Reset the processor, un-stall is done later. */
2638 if (rv2p_proc == RV2P_PROC1)
2639 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2641 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2645 /****************************************************************************/
2646 /* Load RISC processor firmware. */
2648 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */
2649 /* associated with a particular processor. */
2653 /****************************************************************************/
2655 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2661 bce_halt_cpu(sc, cpu_reg);
2663 /* Load the Text area. */
2664 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2666 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2667 REG_WR_IND(sc, offset, fw->text[j]);
2670 /* Load the Data area. */
2671 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2673 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2674 REG_WR_IND(sc, offset, fw->data[j]);
2677 /* Load the SBSS area. */
2678 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2680 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2681 REG_WR_IND(sc, offset, fw->sbss[j]);
2684 /* Load the BSS area. */
2685 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2687 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2688 REG_WR_IND(sc, offset, fw->bss[j]);
2691 /* Load the Read-Only area. */
2692 offset = cpu_reg->spad_base +
2693 (fw->rodata_addr - cpu_reg->mips_view_base);
2695 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2696 REG_WR_IND(sc, offset, fw->rodata[j]);
2699 /* Clear the pre-fetch instruction and set the FW start address. */
2700 REG_WR_IND(sc, cpu_reg->inst, 0);
2701 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2705 /****************************************************************************/
2706 /* Starts the RISC processor. */
2708 /* Assumes the CPU starting address has already been set. */
2712 /****************************************************************************/
2714 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2718 /* Start the CPU. */
2719 val = REG_RD_IND(sc, cpu_reg->mode);
2720 val &= ~cpu_reg->mode_value_halt;
2721 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2722 REG_WR_IND(sc, cpu_reg->mode, val);
2726 /****************************************************************************/
2727 /* Halts the RISC processor. */
2731 /****************************************************************************/
2733 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2738 val = REG_RD_IND(sc, cpu_reg->mode);
2739 val |= cpu_reg->mode_value_halt;
2740 REG_WR_IND(sc, cpu_reg->mode, val);
2741 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2745 /****************************************************************************/
2746 /* Start the RX CPU. */
2750 /****************************************************************************/
2752 bce_start_rxp_cpu(struct bce_softc *sc)
2754 struct cpu_reg cpu_reg;
2756 cpu_reg.mode = BCE_RXP_CPU_MODE;
2757 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2758 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2759 cpu_reg.state = BCE_RXP_CPU_STATE;
2760 cpu_reg.state_value_clear = 0xffffff;
2761 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2762 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2763 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2764 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2765 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2766 cpu_reg.spad_base = BCE_RXP_SCRATCH;
2767 cpu_reg.mips_view_base = 0x8000000;
2769 bce_start_cpu(sc, &cpu_reg);
2773 /****************************************************************************/
2774 /* Initialize the RX CPU. */
2778 /****************************************************************************/
2780 bce_init_rxp_cpu(struct bce_softc *sc)
2782 struct cpu_reg cpu_reg;
2785 cpu_reg.mode = BCE_RXP_CPU_MODE;
2786 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2787 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2788 cpu_reg.state = BCE_RXP_CPU_STATE;
2789 cpu_reg.state_value_clear = 0xffffff;
2790 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2791 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2792 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2793 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2794 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2795 cpu_reg.spad_base = BCE_RXP_SCRATCH;
2796 cpu_reg.mips_view_base = 0x8000000;
2798 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2799 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2800 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2801 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2802 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2803 fw.start_addr = bce_RXP_b09FwStartAddr;
2805 fw.text_addr = bce_RXP_b09FwTextAddr;
2806 fw.text_len = bce_RXP_b09FwTextLen;
2808 fw.text = bce_RXP_b09FwText;
2810 fw.data_addr = bce_RXP_b09FwDataAddr;
2811 fw.data_len = bce_RXP_b09FwDataLen;
2813 fw.data = bce_RXP_b09FwData;
2815 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2816 fw.sbss_len = bce_RXP_b09FwSbssLen;
2818 fw.sbss = bce_RXP_b09FwSbss;
2820 fw.bss_addr = bce_RXP_b09FwBssAddr;
2821 fw.bss_len = bce_RXP_b09FwBssLen;
2823 fw.bss = bce_RXP_b09FwBss;
2825 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2826 fw.rodata_len = bce_RXP_b09FwRodataLen;
2827 fw.rodata_index = 0;
2828 fw.rodata = bce_RXP_b09FwRodata;
2830 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2831 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2832 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2833 fw.start_addr = bce_RXP_b06FwStartAddr;
2835 fw.text_addr = bce_RXP_b06FwTextAddr;
2836 fw.text_len = bce_RXP_b06FwTextLen;
2838 fw.text = bce_RXP_b06FwText;
2840 fw.data_addr = bce_RXP_b06FwDataAddr;
2841 fw.data_len = bce_RXP_b06FwDataLen;
2843 fw.data = bce_RXP_b06FwData;
2845 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2846 fw.sbss_len = bce_RXP_b06FwSbssLen;
2848 fw.sbss = bce_RXP_b06FwSbss;
2850 fw.bss_addr = bce_RXP_b06FwBssAddr;
2851 fw.bss_len = bce_RXP_b06FwBssLen;
2853 fw.bss = bce_RXP_b06FwBss;
2855 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2856 fw.rodata_len = bce_RXP_b06FwRodataLen;
2857 fw.rodata_index = 0;
2858 fw.rodata = bce_RXP_b06FwRodata;
2861 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2862 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2863 /* Delay RXP start until initialization is complete. */
2867 /****************************************************************************/
2868 /* Initialize the TX CPU. */
2872 /****************************************************************************/
2874 bce_init_txp_cpu(struct bce_softc *sc)
2876 struct cpu_reg cpu_reg;
2879 cpu_reg.mode = BCE_TXP_CPU_MODE;
2880 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2881 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2882 cpu_reg.state = BCE_TXP_CPU_STATE;
2883 cpu_reg.state_value_clear = 0xffffff;
2884 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2885 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2886 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2887 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2888 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2889 cpu_reg.spad_base = BCE_TXP_SCRATCH;
2890 cpu_reg.mips_view_base = 0x8000000;
2892 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2893 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2894 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2895 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2896 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2897 fw.start_addr = bce_TXP_b09FwStartAddr;
2899 fw.text_addr = bce_TXP_b09FwTextAddr;
2900 fw.text_len = bce_TXP_b09FwTextLen;
2902 fw.text = bce_TXP_b09FwText;
2904 fw.data_addr = bce_TXP_b09FwDataAddr;
2905 fw.data_len = bce_TXP_b09FwDataLen;
2907 fw.data = bce_TXP_b09FwData;
2909 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2910 fw.sbss_len = bce_TXP_b09FwSbssLen;
2912 fw.sbss = bce_TXP_b09FwSbss;
2914 fw.bss_addr = bce_TXP_b09FwBssAddr;
2915 fw.bss_len = bce_TXP_b09FwBssLen;
2917 fw.bss = bce_TXP_b09FwBss;
2919 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2920 fw.rodata_len = bce_TXP_b09FwRodataLen;
2921 fw.rodata_index = 0;
2922 fw.rodata = bce_TXP_b09FwRodata;
2924 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2925 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2926 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2927 fw.start_addr = bce_TXP_b06FwStartAddr;
2929 fw.text_addr = bce_TXP_b06FwTextAddr;
2930 fw.text_len = bce_TXP_b06FwTextLen;
2932 fw.text = bce_TXP_b06FwText;
2934 fw.data_addr = bce_TXP_b06FwDataAddr;
2935 fw.data_len = bce_TXP_b06FwDataLen;
2937 fw.data = bce_TXP_b06FwData;
2939 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2940 fw.sbss_len = bce_TXP_b06FwSbssLen;
2942 fw.sbss = bce_TXP_b06FwSbss;
2944 fw.bss_addr = bce_TXP_b06FwBssAddr;
2945 fw.bss_len = bce_TXP_b06FwBssLen;
2947 fw.bss = bce_TXP_b06FwBss;
2949 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2950 fw.rodata_len = bce_TXP_b06FwRodataLen;
2951 fw.rodata_index = 0;
2952 fw.rodata = bce_TXP_b06FwRodata;
2955 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2956 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2957 bce_start_cpu(sc, &cpu_reg);
2961 /****************************************************************************/
2962 /* Initialize the TPAT CPU. */
2966 /****************************************************************************/
2968 bce_init_tpat_cpu(struct bce_softc *sc)
2970 struct cpu_reg cpu_reg;
2973 cpu_reg.mode = BCE_TPAT_CPU_MODE;
2974 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2975 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2976 cpu_reg.state = BCE_TPAT_CPU_STATE;
2977 cpu_reg.state_value_clear = 0xffffff;
2978 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2979 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2980 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2981 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2982 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2983 cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2984 cpu_reg.mips_view_base = 0x8000000;
2986 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2987 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2988 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
2989 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
2990 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
2991 fw.start_addr = bce_TPAT_b09FwStartAddr;
2993 fw.text_addr = bce_TPAT_b09FwTextAddr;
2994 fw.text_len = bce_TPAT_b09FwTextLen;
2996 fw.text = bce_TPAT_b09FwText;
2998 fw.data_addr = bce_TPAT_b09FwDataAddr;
2999 fw.data_len = bce_TPAT_b09FwDataLen;
3001 fw.data = bce_TPAT_b09FwData;
3003 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
3004 fw.sbss_len = bce_TPAT_b09FwSbssLen;
3006 fw.sbss = bce_TPAT_b09FwSbss;
3008 fw.bss_addr = bce_TPAT_b09FwBssAddr;
3009 fw.bss_len = bce_TPAT_b09FwBssLen;
3011 fw.bss = bce_TPAT_b09FwBss;
3013 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
3014 fw.rodata_len = bce_TPAT_b09FwRodataLen;
3015 fw.rodata_index = 0;
3016 fw.rodata = bce_TPAT_b09FwRodata;
3018 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
3019 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
3020 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
3021 fw.start_addr = bce_TPAT_b06FwStartAddr;
3023 fw.text_addr = bce_TPAT_b06FwTextAddr;
3024 fw.text_len = bce_TPAT_b06FwTextLen;
3026 fw.text = bce_TPAT_b06FwText;
3028 fw.data_addr = bce_TPAT_b06FwDataAddr;
3029 fw.data_len = bce_TPAT_b06FwDataLen;
3031 fw.data = bce_TPAT_b06FwData;
3033 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
3034 fw.sbss_len = bce_TPAT_b06FwSbssLen;
3036 fw.sbss = bce_TPAT_b06FwSbss;
3038 fw.bss_addr = bce_TPAT_b06FwBssAddr;
3039 fw.bss_len = bce_TPAT_b06FwBssLen;
3041 fw.bss = bce_TPAT_b06FwBss;
3043 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
3044 fw.rodata_len = bce_TPAT_b06FwRodataLen;
3045 fw.rodata_index = 0;
3046 fw.rodata = bce_TPAT_b06FwRodata;
3049 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
3050 bce_load_cpu_fw(sc, &cpu_reg, &fw);
3051 bce_start_cpu(sc, &cpu_reg);
3055 /****************************************************************************/
3056 /* Initialize the CP CPU. */
3060 /****************************************************************************/
3062 bce_init_cp_cpu(struct bce_softc *sc)
3064 struct cpu_reg cpu_reg;
3067 cpu_reg.mode = BCE_CP_CPU_MODE;
3068 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
3069 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
3070 cpu_reg.state = BCE_CP_CPU_STATE;
3071 cpu_reg.state_value_clear = 0xffffff;
3072 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
3073 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
3074 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
3075 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
3076 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
3077 cpu_reg.spad_base = BCE_CP_SCRATCH;
3078 cpu_reg.mips_view_base = 0x8000000;
3080 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3081 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3082 fw.ver_major = bce_CP_b09FwReleaseMajor;
3083 fw.ver_minor = bce_CP_b09FwReleaseMinor;
3084 fw.ver_fix = bce_CP_b09FwReleaseFix;
3085 fw.start_addr = bce_CP_b09FwStartAddr;
3087 fw.text_addr = bce_CP_b09FwTextAddr;
3088 fw.text_len = bce_CP_b09FwTextLen;
3090 fw.text = bce_CP_b09FwText;
3092 fw.data_addr = bce_CP_b09FwDataAddr;
3093 fw.data_len = bce_CP_b09FwDataLen;
3095 fw.data = bce_CP_b09FwData;
3097 fw.sbss_addr = bce_CP_b09FwSbssAddr;
3098 fw.sbss_len = bce_CP_b09FwSbssLen;
3100 fw.sbss = bce_CP_b09FwSbss;
3102 fw.bss_addr = bce_CP_b09FwBssAddr;
3103 fw.bss_len = bce_CP_b09FwBssLen;
3105 fw.bss = bce_CP_b09FwBss;
3107 fw.rodata_addr = bce_CP_b09FwRodataAddr;
3108 fw.rodata_len = bce_CP_b09FwRodataLen;
3109 fw.rodata_index = 0;
3110 fw.rodata = bce_CP_b09FwRodata;
3112 fw.ver_major = bce_CP_b06FwReleaseMajor;
3113 fw.ver_minor = bce_CP_b06FwReleaseMinor;
3114 fw.ver_fix = bce_CP_b06FwReleaseFix;
3115 fw.start_addr = bce_CP_b06FwStartAddr;
3117 fw.text_addr = bce_CP_b06FwTextAddr;
3118 fw.text_len = bce_CP_b06FwTextLen;
3120 fw.text = bce_CP_b06FwText;
3122 fw.data_addr = bce_CP_b06FwDataAddr;
3123 fw.data_len = bce_CP_b06FwDataLen;
3125 fw.data = bce_CP_b06FwData;
3127 fw.sbss_addr = bce_CP_b06FwSbssAddr;
3128 fw.sbss_len = bce_CP_b06FwSbssLen;
3130 fw.sbss = bce_CP_b06FwSbss;
3132 fw.bss_addr = bce_CP_b06FwBssAddr;
3133 fw.bss_len = bce_CP_b06FwBssLen;
3135 fw.bss = bce_CP_b06FwBss;
3137 fw.rodata_addr = bce_CP_b06FwRodataAddr;
3138 fw.rodata_len = bce_CP_b06FwRodataLen;
3139 fw.rodata_index = 0;
3140 fw.rodata = bce_CP_b06FwRodata;
3143 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
3144 bce_load_cpu_fw(sc, &cpu_reg, &fw);
3145 bce_start_cpu(sc, &cpu_reg);
3149 /****************************************************************************/
3150 /* Initialize the COM CPU. */
3154 /****************************************************************************/
3156 bce_init_com_cpu(struct bce_softc *sc)
3158 struct cpu_reg cpu_reg;
3161 cpu_reg.mode = BCE_COM_CPU_MODE;
3162 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3163 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3164 cpu_reg.state = BCE_COM_CPU_STATE;
3165 cpu_reg.state_value_clear = 0xffffff;
3166 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3167 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3168 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3169 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3170 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3171 cpu_reg.spad_base = BCE_COM_SCRATCH;
3172 cpu_reg.mips_view_base = 0x8000000;
3174 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3175 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3176 fw.ver_major = bce_COM_b09FwReleaseMajor;
3177 fw.ver_minor = bce_COM_b09FwReleaseMinor;
3178 fw.ver_fix = bce_COM_b09FwReleaseFix;
3179 fw.start_addr = bce_COM_b09FwStartAddr;
3181 fw.text_addr = bce_COM_b09FwTextAddr;
3182 fw.text_len = bce_COM_b09FwTextLen;
3184 fw.text = bce_COM_b09FwText;
3186 fw.data_addr = bce_COM_b09FwDataAddr;
3187 fw.data_len = bce_COM_b09FwDataLen;
3189 fw.data = bce_COM_b09FwData;
3191 fw.sbss_addr = bce_COM_b09FwSbssAddr;
3192 fw.sbss_len = bce_COM_b09FwSbssLen;
3194 fw.sbss = bce_COM_b09FwSbss;
3196 fw.bss_addr = bce_COM_b09FwBssAddr;
3197 fw.bss_len = bce_COM_b09FwBssLen;
3199 fw.bss = bce_COM_b09FwBss;
3201 fw.rodata_addr = bce_COM_b09FwRodataAddr;
3202 fw.rodata_len = bce_COM_b09FwRodataLen;
3203 fw.rodata_index = 0;
3204 fw.rodata = bce_COM_b09FwRodata;
3206 fw.ver_major = bce_COM_b06FwReleaseMajor;
3207 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3208 fw.ver_fix = bce_COM_b06FwReleaseFix;
3209 fw.start_addr = bce_COM_b06FwStartAddr;
3211 fw.text_addr = bce_COM_b06FwTextAddr;
3212 fw.text_len = bce_COM_b06FwTextLen;
3214 fw.text = bce_COM_b06FwText;
3216 fw.data_addr = bce_COM_b06FwDataAddr;
3217 fw.data_len = bce_COM_b06FwDataLen;
3219 fw.data = bce_COM_b06FwData;
3221 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3222 fw.sbss_len = bce_COM_b06FwSbssLen;
3224 fw.sbss = bce_COM_b06FwSbss;
3226 fw.bss_addr = bce_COM_b06FwBssAddr;
3227 fw.bss_len = bce_COM_b06FwBssLen;
3229 fw.bss = bce_COM_b06FwBss;
3231 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3232 fw.rodata_len = bce_COM_b06FwRodataLen;
3233 fw.rodata_index = 0;
3234 fw.rodata = bce_COM_b06FwRodata;
3237 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3238 bce_load_cpu_fw(sc, &cpu_reg, &fw);
3239 bce_start_cpu(sc, &cpu_reg);
3243 /****************************************************************************/
3244 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */
3246 /* Loads the firmware for each CPU and starts the CPU. */
3250 /****************************************************************************/
3252 bce_init_cpus(struct bce_softc *sc)
3254 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3255 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3256 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3257 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3258 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3259 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3260 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3262 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3263 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3264 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3265 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3268 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3269 sizeof(bce_rv2p_proc1), RV2P_PROC1);
3270 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3271 sizeof(bce_rv2p_proc2), RV2P_PROC2);
3274 bce_init_rxp_cpu(sc);
3275 bce_init_txp_cpu(sc);
3276 bce_init_tpat_cpu(sc);
3277 bce_init_com_cpu(sc);
3278 bce_init_cp_cpu(sc);
3282 /****************************************************************************/
3283 /* Initialize context memory. */
3285 /* Clears the memory associated with each Context ID (CID). */
3289 /****************************************************************************/
3291 bce_init_ctx(struct bce_softc *sc)
3293 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3294 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3295 /* DRC: Replace this constant value with a #define. */
3296 int i, retry_cnt = 10;
3300 * BCM5709 context memory may be cached
3301 * in host memory so prepare the host memory
3304 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3306 val |= (BCM_PAGE_BITS - 8) << 16;
3307 REG_WR(sc, BCE_CTX_COMMAND, val);
3309 /* Wait for mem init command to complete. */
3310 for (i = 0; i < retry_cnt; i++) {
3311 val = REG_RD(sc, BCE_CTX_COMMAND);
3312 if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3316 if (i == retry_cnt) {
3317 device_printf(sc->bce_dev,
3318 "Context memory initialization failed!\n");
3322 for (i = 0; i < sc->ctx_pages; i++) {
3326 * Set the physical address of the context
3329 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3330 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3331 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3332 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3333 BCE_ADDR_HI(sc->ctx_paddr[i]));
3334 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3335 i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3338 * Verify that the context memory write was successful.
3340 for (j = 0; j < retry_cnt; j++) {
3341 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3343 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3347 if (j == retry_cnt) {
3348 device_printf(sc->bce_dev,
3349 "Failed to initialize context page!\n");
3354 uint32_t vcid_addr, offset;
3357 * For the 5706/5708, context memory is local to
3358 * the controller, so initialize the controller
3362 vcid_addr = GET_CID_ADDR(96);
3364 vcid_addr -= PHY_CTX_SIZE;
3366 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3367 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3369 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3370 CTX_WR(sc, 0x00, offset, 0);
3372 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3373 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3380 /****************************************************************************/
3381 /* Fetch the permanent MAC address of the controller. */
3385 /****************************************************************************/
3387 bce_get_mac_addr(struct bce_softc *sc)
3389 uint32_t mac_lo = 0, mac_hi = 0;
3392 * The NetXtreme II bootcode populates various NIC
3393 * power-on and runtime configuration items in a
3394 * shared memory area. The factory configured MAC
3395 * address is available from both NVRAM and the
3396 * shared memory area so we'll read the value from
3397 * shared memory for speed.
3400 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER);
3401 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
3403 if (mac_lo == 0 && mac_hi == 0) {
3404 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3406 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3407 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3408 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3409 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3410 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3411 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3414 DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3418 /****************************************************************************/
3419 /* Program the MAC address. */
3423 /****************************************************************************/
3425 bce_set_mac_addr(struct bce_softc *sc)
3427 const uint8_t *mac_addr = sc->eaddr;
3430 DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3433 val = (mac_addr[0] << 8) | mac_addr[1];
3434 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3436 val = (mac_addr[2] << 24) |
3437 (mac_addr[3] << 16) |
3438 (mac_addr[4] << 8) |
3440 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3444 /****************************************************************************/
3445 /* Stop the controller. */
3449 /****************************************************************************/
3451 bce_stop(struct bce_softc *sc)
3453 struct ifnet *ifp = &sc->arpcom.ac_if;
3455 ASSERT_SERIALIZED(ifp->if_serializer);
3457 callout_stop(&sc->bce_tick_callout);
3459 /* Disable the transmit/receive blocks. */
3460 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3461 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3464 bce_disable_intr(sc);
3466 /* Free the RX lists. */
3467 bce_free_rx_chain(sc);
3469 /* Free TX buffers. */
3470 bce_free_tx_chain(sc);
3473 sc->bce_coalchg_mask = 0;
3475 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3481 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3486 /* Wait for pending PCI transactions to complete. */
3487 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3488 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3489 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3490 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3491 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3492 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3496 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3497 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3498 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3499 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3500 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3503 /* Assume bootcode is running. */
3504 sc->bce_fw_timed_out = 0;
3505 sc->bce_drv_cardiac_arrest = 0;
3507 /* Give the firmware a chance to prepare for the reset. */
3508 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3510 if_printf(&sc->arpcom.ac_if,
3511 "Firmware is not ready for reset\n");
3515 /* Set a firmware reminder that this is a soft reset. */
3516 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE,
3517 BCE_DRV_RESET_SIGNATURE_MAGIC);
3519 /* Dummy read to force the chip to complete all current transactions. */
3520 val = REG_RD(sc, BCE_MISC_ID);
3523 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3524 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3525 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3526 REG_RD(sc, BCE_MISC_COMMAND);
3529 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3530 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3532 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3534 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3535 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3536 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3537 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3539 /* Allow up to 30us for reset to complete. */
3540 for (i = 0; i < 10; i++) {
3541 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3542 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3543 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3548 /* Check that reset completed successfully. */
3549 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3550 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3551 if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3556 /* Make sure byte swapping is properly configured. */
3557 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3558 if (val != 0x01020304) {
3559 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3563 /* Just completed a reset, assume that firmware is running again. */
3564 sc->bce_fw_timed_out = 0;
3565 sc->bce_drv_cardiac_arrest = 0;
3567 /* Wait for the firmware to finish its initialization. */
3568 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3570 if_printf(&sc->arpcom.ac_if,
3571 "Firmware did not complete initialization!\n");
3578 bce_chipinit(struct bce_softc *sc)
3583 /* Make sure the interrupt is not active. */
3584 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3585 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3588 * Initialize DMA byte/word swapping, configure the number of DMA
3589 * channels and PCI clock compensation delay.
3591 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3592 BCE_DMA_CONFIG_DATA_WORD_SWAP |
3593 #if BYTE_ORDER == BIG_ENDIAN
3594 BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3596 BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3597 DMA_READ_CHANS << 12 |
3598 DMA_WRITE_CHANS << 16;
3600 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3602 if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3603 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3606 * This setting resolves a problem observed on certain Intel PCI
3607 * chipsets that cannot handle multiple outstanding DMA operations.
3608 * See errata E9_5706A1_65.
3610 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3611 BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3612 !(sc->bce_flags & BCE_PCIX_FLAG))
3613 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3615 REG_WR(sc, BCE_DMA_CONFIG, val);
3617 /* Enable the RX_V2P and Context state machines before access. */
3618 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3619 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3620 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3621 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3623 /* Initialize context mapping and zero out the quick contexts. */
3624 rc = bce_init_ctx(sc);
3628 /* Initialize the on-boards CPUs */
3631 /* Enable management frames (NC-SI) to flow to the MCP. */
3632 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3633 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) |
3634 BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3635 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3638 /* Prepare NVRAM for access. */
3639 rc = bce_init_nvram(sc);
3643 /* Set the kernel bypass block size */
3644 val = REG_RD(sc, BCE_MQ_CONFIG);
3645 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3646 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3648 /* Enable bins used on the 5709/5716. */
3649 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3650 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3651 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3652 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3653 val |= BCE_MQ_CONFIG_HALT_DIS;
3656 REG_WR(sc, BCE_MQ_CONFIG, val);
3658 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3659 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3660 REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3662 /* Set the page size and clear the RV2P processor stall bits. */
3663 val = (BCM_PAGE_BITS - 8) << 24;
3664 REG_WR(sc, BCE_RV2P_CONFIG, val);
3666 /* Configure page size. */
3667 val = REG_RD(sc, BCE_TBDR_CONFIG);
3668 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3669 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3670 REG_WR(sc, BCE_TBDR_CONFIG, val);
3672 /* Set the perfect match control register to default. */
3673 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
3679 /****************************************************************************/
3680 /* Initialize the controller in preparation to send/receive traffic. */
3683 /* 0 for success, positive value for failure. */
3684 /****************************************************************************/
3686 bce_blockinit(struct bce_softc *sc)
3691 /* Load the hardware default MAC address. */
3692 bce_set_mac_addr(sc);
3694 /* Set the Ethernet backoff seed value */
3695 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3696 sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3697 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3699 sc->last_status_idx = 0;
3700 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3702 sc->pulse_check_status_idx = 0xffff;
3704 /* Set up link change interrupt generation. */
3705 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3707 /* Program the physical address of the status block. */
3708 REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3709 REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3711 /* Program the physical address of the statistics block. */
3712 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3713 BCE_ADDR_LO(sc->stats_block_paddr));
3714 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3715 BCE_ADDR_HI(sc->stats_block_paddr));
3717 /* Program various host coalescing parameters. */
3718 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3719 (sc->bce_tx_quick_cons_trip_int << 16) |
3720 sc->bce_tx_quick_cons_trip);
3721 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3722 (sc->bce_rx_quick_cons_trip_int << 16) |
3723 sc->bce_rx_quick_cons_trip);
3724 REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3725 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3726 REG_WR(sc, BCE_HC_TX_TICKS,
3727 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3728 REG_WR(sc, BCE_HC_RX_TICKS,
3729 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3730 REG_WR(sc, BCE_HC_COM_TICKS,
3731 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3732 REG_WR(sc, BCE_HC_CMD_TICKS,
3733 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3734 REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3735 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
3737 val = BCE_HC_CONFIG_TX_TMR_MODE | BCE_HC_CONFIG_COLLECT_STATS;
3738 if (sc->bce_flags & BCE_ONESHOT_MSI_FLAG) {
3740 if_printf(&sc->arpcom.ac_if, "oneshot MSI\n");
3741 val |= BCE_HC_CONFIG_ONE_SHOT | BCE_HC_CONFIG_USE_INT_PARAM;
3743 REG_WR(sc, BCE_HC_CONFIG, val);
3745 /* Clear the internal statistics counters. */
3746 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3748 /* Verify that bootcode is running. */
3749 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
3751 DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3752 if_printf(&sc->arpcom.ac_if,
3753 "%s(%d): Simulating bootcode failure.\n",
3754 __FILE__, __LINE__);
3757 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3758 BCE_DEV_INFO_SIGNATURE_MAGIC) {
3759 if_printf(&sc->arpcom.ac_if,
3760 "Bootcode not running! Found: 0x%08X, "
3761 "Expected: 08%08X\n",
3762 reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3763 BCE_DEV_INFO_SIGNATURE_MAGIC);
3768 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3769 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3770 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3771 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3772 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3775 /* Allow bootcode to apply any additional fixes before enabling MAC. */
3776 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3778 /* Enable link state change interrupt generation. */
3779 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3781 /* Enable the RXP. */
3782 bce_start_rxp_cpu(sc);
3784 /* Disable management frames (NC-SI) from flowing to the MCP. */
3785 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3786 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
3787 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3788 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3791 /* Enable all remaining blocks in the MAC. */
3792 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3793 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3794 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3795 BCE_MISC_ENABLE_DEFAULT_XI);
3797 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
3799 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3802 /* Save the current host coalescing block settings. */
3803 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
3809 /****************************************************************************/
3810 /* Encapsulate an mbuf cluster into the rx_bd chain. */
3812 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */
3813 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */
3817 /* 0 for success, positive value for failure. */
3818 /****************************************************************************/
3820 bce_newbuf_std(struct bce_softc *sc, uint16_t *prod, uint16_t *chain_prod,
3821 uint32_t *prod_bseq, int init)
3824 bus_dma_segment_t seg;
3828 uint16_t debug_chain_prod = *chain_prod;
3831 /* Make sure the inputs are valid. */
3832 DBRUNIF((*chain_prod > MAX_RX_BD(sc)),
3833 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3834 "RX producer out of range: 0x%04X > 0x%04X\n",
3836 *chain_prod, (uint16_t)MAX_RX_BD(sc)));
3838 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3839 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3841 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3842 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3843 "Simulating mbuf allocation failure.\n",
3844 __FILE__, __LINE__);
3845 sc->mbuf_alloc_failed++;
3848 /* This is a new mbuf allocation. */
3849 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3852 DBRUNIF(1, sc->rx_mbuf_alloc++);
3854 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
3856 /* Map the mbuf cluster into device memory. */
3857 error = bus_dmamap_load_mbuf_segment(sc->rx_mbuf_tag,
3858 sc->rx_mbuf_tmpmap, m_new, &seg, 1, &nseg,
3863 if_printf(&sc->arpcom.ac_if,
3864 "Error mapping mbuf into RX chain!\n");
3866 DBRUNIF(1, sc->rx_mbuf_alloc--);
3870 if (sc->rx_mbuf_ptr[*chain_prod] != NULL) {
3871 bus_dmamap_unload(sc->rx_mbuf_tag,
3872 sc->rx_mbuf_map[*chain_prod]);
3875 map = sc->rx_mbuf_map[*chain_prod];
3876 sc->rx_mbuf_map[*chain_prod] = sc->rx_mbuf_tmpmap;
3877 sc->rx_mbuf_tmpmap = map;
3879 /* Watch for overflow. */
3880 DBRUNIF((sc->free_rx_bd > USABLE_RX_BD(sc)),
3881 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3882 "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3883 __FILE__, __LINE__, sc->free_rx_bd,
3884 (uint16_t)USABLE_RX_BD(sc)));
3886 /* Update some debug statistic counters */
3887 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3888 sc->rx_low_watermark = sc->free_rx_bd);
3889 DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3891 /* Save the mbuf and update our counter. */
3892 sc->rx_mbuf_ptr[*chain_prod] = m_new;
3893 sc->rx_mbuf_paddr[*chain_prod] = seg.ds_addr;
3896 bce_setup_rxdesc_std(sc, *chain_prod, prod_bseq);
3898 DBRUN(BCE_VERBOSE_RECV,
3899 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 1));
3901 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
3902 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3909 bce_setup_rxdesc_std(struct bce_softc *sc, uint16_t chain_prod, uint32_t *prod_bseq)
3915 paddr = sc->rx_mbuf_paddr[chain_prod];
3916 len = sc->rx_mbuf_ptr[chain_prod]->m_len;
3918 /* Setup the rx_bd for the first segment. */
3919 rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
3921 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(paddr));
3922 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(paddr));
3923 rxbd->rx_bd_len = htole32(len);
3924 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3927 rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
3931 /****************************************************************************/
3932 /* Initialize the TX context memory. */
3936 /****************************************************************************/
3938 bce_init_tx_context(struct bce_softc *sc)
3942 /* Initialize the context ID for an L2 TX chain. */
3943 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3944 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3945 /* Set the CID type to support an L2 connection. */
3946 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3947 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
3948 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3949 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE_XI, val);
3951 /* Point the hardware to the first page in the chain. */
3952 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3953 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3954 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
3955 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3956 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3957 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
3959 /* Set the CID type to support an L2 connection. */
3960 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3961 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
3962 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3963 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
3965 /* Point the hardware to the first page in the chain. */
3966 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3967 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3968 BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
3969 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3970 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3971 BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
3976 /****************************************************************************/
3977 /* Allocate memory and initialize the TX data structures. */
3980 /* 0 for success, positive value for failure. */
3981 /****************************************************************************/
3983 bce_init_tx_chain(struct bce_softc *sc)
3988 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3990 /* Set the initial TX producer/consumer indices. */
3993 sc->tx_prod_bseq = 0;
3995 sc->max_tx_bd = USABLE_TX_BD(sc);
3996 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD(sc));
3997 DBRUNIF(1, sc->tx_full_count = 0);
4000 * The NetXtreme II supports a linked-list structre called
4001 * a Buffer Descriptor Chain (or BD chain). A BD chain
4002 * consists of a series of 1 or more chain pages, each of which
4003 * consists of a fixed number of BD entries.
4004 * The last BD entry on each page is a pointer to the next page
4005 * in the chain, and the last pointer in the BD chain
4006 * points back to the beginning of the chain.
4009 /* Set the TX next pointer chain entries. */
4010 for (i = 0; i < sc->tx_pages; i++) {
4013 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
4015 /* Check if we've reached the last page. */
4016 if (i == (sc->tx_pages - 1))
4021 txbd->tx_bd_haddr_hi =
4022 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
4023 txbd->tx_bd_haddr_lo =
4024 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
4026 bce_init_tx_context(sc);
4032 /****************************************************************************/
4033 /* Free memory and clear the TX data structures. */
4037 /****************************************************************************/
4039 bce_free_tx_chain(struct bce_softc *sc)
4043 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4045 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
4046 for (i = 0; i < TOTAL_TX_BD(sc); i++) {
4047 if (sc->tx_mbuf_ptr[i] != NULL) {
4048 bus_dmamap_unload(sc->tx_mbuf_tag, sc->tx_mbuf_map[i]);
4049 m_freem(sc->tx_mbuf_ptr[i]);
4050 sc->tx_mbuf_ptr[i] = NULL;
4051 DBRUNIF(1, sc->tx_mbuf_alloc--);
4055 /* Clear each TX chain page. */
4056 for (i = 0; i < sc->tx_pages; i++)
4057 bzero(sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
4060 /* Check if we lost any mbufs in the process. */
4061 DBRUNIF((sc->tx_mbuf_alloc),
4062 if_printf(&sc->arpcom.ac_if,
4063 "%s(%d): Memory leak! "
4064 "Lost %d mbufs from tx chain!\n",
4065 __FILE__, __LINE__, sc->tx_mbuf_alloc));
4067 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
4071 /****************************************************************************/
4072 /* Initialize the RX context memory. */
4076 /****************************************************************************/
4078 bce_init_rx_context(struct bce_softc *sc)
4082 /* Initialize the context ID for an L2 RX chain. */
4083 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
4084 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
4087 * Set the level for generating pause frames
4088 * when the number of available rx_bd's gets
4089 * too low (the low watermark) and the level
4090 * when pause frames can be stopped (the high
4093 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4094 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4095 uint32_t lo_water, hi_water;
4097 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
4098 hi_water = USABLE_RX_BD(sc) / 4;
4100 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
4101 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
4105 else if (hi_water == 0)
4108 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
4111 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
4113 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
4114 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4115 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4116 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
4117 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
4120 /* Point the hardware to the first page in the chain. */
4121 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
4122 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
4123 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
4124 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
4128 /****************************************************************************/
4129 /* Allocate memory and initialize the RX data structures. */
4132 /* 0 for success, positive value for failure. */
4133 /****************************************************************************/
4135 bce_init_rx_chain(struct bce_softc *sc)
4139 uint16_t prod, chain_prod;
4142 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4144 /* Initialize the RX producer and consumer indices. */
4147 sc->rx_prod_bseq = 0;
4148 sc->free_rx_bd = USABLE_RX_BD(sc);
4149 sc->max_rx_bd = USABLE_RX_BD(sc);
4150 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD(sc));
4151 DBRUNIF(1, sc->rx_empty_count = 0);
4153 /* Initialize the RX next pointer chain entries. */
4154 for (i = 0; i < sc->rx_pages; i++) {
4157 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
4159 /* Check if we've reached the last page. */
4160 if (i == (sc->rx_pages - 1))
4165 /* Setup the chain page pointers. */
4166 rxbd->rx_bd_haddr_hi =
4167 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
4168 rxbd->rx_bd_haddr_lo =
4169 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
4172 /* Allocate mbuf clusters for the rx_bd chain. */
4173 prod = prod_bseq = 0;
4174 while (prod < TOTAL_RX_BD(sc)) {
4175 chain_prod = RX_CHAIN_IDX(sc, prod);
4176 if (bce_newbuf_std(sc, &prod, &chain_prod, &prod_bseq, 1)) {
4177 if_printf(&sc->arpcom.ac_if,
4178 "Error filling RX chain: rx_bd[0x%04X]!\n",
4183 prod = NEXT_RX_BD(prod);
4186 /* Save the RX chain producer index. */
4188 sc->rx_prod_bseq = prod_bseq;
4190 /* Tell the chip about the waiting rx_bd's. */
4191 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4193 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4196 bce_init_rx_context(sc);
4202 /****************************************************************************/
4203 /* Free memory and clear the RX data structures. */
4207 /****************************************************************************/
4209 bce_free_rx_chain(struct bce_softc *sc)
4213 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4215 /* Free any mbufs still in the RX mbuf chain. */
4216 for (i = 0; i < TOTAL_RX_BD(sc); i++) {
4217 if (sc->rx_mbuf_ptr[i] != NULL) {
4218 bus_dmamap_unload(sc->rx_mbuf_tag, sc->rx_mbuf_map[i]);
4219 m_freem(sc->rx_mbuf_ptr[i]);
4220 sc->rx_mbuf_ptr[i] = NULL;
4221 DBRUNIF(1, sc->rx_mbuf_alloc--);
4225 /* Clear each RX chain page. */
4226 for (i = 0; i < sc->rx_pages; i++)
4227 bzero(sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
4229 /* Check if we lost any mbufs in the process. */
4230 DBRUNIF((sc->rx_mbuf_alloc),
4231 if_printf(&sc->arpcom.ac_if,
4232 "%s(%d): Memory leak! "
4233 "Lost %d mbufs from rx chain!\n",
4234 __FILE__, __LINE__, sc->rx_mbuf_alloc));
4236 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
4240 /****************************************************************************/
4241 /* Set media options. */
4244 /* 0 for success, positive value for failure. */
4245 /****************************************************************************/
4247 bce_ifmedia_upd(struct ifnet *ifp)
4249 struct bce_softc *sc = ifp->if_softc;
4250 struct mii_data *mii = device_get_softc(sc->bce_miibus);
4254 * 'mii' will be NULL, when this function is called on following
4255 * code path: bce_attach() -> bce_mgmt_init()
4258 /* Make sure the MII bus has been enumerated. */
4260 if (mii->mii_instance) {
4261 struct mii_softc *miisc;
4263 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4264 mii_phy_reset(miisc);
4266 error = mii_mediachg(mii);
4272 /****************************************************************************/
4273 /* Reports current media status. */
4277 /****************************************************************************/
4279 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4281 struct bce_softc *sc = ifp->if_softc;
4282 struct mii_data *mii = device_get_softc(sc->bce_miibus);
4285 ifmr->ifm_active = mii->mii_media_active;
4286 ifmr->ifm_status = mii->mii_media_status;
4290 /****************************************************************************/
4291 /* Handles PHY generated interrupt events. */
4295 /****************************************************************************/
4297 bce_phy_intr(struct bce_softc *sc)
4299 uint32_t new_link_state, old_link_state;
4300 struct ifnet *ifp = &sc->arpcom.ac_if;
4302 ASSERT_SERIALIZED(ifp->if_serializer);
4304 new_link_state = sc->status_block->status_attn_bits &
4305 STATUS_ATTN_BITS_LINK_STATE;
4306 old_link_state = sc->status_block->status_attn_bits_ack &
4307 STATUS_ATTN_BITS_LINK_STATE;
4309 /* Handle any changes if the link state has changed. */
4310 if (new_link_state != old_link_state) { /* XXX redundant? */
4311 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
4313 /* Update the status_attn_bits_ack field in the status block. */
4314 if (new_link_state) {
4315 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
4316 STATUS_ATTN_BITS_LINK_STATE);
4318 if_printf(ifp, "Link is now UP.\n");
4320 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
4321 STATUS_ATTN_BITS_LINK_STATE);
4323 if_printf(ifp, "Link is now DOWN.\n");
4327 * Assume link is down and allow tick routine to
4328 * update the state based on the actual media state.
4331 callout_stop(&sc->bce_tick_callout);
4332 bce_tick_serialized(sc);
4335 /* Acknowledge the link change interrupt. */
4336 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
4340 /****************************************************************************/
4341 /* Reads the receive consumer value from the status block (skipping over */
4342 /* chain page pointer if necessary). */
4346 /****************************************************************************/
4347 static __inline uint16_t
4348 bce_get_hw_rx_cons(struct bce_softc *sc)
4350 uint16_t hw_cons = sc->status_block->status_rx_quick_consumer_index0;
4352 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
4358 /****************************************************************************/
4359 /* Handles received frame interrupt events. */
4363 /****************************************************************************/
4365 bce_rx_intr(struct bce_softc *sc, int count)
4367 struct ifnet *ifp = &sc->arpcom.ac_if;
4368 uint16_t hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
4369 uint32_t sw_prod_bseq;
4371 ASSERT_SERIALIZED(ifp->if_serializer);
4373 DBRUNIF(1, sc->rx_interrupts++);
4375 /* Get the hardware's view of the RX consumer index. */
4376 hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4378 /* Get working copies of the driver's view of the RX indices. */
4379 sw_cons = sc->rx_cons;
4380 sw_prod = sc->rx_prod;
4381 sw_prod_bseq = sc->rx_prod_bseq;
4383 DBPRINT(sc, BCE_INFO_RECV, "%s(enter): sw_prod = 0x%04X, "
4384 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n",
4385 __func__, sw_prod, sw_cons, sw_prod_bseq);
4387 /* Prevent speculative reads from getting ahead of the status block. */
4388 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4389 BUS_SPACE_BARRIER_READ);
4391 /* Update some debug statistics counters */
4392 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
4393 sc->rx_low_watermark = sc->free_rx_bd);
4394 DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
4396 /* Scan through the receive chain as long as there is work to do. */
4397 while (sw_cons != hw_cons) {
4398 struct mbuf *m = NULL;
4399 struct l2_fhdr *l2fhdr = NULL;
4402 uint32_t status = 0;
4404 #ifdef DEVICE_POLLING
4405 if (count >= 0 && count-- == 0) {
4406 sc->hw_rx_cons = sw_cons;
4412 * Convert the producer/consumer indices
4413 * to an actual rx_bd index.
4415 sw_chain_cons = RX_CHAIN_IDX(sc, sw_cons);
4416 sw_chain_prod = RX_CHAIN_IDX(sc, sw_prod);
4418 /* Get the used rx_bd. */
4419 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)]
4420 [RX_IDX(sw_chain_cons)];
4423 DBRUN(BCE_VERBOSE_RECV,
4424 if_printf(ifp, "%s(): ", __func__);
4425 bce_dump_rxbd(sc, sw_chain_cons, rxbd));
4427 /* The mbuf is stored with the last rx_bd entry of a packet. */
4428 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) {
4429 /* Validate that this is the last rx_bd. */
4430 DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)),
4431 if_printf(ifp, "%s(%d): "
4432 "Unexpected mbuf found in rx_bd[0x%04X]!\n",
4433 __FILE__, __LINE__, sw_chain_cons);
4434 bce_breakpoint(sc));
4436 if (sw_chain_cons != sw_chain_prod) {
4437 if_printf(ifp, "RX cons(%d) != prod(%d), "
4438 "drop!\n", sw_chain_cons,
4442 bce_setup_rxdesc_std(sc, sw_chain_cons,
4445 goto bce_rx_int_next_rx;
4448 /* Unmap the mbuf from DMA space. */
4449 bus_dmamap_sync(sc->rx_mbuf_tag,
4450 sc->rx_mbuf_map[sw_chain_cons],
4451 BUS_DMASYNC_POSTREAD);
4453 /* Save the mbuf from the driver's chain. */
4454 m = sc->rx_mbuf_ptr[sw_chain_cons];
4457 * Frames received on the NetXteme II are prepended
4458 * with an l2_fhdr structure which provides status
4459 * information about the received frame (including
4460 * VLAN tags and checksum info). The frames are also
4461 * automatically adjusted to align the IP header
4462 * (i.e. two null bytes are inserted before the
4463 * Ethernet header). As a result the data DMA'd by
4464 * the controller into the mbuf is as follows:
4466 * +---------+-----+---------------------+-----+
4467 * | l2_fhdr | pad | packet data | FCS |
4468 * +---------+-----+---------------------+-----+
4470 * The l2_fhdr needs to be checked and skipped and the
4471 * FCS needs to be stripped before sending the packet
4474 l2fhdr = mtod(m, struct l2_fhdr *);
4476 len = l2fhdr->l2_fhdr_pkt_len;
4477 status = l2fhdr->l2_fhdr_status;
4479 DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check),
4481 "Simulating l2_fhdr status error.\n");
4482 status = status | L2_FHDR_ERRORS_PHY_DECODE);
4484 /* Watch for unusual sized frames. */
4485 DBRUNIF((len < BCE_MIN_MTU ||
4486 len > BCE_MAX_JUMBO_ETHER_MTU_VLAN),
4488 "%s(%d): Unusual frame size found. "
4489 "Min(%d), Actual(%d), Max(%d)\n",
4491 (int)BCE_MIN_MTU, len,
4492 (int)BCE_MAX_JUMBO_ETHER_MTU_VLAN);
4493 bce_dump_mbuf(sc, m);
4494 bce_breakpoint(sc));
4496 len -= ETHER_CRC_LEN;
4498 /* Check the received frame for errors. */
4499 if (status & (L2_FHDR_ERRORS_BAD_CRC |
4500 L2_FHDR_ERRORS_PHY_DECODE |
4501 L2_FHDR_ERRORS_ALIGNMENT |
4502 L2_FHDR_ERRORS_TOO_SHORT |
4503 L2_FHDR_ERRORS_GIANT_FRAME)) {
4505 DBRUNIF(1, sc->l2fhdr_status_errors++);
4507 /* Reuse the mbuf for a new frame. */
4508 bce_setup_rxdesc_std(sc, sw_chain_prod,
4511 goto bce_rx_int_next_rx;
4515 * Get a new mbuf for the rx_bd. If no new
4516 * mbufs are available then reuse the current mbuf,
4517 * log an ierror on the interface, and generate
4518 * an error in the system log.
4520 if (bce_newbuf_std(sc, &sw_prod, &sw_chain_prod,
4521 &sw_prod_bseq, 0)) {
4524 "%s(%d): Failed to allocate new mbuf, "
4525 "incoming frame dropped!\n",
4526 __FILE__, __LINE__));
4530 /* Try and reuse the exisitng mbuf. */
4531 bce_setup_rxdesc_std(sc, sw_chain_prod,
4534 goto bce_rx_int_next_rx;
4538 * Skip over the l2_fhdr when passing
4539 * the data up the stack.
4541 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN);
4543 m->m_pkthdr.len = m->m_len = len;
4544 m->m_pkthdr.rcvif = ifp;
4546 DBRUN(BCE_VERBOSE_RECV,
4547 struct ether_header *eh;
4548 eh = mtod(m, struct ether_header *);
4549 if_printf(ifp, "%s(): to: %6D, from: %6D, "
4550 "type: 0x%04X\n", __func__,
4551 eh->ether_dhost, ":",
4552 eh->ether_shost, ":",
4553 htons(eh->ether_type)));
4555 /* Validate the checksum if offload enabled. */
4556 if (ifp->if_capenable & IFCAP_RXCSUM) {
4557 /* Check for an IP datagram. */
4558 if (status & L2_FHDR_STATUS_IP_DATAGRAM) {
4559 m->m_pkthdr.csum_flags |=
4562 /* Check if the IP checksum is valid. */
4563 if ((l2fhdr->l2_fhdr_ip_xsum ^
4565 m->m_pkthdr.csum_flags |=
4568 DBPRINT(sc, BCE_WARN_RECV,
4569 "%s(): Invalid IP checksum = 0x%04X!\n",
4570 __func__, l2fhdr->l2_fhdr_ip_xsum);
4574 /* Check for a valid TCP/UDP frame. */
4575 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
4576 L2_FHDR_STATUS_UDP_DATAGRAM)) {
4578 /* Check for a good TCP/UDP checksum. */
4580 (L2_FHDR_ERRORS_TCP_XSUM |
4581 L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
4582 m->m_pkthdr.csum_data =
4583 l2fhdr->l2_fhdr_tcp_udp_xsum;
4584 m->m_pkthdr.csum_flags |=
4588 DBPRINT(sc, BCE_WARN_RECV,
4589 "%s(): Invalid TCP/UDP checksum = 0x%04X!\n",
4590 __func__, l2fhdr->l2_fhdr_tcp_udp_xsum);
4597 sw_prod = NEXT_RX_BD(sw_prod);
4600 sw_cons = NEXT_RX_BD(sw_cons);
4602 /* If we have a packet, pass it up the stack */
4604 DBPRINT(sc, BCE_VERBOSE_RECV,
4605 "%s(): Passing received frame up.\n", __func__);
4607 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
4608 m->m_flags |= M_VLANTAG;
4609 m->m_pkthdr.ether_vlantag =
4610 l2fhdr->l2_fhdr_vlan_tag;
4612 ifp->if_input(ifp, m);
4614 DBRUNIF(1, sc->rx_mbuf_alloc--);
4618 * If polling(4) is not enabled, refresh hw_cons to see
4619 * whether there's new work.
4621 * If polling(4) is enabled, i.e count >= 0, refreshing
4622 * should not be performed, so that we would not spend
4623 * too much time in RX processing.
4625 if (count < 0 && sw_cons == hw_cons)
4626 hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4629 * Prevent speculative reads from getting ahead
4630 * of the status block.
4632 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4633 BUS_SPACE_BARRIER_READ);
4636 sc->rx_cons = sw_cons;
4637 sc->rx_prod = sw_prod;
4638 sc->rx_prod_bseq = sw_prod_bseq;
4640 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4642 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4645 DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, "
4646 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
4647 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
4651 /****************************************************************************/
4652 /* Reads the transmit consumer value from the status block (skipping over */
4653 /* chain page pointer if necessary). */
4657 /****************************************************************************/
4658 static __inline uint16_t
4659 bce_get_hw_tx_cons(struct bce_softc *sc)
4661 uint16_t hw_cons = sc->status_block->status_tx_quick_consumer_index0;
4663 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4669 /****************************************************************************/
4670 /* Handles transmit completion interrupt events. */
4674 /****************************************************************************/
4676 bce_tx_intr(struct bce_softc *sc)
4678 struct ifnet *ifp = &sc->arpcom.ac_if;
4679 uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
4681 ASSERT_SERIALIZED(ifp->if_serializer);
4683 DBRUNIF(1, sc->tx_interrupts++);
4685 /* Get the hardware's view of the TX consumer index. */
4686 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4687 sw_tx_cons = sc->tx_cons;
4689 /* Prevent speculative reads from getting ahead of the status block. */
4690 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4691 BUS_SPACE_BARRIER_READ);
4693 /* Cycle through any completed TX chain page entries. */
4694 while (sw_tx_cons != hw_tx_cons) {
4696 struct tx_bd *txbd = NULL;
4698 sw_tx_chain_cons = TX_CHAIN_IDX(sc, sw_tx_cons);
4700 DBPRINT(sc, BCE_INFO_SEND,
4701 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
4702 "sw_tx_chain_cons = 0x%04X\n",
4703 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
4705 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD(sc)),
4706 if_printf(ifp, "%s(%d): "
4707 "TX chain consumer out of range! "
4708 " 0x%04X > 0x%04X\n",
4709 __FILE__, __LINE__, sw_tx_chain_cons,
4710 (int)MAX_TX_BD(sc));
4711 bce_breakpoint(sc));
4713 DBRUNIF(1, txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
4714 [TX_IDX(sw_tx_chain_cons)]);
4716 DBRUNIF((txbd == NULL),
4717 if_printf(ifp, "%s(%d): "
4718 "Unexpected NULL tx_bd[0x%04X]!\n",
4719 __FILE__, __LINE__, sw_tx_chain_cons);
4720 bce_breakpoint(sc));
4722 DBRUN(BCE_INFO_SEND,
4723 if_printf(ifp, "%s(): ", __func__);
4724 bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
4727 * Free the associated mbuf. Remember
4728 * that only the last tx_bd of a packet
4729 * has an mbuf pointer and DMA map.
4731 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
4732 /* Validate that this is the last tx_bd. */
4733 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
4734 if_printf(ifp, "%s(%d): "
4735 "tx_bd END flag not set but "
4736 "txmbuf == NULL!\n", __FILE__, __LINE__);
4737 bce_breakpoint(sc));
4739 DBRUN(BCE_INFO_SEND,
4740 if_printf(ifp, "%s(): Unloading map/freeing mbuf "
4741 "from tx_bd[0x%04X]\n", __func__,
4744 /* Unmap the mbuf. */
4745 bus_dmamap_unload(sc->tx_mbuf_tag,
4746 sc->tx_mbuf_map[sw_tx_chain_cons]);
4748 /* Free the mbuf. */
4749 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
4750 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
4751 DBRUNIF(1, sc->tx_mbuf_alloc--);
4757 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4759 if (sw_tx_cons == hw_tx_cons) {
4760 /* Refresh hw_cons to see if there's new work. */
4761 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4765 * Prevent speculative reads from getting
4766 * ahead of the status block.
4768 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4769 BUS_SPACE_BARRIER_READ);
4772 if (sc->used_tx_bd == 0) {
4773 /* Clear the TX timeout timer. */
4777 /* Clear the tx hardware queue full flag. */
4778 if (sc->max_tx_bd - sc->used_tx_bd >= BCE_TX_SPARE_SPACE) {
4779 DBRUNIF((ifp->if_flags & IFF_OACTIVE),
4780 DBPRINT(sc, BCE_WARN_SEND,
4781 "%s(): Open TX chain! %d/%d (used/total)\n",
4782 __func__, sc->used_tx_bd, sc->max_tx_bd));
4783 ifp->if_flags &= ~IFF_OACTIVE;
4785 sc->tx_cons = sw_tx_cons;
4789 /****************************************************************************/
4790 /* Disables interrupt generation. */
4794 /****************************************************************************/
4796 bce_disable_intr(struct bce_softc *sc)
4798 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4799 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
4800 lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
4804 /****************************************************************************/
4805 /* Enables interrupt generation. */
4809 /****************************************************************************/
4811 bce_enable_intr(struct bce_softc *sc, int coal_now)
4813 lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
4815 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4816 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4817 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4819 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4820 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4823 REG_WR(sc, BCE_HC_COMMAND,
4824 sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
4829 /****************************************************************************/
4830 /* Handles controller initialization. */
4834 /****************************************************************************/
4838 struct bce_softc *sc = xsc;
4839 struct ifnet *ifp = &sc->arpcom.ac_if;
4843 ASSERT_SERIALIZED(ifp->if_serializer);
4845 /* Check if the driver is still running and bail out if it is. */
4846 if (ifp->if_flags & IFF_RUNNING)
4851 error = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4853 if_printf(ifp, "Controller reset failed!\n");
4857 error = bce_chipinit(sc);
4859 if_printf(ifp, "Controller initialization failed!\n");
4863 error = bce_blockinit(sc);
4865 if_printf(ifp, "Block initialization failed!\n");
4869 /* Load our MAC address. */
4870 bcopy(IF_LLADDR(ifp), sc->eaddr, ETHER_ADDR_LEN);
4871 bce_set_mac_addr(sc);
4873 /* Calculate and program the Ethernet MTU size. */
4874 ether_mtu = ETHER_HDR_LEN + EVL_ENCAPLEN + ifp->if_mtu + ETHER_CRC_LEN;
4876 DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n", __func__, ether_mtu);
4879 * Program the mtu, enabling jumbo frame
4880 * support if necessary. Also set the mbuf
4881 * allocation count for RX frames.
4883 if (ether_mtu > ETHER_MAX_LEN + EVL_ENCAPLEN) {
4885 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
4886 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
4887 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
4888 sc->mbuf_alloc_size = MJUM9BYTES;
4890 panic("jumbo buffer is not supported yet");
4893 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
4894 sc->mbuf_alloc_size = MCLBYTES;
4897 /* Calculate the RX Ethernet frame size for rx_bd's. */
4898 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8;
4900 DBPRINT(sc, BCE_INFO,
4901 "%s(): mclbytes = %d, mbuf_alloc_size = %d, "
4902 "max_frame_size = %d\n",
4903 __func__, (int)MCLBYTES, sc->mbuf_alloc_size,
4904 sc->max_frame_size);
4906 /* Program appropriate promiscuous/multicast filtering. */
4907 bce_set_rx_mode(sc);
4909 /* Init RX buffer descriptor chain. */
4910 bce_init_rx_chain(sc); /* XXX return value */
4912 /* Init TX buffer descriptor chain. */
4913 bce_init_tx_chain(sc); /* XXX return value */
4915 #ifdef DEVICE_POLLING
4916 /* Disable interrupts if we are polling. */
4917 if (ifp->if_flags & IFF_POLLING) {
4918 bce_disable_intr(sc);
4920 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4921 (1 << 16) | sc->bce_rx_quick_cons_trip);
4922 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4923 (1 << 16) | sc->bce_tx_quick_cons_trip);
4926 /* Enable host interrupts. */
4927 bce_enable_intr(sc, 1);
4929 bce_ifmedia_upd(ifp);
4931 ifp->if_flags |= IFF_RUNNING;
4932 ifp->if_flags &= ~IFF_OACTIVE;
4934 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
4941 /****************************************************************************/
4942 /* Initialize the controller just enough so that any management firmware */
4943 /* running on the device will continue to operate corectly. */
4947 /****************************************************************************/
4949 bce_mgmt_init(struct bce_softc *sc)
4951 struct ifnet *ifp = &sc->arpcom.ac_if;
4953 /* Bail out if management firmware is not running. */
4954 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
4957 /* Enable all critical blocks in the MAC. */
4958 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4959 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4960 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4961 BCE_MISC_ENABLE_DEFAULT_XI);
4963 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
4965 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4968 bce_ifmedia_upd(ifp);
4972 /****************************************************************************/
4973 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
4974 /* memory visible to the controller. */
4977 /* 0 for success, positive value for failure. */
4978 /****************************************************************************/
4980 bce_encap(struct bce_softc *sc, struct mbuf **m_head)
4982 bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4983 bus_dmamap_t map, tmp_map;
4984 struct mbuf *m0 = *m_head;
4985 struct tx_bd *txbd = NULL;
4986 uint16_t vlan_tag = 0, flags = 0;
4987 uint16_t chain_prod, chain_prod_start, prod;
4989 int i, error, maxsegs, nsegs;
4991 uint16_t debug_prod;
4994 /* Transfer any checksum offload flags to the bd. */
4995 if (m0->m_pkthdr.csum_flags) {
4996 if (m0->m_pkthdr.csum_flags & CSUM_IP)
4997 flags |= TX_BD_FLAGS_IP_CKSUM;
4998 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
4999 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
5002 /* Transfer any VLAN tags to the bd. */
5003 if (m0->m_flags & M_VLANTAG) {
5004 flags |= TX_BD_FLAGS_VLAN_TAG;
5005 vlan_tag = m0->m_pkthdr.ether_vlantag;
5009 chain_prod_start = chain_prod = TX_CHAIN_IDX(sc, prod);
5011 /* Map the mbuf into DMAable memory. */
5012 map = sc->tx_mbuf_map[chain_prod_start];
5014 maxsegs = sc->max_tx_bd - sc->used_tx_bd;
5015 KASSERT(maxsegs >= BCE_TX_SPARE_SPACE,
5016 ("not enough segments %d", maxsegs));
5017 if (maxsegs > BCE_MAX_SEGMENTS)
5018 maxsegs = BCE_MAX_SEGMENTS;
5020 /* Map the mbuf into our DMA address space. */
5021 error = bus_dmamap_load_mbuf_defrag(sc->tx_mbuf_tag, map, m_head,
5022 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
5025 bus_dmamap_sync(sc->tx_mbuf_tag, map, BUS_DMASYNC_PREWRITE);
5030 /* prod points to an empty tx_bd at this point. */
5031 prod_bseq = sc->tx_prod_bseq;
5034 debug_prod = chain_prod;
5037 DBPRINT(sc, BCE_INFO_SEND,
5038 "%s(): Start: prod = 0x%04X, chain_prod = %04X, "
5039 "prod_bseq = 0x%08X\n",
5040 __func__, prod, chain_prod, prod_bseq);
5043 * Cycle through each mbuf segment that makes up
5044 * the outgoing frame, gathering the mapping info
5045 * for that segment and creating a tx_bd to for
5048 for (i = 0; i < nsegs; i++) {
5049 chain_prod = TX_CHAIN_IDX(sc, prod);
5050 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
5052 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr));
5053 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr));
5054 txbd->tx_bd_mss_nbytes = htole16(segs[i].ds_len);
5055 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
5056 txbd->tx_bd_flags = htole16(flags);
5057 prod_bseq += segs[i].ds_len;
5059 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
5060 prod = NEXT_TX_BD(prod);
5063 /* Set the END flag on the last TX buffer descriptor. */
5064 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
5066 DBRUN(BCE_EXCESSIVE_SEND,
5067 bce_dump_tx_chain(sc, debug_prod, nsegs));
5069 DBPRINT(sc, BCE_INFO_SEND,
5070 "%s(): End: prod = 0x%04X, chain_prod = %04X, "
5071 "prod_bseq = 0x%08X\n",
5072 __func__, prod, chain_prod, prod_bseq);
5075 * Ensure that the mbuf pointer for this transmission
5076 * is placed at the array index of the last
5077 * descriptor in this chain. This is done
5078 * because a single map is used for all
5079 * segments of the mbuf and we don't want to
5080 * unload the map before all of the segments
5083 sc->tx_mbuf_ptr[chain_prod] = m0;
5085 tmp_map = sc->tx_mbuf_map[chain_prod];
5086 sc->tx_mbuf_map[chain_prod] = map;
5087 sc->tx_mbuf_map[chain_prod_start] = tmp_map;
5089 sc->used_tx_bd += nsegs;
5091 /* Update some debug statistic counters */
5092 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
5093 sc->tx_hi_watermark = sc->used_tx_bd);
5094 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
5095 DBRUNIF(1, sc->tx_mbuf_alloc++);
5097 DBRUN(BCE_VERBOSE_SEND,
5098 bce_dump_tx_mbuf_chain(sc, chain_prod, nsegs));
5100 /* prod points to the next free tx_bd at this point. */
5102 sc->tx_prod_bseq = prod_bseq;
5112 /****************************************************************************/
5113 /* Main transmit routine when called from another routine with a lock. */
5117 /****************************************************************************/
5119 bce_start(struct ifnet *ifp)
5121 struct bce_softc *sc = ifp->if_softc;
5124 ASSERT_SERIALIZED(ifp->if_serializer);
5126 /* If there's no link or the transmit queue is empty then just exit. */
5127 if (!sc->bce_link) {
5128 ifq_purge(&ifp->if_snd);
5132 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
5135 DBPRINT(sc, BCE_INFO_SEND,
5136 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04zX, "
5137 "tx_prod_bseq = 0x%08X\n",
5139 sc->tx_prod, TX_CHAIN_IDX(sc, sc->tx_prod), sc->tx_prod_bseq);
5142 struct mbuf *m_head;
5145 * We keep BCE_TX_SPARE_SPACE entries, so bce_encap() is
5148 if (sc->max_tx_bd - sc->used_tx_bd < BCE_TX_SPARE_SPACE) {
5149 ifp->if_flags |= IFF_OACTIVE;
5153 /* Check for any frames to send. */
5154 m_head = ifq_dequeue(&ifp->if_snd, NULL);
5159 * Pack the data into the transmit ring. If we
5160 * don't have room, place the mbuf back at the
5161 * head of the queue and set the OACTIVE flag
5162 * to wait for the NIC to drain the chain.
5164 if (bce_encap(sc, &m_head)) {
5166 if (sc->used_tx_bd == 0) {
5169 ifp->if_flags |= IFF_OACTIVE;
5176 /* Send a copy of the frame to any BPF listeners. */
5177 ETHER_BPF_MTAP(ifp, m_head);
5181 /* no packets were dequeued */
5182 DBPRINT(sc, BCE_VERBOSE_SEND,
5183 "%s(): No packets were dequeued\n", __func__);
5187 DBPRINT(sc, BCE_INFO_SEND,
5188 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04zX, "
5189 "tx_prod_bseq = 0x%08X\n",
5191 sc->tx_prod, TX_CHAIN_IDX(sc, sc->tx_prod), sc->tx_prod_bseq);
5193 REG_WR(sc, BCE_MQ_COMMAND,
5194 REG_RD(sc, BCE_MQ_COMMAND) | BCE_MQ_COMMAND_NO_MAP_ERROR);
5196 /* Start the transmit. */
5197 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
5198 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
5200 /* Set the tx timeout. */
5201 ifp->if_timer = BCE_TX_TIMEOUT;
5205 /****************************************************************************/
5206 /* Handles any IOCTL calls from the operating system. */
5209 /* 0 for success, positive value for failure. */
5210 /****************************************************************************/
5212 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
5214 struct bce_softc *sc = ifp->if_softc;
5215 struct ifreq *ifr = (struct ifreq *)data;
5216 struct mii_data *mii;
5217 int mask, error = 0;
5219 ASSERT_SERIALIZED(ifp->if_serializer);
5223 /* Check that the MTU setting is supported. */
5224 if (ifr->ifr_mtu < BCE_MIN_MTU ||
5226 ifr->ifr_mtu > BCE_MAX_JUMBO_MTU
5228 ifr->ifr_mtu > ETHERMTU
5235 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu);
5237 ifp->if_mtu = ifr->ifr_mtu;
5238 ifp->if_flags &= ~IFF_RUNNING; /* Force reinitialize */
5243 if (ifp->if_flags & IFF_UP) {
5244 if (ifp->if_flags & IFF_RUNNING) {
5245 mask = ifp->if_flags ^ sc->bce_if_flags;
5247 if (mask & (IFF_PROMISC | IFF_ALLMULTI))
5248 bce_set_rx_mode(sc);
5252 } else if (ifp->if_flags & IFF_RUNNING) {
5255 /* If MFW is running, restart the controller a bit. */
5256 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5257 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
5262 sc->bce_if_flags = ifp->if_flags;
5267 if (ifp->if_flags & IFF_RUNNING)
5268 bce_set_rx_mode(sc);
5273 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n",
5275 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n");
5277 mii = device_get_softc(sc->bce_miibus);
5278 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
5282 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5283 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n",
5286 if (mask & IFCAP_HWCSUM) {
5287 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
5288 if (IFCAP_HWCSUM & ifp->if_capenable)
5289 ifp->if_hwassist = BCE_IF_HWASSIST;
5291 ifp->if_hwassist = 0;
5296 error = ether_ioctl(ifp, command, data);
5303 /****************************************************************************/
5304 /* Transmit timeout handler. */
5308 /****************************************************************************/
5310 bce_watchdog(struct ifnet *ifp)
5312 struct bce_softc *sc = ifp->if_softc;
5314 ASSERT_SERIALIZED(ifp->if_serializer);
5316 DBRUN(BCE_VERBOSE_SEND,
5317 bce_dump_driver_state(sc);
5318 bce_dump_status_block(sc));
5321 * If we are in this routine because of pause frames, then
5322 * don't reset the hardware.
5324 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
5327 if_printf(ifp, "Watchdog timeout occurred, resetting!\n");
5329 /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */
5331 ifp->if_flags &= ~IFF_RUNNING; /* Force reinitialize */
5336 if (!ifq_is_empty(&ifp->if_snd))
5341 #ifdef DEVICE_POLLING
5344 bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
5346 struct bce_softc *sc = ifp->if_softc;
5347 struct status_block *sblk = sc->status_block;
5348 uint16_t hw_tx_cons, hw_rx_cons;
5350 ASSERT_SERIALIZED(ifp->if_serializer);
5354 bce_disable_intr(sc);
5356 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5357 (1 << 16) | sc->bce_rx_quick_cons_trip);
5358 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5359 (1 << 16) | sc->bce_tx_quick_cons_trip);
5361 case POLL_DEREGISTER:
5362 bce_enable_intr(sc, 1);
5364 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5365 (sc->bce_tx_quick_cons_trip_int << 16) |
5366 sc->bce_tx_quick_cons_trip);
5367 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5368 (sc->bce_rx_quick_cons_trip_int << 16) |
5369 sc->bce_rx_quick_cons_trip);
5375 if (cmd == POLL_AND_CHECK_STATUS) {
5376 uint32_t status_attn_bits;
5378 status_attn_bits = sblk->status_attn_bits;
5380 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5382 "Simulating unexpected status attention bit set.");
5383 status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5385 /* Was it a link change interrupt? */
5386 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5387 (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
5390 /* Clear any transient status updates during link state change. */
5391 REG_WR(sc, BCE_HC_COMMAND,
5392 sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5393 REG_RD(sc, BCE_HC_COMMAND);
5396 * If any other attention is asserted then
5397 * the chip is toast.
5399 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5400 (sblk->status_attn_bits_ack &
5401 ~STATUS_ATTN_BITS_LINK_STATE)) {
5402 DBRUN(1, sc->unexpected_attentions++);
5404 if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5405 sblk->status_attn_bits);
5408 if (bce_debug_unexpected_attention == 0)
5409 bce_breakpoint(sc));
5416 hw_rx_cons = bce_get_hw_rx_cons(sc);
5417 hw_tx_cons = bce_get_hw_tx_cons(sc);
5419 /* Check for any completed RX frames. */
5420 if (hw_rx_cons != sc->hw_rx_cons)
5421 bce_rx_intr(sc, count);
5423 /* Check for any completed TX frames. */
5424 if (hw_tx_cons != sc->hw_tx_cons)
5427 /* Check for new frames to transmit. */
5428 if (!ifq_is_empty(&ifp->if_snd))
5432 #endif /* DEVICE_POLLING */
5436 * Interrupt handler.
5438 /****************************************************************************/
5439 /* Main interrupt entry point. Verifies that the controller generated the */
5440 /* interrupt and then calls a separate routine for handle the various */
5441 /* interrupt causes (PHY, TX, RX). */
5444 /* 0 for success, positive value for failure. */
5445 /****************************************************************************/
5447 bce_intr(struct bce_softc *sc)
5449 struct ifnet *ifp = &sc->arpcom.ac_if;
5450 struct status_block *sblk;
5451 uint16_t hw_rx_cons, hw_tx_cons;
5453 ASSERT_SERIALIZED(ifp->if_serializer);
5455 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5456 DBRUNIF(1, sc->interrupts_generated++);
5458 sblk = sc->status_block;
5460 /* Check if the hardware has finished any work. */
5461 hw_rx_cons = bce_get_hw_rx_cons(sc);
5462 hw_tx_cons = bce_get_hw_tx_cons(sc);
5464 /* Keep processing data as long as there is work to do. */
5466 uint32_t status_attn_bits;
5468 status_attn_bits = sblk->status_attn_bits;
5470 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5472 "Simulating unexpected status attention bit set.");
5473 status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5475 /* Was it a link change interrupt? */
5476 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5477 (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) {
5481 * Clear any transient status updates during link state
5484 REG_WR(sc, BCE_HC_COMMAND,
5485 sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5486 REG_RD(sc, BCE_HC_COMMAND);
5490 * If any other attention is asserted then
5491 * the chip is toast.
5493 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5494 (sblk->status_attn_bits_ack &
5495 ~STATUS_ATTN_BITS_LINK_STATE)) {
5496 DBRUN(1, sc->unexpected_attentions++);
5498 if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5499 sblk->status_attn_bits);
5502 if (bce_debug_unexpected_attention == 0)
5503 bce_breakpoint(sc));
5509 /* Check for any completed RX frames. */
5510 if (hw_rx_cons != sc->hw_rx_cons)
5511 bce_rx_intr(sc, -1);
5513 /* Check for any completed TX frames. */
5514 if (hw_tx_cons != sc->hw_tx_cons)
5518 * Save the status block index value
5519 * for use during the next interrupt.
5521 sc->last_status_idx = sblk->status_idx;
5524 * Prevent speculative reads from getting
5525 * ahead of the status block.
5527 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
5528 BUS_SPACE_BARRIER_READ);
5531 * If there's no work left then exit the
5532 * interrupt service routine.
5534 hw_rx_cons = bce_get_hw_rx_cons(sc);
5535 hw_tx_cons = bce_get_hw_tx_cons(sc);
5536 if ((hw_rx_cons == sc->hw_rx_cons) && (hw_tx_cons == sc->hw_tx_cons))
5540 /* Re-enable interrupts. */
5541 bce_enable_intr(sc, 0);
5543 if (sc->bce_coalchg_mask)
5544 bce_coal_change(sc);
5546 /* Handle any frames that arrived while handling the interrupt. */
5547 if (!ifq_is_empty(&ifp->if_snd))
5552 bce_intr_legacy(void *xsc)
5554 struct bce_softc *sc = xsc;
5555 struct status_block *sblk;
5557 sblk = sc->status_block;
5560 * If the hardware status block index matches the last value
5561 * read by the driver and we haven't asserted our interrupt
5562 * then there's nothing to do.
5564 if (sblk->status_idx == sc->last_status_idx &&
5565 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
5566 BCE_PCICFG_MISC_STATUS_INTA_VALUE))
5569 /* Ack the interrupt and stop others from occuring. */
5570 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5571 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5572 BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5575 * Read back to deassert IRQ immediately to avoid too
5576 * many spurious interrupts.
5578 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
5584 bce_intr_msi(void *xsc)
5586 struct bce_softc *sc = xsc;
5588 /* Ack the interrupt and stop others from occuring. */
5589 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5590 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5591 BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5597 bce_intr_msi_oneshot(void *xsc)
5603 /****************************************************************************/
5604 /* Programs the various packet receive modes (broadcast and multicast). */
5608 /****************************************************************************/
5610 bce_set_rx_mode(struct bce_softc *sc)
5612 struct ifnet *ifp = &sc->arpcom.ac_if;
5613 struct ifmultiaddr *ifma;
5614 uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
5615 uint32_t rx_mode, sort_mode;
5618 ASSERT_SERIALIZED(ifp->if_serializer);
5620 /* Initialize receive mode default settings. */
5621 rx_mode = sc->rx_mode &
5622 ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
5623 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
5624 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
5627 * ASF/IPMI/UMP firmware requires that VLAN tag stripping
5630 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
5631 !(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
5632 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
5635 * Check for promiscuous, all multicast, or selected
5636 * multicast address filtering.
5638 if (ifp->if_flags & IFF_PROMISC) {
5639 DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n");
5641 /* Enable promiscuous mode. */
5642 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
5643 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
5644 } else if (ifp->if_flags & IFF_ALLMULTI) {
5645 DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n");
5647 /* Enable all multicast addresses. */
5648 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5649 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5652 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
5654 /* Accept one or more multicast(s). */
5655 DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n");
5657 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5658 if (ifma->ifma_addr->sa_family != AF_LINK)
5661 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
5662 ETHER_ADDR_LEN) & 0xFF;
5663 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
5666 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5667 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5670 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
5673 /* Only make changes if the recive mode has actually changed. */
5674 if (rx_mode != sc->rx_mode) {
5675 DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n",
5678 sc->rx_mode = rx_mode;
5679 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
5682 /* Disable and clear the exisitng sort before enabling a new sort. */
5683 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
5684 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
5685 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
5689 /****************************************************************************/
5690 /* Called periodically to updates statistics from the controllers */
5691 /* statistics block. */
5695 /****************************************************************************/
5697 bce_stats_update(struct bce_softc *sc)
5699 struct ifnet *ifp = &sc->arpcom.ac_if;
5700 struct statistics_block *stats = sc->stats_block;
5702 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5704 ASSERT_SERIALIZED(ifp->if_serializer);
5707 * Certain controllers don't report carrier sense errors correctly.
5708 * See errata E11_5708CA0_1165.
5710 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5711 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) {
5713 (u_long)stats->stat_Dot3StatsCarrierSenseErrors;
5717 * Update the sysctl statistics from the hardware statistics.
5719 sc->stat_IfHCInOctets =
5720 ((uint64_t)stats->stat_IfHCInOctets_hi << 32) +
5721 (uint64_t)stats->stat_IfHCInOctets_lo;
5723 sc->stat_IfHCInBadOctets =
5724 ((uint64_t)stats->stat_IfHCInBadOctets_hi << 32) +
5725 (uint64_t)stats->stat_IfHCInBadOctets_lo;
5727 sc->stat_IfHCOutOctets =
5728 ((uint64_t)stats->stat_IfHCOutOctets_hi << 32) +
5729 (uint64_t)stats->stat_IfHCOutOctets_lo;
5731 sc->stat_IfHCOutBadOctets =
5732 ((uint64_t)stats->stat_IfHCOutBadOctets_hi << 32) +
5733 (uint64_t)stats->stat_IfHCOutBadOctets_lo;
5735 sc->stat_IfHCInUcastPkts =
5736 ((uint64_t)stats->stat_IfHCInUcastPkts_hi << 32) +
5737 (uint64_t)stats->stat_IfHCInUcastPkts_lo;
5739 sc->stat_IfHCInMulticastPkts =
5740 ((uint64_t)stats->stat_IfHCInMulticastPkts_hi << 32) +
5741 (uint64_t)stats->stat_IfHCInMulticastPkts_lo;
5743 sc->stat_IfHCInBroadcastPkts =
5744 ((uint64_t)stats->stat_IfHCInBroadcastPkts_hi << 32) +
5745 (uint64_t)stats->stat_IfHCInBroadcastPkts_lo;
5747 sc->stat_IfHCOutUcastPkts =
5748 ((uint64_t)stats->stat_IfHCOutUcastPkts_hi << 32) +
5749 (uint64_t)stats->stat_IfHCOutUcastPkts_lo;
5751 sc->stat_IfHCOutMulticastPkts =
5752 ((uint64_t)stats->stat_IfHCOutMulticastPkts_hi << 32) +
5753 (uint64_t)stats->stat_IfHCOutMulticastPkts_lo;
5755 sc->stat_IfHCOutBroadcastPkts =
5756 ((uint64_t)stats->stat_IfHCOutBroadcastPkts_hi << 32) +
5757 (uint64_t)stats->stat_IfHCOutBroadcastPkts_lo;
5759 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
5760 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
5762 sc->stat_Dot3StatsCarrierSenseErrors =
5763 stats->stat_Dot3StatsCarrierSenseErrors;
5765 sc->stat_Dot3StatsFCSErrors =
5766 stats->stat_Dot3StatsFCSErrors;
5768 sc->stat_Dot3StatsAlignmentErrors =
5769 stats->stat_Dot3StatsAlignmentErrors;
5771 sc->stat_Dot3StatsSingleCollisionFrames =
5772 stats->stat_Dot3StatsSingleCollisionFrames;
5774 sc->stat_Dot3StatsMultipleCollisionFrames =
5775 stats->stat_Dot3StatsMultipleCollisionFrames;
5777 sc->stat_Dot3StatsDeferredTransmissions =
5778 stats->stat_Dot3StatsDeferredTransmissions;
5780 sc->stat_Dot3StatsExcessiveCollisions =
5781 stats->stat_Dot3StatsExcessiveCollisions;
5783 sc->stat_Dot3StatsLateCollisions =
5784 stats->stat_Dot3StatsLateCollisions;
5786 sc->stat_EtherStatsCollisions =
5787 stats->stat_EtherStatsCollisions;
5789 sc->stat_EtherStatsFragments =
5790 stats->stat_EtherStatsFragments;
5792 sc->stat_EtherStatsJabbers =
5793 stats->stat_EtherStatsJabbers;
5795 sc->stat_EtherStatsUndersizePkts =
5796 stats->stat_EtherStatsUndersizePkts;
5798 sc->stat_EtherStatsOverrsizePkts =
5799 stats->stat_EtherStatsOverrsizePkts;
5801 sc->stat_EtherStatsPktsRx64Octets =
5802 stats->stat_EtherStatsPktsRx64Octets;
5804 sc->stat_EtherStatsPktsRx65Octetsto127Octets =
5805 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
5807 sc->stat_EtherStatsPktsRx128Octetsto255Octets =
5808 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
5810 sc->stat_EtherStatsPktsRx256Octetsto511Octets =
5811 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
5813 sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
5814 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
5816 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
5817 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
5819 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
5820 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
5822 sc->stat_EtherStatsPktsTx64Octets =
5823 stats->stat_EtherStatsPktsTx64Octets;
5825 sc->stat_EtherStatsPktsTx65Octetsto127Octets =
5826 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
5828 sc->stat_EtherStatsPktsTx128Octetsto255Octets =
5829 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
5831 sc->stat_EtherStatsPktsTx256Octetsto511Octets =
5832 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
5834 sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
5835 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
5837 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
5838 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
5840 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
5841 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
5843 sc->stat_XonPauseFramesReceived =
5844 stats->stat_XonPauseFramesReceived;
5846 sc->stat_XoffPauseFramesReceived =
5847 stats->stat_XoffPauseFramesReceived;
5849 sc->stat_OutXonSent =
5850 stats->stat_OutXonSent;
5852 sc->stat_OutXoffSent =
5853 stats->stat_OutXoffSent;
5855 sc->stat_FlowControlDone =
5856 stats->stat_FlowControlDone;
5858 sc->stat_MacControlFramesReceived =
5859 stats->stat_MacControlFramesReceived;
5861 sc->stat_XoffStateEntered =
5862 stats->stat_XoffStateEntered;
5864 sc->stat_IfInFramesL2FilterDiscards =
5865 stats->stat_IfInFramesL2FilterDiscards;
5867 sc->stat_IfInRuleCheckerDiscards =
5868 stats->stat_IfInRuleCheckerDiscards;
5870 sc->stat_IfInFTQDiscards =
5871 stats->stat_IfInFTQDiscards;
5873 sc->stat_IfInMBUFDiscards =
5874 stats->stat_IfInMBUFDiscards;
5876 sc->stat_IfInRuleCheckerP4Hit =
5877 stats->stat_IfInRuleCheckerP4Hit;
5879 sc->stat_CatchupInRuleCheckerDiscards =
5880 stats->stat_CatchupInRuleCheckerDiscards;
5882 sc->stat_CatchupInFTQDiscards =
5883 stats->stat_CatchupInFTQDiscards;
5885 sc->stat_CatchupInMBUFDiscards =
5886 stats->stat_CatchupInMBUFDiscards;
5888 sc->stat_CatchupInRuleCheckerP4Hit =
5889 stats->stat_CatchupInRuleCheckerP4Hit;
5891 sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
5894 * Update the interface statistics from the
5895 * hardware statistics.
5897 ifp->if_collisions = (u_long)sc->stat_EtherStatsCollisions;
5899 ifp->if_ierrors = (u_long)sc->stat_EtherStatsUndersizePkts +
5900 (u_long)sc->stat_EtherStatsOverrsizePkts +
5901 (u_long)sc->stat_IfInMBUFDiscards +
5902 (u_long)sc->stat_Dot3StatsAlignmentErrors +
5903 (u_long)sc->stat_Dot3StatsFCSErrors +
5904 (u_long)sc->stat_IfInRuleCheckerDiscards +
5905 (u_long)sc->stat_IfInFTQDiscards +
5906 (u_long)sc->com_no_buffers;
5909 (u_long)sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
5910 (u_long)sc->stat_Dot3StatsExcessiveCollisions +
5911 (u_long)sc->stat_Dot3StatsLateCollisions;
5913 DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __func__);
5917 /****************************************************************************/
5918 /* Periodic function to notify the bootcode that the driver is still */
5923 /****************************************************************************/
5925 bce_pulse(void *xsc)
5927 struct bce_softc *sc = xsc;
5928 struct ifnet *ifp = &sc->arpcom.ac_if;
5931 lwkt_serialize_enter(ifp->if_serializer);
5933 if (ifp->if_flags & IFF_RUNNING) {
5934 if (sc->bce_irq_type == PCI_INTR_TYPE_MSI &&
5935 (sc->bce_flags & BCE_ONESHOT_MSI_FLAG) == 0)
5936 bce_pulse_check_msi(sc);
5939 /* Tell the firmware that the driver is still running. */
5940 msg = (uint32_t)++sc->bce_fw_drv_pulse_wr_seq;
5941 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
5943 /* Update the bootcode condition. */
5944 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
5946 /* Report whether the bootcode still knows the driver is running. */
5947 if (!sc->bce_drv_cardiac_arrest) {
5948 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
5949 sc->bce_drv_cardiac_arrest = 1;
5950 if_printf(ifp, "Bootcode lost the driver pulse! "
5951 "(bc_state = 0x%08X)\n", sc->bc_state);
5955 * Not supported by all bootcode versions.
5956 * (v5.0.11+ and v5.2.1+) Older bootcode
5957 * will require the driver to reset the
5958 * controller to clear this condition.
5960 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
5961 sc->bce_drv_cardiac_arrest = 0;
5962 if_printf(ifp, "Bootcode found the driver pulse! "
5963 "(bc_state = 0x%08X)\n", sc->bc_state);
5967 /* Schedule the next pulse. */
5968 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
5970 lwkt_serialize_exit(ifp->if_serializer);
5974 bce_pulse_check_msi(struct bce_softc *sc)
5978 if (bce_get_hw_rx_cons(sc) != sc->hw_rx_cons) {
5980 } else if (bce_get_hw_tx_cons(sc) != sc->hw_tx_cons) {
5983 struct status_block *sblk = sc->status_block;
5985 if ((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5986 (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
5993 msi_ctrl = REG_RD(sc, BCE_PCICFG_MSI_CONTROL);
5994 if ((msi_ctrl & BCE_PCICFG_MSI_CONTROL_ENABLE) == 0)
5997 if (sc->pulse_check_status_idx == sc->last_status_idx) {
5998 if_printf(&sc->arpcom.ac_if, "missing MSI\n");
6000 REG_WR(sc, BCE_PCICFG_MSI_CONTROL,
6001 msi_ctrl & ~BCE_PCICFG_MSI_CONTROL_ENABLE);
6002 REG_WR(sc, BCE_PCICFG_MSI_CONTROL, msi_ctrl);
6007 sc->pulse_check_status_idx = sc->last_status_idx;
6010 /****************************************************************************/
6011 /* Periodic function to perform maintenance tasks. */
6015 /****************************************************************************/
6017 bce_tick_serialized(struct bce_softc *sc)
6019 struct ifnet *ifp = &sc->arpcom.ac_if;
6020 struct mii_data *mii;
6022 ASSERT_SERIALIZED(ifp->if_serializer);
6024 /* Update the statistics from the hardware statistics block. */
6025 bce_stats_update(sc);
6027 /* Schedule the next tick. */
6028 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
6030 /* If link is up already up then we're done. */
6034 mii = device_get_softc(sc->bce_miibus);
6037 /* Check if the link has come up. */
6038 if ((mii->mii_media_status & IFM_ACTIVE) &&
6039 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6041 /* Now that link is up, handle any outstanding TX traffic. */
6042 if (!ifq_is_empty(&ifp->if_snd))
6051 struct bce_softc *sc = xsc;
6052 struct ifnet *ifp = &sc->arpcom.ac_if;
6054 lwkt_serialize_enter(ifp->if_serializer);
6055 bce_tick_serialized(sc);
6056 lwkt_serialize_exit(ifp->if_serializer);
6061 /****************************************************************************/
6062 /* Allows the driver state to be dumped through the sysctl interface. */
6065 /* 0 for success, positive value for failure. */
6066 /****************************************************************************/
6068 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
6072 struct bce_softc *sc;
6075 error = sysctl_handle_int(oidp, &result, 0, req);
6077 if (error || !req->newptr)
6081 sc = (struct bce_softc *)arg1;
6082 bce_dump_driver_state(sc);
6089 /****************************************************************************/
6090 /* Allows the hardware state to be dumped through the sysctl interface. */
6093 /* 0 for success, positive value for failure. */
6094 /****************************************************************************/
6096 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
6100 struct bce_softc *sc;
6103 error = sysctl_handle_int(oidp, &result, 0, req);
6105 if (error || !req->newptr)
6109 sc = (struct bce_softc *)arg1;
6110 bce_dump_hw_state(sc);
6117 /****************************************************************************/
6118 /* Provides a sysctl interface to allows dumping the RX chain. */
6121 /* 0 for success, positive value for failure. */
6122 /****************************************************************************/
6124 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS)
6128 struct bce_softc *sc;
6131 error = sysctl_handle_int(oidp, &result, 0, req);
6133 if (error || !req->newptr)
6137 sc = (struct bce_softc *)arg1;
6138 bce_dump_rx_chain(sc, 0, USABLE_RX_BD(sc));
6145 /****************************************************************************/
6146 /* Provides a sysctl interface to allows dumping the TX chain. */
6149 /* 0 for success, positive value for failure. */
6150 /****************************************************************************/
6152 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
6156 struct bce_softc *sc;
6159 error = sysctl_handle_int(oidp, &result, 0, req);
6161 if (error || !req->newptr)
6165 sc = (struct bce_softc *)arg1;
6166 bce_dump_tx_chain(sc, 0, USABLE_TX_BD(sc));
6173 /****************************************************************************/
6174 /* Provides a sysctl interface to allow reading arbitrary registers in the */
6175 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
6178 /* 0 for success, positive value for failure. */
6179 /****************************************************************************/
6181 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6183 struct bce_softc *sc;
6185 uint32_t val, result;
6188 error = sysctl_handle_int(oidp, &result, 0, req);
6189 if (error || (req->newptr == NULL))
6192 /* Make sure the register is accessible. */
6193 if (result < 0x8000) {
6194 sc = (struct bce_softc *)arg1;
6195 val = REG_RD(sc, result);
6196 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
6198 } else if (result < 0x0280000) {
6199 sc = (struct bce_softc *)arg1;
6200 val = REG_RD_IND(sc, result);
6201 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
6208 /****************************************************************************/
6209 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */
6210 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
6213 /* 0 for success, positive value for failure. */
6214 /****************************************************************************/
6216 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
6218 struct bce_softc *sc;
6224 error = sysctl_handle_int(oidp, &result, 0, req);
6225 if (error || (req->newptr == NULL))
6228 /* Make sure the register is accessible. */
6229 if (result < 0x20) {
6230 sc = (struct bce_softc *)arg1;
6232 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
6233 if_printf(&sc->arpcom.ac_if,
6234 "phy 0x%02X = 0x%04X\n", result, val);
6240 /****************************************************************************/
6241 /* Provides a sysctl interface to forcing the driver to dump state and */
6242 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
6245 /* 0 for success, positive value for failure. */
6246 /****************************************************************************/
6248 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
6252 struct bce_softc *sc;
6255 error = sysctl_handle_int(oidp, &result, 0, req);
6257 if (error || !req->newptr)
6261 sc = (struct bce_softc *)arg1;
6270 /****************************************************************************/
6271 /* Adds any sysctl parameters for tuning or debugging purposes. */
6274 /* 0 for success, positive value for failure. */
6275 /****************************************************************************/
6277 bce_add_sysctls(struct bce_softc *sc)
6279 struct sysctl_ctx_list *ctx;
6280 struct sysctl_oid_list *children;
6282 sysctl_ctx_init(&sc->bce_sysctl_ctx);
6283 sc->bce_sysctl_tree = SYSCTL_ADD_NODE(&sc->bce_sysctl_ctx,
6284 SYSCTL_STATIC_CHILDREN(_hw),
6286 device_get_nameunit(sc->bce_dev),
6288 if (sc->bce_sysctl_tree == NULL) {
6289 device_printf(sc->bce_dev, "can't add sysctl node\n");
6293 ctx = &sc->bce_sysctl_ctx;
6294 children = SYSCTL_CHILDREN(sc->bce_sysctl_tree);
6296 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds_int",
6297 CTLTYPE_INT | CTLFLAG_RW,
6298 sc, 0, bce_sysctl_tx_bds_int, "I",
6299 "Send max coalesced BD count during interrupt");
6300 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds",
6301 CTLTYPE_INT | CTLFLAG_RW,
6302 sc, 0, bce_sysctl_tx_bds, "I",
6303 "Send max coalesced BD count");
6304 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks_int",
6305 CTLTYPE_INT | CTLFLAG_RW,
6306 sc, 0, bce_sysctl_tx_ticks_int, "I",
6307 "Send coalescing ticks during interrupt");
6308 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks",
6309 CTLTYPE_INT | CTLFLAG_RW,
6310 sc, 0, bce_sysctl_tx_ticks, "I",
6311 "Send coalescing ticks");
6313 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds_int",
6314 CTLTYPE_INT | CTLFLAG_RW,
6315 sc, 0, bce_sysctl_rx_bds_int, "I",
6316 "Receive max coalesced BD count during interrupt");
6317 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds",
6318 CTLTYPE_INT | CTLFLAG_RW,
6319 sc, 0, bce_sysctl_rx_bds, "I",
6320 "Receive max coalesced BD count");
6321 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks_int",
6322 CTLTYPE_INT | CTLFLAG_RW,
6323 sc, 0, bce_sysctl_rx_ticks_int, "I",
6324 "Receive coalescing ticks during interrupt");
6325 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks",
6326 CTLTYPE_INT | CTLFLAG_RW,
6327 sc, 0, bce_sysctl_rx_ticks, "I",
6328 "Receive coalescing ticks");
6330 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_pages",
6331 CTLFLAG_RD, &sc->rx_pages, 0, "# of RX pages");
6332 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_pages",
6333 CTLFLAG_RD, &sc->tx_pages, 0, "# of TX pages");
6336 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6338 CTLFLAG_RD, &sc->rx_low_watermark,
6339 0, "Lowest level of free rx_bd's");
6341 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6343 CTLFLAG_RD, &sc->rx_empty_count,
6344 0, "Number of times the RX chain was empty");
6346 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6348 CTLFLAG_RD, &sc->tx_hi_watermark,
6349 0, "Highest level of used tx_bd's");
6351 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6353 CTLFLAG_RD, &sc->tx_full_count,
6354 0, "Number of times the TX chain was full");
6356 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6357 "l2fhdr_status_errors",
6358 CTLFLAG_RD, &sc->l2fhdr_status_errors,
6359 0, "l2_fhdr status errors");
6361 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6362 "unexpected_attentions",
6363 CTLFLAG_RD, &sc->unexpected_attentions,
6364 0, "unexpected attentions");
6366 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6367 "lost_status_block_updates",
6368 CTLFLAG_RD, &sc->lost_status_block_updates,
6369 0, "lost status block updates");
6371 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6372 "mbuf_alloc_failed",
6373 CTLFLAG_RD, &sc->mbuf_alloc_failed,
6374 0, "mbuf cluster allocation failures");
6377 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6378 "stat_IfHCInOctets",
6379 CTLFLAG_RD, &sc->stat_IfHCInOctets,
6382 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6383 "stat_IfHCInBadOctets",
6384 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
6385 "Bad bytes received");
6387 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6388 "stat_IfHCOutOctets",
6389 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
6392 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6393 "stat_IfHCOutBadOctets",
6394 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
6397 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6398 "stat_IfHCInUcastPkts",
6399 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
6400 "Unicast packets received");
6402 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6403 "stat_IfHCInMulticastPkts",
6404 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
6405 "Multicast packets received");
6407 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6408 "stat_IfHCInBroadcastPkts",
6409 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
6410 "Broadcast packets received");
6412 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6413 "stat_IfHCOutUcastPkts",
6414 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
6415 "Unicast packets sent");
6417 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6418 "stat_IfHCOutMulticastPkts",
6419 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
6420 "Multicast packets sent");
6422 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6423 "stat_IfHCOutBroadcastPkts",
6424 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
6425 "Broadcast packets sent");
6427 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6428 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
6429 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
6430 0, "Internal MAC transmit errors");
6432 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6433 "stat_Dot3StatsCarrierSenseErrors",
6434 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
6435 0, "Carrier sense errors");
6437 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6438 "stat_Dot3StatsFCSErrors",
6439 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
6440 0, "Frame check sequence errors");
6442 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6443 "stat_Dot3StatsAlignmentErrors",
6444 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
6445 0, "Alignment errors");
6447 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6448 "stat_Dot3StatsSingleCollisionFrames",
6449 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
6450 0, "Single Collision Frames");
6452 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6453 "stat_Dot3StatsMultipleCollisionFrames",
6454 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
6455 0, "Multiple Collision Frames");
6457 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6458 "stat_Dot3StatsDeferredTransmissions",
6459 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
6460 0, "Deferred Transmissions");
6462 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6463 "stat_Dot3StatsExcessiveCollisions",
6464 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
6465 0, "Excessive Collisions");
6467 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6468 "stat_Dot3StatsLateCollisions",
6469 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
6470 0, "Late Collisions");
6472 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6473 "stat_EtherStatsCollisions",
6474 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
6477 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6478 "stat_EtherStatsFragments",
6479 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
6482 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6483 "stat_EtherStatsJabbers",
6484 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
6487 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6488 "stat_EtherStatsUndersizePkts",
6489 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
6490 0, "Undersize packets");
6492 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6493 "stat_EtherStatsOverrsizePkts",
6494 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
6495 0, "stat_EtherStatsOverrsizePkts");
6497 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6498 "stat_EtherStatsPktsRx64Octets",
6499 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
6500 0, "Bytes received in 64 byte packets");
6502 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6503 "stat_EtherStatsPktsRx65Octetsto127Octets",
6504 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
6505 0, "Bytes received in 65 to 127 byte packets");
6507 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6508 "stat_EtherStatsPktsRx128Octetsto255Octets",
6509 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
6510 0, "Bytes received in 128 to 255 byte packets");
6512 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6513 "stat_EtherStatsPktsRx256Octetsto511Octets",
6514 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
6515 0, "Bytes received in 256 to 511 byte packets");
6517 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6518 "stat_EtherStatsPktsRx512Octetsto1023Octets",
6519 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
6520 0, "Bytes received in 512 to 1023 byte packets");
6522 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6523 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
6524 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
6525 0, "Bytes received in 1024 t0 1522 byte packets");
6527 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6528 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
6529 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
6530 0, "Bytes received in 1523 to 9022 byte packets");
6532 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6533 "stat_EtherStatsPktsTx64Octets",
6534 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
6535 0, "Bytes sent in 64 byte packets");
6537 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6538 "stat_EtherStatsPktsTx65Octetsto127Octets",
6539 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
6540 0, "Bytes sent in 65 to 127 byte packets");
6542 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6543 "stat_EtherStatsPktsTx128Octetsto255Octets",
6544 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
6545 0, "Bytes sent in 128 to 255 byte packets");
6547 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6548 "stat_EtherStatsPktsTx256Octetsto511Octets",
6549 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
6550 0, "Bytes sent in 256 to 511 byte packets");
6552 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6553 "stat_EtherStatsPktsTx512Octetsto1023Octets",
6554 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
6555 0, "Bytes sent in 512 to 1023 byte packets");
6557 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6558 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
6559 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
6560 0, "Bytes sent in 1024 to 1522 byte packets");
6562 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6563 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
6564 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
6565 0, "Bytes sent in 1523 to 9022 byte packets");
6567 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6568 "stat_XonPauseFramesReceived",
6569 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
6570 0, "XON pause frames receved");
6572 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6573 "stat_XoffPauseFramesReceived",
6574 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
6575 0, "XOFF pause frames received");
6577 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6579 CTLFLAG_RD, &sc->stat_OutXonSent,
6580 0, "XON pause frames sent");
6582 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6584 CTLFLAG_RD, &sc->stat_OutXoffSent,
6585 0, "XOFF pause frames sent");
6587 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6588 "stat_FlowControlDone",
6589 CTLFLAG_RD, &sc->stat_FlowControlDone,
6590 0, "Flow control done");
6592 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6593 "stat_MacControlFramesReceived",
6594 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
6595 0, "MAC control frames received");
6597 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6598 "stat_XoffStateEntered",
6599 CTLFLAG_RD, &sc->stat_XoffStateEntered,
6600 0, "XOFF state entered");
6602 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6603 "stat_IfInFramesL2FilterDiscards",
6604 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
6605 0, "Received L2 packets discarded");
6607 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6608 "stat_IfInRuleCheckerDiscards",
6609 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
6610 0, "Received packets discarded by rule");
6612 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6613 "stat_IfInFTQDiscards",
6614 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
6615 0, "Received packet FTQ discards");
6617 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6618 "stat_IfInMBUFDiscards",
6619 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
6620 0, "Received packets discarded due to lack of controller buffer memory");
6622 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6623 "stat_IfInRuleCheckerP4Hit",
6624 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
6625 0, "Received packets rule checker hits");
6627 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6628 "stat_CatchupInRuleCheckerDiscards",
6629 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
6630 0, "Received packets discarded in Catchup path");
6632 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6633 "stat_CatchupInFTQDiscards",
6634 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
6635 0, "Received packets discarded in FTQ in Catchup path");
6637 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6638 "stat_CatchupInMBUFDiscards",
6639 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
6640 0, "Received packets discarded in controller buffer memory in Catchup path");
6642 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6643 "stat_CatchupInRuleCheckerP4Hit",
6644 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
6645 0, "Received packets rule checker hits in Catchup path");
6647 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6649 CTLFLAG_RD, &sc->com_no_buffers,
6650 0, "Valid packets received but no RX buffers available");
6653 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6654 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
6656 bce_sysctl_driver_state, "I", "Drive state information");
6658 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6659 "hw_state", CTLTYPE_INT | CTLFLAG_RW,
6661 bce_sysctl_hw_state, "I", "Hardware state information");
6663 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6664 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW,
6666 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain");
6668 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6669 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
6671 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
6673 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6674 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
6676 bce_sysctl_breakpoint, "I", "Driver breakpoint");
6678 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6679 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
6681 bce_sysctl_reg_read, "I", "Register read");
6683 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6684 "phy_read", CTLTYPE_INT | CTLFLAG_RW,
6686 bce_sysctl_phy_read, "I", "PHY register read");
6693 /****************************************************************************/
6694 /* BCE Debug Routines */
6695 /****************************************************************************/
6698 /****************************************************************************/
6699 /* Freezes the controller to allow for a cohesive state dump. */
6703 /****************************************************************************/
6705 bce_freeze_controller(struct bce_softc *sc)
6709 val = REG_RD(sc, BCE_MISC_COMMAND);
6710 val |= BCE_MISC_COMMAND_DISABLE_ALL;
6711 REG_WR(sc, BCE_MISC_COMMAND, val);
6715 /****************************************************************************/
6716 /* Unfreezes the controller after a freeze operation. This may not always */
6717 /* work and the controller will require a reset! */
6721 /****************************************************************************/
6723 bce_unfreeze_controller(struct bce_softc *sc)
6727 val = REG_RD(sc, BCE_MISC_COMMAND);
6728 val |= BCE_MISC_COMMAND_ENABLE_ALL;
6729 REG_WR(sc, BCE_MISC_COMMAND, val);
6733 /****************************************************************************/
6734 /* Prints out information about an mbuf. */
6738 /****************************************************************************/
6740 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
6742 struct ifnet *ifp = &sc->arpcom.ac_if;
6743 uint32_t val_hi, val_lo;
6744 struct mbuf *mp = m;
6747 /* Index out of range. */
6748 if_printf(ifp, "mbuf: null pointer\n");
6753 val_hi = BCE_ADDR_HI(mp);
6754 val_lo = BCE_ADDR_LO(mp);
6755 if_printf(ifp, "mbuf: vaddr = 0x%08X:%08X, m_len = %d, "
6756 "m_flags = ( ", val_hi, val_lo, mp->m_len);
6758 if (mp->m_flags & M_EXT)
6760 if (mp->m_flags & M_PKTHDR)
6761 kprintf("M_PKTHDR ");
6762 if (mp->m_flags & M_EOR)
6765 if (mp->m_flags & M_RDONLY)
6766 kprintf("M_RDONLY ");
6769 val_hi = BCE_ADDR_HI(mp->m_data);
6770 val_lo = BCE_ADDR_LO(mp->m_data);
6771 kprintf(") m_data = 0x%08X:%08X\n", val_hi, val_lo);
6773 if (mp->m_flags & M_PKTHDR) {
6774 if_printf(ifp, "- m_pkthdr: flags = ( ");
6775 if (mp->m_flags & M_BCAST)
6776 kprintf("M_BCAST ");
6777 if (mp->m_flags & M_MCAST)
6778 kprintf("M_MCAST ");
6779 if (mp->m_flags & M_FRAG)
6781 if (mp->m_flags & M_FIRSTFRAG)
6782 kprintf("M_FIRSTFRAG ");
6783 if (mp->m_flags & M_LASTFRAG)
6784 kprintf("M_LASTFRAG ");
6786 if (mp->m_flags & M_VLANTAG)
6787 kprintf("M_VLANTAG ");
6790 if (mp->m_flags & M_PROMISC)
6791 kprintf("M_PROMISC ");
6793 kprintf(") csum_flags = ( ");
6794 if (mp->m_pkthdr.csum_flags & CSUM_IP)
6795 kprintf("CSUM_IP ");
6796 if (mp->m_pkthdr.csum_flags & CSUM_TCP)
6797 kprintf("CSUM_TCP ");
6798 if (mp->m_pkthdr.csum_flags & CSUM_UDP)
6799 kprintf("CSUM_UDP ");
6800 if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS)
6801 kprintf("CSUM_IP_FRAGS ");
6802 if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT)
6803 kprintf("CSUM_FRAGMENT ");
6805 if (mp->m_pkthdr.csum_flags & CSUM_TSO)
6806 kprintf("CSUM_TSO ");
6808 if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED)
6809 kprintf("CSUM_IP_CHECKED ");
6810 if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID)
6811 kprintf("CSUM_IP_VALID ");
6812 if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID)
6813 kprintf("CSUM_DATA_VALID ");
6817 if (mp->m_flags & M_EXT) {
6818 val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf);
6819 val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf);
6820 if_printf(ifp, "- m_ext: vaddr = 0x%08X:%08X, "
6822 val_hi, val_lo, mp->m_ext.ext_size);
6829 /****************************************************************************/
6830 /* Prints out the mbufs in the TX mbuf chain. */
6834 /****************************************************************************/
6836 bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6838 struct ifnet *ifp = &sc->arpcom.ac_if;
6842 "----------------------------"
6844 "----------------------------\n");
6846 for (i = 0; i < count; i++) {
6847 if_printf(ifp, "txmbuf[%d]\n", chain_prod);
6848 bce_dump_mbuf(sc, sc->tx_mbuf_ptr[chain_prod]);
6849 chain_prod = TX_CHAIN_IDX(sc, NEXT_TX_BD(chain_prod));
6853 "----------------------------"
6855 "----------------------------\n");
6859 /****************************************************************************/
6860 /* Prints out the mbufs in the RX mbuf chain. */
6864 /****************************************************************************/
6866 bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6868 struct ifnet *ifp = &sc->arpcom.ac_if;
6872 "----------------------------"
6874 "----------------------------\n");
6876 for (i = 0; i < count; i++) {
6877 if_printf(ifp, "rxmbuf[0x%04X]\n", chain_prod);
6878 bce_dump_mbuf(sc, sc->rx_mbuf_ptr[chain_prod]);
6879 chain_prod = RX_CHAIN_IDX(sc, NEXT_RX_BD(chain_prod));
6883 "----------------------------"
6885 "----------------------------\n");
6889 /****************************************************************************/
6890 /* Prints out a tx_bd structure. */
6894 /****************************************************************************/
6896 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
6898 struct ifnet *ifp = &sc->arpcom.ac_if;
6900 if (idx > MAX_TX_BD(sc)) {
6901 /* Index out of range. */
6902 if_printf(ifp, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
6903 } else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) {
6904 /* TX Chain page pointer. */
6905 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6906 "chain page pointer\n",
6907 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo);
6909 /* Normal tx_bd entry. */
6910 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6912 "vlan tag= 0x%04X, flags = 0x%04X (",
6913 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
6914 txbd->tx_bd_mss_nbytes,
6915 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
6917 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT)
6918 kprintf(" CONN_FAULT");
6920 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM)
6921 kprintf(" TCP_UDP_CKSUM");
6923 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM)
6924 kprintf(" IP_CKSUM");
6926 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG)
6929 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW)
6930 kprintf(" COAL_NOW");
6932 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC)
6933 kprintf(" DONT_GEN_CRC");
6935 if (txbd->tx_bd_flags & TX_BD_FLAGS_START)
6938 if (txbd->tx_bd_flags & TX_BD_FLAGS_END)
6941 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO)
6944 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD)
6945 kprintf(" OPTION_WORD");
6947 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS)
6950 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP)
6958 /****************************************************************************/
6959 /* Prints out a rx_bd structure. */
6963 /****************************************************************************/
6965 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
6967 struct ifnet *ifp = &sc->arpcom.ac_if;
6969 if (idx > MAX_RX_BD(sc)) {
6970 /* Index out of range. */
6971 if_printf(ifp, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
6972 } else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) {
6973 /* TX Chain page pointer. */
6974 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6975 "chain page pointer\n",
6976 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo);
6978 /* Normal tx_bd entry. */
6979 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6980 "nbytes = 0x%08X, flags = 0x%08X\n",
6981 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
6982 rxbd->rx_bd_len, rxbd->rx_bd_flags);
6987 /****************************************************************************/
6988 /* Prints out a l2_fhdr structure. */
6992 /****************************************************************************/
6994 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
6996 if_printf(&sc->arpcom.ac_if, "l2_fhdr[0x%04X]: status = 0x%08X, "
6997 "pkt_len = 0x%04X, vlan = 0x%04x, "
6998 "ip_xsum = 0x%04X, tcp_udp_xsum = 0x%04X\n",
6999 idx, l2fhdr->l2_fhdr_status,
7000 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
7001 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
7005 /****************************************************************************/
7006 /* Prints out the tx chain. */
7010 /****************************************************************************/
7012 bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count)
7014 struct ifnet *ifp = &sc->arpcom.ac_if;
7017 /* First some info about the tx_bd chain structure. */
7019 "----------------------------"
7021 "----------------------------\n");
7023 if_printf(ifp, "page size = 0x%08X, "
7024 "tx chain pages = 0x%08X\n",
7025 (uint32_t)BCM_PAGE_SIZE, (uint32_t)sc->tx_pages);
7027 if_printf(ifp, "tx_bd per page = 0x%08X, "
7028 "usable tx_bd per page = 0x%08X\n",
7029 (uint32_t)TOTAL_TX_BD_PER_PAGE,
7030 (uint32_t)USABLE_TX_BD_PER_PAGE);
7032 if_printf(ifp, "total tx_bd = 0x%08X\n", (uint32_t)TOTAL_TX_BD(sc));
7035 "----------------------------"
7037 "----------------------------\n");
7039 /* Now print out the tx_bd's themselves. */
7040 for (i = 0; i < count; i++) {
7043 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
7044 bce_dump_txbd(sc, tx_prod, txbd);
7045 tx_prod = TX_CHAIN_IDX(sc, NEXT_TX_BD(tx_prod));
7049 "----------------------------"
7051 "----------------------------\n");
7055 /****************************************************************************/
7056 /* Prints out the rx chain. */
7060 /****************************************************************************/
7062 bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count)
7064 struct ifnet *ifp = &sc->arpcom.ac_if;
7067 /* First some info about the tx_bd chain structure. */
7069 "----------------------------"
7071 "----------------------------\n");
7073 if_printf(ifp, "page size = 0x%08X, "
7074 "rx chain pages = 0x%08X\n",
7075 (uint32_t)BCM_PAGE_SIZE, (uint32_t)sc->rx_pages);
7077 if_printf(ifp, "rx_bd per page = 0x%08X, "
7078 "usable rx_bd per page = 0x%08X\n",
7079 (uint32_t)TOTAL_RX_BD_PER_PAGE,
7080 (uint32_t)USABLE_RX_BD_PER_PAGE);
7082 if_printf(ifp, "total rx_bd = 0x%08X\n", (uint32_t)TOTAL_RX_BD(sc));
7085 "----------------------------"
7087 "----------------------------\n");
7089 /* Now print out the rx_bd's themselves. */
7090 for (i = 0; i < count; i++) {
7093 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
7094 bce_dump_rxbd(sc, rx_prod, rxbd);
7095 rx_prod = RX_CHAIN_IDX(sc, NEXT_RX_BD(rx_prod));
7099 "----------------------------"
7101 "----------------------------\n");
7105 /****************************************************************************/
7106 /* Prints out the status block from host memory. */
7110 /****************************************************************************/
7112 bce_dump_status_block(struct bce_softc *sc)
7114 struct status_block *sblk = sc->status_block;
7115 struct ifnet *ifp = &sc->arpcom.ac_if;
7118 "----------------------------"
7120 "----------------------------\n");
7122 if_printf(ifp, " 0x%08X - attn_bits\n", sblk->status_attn_bits);
7124 if_printf(ifp, " 0x%08X - attn_bits_ack\n",
7125 sblk->status_attn_bits_ack);
7127 if_printf(ifp, "0x%04X(0x%04X) - rx_cons0\n",
7128 sblk->status_rx_quick_consumer_index0,
7129 (uint16_t)RX_CHAIN_IDX(sc, sblk->status_rx_quick_consumer_index0));
7131 if_printf(ifp, "0x%04X(0x%04X) - tx_cons0\n",
7132 sblk->status_tx_quick_consumer_index0,
7133 (uint16_t)TX_CHAIN_IDX(sc, sblk->status_tx_quick_consumer_index0));
7135 if_printf(ifp, " 0x%04X - status_idx\n", sblk->status_idx);
7137 /* Theses indices are not used for normal L2 drivers. */
7138 if (sblk->status_rx_quick_consumer_index1) {
7139 if_printf(ifp, "0x%04X(0x%04X) - rx_cons1\n",
7140 sblk->status_rx_quick_consumer_index1,
7141 (uint16_t)RX_CHAIN_IDX(sc,
7142 sblk->status_rx_quick_consumer_index1));
7145 if (sblk->status_tx_quick_consumer_index1) {
7146 if_printf(ifp, "0x%04X(0x%04X) - tx_cons1\n",
7147 sblk->status_tx_quick_consumer_index1,
7148 (uint16_t)TX_CHAIN_IDX(sc,
7149 sblk->status_tx_quick_consumer_index1));
7152 if (sblk->status_rx_quick_consumer_index2) {
7153 if_printf(ifp, "0x%04X(0x%04X)- rx_cons2\n",
7154 sblk->status_rx_quick_consumer_index2,
7155 (uint16_t)RX_CHAIN_IDX(sc,
7156 sblk->status_rx_quick_consumer_index2));
7159 if (sblk->status_tx_quick_consumer_index2) {
7160 if_printf(ifp, "0x%04X(0x%04X) - tx_cons2\n",
7161 sblk->status_tx_quick_consumer_index2,
7162 (uint16_t)TX_CHAIN_IDX(sc,
7163 sblk->status_tx_quick_consumer_index2));
7166 if (sblk->status_rx_quick_consumer_index3) {
7167 if_printf(ifp, "0x%04X(0x%04X) - rx_cons3\n",
7168 sblk->status_rx_quick_consumer_index3,
7169 (uint16_t)RX_CHAIN_IDX(sc,
7170 sblk->status_rx_quick_consumer_index3));
7173 if (sblk->status_tx_quick_consumer_index3) {
7174 if_printf(ifp, "0x%04X(0x%04X) - tx_cons3\n",
7175 sblk->status_tx_quick_consumer_index3,
7176 (uint16_t)TX_CHAIN_IDX(sc,
7177 sblk->status_tx_quick_consumer_index3));
7180 if (sblk->status_rx_quick_consumer_index4 ||
7181 sblk->status_rx_quick_consumer_index5) {
7182 if_printf(ifp, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n",
7183 sblk->status_rx_quick_consumer_index4,
7184 sblk->status_rx_quick_consumer_index5);
7187 if (sblk->status_rx_quick_consumer_index6 ||
7188 sblk->status_rx_quick_consumer_index7) {
7189 if_printf(ifp, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n",
7190 sblk->status_rx_quick_consumer_index6,
7191 sblk->status_rx_quick_consumer_index7);
7194 if (sblk->status_rx_quick_consumer_index8 ||
7195 sblk->status_rx_quick_consumer_index9) {
7196 if_printf(ifp, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n",
7197 sblk->status_rx_quick_consumer_index8,
7198 sblk->status_rx_quick_consumer_index9);
7201 if (sblk->status_rx_quick_consumer_index10 ||
7202 sblk->status_rx_quick_consumer_index11) {
7203 if_printf(ifp, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n",
7204 sblk->status_rx_quick_consumer_index10,
7205 sblk->status_rx_quick_consumer_index11);
7208 if (sblk->status_rx_quick_consumer_index12 ||
7209 sblk->status_rx_quick_consumer_index13) {
7210 if_printf(ifp, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n",
7211 sblk->status_rx_quick_consumer_index12,
7212 sblk->status_rx_quick_consumer_index13);
7215 if (sblk->status_rx_quick_consumer_index14 ||
7216 sblk->status_rx_quick_consumer_index15) {
7217 if_printf(ifp, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n",
7218 sblk->status_rx_quick_consumer_index14,
7219 sblk->status_rx_quick_consumer_index15);
7222 if (sblk->status_completion_producer_index ||
7223 sblk->status_cmd_consumer_index) {
7224 if_printf(ifp, "com_prod = 0x%08X, cmd_cons = 0x%08X\n",
7225 sblk->status_completion_producer_index,
7226 sblk->status_cmd_consumer_index);
7230 "----------------------------"
7232 "----------------------------\n");
7236 /****************************************************************************/
7237 /* Prints out the statistics block. */
7241 /****************************************************************************/
7243 bce_dump_stats_block(struct bce_softc *sc)
7245 struct statistics_block *sblk = sc->stats_block;
7246 struct ifnet *ifp = &sc->arpcom.ac_if;
7250 " Stats Block (All Stats Not Shown Are 0) "
7251 "---------------\n");
7253 if (sblk->stat_IfHCInOctets_hi || sblk->stat_IfHCInOctets_lo) {
7254 if_printf(ifp, "0x%08X:%08X : IfHcInOctets\n",
7255 sblk->stat_IfHCInOctets_hi,
7256 sblk->stat_IfHCInOctets_lo);
7259 if (sblk->stat_IfHCInBadOctets_hi || sblk->stat_IfHCInBadOctets_lo) {
7260 if_printf(ifp, "0x%08X:%08X : IfHcInBadOctets\n",
7261 sblk->stat_IfHCInBadOctets_hi,
7262 sblk->stat_IfHCInBadOctets_lo);
7265 if (sblk->stat_IfHCOutOctets_hi || sblk->stat_IfHCOutOctets_lo) {
7266 if_printf(ifp, "0x%08X:%08X : IfHcOutOctets\n",
7267 sblk->stat_IfHCOutOctets_hi,
7268 sblk->stat_IfHCOutOctets_lo);
7271 if (sblk->stat_IfHCOutBadOctets_hi || sblk->stat_IfHCOutBadOctets_lo) {
7272 if_printf(ifp, "0x%08X:%08X : IfHcOutBadOctets\n",
7273 sblk->stat_IfHCOutBadOctets_hi,
7274 sblk->stat_IfHCOutBadOctets_lo);
7277 if (sblk->stat_IfHCInUcastPkts_hi || sblk->stat_IfHCInUcastPkts_lo) {
7278 if_printf(ifp, "0x%08X:%08X : IfHcInUcastPkts\n",
7279 sblk->stat_IfHCInUcastPkts_hi,
7280 sblk->stat_IfHCInUcastPkts_lo);
7283 if (sblk->stat_IfHCInBroadcastPkts_hi ||
7284 sblk->stat_IfHCInBroadcastPkts_lo) {
7285 if_printf(ifp, "0x%08X:%08X : IfHcInBroadcastPkts\n",
7286 sblk->stat_IfHCInBroadcastPkts_hi,
7287 sblk->stat_IfHCInBroadcastPkts_lo);
7290 if (sblk->stat_IfHCInMulticastPkts_hi ||
7291 sblk->stat_IfHCInMulticastPkts_lo) {
7292 if_printf(ifp, "0x%08X:%08X : IfHcInMulticastPkts\n",
7293 sblk->stat_IfHCInMulticastPkts_hi,
7294 sblk->stat_IfHCInMulticastPkts_lo);
7297 if (sblk->stat_IfHCOutUcastPkts_hi || sblk->stat_IfHCOutUcastPkts_lo) {
7298 if_printf(ifp, "0x%08X:%08X : IfHcOutUcastPkts\n",
7299 sblk->stat_IfHCOutUcastPkts_hi,
7300 sblk->stat_IfHCOutUcastPkts_lo);
7303 if (sblk->stat_IfHCOutBroadcastPkts_hi ||
7304 sblk->stat_IfHCOutBroadcastPkts_lo) {
7305 if_printf(ifp, "0x%08X:%08X : IfHcOutBroadcastPkts\n",
7306 sblk->stat_IfHCOutBroadcastPkts_hi,
7307 sblk->stat_IfHCOutBroadcastPkts_lo);
7310 if (sblk->stat_IfHCOutMulticastPkts_hi ||
7311 sblk->stat_IfHCOutMulticastPkts_lo) {
7312 if_printf(ifp, "0x%08X:%08X : IfHcOutMulticastPkts\n",
7313 sblk->stat_IfHCOutMulticastPkts_hi,
7314 sblk->stat_IfHCOutMulticastPkts_lo);
7317 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) {
7318 if_printf(ifp, " 0x%08X : "
7319 "emac_tx_stat_dot3statsinternalmactransmiterrors\n",
7320 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
7323 if (sblk->stat_Dot3StatsCarrierSenseErrors) {
7324 if_printf(ifp, " 0x%08X : "
7325 "Dot3StatsCarrierSenseErrors\n",
7326 sblk->stat_Dot3StatsCarrierSenseErrors);
7329 if (sblk->stat_Dot3StatsFCSErrors) {
7330 if_printf(ifp, " 0x%08X : Dot3StatsFCSErrors\n",
7331 sblk->stat_Dot3StatsFCSErrors);
7334 if (sblk->stat_Dot3StatsAlignmentErrors) {
7335 if_printf(ifp, " 0x%08X : Dot3StatsAlignmentErrors\n",
7336 sblk->stat_Dot3StatsAlignmentErrors);
7339 if (sblk->stat_Dot3StatsSingleCollisionFrames) {
7340 if_printf(ifp, " 0x%08X : "
7341 "Dot3StatsSingleCollisionFrames\n",
7342 sblk->stat_Dot3StatsSingleCollisionFrames);
7345 if (sblk->stat_Dot3StatsMultipleCollisionFrames) {
7346 if_printf(ifp, " 0x%08X : "
7347 "Dot3StatsMultipleCollisionFrames\n",
7348 sblk->stat_Dot3StatsMultipleCollisionFrames);
7351 if (sblk->stat_Dot3StatsDeferredTransmissions) {
7352 if_printf(ifp, " 0x%08X : "
7353 "Dot3StatsDeferredTransmissions\n",
7354 sblk->stat_Dot3StatsDeferredTransmissions);
7357 if (sblk->stat_Dot3StatsExcessiveCollisions) {
7358 if_printf(ifp, " 0x%08X : "
7359 "Dot3StatsExcessiveCollisions\n",
7360 sblk->stat_Dot3StatsExcessiveCollisions);
7363 if (sblk->stat_Dot3StatsLateCollisions) {
7364 if_printf(ifp, " 0x%08X : Dot3StatsLateCollisions\n",
7365 sblk->stat_Dot3StatsLateCollisions);
7368 if (sblk->stat_EtherStatsCollisions) {
7369 if_printf(ifp, " 0x%08X : EtherStatsCollisions\n",
7370 sblk->stat_EtherStatsCollisions);
7373 if (sblk->stat_EtherStatsFragments) {
7374 if_printf(ifp, " 0x%08X : EtherStatsFragments\n",
7375 sblk->stat_EtherStatsFragments);
7378 if (sblk->stat_EtherStatsJabbers) {
7379 if_printf(ifp, " 0x%08X : EtherStatsJabbers\n",
7380 sblk->stat_EtherStatsJabbers);
7383 if (sblk->stat_EtherStatsUndersizePkts) {
7384 if_printf(ifp, " 0x%08X : EtherStatsUndersizePkts\n",
7385 sblk->stat_EtherStatsUndersizePkts);
7388 if (sblk->stat_EtherStatsOverrsizePkts) {
7389 if_printf(ifp, " 0x%08X : EtherStatsOverrsizePkts\n",
7390 sblk->stat_EtherStatsOverrsizePkts);
7393 if (sblk->stat_EtherStatsPktsRx64Octets) {
7394 if_printf(ifp, " 0x%08X : EtherStatsPktsRx64Octets\n",
7395 sblk->stat_EtherStatsPktsRx64Octets);
7398 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) {
7399 if_printf(ifp, " 0x%08X : "
7400 "EtherStatsPktsRx65Octetsto127Octets\n",
7401 sblk->stat_EtherStatsPktsRx65Octetsto127Octets);
7404 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) {
7405 if_printf(ifp, " 0x%08X : "
7406 "EtherStatsPktsRx128Octetsto255Octets\n",
7407 sblk->stat_EtherStatsPktsRx128Octetsto255Octets);
7410 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) {
7411 if_printf(ifp, " 0x%08X : "
7412 "EtherStatsPktsRx256Octetsto511Octets\n",
7413 sblk->stat_EtherStatsPktsRx256Octetsto511Octets);
7416 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) {
7417 if_printf(ifp, " 0x%08X : "
7418 "EtherStatsPktsRx512Octetsto1023Octets\n",
7419 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets);
7422 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) {
7423 if_printf(ifp, " 0x%08X : "
7424 "EtherStatsPktsRx1024Octetsto1522Octets\n",
7425 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets);
7428 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) {
7429 if_printf(ifp, " 0x%08X : "
7430 "EtherStatsPktsRx1523Octetsto9022Octets\n",
7431 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets);
7434 if (sblk->stat_EtherStatsPktsTx64Octets) {
7435 if_printf(ifp, " 0x%08X : EtherStatsPktsTx64Octets\n",
7436 sblk->stat_EtherStatsPktsTx64Octets);
7439 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) {
7440 if_printf(ifp, " 0x%08X : "
7441 "EtherStatsPktsTx65Octetsto127Octets\n",
7442 sblk->stat_EtherStatsPktsTx65Octetsto127Octets);
7445 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) {
7446 if_printf(ifp, " 0x%08X : "
7447 "EtherStatsPktsTx128Octetsto255Octets\n",
7448 sblk->stat_EtherStatsPktsTx128Octetsto255Octets);
7451 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) {
7452 if_printf(ifp, " 0x%08X : "
7453 "EtherStatsPktsTx256Octetsto511Octets\n",
7454 sblk->stat_EtherStatsPktsTx256Octetsto511Octets);
7457 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) {
7458 if_printf(ifp, " 0x%08X : "
7459 "EtherStatsPktsTx512Octetsto1023Octets\n",
7460 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets);
7463 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) {
7464 if_printf(ifp, " 0x%08X : "
7465 "EtherStatsPktsTx1024Octetsto1522Octets\n",
7466 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets);
7469 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) {
7470 if_printf(ifp, " 0x%08X : "
7471 "EtherStatsPktsTx1523Octetsto9022Octets\n",
7472 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets);
7475 if (sblk->stat_XonPauseFramesReceived) {
7476 if_printf(ifp, " 0x%08X : XonPauseFramesReceived\n",
7477 sblk->stat_XonPauseFramesReceived);
7480 if (sblk->stat_XoffPauseFramesReceived) {
7481 if_printf(ifp, " 0x%08X : XoffPauseFramesReceived\n",
7482 sblk->stat_XoffPauseFramesReceived);
7485 if (sblk->stat_OutXonSent) {
7486 if_printf(ifp, " 0x%08X : OutXoffSent\n",
7487 sblk->stat_OutXonSent);
7490 if (sblk->stat_OutXoffSent) {
7491 if_printf(ifp, " 0x%08X : OutXoffSent\n",
7492 sblk->stat_OutXoffSent);
7495 if (sblk->stat_FlowControlDone) {
7496 if_printf(ifp, " 0x%08X : FlowControlDone\n",
7497 sblk->stat_FlowControlDone);
7500 if (sblk->stat_MacControlFramesReceived) {
7501 if_printf(ifp, " 0x%08X : MacControlFramesReceived\n",
7502 sblk->stat_MacControlFramesReceived);
7505 if (sblk->stat_XoffStateEntered) {
7506 if_printf(ifp, " 0x%08X : XoffStateEntered\n",
7507 sblk->stat_XoffStateEntered);
7510 if (sblk->stat_IfInFramesL2FilterDiscards) {
7511 if_printf(ifp, " 0x%08X : IfInFramesL2FilterDiscards\n", sblk->stat_IfInFramesL2FilterDiscards);
7514 if (sblk->stat_IfInRuleCheckerDiscards) {
7515 if_printf(ifp, " 0x%08X : IfInRuleCheckerDiscards\n",
7516 sblk->stat_IfInRuleCheckerDiscards);
7519 if (sblk->stat_IfInFTQDiscards) {
7520 if_printf(ifp, " 0x%08X : IfInFTQDiscards\n",
7521 sblk->stat_IfInFTQDiscards);
7524 if (sblk->stat_IfInMBUFDiscards) {
7525 if_printf(ifp, " 0x%08X : IfInMBUFDiscards\n",
7526 sblk->stat_IfInMBUFDiscards);
7529 if (sblk->stat_IfInRuleCheckerP4Hit) {
7530 if_printf(ifp, " 0x%08X : IfInRuleCheckerP4Hit\n",
7531 sblk->stat_IfInRuleCheckerP4Hit);
7534 if (sblk->stat_CatchupInRuleCheckerDiscards) {
7535 if_printf(ifp, " 0x%08X : "
7536 "CatchupInRuleCheckerDiscards\n",
7537 sblk->stat_CatchupInRuleCheckerDiscards);
7540 if (sblk->stat_CatchupInFTQDiscards) {
7541 if_printf(ifp, " 0x%08X : CatchupInFTQDiscards\n",
7542 sblk->stat_CatchupInFTQDiscards);
7545 if (sblk->stat_CatchupInMBUFDiscards) {
7546 if_printf(ifp, " 0x%08X : CatchupInMBUFDiscards\n",
7547 sblk->stat_CatchupInMBUFDiscards);
7550 if (sblk->stat_CatchupInRuleCheckerP4Hit) {
7551 if_printf(ifp, " 0x%08X : CatchupInRuleCheckerP4Hit\n",
7552 sblk->stat_CatchupInRuleCheckerP4Hit);
7556 "----------------------------"
7558 "----------------------------\n");
7562 /****************************************************************************/
7563 /* Prints out a summary of the driver state. */
7567 /****************************************************************************/
7569 bce_dump_driver_state(struct bce_softc *sc)
7571 struct ifnet *ifp = &sc->arpcom.ac_if;
7572 uint32_t val_hi, val_lo;
7575 "-----------------------------"
7577 "-----------------------------\n");
7579 val_hi = BCE_ADDR_HI(sc);
7580 val_lo = BCE_ADDR_LO(sc);
7581 if_printf(ifp, "0x%08X:%08X - (sc) driver softc structure "
7582 "virtual address\n", val_hi, val_lo);
7584 val_hi = BCE_ADDR_HI(sc->status_block);
7585 val_lo = BCE_ADDR_LO(sc->status_block);
7586 if_printf(ifp, "0x%08X:%08X - (sc->status_block) status block "
7587 "virtual address\n", val_hi, val_lo);
7589 val_hi = BCE_ADDR_HI(sc->stats_block);
7590 val_lo = BCE_ADDR_LO(sc->stats_block);
7591 if_printf(ifp, "0x%08X:%08X - (sc->stats_block) statistics block "
7592 "virtual address\n", val_hi, val_lo);
7594 val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
7595 val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
7596 if_printf(ifp, "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
7597 "virtual adddress\n", val_hi, val_lo);
7599 val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
7600 val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
7601 if_printf(ifp, "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
7602 "virtual address\n", val_hi, val_lo);
7604 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
7605 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
7606 if_printf(ifp, "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
7607 "virtual address\n", val_hi, val_lo);
7609 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
7610 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
7611 if_printf(ifp, "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
7612 "virtual address\n", val_hi, val_lo);
7614 if_printf(ifp, " 0x%08X - (sc->interrupts_generated) "
7615 "h/w intrs\n", sc->interrupts_generated);
7617 if_printf(ifp, " 0x%08X - (sc->rx_interrupts) "
7618 "rx interrupts handled\n", sc->rx_interrupts);
7620 if_printf(ifp, " 0x%08X - (sc->tx_interrupts) "
7621 "tx interrupts handled\n", sc->tx_interrupts);
7623 if_printf(ifp, " 0x%08X - (sc->last_status_idx) "
7624 "status block index\n", sc->last_status_idx);
7626 if_printf(ifp, " 0x%04X(0x%04X) - (sc->tx_prod) "
7627 "tx producer index\n",
7628 sc->tx_prod, (uint16_t)TX_CHAIN_IDX(sc, sc->tx_prod));
7630 if_printf(ifp, " 0x%04X(0x%04X) - (sc->tx_cons) "
7631 "tx consumer index\n",
7632 sc->tx_cons, (uint16_t)TX_CHAIN_IDX(sc, sc->tx_cons));
7634 if_printf(ifp, " 0x%08X - (sc->tx_prod_bseq) "
7635 "tx producer bseq index\n", sc->tx_prod_bseq);
7637 if_printf(ifp, " 0x%04X(0x%04X) - (sc->rx_prod) "
7638 "rx producer index\n",
7639 sc->rx_prod, (uint16_t)RX_CHAIN_IDX(sc, sc->rx_prod));
7641 if_printf(ifp, " 0x%04X(0x%04X) - (sc->rx_cons) "
7642 "rx consumer index\n",
7643 sc->rx_cons, (uint16_t)RX_CHAIN_IDX(sc, sc->rx_cons));
7645 if_printf(ifp, " 0x%08X - (sc->rx_prod_bseq) "
7646 "rx producer bseq index\n", sc->rx_prod_bseq);
7648 if_printf(ifp, " 0x%08X - (sc->rx_mbuf_alloc) "
7649 "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7651 if_printf(ifp, " 0x%08X - (sc->free_rx_bd) "
7652 "free rx_bd's\n", sc->free_rx_bd);
7654 if_printf(ifp, "0x%08X/%08X - (sc->rx_low_watermark) rx "
7655 "low watermark\n", sc->rx_low_watermark, sc->max_rx_bd);
7657 if_printf(ifp, " 0x%08X - (sc->txmbuf_alloc) "
7658 "tx mbufs allocated\n", sc->tx_mbuf_alloc);
7660 if_printf(ifp, " 0x%08X - (sc->rx_mbuf_alloc) "
7661 "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7663 if_printf(ifp, " 0x%08X - (sc->used_tx_bd) used tx_bd's\n",
7666 if_printf(ifp, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n",
7667 sc->tx_hi_watermark, sc->max_tx_bd);
7669 if_printf(ifp, " 0x%08X - (sc->mbuf_alloc_failed) "
7670 "failed mbuf alloc\n", sc->mbuf_alloc_failed);
7673 "----------------------------"
7675 "----------------------------\n");
7679 /****************************************************************************/
7680 /* Prints out the hardware state through a summary of important registers, */
7681 /* followed by a complete register dump. */
7685 /****************************************************************************/
7687 bce_dump_hw_state(struct bce_softc *sc)
7689 struct ifnet *ifp = &sc->arpcom.ac_if;
7694 "----------------------------"
7696 "----------------------------\n");
7698 if_printf(ifp, "%s - bootcode version\n", sc->bce_bc_ver);
7700 val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
7701 if_printf(ifp, "0x%08X - (0x%06X) misc_enable_status_bits\n",
7702 val1, BCE_MISC_ENABLE_STATUS_BITS);
7704 val1 = REG_RD(sc, BCE_DMA_STATUS);
7705 if_printf(ifp, "0x%08X - (0x%04X) dma_status\n", val1, BCE_DMA_STATUS);
7707 val1 = REG_RD(sc, BCE_CTX_STATUS);
7708 if_printf(ifp, "0x%08X - (0x%04X) ctx_status\n", val1, BCE_CTX_STATUS);
7710 val1 = REG_RD(sc, BCE_EMAC_STATUS);
7711 if_printf(ifp, "0x%08X - (0x%04X) emac_status\n",
7712 val1, BCE_EMAC_STATUS);
7714 val1 = REG_RD(sc, BCE_RPM_STATUS);
7715 if_printf(ifp, "0x%08X - (0x%04X) rpm_status\n", val1, BCE_RPM_STATUS);
7717 val1 = REG_RD(sc, BCE_TBDR_STATUS);
7718 if_printf(ifp, "0x%08X - (0x%04X) tbdr_status\n",
7719 val1, BCE_TBDR_STATUS);
7721 val1 = REG_RD(sc, BCE_TDMA_STATUS);
7722 if_printf(ifp, "0x%08X - (0x%04X) tdma_status\n",
7723 val1, BCE_TDMA_STATUS);
7725 val1 = REG_RD(sc, BCE_HC_STATUS);
7726 if_printf(ifp, "0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS);
7728 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7729 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7730 val1, BCE_TXP_CPU_STATE);
7732 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7733 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7734 val1, BCE_TPAT_CPU_STATE);
7736 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7737 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7738 val1, BCE_RXP_CPU_STATE);
7740 val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE);
7741 if_printf(ifp, "0x%08X - (0x%06X) com_cpu_state\n",
7742 val1, BCE_COM_CPU_STATE);
7744 val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
7745 if_printf(ifp, "0x%08X - (0x%06X) mcp_cpu_state\n",
7746 val1, BCE_MCP_CPU_STATE);
7748 val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE);
7749 if_printf(ifp, "0x%08X - (0x%06X) cp_cpu_state\n",
7750 val1, BCE_CP_CPU_STATE);
7753 "----------------------------"
7755 "----------------------------\n");
7758 "----------------------------"
7760 "----------------------------\n");
7762 for (i = 0x400; i < 0x8000; i += 0x10) {
7763 if_printf(ifp, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7765 REG_RD(sc, i + 0x4),
7766 REG_RD(sc, i + 0x8),
7767 REG_RD(sc, i + 0xc));
7771 "----------------------------"
7773 "----------------------------\n");
7777 /****************************************************************************/
7778 /* Prints out the TXP state. */
7782 /****************************************************************************/
7784 bce_dump_txp_state(struct bce_softc *sc)
7786 struct ifnet *ifp = &sc->arpcom.ac_if;
7791 "----------------------------"
7793 "----------------------------\n");
7795 val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
7796 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_mode\n",
7797 val1, BCE_TXP_CPU_MODE);
7799 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7800 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7801 val1, BCE_TXP_CPU_STATE);
7803 val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
7804 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_event_mask\n",
7805 val1, BCE_TXP_CPU_EVENT_MASK);
7808 "----------------------------"
7810 "----------------------------\n");
7812 for (i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
7813 /* Skip the big blank spaces */
7814 if (i < 0x454000 && i > 0x5ffff) {
7815 if_printf(ifp, "0x%04X: "
7816 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7818 REG_RD_IND(sc, i + 0x4),
7819 REG_RD_IND(sc, i + 0x8),
7820 REG_RD_IND(sc, i + 0xc));
7825 "----------------------------"
7827 "----------------------------\n");
7831 /****************************************************************************/
7832 /* Prints out the RXP state. */
7836 /****************************************************************************/
7838 bce_dump_rxp_state(struct bce_softc *sc)
7840 struct ifnet *ifp = &sc->arpcom.ac_if;
7845 "----------------------------"
7847 "----------------------------\n");
7849 val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
7850 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_mode\n",
7851 val1, BCE_RXP_CPU_MODE);
7853 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7854 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7855 val1, BCE_RXP_CPU_STATE);
7857 val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
7858 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_event_mask\n",
7859 val1, BCE_RXP_CPU_EVENT_MASK);
7862 "----------------------------"
7864 "----------------------------\n");
7866 for (i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
7867 /* Skip the big blank sapces */
7868 if (i < 0xc5400 && i > 0xdffff) {
7869 if_printf(ifp, "0x%04X: "
7870 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7872 REG_RD_IND(sc, i + 0x4),
7873 REG_RD_IND(sc, i + 0x8),
7874 REG_RD_IND(sc, i + 0xc));
7879 "----------------------------"
7881 "----------------------------\n");
7885 /****************************************************************************/
7886 /* Prints out the TPAT state. */
7890 /****************************************************************************/
7892 bce_dump_tpat_state(struct bce_softc *sc)
7894 struct ifnet *ifp = &sc->arpcom.ac_if;
7899 "----------------------------"
7901 "----------------------------\n");
7903 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
7904 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_mode\n",
7905 val1, BCE_TPAT_CPU_MODE);
7907 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7908 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7909 val1, BCE_TPAT_CPU_STATE);
7911 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
7912 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_event_mask\n",
7913 val1, BCE_TPAT_CPU_EVENT_MASK);
7916 "----------------------------"
7918 "----------------------------\n");
7920 for (i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
7921 /* Skip the big blank spaces */
7922 if (i < 0x854000 && i > 0x9ffff) {
7923 if_printf(ifp, "0x%04X: "
7924 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7926 REG_RD_IND(sc, i + 0x4),
7927 REG_RD_IND(sc, i + 0x8),
7928 REG_RD_IND(sc, i + 0xc));
7933 "----------------------------"
7935 "----------------------------\n");
7939 /****************************************************************************/
7940 /* Prints out the driver state and then enters the debugger. */
7944 /****************************************************************************/
7946 bce_breakpoint(struct bce_softc *sc)
7949 bce_freeze_controller(sc);
7952 bce_dump_driver_state(sc);
7953 bce_dump_status_block(sc);
7954 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD(sc));
7955 bce_dump_hw_state(sc);
7956 bce_dump_txp_state(sc);
7959 bce_unfreeze_controller(sc);
7962 /* Call the debugger. */
7966 #endif /* BCE_DEBUG */
7969 bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS)
7971 struct bce_softc *sc = arg1;
7973 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7974 &sc->bce_tx_quick_cons_trip_int,
7975 BCE_COALMASK_TX_BDS_INT);
7979 bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS)
7981 struct bce_softc *sc = arg1;
7983 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7984 &sc->bce_tx_quick_cons_trip,
7985 BCE_COALMASK_TX_BDS);
7989 bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS)
7991 struct bce_softc *sc = arg1;
7993 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7994 &sc->bce_tx_ticks_int,
7995 BCE_COALMASK_TX_TICKS_INT);
7999 bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS)
8001 struct bce_softc *sc = arg1;
8003 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
8005 BCE_COALMASK_TX_TICKS);
8009 bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS)
8011 struct bce_softc *sc = arg1;
8013 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
8014 &sc->bce_rx_quick_cons_trip_int,
8015 BCE_COALMASK_RX_BDS_INT);
8019 bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS)
8021 struct bce_softc *sc = arg1;
8023 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
8024 &sc->bce_rx_quick_cons_trip,
8025 BCE_COALMASK_RX_BDS);
8029 bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS)
8031 struct bce_softc *sc = arg1;
8033 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
8034 &sc->bce_rx_ticks_int,
8035 BCE_COALMASK_RX_TICKS_INT);
8039 bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS)
8041 struct bce_softc *sc = arg1;
8043 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
8045 BCE_COALMASK_RX_TICKS);
8049 bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS, uint32_t *coal,
8050 uint32_t coalchg_mask)
8052 struct bce_softc *sc = arg1;
8053 struct ifnet *ifp = &sc->arpcom.ac_if;
8056 lwkt_serialize_enter(ifp->if_serializer);
8059 error = sysctl_handle_int(oidp, &v, 0, req);
8060 if (!error && req->newptr != NULL) {
8065 sc->bce_coalchg_mask |= coalchg_mask;
8069 lwkt_serialize_exit(ifp->if_serializer);
8074 bce_coal_change(struct bce_softc *sc)
8076 struct ifnet *ifp = &sc->arpcom.ac_if;
8078 ASSERT_SERIALIZED(ifp->if_serializer);
8080 if ((ifp->if_flags & IFF_RUNNING) == 0) {
8081 sc->bce_coalchg_mask = 0;
8085 if (sc->bce_coalchg_mask &
8086 (BCE_COALMASK_TX_BDS | BCE_COALMASK_TX_BDS_INT)) {
8087 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
8088 (sc->bce_tx_quick_cons_trip_int << 16) |
8089 sc->bce_tx_quick_cons_trip);
8091 if_printf(ifp, "tx_bds %u, tx_bds_int %u\n",
8092 sc->bce_tx_quick_cons_trip,
8093 sc->bce_tx_quick_cons_trip_int);
8097 if (sc->bce_coalchg_mask &
8098 (BCE_COALMASK_TX_TICKS | BCE_COALMASK_TX_TICKS_INT)) {
8099 REG_WR(sc, BCE_HC_TX_TICKS,
8100 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
8102 if_printf(ifp, "tx_ticks %u, tx_ticks_int %u\n",
8103 sc->bce_tx_ticks, sc->bce_tx_ticks_int);
8107 if (sc->bce_coalchg_mask &
8108 (BCE_COALMASK_RX_BDS | BCE_COALMASK_RX_BDS_INT)) {
8109 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
8110 (sc->bce_rx_quick_cons_trip_int << 16) |
8111 sc->bce_rx_quick_cons_trip);
8113 if_printf(ifp, "rx_bds %u, rx_bds_int %u\n",
8114 sc->bce_rx_quick_cons_trip,
8115 sc->bce_rx_quick_cons_trip_int);
8119 if (sc->bce_coalchg_mask &
8120 (BCE_COALMASK_RX_TICKS | BCE_COALMASK_RX_TICKS_INT)) {
8121 REG_WR(sc, BCE_HC_RX_TICKS,
8122 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
8124 if_printf(ifp, "rx_ticks %u, rx_ticks_int %u\n",
8125 sc->bce_rx_ticks, sc->bce_rx_ticks_int);
8129 sc->bce_coalchg_mask = 0;