2 * Copyright (c) 1997, 1998, 1999, 2000
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $
33 * $FreeBSD: src/sys/pci/if_sk.c,v 1.19.2.9 2003/03/05 18:42:34 njl Exp $
34 * $DragonFly: src/sys/dev/netif/sk/if_sk.c,v 1.41 2005/11/29 19:56:55 dillon Exp $
38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
40 * Permission to use, copy, modify, and distribute this software for any
41 * purpose with or without fee is hereby granted, provided that the above
42 * copyright notice and this permission notice appear in all copies.
44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
55 * the SK-984x series adapters, both single port and dual port.
57 * The XaQti XMAC II datasheet,
58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
59 * The SysKonnect GEnesis manual, http://www.syskonnect.com
61 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the
62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
63 * convenience to others until Vitesse corrects this problem:
65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
67 * Written by Bill Paul <wpaul@ee.columbia.edu>
68 * Department of Electrical Engineering
69 * Columbia University, New York City
73 * The SysKonnect gigabit ethernet adapters consist of two main
74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
76 * components and a PHY while the GEnesis controller provides a PCI
77 * interface with DMA support. Each card may have between 512K and
78 * 2MB of SRAM on board depending on the configuration.
80 * The SysKonnect GEnesis controller can have either one or two XMAC
81 * chips connected to it, allowing single or dual port NIC configurations.
82 * SysKonnect has the distinction of being the only vendor on the market
83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
85 * XMAC registers. This driver takes advantage of these features to allow
86 * both XMACs to operate as independent interfaces.
89 #include <sys/param.h>
90 #include <sys/systm.h>
91 #include <sys/sockio.h>
93 #include <sys/malloc.h>
94 #include <sys/kernel.h>
95 #include <sys/socket.h>
96 #include <sys/queue.h>
97 #include <sys/serialize.h>
98 #include <sys/thread2.h>
101 #include <net/ifq_var.h>
102 #include <net/if_arp.h>
103 #include <net/ethernet.h>
104 #include <net/if_dl.h>
105 #include <net/if_media.h>
109 #include <vm/vm.h> /* for vtophys */
110 #include <vm/pmap.h> /* for vtophys */
111 #include <machine/bus.h>
112 #include <machine/resource.h>
114 #include <sys/rman.h>
116 #include <dev/netif/mii_layer/mii.h>
117 #include <dev/netif/mii_layer/miivar.h>
118 #include <dev/netif/mii_layer/brgphyreg.h>
120 #include <bus/pci/pcireg.h>
121 #include <bus/pci/pcivar.h>
124 #define SK_USEIOSPACE
127 #include "if_skreg.h"
128 #include "xmaciireg.h"
129 #include "yukonreg.h"
131 /* "controller miibus0" required. See GENERIC if you get errors here. */
132 #include "miibus_if.h"
134 static struct sk_type sk_devs[] = {
135 { VENDORID_SK, DEVICEID_SK_V1,
136 "SysKonnect Gigabit Ethernet (V1.0)" },
137 { VENDORID_SK, DEVICEID_SK_V2,
138 "SysKonnect Gigabit Ethernet (V2.0)" },
139 { VENDORID_MARVELL, DEVICEID_SK_V2,
140 "Marvell Gigabit Ethernet" },
141 { VENDORID_3COM, DEVICEID_3COM_3C940,
142 "3Com 3C940 Gigabit Ethernet" },
143 { VENDORID_LINKSYS, DEVICEID_LINKSYS_EG1032,
144 "Linksys EG1032 Gigabit Ethernet" },
145 { VENDORID_DLINK, DEVICEID_DLINK_DGE530T,
146 "D-Link DGE-530T Gigabit Ethernet" },
150 static int skc_probe(device_t);
151 static int skc_attach(device_t);
152 static int skc_detach(device_t);
153 static void skc_shutdown(device_t);
154 static int sk_probe(device_t);
155 static int sk_attach(device_t);
156 static int sk_detach(device_t);
157 static void sk_tick(void *);
158 static void sk_intr(void *);
159 static void sk_intr_bcom(struct sk_if_softc *);
160 static void sk_intr_xmac(struct sk_if_softc *);
161 static void sk_intr_yukon(struct sk_if_softc *);
162 static void sk_rxeof(struct sk_if_softc *);
163 static void sk_txeof(struct sk_if_softc *);
164 static int sk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *);
165 static void sk_start(struct ifnet *);
166 static int sk_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
167 static void sk_init(void *);
168 static void sk_init_xmac(struct sk_if_softc *);
169 static void sk_init_yukon(struct sk_if_softc *);
170 static void sk_stop(struct sk_if_softc *);
171 static void sk_watchdog(struct ifnet *);
172 static int sk_ifmedia_upd(struct ifnet *);
173 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
174 static void sk_reset(struct sk_softc *);
175 static int sk_newbuf(struct sk_if_softc *, struct sk_chain *,
177 static int sk_alloc_jumbo_mem(struct sk_if_softc *);
178 static struct sk_jslot
179 *sk_jalloc(struct sk_if_softc *);
180 static void sk_jfree(void *);
181 static void sk_jref(void *);
182 static int sk_init_rx_ring(struct sk_if_softc *);
183 static void sk_init_tx_ring(struct sk_if_softc *);
184 static uint32_t sk_win_read_4(struct sk_softc *, int);
185 static uint16_t sk_win_read_2(struct sk_softc *, int);
186 static uint8_t sk_win_read_1(struct sk_softc *, int);
187 static void sk_win_write_4(struct sk_softc *, int, uint32_t);
188 static void sk_win_write_2(struct sk_softc *, int, uint32_t);
189 static void sk_win_write_1(struct sk_softc *, int, uint32_t);
190 static uint8_t sk_vpd_readbyte(struct sk_softc *, int);
191 static void sk_vpd_read_res(struct sk_softc *, struct vpd_res *, int);
192 static void sk_vpd_read(struct sk_softc *);
194 static int sk_miibus_readreg(device_t, int, int);
195 static int sk_miibus_writereg(device_t, int, int, int);
196 static void sk_miibus_statchg(device_t);
198 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
199 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, int);
200 static void sk_xmac_miibus_statchg(struct sk_if_softc *);
202 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
203 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, int);
204 static void sk_marv_miibus_statchg(struct sk_if_softc *);
206 static void sk_setfilt(struct sk_if_softc *, caddr_t, int);
207 static void sk_setmulti(struct sk_if_softc *);
208 static void sk_setpromisc(struct sk_if_softc *);
211 #define SK_RES SYS_RES_IOPORT
212 #define SK_RID SK_PCI_LOIO
214 #define SK_RES SYS_RES_MEMORY
215 #define SK_RID SK_PCI_LOMEM
219 * Note that we have newbus methods for both the GEnesis controller
220 * itself and the XMAC(s). The XMACs are children of the GEnesis, and
221 * the miibus code is a child of the XMACs. We need to do it this way
222 * so that the miibus drivers can access the PHY registers on the
223 * right PHY. It's not quite what I had in mind, but it's the only
224 * design that achieves the desired effect.
226 static device_method_t skc_methods[] = {
227 /* Device interface */
228 DEVMETHOD(device_probe, skc_probe),
229 DEVMETHOD(device_attach, skc_attach),
230 DEVMETHOD(device_detach, skc_detach),
231 DEVMETHOD(device_shutdown, skc_shutdown),
234 DEVMETHOD(bus_print_child, bus_generic_print_child),
235 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
240 static DEFINE_CLASS_0(skc, skc_driver, skc_methods, sizeof(struct sk_softc));
241 static devclass_t skc_devclass;
243 static device_method_t sk_methods[] = {
244 /* Device interface */
245 DEVMETHOD(device_probe, sk_probe),
246 DEVMETHOD(device_attach, sk_attach),
247 DEVMETHOD(device_detach, sk_detach),
248 DEVMETHOD(device_shutdown, bus_generic_shutdown),
251 DEVMETHOD(bus_print_child, bus_generic_print_child),
252 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
255 DEVMETHOD(miibus_readreg, sk_miibus_readreg),
256 DEVMETHOD(miibus_writereg, sk_miibus_writereg),
257 DEVMETHOD(miibus_statchg, sk_miibus_statchg),
262 static DEFINE_CLASS_0(sk, sk_driver, sk_methods, sizeof(struct sk_if_softc));
263 static devclass_t sk_devclass;
264 static struct lwkt_serialize sk_serializer;
266 DECLARE_DUMMY_MODULE(if_sk);
267 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0);
268 DRIVER_MODULE(if_sk, skc, sk_driver, sk_devclass, 0, 0);
269 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0);
271 #define SK_SETBIT(sc, reg, x) \
272 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
274 #define SK_CLRBIT(sc, reg, x) \
275 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
277 #define SK_WIN_SETBIT_4(sc, reg, x) \
278 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
280 #define SK_WIN_CLRBIT_4(sc, reg, x) \
281 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
283 #define SK_WIN_SETBIT_2(sc, reg, x) \
284 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
286 #define SK_WIN_CLRBIT_2(sc, reg, x) \
287 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
290 sk_win_read_4(struct sk_softc *sc, int reg)
293 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
294 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
296 return(CSR_READ_4(sc, reg));
301 sk_win_read_2(struct sk_softc *sc, int reg)
304 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
305 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
307 return(CSR_READ_2(sc, reg));
312 sk_win_read_1(struct sk_softc *sc, int reg)
315 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
316 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
318 return(CSR_READ_1(sc, reg));
323 sk_win_write_4(struct sk_softc *sc, int reg, uint32_t val)
326 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
327 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
329 CSR_WRITE_4(sc, reg, val);
334 sk_win_write_2(struct sk_softc *sc, int reg, uint32_t val)
337 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
338 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
340 CSR_WRITE_2(sc, reg, val);
345 sk_win_write_1(struct sk_softc *sc, int reg, uint32_t val)
348 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
349 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
351 CSR_WRITE_1(sc, reg, val);
356 * The VPD EEPROM contains Vital Product Data, as suggested in
357 * the PCI 2.1 specification. The VPD data is separared into areas
358 * denoted by resource IDs. The SysKonnect VPD contains an ID string
359 * resource (the name of the adapter), a read-only area resource
360 * containing various key/data fields and a read/write area which
361 * can be used to store asset management information or log messages.
362 * We read the ID string and read-only into buffers attached to
363 * the controller softc structure for later use. At the moment,
364 * we only use the ID string during sk_attach().
367 sk_vpd_readbyte(struct sk_softc *sc, int addr)
371 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr);
372 for (i = 0; i < SK_TIMEOUT; i++) {
374 if (sk_win_read_2(sc,
375 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG)
382 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)));
386 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr)
391 ptr = (uint8_t *)res;
392 for (i = 0; i < sizeof(struct vpd_res); i++)
393 ptr[i] = sk_vpd_readbyte(sc, i + addr);
397 sk_vpd_read(struct sk_softc *sc)
402 if (sc->sk_vpd_prodname != NULL)
403 free(sc->sk_vpd_prodname, M_DEVBUF);
404 if (sc->sk_vpd_readonly != NULL)
405 free(sc->sk_vpd_readonly, M_DEVBUF);
406 sc->sk_vpd_prodname = NULL;
407 sc->sk_vpd_readonly = NULL;
409 sk_vpd_read_res(sc, &res, pos);
411 if (res.vr_id != VPD_RES_ID) {
412 printf("skc%d: bad VPD resource id: expected %x got %x\n",
413 sc->sk_unit, VPD_RES_ID, res.vr_id);
418 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT);
419 for (i = 0; i < res.vr_len; i++)
420 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos);
421 sc->sk_vpd_prodname[i] = '\0';
424 sk_vpd_read_res(sc, &res, pos);
426 if (res.vr_id != VPD_RES_READ) {
427 printf("skc%d: bad VPD resource id: expected %x got %x\n",
428 sc->sk_unit, VPD_RES_READ, res.vr_id);
433 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_INTWAIT);
434 for (i = 0; i < res.vr_len + 1; i++)
435 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos);
439 sk_miibus_readreg(device_t dev, int phy, int reg)
441 struct sk_if_softc *sc_if = device_get_softc(dev);
443 switch(sc_if->sk_softc->sk_type) {
445 return(sk_xmac_miibus_readreg(sc_if, phy, reg));
447 return(sk_marv_miibus_readreg(sc_if, phy, reg));
454 sk_miibus_writereg(device_t dev, int phy, int reg, int val)
456 struct sk_if_softc *sc_if = device_get_softc(dev);
458 switch(sc_if->sk_softc->sk_type) {
460 return(sk_xmac_miibus_writereg(sc_if, phy, reg, val));
462 return(sk_marv_miibus_writereg(sc_if, phy, reg, val));
469 sk_miibus_statchg(device_t dev)
471 struct sk_if_softc *sc_if = device_get_softc(dev);
473 switch(sc_if->sk_softc->sk_type) {
475 sk_xmac_miibus_statchg(sc_if);
478 sk_marv_miibus_statchg(sc_if);
484 sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
488 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
491 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
492 SK_XM_READ_2(sc_if, XM_PHY_DATA);
493 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
494 for (i = 0; i < SK_TIMEOUT; i++) {
496 if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
497 XM_MMUCMD_PHYDATARDY)
501 if (i == SK_TIMEOUT) {
502 printf("sk%d: phy failed to come ready\n",
508 return(SK_XM_READ_2(sc_if, XM_PHY_DATA));
512 sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
516 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
517 for (i = 0; i < SK_TIMEOUT; i++) {
518 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0)
522 if (i == SK_TIMEOUT) {
523 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit);
527 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
528 for (i = 0; i < SK_TIMEOUT; i++) {
530 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0)
535 printf("sk%d: phy write timed out\n", sc_if->sk_unit);
541 sk_xmac_miibus_statchg(struct sk_if_softc *sc_if)
543 struct mii_data *mii;
545 mii = device_get_softc(sc_if->sk_miibus);
548 * If this is a GMII PHY, manually set the XMAC's
549 * duplex mode accordingly.
551 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
552 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
553 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
555 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
560 sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
566 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
567 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
571 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
572 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
574 for (i = 0; i < SK_TIMEOUT; i++) {
576 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
577 if (val & YU_SMICR_READ_VALID)
581 if (i == SK_TIMEOUT) {
582 printf("sk%d: phy failed to come ready\n",
587 val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
593 sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
597 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
598 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
599 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
601 for (i = 0; i < SK_TIMEOUT; i++) {
603 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)
611 sk_marv_miibus_statchg(struct sk_if_softc *sc_if)
617 static void sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot)
621 base = XM_RXFILT_ENTRY(slot);
623 SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0]));
624 SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2]));
625 SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4]));
629 sk_setmulti(struct sk_if_softc *sc_if)
631 struct sk_softc *sc = sc_if->sk_softc;
632 struct ifnet *ifp = &sc_if->arpcom.ac_if;
633 uint32_t hashes[2] = { 0, 0 };
635 struct ifmultiaddr *ifma;
636 uint8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
638 /* First, zot all the existing filters. */
639 switch(sc->sk_type) {
641 for (i = 1; i < XM_RXFILT_MAX; i++)
642 sk_setfilt(sc_if, (caddr_t)&dummy, i);
644 SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
645 SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
648 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
649 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
650 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
651 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
655 /* Now program new ones. */
656 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
657 hashes[0] = 0xFFFFFFFF;
658 hashes[1] = 0xFFFFFFFF;
661 /* First find the tail of the list. */
662 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
663 if (ifma->ifma_link.le_next == NULL)
666 /* Now traverse the list backwards. */
667 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
668 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
669 if (ifma->ifma_addr->sa_family != AF_LINK)
672 * Program the first XM_RXFILT_MAX multicast groups
673 * into the perfect filter. For all others,
674 * use the hash table.
676 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) {
678 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
683 switch(sc->sk_type) {
685 h = ~ether_crc32_le(LLADDR((struct sockaddr_dl *)
686 ifma->ifma_addr), ETHER_ADDR_LEN) &
687 ((1 << HASH_BITS) -1 );
689 hashes[0] |= (1 << h);
691 hashes[1] |= (1 << (h - 32));
695 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
696 ifma->ifma_addr), ETHER_ADDR_LEN) &
697 ((1 << HASH_BITS) -1 );
699 hashes[0] |= (1 << h);
701 hashes[1] |= (1 << (h - 32));
707 switch(sc->sk_type) {
709 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH|
710 XM_MODE_RX_USE_PERFECT);
711 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
712 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
715 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
716 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
717 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
718 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
724 sk_setpromisc(struct sk_if_softc *sc_if)
726 struct sk_softc *sc = sc_if->sk_softc;
727 struct ifnet *ifp = &sc_if->arpcom.ac_if;
729 switch(sc->sk_type) {
731 if (ifp->if_flags & IFF_PROMISC) {
732 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
734 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
738 if (ifp->if_flags & IFF_PROMISC) {
739 SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
740 YU_RCR_UFLEN | YU_RCR_MUFLEN);
742 SK_YU_SETBIT_2(sc_if, YUKON_RCR,
743 YU_RCR_UFLEN | YU_RCR_MUFLEN);
750 sk_init_rx_ring(struct sk_if_softc *sc_if)
752 struct sk_chain_data *cd = &sc_if->sk_cdata;
753 struct sk_ring_data *rd = sc_if->sk_rdata;
756 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
758 for (i = 0; i < SK_RX_RING_CNT; i++) {
759 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i];
760 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS)
762 if (i == (SK_RX_RING_CNT - 1)) {
763 cd->sk_rx_chain[i].sk_next =
765 rd->sk_rx_ring[i].sk_next =
766 vtophys(&rd->sk_rx_ring[0]);
768 cd->sk_rx_chain[i].sk_next =
769 &cd->sk_rx_chain[i + 1];
770 rd->sk_rx_ring[i].sk_next =
771 vtophys(&rd->sk_rx_ring[i + 1]);
775 sc_if->sk_cdata.sk_rx_prod = 0;
776 sc_if->sk_cdata.sk_rx_cons = 0;
782 sk_init_tx_ring(struct sk_if_softc *sc_if)
784 struct sk_chain_data *cd = &sc_if->sk_cdata;
785 struct sk_ring_data *rd = sc_if->sk_rdata;
788 bzero(sc_if->sk_rdata->sk_tx_ring,
789 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
791 for (i = 0; i < SK_TX_RING_CNT; i++) {
792 nexti = (i == (SK_TX_RING_CNT - 1)) ? 0 : i + 1;
793 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i];
794 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti];
795 rd->sk_tx_ring[i].sk_next = vtophys(&rd->sk_tx_ring[nexti]);
798 sc_if->sk_cdata.sk_tx_prod = 0;
799 sc_if->sk_cdata.sk_tx_cons = 0;
800 sc_if->sk_cdata.sk_tx_cnt = 0;
804 sk_newbuf(struct sk_if_softc *sc_if, struct sk_chain *c, struct mbuf *m)
806 struct mbuf *m_new = NULL;
807 struct sk_rx_desc *r;
808 struct sk_jslot *buf;
811 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
815 /* Allocate the jumbo buffer */
816 buf = sk_jalloc(sc_if);
820 printf("sk%d: jumbo allocation failed "
821 "-- packet dropped!\n", sc_if->sk_unit);
826 /* Attach the buffer to the mbuf */
827 m_new->m_ext.ext_arg = buf;
828 m_new->m_ext.ext_buf = buf->sk_buf;
829 m_new->m_ext.ext_free = sk_jfree;
830 m_new->m_ext.ext_ref = sk_jref;
831 m_new->m_ext.ext_size = SK_JUMBO_FRAMELEN;
833 m_new->m_data = m_new->m_ext.ext_buf;
834 m_new->m_flags |= M_EXT;
835 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
838 * We're re-using a previously allocated mbuf;
839 * be sure to re-init pointers and lengths to
843 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN;
844 m_new->m_data = m_new->m_ext.ext_buf;
848 * Adjust alignment so packet payload begins on a
849 * longword boundary. Mandatory for Alpha, useful on
852 m_adj(m_new, ETHER_ALIGN);
856 r->sk_data_lo = vtophys(mtod(m_new, caddr_t));
857 r->sk_ctl = m_new->m_len | SK_RXSTAT;
863 * Allocate jumbo buffer storage. The SysKonnect adapters support
864 * "jumbograms" (9K frames), although SysKonnect doesn't currently
865 * use them in their drivers. In order for us to use them, we need
866 * large 9K receive buffers, however standard mbuf clusters are only
867 * 2048 bytes in size. Consequently, we need to allocate and manage
868 * our own jumbo buffer pool. Fortunately, this does not require an
869 * excessive amount of additional code.
872 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if)
876 struct sk_jslot *entry;
878 /* Grab a big chunk o' storage. */
879 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF,
880 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
882 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) {
883 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit);
887 SLIST_INIT(&sc_if->sk_jfree_listhead);
890 * Now divide it up into 9K pieces and save the addresses
891 * in an array. Note that we play an evil trick here by using
892 * the first few bytes in the buffer to hold the the address
893 * of the softc structure for this interface. This is because
894 * sk_jfree() needs it, but it is called by the mbuf management
895 * code which will not pass it to us explicitly.
897 ptr = sc_if->sk_cdata.sk_jumbo_buf;
898 for (i = 0; i < SK_JSLOTS; i++) {
899 entry = &sc_if->sk_cdata.sk_jslots[i];
900 entry->sk_sc = sc_if;
904 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jslot_link);
912 * Allocate a jumbo buffer.
914 static struct sk_jslot *
915 sk_jalloc(struct sk_if_softc *sc_if)
917 struct sk_jslot *entry;
919 lwkt_serialize_enter(&sc_if->sk_jslot_serializer);
920 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead);
922 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jslot_link);
926 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit);
929 lwkt_serialize_exit(&sc_if->sk_jslot_serializer);
934 * Adjust usage count on a jumbo buffer. In general this doesn't
935 * get used much because our jumbo buffers don't get passed around
936 * a lot, but it's implemented for correctness.
941 struct sk_jslot *entry = (struct sk_jslot *)arg;
942 struct sk_if_softc *sc = entry->sk_sc;
945 panic("sk_jref: can't find softc pointer!");
947 if (&sc->sk_cdata.sk_jslots[entry->sk_slot] != entry)
948 panic("sk_jref: asked to reference buffer "
949 "that we don't manage!");
950 if (entry->sk_inuse == 0)
951 panic("sk_jref: buffer already free!");
952 atomic_add_int(&entry->sk_inuse, 1);
956 * Release a jumbo buffer.
961 struct sk_jslot *entry = (struct sk_jslot *)arg;
962 struct sk_if_softc *sc = entry->sk_sc;
965 panic("sk_jref: can't find softc pointer!");
967 if (&sc->sk_cdata.sk_jslots[entry->sk_slot] != entry)
968 panic("sk_jref: asked to reference buffer "
969 "that we don't manage!");
970 if (entry->sk_inuse == 0)
971 panic("sk_jref: buffer already free!");
972 lwkt_serialize_enter(&sc->sk_jslot_serializer);
973 atomic_subtract_int(&entry->sk_inuse, 1);
974 if (entry->sk_inuse == 0)
975 SLIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jslot_link);
976 lwkt_serialize_exit(&sc->sk_jslot_serializer);
983 sk_ifmedia_upd(struct ifnet *ifp)
985 struct sk_if_softc *sc_if = ifp->if_softc;
986 struct mii_data *mii;
988 mii = device_get_softc(sc_if->sk_miibus);
996 * Report current media status.
999 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1001 struct sk_if_softc *sc_if;
1002 struct mii_data *mii;
1004 sc_if = ifp->if_softc;
1005 mii = device_get_softc(sc_if->sk_miibus);
1008 ifmr->ifm_active = mii->mii_media_active;
1009 ifmr->ifm_status = mii->mii_media_status;
1013 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1015 struct sk_if_softc *sc_if = ifp->if_softc;
1016 struct ifreq *ifr = (struct ifreq *)data;
1017 struct mii_data *mii;
1024 if (ifr->ifr_mtu > SK_JUMBO_MTU)
1027 ifp->if_mtu = ifr->ifr_mtu;
1032 if (ifp->if_flags & IFF_UP) {
1033 if (ifp->if_flags & IFF_RUNNING) {
1034 if ((ifp->if_flags ^ sc_if->sk_if_flags)
1036 sk_setpromisc(sc_if);
1042 if (ifp->if_flags & IFF_RUNNING)
1045 sc_if->sk_if_flags = ifp->if_flags;
1055 mii = device_get_softc(sc_if->sk_miibus);
1056 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1059 error = ether_ioctl(ifp, command, data);
1069 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1070 * IDs against our list and return a device name if we find a match.
1073 skc_probe(device_t dev)
1076 uint16_t vendor, product;
1078 lwkt_serialize_init(&sk_serializer);
1079 vendor = pci_get_vendor(dev);
1080 product = pci_get_device(dev);
1082 for (t = sk_devs; t->sk_name != NULL; t++) {
1083 if (vendor == t->sk_vid && product == t->sk_did) {
1084 device_set_desc(dev, t->sk_name);
1093 * Force the GEnesis into reset, then bring it out of reset.
1096 sk_reset(struct sk_softc *sc)
1098 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1099 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1100 if (sc->sk_type == SK_YUKON)
1101 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1104 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1106 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1107 if (sc->sk_type == SK_YUKON)
1108 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1110 if (sc->sk_type == SK_GENESIS) {
1111 /* Configure packet arbiter */
1112 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1113 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1114 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1115 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1116 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1119 /* Enable RAM interface */
1120 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1123 * Configure interrupt moderation. The moderation timer
1124 * defers interrupts specified in the interrupt moderation
1125 * timer mask based on the timeout specified in the interrupt
1126 * moderation timer init register. Each bit in the timer
1127 * register represents 18.825ns, so to specify a timeout in
1128 * microseconds, we have to multiply by 54.
1130 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200));
1131 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1132 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1133 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1137 sk_probe(device_t dev)
1139 struct sk_softc *sc = device_get_softc(device_get_parent(dev));
1142 * Not much to do here. We always know there will be
1143 * at least one XMAC present, and if there are two,
1144 * skc_attach() will create a second device instance
1147 switch (sc->sk_type) {
1149 device_set_desc(dev, "XaQti Corp. XMAC II");
1152 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
1160 * Each XMAC chip is attached as a separate logical IP interface.
1161 * Single port cards will have only one logical interface of course.
1164 sk_attach(device_t dev)
1166 struct sk_softc *sc = device_get_softc(device_get_parent(dev));
1167 struct sk_if_softc *sc_if = device_get_softc(dev);
1171 port = *(int *)device_get_ivars(dev);
1172 free(device_get_ivars(dev), M_DEVBUF);
1173 device_set_ivars(dev, NULL);
1174 sc_if->sk_dev = dev;
1175 callout_init(&sc_if->sk_tick_timer);
1176 lwkt_serialize_init(&sc_if->sk_jslot_serializer);
1178 sc_if->sk_dev = dev;
1179 sc_if->sk_unit = device_get_unit(dev);
1180 sc_if->sk_port = port;
1181 sc_if->sk_softc = sc;
1182 sc->sk_if[port] = sc_if;
1183 if (port == SK_PORT_A)
1184 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1185 if (port == SK_PORT_B)
1186 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1189 * Get station address for this interface. Note that
1190 * dual port cards actually come with three station
1191 * addresses: one for each port, plus an extra. The
1192 * extra one is used by the SysKonnect driver software
1193 * as a 'virtual' station address for when both ports
1194 * are operating in failover mode. Currently we don't
1195 * use this extra address.
1197 for (i = 0; i < ETHER_ADDR_LEN; i++)
1198 sc_if->arpcom.ac_enaddr[i] =
1199 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1202 * Set up RAM buffer addresses. The NIC will have a certain
1203 * amount of SRAM on it, somewhere between 512K and 2MB. We
1204 * need to divide this up a) between the transmitter and
1205 * receiver and b) between the two XMACs, if this is a
1206 * dual port NIC. Our algotithm is to divide up the memory
1207 * evenly so that everyone gets a fair share.
1209 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1210 uint32_t chunk, val;
1212 chunk = sc->sk_ramsize / 2;
1213 val = sc->sk_rboff / sizeof(uint64_t);
1214 sc_if->sk_rx_ramstart = val;
1215 val += (chunk / sizeof(uint64_t));
1216 sc_if->sk_rx_ramend = val - 1;
1217 sc_if->sk_tx_ramstart = val;
1218 val += (chunk / sizeof(uint64_t));
1219 sc_if->sk_tx_ramend = val - 1;
1221 uint32_t chunk, val;
1223 chunk = sc->sk_ramsize / 4;
1224 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1226 sc_if->sk_rx_ramstart = val;
1227 val += (chunk / sizeof(uint64_t));
1228 sc_if->sk_rx_ramend = val - 1;
1229 sc_if->sk_tx_ramstart = val;
1230 val += (chunk / sizeof(uint64_t));
1231 sc_if->sk_tx_ramend = val - 1;
1234 /* Read and save PHY type and set PHY address */
1235 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1236 switch(sc_if->sk_phytype) {
1237 case SK_PHYTYPE_XMAC:
1238 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1240 case SK_PHYTYPE_BCOM:
1241 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1243 case SK_PHYTYPE_MARV_COPPER:
1244 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1247 printf("skc%d: unsupported PHY type: %d\n",
1248 sc->sk_unit, sc_if->sk_phytype);
1252 /* Allocate the descriptor queues. */
1253 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF,
1254 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1256 if (sc_if->sk_rdata == NULL) {
1257 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit);
1258 sc->sk_if[port] = NULL;
1262 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data));
1264 /* Try to allocate memory for jumbo buffers. */
1265 if (sk_alloc_jumbo_mem(sc_if)) {
1266 printf("sk%d: jumbo buffer allocation failed\n",
1268 contigfree(sc_if->sk_rdata,
1269 sizeof(struct sk_ring_data), M_DEVBUF);
1270 sc->sk_if[port] = NULL;
1274 ifp = &sc_if->arpcom.ac_if;
1275 ifp->if_softc = sc_if;
1276 if_initname(ifp, "sk", sc_if->sk_unit);
1277 ifp->if_mtu = ETHERMTU;
1278 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1279 ifp->if_ioctl = sk_ioctl;
1280 ifp->if_start = sk_start;
1281 ifp->if_watchdog = sk_watchdog;
1282 ifp->if_init = sk_init;
1283 ifp->if_baudrate = 1000000000;
1284 ifq_set_maxlen(&ifp->if_snd, SK_TX_RING_CNT - 1);
1285 ifq_set_ready(&ifp->if_snd);
1290 switch (sc->sk_type) {
1292 sk_init_xmac(sc_if);
1295 sk_init_yukon(sc_if);
1299 if (mii_phy_probe(dev, &sc_if->sk_miibus,
1300 sk_ifmedia_upd, sk_ifmedia_sts)) {
1301 printf("skc%d: no PHY found!\n", sc_if->sk_unit);
1302 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM,
1304 contigfree(sc_if->sk_rdata,
1305 sizeof(struct sk_ring_data), M_DEVBUF);
1310 * Call MI attach routine.
1312 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr, &sk_serializer);
1313 callout_init(&sc_if->sk_tick_timer);
1319 * Attach the interface. Allocate softc structures, do ifmedia
1320 * setup and ethernet/BPF attach.
1323 skc_attach(device_t dev)
1325 struct sk_softc *sc;
1326 int error = 0, *port, rid, unit;
1332 sc = device_get_softc(dev);
1333 unit = device_get_unit(dev);
1334 switch (pci_get_device(dev)) {
1335 case DEVICEID_SK_V1:
1336 sc->sk_type = SK_GENESIS;
1338 case DEVICEID_SK_V2:
1339 case DEVICEID_3COM_3C940:
1340 case DEVICEID_LINKSYS_EG1032:
1341 case DEVICEID_DLINK_DGE530T:
1342 sc->sk_type = SK_YUKON;
1347 * Handle power management nonsense.
1349 command = pci_read_config(dev, SK_PCI_CAPID, 4) & 0x000000FF;
1350 if (command == 0x01) {
1351 command = pci_read_config(dev, SK_PCI_PWRMGMTCTRL, 4);
1352 if (command & SK_PSTATE_MASK) {
1353 uint32_t iobase, membase, irq;
1355 /* Save important PCI config data. */
1356 iobase = pci_read_config(dev, SK_PCI_LOIO, 4);
1357 membase = pci_read_config(dev, SK_PCI_LOMEM, 4);
1358 irq = pci_read_config(dev, SK_PCI_INTLINE, 4);
1360 /* Reset the power state. */
1361 printf("skc%d: chip is in D%d power mode "
1362 "-- setting to D0\n", unit, command & SK_PSTATE_MASK);
1363 command &= 0xFFFFFFFC;
1364 pci_write_config(dev, SK_PCI_PWRMGMTCTRL, command, 4);
1366 /* Restore PCI config data. */
1367 pci_write_config(dev, SK_PCI_LOIO, iobase, 4);
1368 pci_write_config(dev, SK_PCI_LOMEM, membase, 4);
1369 pci_write_config(dev, SK_PCI_INTLINE, irq, 4);
1374 * Map control/status registers.
1376 command = pci_read_config(dev, PCIR_COMMAND, 4);
1377 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1378 pci_write_config(dev, PCIR_COMMAND, command, 4);
1379 command = pci_read_config(dev, PCIR_COMMAND, 4);
1381 #ifdef SK_USEIOSPACE
1382 if ((command & PCIM_CMD_PORTEN) == 0) {
1383 printf("skc%d: failed to enable I/O ports!\n", unit);
1388 if ((command & PCIM_CMD_MEMEN) == 0) {
1389 printf("skc%d: failed to enable memory mapping!\n", unit);
1396 sc->sk_res = bus_alloc_resource_any(dev, SK_RES, &rid, RF_ACTIVE);
1398 if (sc->sk_res == NULL) {
1399 printf("sk%d: couldn't map ports/memory\n", unit);
1404 sc->sk_btag = rman_get_bustag(sc->sk_res);
1405 sc->sk_bhandle = rman_get_bushandle(sc->sk_res);
1407 /* Allocate interrupt */
1409 sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1410 RF_SHAREABLE | RF_ACTIVE);
1412 if (sc->sk_irq == NULL) {
1413 printf("skc%d: couldn't map interrupt\n", unit);
1414 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1419 error = bus_setup_intr(dev, sc->sk_irq, INTR_NETSAFE,
1421 &sc->sk_intrhand, &sk_serializer);
1424 printf("skc%d: couldn't set up irq\n", unit);
1425 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1426 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1430 /* Reset the adapter. */
1435 /* Read and save vital product data from EEPROM. */
1438 skrs = sk_win_read_1(sc, SK_EPROM0);
1439 if (sc->sk_type == SK_GENESIS) {
1440 /* Read and save RAM size and RAMbuffer offset */
1442 case SK_RAMSIZE_512K_64:
1443 sc->sk_ramsize = 0x80000;
1444 sc->sk_rboff = SK_RBOFF_0;
1446 case SK_RAMSIZE_1024K_64:
1447 sc->sk_ramsize = 0x100000;
1448 sc->sk_rboff = SK_RBOFF_80000;
1450 case SK_RAMSIZE_1024K_128:
1451 sc->sk_ramsize = 0x100000;
1452 sc->sk_rboff = SK_RBOFF_0;
1454 case SK_RAMSIZE_2048K_128:
1455 sc->sk_ramsize = 0x200000;
1456 sc->sk_rboff = SK_RBOFF_0;
1459 printf("skc%d: unknown ram size: %d\n",
1460 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0));
1461 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1462 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1463 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1468 } else { /* SK_YUKON */
1470 sc->sk_ramsize = 0x20000;
1472 sc->sk_ramsize = skrs * (1<<12);
1474 sc->sk_rboff = SK_RBOFF_0;
1477 /* Read and save physical media type */
1478 switch(sk_win_read_1(sc, SK_PMDTYPE)) {
1479 case SK_PMD_1000BASESX:
1480 sc->sk_pmd = IFM_1000_SX;
1482 case SK_PMD_1000BASELX:
1483 sc->sk_pmd = IFM_1000_LX;
1485 case SK_PMD_1000BASECX:
1486 sc->sk_pmd = IFM_1000_CX;
1488 case SK_PMD_1000BASETX:
1489 sc->sk_pmd = IFM_1000_T;
1492 printf("skc%d: unknown media type: 0x%x\n",
1493 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE));
1494 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1495 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1496 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1501 /* Announce the product name. */
1502 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname);
1503 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1504 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK);
1506 device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1508 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1509 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1510 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK);
1512 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1515 /* Turn on the 'driver is loaded' LED. */
1516 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1518 bus_generic_attach(dev);
1526 sk_detach(device_t dev)
1528 struct sk_if_softc *sc_if = device_get_softc(dev);
1529 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1531 lwkt_serialize_enter(&sk_serializer);
1534 ether_ifdetach(ifp);
1535 bus_generic_detach(dev);
1536 if (sc_if->sk_miibus != NULL)
1537 device_delete_child(dev, sc_if->sk_miibus);
1538 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF);
1539 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), M_DEVBUF);
1541 lwkt_serialize_exit(&sk_serializer);
1547 skc_detach(device_t dev)
1549 struct sk_softc *sc;
1551 sc = device_get_softc(dev);
1554 * recursed from sk_detach ? don't need serializer
1556 bus_generic_detach(dev);
1557 if (sc->sk_devs[SK_PORT_A] != NULL)
1558 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1559 if (sc->sk_devs[SK_PORT_B] != NULL)
1560 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1562 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1563 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1564 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1570 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx)
1572 struct sk_tx_desc *f = NULL;
1574 uint32_t cnt = 0, cur, frag;
1577 cur = frag = *txidx;
1580 * Start packing the mbufs in this chain into
1581 * the fragment pointers. Stop when we run out
1582 * of fragments or hit the end of the mbuf chain.
1584 for (m = m_head; m != NULL; m = m->m_next) {
1585 if (m->m_len != 0) {
1586 if ((SK_TX_RING_CNT -
1587 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2)
1589 f = &sc_if->sk_rdata->sk_tx_ring[frag];
1590 f->sk_data_lo = vtophys(mtod(m, vm_offset_t));
1591 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT;
1593 f->sk_ctl |= SK_TXCTL_FIRSTFRAG;
1595 f->sk_ctl |= SK_TXCTL_OWN;
1597 SK_INC(frag, SK_TX_RING_CNT);
1605 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |=
1606 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR;
1607 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head;
1608 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN;
1609 sc_if->sk_cdata.sk_tx_cnt += cnt;
1617 sk_start(struct ifnet *ifp)
1619 struct sk_if_softc *sc_if = ifp->if_softc;
1620 struct sk_softc *sc = sc_if->sk_softc;
1621 struct mbuf *m_head = NULL;
1625 idx = sc_if->sk_cdata.sk_tx_prod;
1628 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) {
1629 m_head = ifq_poll(&ifp->if_snd);
1634 * Pack the data into the transmit ring. If we
1635 * don't have room, set the OACTIVE flag and wait
1636 * for the NIC to drain the ring.
1638 if (sk_encap(sc_if, m_head, &idx)) {
1639 ifp->if_flags |= IFF_OACTIVE;
1642 ifq_dequeue(&ifp->if_snd, m_head);
1645 BPF_MTAP(ifp, m_head);
1652 sc_if->sk_cdata.sk_tx_prod = idx;
1653 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
1655 /* Set a timeout in case the chip goes out to lunch. */
1661 sk_watchdog(struct ifnet *ifp)
1663 struct sk_if_softc *sc_if;
1665 sc_if = ifp->if_softc;
1667 printf("sk%d: watchdog timeout\n", sc_if->sk_unit);
1670 if (!ifq_is_empty(&ifp->if_snd))
1675 skc_shutdown(device_t dev)
1677 struct sk_softc *sc = device_get_softc(dev);
1679 lwkt_serialize_enter(&sk_serializer);
1681 /* Turn off the 'driver is loaded' LED. */
1682 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
1685 * Reset the GEnesis controller. Doing this should also
1686 * assert the resets on the attached XMAC(s).
1689 lwkt_serialize_exit(&sk_serializer);
1693 sk_rxeof(struct sk_if_softc *sc_if)
1695 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1697 struct sk_chain *cur_rx;
1698 int i, total_len = 0;
1701 i = sc_if->sk_cdata.sk_rx_prod;
1702 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
1704 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) {
1705 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
1706 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat;
1707 m = cur_rx->sk_mbuf;
1708 cur_rx->sk_mbuf = NULL;
1709 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl);
1710 SK_INC(i, SK_RX_RING_CNT);
1712 if (rxstat & XM_RXSTAT_ERRFRAME) {
1714 sk_newbuf(sc_if, cur_rx, m);
1719 * Try to allocate a new jumbo buffer. If that
1720 * fails, copy the packet to mbufs and put the
1721 * jumbo buffer back in the ring so it can be
1722 * re-used. If allocating mbufs fails, then we
1723 * have to drop the packet.
1725 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) {
1727 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1728 total_len + ETHER_ALIGN, 0, ifp, NULL);
1729 sk_newbuf(sc_if, cur_rx, m);
1731 printf("sk%d: no receive buffers "
1732 "available -- packet dropped!\n",
1737 m_adj(m0, ETHER_ALIGN);
1740 m->m_pkthdr.rcvif = ifp;
1741 m->m_pkthdr.len = m->m_len = total_len;
1745 ifp->if_input(ifp, m);
1748 sc_if->sk_cdata.sk_rx_prod = i;
1752 sk_txeof(struct sk_if_softc *sc_if)
1754 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1755 struct sk_tx_desc *cur_tx = NULL;
1759 * Go through our tx ring and free mbufs for those
1760 * frames that have been sent.
1762 idx = sc_if->sk_cdata.sk_tx_cons;
1763 while(idx != sc_if->sk_cdata.sk_tx_prod) {
1764 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx];
1765 if (cur_tx->sk_ctl & SK_TXCTL_OWN)
1767 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG)
1769 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) {
1770 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf);
1771 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL;
1773 sc_if->sk_cdata.sk_tx_cnt--;
1774 SK_INC(idx, SK_TX_RING_CNT);
1778 sc_if->sk_cdata.sk_tx_cons = idx;
1781 ifp->if_flags &= ~IFF_OACTIVE;
1785 sk_tick(void *xsc_if)
1787 struct sk_if_softc *sc_if = xsc_if;
1788 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1789 struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
1792 lwkt_serialize_enter(&sk_serializer);
1794 if ((ifp->if_flags & IFF_UP) == 0) {
1795 lwkt_serialize_exit(&sk_serializer);
1799 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
1800 sk_intr_bcom(sc_if);
1801 lwkt_serialize_exit(&sk_serializer);
1806 * According to SysKonnect, the correct way to verify that
1807 * the link has come back up is to poll bit 0 of the GPIO
1808 * register three times. This pin has the signal from the
1809 * link_sync pin connected to it; if we read the same link
1810 * state 3 times in a row, we know the link is up.
1812 for (i = 0; i < 3; i++) {
1813 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
1818 callout_reset(&sc_if->sk_tick_timer, hz, sk_tick, sc_if);
1819 lwkt_serialize_exit(&sk_serializer);
1823 /* Turn the GP0 interrupt back on. */
1824 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
1825 SK_XM_READ_2(sc_if, XM_ISR);
1828 callout_stop(&sc_if->sk_tick_timer);
1829 lwkt_serialize_exit(&sk_serializer);
1833 sk_intr_bcom(struct sk_if_softc *sc_if)
1835 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1836 struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
1839 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
1842 * Read the PHY interrupt register to make sure
1843 * we clear any pending interrupts.
1845 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
1847 if ((ifp->if_flags & IFF_RUNNING) == 0) {
1848 sk_init_xmac(sc_if);
1852 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
1854 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
1857 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
1859 /* Turn off the link LED. */
1860 SK_IF_WRITE_1(sc_if, 0,
1861 SK_LINKLED1_CTL, SK_LINKLED_OFF);
1863 } else if (status & BRGPHY_ISR_LNK_CHG) {
1864 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
1865 BRGPHY_MII_IMR, 0xFF00);
1868 /* Turn on the link LED. */
1869 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
1870 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
1871 SK_LINKLED_BLINK_OFF);
1875 callout_reset(&sc_if->sk_tick_timer, hz,
1880 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
1884 sk_intr_xmac(struct sk_if_softc *sc_if)
1888 status = SK_XM_READ_2(sc_if, XM_ISR);
1891 * Link has gone down. Start MII tick timeout to
1892 * watch for link resync.
1894 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
1895 if (status & XM_ISR_GP0_SET) {
1896 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
1897 callout_reset(&sc_if->sk_tick_timer, hz,
1901 if (status & XM_ISR_AUTONEG_DONE) {
1902 callout_reset(&sc_if->sk_tick_timer, hz,
1907 if (status & XM_IMR_TX_UNDERRUN)
1908 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
1910 if (status & XM_IMR_RX_OVERRUN)
1911 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
1913 status = SK_XM_READ_2(sc_if, XM_ISR);
1917 sk_intr_yukon(struct sk_if_softc *sc_if)
1921 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
1927 struct sk_softc *sc = xsc;
1928 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A];
1929 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_A];
1930 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
1934 ifp0 = &sc_if0->arpcom.ac_if;
1936 ifp1 = &sc_if1->arpcom.ac_if;
1939 status = CSR_READ_4(sc, SK_ISSR);
1940 if ((status & sc->sk_intrmask) == 0)
1943 /* Handle receive interrupts first. */
1944 if (status & SK_ISR_RX1_EOF) {
1946 CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
1947 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
1949 if (status & SK_ISR_RX2_EOF) {
1951 CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
1952 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
1955 /* Then transmit interrupts. */
1956 if (status & SK_ISR_TX1_S_EOF) {
1958 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0,
1959 SK_TXBMU_CLR_IRQ_EOF);
1961 if (status & SK_ISR_TX2_S_EOF) {
1963 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1,
1964 SK_TXBMU_CLR_IRQ_EOF);
1967 /* Then MAC interrupts. */
1968 if (status & SK_ISR_MAC1 && ifp0->if_flags & IFF_RUNNING) {
1969 if (sc->sk_type == SK_GENESIS)
1970 sk_intr_xmac(sc_if0);
1972 sk_intr_yukon(sc_if0);
1975 if (status & SK_ISR_MAC2 && ifp1->if_flags & IFF_RUNNING) {
1976 if (sc->sk_type == SK_GENESIS)
1977 sk_intr_xmac(sc_if1);
1979 sk_intr_yukon(sc_if0);
1982 if (status & SK_ISR_EXTERNAL_REG) {
1984 sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
1985 sk_intr_bcom(sc_if0);
1987 sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
1988 sk_intr_bcom(sc_if1);
1992 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
1994 if (ifp0 != NULL && !ifq_is_empty(&ifp0->if_snd))
1996 if (ifp1 != NULL && !ifq_is_empty(&ifp0->if_snd))
2001 sk_init_xmac(struct sk_if_softc *sc_if)
2003 struct sk_softc *sc = sc_if->sk_softc;
2004 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2005 struct sk_bcom_hack bhack[] = {
2006 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
2007 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
2008 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
2011 /* Unreset the XMAC. */
2012 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
2015 /* Reset the XMAC's internal state. */
2016 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2018 /* Save the XMAC II revision */
2019 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
2022 * Perform additional initialization for external PHYs,
2023 * namely for the 1000baseTX cards that use the XMAC's
2026 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2030 /* Take PHY out of reset. */
2031 val = sk_win_read_4(sc, SK_GPIO);
2032 if (sc_if->sk_port == SK_PORT_A)
2033 val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
2035 val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
2036 sk_win_write_4(sc, SK_GPIO, val);
2038 /* Enable GMII mode on the XMAC. */
2039 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
2041 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2042 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
2044 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2045 BRGPHY_MII_IMR, 0xFFF0);
2048 * Early versions of the BCM5400 apparently have
2049 * a bug that requires them to have their reserved
2050 * registers initialized to some magic values. I don't
2051 * know what the numbers do, I'm just the messenger.
2053 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
2055 while(bhack[i].reg) {
2056 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2057 bhack[i].reg, bhack[i].val);
2063 /* Set station address */
2064 SK_XM_WRITE_2(sc_if, XM_PAR0,
2065 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[0]));
2066 SK_XM_WRITE_2(sc_if, XM_PAR1,
2067 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[2]));
2068 SK_XM_WRITE_2(sc_if, XM_PAR2,
2069 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[4]));
2070 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
2072 if (ifp->if_flags & IFF_BROADCAST)
2073 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2075 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2077 /* We don't need the FCS appended to the packet. */
2078 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
2080 /* We want short frames padded to 60 bytes. */
2081 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
2084 * Enable the reception of all error frames. This is is
2085 * a necessary evil due to the design of the XMAC. The
2086 * XMAC's receive FIFO is only 8K in size, however jumbo
2087 * frames can be up to 9000 bytes in length. When bad
2088 * frame filtering is enabled, the XMAC's RX FIFO operates
2089 * in 'store and forward' mode. For this to work, the
2090 * entire frame has to fit into the FIFO, but that means
2091 * that jumbo frames larger than 8192 bytes will be
2092 * truncated. Disabling all bad frame filtering causes
2093 * the RX FIFO to operate in streaming mode, in which
2094 * case the XMAC will start transfering frames out of the
2095 * RX FIFO as soon as the FIFO threshold is reached.
2097 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
2098 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
2099 XM_MODE_RX_INRANGELEN);
2101 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2102 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2104 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2107 * Bump up the transmit threshold. This helps hold off transmit
2108 * underruns when we're blasting traffic from both ports at once.
2110 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
2112 /* Set promiscuous mode */
2113 sk_setpromisc(sc_if);
2115 /* Set multicast filter */
2118 /* Clear and enable interrupts */
2119 SK_XM_READ_2(sc_if, XM_ISR);
2120 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
2121 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
2123 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2125 /* Configure MAC arbiter */
2126 switch(sc_if->sk_xmac_rev) {
2127 case XM_XMAC_REV_B2:
2128 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
2129 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
2130 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
2131 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
2132 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
2133 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
2134 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
2135 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
2136 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2138 case XM_XMAC_REV_C1:
2139 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
2140 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
2141 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
2142 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
2143 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
2144 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
2145 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
2146 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
2147 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2152 sk_win_write_2(sc, SK_MACARB_CTL,
2153 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
2159 sk_init_yukon(struct sk_if_softc *sc_if)
2161 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2166 /* GMAC and GPHY Reset */
2167 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
2168 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2170 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR);
2171 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2174 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
2175 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
2177 switch(sc_if->sk_softc->sk_pmd) {
2180 phy |= SK_GPHY_FIBER;
2185 phy |= SK_GPHY_COPPER;
2189 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
2191 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
2192 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
2193 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
2195 /* unused read of the interrupt source register */
2196 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2198 reg = SK_YU_READ_2(sc_if, YUKON_PAR);
2200 /* MIB Counter Clear Mode set */
2201 reg |= YU_PAR_MIB_CLR;
2202 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2204 /* MIB Counter Clear Mode clear */
2205 reg &= ~YU_PAR_MIB_CLR;
2206 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2208 /* receive control reg */
2209 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
2211 /* transmit parameter register */
2212 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
2213 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
2215 /* serial mode register */
2216 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
2217 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2218 reg |= YU_SMR_MFL_JUMBO;
2219 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
2221 /* Setup Yukon's address */
2222 for (i = 0; i < 3; i++) {
2223 /* Write Source Address 1 (unicast filter) */
2224 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
2225 sc_if->arpcom.ac_enaddr[i * 2] |
2226 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8);
2229 for (i = 0; i < 3; i++) {
2230 reg = sk_win_read_2(sc_if->sk_softc,
2231 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
2232 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
2235 /* Set promiscuous mode */
2236 sk_setpromisc(sc_if);
2238 /* Set multicast filter */
2241 /* enable interrupt mask for counter overflows */
2242 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
2243 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
2244 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
2246 /* Configure RX MAC FIFO */
2247 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
2248 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON);
2250 /* Configure TX MAC FIFO */
2251 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
2252 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
2256 * Note that to properly initialize any part of the GEnesis chip,
2257 * you first have to take it out of reset mode.
2262 struct sk_if_softc *sc_if = xsc;
2263 struct sk_softc *sc = sc_if->sk_softc;
2264 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2265 struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2270 /* Cancel pending I/O and free all RX/TX buffers. */
2273 if (sc->sk_type == SK_GENESIS) {
2274 /* Configure LINK_SYNC LED */
2275 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
2276 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2277 SK_LINKLED_LINKSYNC_ON);
2279 /* Configure RX LED */
2280 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
2281 SK_RXLEDCTL_COUNTER_START);
2283 /* Configure TX LED */
2284 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
2285 SK_TXLEDCTL_COUNTER_START);
2288 /* Configure I2C registers */
2290 /* Configure XMAC(s) */
2291 switch (sc->sk_type) {
2293 sk_init_xmac(sc_if);
2296 sk_init_yukon(sc_if);
2301 if (sc->sk_type == SK_GENESIS) {
2302 /* Configure MAC FIFOs */
2303 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
2304 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
2305 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
2307 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
2308 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
2309 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
2312 /* Configure transmit arbiter(s) */
2313 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
2314 SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON);
2316 /* Configure RAMbuffers */
2317 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2318 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2319 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2320 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2321 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2322 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2324 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
2325 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
2326 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
2327 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
2328 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
2329 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
2330 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
2332 /* Configure BMUs */
2333 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
2334 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
2335 vtophys(&sc_if->sk_rdata->sk_rx_ring[0]));
2336 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0);
2338 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
2339 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
2340 vtophys(&sc_if->sk_rdata->sk_tx_ring[0]));
2341 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0);
2343 /* Init descriptors */
2344 if (sk_init_rx_ring(sc_if) == ENOBUFS) {
2345 printf("sk%d: initialization failed: no "
2346 "memory for rx buffers\n", sc_if->sk_unit);
2351 sk_init_tx_ring(sc_if);
2353 /* Configure interrupt handling */
2354 CSR_READ_4(sc, SK_ISSR);
2355 if (sc_if->sk_port == SK_PORT_A)
2356 sc->sk_intrmask |= SK_INTRS1;
2358 sc->sk_intrmask |= SK_INTRS2;
2360 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
2362 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2365 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
2367 switch(sc->sk_type) {
2369 /* Enable XMACs TX and RX state machines */
2370 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
2371 SK_XM_SETBIT_2(sc_if, XM_MMUCMD,
2372 XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB);
2375 reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
2376 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
2377 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN);
2378 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
2381 ifp->if_flags |= IFF_RUNNING;
2382 ifp->if_flags &= ~IFF_OACTIVE;
2388 sk_stop(struct sk_if_softc *sc_if)
2391 struct sk_softc *sc = sc_if->sk_softc;
2392 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2394 callout_stop(&sc_if->sk_tick_timer);
2396 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2399 /* Put PHY back into reset. */
2400 val = sk_win_read_4(sc, SK_GPIO);
2401 if (sc_if->sk_port == SK_PORT_A) {
2402 val |= SK_GPIO_DIR0;
2403 val &= ~SK_GPIO_DAT0;
2405 val |= SK_GPIO_DIR2;
2406 val &= ~SK_GPIO_DAT2;
2408 sk_win_write_4(sc, SK_GPIO, val);
2411 /* Turn off various components of this interface. */
2412 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2413 switch (sc->sk_type) {
2415 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
2416 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
2419 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
2420 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
2423 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2424 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF);
2425 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
2426 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST,
2427 SK_RBCTL_RESET | SK_RBCTL_OFF);
2428 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2429 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2430 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2431 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2432 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2434 /* Disable interrupts */
2435 if (sc_if->sk_port == SK_PORT_A)
2436 sc->sk_intrmask &= ~SK_INTRS1;
2438 sc->sk_intrmask &= ~SK_INTRS2;
2439 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2441 SK_XM_READ_2(sc_if, XM_ISR);
2442 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2444 /* Free RX and TX mbufs still in the queues. */
2445 for (i = 0; i < SK_RX_RING_CNT; i++) {
2446 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) {
2447 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf);
2448 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL;
2452 for (i = 0; i < SK_TX_RING_CNT; i++) {
2453 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) {
2454 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf);
2455 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL;
2459 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);