2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/export.h>
31 #include <linux/slab.h>
32 #include <linux/string.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
40 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
44 * @intel_dp: DP struct
46 * If a CPU or PCH DP output is attached to an eDP panel, this function
47 * will return true, and false otherwise.
49 static bool is_edp(struct intel_dp *intel_dp)
51 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
53 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
56 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
58 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
60 return intel_dig_port->base.base.dev;
63 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
65 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
68 static void intel_dp_link_down(struct intel_dp *intel_dp);
71 intel_dp_max_link_bw(struct intel_dp *intel_dp)
73 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
75 switch (max_link_bw) {
79 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
80 max_link_bw = DP_LINK_BW_2_7;
83 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
85 max_link_bw = DP_LINK_BW_1_62;
92 * The units on the numbers in the next two are... bizarre. Examples will
93 * make it clearer; this one parallels an example in the eDP spec.
95 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
97 * 270000 * 1 * 8 / 10 == 216000
99 * The actual data capacity of that configuration is 2.16Gbit/s, so the
100 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
101 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
102 * 119000. At 18bpp that's 2142000 kilobits per second.
104 * Thus the strange-looking division by 10 in intel_dp_link_required, to
105 * get the result in decakilobits instead of kilobits.
109 intel_dp_link_required(int pixel_clock, int bpp)
111 return (pixel_clock * bpp + 9) / 10;
115 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
117 return (max_link_clock * max_lanes * 8) / 10;
121 intel_dp_mode_valid(struct drm_connector *connector,
122 struct drm_display_mode *mode)
124 struct intel_dp *intel_dp = intel_attached_dp(connector);
125 struct intel_connector *intel_connector = to_intel_connector(connector);
126 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
127 int target_clock = mode->clock;
128 int max_rate, mode_rate, max_lanes, max_link_clock;
130 if (is_edp(intel_dp) && fixed_mode) {
131 if (mode->hdisplay > fixed_mode->hdisplay)
134 if (mode->vdisplay > fixed_mode->vdisplay)
137 target_clock = fixed_mode->clock;
140 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
141 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
143 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
144 mode_rate = intel_dp_link_required(target_clock, 18);
146 if (mode_rate > max_rate)
147 return MODE_CLOCK_HIGH;
149 if (mode->clock < 10000)
150 return MODE_CLOCK_LOW;
152 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
153 return MODE_H_ILLEGAL;
159 pack_aux(uint8_t *src, int src_bytes)
166 for (i = 0; i < src_bytes; i++)
167 v |= ((uint32_t) src[i]) << ((3-i) * 8);
172 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
177 for (i = 0; i < dst_bytes; i++)
178 dst[i] = src >> ((3-i) * 8);
181 /* hrawclock is 1/4 the FSB frequency */
183 intel_hrawclk(struct drm_device *dev)
185 struct drm_i915_private *dev_priv = dev->dev_private;
188 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
189 if (IS_VALLEYVIEW(dev))
192 clkcfg = I915_READ(CLKCFG);
193 switch (clkcfg & CLKCFG_FSB_MASK) {
202 case CLKCFG_FSB_1067:
204 case CLKCFG_FSB_1333:
206 /* these two are just a guess; one of them might be right */
207 case CLKCFG_FSB_1600:
208 case CLKCFG_FSB_1600_ALT:
215 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
217 struct drm_device *dev = intel_dp_to_dev(intel_dp);
218 struct drm_i915_private *dev_priv = dev->dev_private;
221 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
222 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
225 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
227 struct drm_device *dev = intel_dp_to_dev(intel_dp);
228 struct drm_i915_private *dev_priv = dev->dev_private;
231 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
232 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
236 intel_dp_check_edp(struct intel_dp *intel_dp)
238 struct drm_device *dev = intel_dp_to_dev(intel_dp);
239 struct drm_i915_private *dev_priv = dev->dev_private;
240 u32 pp_stat_reg, pp_ctrl_reg;
242 if (!is_edp(intel_dp))
245 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
246 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
248 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
249 WARN(1, "eDP powered off while attempting aux channel communication.\n");
250 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
251 I915_READ(pp_stat_reg),
252 I915_READ(pp_ctrl_reg));
257 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
259 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
260 struct drm_device *dev = intel_dig_port->base.base.dev;
261 struct drm_i915_private *dev_priv = dev->dev_private;
262 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
266 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
268 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
269 msecs_to_jiffies(10));
271 done = wait_for_atomic(C, 10) == 0;
273 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
281 intel_dp_aux_ch(struct intel_dp *intel_dp,
282 uint8_t *send, int send_bytes,
283 uint8_t *recv, int recv_size)
285 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
286 struct drm_device *dev = intel_dig_port->base.base.dev;
287 struct drm_i915_private *dev_priv = dev->dev_private;
288 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
289 uint32_t ch_data = ch_ctl + 4;
290 int i, ret, recv_bytes;
292 uint32_t aux_clock_divider;
294 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
296 /* dp aux is extremely sensitive to irq latency, hence request the
297 * lowest possible wakeup latency and so prevent the cpu from going into
300 pm_qos_update_request(&dev_priv->pm_qos, 0);
302 intel_dp_check_edp(intel_dp);
303 /* The clock divider is based off the hrawclk,
304 * and would like to run at 2MHz. So, take the
305 * hrawclk value and divide by 2 and use that
307 * Note that PCH attached eDP panels should use a 125MHz input
310 if (IS_VALLEYVIEW(dev)) {
311 aux_clock_divider = 100;
312 } else if (intel_dig_port->port == PORT_A) {
314 aux_clock_divider = DIV_ROUND_CLOSEST(
315 intel_ddi_get_cdclk_freq(dev_priv), 2000);
316 else if (IS_GEN6(dev) || IS_GEN7(dev))
317 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
319 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
320 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
321 /* Workaround for non-ULT HSW */
322 aux_clock_divider = 74;
323 } else if (HAS_PCH_SPLIT(dev)) {
324 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
326 aux_clock_divider = intel_hrawclk(dev) / 2;
334 /* Try to wait for any previous AUX channel activity */
335 for (try = 0; try < 3; try++) {
336 status = I915_READ_NOTRACE(ch_ctl);
337 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
343 WARN(1, "dp_aux_ch not started status 0x%08x\n",
349 /* Must try at least 3 times according to DP spec */
350 for (try = 0; try < 5; try++) {
351 /* Load the send data into the aux channel data registers */
352 for (i = 0; i < send_bytes; i += 4)
353 I915_WRITE(ch_data + i,
354 pack_aux(send + i, send_bytes - i));
356 /* Send the command and wait for it to complete */
358 DP_AUX_CH_CTL_SEND_BUSY |
359 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
360 DP_AUX_CH_CTL_TIME_OUT_400us |
361 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
362 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
363 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
365 DP_AUX_CH_CTL_TIME_OUT_ERROR |
366 DP_AUX_CH_CTL_RECEIVE_ERROR);
368 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
370 /* Clear done status and any errors */
374 DP_AUX_CH_CTL_TIME_OUT_ERROR |
375 DP_AUX_CH_CTL_RECEIVE_ERROR);
377 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
378 DP_AUX_CH_CTL_RECEIVE_ERROR))
380 if (status & DP_AUX_CH_CTL_DONE)
384 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
385 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
390 /* Check for timeout or receive error.
391 * Timeouts occur when the sink is not connected
393 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
394 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
399 /* Timeouts occur when the device isn't connected, so they're
400 * "normal" -- don't fill the kernel log with these */
401 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
402 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
407 /* Unload any bytes sent back from the other side */
408 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
409 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
410 if (recv_bytes > recv_size)
411 recv_bytes = recv_size;
413 for (i = 0; i < recv_bytes; i += 4)
414 unpack_aux(I915_READ(ch_data + i),
415 recv + i, recv_bytes - i);
419 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
424 /* Write data to the aux channel in native mode */
426 intel_dp_aux_native_write(struct intel_dp *intel_dp,
427 uint16_t address, uint8_t *send, int send_bytes)
434 intel_dp_check_edp(intel_dp);
437 msg[0] = AUX_NATIVE_WRITE << 4;
438 msg[1] = address >> 8;
439 msg[2] = address & 0xff;
440 msg[3] = send_bytes - 1;
441 memcpy(&msg[4], send, send_bytes);
442 msg_bytes = send_bytes + 4;
444 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
447 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
449 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
457 /* Write a single byte to the aux channel in native mode */
459 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
460 uint16_t address, uint8_t byte)
462 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
465 /* read bytes from a native aux channel */
467 intel_dp_aux_native_read(struct intel_dp *intel_dp,
468 uint16_t address, uint8_t *recv, int recv_bytes)
477 intel_dp_check_edp(intel_dp);
478 msg[0] = AUX_NATIVE_READ << 4;
479 msg[1] = address >> 8;
480 msg[2] = address & 0xff;
481 msg[3] = recv_bytes - 1;
484 reply_bytes = recv_bytes + 1;
487 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
494 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
495 memcpy(recv, reply + 1, ret - 1);
498 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
506 intel_dp_i2c_aux_ch(struct device *adapter, int mode,
507 uint8_t write_byte, uint8_t *read_byte)
509 struct iic_dp_aux_data *data = device_get_softc(adapter);
510 struct intel_dp *intel_dp = data->priv;
511 uint16_t address = data->address;
519 intel_dp_check_edp(intel_dp);
520 /* Set up the command byte */
521 if (mode & MODE_I2C_READ)
522 msg[0] = AUX_I2C_READ << 4;
524 msg[0] = AUX_I2C_WRITE << 4;
526 if (!(mode & MODE_I2C_STOP))
527 msg[0] |= AUX_I2C_MOT << 4;
529 msg[1] = address >> 8;
550 for (retry = 0; retry < 5; retry++) {
551 ret = intel_dp_aux_ch(intel_dp,
555 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
559 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
560 case AUX_NATIVE_REPLY_ACK:
561 /* I2C-over-AUX Reply field is only valid
562 * when paired with AUX ACK.
565 case AUX_NATIVE_REPLY_NACK:
566 DRM_DEBUG_KMS("aux_ch native nack\n");
568 case AUX_NATIVE_REPLY_DEFER:
572 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
577 switch (reply[0] & AUX_I2C_REPLY_MASK) {
578 case AUX_I2C_REPLY_ACK:
579 if (mode == MODE_I2C_READ) {
580 *read_byte = reply[1];
582 return (0/*reply_bytes - 1*/);
583 case AUX_I2C_REPLY_NACK:
584 DRM_DEBUG_KMS("aux_i2c nack\n");
586 case AUX_I2C_REPLY_DEFER:
587 DRM_DEBUG_KMS("aux_i2c defer\n");
591 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
596 DRM_ERROR("too many retries, giving up\n");
601 intel_dp_i2c_init(struct intel_dp *intel_dp,
602 struct intel_connector *intel_connector, const char *name)
606 DRM_DEBUG_KMS("i2c_init %s\n", name);
608 ironlake_edp_panel_vdd_on(intel_dp);
609 ret = iic_dp_aux_add_bus(intel_connector->base.dev->dev, name,
610 intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus,
612 ironlake_edp_panel_vdd_off(intel_dp, false);
617 intel_dp_set_clock(struct intel_encoder *encoder,
618 struct intel_crtc_config *pipe_config, int link_bw)
620 struct drm_device *dev = encoder->base.dev;
623 if (link_bw == DP_LINK_BW_1_62) {
624 pipe_config->dpll.p1 = 2;
625 pipe_config->dpll.p2 = 10;
626 pipe_config->dpll.n = 2;
627 pipe_config->dpll.m1 = 23;
628 pipe_config->dpll.m2 = 8;
630 pipe_config->dpll.p1 = 1;
631 pipe_config->dpll.p2 = 10;
632 pipe_config->dpll.n = 1;
633 pipe_config->dpll.m1 = 14;
634 pipe_config->dpll.m2 = 2;
636 pipe_config->clock_set = true;
637 } else if (IS_HASWELL(dev)) {
638 /* Haswell has special-purpose DP DDI clocks. */
639 } else if (HAS_PCH_SPLIT(dev)) {
640 if (link_bw == DP_LINK_BW_1_62) {
641 pipe_config->dpll.n = 1;
642 pipe_config->dpll.p1 = 2;
643 pipe_config->dpll.p2 = 10;
644 pipe_config->dpll.m1 = 12;
645 pipe_config->dpll.m2 = 9;
647 pipe_config->dpll.n = 2;
648 pipe_config->dpll.p1 = 1;
649 pipe_config->dpll.p2 = 10;
650 pipe_config->dpll.m1 = 14;
651 pipe_config->dpll.m2 = 8;
653 pipe_config->clock_set = true;
654 } else if (IS_VALLEYVIEW(dev)) {
655 /* FIXME: Need to figure out optimized DP clocks for vlv. */
660 intel_dp_compute_config(struct intel_encoder *encoder,
661 struct intel_crtc_config *pipe_config)
663 struct drm_device *dev = encoder->base.dev;
664 struct drm_i915_private *dev_priv = dev->dev_private;
665 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
666 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
667 enum port port = dp_to_dig_port(intel_dp)->port;
668 struct intel_crtc *intel_crtc = encoder->new_crtc;
669 struct intel_connector *intel_connector = intel_dp->attached_connector;
670 int lane_count, clock;
671 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
672 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
674 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
675 int link_avail, link_clock;
677 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
678 pipe_config->has_pch_encoder = true;
680 pipe_config->has_dp_encoder = true;
682 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
683 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
685 if (!HAS_PCH_SPLIT(dev))
686 intel_gmch_panel_fitting(intel_crtc, pipe_config,
687 intel_connector->panel.fitting_mode);
689 intel_pch_panel_fitting(intel_crtc, pipe_config,
690 intel_connector->panel.fitting_mode);
693 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
696 DRM_DEBUG_KMS("DP link computation with max lane count %i "
697 "max bw %02x pixel clock %iKHz\n",
698 max_lane_count, bws[max_clock], adjusted_mode->clock);
700 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
702 bpp = pipe_config->pipe_bpp;
703 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp)
704 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
706 for (; bpp >= 6*3; bpp -= 2*3) {
707 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
709 for (clock = 0; clock <= max_clock; clock++) {
710 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
711 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
712 link_avail = intel_dp_max_data_rate(link_clock,
715 if (mode_rate <= link_avail) {
725 if (intel_dp->color_range_auto) {
728 * CEA-861-E - 5.1 Default Encoding Parameters
729 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
731 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
732 intel_dp->color_range = DP_COLOR_RANGE_16_235;
734 intel_dp->color_range = 0;
737 if (intel_dp->color_range)
738 pipe_config->limited_color_range = true;
740 intel_dp->link_bw = bws[clock];
741 intel_dp->lane_count = lane_count;
742 pipe_config->pipe_bpp = bpp;
743 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
745 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
746 intel_dp->link_bw, intel_dp->lane_count,
747 pipe_config->port_clock, bpp);
748 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
749 mode_rate, link_avail);
751 intel_link_compute_m_n(bpp, lane_count,
752 adjusted_mode->clock, pipe_config->port_clock,
753 &pipe_config->dp_m_n);
755 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
760 void intel_dp_init_link_config(struct intel_dp *intel_dp)
762 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
763 intel_dp->link_configuration[0] = intel_dp->link_bw;
764 intel_dp->link_configuration[1] = intel_dp->lane_count;
765 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
767 * Check for DPCD version > 1.1 and enhanced framing support
769 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
770 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
771 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
775 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
777 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
778 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
779 struct drm_device *dev = crtc->base.dev;
780 struct drm_i915_private *dev_priv = dev->dev_private;
783 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
784 dpa_ctl = I915_READ(DP_A);
785 dpa_ctl &= ~DP_PLL_FREQ_MASK;
787 if (crtc->config.port_clock == 162000) {
788 /* For a long time we've carried around a ILK-DevA w/a for the
789 * 160MHz clock. If we're really unlucky, it's still required.
791 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
792 dpa_ctl |= DP_PLL_FREQ_160MHZ;
793 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
795 dpa_ctl |= DP_PLL_FREQ_270MHZ;
796 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
799 I915_WRITE(DP_A, dpa_ctl);
806 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
807 struct drm_display_mode *adjusted_mode)
809 struct drm_device *dev = encoder->dev;
810 struct drm_i915_private *dev_priv = dev->dev_private;
811 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
812 enum port port = dp_to_dig_port(intel_dp)->port;
813 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
816 * There are four kinds of DP registers:
823 * IBX PCH and CPU are the same for almost everything,
824 * except that the CPU DP PLL is configured in this
827 * CPT PCH is quite different, having many bits moved
828 * to the TRANS_DP_CTL register instead. That
829 * configuration happens (oddly) in ironlake_pch_enable
832 /* Preserve the BIOS-computed detected bit. This is
833 * supposed to be read-only.
835 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
837 /* Handle DP bits in common between all three register formats */
838 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
839 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
841 if (intel_dp->has_audio) {
842 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
843 pipe_name(crtc->pipe));
844 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
845 intel_write_eld(encoder, adjusted_mode);
848 intel_dp_init_link_config(intel_dp);
850 /* Split out the IBX/CPU vs CPT settings */
852 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
853 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
854 intel_dp->DP |= DP_SYNC_HS_HIGH;
855 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
856 intel_dp->DP |= DP_SYNC_VS_HIGH;
857 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
859 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
860 intel_dp->DP |= DP_ENHANCED_FRAMING;
862 intel_dp->DP |= crtc->pipe << 29;
863 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
864 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
865 intel_dp->DP |= intel_dp->color_range;
867 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
868 intel_dp->DP |= DP_SYNC_HS_HIGH;
869 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
870 intel_dp->DP |= DP_SYNC_VS_HIGH;
871 intel_dp->DP |= DP_LINK_TRAIN_OFF;
873 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
874 intel_dp->DP |= DP_ENHANCED_FRAMING;
877 intel_dp->DP |= DP_PIPEB_SELECT;
879 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
882 if (port == PORT_A && !IS_VALLEYVIEW(dev))
883 ironlake_set_pll_cpu_edp(intel_dp);
886 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
887 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
889 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
890 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
892 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
893 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
895 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
899 struct drm_device *dev = intel_dp_to_dev(intel_dp);
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 u32 pp_stat_reg, pp_ctrl_reg;
903 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
904 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
906 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
908 I915_READ(pp_stat_reg),
909 I915_READ(pp_ctrl_reg));
911 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
912 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
913 I915_READ(pp_stat_reg),
914 I915_READ(pp_ctrl_reg));
918 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
920 DRM_DEBUG_KMS("Wait for panel power on\n");
921 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
924 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
926 DRM_DEBUG_KMS("Wait for panel power off time\n");
927 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
930 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
932 DRM_DEBUG_KMS("Wait for panel power cycle\n");
933 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
937 /* Read the current pp_control value, unlocking the register if it
941 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
943 struct drm_device *dev = intel_dp_to_dev(intel_dp);
944 struct drm_i915_private *dev_priv = dev->dev_private;
948 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
949 control = I915_READ(pp_ctrl_reg);
951 control &= ~PANEL_UNLOCK_MASK;
952 control |= PANEL_UNLOCK_REGS;
956 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
958 struct drm_device *dev = intel_dp_to_dev(intel_dp);
959 struct drm_i915_private *dev_priv = dev->dev_private;
961 u32 pp_stat_reg, pp_ctrl_reg;
963 if (!is_edp(intel_dp))
965 DRM_DEBUG_KMS("Turn eDP VDD on\n");
967 WARN(intel_dp->want_panel_vdd,
968 "eDP VDD already requested on\n");
970 intel_dp->want_panel_vdd = true;
972 if (ironlake_edp_have_panel_vdd(intel_dp)) {
973 DRM_DEBUG_KMS("eDP VDD already on\n");
977 if (!ironlake_edp_have_panel_power(intel_dp))
978 ironlake_wait_panel_power_cycle(intel_dp);
980 pp = ironlake_get_pp_control(intel_dp);
983 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
984 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
986 I915_WRITE(pp_ctrl_reg, pp);
987 POSTING_READ(pp_ctrl_reg);
988 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
989 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
991 * If the panel wasn't on, delay before accessing aux channel
993 if (!ironlake_edp_have_panel_power(intel_dp)) {
994 DRM_DEBUG_KMS("eDP was not running\n");
995 msleep(intel_dp->panel_power_up_delay);
999 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1001 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1002 struct drm_i915_private *dev_priv = dev->dev_private;
1004 u32 pp_stat_reg, pp_ctrl_reg;
1006 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1008 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1009 pp = ironlake_get_pp_control(intel_dp);
1010 pp &= ~EDP_FORCE_VDD;
1012 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1013 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1015 I915_WRITE(pp_ctrl_reg, pp);
1016 POSTING_READ(pp_ctrl_reg);
1018 /* Make sure sequencer is idle before allowing subsequent activity */
1019 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1020 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1021 msleep(intel_dp->panel_power_down_delay);
1025 static void ironlake_panel_vdd_work(struct work_struct *__work)
1027 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1028 struct intel_dp, panel_vdd_work);
1029 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1031 mutex_lock(&dev->mode_config.mutex);
1032 ironlake_panel_vdd_off_sync(intel_dp);
1033 mutex_unlock(&dev->mode_config.mutex);
1036 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1038 if (!is_edp(intel_dp))
1041 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1042 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1044 intel_dp->want_panel_vdd = false;
1047 ironlake_panel_vdd_off_sync(intel_dp);
1050 * Queue the timer to fire a long
1051 * time from now (relative to the power down delay)
1052 * to keep the panel power up across a sequence of operations
1054 schedule_delayed_work(&intel_dp->panel_vdd_work,
1055 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1059 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1061 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1062 struct drm_i915_private *dev_priv = dev->dev_private;
1066 if (!is_edp(intel_dp))
1069 DRM_DEBUG_KMS("Turn eDP power on\n");
1071 if (ironlake_edp_have_panel_power(intel_dp)) {
1072 DRM_DEBUG_KMS("eDP power already on\n");
1076 ironlake_wait_panel_power_cycle(intel_dp);
1078 pp = ironlake_get_pp_control(intel_dp);
1080 /* ILK workaround: disable reset around power sequence */
1081 pp &= ~PANEL_POWER_RESET;
1082 I915_WRITE(PCH_PP_CONTROL, pp);
1083 POSTING_READ(PCH_PP_CONTROL);
1086 pp |= POWER_TARGET_ON;
1088 pp |= PANEL_POWER_RESET;
1090 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1092 I915_WRITE(pp_ctrl_reg, pp);
1093 POSTING_READ(pp_ctrl_reg);
1095 ironlake_wait_panel_on(intel_dp);
1098 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1099 I915_WRITE(PCH_PP_CONTROL, pp);
1100 POSTING_READ(PCH_PP_CONTROL);
1104 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1106 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1107 struct drm_i915_private *dev_priv = dev->dev_private;
1111 if (!is_edp(intel_dp))
1114 DRM_DEBUG_KMS("Turn eDP power off\n");
1116 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1118 pp = ironlake_get_pp_control(intel_dp);
1119 /* We need to switch off panel power _and_ force vdd, for otherwise some
1120 * panels get very unhappy and cease to work. */
1121 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1123 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1125 I915_WRITE(pp_ctrl_reg, pp);
1126 POSTING_READ(pp_ctrl_reg);
1128 intel_dp->want_panel_vdd = false;
1130 ironlake_wait_panel_off(intel_dp);
1133 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1135 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1136 struct drm_device *dev = intel_dig_port->base.base.dev;
1137 struct drm_i915_private *dev_priv = dev->dev_private;
1138 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1142 if (!is_edp(intel_dp))
1145 DRM_DEBUG_KMS("\n");
1147 * If we enable the backlight right away following a panel power
1148 * on, we may see slight flicker as the panel syncs with the eDP
1149 * link. So delay a bit to make sure the image is solid before
1150 * allowing it to appear.
1152 msleep(intel_dp->backlight_on_delay);
1153 pp = ironlake_get_pp_control(intel_dp);
1154 pp |= EDP_BLC_ENABLE;
1156 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1158 I915_WRITE(pp_ctrl_reg, pp);
1159 POSTING_READ(pp_ctrl_reg);
1161 intel_panel_enable_backlight(dev, pipe);
1164 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1166 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1167 struct drm_i915_private *dev_priv = dev->dev_private;
1171 if (!is_edp(intel_dp))
1174 intel_panel_disable_backlight(dev);
1176 DRM_DEBUG_KMS("\n");
1177 pp = ironlake_get_pp_control(intel_dp);
1178 pp &= ~EDP_BLC_ENABLE;
1180 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1182 I915_WRITE(pp_ctrl_reg, pp);
1183 POSTING_READ(pp_ctrl_reg);
1184 msleep(intel_dp->backlight_off_delay);
1187 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1189 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1190 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1191 struct drm_device *dev = crtc->dev;
1192 struct drm_i915_private *dev_priv = dev->dev_private;
1195 assert_pipe_disabled(dev_priv,
1196 to_intel_crtc(crtc)->pipe);
1198 DRM_DEBUG_KMS("\n");
1199 dpa_ctl = I915_READ(DP_A);
1200 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1201 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1203 /* We don't adjust intel_dp->DP while tearing down the link, to
1204 * facilitate link retraining (e.g. after hotplug). Hence clear all
1205 * enable bits here to ensure that we don't enable too much. */
1206 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1207 intel_dp->DP |= DP_PLL_ENABLE;
1208 I915_WRITE(DP_A, intel_dp->DP);
1213 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1215 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1216 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1217 struct drm_device *dev = crtc->dev;
1218 struct drm_i915_private *dev_priv = dev->dev_private;
1221 assert_pipe_disabled(dev_priv,
1222 to_intel_crtc(crtc)->pipe);
1224 dpa_ctl = I915_READ(DP_A);
1225 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1226 "dp pll off, should be on\n");
1227 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1229 /* We can't rely on the value tracked for the DP register in
1230 * intel_dp->DP because link_down must not change that (otherwise link
1231 * re-training will fail. */
1232 dpa_ctl &= ~DP_PLL_ENABLE;
1233 I915_WRITE(DP_A, dpa_ctl);
1238 /* If the sink supports it, try to set the power state appropriately */
1239 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1243 /* Should have a valid DPCD by this point */
1244 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1247 if (mode != DRM_MODE_DPMS_ON) {
1248 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1251 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1254 * When turning on, we need to retry for 1ms to give the sink
1257 for (i = 0; i < 3; i++) {
1258 ret = intel_dp_aux_native_write_1(intel_dp,
1268 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1269 enum i915_pipe *pipe)
1271 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1272 enum port port = dp_to_dig_port(intel_dp)->port;
1273 struct drm_device *dev = encoder->base.dev;
1274 struct drm_i915_private *dev_priv = dev->dev_private;
1275 u32 tmp = I915_READ(intel_dp->output_reg);
1277 if (!(tmp & DP_PORT_EN))
1280 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1281 *pipe = PORT_TO_PIPE_CPT(tmp);
1282 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1283 *pipe = PORT_TO_PIPE(tmp);
1289 switch (intel_dp->output_reg) {
1291 trans_sel = TRANS_DP_PORT_SEL_B;
1294 trans_sel = TRANS_DP_PORT_SEL_C;
1297 trans_sel = TRANS_DP_PORT_SEL_D;
1304 trans_dp = I915_READ(TRANS_DP_CTL(i));
1305 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1311 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1312 intel_dp->output_reg);
1318 static void intel_dp_get_config(struct intel_encoder *encoder,
1319 struct intel_crtc_config *pipe_config)
1321 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1323 struct drm_device *dev = encoder->base.dev;
1324 struct drm_i915_private *dev_priv = dev->dev_private;
1325 enum port port = dp_to_dig_port(intel_dp)->port;
1326 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1328 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1329 tmp = I915_READ(intel_dp->output_reg);
1330 if (tmp & DP_SYNC_HS_HIGH)
1331 flags |= DRM_MODE_FLAG_PHSYNC;
1333 flags |= DRM_MODE_FLAG_NHSYNC;
1335 if (tmp & DP_SYNC_VS_HIGH)
1336 flags |= DRM_MODE_FLAG_PVSYNC;
1338 flags |= DRM_MODE_FLAG_NVSYNC;
1340 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1341 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1342 flags |= DRM_MODE_FLAG_PHSYNC;
1344 flags |= DRM_MODE_FLAG_NHSYNC;
1346 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1347 flags |= DRM_MODE_FLAG_PVSYNC;
1349 flags |= DRM_MODE_FLAG_NVSYNC;
1352 pipe_config->adjusted_mode.flags |= flags;
1355 static void intel_disable_dp(struct intel_encoder *encoder)
1357 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1358 enum port port = dp_to_dig_port(intel_dp)->port;
1359 struct drm_device *dev = encoder->base.dev;
1361 /* Make sure the panel is off before trying to change the mode. But also
1362 * ensure that we have vdd while we switch off the panel. */
1363 ironlake_edp_panel_vdd_on(intel_dp);
1364 ironlake_edp_backlight_off(intel_dp);
1365 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1366 ironlake_edp_panel_off(intel_dp);
1368 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1369 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1370 intel_dp_link_down(intel_dp);
1373 static void intel_post_disable_dp(struct intel_encoder *encoder)
1375 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1376 enum port port = dp_to_dig_port(intel_dp)->port;
1377 struct drm_device *dev = encoder->base.dev;
1379 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1380 intel_dp_link_down(intel_dp);
1381 if (!IS_VALLEYVIEW(dev))
1382 ironlake_edp_pll_off(intel_dp);
1386 static void intel_enable_dp(struct intel_encoder *encoder)
1388 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1389 struct drm_device *dev = encoder->base.dev;
1390 struct drm_i915_private *dev_priv = dev->dev_private;
1391 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1393 if (WARN_ON(dp_reg & DP_PORT_EN))
1396 ironlake_edp_panel_vdd_on(intel_dp);
1397 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1398 intel_dp_start_link_train(intel_dp);
1399 ironlake_edp_panel_on(intel_dp);
1400 ironlake_edp_panel_vdd_off(intel_dp, true);
1401 intel_dp_complete_link_train(intel_dp);
1402 intel_dp_stop_link_train(intel_dp);
1403 ironlake_edp_backlight_on(intel_dp);
1405 if (IS_VALLEYVIEW(dev)) {
1406 struct intel_digital_port *dport =
1407 enc_to_dig_port(&encoder->base);
1408 int channel = vlv_dport_to_channel(dport);
1410 vlv_wait_port_ready(dev_priv, channel);
1414 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1416 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1417 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1418 struct drm_device *dev = encoder->base.dev;
1419 struct drm_i915_private *dev_priv = dev->dev_private;
1421 if (dport->port == PORT_A && !IS_VALLEYVIEW(dev))
1422 ironlake_edp_pll_on(intel_dp);
1424 if (IS_VALLEYVIEW(dev)) {
1425 struct intel_crtc *intel_crtc =
1426 to_intel_crtc(encoder->base.crtc);
1427 int port = vlv_dport_to_channel(dport);
1428 int pipe = intel_crtc->pipe;
1431 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1438 vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1440 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
1442 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1447 static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1449 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1450 struct drm_device *dev = encoder->base.dev;
1451 struct drm_i915_private *dev_priv = dev->dev_private;
1452 int port = vlv_dport_to_channel(dport);
1454 if (!IS_VALLEYVIEW(dev))
1457 /* Program Tx lane resets to default */
1458 vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
1459 DPIO_PCS_TX_LANE2_RESET |
1460 DPIO_PCS_TX_LANE1_RESET);
1461 vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1462 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1463 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1464 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1465 DPIO_PCS_CLK_SOFT_RESET);
1467 /* Fix up inter-pair skew failure */
1468 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1469 vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1470 vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
1474 * Native read with retry for link status and receiver capability reads for
1475 * cases where the sink may still be asleep.
1478 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1479 uint8_t *recv, int recv_bytes)
1484 * Sinks are *supposed* to come up within 1ms from an off state,
1485 * but we're also supposed to retry 3 times per the spec.
1487 for (i = 0; i < 3; i++) {
1488 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1490 if (ret == recv_bytes)
1499 * Fetch AUX CH registers 0x202 - 0x207 which contain
1500 * link status information
1503 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1505 return intel_dp_aux_native_read_retry(intel_dp,
1508 DP_LINK_STATUS_SIZE);
1512 static char *voltage_names[] = {
1513 "0.4V", "0.6V", "0.8V", "1.2V"
1515 static char *pre_emph_names[] = {
1516 "0dB", "3.5dB", "6dB", "9.5dB"
1518 static char *link_train_names[] = {
1519 "pattern 1", "pattern 2", "idle", "off"
1524 * These are source-specific values; current Intel hardware supports
1525 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1529 intel_dp_voltage_max(struct intel_dp *intel_dp)
1531 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1532 enum port port = dp_to_dig_port(intel_dp)->port;
1534 if (IS_VALLEYVIEW(dev))
1535 return DP_TRAIN_VOLTAGE_SWING_1200;
1536 else if (IS_GEN7(dev) && port == PORT_A)
1537 return DP_TRAIN_VOLTAGE_SWING_800;
1538 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1539 return DP_TRAIN_VOLTAGE_SWING_1200;
1541 return DP_TRAIN_VOLTAGE_SWING_800;
1545 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1547 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1548 enum port port = dp_to_dig_port(intel_dp)->port;
1551 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1552 case DP_TRAIN_VOLTAGE_SWING_400:
1553 return DP_TRAIN_PRE_EMPHASIS_9_5;
1554 case DP_TRAIN_VOLTAGE_SWING_600:
1555 return DP_TRAIN_PRE_EMPHASIS_6;
1556 case DP_TRAIN_VOLTAGE_SWING_800:
1557 return DP_TRAIN_PRE_EMPHASIS_3_5;
1558 case DP_TRAIN_VOLTAGE_SWING_1200:
1560 return DP_TRAIN_PRE_EMPHASIS_0;
1562 } else if (IS_VALLEYVIEW(dev)) {
1563 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1564 case DP_TRAIN_VOLTAGE_SWING_400:
1565 return DP_TRAIN_PRE_EMPHASIS_9_5;
1566 case DP_TRAIN_VOLTAGE_SWING_600:
1567 return DP_TRAIN_PRE_EMPHASIS_6;
1568 case DP_TRAIN_VOLTAGE_SWING_800:
1569 return DP_TRAIN_PRE_EMPHASIS_3_5;
1570 case DP_TRAIN_VOLTAGE_SWING_1200:
1572 return DP_TRAIN_PRE_EMPHASIS_0;
1574 } else if (IS_GEN7(dev) && port == PORT_A) {
1575 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1576 case DP_TRAIN_VOLTAGE_SWING_400:
1577 return DP_TRAIN_PRE_EMPHASIS_6;
1578 case DP_TRAIN_VOLTAGE_SWING_600:
1579 case DP_TRAIN_VOLTAGE_SWING_800:
1580 return DP_TRAIN_PRE_EMPHASIS_3_5;
1582 return DP_TRAIN_PRE_EMPHASIS_0;
1585 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1586 case DP_TRAIN_VOLTAGE_SWING_400:
1587 return DP_TRAIN_PRE_EMPHASIS_6;
1588 case DP_TRAIN_VOLTAGE_SWING_600:
1589 return DP_TRAIN_PRE_EMPHASIS_6;
1590 case DP_TRAIN_VOLTAGE_SWING_800:
1591 return DP_TRAIN_PRE_EMPHASIS_3_5;
1592 case DP_TRAIN_VOLTAGE_SWING_1200:
1594 return DP_TRAIN_PRE_EMPHASIS_0;
1599 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1601 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1602 struct drm_i915_private *dev_priv = dev->dev_private;
1603 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1604 unsigned long demph_reg_value, preemph_reg_value,
1605 uniqtranscale_reg_value;
1606 uint8_t train_set = intel_dp->train_set[0];
1607 int port = vlv_dport_to_channel(dport);
1609 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1610 case DP_TRAIN_PRE_EMPHASIS_0:
1611 preemph_reg_value = 0x0004000;
1612 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1613 case DP_TRAIN_VOLTAGE_SWING_400:
1614 demph_reg_value = 0x2B405555;
1615 uniqtranscale_reg_value = 0x552AB83A;
1617 case DP_TRAIN_VOLTAGE_SWING_600:
1618 demph_reg_value = 0x2B404040;
1619 uniqtranscale_reg_value = 0x5548B83A;
1621 case DP_TRAIN_VOLTAGE_SWING_800:
1622 demph_reg_value = 0x2B245555;
1623 uniqtranscale_reg_value = 0x5560B83A;
1625 case DP_TRAIN_VOLTAGE_SWING_1200:
1626 demph_reg_value = 0x2B405555;
1627 uniqtranscale_reg_value = 0x5598DA3A;
1633 case DP_TRAIN_PRE_EMPHASIS_3_5:
1634 preemph_reg_value = 0x0002000;
1635 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1636 case DP_TRAIN_VOLTAGE_SWING_400:
1637 demph_reg_value = 0x2B404040;
1638 uniqtranscale_reg_value = 0x5552B83A;
1640 case DP_TRAIN_VOLTAGE_SWING_600:
1641 demph_reg_value = 0x2B404848;
1642 uniqtranscale_reg_value = 0x5580B83A;
1644 case DP_TRAIN_VOLTAGE_SWING_800:
1645 demph_reg_value = 0x2B404040;
1646 uniqtranscale_reg_value = 0x55ADDA3A;
1652 case DP_TRAIN_PRE_EMPHASIS_6:
1653 preemph_reg_value = 0x0000000;
1654 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1655 case DP_TRAIN_VOLTAGE_SWING_400:
1656 demph_reg_value = 0x2B305555;
1657 uniqtranscale_reg_value = 0x5570B83A;
1659 case DP_TRAIN_VOLTAGE_SWING_600:
1660 demph_reg_value = 0x2B2B4040;
1661 uniqtranscale_reg_value = 0x55ADDA3A;
1667 case DP_TRAIN_PRE_EMPHASIS_9_5:
1668 preemph_reg_value = 0x0006000;
1669 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1670 case DP_TRAIN_VOLTAGE_SWING_400:
1671 demph_reg_value = 0x1B405555;
1672 uniqtranscale_reg_value = 0x55ADDA3A;
1682 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1683 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1684 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1685 uniqtranscale_reg_value);
1686 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1687 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1688 vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1689 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
1695 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1700 uint8_t voltage_max;
1701 uint8_t preemph_max;
1703 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1704 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1705 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1713 voltage_max = intel_dp_voltage_max(intel_dp);
1714 if (v >= voltage_max)
1715 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1717 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1718 if (p >= preemph_max)
1719 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1721 for (lane = 0; lane < 4; lane++)
1722 intel_dp->train_set[lane] = v | p;
1726 intel_gen4_signal_levels(uint8_t train_set)
1728 uint32_t signal_levels = 0;
1730 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1731 case DP_TRAIN_VOLTAGE_SWING_400:
1733 signal_levels |= DP_VOLTAGE_0_4;
1735 case DP_TRAIN_VOLTAGE_SWING_600:
1736 signal_levels |= DP_VOLTAGE_0_6;
1738 case DP_TRAIN_VOLTAGE_SWING_800:
1739 signal_levels |= DP_VOLTAGE_0_8;
1741 case DP_TRAIN_VOLTAGE_SWING_1200:
1742 signal_levels |= DP_VOLTAGE_1_2;
1745 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1746 case DP_TRAIN_PRE_EMPHASIS_0:
1748 signal_levels |= DP_PRE_EMPHASIS_0;
1750 case DP_TRAIN_PRE_EMPHASIS_3_5:
1751 signal_levels |= DP_PRE_EMPHASIS_3_5;
1753 case DP_TRAIN_PRE_EMPHASIS_6:
1754 signal_levels |= DP_PRE_EMPHASIS_6;
1756 case DP_TRAIN_PRE_EMPHASIS_9_5:
1757 signal_levels |= DP_PRE_EMPHASIS_9_5;
1760 return signal_levels;
1763 /* Gen6's DP voltage swing and pre-emphasis control */
1765 intel_gen6_edp_signal_levels(uint8_t train_set)
1767 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1768 DP_TRAIN_PRE_EMPHASIS_MASK);
1769 switch (signal_levels) {
1770 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1771 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1772 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1773 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1774 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1775 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1776 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1777 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1778 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1779 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1780 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1781 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1782 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1783 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1785 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1786 "0x%x\n", signal_levels);
1787 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1791 /* Gen7's DP voltage swing and pre-emphasis control */
1793 intel_gen7_edp_signal_levels(uint8_t train_set)
1795 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1796 DP_TRAIN_PRE_EMPHASIS_MASK);
1797 switch (signal_levels) {
1798 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1799 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1800 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1801 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1802 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1803 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1805 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1806 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1807 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1808 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1810 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1811 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1812 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1813 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1816 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1817 "0x%x\n", signal_levels);
1818 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1822 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1824 intel_hsw_signal_levels(uint8_t train_set)
1826 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1827 DP_TRAIN_PRE_EMPHASIS_MASK);
1828 switch (signal_levels) {
1829 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1830 return DDI_BUF_EMP_400MV_0DB_HSW;
1831 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1832 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1833 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1834 return DDI_BUF_EMP_400MV_6DB_HSW;
1835 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1836 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1838 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1839 return DDI_BUF_EMP_600MV_0DB_HSW;
1840 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1841 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1842 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1843 return DDI_BUF_EMP_600MV_6DB_HSW;
1845 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1846 return DDI_BUF_EMP_800MV_0DB_HSW;
1847 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1848 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1850 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1851 "0x%x\n", signal_levels);
1852 return DDI_BUF_EMP_400MV_0DB_HSW;
1856 /* Properly updates "DP" with the correct signal levels. */
1858 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1860 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1861 enum port port = intel_dig_port->port;
1862 struct drm_device *dev = intel_dig_port->base.base.dev;
1863 uint32_t signal_levels, mask;
1864 uint8_t train_set = intel_dp->train_set[0];
1867 signal_levels = intel_hsw_signal_levels(train_set);
1868 mask = DDI_BUF_EMP_MASK;
1869 } else if (IS_VALLEYVIEW(dev)) {
1870 signal_levels = intel_vlv_signal_levels(intel_dp);
1872 } else if (IS_GEN7(dev) && port == PORT_A) {
1873 signal_levels = intel_gen7_edp_signal_levels(train_set);
1874 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1875 } else if (IS_GEN6(dev) && port == PORT_A) {
1876 signal_levels = intel_gen6_edp_signal_levels(train_set);
1877 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1879 signal_levels = intel_gen4_signal_levels(train_set);
1880 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1883 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1885 *DP = (*DP & ~mask) | signal_levels;
1889 intel_dp_set_link_train(struct intel_dp *intel_dp,
1890 uint32_t dp_reg_value,
1891 uint8_t dp_train_pat)
1893 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1894 struct drm_device *dev = intel_dig_port->base.base.dev;
1895 struct drm_i915_private *dev_priv = dev->dev_private;
1896 enum port port = intel_dig_port->port;
1900 uint32_t temp = I915_READ(DP_TP_CTL(port));
1902 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1903 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1905 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1907 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1908 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1909 case DP_TRAINING_PATTERN_DISABLE:
1910 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1913 case DP_TRAINING_PATTERN_1:
1914 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1916 case DP_TRAINING_PATTERN_2:
1917 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1919 case DP_TRAINING_PATTERN_3:
1920 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1923 I915_WRITE(DP_TP_CTL(port), temp);
1925 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
1926 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1928 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1929 case DP_TRAINING_PATTERN_DISABLE:
1930 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1932 case DP_TRAINING_PATTERN_1:
1933 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1935 case DP_TRAINING_PATTERN_2:
1936 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1938 case DP_TRAINING_PATTERN_3:
1939 DRM_ERROR("DP training pattern 3 not supported\n");
1940 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1945 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1947 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1948 case DP_TRAINING_PATTERN_DISABLE:
1949 dp_reg_value |= DP_LINK_TRAIN_OFF;
1951 case DP_TRAINING_PATTERN_1:
1952 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1954 case DP_TRAINING_PATTERN_2:
1955 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1957 case DP_TRAINING_PATTERN_3:
1958 DRM_ERROR("DP training pattern 3 not supported\n");
1959 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1964 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1965 POSTING_READ(intel_dp->output_reg);
1967 intel_dp_aux_native_write_1(intel_dp,
1968 DP_TRAINING_PATTERN_SET,
1971 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1972 DP_TRAINING_PATTERN_DISABLE) {
1973 ret = intel_dp_aux_native_write(intel_dp,
1974 DP_TRAINING_LANE0_SET,
1975 intel_dp->train_set,
1976 intel_dp->lane_count);
1977 if (ret != intel_dp->lane_count)
1984 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
1986 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1987 struct drm_device *dev = intel_dig_port->base.base.dev;
1988 struct drm_i915_private *dev_priv = dev->dev_private;
1989 enum port port = intel_dig_port->port;
1995 val = I915_READ(DP_TP_CTL(port));
1996 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1997 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
1998 I915_WRITE(DP_TP_CTL(port), val);
2001 * On PORT_A we can have only eDP in SST mode. There the only reason
2002 * we need to set idle transmission mode is to work around a HW issue
2003 * where we enable the pipe while not in idle link-training mode.
2004 * In this case there is requirement to wait for a minimum number of
2005 * idle patterns to be sent.
2010 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2012 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2015 /* Enable corresponding port and start training pattern 1 */
2017 intel_dp_start_link_train(struct intel_dp *intel_dp)
2019 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2020 struct drm_device *dev = encoder->dev;
2023 bool clock_recovery = false;
2024 int voltage_tries, loop_tries;
2025 uint32_t DP = intel_dp->DP;
2028 intel_ddi_prepare_link_retrain(encoder);
2030 /* Write the link configuration data */
2031 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2032 intel_dp->link_configuration,
2033 DP_LINK_CONFIGURATION_SIZE);
2037 memset(intel_dp->train_set, 0, 4);
2041 clock_recovery = false;
2043 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2044 uint8_t link_status[DP_LINK_STATUS_SIZE];
2046 intel_dp_set_signal_levels(intel_dp, &DP);
2048 /* Set training pattern 1 */
2049 if (!intel_dp_set_link_train(intel_dp, DP,
2050 DP_TRAINING_PATTERN_1 |
2051 DP_LINK_SCRAMBLING_DISABLE))
2054 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2055 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2056 DRM_ERROR("failed to get link status\n");
2060 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2061 DRM_DEBUG_KMS("clock recovery OK\n");
2062 clock_recovery = true;
2066 /* Check to see if we've tried the max voltage */
2067 for (i = 0; i < intel_dp->lane_count; i++)
2068 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2070 if (i == intel_dp->lane_count) {
2072 if (loop_tries == 5) {
2073 DRM_DEBUG_KMS("too many full retries, give up\n");
2076 memset(intel_dp->train_set, 0, 4);
2081 /* Check to see if we've tried the same voltage 5 times */
2082 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2084 if (voltage_tries == 5) {
2085 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2090 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2092 /* Compute new intel_dp->train_set as requested by target */
2093 intel_get_adjust_train(intel_dp, link_status);
2100 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2102 bool channel_eq = false;
2103 int tries, cr_tries;
2104 uint32_t DP = intel_dp->DP;
2106 /* channel equalization */
2111 uint8_t link_status[DP_LINK_STATUS_SIZE];
2114 DRM_ERROR("failed to train DP, aborting\n");
2115 intel_dp_link_down(intel_dp);
2119 intel_dp_set_signal_levels(intel_dp, &DP);
2121 /* channel eq pattern */
2122 if (!intel_dp_set_link_train(intel_dp, DP,
2123 DP_TRAINING_PATTERN_2 |
2124 DP_LINK_SCRAMBLING_DISABLE))
2127 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2128 if (!intel_dp_get_link_status(intel_dp, link_status))
2131 /* Make sure clock is still ok */
2132 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2133 intel_dp_start_link_train(intel_dp);
2138 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2143 /* Try 5 times, then try clock recovery if that fails */
2145 intel_dp_link_down(intel_dp);
2146 intel_dp_start_link_train(intel_dp);
2152 /* Compute new intel_dp->train_set as requested by target */
2153 intel_get_adjust_train(intel_dp, link_status);
2157 intel_dp_set_idle_link_train(intel_dp);
2162 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2166 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2168 intel_dp_set_link_train(intel_dp, intel_dp->DP,
2169 DP_TRAINING_PATTERN_DISABLE);
2173 intel_dp_link_down(struct intel_dp *intel_dp)
2175 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2176 enum port port = intel_dig_port->port;
2177 struct drm_device *dev = intel_dig_port->base.base.dev;
2178 struct drm_i915_private *dev_priv = dev->dev_private;
2179 struct intel_crtc *intel_crtc =
2180 to_intel_crtc(intel_dig_port->base.base.crtc);
2181 uint32_t DP = intel_dp->DP;
2184 * DDI code has a strict mode set sequence and we should try to respect
2185 * it, otherwise we might hang the machine in many different ways. So we
2186 * really should be disabling the port only on a complete crtc_disable
2187 * sequence. This function is just called under two conditions on DDI
2189 * - Link train failed while doing crtc_enable, and on this case we
2190 * really should respect the mode set sequence and wait for a
2192 * - Someone turned the monitor off and intel_dp_check_link_status
2193 * called us. We don't need to disable the whole port on this case, so
2194 * when someone turns the monitor on again,
2195 * intel_ddi_prepare_link_retrain will take care of redoing the link
2201 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2204 DRM_DEBUG_KMS("\n");
2206 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2207 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2208 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2210 DP &= ~DP_LINK_TRAIN_MASK;
2211 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2213 POSTING_READ(intel_dp->output_reg);
2215 /* We don't really know why we're doing this */
2216 intel_wait_for_vblank(dev, intel_crtc->pipe);
2218 if (HAS_PCH_IBX(dev) &&
2219 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2220 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2222 /* Hardware workaround: leaving our transcoder select
2223 * set to transcoder B while it's off will prevent the
2224 * corresponding HDMI output on transcoder A.
2226 * Combine this with another hardware workaround:
2227 * transcoder select bit can only be cleared while the
2230 DP &= ~DP_PIPEB_SELECT;
2231 I915_WRITE(intel_dp->output_reg, DP);
2233 /* Changes to enable or select take place the vblank
2234 * after being written.
2236 if (WARN_ON(crtc == NULL)) {
2237 /* We should never try to disable a port without a crtc
2238 * attached. For paranoia keep the code around for a
2240 POSTING_READ(intel_dp->output_reg);
2243 intel_wait_for_vblank(dev, intel_crtc->pipe);
2246 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2247 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2248 POSTING_READ(intel_dp->output_reg);
2249 msleep(intel_dp->panel_power_down_delay);
2253 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2255 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2257 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2258 sizeof(intel_dp->dpcd)) == 0)
2259 return false; /* aux transfer failed */
2261 ksnprintf(dpcd_hex_dump,
2262 sizeof(dpcd_hex_dump),
2263 "%02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2264 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2265 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2266 intel_dp->dpcd[6], intel_dp->dpcd[7]);
2268 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2270 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2271 return false; /* DPCD not present */
2273 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2274 DP_DWN_STRM_PORT_PRESENT))
2275 return true; /* native DP sink */
2277 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2278 return true; /* no per-port downstream info */
2280 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2281 intel_dp->downstream_ports,
2282 DP_MAX_DOWNSTREAM_PORTS) == 0)
2283 return false; /* downstream port status fetch failed */
2289 intel_dp_probe_oui(struct intel_dp *intel_dp)
2293 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2296 ironlake_edp_panel_vdd_on(intel_dp);
2298 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2299 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2300 buf[0], buf[1], buf[2]);
2302 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2303 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2304 buf[0], buf[1], buf[2]);
2306 ironlake_edp_panel_vdd_off(intel_dp, false);
2310 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2314 ret = intel_dp_aux_native_read_retry(intel_dp,
2315 DP_DEVICE_SERVICE_IRQ_VECTOR,
2316 sink_irq_vector, 1);
2324 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2326 /* NAK by default */
2327 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2331 * According to DP spec
2334 * 2. Configure link according to Receiver Capabilities
2335 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2336 * 4. Check link status on receipt of hot-plug interrupt
2340 intel_dp_check_link_status(struct intel_dp *intel_dp)
2342 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2344 u8 link_status[DP_LINK_STATUS_SIZE];
2346 if (!intel_encoder->connectors_active)
2349 if (WARN_ON(!intel_encoder->base.crtc))
2352 /* Try to read receiver status if the link appears to be up */
2353 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2354 intel_dp_link_down(intel_dp);
2358 /* Now read the DPCD to see if it's actually running */
2359 if (!intel_dp_get_dpcd(intel_dp)) {
2360 intel_dp_link_down(intel_dp);
2364 /* Try to read the source of the interrupt */
2365 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2366 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2367 /* Clear interrupt source */
2368 intel_dp_aux_native_write_1(intel_dp,
2369 DP_DEVICE_SERVICE_IRQ_VECTOR,
2372 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2373 intel_dp_handle_test_request(intel_dp);
2374 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2375 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2378 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2379 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2380 drm_get_encoder_name(&intel_encoder->base));
2381 intel_dp_start_link_train(intel_dp);
2382 intel_dp_complete_link_train(intel_dp);
2383 intel_dp_stop_link_train(intel_dp);
2387 /* XXX this is probably wrong for multiple downstream ports */
2388 static enum drm_connector_status
2389 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2391 uint8_t *dpcd = intel_dp->dpcd;
2395 if (!intel_dp_get_dpcd(intel_dp))
2396 return connector_status_disconnected;
2398 /* if there's no downstream port, we're done */
2399 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2400 return connector_status_connected;
2402 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2403 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2406 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2408 return connector_status_unknown;
2409 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2410 : connector_status_disconnected;
2413 /* If no HPD, poke DDC gently */
2414 if (drm_probe_ddc(intel_dp->adapter))
2415 return connector_status_connected;
2417 /* Well we tried, say unknown for unreliable port types */
2418 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2419 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2420 return connector_status_unknown;
2422 /* Anything else is out of spec, warn and ignore */
2423 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2424 return connector_status_disconnected;
2427 static enum drm_connector_status
2428 ironlake_dp_detect(struct intel_dp *intel_dp)
2430 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2431 struct drm_i915_private *dev_priv = dev->dev_private;
2432 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2433 enum drm_connector_status status;
2435 /* Can't disconnect eDP, but you can close the lid... */
2436 if (is_edp(intel_dp)) {
2437 status = intel_panel_detect(dev);
2438 if (status == connector_status_unknown)
2439 status = connector_status_connected;
2443 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2444 return connector_status_disconnected;
2446 return intel_dp_detect_dpcd(intel_dp);
2449 static enum drm_connector_status
2450 g4x_dp_detect(struct intel_dp *intel_dp)
2452 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2453 struct drm_i915_private *dev_priv = dev->dev_private;
2454 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2457 /* Can't disconnect eDP, but you can close the lid... */
2458 if (is_edp(intel_dp)) {
2459 enum drm_connector_status status;
2461 status = intel_panel_detect(dev);
2462 if (status == connector_status_unknown)
2463 status = connector_status_connected;
2467 switch (intel_dig_port->port) {
2469 bit = PORTB_HOTPLUG_LIVE_STATUS;
2472 bit = PORTC_HOTPLUG_LIVE_STATUS;
2475 bit = PORTD_HOTPLUG_LIVE_STATUS;
2478 return connector_status_unknown;
2481 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2482 return connector_status_disconnected;
2484 return intel_dp_detect_dpcd(intel_dp);
2487 static struct edid *
2488 intel_dp_get_edid(struct drm_connector *connector, struct device *adapter)
2490 struct intel_connector *intel_connector = to_intel_connector(connector);
2492 /* use cached edid if we have one */
2493 if (intel_connector->edid) {
2498 if (IS_ERR(intel_connector->edid))
2501 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2502 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
2509 return drm_get_edid(connector, adapter);
2513 intel_dp_get_edid_modes(struct drm_connector *connector, struct device *adapter)
2515 struct intel_connector *intel_connector = to_intel_connector(connector);
2517 /* use cached edid if we have one */
2518 if (intel_connector->edid) {
2520 if (IS_ERR(intel_connector->edid))
2523 return intel_connector_update_modes(connector,
2524 intel_connector->edid);
2527 return intel_ddc_get_modes(connector, adapter);
2530 static enum drm_connector_status
2531 intel_dp_detect(struct drm_connector *connector, bool force)
2533 struct intel_dp *intel_dp = intel_attached_dp(connector);
2534 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2535 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2536 struct drm_device *dev = connector->dev;
2537 enum drm_connector_status status;
2538 struct edid *edid = NULL;
2540 intel_dp->has_audio = false;
2542 if (HAS_PCH_SPLIT(dev))
2543 status = ironlake_dp_detect(intel_dp);
2545 status = g4x_dp_detect(intel_dp);
2547 if (status != connector_status_connected)
2550 intel_dp_probe_oui(intel_dp);
2552 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2553 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2555 edid = intel_dp_get_edid(connector, intel_dp->adapter);
2557 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2562 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2563 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2564 return connector_status_connected;
2567 static int intel_dp_get_modes(struct drm_connector *connector)
2569 struct intel_dp *intel_dp = intel_attached_dp(connector);
2570 struct intel_connector *intel_connector = to_intel_connector(connector);
2571 struct drm_device *dev = connector->dev;
2574 /* We should parse the EDID data and find out if it has an audio sink
2577 ret = intel_dp_get_edid_modes(connector, intel_dp->adapter);
2581 /* if eDP has no EDID, fall back to fixed mode */
2582 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2583 struct drm_display_mode *mode;
2584 mode = drm_mode_duplicate(dev,
2585 intel_connector->panel.fixed_mode);
2587 drm_mode_probed_add(connector, mode);
2595 intel_dp_detect_audio(struct drm_connector *connector)
2597 struct intel_dp *intel_dp = intel_attached_dp(connector);
2599 bool has_audio = false;
2601 edid = intel_dp_get_edid(connector, intel_dp->adapter);
2603 has_audio = drm_detect_monitor_audio(edid);
2611 intel_dp_set_property(struct drm_connector *connector,
2612 struct drm_property *property,
2615 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2616 struct intel_connector *intel_connector = to_intel_connector(connector);
2617 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2618 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2621 ret = drm_object_property_set_value(&connector->base, property, val);
2625 if (property == dev_priv->force_audio_property) {
2629 if (i == intel_dp->force_audio)
2632 intel_dp->force_audio = i;
2634 if (i == HDMI_AUDIO_AUTO)
2635 has_audio = intel_dp_detect_audio(connector);
2637 has_audio = (i == HDMI_AUDIO_ON);
2639 if (has_audio == intel_dp->has_audio)
2642 intel_dp->has_audio = has_audio;
2646 if (property == dev_priv->broadcast_rgb_property) {
2647 bool old_auto = intel_dp->color_range_auto;
2648 uint32_t old_range = intel_dp->color_range;
2651 case INTEL_BROADCAST_RGB_AUTO:
2652 intel_dp->color_range_auto = true;
2654 case INTEL_BROADCAST_RGB_FULL:
2655 intel_dp->color_range_auto = false;
2656 intel_dp->color_range = 0;
2658 case INTEL_BROADCAST_RGB_LIMITED:
2659 intel_dp->color_range_auto = false;
2660 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2666 if (old_auto == intel_dp->color_range_auto &&
2667 old_range == intel_dp->color_range)
2673 if (is_edp(intel_dp) &&
2674 property == connector->dev->mode_config.scaling_mode_property) {
2675 if (val == DRM_MODE_SCALE_NONE) {
2676 DRM_DEBUG_KMS("no scaling not supported\n");
2680 if (intel_connector->panel.fitting_mode == val) {
2681 /* the eDP scaling property is not changed */
2684 intel_connector->panel.fitting_mode = val;
2692 if (intel_encoder->base.crtc)
2693 intel_crtc_restore_mode(intel_encoder->base.crtc);
2699 intel_dp_connector_destroy(struct drm_connector *connector)
2701 struct intel_connector *intel_connector = to_intel_connector(connector);
2703 if (!IS_ERR_OR_NULL(intel_connector->edid))
2704 kfree(intel_connector->edid);
2706 /* Can't call is_edp() since the encoder may have been destroyed
2708 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2709 intel_panel_fini(&intel_connector->panel);
2711 drm_sysfs_connector_remove(connector);
2712 drm_connector_cleanup(connector);
2716 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2718 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2719 struct intel_dp *intel_dp = &intel_dig_port->dp;
2720 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2722 if (intel_dp->dp_iic_bus != NULL) {
2723 if (intel_dp->adapter != NULL) {
2724 device_delete_child(intel_dp->dp_iic_bus,
2727 device_delete_child(dev->dev, intel_dp->dp_iic_bus);
2729 drm_encoder_cleanup(encoder);
2730 if (is_edp(intel_dp)) {
2731 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2732 mutex_lock(&dev->mode_config.mutex);
2733 ironlake_panel_vdd_off_sync(intel_dp);
2734 mutex_unlock(&dev->mode_config.mutex);
2736 kfree(intel_dig_port);
2739 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2740 .mode_set = intel_dp_mode_set,
2743 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2744 .dpms = intel_connector_dpms,
2745 .detect = intel_dp_detect,
2746 .fill_modes = drm_helper_probe_single_connector_modes,
2747 .set_property = intel_dp_set_property,
2748 .destroy = intel_dp_connector_destroy,
2751 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2752 .get_modes = intel_dp_get_modes,
2753 .mode_valid = intel_dp_mode_valid,
2754 .best_encoder = intel_best_encoder,
2757 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2758 .destroy = intel_dp_encoder_destroy,
2762 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2764 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2766 intel_dp_check_link_status(intel_dp);
2769 /* Return which DP Port should be selected for Transcoder DP control */
2771 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2773 struct drm_device *dev = crtc->dev;
2774 struct intel_encoder *intel_encoder;
2775 struct intel_dp *intel_dp;
2777 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2778 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2780 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2781 intel_encoder->type == INTEL_OUTPUT_EDP)
2782 return intel_dp->output_reg;
2788 /* check the VBT to see whether the eDP is on DP-D port */
2789 bool intel_dpd_is_edp(struct drm_device *dev)
2791 struct drm_i915_private *dev_priv = dev->dev_private;
2792 struct child_device_config *p_child;
2795 if (!dev_priv->vbt.child_dev_num)
2798 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
2799 p_child = dev_priv->vbt.child_dev + i;
2801 if (p_child->dvo_port == PORT_IDPD &&
2802 p_child->device_type == DEVICE_TYPE_eDP)
2809 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2811 struct intel_connector *intel_connector = to_intel_connector(connector);
2813 intel_attach_force_audio_property(connector);
2814 intel_attach_broadcast_rgb_property(connector);
2815 intel_dp->color_range_auto = true;
2817 if (is_edp(intel_dp)) {
2818 drm_mode_create_scaling_mode_property(connector->dev);
2819 drm_object_attach_property(
2821 connector->dev->mode_config.scaling_mode_property,
2822 DRM_MODE_SCALE_ASPECT);
2823 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2828 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2829 struct intel_dp *intel_dp,
2830 struct edp_power_seq *out)
2832 struct drm_i915_private *dev_priv = dev->dev_private;
2833 struct edp_power_seq cur, vbt, spec, final;
2834 u32 pp_on, pp_off, pp_div, pp;
2835 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2837 if (HAS_PCH_SPLIT(dev)) {
2838 pp_control_reg = PCH_PP_CONTROL;
2839 pp_on_reg = PCH_PP_ON_DELAYS;
2840 pp_off_reg = PCH_PP_OFF_DELAYS;
2841 pp_div_reg = PCH_PP_DIVISOR;
2843 pp_control_reg = PIPEA_PP_CONTROL;
2844 pp_on_reg = PIPEA_PP_ON_DELAYS;
2845 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2846 pp_div_reg = PIPEA_PP_DIVISOR;
2849 /* Workaround: Need to write PP_CONTROL with the unlock key as
2850 * the very first thing. */
2851 pp = ironlake_get_pp_control(intel_dp);
2852 I915_WRITE(pp_control_reg, pp);
2854 pp_on = I915_READ(pp_on_reg);
2855 pp_off = I915_READ(pp_off_reg);
2856 pp_div = I915_READ(pp_div_reg);
2858 /* Pull timing values out of registers */
2859 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2860 PANEL_POWER_UP_DELAY_SHIFT;
2862 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2863 PANEL_LIGHT_ON_DELAY_SHIFT;
2865 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2866 PANEL_LIGHT_OFF_DELAY_SHIFT;
2868 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2869 PANEL_POWER_DOWN_DELAY_SHIFT;
2871 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2872 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2874 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2875 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2877 vbt = dev_priv->vbt.edp_pps;
2879 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2880 * our hw here, which are all in 100usec. */
2881 spec.t1_t3 = 210 * 10;
2882 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2883 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2884 spec.t10 = 500 * 10;
2885 /* This one is special and actually in units of 100ms, but zero
2886 * based in the hw (so we need to add 100 ms). But the sw vbt
2887 * table multiplies it with 1000 to make it in units of 100usec,
2889 spec.t11_t12 = (510 + 100) * 10;
2891 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2892 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2894 /* Use the max of the register settings and vbt. If both are
2895 * unset, fall back to the spec limits. */
2896 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2898 max(cur.field, vbt.field))
2899 assign_final(t1_t3);
2903 assign_final(t11_t12);
2906 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2907 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2908 intel_dp->backlight_on_delay = get_delay(t8);
2909 intel_dp->backlight_off_delay = get_delay(t9);
2910 intel_dp->panel_power_down_delay = get_delay(t10);
2911 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2914 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2915 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2916 intel_dp->panel_power_cycle_delay);
2918 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2919 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2926 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2927 struct intel_dp *intel_dp,
2928 struct edp_power_seq *seq)
2930 struct drm_i915_private *dev_priv = dev->dev_private;
2931 u32 pp_on, pp_off, pp_div, port_sel = 0;
2932 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2933 int pp_on_reg, pp_off_reg, pp_div_reg;
2935 if (HAS_PCH_SPLIT(dev)) {
2936 pp_on_reg = PCH_PP_ON_DELAYS;
2937 pp_off_reg = PCH_PP_OFF_DELAYS;
2938 pp_div_reg = PCH_PP_DIVISOR;
2940 pp_on_reg = PIPEA_PP_ON_DELAYS;
2941 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2942 pp_div_reg = PIPEA_PP_DIVISOR;
2945 /* And finally store the new values in the power sequencer. */
2946 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2947 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2948 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2949 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2950 /* Compute the divisor for the pp clock, simply match the Bspec
2952 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
2953 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2954 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2956 /* Haswell doesn't have any port selection bits for the panel
2957 * power sequencer any more. */
2958 if (IS_VALLEYVIEW(dev)) {
2959 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2960 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2961 if (dp_to_dig_port(intel_dp)->port == PORT_A)
2962 port_sel = PANEL_POWER_PORT_DP_A;
2964 port_sel = PANEL_POWER_PORT_DP_D;
2969 I915_WRITE(pp_on_reg, pp_on);
2970 I915_WRITE(pp_off_reg, pp_off);
2971 I915_WRITE(pp_div_reg, pp_div);
2973 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2974 I915_READ(pp_on_reg),
2975 I915_READ(pp_off_reg),
2976 I915_READ(pp_div_reg));
2979 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
2980 struct intel_connector *intel_connector)
2982 struct drm_connector *connector = &intel_connector->base;
2983 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2984 struct drm_device *dev = intel_dig_port->base.base.dev;
2985 struct drm_i915_private *dev_priv = dev->dev_private;
2986 struct drm_display_mode *fixed_mode = NULL;
2987 struct edp_power_seq power_seq = { 0 };
2989 struct drm_display_mode *scan;
2992 if (!is_edp(intel_dp))
2995 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2997 /* Cache DPCD and EDID for edp. */
2998 ironlake_edp_panel_vdd_on(intel_dp);
2999 has_dpcd = intel_dp_get_dpcd(intel_dp);
3000 ironlake_edp_panel_vdd_off(intel_dp, false);
3003 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3004 dev_priv->no_aux_handshake =
3005 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3006 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3008 /* if this fails, presume the device is a ghost */
3009 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3013 /* We now know it's not a ghost, init power sequence regs. */
3014 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3017 ironlake_edp_panel_vdd_on(intel_dp);
3018 edid = drm_get_edid(connector, intel_dp->adapter);
3020 if (drm_add_edid_modes(connector, edid)) {
3021 drm_mode_connector_update_edid_property(connector,
3023 drm_edid_to_eld(connector, edid);
3026 edid = ERR_PTR(-EINVAL);
3029 edid = ERR_PTR(-ENOENT);
3031 intel_connector->edid = edid;
3033 /* prefer fixed mode from EDID if available */
3034 list_for_each_entry(scan, &connector->probed_modes, head) {
3035 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3036 fixed_mode = drm_mode_duplicate(dev, scan);
3041 /* fallback to VBT if available for eDP */
3042 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3043 fixed_mode = drm_mode_duplicate(dev,
3044 dev_priv->vbt.lfp_lvds_vbt_mode);
3046 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3049 ironlake_edp_panel_vdd_off(intel_dp, false);
3051 intel_panel_init(&intel_connector->panel, fixed_mode);
3052 intel_panel_setup_backlight(connector);
3058 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3059 struct intel_connector *intel_connector)
3061 struct drm_connector *connector = &intel_connector->base;
3062 struct intel_dp *intel_dp = &intel_dig_port->dp;
3063 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3064 struct drm_device *dev = intel_encoder->base.dev;
3065 struct drm_i915_private *dev_priv = dev->dev_private;
3066 enum port port = intel_dig_port->port;
3067 const char *name = NULL;
3070 /* Preserve the current hw state. */
3071 intel_dp->DP = I915_READ(intel_dp->output_reg);
3072 intel_dp->attached_connector = intel_connector;
3074 type = DRM_MODE_CONNECTOR_DisplayPort;
3076 * FIXME : We need to initialize built-in panels before external panels.
3077 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3081 type = DRM_MODE_CONNECTOR_eDP;
3084 if (IS_VALLEYVIEW(dev))
3085 type = DRM_MODE_CONNECTOR_eDP;
3088 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3089 type = DRM_MODE_CONNECTOR_eDP;
3091 default: /* silence GCC warning */
3096 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3097 * for DP the encoder type can be set by the caller to
3098 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3100 if (type == DRM_MODE_CONNECTOR_eDP)
3101 intel_encoder->type = INTEL_OUTPUT_EDP;
3103 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3104 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3107 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3108 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3110 connector->interlace_allowed = true;
3111 connector->doublescan_allowed = 0;
3113 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3114 ironlake_panel_vdd_work);
3116 intel_connector_attach_encoder(intel_connector, intel_encoder);
3117 drm_sysfs_connector_add(connector);
3120 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3122 intel_connector->get_hw_state = intel_connector_get_hw_state;
3124 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3126 switch (intel_dig_port->port) {
3128 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3131 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3134 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3137 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3144 /* Set up the DDC bus. */
3147 intel_encoder->hpd_pin = HPD_PORT_A;
3151 intel_encoder->hpd_pin = HPD_PORT_B;
3155 intel_encoder->hpd_pin = HPD_PORT_C;
3159 intel_encoder->hpd_pin = HPD_PORT_D;
3166 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3167 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3168 error, port_name(port));
3170 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
3172 i2c_del_adapter(&intel_dp->adapter);
3174 if (is_edp(intel_dp)) {
3175 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3176 mutex_lock(&dev->mode_config.mutex);
3177 ironlake_panel_vdd_off_sync(intel_dp);
3178 mutex_unlock(&dev->mode_config.mutex);
3180 drm_sysfs_connector_remove(connector);
3181 drm_connector_cleanup(connector);
3185 intel_dp_add_properties(intel_dp, connector);
3187 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3188 * 0xd. Failure to do so will result in spurious interrupts being
3189 * generated on the port when a cable is not attached.
3191 if (IS_G4X(dev) && !IS_GM45(dev)) {
3192 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3193 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3200 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3202 struct intel_digital_port *intel_dig_port;
3203 struct intel_encoder *intel_encoder;
3204 struct drm_encoder *encoder;
3205 struct intel_connector *intel_connector;
3207 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3208 if (!intel_dig_port)
3211 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3212 if (!intel_connector) {
3213 kfree(intel_dig_port);
3217 intel_encoder = &intel_dig_port->base;
3218 encoder = &intel_encoder->base;
3220 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3221 DRM_MODE_ENCODER_TMDS);
3222 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
3224 intel_encoder->compute_config = intel_dp_compute_config;
3225 intel_encoder->enable = intel_enable_dp;
3226 intel_encoder->pre_enable = intel_pre_enable_dp;
3227 intel_encoder->disable = intel_disable_dp;
3228 intel_encoder->post_disable = intel_post_disable_dp;
3229 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3230 intel_encoder->get_config = intel_dp_get_config;
3231 if (IS_VALLEYVIEW(dev))
3232 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
3234 intel_dig_port->port = port;
3235 intel_dig_port->dp.output_reg = output_reg;
3237 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3238 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3239 intel_encoder->cloneable = false;
3240 intel_encoder->hot_plug = intel_dp_hot_plug;
3242 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3243 drm_encoder_cleanup(encoder);
3244 kfree(intel_dig_port);
3245 kfree(intel_connector);