2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/kernel.h>
32 #include <sys/machintr.h>
33 #include <machine/globaldata.h>
34 #include <machine/smp.h>
35 #include <machine/md_var.h>
36 #include <machine/pmap.h>
37 #include <machine/specialreg.h>
38 #include <machine_base/apic/lapic.h>
39 #include <machine_base/apic/ioapic.h>
40 #include <machine_base/apic/ioapic_abi.h>
41 #include <machine_base/apic/apicvar.h>
42 #include <machine_base/icu/icu_var.h>
43 #include <machine/segments.h>
44 #include <sys/thread2.h>
46 #include <machine/cputypes.h>
47 #include <machine/intr_machdep.h>
51 volatile lapic_t *lapic;
53 static void lapic_timer_calibrate(void);
54 static void lapic_timer_set_divisor(int);
55 static void lapic_timer_fixup_handler(void *);
56 static void lapic_timer_restart_handler(void *);
58 void lapic_timer_process(void);
59 void lapic_timer_process_frame(struct intrframe *);
60 void lapic_timer_always(struct intrframe *);
62 static int lapic_timer_enable = 1;
63 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
65 static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
66 static void lapic_timer_intr_enable(struct cputimer_intr *);
67 static void lapic_timer_intr_restart(struct cputimer_intr *);
68 static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
70 static struct cputimer_intr lapic_cputimer_intr = {
72 .reload = lapic_timer_intr_reload,
73 .enable = lapic_timer_intr_enable,
74 .config = cputimer_intr_default_config,
75 .restart = lapic_timer_intr_restart,
76 .pmfixup = lapic_timer_intr_pmfixup,
77 .initclock = cputimer_intr_default_initclock,
78 .next = SLIST_ENTRY_INITIALIZER,
80 .type = CPUTIMER_INTR_LAPIC,
81 .prio = CPUTIMER_INTR_PRIO_LAPIC,
82 .caps = CPUTIMER_INTR_CAP_NONE
85 static int lapic_timer_divisor_idx = -1;
86 static const uint32_t lapic_timer_divisors[] = {
87 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
88 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
90 #define APIC_TIMER_NDIVISORS (int)(NELEM(lapic_timer_divisors))
93 * APIC ID <-> CPU ID mapping structures.
95 int cpu_id_to_apic_id[NAPICID];
96 int apic_id_to_cpu_id[NAPICID];
100 * Enable LAPIC, configure interrupts.
103 lapic_init(boolean_t bsp)
111 * Since IDT is shared between BSP and APs, these vectors
112 * only need to be installed once; we do it on BSP.
115 if (cpu_vendor_id == CPU_VENDOR_AMD &&
116 CPUID_TO_FAMILY(cpu_id) >= 0xf) {
120 * Set the LINTEN bit in the HyperTransport
121 * Transaction Control Register.
123 * This will cause EXTINT and NMI interrupts
124 * routed over the hypertransport bus to be
125 * fed into the LAPIC LINT0/LINT1. If the bit
126 * isn't set, the interrupts will go to the
127 * general cpu INTR/NMI pins. On a dual-core
128 * cpu the interrupt winds up going to BOTH cpus.
129 * The first cpu that does the interrupt ack
130 * cycle will get the correct interrupt. The
131 * second cpu that does it will get a spurious
132 * interrupt vector (typically IRQ 7).
135 (1 << 31) | /* enable */
136 (0 << 16) | /* bus */
137 (0x18 << 11) | /* dev (cpu + 0x18) */
138 (0 << 8) | /* func */
142 if ((tcr & 0x00010000) == 0) {
143 kprintf("LAPIC: AMD LINTEN on\n");
144 outl(0xcfc, tcr|0x00010000);
149 /* Install a 'Spurious INTerrupt' vector */
150 setidt_global(XSPURIOUSINT_OFFSET, Xspuriousint,
151 SDT_SYSIGT, SEL_KPL, 0);
153 /* Install a timer vector */
154 setidt_global(XTIMER_OFFSET, Xtimer,
155 SDT_SYSIGT, SEL_KPL, 0);
157 /* Install an inter-CPU IPI for TLB invalidation */
158 setidt_global(XINVLTLB_OFFSET, Xinvltlb,
159 SDT_SYSIGT, SEL_KPL, 0);
161 /* Install an inter-CPU IPI for IPIQ messaging */
162 setidt_global(XIPIQ_OFFSET, Xipiq,
163 SDT_SYSIGT, SEL_KPL, 0);
165 /* Install an inter-CPU IPI for CPU stop/restart */
166 setidt_global(XCPUSTOP_OFFSET, Xcpustop,
167 SDT_SYSIGT, SEL_KPL, 0);
171 * Setup LINT0 as ExtINT on the BSP. This is theoretically an
172 * aggregate interrupt input from the 8259. The INTA cycle
173 * will be routed to the external controller (the 8259) which
174 * is expected to supply the vector.
176 * Must be setup edge triggered, active high.
178 * Disable LINT0 on BSP, if I/O APIC is enabled.
180 * Disable LINT0 on the APs. It doesn't matter what delivery
181 * mode we use because we leave it masked.
183 temp = lapic->lvt_lint0;
184 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
185 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
187 temp |= APIC_LVT_DM_EXTINT;
189 temp |= APIC_LVT_MASKED;
191 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
193 lapic->lvt_lint0 = temp;
196 * Setup LINT1 as NMI.
198 * Must be setup edge trigger, active high.
200 * Enable LINT1 on BSP, if I/O APIC is enabled.
202 * Disable LINT1 on the APs.
204 temp = lapic->lvt_lint1;
205 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
206 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
207 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
208 if (bsp && ioapic_enable)
209 temp &= ~APIC_LVT_MASKED;
210 lapic->lvt_lint1 = temp;
213 * Mask the LAPIC error interrupt, LAPIC performance counter
216 lapic->lvt_error = lapic->lvt_error | APIC_LVT_MASKED;
217 lapic->lvt_pcint = lapic->lvt_pcint | APIC_LVT_MASKED;
220 * Set LAPIC timer vector and mask the LAPIC timer interrupt.
222 timer = lapic->lvt_timer;
223 timer &= ~APIC_LVTT_VECTOR;
224 timer |= XTIMER_OFFSET;
225 timer |= APIC_LVTT_MASKED;
226 lapic->lvt_timer = timer;
229 * Set the Task Priority Register as needed. At the moment allow
230 * interrupts on all cpus (the APs will remain CLId until they are
234 temp &= ~APIC_TPR_PRIO; /* clear priority field */
241 temp |= APIC_SVR_ENABLE; /* enable the LAPIC */
242 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
245 * Set the spurious interrupt vector. The low 4 bits of the vector
248 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
249 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
250 temp &= ~APIC_SVR_VECTOR;
251 temp |= XSPURIOUSINT_OFFSET;
256 * Pump out a few EOIs to clean out interrupts that got through
257 * before we were able to set the TPR.
264 lapic_timer_calibrate();
265 if (lapic_timer_enable) {
266 if (cpu_thermal_feature & CPUID_THERMAL_ARAT) {
268 * Local APIC timer will not stop
271 lapic_cputimer_intr.caps |=
272 CPUTIMER_INTR_CAP_PS;
274 cputimer_intr_register(&lapic_cputimer_intr);
275 cputimer_intr_select(&lapic_cputimer_intr, 0);
278 lapic_timer_set_divisor(lapic_timer_divisor_idx);
282 apic_dump("apic_initialize()");
286 lapic_timer_set_divisor(int divisor_idx)
288 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
289 lapic->dcr_timer = lapic_timer_divisors[divisor_idx];
293 lapic_timer_oneshot(u_int count)
297 value = lapic->lvt_timer;
298 value &= ~APIC_LVTT_PERIODIC;
299 lapic->lvt_timer = value;
300 lapic->icr_timer = count;
304 lapic_timer_oneshot_quick(u_int count)
306 lapic->icr_timer = count;
310 lapic_timer_calibrate(void)
314 /* Try to calibrate the local APIC timer. */
315 for (lapic_timer_divisor_idx = 0;
316 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
317 lapic_timer_divisor_idx++) {
318 lapic_timer_set_divisor(lapic_timer_divisor_idx);
319 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
321 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
322 if (value != APIC_TIMER_MAX_COUNT)
325 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
326 panic("lapic: no proper timer divisor?!");
327 lapic_cputimer_intr.freq = value / 2;
329 kprintf("lapic: divisor index %d, frequency %u Hz\n",
330 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
334 lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
338 gd->gd_timer_running = 0;
340 count = sys_cputimer->count();
341 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
342 systimer_intr(&count, 0, frame);
346 lapic_timer_process(void)
348 lapic_timer_process_oncpu(mycpu, NULL);
352 lapic_timer_process_frame(struct intrframe *frame)
354 lapic_timer_process_oncpu(mycpu, frame);
358 * This manual debugging code is called unconditionally from Xtimer
359 * (the lapic timer interrupt) whether the current thread is in a
360 * critical section or not) and can be useful in tracking down lockups.
362 * NOTE: MANUAL DEBUG CODE
365 static int saveticks[SMP_MAXCPU];
366 static int savecounts[SMP_MAXCPU];
370 lapic_timer_always(struct intrframe *frame)
373 globaldata_t gd = mycpu;
374 int cpu = gd->gd_cpuid;
380 gptr = (short *)0xFFFFFFFF800b8000 + 80 * cpu;
381 *gptr = ((*gptr + 1) & 0x00FF) | 0x0700;
384 ksnprintf(buf, sizeof(buf), " %p %16s %d %16s ",
385 (void *)frame->if_rip, gd->gd_curthread->td_comm, ticks,
387 for (i = 0; buf[i]; ++i) {
388 gptr[i] = 0x0700 | (unsigned char)buf[i];
392 if (saveticks[gd->gd_cpuid] != ticks) {
393 saveticks[gd->gd_cpuid] = ticks;
394 savecounts[gd->gd_cpuid] = 0;
396 ++savecounts[gd->gd_cpuid];
397 if (savecounts[gd->gd_cpuid] > 2000 && panicstr == NULL) {
398 panic("cpud %d panicing on ticks failure",
401 for (i = 0; i < ncpus; ++i) {
403 if (saveticks[i] && panicstr == NULL) {
404 delta = saveticks[i] - ticks;
405 if (delta < -10 || delta > 10) {
406 panic("cpu %d panicing on cpu %d watchdog",
416 lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
418 struct globaldata *gd = mycpu;
420 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
424 if (gd->gd_timer_running) {
425 if (reload < lapic->ccr_timer)
426 lapic_timer_oneshot_quick(reload);
428 gd->gd_timer_running = 1;
429 lapic_timer_oneshot_quick(reload);
434 lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
438 timer = lapic->lvt_timer;
439 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
440 lapic->lvt_timer = timer;
442 lapic_timer_fixup_handler(NULL);
446 lapic_timer_fixup_handler(void *arg)
453 if (cpu_vendor_id == CPU_VENDOR_AMD) {
455 * Detect the presence of C1E capability mostly on latest
456 * dual-cores (or future) k8 family. This feature renders
457 * the local APIC timer dead, so we disable it by reading
458 * the Interrupt Pending Message register and clearing both
459 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
462 * "BIOS and Kernel Developer's Guide for AMD NPT
463 * Family 0Fh Processors"
464 * #32559 revision 3.00
466 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
467 (cpu_id & 0x0fff0000) >= 0x00040000) {
470 msr = rdmsr(0xc0010055);
471 if (msr & 0x18000000) {
472 struct globaldata *gd = mycpu;
474 kprintf("cpu%d: AMD C1E detected\n",
476 wrmsr(0xc0010055, msr & ~0x18000000ULL);
479 * We are kinda stalled;
482 gd->gd_timer_running = 1;
483 lapic_timer_oneshot_quick(2);
493 lapic_timer_restart_handler(void *dummy __unused)
497 lapic_timer_fixup_handler(&started);
499 struct globaldata *gd = mycpu;
501 gd->gd_timer_running = 1;
502 lapic_timer_oneshot_quick(2);
507 * This function is called only by ACPICA code currently:
508 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
509 * module controls PM. So once ACPICA is attached, we try
510 * to apply the fixup to prevent LAPIC timer from hanging.
513 lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
515 lwkt_send_ipiq_mask(smp_active_mask,
516 lapic_timer_fixup_handler, NULL);
520 lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
522 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
527 * dump contents of local APIC registers
532 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
533 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
534 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
538 * Inter Processor Interrupt functions.
542 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
544 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
545 * vector is any valid SYSTEM INT vector
546 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
550 * We now implement a per-cpu interlock (gd->gd_npoll) to prevent more than
551 * one IPI from being sent to any given cpu at a time. Thus we no longer
552 * have to process incoming IPIs while waiting for the status to clear.
553 * No deadlock should be possible.
555 * We now physically disable interrupts for the lapic ICR operation. If
556 * we do not do this then it looks like an EOI sent to the lapic (which
557 * occurs even with a critical section) can interfere with the command
558 * register ready status and cause an IPI to be lost.
560 * e.g. an interrupt can occur, issue the EOI, IRET, and cause the command
561 * register to busy just before we write to icr_lo, resulting in a lost
562 * issuance. This only appears to occur on Intel cpus and is not
563 * documented. It could simply be that cpus are so fast these days that
564 * it was always an issue, but is only now rearing its ugly head. This
568 apic_ipi(int dest_type, int vector, int delivery_mode)
570 unsigned long rflags;
573 rflags = read_rflags();
575 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
578 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
579 delivery_mode | vector;
580 lapic->icr_lo = icr_lo;
581 write_rflags(rflags);
587 single_apic_ipi(int cpu, int vector, int delivery_mode)
589 unsigned long rflags;
593 rflags = read_rflags();
595 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
598 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
599 icr_hi |= (CPUID_TO_APICID(cpu) << 24);
600 lapic->icr_hi = icr_hi;
603 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK) |
604 APIC_DEST_DESTFLD | delivery_mode | vector;
607 lapic->icr_lo = icr_lo;
608 write_rflags(rflags);
614 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
616 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
617 * to the target, and the scheduler does not 'poll' for IPI messages.
620 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
626 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
630 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
631 icr_hi |= (CPUID_TO_APICID(cpu) << 24);
632 lapic->icr_hi = icr_hi;
635 icr_lo = (lapic->icr_lo & APIC_RESV2_MASK)
636 | APIC_DEST_DESTFLD | delivery_mode | vector;
639 lapic->icr_lo = icr_lo;
647 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
649 * target is a bitmask of destination cpus. Vector is any
650 * valid system INT vector. Delivery mode may be either
651 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
654 selected_apic_ipi(cpumask_t target, int vector, int delivery_mode)
657 while (CPUMASK_TESTNZERO(target)) {
658 int n = BSFCPUMASK(target);
659 CPUMASK_NANDBIT(target, n);
660 single_apic_ipi(n, vector, delivery_mode);
666 * Timer code, in development...
667 * - suggested by rgrimes@gndrsh.aac.dev.com
670 get_apic_timer_frequency(void)
672 return(lapic_cputimer_intr.freq);
676 * Load a 'downcount time' in uSeconds.
679 set_apic_timer(int us)
684 * When we reach here, lapic timer's frequency
685 * must have been calculated as well as the
686 * divisor (lapic->dcr_timer is setup during the
687 * divisor calculation).
689 KKASSERT(lapic_cputimer_intr.freq != 0 &&
690 lapic_timer_divisor_idx >= 0);
692 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
693 lapic_timer_oneshot(count);
698 * Read remaining time in timer.
701 read_apic_timer(void)
704 /** XXX FIXME: we need to return the actual remaining time,
705 * for now we just return the remaining count.
708 return lapic->ccr_timer;
714 * Spin-style delay, set delay time in uS, spin till it drains.
719 set_apic_timer(count);
720 while (read_apic_timer())
725 lapic_unused_apic_id(int start)
729 for (i = start; i < APICID_MAX; ++i) {
730 if (APICID_TO_CPUID(i) == -1)
737 lapic_map(vm_paddr_t lapic_addr)
739 lapic = pmap_mapdev_uncacheable(lapic_addr, sizeof(struct LAPIC));
742 static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
743 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
748 struct lapic_enumerator *e;
749 int error, i, ap_max;
751 KKASSERT(lapic_enable);
753 for (i = 0; i < NAPICID; ++i)
754 APICID_TO_CPUID(i) = -1;
756 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
757 error = e->lapic_probe(e);
762 kprintf("LAPIC: Can't find LAPIC\n");
766 error = e->lapic_enumerate(e);
768 kprintf("LAPIC: enumeration failed\n");
773 TUNABLE_INT_FETCH("hw.ap_max", &ap_max);
774 if (ap_max > MAXCPU - 1)
778 kprintf("LAPIC: Warning use only %d out of %d "
788 lapic_enumerator_register(struct lapic_enumerator *ne)
790 struct lapic_enumerator *e;
792 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
793 if (e->lapic_prio < ne->lapic_prio) {
794 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
798 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);
802 lapic_set_cpuid(int cpu_id, int apic_id)
804 CPUID_TO_APICID(cpu_id) = apic_id;
805 APICID_TO_CPUID(apic_id) = cpu_id;
809 lapic_fixup_noioapic(void)
813 /* Only allowed on BSP */
814 KKASSERT(mycpuid == 0);
815 KKASSERT(!ioapic_enable);
817 temp = lapic->lvt_lint0;
818 temp &= ~APIC_LVT_MASKED;
819 lapic->lvt_lint0 = temp;
821 temp = lapic->lvt_lint1;
822 temp |= APIC_LVT_MASKED;
823 lapic->lvt_lint1 = temp;
827 lapic_sysinit(void *dummy __unused)
832 error = lapic_config();
838 /* Initialize BSP's local APIC */
840 } else if (ioapic_enable) {
842 icu_reinit_noioapic();
845 SYSINIT(lapic, SI_BOOT2_LAPIC, SI_ORDER_FIRST, lapic_sysinit, NULL);