2 * from: vector.s, 386BSD 0.1 unknown origin
3 * $FreeBSD: src/sys/i386/isa/apic_vector.s,v 1.47.2.5 2001/09/01 22:33:38 tegge Exp $
4 * $DragonFly: src/sys/platform/pc32/apic/apic_vector.s,v 1.37 2008/01/14 15:27:16 dillon Exp $
8 #include "opt_auto_eoi.h"
10 #include <machine/asmacros.h>
11 #include <machine/lock.h>
12 #include <machine/psl.h>
13 #include <machine/trap.h>
15 #include <machine_base/icu/icu.h>
16 #include <bus/isa/i386/isa.h>
22 #include <machine/smp.h>
23 #include <machine_base/isa/intr_machdep.h>
25 /* convert an absolute IRQ# into a bitmask */
26 #define IRQ_LBIT(irq_num) (1 << (irq_num))
28 /* make an index into the IO APIC from the IRQ# */
29 #define REDTBL_IDX(irq_num) (0x10 + ((irq_num) * 2))
32 #define MPLOCKED lock ;
38 * Push an interrupt frame in a format acceptable to doreti, reload
39 * the segment registers for the kernel.
42 pushl $0 ; /* dummy error code */ \
43 pushl $0 ; /* dummy trap type */ \
44 pushl $0 ; /* dummy xflags type */ \
46 pushl %ds ; /* save data and extra segments ... */ \
58 pushfl ; /* phys int frame / flags */ \
59 pushl %cs ; /* phys int frame / cs */ \
60 pushl 12(%esp) ; /* original caller eip */ \
61 pushl $0 ; /* dummy error code */ \
62 pushl $0 ; /* dummy trap type */ \
63 pushl $0 ; /* dummy xflags type */ \
64 subl $13*4,%esp ; /* pushal + 4 seg regs (dummy) + CPL */ \
67 * Warning: POP_FRAME can only be used if there is no chance of a
68 * segment register being changed (e.g. by procfs), which is why syscalls
77 addl $3*4,%esp ; /* dummy xflags, trap & error codes */ \
82 #define IOAPICADDR(irq_num) CNAME(int_to_apicintpin) + 16 * (irq_num) + 8
83 #define REDIRIDX(irq_num) CNAME(int_to_apicintpin) + 16 * (irq_num) + 12
85 #define MASK_IRQ(irq_num) \
86 APIC_IMASK_LOCK ; /* into critical reg */ \
87 testl $IRQ_LBIT(irq_num), apic_imen ; \
88 jne 7f ; /* masked, don't mask */ \
89 orl $IRQ_LBIT(irq_num), apic_imen ; /* set the mask bit */ \
90 movl IOAPICADDR(irq_num), %ecx ; /* ioapic addr */ \
91 movl REDIRIDX(irq_num), %eax ; /* get the index */ \
92 movl %eax, (%ecx) ; /* write the index */ \
93 movl IOAPIC_WINDOW(%ecx), %eax ; /* current value */ \
94 orl $IOART_INTMASK, %eax ; /* set the mask */ \
95 movl %eax, IOAPIC_WINDOW(%ecx) ; /* new value */ \
96 7: ; /* already masked */ \
100 * Test to see whether we are handling an edge or level triggered INT.
101 * Level-triggered INTs must still be masked as we don't clear the source,
102 * and the EOI cycle would cause redundant INTs to occur.
104 #define MASK_LEVEL_IRQ(irq_num) \
105 testl $IRQ_LBIT(irq_num), apic_pin_trigger ; \
106 jz 9f ; /* edge, don't mask */ \
107 MASK_IRQ(irq_num) ; \
111 * Test to see if the source is currntly masked, clear if so.
113 #define UNMASK_IRQ(irq_num) \
116 APIC_IMASK_LOCK ; /* into critical reg */ \
117 testl $IRQ_LBIT(irq_num), apic_imen ; \
118 je 7f ; /* bit clear, not masked */ \
119 andl $~IRQ_LBIT(irq_num), apic_imen ;/* clear mask bit */ \
120 movl IOAPICADDR(irq_num),%ecx ; /* ioapic addr */ \
121 movl REDIRIDX(irq_num), %eax ; /* get the index */ \
122 movl %eax,(%ecx) ; /* write the index */ \
123 movl IOAPIC_WINDOW(%ecx),%eax ; /* current value */ \
124 andl $~IOART_INTMASK,%eax ; /* clear the mask */ \
125 movl %eax,IOAPIC_WINDOW(%ecx) ; /* new value */ \
127 APIC_IMASK_UNLOCK ; \
133 * Fast interrupt call handlers run in the following sequence:
135 * - Push the trap frame required by doreti
136 * - Mask the interrupt and reenable its source
137 * - If we cannot take the interrupt set its fpending bit and
138 * doreti. Note that we cannot mess with mp_lock at all
139 * if we entered from a critical section!
140 * - If we can take the interrupt clear its fpending bit,
141 * call the handler, then unmask and doreti.
143 * YYY can cache gd base opitner instead of using hidden %fs prefixes.
146 #define FAST_INTR(irq_num, vec_name) \
151 FAKE_MCOUNT(15*4(%esp)) ; \
152 MASK_LEVEL_IRQ(irq_num) ; \
153 movl $0, lapic_eoi ; \
154 movl PCPU(curthread),%ebx ; \
155 movl $0,%eax ; /* CURRENT CPL IN FRAME (REMOVED) */ \
157 testl $-1,TD_NEST_COUNT(%ebx) ; \
159 cmpl $TDPRI_CRIT,TD_PRI(%ebx) ; \
162 /* in critical section, make interrupt pending */ \
163 /* set the pending bit and return, leave interrupt masked */ \
164 orl $IRQ_LBIT(irq_num),PCPU(fpending) ; \
165 orl $RQF_INTPEND,PCPU(reqflags) ; \
168 /* clear pending bit, run handler */ \
169 andl $~IRQ_LBIT(irq_num),PCPU(fpending) ; \
171 pushl %esp ; /* pass frame by reference */ \
172 call ithread_fast_handler ; /* returns 0 to unmask */ \
174 UNMASK_IRQ(irq_num) ; \
180 * Slow interrupt call handlers run in the following sequence:
182 * - Push the trap frame required by doreti.
183 * - Mask the interrupt and reenable its source.
184 * - If we cannot take the interrupt set its ipending bit and
185 * doreti. In addition to checking for a critical section
186 * and cpl mask we also check to see if the thread is still
187 * running. Note that we cannot mess with mp_lock at all
188 * if we entered from a critical section!
189 * - If we can take the interrupt clear its ipending bit
190 * and schedule the thread. Leave interrupts masked and doreti.
192 * Note that calls to sched_ithd() are made with interrupts enabled
193 * and outside a critical section. YYY sched_ithd may preempt us
194 * synchronously (fix interrupt stacking).
196 * YYY can cache gd base pointer instead of using hidden %fs
200 #define SLOW_INTR(irq_num, vec_name, maybe_extra_ipending) \
205 maybe_extra_ipending ; \
207 MASK_LEVEL_IRQ(irq_num) ; \
208 incl PCPU(cnt) + V_INTR ; \
209 movl $0, lapic_eoi ; \
210 movl PCPU(curthread),%ebx ; \
211 movl $0,%eax ; /* CURRENT CPL IN FRAME (REMOVED) */ \
212 pushl %eax ; /* cpl do restore */ \
213 testl $-1,TD_NEST_COUNT(%ebx) ; \
215 cmpl $TDPRI_CRIT,TD_PRI(%ebx) ; \
218 /* set the pending bit and return, leave the interrupt masked */ \
219 orl $IRQ_LBIT(irq_num), PCPU(ipending) ; \
220 orl $RQF_INTPEND,PCPU(reqflags) ; \
223 /* set running bit, clear pending bit, run handler */ \
224 andl $~IRQ_LBIT(irq_num), PCPU(ipending) ; \
225 incl TD_NEST_COUNT(%ebx) ; \
231 decl TD_NEST_COUNT(%ebx) ; \
237 * Wrong interrupt call handlers. We program these into APIC vectors
238 * that should otherwise never occur. For example, we program the SLOW
239 * vector for irq N with this when we program the FAST vector with the
242 * XXX for now all we can do is EOI it. We can't call do_wrongintr
243 * (yet) because we could be in a critical section.
245 #define WRONGINTR(irq_num,vec_name) \
250 movl $0, lapic_eoi ; /* End Of Interrupt to APIC */ \
251 /*pushl $irq_num ;*/ \
252 /*call do_wrongintr ;*/ \
260 * Handle "spurious INTerrupts".
262 * This is different than the "spurious INTerrupt" generated by an
263 * 8259 PIC for missing INTs. See the APIC documentation for details.
264 * This routine should NOT do an 'EOI' cycle.
271 /* No EOI cycle used here */
277 * Handle TLB shootdowns.
285 movl %cr3, %eax /* invalidate the TLB */
288 ss /* stack segment, avoid %ds load */
289 movl $0, lapic_eoi /* End Of Interrupt to APIC */
296 * Executed by a CPU when it receives an Xcpustop IPI from another CPU,
298 * - Signals its receipt.
299 * - Waits for permission to restart.
300 * - Processing pending IPIQ events while waiting.
301 * - Signals its restart.
313 pushl %ds /* save current data segment */
317 mov %ax, %ds /* use KERNEL data segment */
321 movl $0, lapic_eoi /* End Of Interrupt to APIC */
323 movl PCPU(cpuid), %eax
324 imull $PCB_SIZE, %eax
325 leal CNAME(stoppcbs)(%eax), %eax
327 call CNAME(savectx) /* Save process context */
331 movl PCPU(cpuid), %eax
334 * Indicate that we have stopped and loop waiting for permission
335 * to start again. We must still process IPI events while in a
339 btsl %eax, stopped_cpus /* stopped_cpus |= (1<<id) */
341 andl $~RQF_IPIQ,PCPU(reqflags)
343 call lwkt_smp_stopped
345 btl %eax, started_cpus /* while (!(started_cpus & (1<<id))) */
349 btrl %eax, started_cpus /* started_cpus &= ~(1<<id) */
351 btrl %eax, stopped_cpus /* stopped_cpus &= ~(1<<id) */
356 movl CNAME(cpustop_restartfunc), %eax
359 movl $0, CNAME(cpustop_restartfunc) /* One-shot */
364 popl %ds /* restore previous data segment */
373 * For now just have one ipiq IPI, but what we really want is
374 * to have one for each source cpu to the APICs don't get stalled
375 * backlogging the requests.
382 movl $0, lapic_eoi /* End Of Interrupt to APIC */
383 FAKE_MCOUNT(15*4(%esp))
385 movl PCPU(curthread),%ebx
386 cmpl $TDPRI_CRIT,TD_PRI(%ebx)
388 subl $8,%esp /* make same as interrupt frame */
389 pushl %esp /* pass frame by reference */
390 incl PCPU(intr_nesting_level)
391 addl $TDPRI_CRIT,TD_PRI(%ebx)
392 call lwkt_process_ipiq_frame
393 subl $TDPRI_CRIT,TD_PRI(%ebx)
394 decl PCPU(intr_nesting_level)
396 pushl $0 /* CPL for frame (REMOVED) */
400 orl $RQF_IPIQ,PCPU(reqflags)
408 FAST_INTR(0,apic_fastintr0)
409 FAST_INTR(1,apic_fastintr1)
410 FAST_INTR(2,apic_fastintr2)
411 FAST_INTR(3,apic_fastintr3)
412 FAST_INTR(4,apic_fastintr4)
413 FAST_INTR(5,apic_fastintr5)
414 FAST_INTR(6,apic_fastintr6)
415 FAST_INTR(7,apic_fastintr7)
416 FAST_INTR(8,apic_fastintr8)
417 FAST_INTR(9,apic_fastintr9)
418 FAST_INTR(10,apic_fastintr10)
419 FAST_INTR(11,apic_fastintr11)
420 FAST_INTR(12,apic_fastintr12)
421 FAST_INTR(13,apic_fastintr13)
422 FAST_INTR(14,apic_fastintr14)
423 FAST_INTR(15,apic_fastintr15)
424 FAST_INTR(16,apic_fastintr16)
425 FAST_INTR(17,apic_fastintr17)
426 FAST_INTR(18,apic_fastintr18)
427 FAST_INTR(19,apic_fastintr19)
428 FAST_INTR(20,apic_fastintr20)
429 FAST_INTR(21,apic_fastintr21)
430 FAST_INTR(22,apic_fastintr22)
431 FAST_INTR(23,apic_fastintr23)
433 /* YYY what is this garbage? */
435 SLOW_INTR(0,apic_slowintr0,)
436 SLOW_INTR(1,apic_slowintr1,)
437 SLOW_INTR(2,apic_slowintr2,)
438 SLOW_INTR(3,apic_slowintr3,)
439 SLOW_INTR(4,apic_slowintr4,)
440 SLOW_INTR(5,apic_slowintr5,)
441 SLOW_INTR(6,apic_slowintr6,)
442 SLOW_INTR(7,apic_slowintr7,)
443 SLOW_INTR(8,apic_slowintr8,)
444 SLOW_INTR(9,apic_slowintr9,)
445 SLOW_INTR(10,apic_slowintr10,)
446 SLOW_INTR(11,apic_slowintr11,)
447 SLOW_INTR(12,apic_slowintr12,)
448 SLOW_INTR(13,apic_slowintr13,)
449 SLOW_INTR(14,apic_slowintr14,)
450 SLOW_INTR(15,apic_slowintr15,)
451 SLOW_INTR(16,apic_slowintr16,)
452 SLOW_INTR(17,apic_slowintr17,)
453 SLOW_INTR(18,apic_slowintr18,)
454 SLOW_INTR(19,apic_slowintr19,)
455 SLOW_INTR(20,apic_slowintr20,)
456 SLOW_INTR(21,apic_slowintr21,)
457 SLOW_INTR(22,apic_slowintr22,)
458 SLOW_INTR(23,apic_slowintr23,)
460 WRONGINTR(0,apic_wrongintr0)
461 WRONGINTR(1,apic_wrongintr1)
462 WRONGINTR(2,apic_wrongintr2)
463 WRONGINTR(3,apic_wrongintr3)
464 WRONGINTR(4,apic_wrongintr4)
465 WRONGINTR(5,apic_wrongintr5)
466 WRONGINTR(6,apic_wrongintr6)
467 WRONGINTR(7,apic_wrongintr7)
468 WRONGINTR(8,apic_wrongintr8)
469 WRONGINTR(9,apic_wrongintr9)
470 WRONGINTR(10,apic_wrongintr10)
471 WRONGINTR(11,apic_wrongintr11)
472 WRONGINTR(12,apic_wrongintr12)
473 WRONGINTR(13,apic_wrongintr13)
474 WRONGINTR(14,apic_wrongintr14)
475 WRONGINTR(15,apic_wrongintr15)
476 WRONGINTR(16,apic_wrongintr16)
477 WRONGINTR(17,apic_wrongintr17)
478 WRONGINTR(18,apic_wrongintr18)
479 WRONGINTR(19,apic_wrongintr19)
480 WRONGINTR(20,apic_wrongintr20)
481 WRONGINTR(21,apic_wrongintr21)
482 WRONGINTR(22,apic_wrongintr22)
483 WRONGINTR(23,apic_wrongintr23)
490 /* variables used by stop_cpus()/restart_cpus()/Xcpustop */
491 .globl stopped_cpus, started_cpus
497 .globl CNAME(cpustop_restartfunc)
498 CNAME(cpustop_restartfunc):
501 .globl apic_pin_trigger