6465c56bf669ebeb5a7bb4204050665d56a39965
[dragonfly.git] / sys / dev / serial / rc / rc.c
1 /*
2  * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
3  * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  * $FreeBSD: src/sys/i386/isa/rc.c,v 1.53.2.1 2001/02/26 04:23:10 jlemon Exp $
28  * $DragonFly: src/sys/dev/serial/rc/rc.c,v 1.24 2008/08/02 01:14:43 dillon Exp $
29  *
30  */
31
32 /*
33  * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver
34  *
35  */
36
37 #include "use_rc.h"
38
39 /*#define RCDEBUG*/
40
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/tty.h>
44 #include <sys/proc.h>
45 #include <sys/priv.h>
46 #include <sys/conf.h>
47 #include <sys/dkstat.h>
48 #include <sys/fcntl.h>
49 #include <sys/interrupt.h>
50 #include <sys/kernel.h>
51 #include <sys/thread2.h>
52 #include <machine/clock.h>
53
54 #include <bus/isa/isa_device.h>
55
56 #include <machine_base/isa/ic/cd180.h>
57 #include "rcreg.h"
58
59 /* Prototypes */
60 static int     rcprobe         (struct isa_device *);
61 static int     rcattach        (struct isa_device *);
62
63 #define rcin(port)      RC_IN  (nec, port)
64 #define rcout(port,v)   RC_OUT (nec, port, v)
65
66 #define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__)
67 #define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd))
68
69 #define RC_IBUFSIZE     256
70 #define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE)
71 #define RC_OBUFSIZE     512
72 #define RC_IHIGHWATER   (3 * RC_IBUFSIZE / 4)
73 #define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE)
74 #define LOTS_OF_EVENTS  64
75
76 #define RC_FAKEID       0x10
77
78 #define RC_PROBED 1
79 #define RC_ATTACHED 2
80
81 #define GET_UNIT(dev)   (minor(dev) & 0x3F)
82 #define CALLOUT(dev)    (minor(dev) & 0x80)
83
84 /* For isa routines */
85 struct isa_driver rcdriver = {
86         rcprobe, rcattach, "rc"
87 };
88
89 static  d_open_t        rcopen;
90 static  d_close_t       rcclose;
91 static  d_ioctl_t       rcioctl;
92
93 #define CDEV_MAJOR      63
94 static struct dev_ops rc_ops = {
95         { "rc", CDEV_MAJOR, D_TTY | D_KQFILTER },
96         .d_open =       rcopen,
97         .d_close =      rcclose,
98         .d_read =       ttyread,
99         .d_write =      ttywrite,
100         .d_ioctl =      rcioctl,
101         .d_poll =       ttypoll,
102         .d_kqfilter =   ttykqfilter,
103         .d_revoke =     ttyrevoke
104 };
105
106 /* Per-board structure */
107 static struct rc_softc {
108         u_int           rcb_probed;     /* 1 - probed, 2 - attached */
109         u_int           rcb_addr;       /* Base I/O addr        */
110         u_int           rcb_unit;       /* unit #               */
111         u_char          rcb_dtr;        /* DTR status           */
112         struct rc_chans *rcb_baserc;    /* base rc ptr          */
113 } rc_softc[NRC];
114
115 /* Per-channel structure */
116 static struct rc_chans  {
117         struct rc_softc *rc_rcb;                /* back ptr             */
118         u_short          rc_flags;              /* Misc. flags          */
119         int              rc_chan;               /* Channel #            */
120         u_char           rc_ier;                /* intr. enable reg     */
121         u_char           rc_msvr;               /* modem sig. status    */
122         u_char           rc_cor2;               /* options reg          */
123         u_char           rc_pendcmd;            /* special cmd pending  */
124         u_int            rc_dtrwait;            /* dtr timeout          */
125         u_int            rc_dcdwaits;           /* how many waits DCD in open */
126         u_char           rc_hotchar;            /* end packed optimize */
127         struct tty      *rc_tp;                 /* tty struct           */
128         u_char          *rc_iptr;               /* Chars input buffer         */
129         u_char          *rc_hiwat;              /* hi-water mark        */
130         u_char          *rc_bufend;             /* end of buffer        */
131         u_char          *rc_optr;               /* ptr in output buf    */
132         u_char          *rc_obufend;            /* end of output buf    */
133         struct callout   rc_dtr_ch;
134         u_char           rc_ibuf[4 * RC_IBUFSIZE];  /* input buffer         */
135         u_char           rc_obuf[RC_OBUFSIZE];  /* output buffer        */
136 } rc_chans[NRC * CD180_NCHAN];
137
138 static int rc_scheduled_event = 0;
139 static struct callout rc_wakeup_ch;
140
141 /* for pstat -t */
142 static struct tty rc_tty[NRC * CD180_NCHAN];
143 static const int  nrc_tty = NRC * CD180_NCHAN;
144
145 /* Flags */
146 #define RC_DTR_OFF      0x0001          /* DTR wait, for close/open     */
147 #define RC_ACTOUT       0x0002          /* Dial-out port active         */
148 #define RC_RTSFLOW      0x0004          /* RTS flow ctl enabled         */
149 #define RC_CTSFLOW      0x0008          /* CTS flow ctl enabled         */
150 #define RC_DORXFER      0x0010          /* RXFER event planned          */
151 #define RC_DOXXFER      0x0020          /* XXFER event planned          */
152 #define RC_MODCHG       0x0040          /* Modem status changed         */
153 #define RC_OSUSP        0x0080          /* Output suspended             */
154 #define RC_OSBUSY       0x0100          /* start() routine in progress  */
155 #define RC_WAS_BUFOVFL  0x0200          /* low-level buffer ovferflow   */
156 #define RC_WAS_SILOVFL  0x0400          /* silo buffer overflow         */
157 #define RC_SEND_RDY     0x0800          /* ready to send */
158
159 /* Table for translation of RCSR status bits to internal form */
160 static int rc_rcsrt[16] = {
161         0,             TTY_OE,               TTY_FE,
162         TTY_FE|TTY_OE, TTY_PE,               TTY_PE|TTY_OE,
163         TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI,
164         TTY_BI|TTY_OE, TTY_BI|TTY_FE,        TTY_BI|TTY_FE|TTY_OE,
165         TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE,
166         TTY_BI|TTY_PE|TTY_FE|TTY_OE
167 };
168
169 /* Static prototypes */
170 static inthand2_t rcintr;
171 static void rc_hwreset          (int, int, unsigned int);
172 static int  rc_test             (int, int);
173 static void rc_discard_output   (struct rc_chans *);
174 static void rc_hardclose        (struct rc_chans *);
175 static int  rc_modctl           (struct rc_chans *, int, int);
176 static void rc_start            (struct tty *);
177 static void rc_stop              (struct tty *, int rw);
178 static int  rc_param            (struct tty *, struct termios *);
179 static inthand2_t rcpoll;
180 static void rc_reinit           (struct rc_softc *);
181 #ifdef RCDEBUG
182 static void printrcflags();
183 #endif
184 static timeout_t rc_dtrwakeup;
185 static timeout_t rc_wakeup;
186 static void disc_optim          (struct tty     *tp, struct termios *t, struct rc_chans *);
187 static void rc_wait0            (int nec, int unit, int chan, int line);
188
189 /**********************************************/
190
191 /* Quick device probing */
192 static int
193 rcprobe(struct isa_device *dvp)
194 {
195         int             irq = ffs(dvp->id_irq) - 1;
196         int    nec = dvp->id_iobase;
197
198         if (dvp->id_unit > NRC)
199                 return 0;
200         if (!RC_VALIDADDR(nec)) {
201                 kprintf("rc%d: illegal base address %x\n", dvp->id_unit, nec);
202                 return 0;
203         }
204         if (!RC_VALIDIRQ(irq)) {
205                 kprintf("rc%d: illegal IRQ value %d\n", dvp->id_unit, irq);
206                 return 0;
207         }
208         rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */
209         rcout(CD180_PPRH, 0x11);
210         if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11)
211                 return 0;
212         /* Now, test the board more thoroughly, with diagnostic */
213         if (rc_test(nec, dvp->id_unit))
214                 return 0;
215         rc_softc[dvp->id_unit].rcb_probed = RC_PROBED;
216
217         return 0xF;
218 }
219
220 static int
221 rcattach(struct isa_device *dvp)
222 {
223         int            chan, nec = dvp->id_iobase;
224         struct rc_softc         *rcb = &rc_softc[dvp->id_unit];
225         struct rc_chans         *rc  = &rc_chans[dvp->id_unit * CD180_NCHAN];
226         static int              rc_started = 0;
227         struct tty              *tp;
228
229         dvp->id_intr = rcintr;
230
231         /* Thorooughly test the device */
232         if (rcb->rcb_probed != RC_PROBED)
233                 return 0;
234         rcb->rcb_addr   = nec;
235         rcb->rcb_dtr    = 0;
236         rcb->rcb_baserc = rc;
237         rcb->rcb_unit   = dvp->id_unit;
238         /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/
239         kprintf("rc%d: %d chans, firmware rev. %c\n", rcb->rcb_unit,
240                 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A');
241
242         for (chan = 0; chan < CD180_NCHAN; chan++, rc++) {
243                 callout_init(&rc->rc_dtr_ch);
244                 rc->rc_rcb     = rcb;
245                 rc->rc_chan    = chan;
246                 rc->rc_iptr    = rc->rc_ibuf;
247                 rc->rc_bufend  = &rc->rc_ibuf[RC_IBUFSIZE];
248                 rc->rc_hiwat   = &rc->rc_ibuf[RC_IHIGHWATER];
249                 rc->rc_flags   = rc->rc_ier = rc->rc_msvr = 0;
250                 rc->rc_cor2    = rc->rc_pendcmd = 0;
251                 rc->rc_optr    = rc->rc_obufend  = rc->rc_obuf;
252                 rc->rc_dtrwait = 3 * hz;
253                 rc->rc_dcdwaits= 0;
254                 rc->rc_hotchar = 0;
255                 tp = rc->rc_tp = &rc_tty[chan + (dvp->id_unit * CD180_NCHAN)];
256                 ttychars(tp);
257                 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0;
258                 tp->t_cflag = TTYDEF_CFLAG;
259                 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
260         }
261         rcb->rcb_probed = RC_ATTACHED;
262         if (!rc_started) {
263                 dev_ops_add(&rc_ops, -1, rcb->rcb_unit);
264                 register_swi(SWI_TTY, rcpoll, NULL, "rcpoll", NULL);
265                 callout_init(&rc_wakeup_ch);
266                 rc_wakeup(NULL);
267                 rc_started = 1;
268         }
269         return 1;
270 }
271
272 /* RC interrupt handling */
273 static void
274 rcintr(void *arg, void *frame)
275 {
276         int unit = (int)arg;
277         struct rc_softc        *rcb = &rc_softc[unit];
278         struct rc_chans        *rc;
279         int                    nec, resid;
280         u_char                 val, iack, bsr, ucnt, *optr;
281         int                             good_data, t_state;
282
283         if (rcb->rcb_probed != RC_ATTACHED) {
284                 kprintf("rc%d: bogus interrupt\n", unit);
285                 return;
286         }
287         nec = rcb->rcb_addr;
288
289         bsr = ~(rcin(RC_BSR));
290
291         if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) {
292                 kprintf("rc%d: extra interrupt\n", unit);
293                 rcout(CD180_EOIR, 0);
294                 return;
295         }
296
297         while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) {
298 #ifdef RCDEBUG_DETAILED
299                 kprintf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr,
300                         (bsr & RC_BSR_TOUT)?"TOUT ":"",
301                         (bsr & RC_BSR_RXINT)?"RXINT ":"",
302                         (bsr & RC_BSR_TXINT)?"TXINT ":"",
303                         (bsr & RC_BSR_MOINT)?"MOINT":"");
304 #endif
305                 if (bsr & RC_BSR_TOUT) {
306                         kprintf("rc%d: hardware failure, reset board\n", unit);
307                         rcout(RC_CTOUT, 0);
308                         rc_reinit(rcb);
309                         return;
310                 }
311                 if (bsr & RC_BSR_RXINT) {
312                         iack = rcin(RC_PILR_RX);
313                         good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID));
314                         if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) {
315                                 kprintf("rc%d: fake rxint: %02x\n", unit, iack);
316                                 goto more_intrs;
317                         }
318                         rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
319                         t_state = rc->rc_tp->t_state;
320                         /* Do RTS flow control stuff */
321                         if (  (rc->rc_flags & RC_RTSFLOW)
322                             || !(t_state & TS_ISOPEN)
323                            ) {
324                                 if (  (   !(t_state & TS_ISOPEN)
325                                        || (t_state & TS_TBLOCK)
326                                       )
327                                     && (rc->rc_msvr & MSVR_RTS)
328                                    )
329                                         rcout(CD180_MSVR,
330                                                 rc->rc_msvr &= ~MSVR_RTS);
331                                 else if (!(rc->rc_msvr & MSVR_RTS))
332                                         rcout(CD180_MSVR,
333                                                 rc->rc_msvr |= MSVR_RTS);
334                         }
335                         ucnt  = rcin(CD180_RDCR) & 0xF;
336                         resid = 0;
337
338                         if (t_state & TS_ISOPEN) {
339                                 /* check for input buffer overflow */
340                                 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) {
341                                         resid  = ucnt;
342                                         ucnt   = rc->rc_bufend - rc->rc_iptr;
343                                         resid -= ucnt;
344                                         if (!(rc->rc_flags & RC_WAS_BUFOVFL)) {
345                                                 rc->rc_flags |= RC_WAS_BUFOVFL;
346                                                 rc_scheduled_event++;
347                                         }
348                                 }
349                                 optr = rc->rc_iptr;
350                                 /* check foor good data */
351                                 if (good_data) {
352                                         while (ucnt-- > 0) {
353                                                 val = rcin(CD180_RDR);
354                                                 optr[0] = val;
355                                                 optr[INPUT_FLAGS_SHIFT] = 0;
356                                                 optr++;
357                                                 rc_scheduled_event++;
358                                                 if (val != 0 && val == rc->rc_hotchar)
359                                                         setsofttty();
360                                         }
361                                 } else {
362                                         /* Store also status data */
363                                         while (ucnt-- > 0) {
364                                                 iack = rcin(CD180_RCSR);
365                                                 if (iack & RCSR_Timeout)
366                                                         break;
367                                                 if (   (iack & RCSR_OE)
368                                                     && !(rc->rc_flags & RC_WAS_SILOVFL)) {
369                                                         rc->rc_flags |= RC_WAS_SILOVFL;
370                                                         rc_scheduled_event++;
371                                                 }
372                                                 val = rcin(CD180_RDR);
373                                                 /*
374                                                   Don't store PE if IGNPAR and BREAK if IGNBRK,
375                                                   this hack allows "raw" tty optimization
376                                                   works even if IGN* is set.
377                                                 */
378                                                 if (   !(iack & (RCSR_PE|RCSR_FE|RCSR_Break))
379                                                     || ((!(iack & (RCSR_PE|RCSR_FE))
380                                                     ||  !(rc->rc_tp->t_iflag & IGNPAR))
381                                                     && (!(iack & RCSR_Break)
382                                                     ||  !(rc->rc_tp->t_iflag & IGNBRK)))) {
383                                                         if (   (iack & (RCSR_PE|RCSR_FE))
384                                                             && (t_state & TS_CAN_BYPASS_L_RINT)
385                                                             && ((iack & RCSR_FE)
386                                                             ||  ((iack & RCSR_PE)
387                                                             &&  (rc->rc_tp->t_iflag & INPCK))))
388                                                                 val = 0;
389                                                         else if (val != 0 && val == rc->rc_hotchar)
390                                                                 setsofttty();
391                                                         optr[0] = val;
392                                                         optr[INPUT_FLAGS_SHIFT] = iack;
393                                                         optr++;
394                                                         rc_scheduled_event++;
395                                                 }
396                                         }
397                                 }
398                                 rc->rc_iptr = optr;
399                                 rc->rc_flags |= RC_DORXFER;
400                         } else
401                                 resid = ucnt;
402                         /* Clear FIFO if necessary */
403                         while (resid-- > 0) {
404                                 if (!good_data)
405                                         iack = rcin(CD180_RCSR);
406                                 else
407                                         iack = 0;
408                                 if (iack & RCSR_Timeout)
409                                         break;
410                                 (void) rcin(CD180_RDR);
411                         }
412                         goto more_intrs;
413                 }
414                 if (bsr & RC_BSR_MOINT) {
415                         iack = rcin(RC_PILR_MODEM);
416                         if (iack != (GIVR_IT_MSCI | RC_FAKEID)) {
417                                 kprintf("rc%d: fake moint: %02x\n", unit, iack);
418                                 goto more_intrs;
419                         }
420                         rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
421                         iack = rcin(CD180_MCR);
422                         rc->rc_msvr = rcin(CD180_MSVR);
423                         rcout(CD180_MCR, 0);
424 #ifdef RCDEBUG
425                         printrcflags(rc, "moint");
426 #endif
427                         if (rc->rc_flags & RC_CTSFLOW) {
428                                 if (rc->rc_msvr & MSVR_CTS)
429                                         rc->rc_flags |= RC_SEND_RDY;
430                                 else
431                                         rc->rc_flags &= ~RC_SEND_RDY;
432                         } else
433                                 rc->rc_flags |= RC_SEND_RDY;
434                         if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) {
435                                 rc_scheduled_event += LOTS_OF_EVENTS;
436                                 rc->rc_flags |= RC_MODCHG;
437                                 setsofttty();
438                         }
439                         goto more_intrs;
440                 }
441                 if (bsr & RC_BSR_TXINT) {
442                         iack = rcin(RC_PILR_TX);
443                         if (iack != (GIVR_IT_TDI | RC_FAKEID)) {
444                                 kprintf("rc%d: fake txint: %02x\n", unit, iack);
445                                 goto more_intrs;
446                         }
447                         rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
448                         if (    (rc->rc_flags & RC_OSUSP)
449                             || !(rc->rc_flags & RC_SEND_RDY)
450                            )
451                                 goto more_intrs;
452                         /* Handle breaks and other stuff */
453                         if (rc->rc_pendcmd) {
454                                 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC);
455                                 rcout(CD180_TDR,  CD180_C_ESC);
456                                 rcout(CD180_TDR,  rc->rc_pendcmd);
457                                 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC);
458                                 rc->rc_pendcmd = 0;
459                                 goto more_intrs;
460                         }
461                         optr = rc->rc_optr;
462                         resid = rc->rc_obufend - optr;
463                         if (resid > CD180_NFIFO)
464                                 resid = CD180_NFIFO;
465                         while (resid-- > 0)
466                                 rcout(CD180_TDR, *optr++);
467                         rc->rc_optr = optr;
468
469                         /* output completed? */
470                         if (optr >= rc->rc_obufend) {
471                                 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy);
472 #ifdef RCDEBUG
473                                 kprintf("rc%d/%d: output completed\n", unit, rc->rc_chan);
474 #endif
475                                 if (!(rc->rc_flags & RC_DOXXFER)) {
476                                         rc_scheduled_event += LOTS_OF_EVENTS;
477                                         rc->rc_flags |= RC_DOXXFER;
478                                         setsofttty();
479                                 }
480                         }
481                 }
482         more_intrs:
483                 rcout(CD180_EOIR, 0);   /* end of interrupt */
484                 rcout(RC_CTOUT, 0);
485                 bsr = ~(rcin(RC_BSR));
486         }
487 }
488
489 /* Feed characters to output buffer */
490 static void
491 rc_start(struct tty *tp)
492 {
493         struct rc_chans       *rc = &rc_chans[GET_UNIT(tp->t_dev)];
494         int                    nec = rc->rc_rcb->rcb_addr;
495
496         if (rc->rc_flags & RC_OSBUSY)
497                 return;
498         crit_enter();
499         rc->rc_flags |= RC_OSBUSY;
500         cpu_disable_intr();
501         if (tp->t_state & TS_TTSTOP)
502                 rc->rc_flags |= RC_OSUSP;
503         else
504                 rc->rc_flags &= ~RC_OSUSP;
505         /* Do RTS flow control stuff */
506         if (   (rc->rc_flags & RC_RTSFLOW)
507             && (tp->t_state & TS_TBLOCK)
508             && (rc->rc_msvr & MSVR_RTS)
509            ) {
510                 rcout(CD180_CAR, rc->rc_chan);
511                 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS);
512         } else if (!(rc->rc_msvr & MSVR_RTS)) {
513                 rcout(CD180_CAR, rc->rc_chan);
514                 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS);
515         }
516         cpu_enable_intr();
517         if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP))
518                 goto out;
519 #ifdef RCDEBUG
520         printrcflags(rc, "rcstart");
521 #endif
522         ttwwakeup(tp);
523 #ifdef RCDEBUG
524         kprintf("rcstart: outq = %d obuf = %d\n",
525                 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr);
526 #endif
527         if (tp->t_state & TS_BUSY)
528                 goto    out;    /* output still in progress ... */
529
530         if (tp->t_outq.c_cc > 0) {
531                 u_int   ocnt;
532
533                 tp->t_state |= TS_BUSY;
534                 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf);
535                 cpu_disable_intr();
536                 rc->rc_optr = rc->rc_obuf;
537                 rc->rc_obufend = rc->rc_optr + ocnt;
538                 cpu_enable_intr();
539                 if (!(rc->rc_ier & IER_TxRdy)) {
540 #ifdef RCDEBUG
541                         kprintf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan);
542 #endif
543                         rcout(CD180_CAR, rc->rc_chan);
544                         rcout(CD180_IER, rc->rc_ier |= IER_TxRdy);
545                 }
546         }
547 out:
548         rc->rc_flags &= ~RC_OSBUSY;
549         crit_exit();
550 }
551
552 /* Handle delayed events. */
553 void 
554 rcpoll(void *dummy, void *frame)
555 {
556         struct rc_chans *rc;
557         struct rc_softc *rcb;
558         u_char        *tptr, *eptr;
559         struct tty    *tp;
560         int            chan, icnt, nec, unit;
561
562         if (rc_scheduled_event == 0)
563                 return;
564 repeat:
565         for (unit = 0; unit < NRC; unit++) {
566                 rcb = &rc_softc[unit];
567                 rc = rcb->rcb_baserc;
568                 nec = rc->rc_rcb->rcb_addr;
569                 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) {
570                         tp = rc->rc_tp;
571 #ifdef RCDEBUG
572                         if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG|
573                             RC_WAS_BUFOVFL|RC_WAS_SILOVFL))
574                                 printrcflags(rc, "rcevent");
575 #endif
576                         if (rc->rc_flags & RC_WAS_BUFOVFL) {
577                                 cpu_disable_intr();
578                                 rc->rc_flags &= ~RC_WAS_BUFOVFL;
579                                 rc_scheduled_event--;
580                                 cpu_enable_intr();
581                                 kprintf("rc%d/%d: interrupt-level buffer overflow\n",
582                                         unit, chan);
583                         }
584                         if (rc->rc_flags & RC_WAS_SILOVFL) {
585                                 cpu_disable_intr();
586                                 rc->rc_flags &= ~RC_WAS_SILOVFL;
587                                 rc_scheduled_event--;
588                                 cpu_enable_intr();
589                                 kprintf("rc%d/%d: silo overflow\n",
590                                         unit, chan);
591                         }
592                         if (rc->rc_flags & RC_MODCHG) {
593                                 cpu_disable_intr();
594                                 rc->rc_flags &= ~RC_MODCHG;
595                                 rc_scheduled_event -= LOTS_OF_EVENTS;
596                                 cpu_enable_intr();
597                                 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD));
598                         }
599                         if (rc->rc_flags & RC_DORXFER) {
600                                 cpu_disable_intr();
601                                 rc->rc_flags &= ~RC_DORXFER;
602                                 eptr = rc->rc_iptr;
603                                 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE])
604                                         tptr = &rc->rc_ibuf[RC_IBUFSIZE];
605                                 else
606                                         tptr = rc->rc_ibuf;
607                                 icnt = eptr - tptr;
608                                 if (icnt > 0) {
609                                         if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
610                                                 rc->rc_iptr   = rc->rc_ibuf;
611                                                 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
612                                                 rc->rc_hiwat  = &rc->rc_ibuf[RC_IHIGHWATER];
613                                         } else {
614                                                 rc->rc_iptr   = &rc->rc_ibuf[RC_IBUFSIZE];
615                                                 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE];
616                                                 rc->rc_hiwat  =
617                                                         &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER];
618                                         }
619                                         if (   (rc->rc_flags & RC_RTSFLOW)
620                                             && (tp->t_state & TS_ISOPEN)
621                                             && !(tp->t_state & TS_TBLOCK)
622                                             && !(rc->rc_msvr & MSVR_RTS)
623                                             ) {
624                                                 rcout(CD180_CAR, chan);
625                                                 rcout(CD180_MSVR,
626                                                         rc->rc_msvr |= MSVR_RTS);
627                                         }
628                                         rc_scheduled_event -= icnt;
629                                 }
630                                 cpu_enable_intr();
631
632                                 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN))
633                                         goto done1;
634
635                                 if (   (tp->t_state & TS_CAN_BYPASS_L_RINT)
636                                     && !(tp->t_state & TS_LOCAL)) {
637                                         if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER
638                                             && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF))
639                                             && !(tp->t_state & TS_TBLOCK))
640                                                 ttyblock(tp);
641                                         tk_nin += icnt;
642                                         tk_rawcc += icnt;
643                                         tp->t_rawcc += icnt;
644                                         if (b_to_q(tptr, icnt, &tp->t_rawq))
645                                                 kprintf("rc%d/%d: tty-level buffer overflow\n",
646                                                         unit, chan);
647                                         ttwakeup(tp);
648                                         if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY)
649                                             || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) {
650                                                 tp->t_state &= ~TS_TTSTOP;
651                                                 tp->t_lflag &= ~FLUSHO;
652                                                 rc_start(tp);
653                                         }
654                                 } else {
655                                         for (; tptr < eptr; tptr++)
656                                                 (*linesw[tp->t_line].l_rint)
657                                                     (tptr[0] |
658                                                     rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp);
659                                 }
660 done1: ;
661                         }
662                         if (rc->rc_flags & RC_DOXXFER) {
663                                 cpu_disable_intr();
664                                 rc_scheduled_event -= LOTS_OF_EVENTS;
665                                 rc->rc_flags &= ~RC_DOXXFER;
666                                 rc->rc_tp->t_state &= ~TS_BUSY;
667                                 cpu_enable_intr();
668                                 (*linesw[tp->t_line].l_start)(tp);
669                         }
670                 }
671                 if (rc_scheduled_event == 0)
672                         break;
673         }
674         if (rc_scheduled_event >= LOTS_OF_EVENTS)
675                 goto repeat;
676 }
677
678 static  void
679 rc_stop(struct tty *tp, int rw)
680 {
681         struct rc_chans        *rc = &rc_chans[GET_UNIT(tp->t_dev)];
682         u_char *tptr, *eptr;
683
684 #ifdef RCDEBUG
685         kprintf("rc%d/%d: rc_stop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan,
686                 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":"");
687 #endif
688         if (rw & FWRITE)
689                 rc_discard_output(rc);
690         cpu_disable_intr();
691         if (rw & FREAD) {
692                 rc->rc_flags &= ~RC_DORXFER;
693                 eptr = rc->rc_iptr;
694                 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
695                         tptr = &rc->rc_ibuf[RC_IBUFSIZE];
696                         rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
697                 } else {
698                         tptr = rc->rc_ibuf;
699                         rc->rc_iptr = rc->rc_ibuf;
700                 }
701                 rc_scheduled_event -= eptr - tptr;
702         }
703         if (tp->t_state & TS_TTSTOP)
704                 rc->rc_flags |= RC_OSUSP;
705         else
706                 rc->rc_flags &= ~RC_OSUSP;
707         cpu_enable_intr();
708 }
709
710 static  int
711 rcopen(struct dev_open_args *ap)
712 {
713         cdev_t dev = ap->a_head.a_dev;
714         struct rc_chans *rc;
715         struct tty      *tp;
716         int             unit, nec, error = 0;
717
718         unit = GET_UNIT(dev);
719         if (unit >= NRC * CD180_NCHAN)
720                 return ENXIO;
721         if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED)
722                 return ENXIO;
723         rc  = &rc_chans[unit];
724         tp  = rc->rc_tp;
725         dev->si_tty = tp;
726         nec = rc->rc_rcb->rcb_addr;
727 #ifdef RCDEBUG
728         kprintf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
729 #endif
730         crit_enter();
731
732 again:
733         while (rc->rc_flags & RC_DTR_OFF) {
734                 error = tsleep(&(rc->rc_dtrwait), PCATCH, "rcdtr", 0);
735                 if (error != 0)
736                         goto out;
737         }
738         if (tp->t_state & TS_ISOPEN) {
739                 if (CALLOUT(dev)) {
740                         if (!(rc->rc_flags & RC_ACTOUT)) {
741                                 error = EBUSY;
742                                 goto out;
743                         }
744                 } else {
745                         if (rc->rc_flags & RC_ACTOUT) {
746                                 if (ap->a_oflags & O_NONBLOCK) {
747                                         error = EBUSY;
748                                         goto out;
749                                 }
750                                 error = tsleep(&rc->rc_rcb, PCATCH, "rcbi", 0);
751                                 if (error)
752                                         goto out;
753                                 goto again;
754                         }
755                 }
756                 if (tp->t_state & TS_XCLUDE &&
757                     priv_check_cred(ap->a_cred, PRIV_ROOT, 0)) {
758                         error = EBUSY;
759                         goto out;
760                 }
761         } else {
762                 tp->t_oproc   = rc_start;
763                 tp->t_param   = rc_param;
764                 tp->t_stop    = rc_stop;
765                 tp->t_dev     = dev;
766
767                 if (CALLOUT(dev))
768                         tp->t_cflag |= CLOCAL;
769                 else
770                         tp->t_cflag &= ~CLOCAL;
771
772                 error = rc_param(tp, &tp->t_termios);
773                 if (error)
774                         goto out;
775                 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET);
776
777                 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev))
778                         (*linesw[tp->t_line].l_modem)(tp, 1);
779         }
780         if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev)
781             && !(tp->t_cflag & CLOCAL) && !(ap->a_oflags & O_NONBLOCK)) {
782                 rc->rc_dcdwaits++;
783                 error = tsleep(TSA_CARR_ON(tp), PCATCH, "rcdcd", 0);
784                 rc->rc_dcdwaits--;
785                 if (error != 0)
786                         goto out;
787                 goto again;
788         }
789         error = (*linesw[tp->t_line].l_open)(dev, tp);
790         disc_optim(tp, &tp->t_termios, rc);
791         if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev))
792                 rc->rc_flags |= RC_ACTOUT;
793 out:
794         crit_exit();
795
796         if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN))
797                 rc_hardclose(rc);
798
799         return error;
800 }
801
802 static int
803 rcclose(struct dev_close_args *ap)
804 {
805         cdev_t dev = ap->a_head.a_dev;
806         struct rc_chans *rc;
807         struct tty      *tp;
808         int unit = GET_UNIT(dev);
809
810         if (unit >= NRC * CD180_NCHAN)
811                 return ENXIO;
812         rc  = &rc_chans[unit];
813         tp  = rc->rc_tp;
814 #ifdef RCDEBUG
815         kprintf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
816 #endif
817         crit_enter();
818         (*linesw[tp->t_line].l_close)(tp, ap->a_fflag);
819         disc_optim(tp, &tp->t_termios, rc);
820         rc_stop(tp, FREAD | FWRITE);
821         rc_hardclose(rc);
822         ttyclose(tp);
823         crit_exit();
824         return 0;
825 }
826
827 static void
828 rc_hardclose(struct rc_chans *rc)
829 {
830         int nec = rc->rc_rcb->rcb_addr;
831         struct tty *tp = rc->rc_tp;
832
833         crit_enter();
834         rcout(CD180_CAR, rc->rc_chan);
835
836         /* Disable rx/tx intrs */
837         rcout(CD180_IER, rc->rc_ier = 0);
838         if (   (tp->t_cflag & HUPCL)
839             || (!(rc->rc_flags & RC_ACTOUT)
840                && !(rc->rc_msvr & MSVR_CD)
841                && !(tp->t_cflag & CLOCAL))
842             || !(tp->t_state & TS_ISOPEN)
843            ) {
844                 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
845                 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
846                 (void) rc_modctl(rc, TIOCM_RTS, DMSET);
847                 if (rc->rc_dtrwait) {
848                         callout_reset(&rc->rc_dtr_ch, rc->rc_dtrwait,
849                                 rc_dtrwakeup, rc);
850                         rc->rc_flags |= RC_DTR_OFF;
851                 }
852         }
853         rc->rc_flags &= ~RC_ACTOUT;
854         wakeup((caddr_t) &rc->rc_rcb);  /* wake bi */
855         wakeup(TSA_CARR_ON(tp));
856         crit_exit();
857 }
858
859 /* Reset the bastard */
860 static void
861 rc_hwreset(int unit, int nec, unsigned int chipid)
862 {
863         CCRCMD(unit, -1, CCR_HWRESET);            /* Hardware reset */
864         DELAY(20000);
865         WAITFORCCR(unit, -1);
866
867         rcout(RC_CTOUT, 0);             /* Clear timeout  */
868         rcout(CD180_GIVR,  chipid);
869         rcout(CD180_GICR,  0);
870
871         /* Set Prescaler Registers (1 msec) */
872         rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF);
873         rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8);
874
875         /* Initialize Priority Interrupt Level Registers */
876         rcout(CD180_PILR1, RC_PILR_MODEM);
877         rcout(CD180_PILR2, RC_PILR_TX);
878         rcout(CD180_PILR3, RC_PILR_RX);
879
880         /* Reset DTR */
881         rcout(RC_DTREG, ~0);
882 }
883
884 /* Set channel parameters */
885 static int
886 rc_param(struct tty *tp, struct termios *ts)
887 {
888         struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
889         int    nec = rc->rc_rcb->rcb_addr;
890         int      idivs, odivs, val, cflag, iflag, lflag, inpflow;
891
892         if (   ts->c_ospeed < 0 || ts->c_ospeed > 76800
893             || ts->c_ispeed < 0 || ts->c_ispeed > 76800
894            )
895                 return (EINVAL);
896         if (ts->c_ispeed == 0)
897                 ts->c_ispeed = ts->c_ospeed;
898         odivs = RC_BRD(ts->c_ospeed);
899         idivs = RC_BRD(ts->c_ispeed);
900
901         crit_enter();
902
903         /* Select channel */
904         rcout(CD180_CAR, rc->rc_chan);
905
906         /* If speed == 0, hangup line */
907         if (ts->c_ospeed == 0) {
908                 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
909                 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
910                 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
911         }
912
913         tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
914         cflag = ts->c_cflag;
915         iflag = ts->c_iflag;
916         lflag = ts->c_lflag;
917
918         if (idivs > 0) {
919                 rcout(CD180_RBPRL, idivs & 0xFF);
920                 rcout(CD180_RBPRH, idivs >> 8);
921         }
922         if (odivs > 0) {
923                 rcout(CD180_TBPRL, odivs & 0xFF);
924                 rcout(CD180_TBPRH, odivs >> 8);
925         }
926
927         /* set timeout value */
928         if (ts->c_ispeed > 0) {
929                 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1;
930
931                 if (   !(lflag & ICANON)
932                     && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0
933                     && ts->c_cc[VTIME] * 10 > itm)
934                         itm = ts->c_cc[VTIME] * 10;
935
936                 rcout(CD180_RTPR, itm <= 255 ? itm : 255);
937         }
938
939         switch (cflag & CSIZE) {
940                 case CS5:       val = COR1_5BITS;      break;
941                 case CS6:       val = COR1_6BITS;      break;
942                 case CS7:       val = COR1_7BITS;      break;
943                 default:
944                 case CS8:       val = COR1_8BITS;      break;
945         }
946         if (cflag & PARENB) {
947                 val |= COR1_NORMPAR;
948                 if (cflag & PARODD)
949                         val |= COR1_ODDP;
950                 if (!(cflag & INPCK))
951                         val |= COR1_Ignore;
952         } else
953                 val |= COR1_Ignore;
954         if (cflag & CSTOPB)
955                 val |= COR1_2SB;
956         rcout(CD180_COR1, val);
957
958         /* Set FIFO threshold */
959         val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2;
960         inpflow = 0;
961         if (   (iflag & IXOFF)
962             && (   ts->c_cc[VSTOP] != _POSIX_VDISABLE
963                 && (   ts->c_cc[VSTART] != _POSIX_VDISABLE
964                     || (iflag & IXANY)
965                    )
966                )
967            ) {
968                 inpflow = 1;
969                 val |= COR3_SCDE|COR3_FCT;
970         }
971         rcout(CD180_COR3, val);
972
973         /* Initialize on-chip automatic flow control */
974         val = 0;
975         rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY);
976         if (cflag & CCTS_OFLOW) {
977                 rc->rc_flags |= RC_CTSFLOW;
978                 val |= COR2_CtsAE;
979         } else
980                 rc->rc_flags |= RC_SEND_RDY;
981         if (tp->t_state & TS_TTSTOP)
982                 rc->rc_flags |= RC_OSUSP;
983         else
984                 rc->rc_flags &= ~RC_OSUSP;
985         if (cflag & CRTS_IFLOW)
986                 rc->rc_flags |= RC_RTSFLOW;
987         else
988                 rc->rc_flags &= ~RC_RTSFLOW;
989
990         if (inpflow) {
991                 if (ts->c_cc[VSTART] != _POSIX_VDISABLE)
992                         rcout(CD180_SCHR1, ts->c_cc[VSTART]);
993                 rcout(CD180_SCHR2, ts->c_cc[VSTOP]);
994                 val |= COR2_TxIBE;
995                 if (iflag & IXANY)
996                         val |= COR2_IXM;
997         }
998
999         rcout(CD180_COR2, rc->rc_cor2 = val);
1000
1001         CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1002                 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1003
1004         disc_optim(tp, ts, rc);
1005
1006         /* modem ctl */
1007         val = cflag & CLOCAL ? 0 : MCOR1_CDzd;
1008         if (cflag & CCTS_OFLOW)
1009                 val |= MCOR1_CTSzd;
1010         rcout(CD180_MCOR1, val);
1011
1012         val = cflag & CLOCAL ? 0 : MCOR2_CDod;
1013         if (cflag & CCTS_OFLOW)
1014                 val |= MCOR2_CTSod;
1015         rcout(CD180_MCOR2, val);
1016
1017         /* enable i/o and interrupts */
1018         CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1019                 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS));
1020         WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
1021
1022         rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD;
1023         if (cflag & CCTS_OFLOW)
1024                 rc->rc_ier |= IER_CTS;
1025         if (cflag & CREAD)
1026                 rc->rc_ier |= IER_RxData;
1027         if (tp->t_state & TS_BUSY)
1028                 rc->rc_ier |= IER_TxRdy;
1029         if (ts->c_ospeed != 0)
1030                 rc_modctl(rc, TIOCM_DTR, DMBIS);
1031         if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS))
1032                 rc->rc_flags |= RC_SEND_RDY;
1033         rcout(CD180_IER, rc->rc_ier);
1034         crit_exit();
1035         return 0;
1036 }
1037
1038 /* Re-initialize board after bogus interrupts */
1039 static void
1040 rc_reinit(struct rc_softc *rcb)
1041 {
1042         struct rc_chans       *rc, *rce;
1043         int                    nec;
1044
1045         nec = rcb->rcb_addr;
1046         rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID);
1047         rc  = &rc_chans[rcb->rcb_unit * CD180_NCHAN];
1048         rce = rc + CD180_NCHAN;
1049         for (; rc < rce; rc++)
1050                 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios);
1051 }
1052
1053 static  int
1054 rcioctl(struct dev_ioctl_args *ap)
1055 {
1056         cdev_t dev = ap->a_head.a_dev;
1057         struct rc_chans       *rc = &rc_chans[GET_UNIT(dev)];
1058         int                   error;
1059         struct tty                     *tp = rc->rc_tp;
1060
1061         error = (*linesw[tp->t_line].l_ioctl)(tp, ap->a_cmd, ap->a_data,
1062                                               ap->a_fflag, ap->a_cred);
1063         if (error != ENOIOCTL)
1064                 return (error);
1065         error = ttioctl(tp, ap->a_cmd, ap->a_data, ap->a_fflag);
1066         disc_optim(tp, &tp->t_termios, rc);
1067         if (error != ENOIOCTL)
1068                 return (error);
1069         crit_enter();
1070
1071         switch (ap->a_cmd) {
1072             case TIOCSBRK:
1073                 rc->rc_pendcmd = CD180_C_SBRK;
1074                 break;
1075
1076             case TIOCCBRK:
1077                 rc->rc_pendcmd = CD180_C_EBRK;
1078                 break;
1079
1080             case TIOCSDTR:
1081                 (void) rc_modctl(rc, TIOCM_DTR, DMBIS);
1082                 break;
1083
1084             case TIOCCDTR:
1085                 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
1086                 break;
1087
1088             case TIOCMGET:
1089                 *(int *) ap->a_data = rc_modctl(rc, 0, DMGET);
1090                 break;
1091
1092             case TIOCMSET:
1093                 (void) rc_modctl(rc, *(int *) ap->a_data, DMSET);
1094                 break;
1095
1096             case TIOCMBIC:
1097                 (void) rc_modctl(rc, *(int *) ap->a_data, DMBIC);
1098                 break;
1099
1100             case TIOCMBIS:
1101                 (void) rc_modctl(rc, *(int *) ap->a_data, DMBIS);
1102                 break;
1103
1104             case TIOCMSDTRWAIT:
1105                 error = priv_check_cred(ap->a_cred, PRIV_ROOT, 0);
1106                 if (error != 0) {
1107                         crit_exit();
1108                         return (error);
1109                 }
1110                 rc->rc_dtrwait = *(int *)ap->a_data * hz / 100;
1111                 break;
1112
1113             case TIOCMGDTRWAIT:
1114                 *(int *)ap->a_data = rc->rc_dtrwait * 100 / hz;
1115                 break;
1116
1117             default:
1118                 crit_exit();
1119                 return ENOTTY;
1120         }
1121         crit_exit();
1122         return 0;
1123 }
1124
1125
1126 /* Modem control routines */
1127
1128 static int
1129 rc_modctl(struct rc_chans *rc, int bits, int cmd)
1130 {
1131         int    nec = rc->rc_rcb->rcb_addr;
1132         u_char         *dtr = &rc->rc_rcb->rcb_dtr, msvr;
1133
1134         rcout(CD180_CAR, rc->rc_chan);
1135
1136         switch (cmd) {
1137             case DMSET:
1138                 rcout(RC_DTREG, (bits & TIOCM_DTR) ?
1139                                 ~(*dtr |= 1 << rc->rc_chan) :
1140                                 ~(*dtr &= ~(1 << rc->rc_chan)));
1141                 msvr = rcin(CD180_MSVR);
1142                 if (bits & TIOCM_RTS)
1143                         msvr |= MSVR_RTS;
1144                 else
1145                         msvr &= ~MSVR_RTS;
1146                 if (bits & TIOCM_DTR)
1147                         msvr |= MSVR_DTR;
1148                 else
1149                         msvr &= ~MSVR_DTR;
1150                 rcout(CD180_MSVR, msvr);
1151                 break;
1152
1153             case DMBIS:
1154                 if (bits & TIOCM_DTR)
1155                         rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan));
1156                 msvr = rcin(CD180_MSVR);
1157                 if (bits & TIOCM_RTS)
1158                         msvr |= MSVR_RTS;
1159                 if (bits & TIOCM_DTR)
1160                         msvr |= MSVR_DTR;
1161                 rcout(CD180_MSVR, msvr);
1162                 break;
1163
1164             case DMGET:
1165                 bits = TIOCM_LE;
1166                 msvr = rc->rc_msvr = rcin(CD180_MSVR);
1167
1168                 if (msvr & MSVR_RTS)
1169                         bits |= TIOCM_RTS;
1170                 if (msvr & MSVR_CTS)
1171                         bits |= TIOCM_CTS;
1172                 if (msvr & MSVR_DSR)
1173                         bits |= TIOCM_DSR;
1174                 if (msvr & MSVR_DTR)
1175                         bits |= TIOCM_DTR;
1176                 if (msvr & MSVR_CD)
1177                         bits |= TIOCM_CD;
1178                 if (~rcin(RC_RIREG) & (1 << rc->rc_chan))
1179                         bits |= TIOCM_RI;
1180                 return bits;
1181
1182             case DMBIC:
1183                 if (bits & TIOCM_DTR)
1184                         rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan)));
1185                 msvr = rcin(CD180_MSVR);
1186                 if (bits & TIOCM_RTS)
1187                         msvr &= ~MSVR_RTS;
1188                 if (bits & TIOCM_DTR)
1189                         msvr &= ~MSVR_DTR;
1190                 rcout(CD180_MSVR, msvr);
1191                 break;
1192         }
1193         rc->rc_msvr = rcin(CD180_MSVR);
1194         return 0;
1195 }
1196
1197 /* Test the board. */
1198 int
1199 rc_test(int nec, int unit)
1200 {
1201         int     chan = 0;
1202         int     i = 0, rcnt;
1203         unsigned int    iack, chipid;
1204         unsigned short  divs;
1205         static  u_char  ctest[] = "\377\125\252\045\244\0\377";
1206 #define CTLEN   8
1207 #define ERR(s)  { \
1208                 kprintf("rc%d: ", unit); kprintf s ; kprintf("\n"); \
1209                 crit_exit(); return 1; }
1210
1211         struct rtest {
1212                 u_char  txbuf[CD180_NFIFO];     /* TX buffer  */
1213                 u_char  rxbuf[CD180_NFIFO];     /* RX buffer  */
1214                 int     rxptr;                  /* RX pointer */
1215                 int     txptr;                  /* TX pointer */
1216         } tchans[CD180_NCHAN];
1217
1218         crit_enter();
1219
1220         chipid = RC_FAKEID;
1221
1222         /* First, reset board to inital state */
1223         rc_hwreset(unit, nec, chipid);
1224
1225         divs = RC_BRD(19200);
1226
1227         /* Initialize channels */
1228         for (chan = 0; chan < CD180_NCHAN; chan++) {
1229
1230                 /* Select and reset channel */
1231                 rcout(CD180_CAR, chan);
1232                 CCRCMD(unit, chan, CCR_ResetChan);
1233                 WAITFORCCR(unit, chan);
1234
1235                 /* Set speed */
1236                 rcout(CD180_RBPRL, divs & 0xFF);
1237                 rcout(CD180_RBPRH, divs >> 8);
1238                 rcout(CD180_TBPRL, divs & 0xFF);
1239                 rcout(CD180_TBPRH, divs >> 8);
1240
1241                 /* set timeout value */
1242                 rcout(CD180_RTPR,  0);
1243
1244                 /* Establish local loopback */
1245                 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB);
1246                 rcout(CD180_COR2, COR2_LLM);
1247                 rcout(CD180_COR3, CD180_NFIFO);
1248                 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1249                 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN);
1250                 WAITFORCCR(unit, chan);
1251                 rcout(CD180_MSVR, MSVR_RTS);
1252
1253                 /* Fill TXBUF with test data */
1254                 for (i = 0; i < CD180_NFIFO; i++) {
1255                         tchans[chan].txbuf[i] = ctest[i];
1256                         tchans[chan].rxbuf[i] = 0;
1257                 }
1258                 tchans[chan].txptr = tchans[chan].rxptr = 0;
1259
1260                 /* Now, start transmit */
1261                 rcout(CD180_IER, IER_TxMpty|IER_RxData);
1262         }
1263         /* Pseudo-interrupt poll stuff */
1264         for (rcnt = 10000; rcnt-- > 0; rcnt--) {
1265                 i = ~(rcin(RC_BSR));
1266                 if (i & RC_BSR_TOUT)
1267                         ERR(("BSR timeout bit set\n"))
1268                 else if (i & RC_BSR_TXINT) {
1269                         iack = rcin(RC_PILR_TX);
1270                         if (iack != (GIVR_IT_TDI | chipid))
1271                                 ERR(("Bad TX intr ack (%02x != %02x)\n",
1272                                         iack, GIVR_IT_TDI | chipid));
1273                         chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1274                         /* If no more data to transmit, disable TX intr */
1275                         if (tchans[chan].txptr >= CD180_NFIFO) {
1276                                 iack = rcin(CD180_IER);
1277                                 rcout(CD180_IER, iack & ~IER_TxMpty);
1278                         } else {
1279                                 for (iack = tchans[chan].txptr;
1280                                     iack < CD180_NFIFO; iack++)
1281                                         rcout(CD180_TDR,
1282                                             tchans[chan].txbuf[iack]);
1283                                 tchans[chan].txptr = iack;
1284                         }
1285                         rcout(CD180_EOIR, 0);
1286                 } else if (i & RC_BSR_RXINT) {
1287                         u_char ucnt;
1288
1289                         iack = rcin(RC_PILR_RX);
1290                         if (iack != (GIVR_IT_RGDI | chipid) &&
1291                             iack != (GIVR_IT_REI  | chipid))
1292                                 ERR(("Bad RX intr ack (%02x != %02x)\n",
1293                                         iack, GIVR_IT_RGDI | chipid))
1294                         chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1295                         ucnt = rcin(CD180_RDCR) & 0xF;
1296                         while (ucnt-- > 0) {
1297                                 iack = rcin(CD180_RCSR);
1298                                 if (iack & RCSR_Timeout)
1299                                         break;
1300                                 if (iack & 0xF)
1301                                         ERR(("Bad char chan %d (RCSR = %02X)\n",
1302                                             chan, iack))
1303                                 if (tchans[chan].rxptr > CD180_NFIFO)
1304                                         ERR(("Got extra chars chan %d\n",
1305                                             chan))
1306                                 tchans[chan].rxbuf[tchans[chan].rxptr++] =
1307                                         rcin(CD180_RDR);
1308                         }
1309                         rcout(CD180_EOIR, 0);
1310                 }
1311                 rcout(RC_CTOUT, 0);
1312                 for (iack = chan = 0; chan < CD180_NCHAN; chan++)
1313                         if (tchans[chan].rxptr >= CD180_NFIFO)
1314                                 iack++;
1315                 if (iack == CD180_NCHAN)
1316                         break;
1317         }
1318         for (chan = 0; chan < CD180_NCHAN; chan++) {
1319                 /* Select and reset channel */
1320                 rcout(CD180_CAR, chan);
1321                 CCRCMD(unit, chan, CCR_ResetChan);
1322         }
1323
1324         if (!rcnt)
1325                 ERR(("looses characters during local loopback\n"))
1326         /* Now, check data */
1327         for (chan = 0; chan < CD180_NCHAN; chan++)
1328                 for (i = 0; i < CD180_NFIFO; i++)
1329                         if (ctest[i] != tchans[chan].rxbuf[i])
1330                                 ERR(("data mismatch chan %d ptr %d (%d != %d)\n",
1331                                     chan, i, ctest[i], tchans[chan].rxbuf[i]))
1332         crit_exit();
1333         return 0;
1334 }
1335
1336 #ifdef RCDEBUG
1337 static void
1338 printrcflags(struct rc_chans *rc, char *comment)
1339 {
1340         u_short f = rc->rc_flags;
1341         int    nec = rc->rc_rcb->rcb_addr;
1342
1343         kprintf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n",
1344                 rc->rc_rcb->rcb_unit, rc->rc_chan, comment,
1345                 (f & RC_DTR_OFF)?"DTR_OFF " :"",
1346                 (f & RC_ACTOUT) ?"ACTOUT " :"",
1347                 (f & RC_RTSFLOW)?"RTSFLOW " :"",
1348                 (f & RC_CTSFLOW)?"CTSFLOW " :"",
1349                 (f & RC_DORXFER)?"DORXFER " :"",
1350                 (f & RC_DOXXFER)?"DOXXFER " :"",
1351                 (f & RC_MODCHG) ?"MODCHG "  :"",
1352                 (f & RC_OSUSP)  ?"OSUSP " :"",
1353                 (f & RC_OSBUSY) ?"OSBUSY " :"",
1354                 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"",
1355                 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"",
1356                 (f & RC_SEND_RDY) ?"SEND_RDY":"");
1357
1358         rcout(CD180_CAR, rc->rc_chan);
1359
1360         kprintf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n",
1361                 rc->rc_rcb->rcb_unit, rc->rc_chan,
1362                 rcin(CD180_MSVR),
1363                 rcin(CD180_IER),
1364                 rcin(CD180_CCSR));
1365 }
1366 #endif /* RCDEBUG */
1367
1368 static void
1369 rc_dtrwakeup(void *chan)
1370 {
1371         struct rc_chans  *rc;
1372
1373         rc = (struct rc_chans *)chan;
1374         rc->rc_flags &= ~RC_DTR_OFF;
1375         wakeup(&rc->rc_dtrwait);
1376 }
1377
1378 static void
1379 rc_discard_output(struct rc_chans *rc)
1380 {
1381         cpu_disable_intr();
1382         if (rc->rc_flags & RC_DOXXFER) {
1383                 rc_scheduled_event -= LOTS_OF_EVENTS;
1384                 rc->rc_flags &= ~RC_DOXXFER;
1385         }
1386         rc->rc_optr = rc->rc_obufend;
1387         rc->rc_tp->t_state &= ~TS_BUSY;
1388         cpu_enable_intr();
1389         ttwwakeup(rc->rc_tp);
1390 }
1391
1392 static void
1393 rc_wakeup(void *chan)
1394 {
1395         if (rc_scheduled_event != 0) {
1396                 crit_enter();
1397                 rcpoll(NULL, NULL);
1398                 crit_exit();
1399         }
1400         callout_reset(&rc_wakeup_ch, 1, rc_wakeup, NULL);
1401 }
1402
1403 static void
1404 disc_optim(struct tty *tp, struct termios *t, struct rc_chans *rc)
1405 {
1406
1407         if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
1408             && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
1409             && (!(t->c_iflag & PARMRK)
1410                 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
1411             && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
1412             && linesw[tp->t_line].l_rint == ttyinput)
1413                 tp->t_state |= TS_CAN_BYPASS_L_RINT;
1414         else
1415                 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
1416         rc->rc_hotchar = linesw[tp->t_line].l_hotchar;
1417 }
1418
1419 static void
1420 rc_wait0(int nec, int unit, int chan, int line)
1421 {
1422         int rcnt;
1423
1424         for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--)
1425                 DELAY(30);
1426         if (rcnt == 0)
1427                 kprintf("rc%d/%d: channel command timeout, rc.c line: %d\n",
1428                       unit, chan, line);
1429 }