2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
40 #include <sys/mplock2.h>
43 #include <vm/vm_param.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
48 #include <vm/vm_map.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine_base/apic/mpapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
64 #include <machine/pmap_inval.h>
66 #include <machine/md_var.h> /* setidt() */
67 #include <machine_base/icu/icu.h> /* IPIs */
68 #include <machine/intr_machdep.h> /* IPIs */
70 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
72 #define WARMBOOT_TARGET 0
73 #define WARMBOOT_OFF (KERNBASE + 0x0467)
74 #define WARMBOOT_SEG (KERNBASE + 0x0469)
76 #define BIOS_BASE (0xf0000)
77 #define BIOS_BASE2 (0xe0000)
78 #define BIOS_SIZE (0x10000)
79 #define BIOS_COUNT (BIOS_SIZE/4)
81 #define CMOS_REG (0x70)
82 #define CMOS_DATA (0x71)
83 #define BIOS_RESET (0x0f)
84 #define BIOS_WARM (0x0a)
86 #define PROCENTRY_FLAG_EN 0x01
87 #define PROCENTRY_FLAG_BP 0x02
88 #define IOAPICENTRY_FLAG_EN 0x01
91 /* MP Floating Pointer Structure */
92 typedef struct MPFPS {
105 /* MP Configuration Table Header */
106 typedef struct MPCTH {
108 u_short base_table_length;
112 u_char product_id[12];
113 u_int32_t oem_table_pointer;
114 u_short oem_table_size;
116 u_int32_t apic_address;
117 u_short extended_table_length;
118 u_char extended_table_checksum;
123 typedef struct PROCENTRY {
128 u_int32_t cpu_signature;
129 u_int32_t feature_flags;
134 typedef struct BUSENTRY {
140 typedef struct IOAPICENTRY {
145 u_int32_t apic_address;
146 } *io_apic_entry_ptr;
148 typedef struct INTENTRY {
158 /* descriptions of MP basetable entries */
159 typedef struct BASETABLE_ENTRY {
168 vm_size_t mp_cth_mapsz;
171 typedef int (*mptable_iter_func)(void *, const void *, int);
174 * this code MUST be enabled here and in mpboot.s.
175 * it follows the very early stages of AP boot by placing values in CMOS ram.
176 * it NORMALLY will never be needed and thus the primitive method for enabling.
179 #if defined(CHECK_POINTS)
180 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
181 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
183 #define CHECK_INIT(D); \
184 CHECK_WRITE(0x34, (D)); \
185 CHECK_WRITE(0x35, (D)); \
186 CHECK_WRITE(0x36, (D)); \
187 CHECK_WRITE(0x37, (D)); \
188 CHECK_WRITE(0x38, (D)); \
189 CHECK_WRITE(0x39, (D));
191 #define CHECK_PRINT(S); \
192 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
201 #else /* CHECK_POINTS */
203 #define CHECK_INIT(D)
204 #define CHECK_PRINT(S)
206 #endif /* CHECK_POINTS */
209 * Values to send to the POST hardware.
211 #define MP_BOOTADDRESS_POST 0x10
212 #define MP_PROBE_POST 0x11
213 #define MPTABLE_PASS1_POST 0x12
215 #define MP_START_POST 0x13
216 #define MP_ENABLE_POST 0x14
217 #define MPTABLE_PASS2_POST 0x15
219 #define START_ALL_APS_POST 0x16
220 #define INSTALL_AP_TRAMP_POST 0x17
221 #define START_AP_POST 0x18
223 #define MP_ANNOUNCE_POST 0x19
225 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
226 int current_postcode;
228 /** XXX FIXME: what system files declare these??? */
229 extern struct region_descriptor r_gdt, r_idt;
231 int mp_naps; /* # of Applications processors */
232 #ifdef SMP /* APIC-IO */
233 static int mp_nbusses; /* # of busses */
234 int mp_napics; /* # of IO APICs */
235 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
236 u_int32_t *io_apic_versions;
240 u_int32_t cpu_apic_versions[NAPICID]; /* populated during mptable scan */
242 extern int64_t tsc_offsets[];
244 extern u_long ebda_addr;
246 #ifdef SMP /* APIC-IO */
247 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
251 * APIC ID logical/physical mapping structures.
252 * We oversize these to simplify boot-time config.
254 int cpu_num_to_apic_id[NAPICID];
255 #ifdef SMP /* APIC-IO */
256 int io_num_to_apic_id[NAPICID];
258 int apic_id_to_logical[NAPICID];
260 /* AP uses this during bootstrap. Do not staticize. */
264 struct pcb stoppcbs[MAXCPU];
266 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
268 static basetable_entry basetable_entry_types[] =
270 {0, 20, "Processor"},
278 * Local data and functions.
281 static u_int boot_address;
282 static u_int base_memory;
283 static int mp_finish;
285 static void mp_enable(u_int boot_addr);
287 static int mptable_iterate_entries(const mpcth_t,
288 mptable_iter_func, void *);
289 static int mptable_probe(void);
290 static int mptable_search(void);
291 static int mptable_check(vm_paddr_t);
292 static long mptable_search_sig(u_int32_t target, int count);
293 static int mptable_hyperthread_fixup(cpumask_t, int);
294 #ifdef SMP /* APIC-IO */
295 static void mptable_pass1(struct mptable_pos *);
296 static void mptable_pass2(struct mptable_pos *);
297 static void mptable_default(int type);
298 static void mptable_fix(void);
300 static int mptable_map(struct mptable_pos *, vm_paddr_t);
301 static void mptable_unmap(struct mptable_pos *);
302 static void mptable_imcr(struct mptable_pos *);
304 static int mptable_lapic_probe(struct lapic_enumerator *);
305 static void mptable_lapic_enumerate(struct lapic_enumerator *);
306 static void mptable_lapic_default(void);
308 #ifdef SMP /* APIC-IO */
309 static void setup_apic_irq_mapping(void);
310 static int apic_int_is_bus_type(int intr, int bus_type);
312 static int start_all_aps(u_int boot_addr);
314 static void install_ap_tramp(u_int boot_addr);
316 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
317 static int smitest(void);
319 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
320 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
321 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
322 static u_int bootMP_size;
325 * Calculate usable address in base memory for AP trampoline code.
328 mp_bootaddress(u_int basemem)
330 POSTCODE(MP_BOOTADDRESS_POST);
332 base_memory = basemem;
334 bootMP_size = mptramp_end - mptramp_start;
335 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
336 if (((basemem * 1024) - boot_address) < bootMP_size)
337 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
338 /* 3 levels of page table pages */
339 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
341 return mptramp_pagetables;
350 mpfps_paddr = mptable_search();
351 if (mptable_check(mpfps_paddr))
358 * Look for an Intel MP spec table (ie, SMP capable hardware).
366 POSTCODE(MP_PROBE_POST);
368 /* see if EBDA exists */
369 if (ebda_addr != 0) {
370 /* search first 1K of EBDA */
371 target = (u_int32_t)ebda_addr;
372 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
375 /* last 1K of base memory, effective 'top of base' passed in */
376 target = (u_int32_t)(base_memory - 0x400);
377 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
381 /* search the BIOS */
382 target = (u_int32_t)BIOS_BASE;
383 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
386 /* search the extended BIOS */
387 target = (u_int32_t)BIOS_BASE2;
388 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
395 struct mptable_check_cbarg {
401 mptable_check_callback(void *xarg, const void *pos, int type)
403 const struct PROCENTRY *ent;
404 struct mptable_check_cbarg *arg = xarg;
410 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
414 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
415 if (arg->found_bsp) {
416 kprintf("more than one BSP in base MP table\n");
425 mptable_check(vm_paddr_t mpfps_paddr)
427 struct mptable_pos mpt;
428 struct mptable_check_cbarg arg;
432 if (mpfps_paddr == 0)
435 error = mptable_map(&mpt, mpfps_paddr);
439 if (mpt.mp_fps->mpfb1 != 0)
447 if (cth->apic_address == 0)
450 bzero(&arg, sizeof(arg));
451 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
453 if (arg.cpu_count == 0) {
454 kprintf("MP table contains no processor entries\n");
456 } else if (!arg.found_bsp) {
457 kprintf("MP table does not contains BSP entry\n");
467 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
469 int count, total_size;
470 const void *position;
472 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
473 total_size = cth->base_table_length - sizeof(struct MPCTH);
474 position = (const uint8_t *)cth + sizeof(struct MPCTH);
475 count = cth->entry_count;
480 KKASSERT(total_size >= 0);
481 if (total_size == 0) {
482 kprintf("invalid base MP table, "
483 "entry count and length mismatch\n");
487 type = *(const uint8_t *)position;
489 case 0: /* processor_entry */
490 case 1: /* bus_entry */
491 case 2: /* io_apic_entry */
492 case 3: /* int_entry */
493 case 4: /* int_entry */
496 kprintf("unknown base MP table entry type %d\n", type);
500 if (total_size < basetable_entry_types[type].length) {
501 kprintf("invalid base MP table length, "
502 "does not contain all entries\n");
505 total_size -= basetable_entry_types[type].length;
507 error = func(arg, position, type);
511 position = (const uint8_t *)position +
512 basetable_entry_types[type].length;
519 * Startup the SMP processors.
524 POSTCODE(MP_START_POST);
525 mp_enable(boot_address);
530 * Print various information about the SMP system hardware and setup.
537 POSTCODE(MP_ANNOUNCE_POST);
539 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
540 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
541 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
542 for (x = 1; x <= mp_naps; ++x) {
543 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
544 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
547 if (apic_io_enable) {
548 for (x = 0; x < mp_napics; ++x) {
549 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
550 kprintf(", version: 0x%08x", io_apic_versions[x]);
551 kprintf(", at 0x%08lx\n", io_apic_address[x]);
554 kprintf(" Warning: APIC I/O disabled\n");
559 * AP cpu's call this to sync up protected mode.
561 * WARNING! %gs is not set up on entry. This routine sets up %gs.
567 int x, myid = bootAP;
569 struct mdglobaldata *md;
570 struct privatespace *ps;
572 ps = &CPU_prvspace[myid];
574 gdt_segs[GPROC0_SEL].ssd_base =
575 (long) &ps->mdglobaldata.gd_common_tss;
576 ps->mdglobaldata.mi.gd_prvspace = ps;
578 /* We fill the 32-bit segment descriptors */
579 for (x = 0; x < NGDT; x++) {
580 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
581 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
583 /* And now a 64-bit one */
584 ssdtosyssd(&gdt_segs[GPROC0_SEL],
585 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
587 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
588 r_gdt.rd_base = (long) &gdt[myid * NGDT];
589 lgdt(&r_gdt); /* does magic intra-segment return */
591 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
592 wrmsr(MSR_FSBASE, 0); /* User value */
593 wrmsr(MSR_GSBASE, (u_int64_t)ps);
594 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
600 mdcpu->gd_currentldt = _default_ldt;
603 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
604 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
606 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
608 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
610 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
612 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
613 md->gd_common_tssd = *md->gd_tss_gdt;
615 /* double fault stack */
616 md->gd_common_tss.tss_ist1 =
617 (long)&md->mi.gd_prvspace->idlestack[
618 sizeof(md->mi.gd_prvspace->idlestack)];
623 * Set to a known state:
624 * Set by mpboot.s: CR0_PG, CR0_PE
625 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
628 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
631 /* Set up the fast syscall stuff */
632 msr = rdmsr(MSR_EFER) | EFER_SCE;
633 wrmsr(MSR_EFER, msr);
634 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
635 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
636 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
637 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
638 wrmsr(MSR_STAR, msr);
639 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
641 pmap_set_opt(); /* PSE/4MB pages, etc */
643 /* Initialize the PAT MSR. */
647 /* set up CPU registers and state */
650 /* set up SSE/NX registers */
653 /* set up FPU state on the AP */
654 npxinit(__INITIAL_NPXCW__);
656 /* disable the APIC, just to be SURE */
657 lapic->svr &= ~APIC_SVR_ENABLE;
659 /* data returned to BSP */
660 cpu_apic_versions[0] = lapic->version;
663 /*******************************************************************
664 * local functions and data
668 * start the SMP system
671 mp_enable(u_int boot_addr)
675 vm_paddr_t mpfps_paddr;
676 struct mptable_pos mpt;
678 POSTCODE(MP_ENABLE_POST);
685 mpfps_paddr = mptable_probe();
687 mptable_map(&mpt, mpfps_paddr);
691 if (apic_io_enable) {
694 panic("no MP table, disable APIC_IO! (set hw.apic_io_enable=0)\n");
696 mptable_map(&mpt, mpfps_paddr);
699 * Examine the MP table for needed info
706 /* Post scan cleanup */
709 setup_apic_irq_mapping();
711 /* fill the LOGICAL io_apic_versions table */
712 for (apic = 0; apic < mp_napics; ++apic) {
713 ux = ioapic_read(apic, IOAPIC_VER);
714 io_apic_versions[apic] = ux;
715 io_apic_set_id(apic, IO_TO_ID(apic));
718 /* program each IO APIC in the system */
719 for (apic = 0; apic < mp_napics; ++apic)
720 if (io_apic_setup(apic) < 0)
721 panic("IO APIC setup failure");
726 * These are required for SMP operation
729 /* install a 'Spurious INTerrupt' vector */
730 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
731 SDT_SYSIGT, SEL_KPL, 0);
733 /* install an inter-CPU IPI for TLB invalidation */
734 setidt(XINVLTLB_OFFSET, Xinvltlb,
735 SDT_SYSIGT, SEL_KPL, 0);
737 /* install an inter-CPU IPI for IPIQ messaging */
738 setidt(XIPIQ_OFFSET, Xipiq,
739 SDT_SYSIGT, SEL_KPL, 0);
741 /* install a timer vector */
742 setidt(XTIMER_OFFSET, Xtimer,
743 SDT_SYSIGT, SEL_KPL, 0);
745 /* install an inter-CPU IPI for CPU stop/restart */
746 setidt(XCPUSTOP_OFFSET, Xcpustop,
747 SDT_SYSIGT, SEL_KPL, 0);
749 /* start each Application Processor */
750 start_all_aps(boot_addr);
755 * look for the MP spec signature
758 /* string defined by the Intel MP Spec as identifying the MP table */
759 #define MP_SIG 0x5f504d5f /* _MP_ */
760 #define NEXT(X) ((X) += 4)
762 mptable_search_sig(u_int32_t target, int count)
768 KKASSERT(target != 0);
770 map_size = count * sizeof(u_int32_t);
771 addr = pmap_mapdev((vm_paddr_t)target, map_size);
774 for (x = 0; x < count; NEXT(x)) {
775 if (addr[x] == MP_SIG) {
776 /* make array index a byte index */
777 ret = target + (x * sizeof(u_int32_t));
782 pmap_unmapdev((vm_offset_t)addr, map_size);
787 typedef struct BUSDATA {
789 enum busTypes bus_type;
792 typedef struct INTDATA {
802 typedef struct BUSTYPENAME {
807 static bus_type_name bus_type_table[] =
813 {UNKNOWN_BUSTYPE, "---"},
816 {UNKNOWN_BUSTYPE, "---"},
817 {UNKNOWN_BUSTYPE, "---"},
818 {UNKNOWN_BUSTYPE, "---"},
819 {UNKNOWN_BUSTYPE, "---"},
820 {UNKNOWN_BUSTYPE, "---"},
822 {UNKNOWN_BUSTYPE, "---"},
823 {UNKNOWN_BUSTYPE, "---"},
824 {UNKNOWN_BUSTYPE, "---"},
825 {UNKNOWN_BUSTYPE, "---"},
827 {UNKNOWN_BUSTYPE, "---"}
830 /* from MP spec v1.4, table 5-1 */
831 static int default_data[7][5] =
833 /* nbus, id0, type0, id1, type1 */
834 {1, 0, ISA, 255, 255},
835 {1, 0, EISA, 255, 255},
836 {1, 0, EISA, 255, 255},
837 {1, 0, MCA, 255, 255},
839 {2, 0, EISA, 1, PCI},
844 static bus_datum *bus_data;
846 /* the IO INT data, one entry per possible APIC INTerrupt */
847 static io_int *io_apic_ints;
850 static int processor_entry (const struct PROCENTRY *entry, int cpu);
851 static int bus_entry (const struct BUSENTRY *entry, int bus);
852 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
853 static int int_entry (const struct INTENTRY *entry, int intr);
854 static int lookup_bus_type (char *name);
857 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
859 const struct IOAPICENTRY *ioapic_ent;
862 case 1: /* bus_entry */
866 case 2: /* io_apic_entry */
868 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
869 io_apic_address[mp_napics++] =
870 (vm_offset_t)ioapic_ent->apic_address;
874 case 3: /* int_entry */
882 * 1st pass on motherboard's Intel MP specification table.
891 mptable_pass1(struct mptable_pos *mpt)
896 POSTCODE(MPTABLE_PASS1_POST);
899 KKASSERT(fps != NULL);
901 /* clear various tables */
902 for (x = 0; x < NAPICID; ++x)
903 io_apic_address[x] = ~0; /* IO APIC address table */
909 /* check for use of 'default' configuration */
910 if (fps->mpfb1 != 0) {
911 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
912 mp_nbusses = default_data[fps->mpfb1 - 1][0];
918 error = mptable_iterate_entries(mpt->mp_cth,
919 mptable_ioapic_pass1_callback, NULL);
921 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
925 struct mptable_ioapic2_cbarg {
932 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
934 struct mptable_ioapic2_cbarg *arg = xarg;
938 if (bus_entry(pos, arg->bus))
943 if (io_apic_entry(pos, arg->apic))
948 if (int_entry(pos, arg->intr))
956 * 2nd pass on motherboard's Intel MP specification table.
959 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
960 * IO_TO_ID(N), logical IO to APIC ID table
965 mptable_pass2(struct mptable_pos *mpt)
967 struct mptable_ioapic2_cbarg arg;
971 POSTCODE(MPTABLE_PASS2_POST);
974 KKASSERT(fps != NULL);
976 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
978 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
979 M_DEVBUF, M_WAITOK | M_ZERO);
980 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
982 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
985 for (x = 0; x < mp_napics; x++)
986 ioapic[x] = permanent_io_mapping(io_apic_address[x]);
988 /* clear various tables */
989 for (x = 0; x < NAPICID; ++x) {
990 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
991 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
994 /* clear bus data table */
995 for (x = 0; x < mp_nbusses; ++x)
996 bus_data[x].bus_id = 0xff;
998 /* clear IO APIC INT table */
999 for (x = 0; x < nintrs + FIXUP_EXTRA_APIC_INTS; ++x) {
1000 io_apic_ints[x].int_type = 0xff;
1001 io_apic_ints[x].int_vector = 0xff;
1004 /* check for use of 'default' configuration */
1005 if (fps->mpfb1 != 0) {
1006 mptable_default(fps->mpfb1);
1010 bzero(&arg, sizeof(arg));
1011 error = mptable_iterate_entries(mpt->mp_cth,
1012 mptable_ioapic_pass2_callback, &arg);
1014 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
1018 * Check if we should perform a hyperthreading "fix-up" to
1019 * enumerate any logical CPU's that aren't already listed
1022 * XXX: We assume that all of the physical CPUs in the
1023 * system have the same number of logical CPUs.
1025 * XXX: We assume that APIC ID's are allocated such that
1026 * the APIC ID's for a physical processor are aligned
1027 * with the number of logical CPU's in the processor.
1030 mptable_hyperthread_fixup(cpumask_t id_mask, int cpu_count)
1032 int i, id, lcpus_max, logical_cpus;
1034 if ((cpu_feature & CPUID_HTT) == 0)
1037 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1041 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1043 * INSTRUCTION SET REFERENCE, A-M (#253666)
1044 * Page 3-181, Table 3-20
1045 * "The nearest power-of-2 integer that is not smaller
1046 * than EBX[23:16] is the number of unique initial APIC
1047 * IDs reserved for addressing different logical
1048 * processors in a physical package."
1050 for (i = 0; ; ++i) {
1051 if ((1 << i) >= lcpus_max) {
1058 KKASSERT(cpu_count != 0);
1059 if (cpu_count == lcpus_max) {
1060 /* We have nothing to fix */
1062 } else if (cpu_count == 1) {
1063 /* XXX this may be incorrect */
1064 logical_cpus = lcpus_max;
1066 int cur, prev, dist;
1069 * Calculate the distances between two nearest
1070 * APIC IDs. If all such distances are same,
1071 * then it is the number of missing cpus that
1072 * we are going to fill later.
1074 dist = cur = prev = -1;
1075 for (id = 0; id < MAXCPU; ++id) {
1076 if ((id_mask & CPUMASK(id)) == 0)
1081 int new_dist = cur - prev;
1087 * Make sure that all distances
1088 * between two nearest APIC IDs
1091 if (dist != new_dist)
1099 /* Must be power of 2 */
1100 if (dist & (dist - 1))
1103 /* Can't exceed CPU package capacity */
1104 if (dist > lcpus_max)
1105 logical_cpus = lcpus_max;
1107 logical_cpus = dist;
1111 * For each APIC ID of a CPU that is set in the mask,
1112 * scan the other candidate APIC ID's for this
1113 * physical processor. If any of those ID's are
1114 * already in the table, then kill the fixup.
1116 for (id = 0; id < MAXCPU; id++) {
1117 if ((id_mask & CPUMASK(id)) == 0)
1119 /* First, make sure we are on a logical_cpus boundary. */
1120 if (id % logical_cpus != 0)
1122 for (i = id + 1; i < id + logical_cpus; i++)
1123 if ((id_mask & CPUMASK(i)) != 0)
1126 return logical_cpus;
1130 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1134 vm_size_t cth_mapsz = 0;
1136 bzero(mpt, sizeof(*mpt));
1138 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1139 if (fps->pap != 0) {
1141 * Map configuration table header to get
1142 * the base table size
1144 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1145 cth_mapsz = cth->base_table_length;
1146 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1148 if (cth_mapsz < sizeof(*cth)) {
1149 kprintf("invalid base MP table length %d\n",
1151 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1156 * Map the base table
1158 cth = pmap_mapdev(fps->pap, cth_mapsz);
1163 mpt->mp_cth_mapsz = cth_mapsz;
1169 mptable_unmap(struct mptable_pos *mpt)
1171 if (mpt->mp_cth != NULL) {
1172 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1174 mpt->mp_cth_mapsz = 0;
1176 if (mpt->mp_fps != NULL) {
1177 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1183 assign_apic_irq(int apic, int intpin, int irq)
1187 if (int_to_apicintpin[irq].ioapic != -1)
1188 panic("assign_apic_irq: inconsistent table");
1190 int_to_apicintpin[irq].ioapic = apic;
1191 int_to_apicintpin[irq].int_pin = intpin;
1192 int_to_apicintpin[irq].apic_address = ioapic[apic];
1193 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1195 for (x = 0; x < nintrs; x++) {
1196 if ((io_apic_ints[x].int_type == 0 ||
1197 io_apic_ints[x].int_type == 3) &&
1198 io_apic_ints[x].int_vector == 0xff &&
1199 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1200 io_apic_ints[x].dst_apic_int == intpin)
1201 io_apic_ints[x].int_vector = irq;
1206 revoke_apic_irq(int irq)
1212 if (int_to_apicintpin[irq].ioapic == -1)
1213 panic("revoke_apic_irq: inconsistent table");
1215 oldapic = int_to_apicintpin[irq].ioapic;
1216 oldintpin = int_to_apicintpin[irq].int_pin;
1218 int_to_apicintpin[irq].ioapic = -1;
1219 int_to_apicintpin[irq].int_pin = 0;
1220 int_to_apicintpin[irq].apic_address = NULL;
1221 int_to_apicintpin[irq].redirindex = 0;
1223 for (x = 0; x < nintrs; x++) {
1224 if ((io_apic_ints[x].int_type == 0 ||
1225 io_apic_ints[x].int_type == 3) &&
1226 io_apic_ints[x].int_vector != 0xff &&
1227 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1228 io_apic_ints[x].dst_apic_int == oldintpin)
1229 io_apic_ints[x].int_vector = 0xff;
1237 allocate_apic_irq(int intr)
1243 if (io_apic_ints[intr].int_vector != 0xff)
1244 return; /* Interrupt handler already assigned */
1246 if (io_apic_ints[intr].int_type != 0 &&
1247 (io_apic_ints[intr].int_type != 3 ||
1248 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1249 io_apic_ints[intr].dst_apic_int == 0)))
1250 return; /* Not INT or ExtInt on != (0, 0) */
1253 while (irq < APIC_INTMAPSIZE &&
1254 int_to_apicintpin[irq].ioapic != -1)
1257 if (irq >= APIC_INTMAPSIZE)
1258 return; /* No free interrupt handlers */
1260 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1261 intpin = io_apic_ints[intr].dst_apic_int;
1263 assign_apic_irq(apic, intpin, irq);
1268 swap_apic_id(int apic, int oldid, int newid)
1275 return; /* Nothing to do */
1277 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1278 apic, oldid, newid);
1280 /* Swap physical APIC IDs in interrupt entries */
1281 for (x = 0; x < nintrs; x++) {
1282 if (io_apic_ints[x].dst_apic_id == oldid)
1283 io_apic_ints[x].dst_apic_id = newid;
1284 else if (io_apic_ints[x].dst_apic_id == newid)
1285 io_apic_ints[x].dst_apic_id = oldid;
1288 /* Swap physical APIC IDs in IO_TO_ID mappings */
1289 for (oapic = 0; oapic < mp_napics; oapic++)
1290 if (IO_TO_ID(oapic) == newid)
1293 if (oapic < mp_napics) {
1294 kprintf("Changing APIC ID for IO APIC #%d from "
1295 "%d to %d in MP table\n",
1296 oapic, newid, oldid);
1297 IO_TO_ID(oapic) = oldid;
1299 IO_TO_ID(apic) = newid;
1304 fix_id_to_io_mapping(void)
1308 for (x = 0; x < NAPICID; x++)
1311 for (x = 0; x <= mp_naps; x++) {
1312 if ((u_int)CPU_TO_ID(x) < NAPICID)
1313 ID_TO_IO(CPU_TO_ID(x)) = x;
1316 for (x = 0; x < mp_napics; x++) {
1317 if ((u_int)IO_TO_ID(x) < NAPICID)
1318 ID_TO_IO(IO_TO_ID(x)) = x;
1324 first_free_apic_id(void)
1328 for (freeid = 0; freeid < NAPICID; freeid++) {
1329 for (x = 0; x <= mp_naps; x++)
1330 if (CPU_TO_ID(x) == freeid)
1334 for (x = 0; x < mp_napics; x++)
1335 if (IO_TO_ID(x) == freeid)
1346 io_apic_id_acceptable(int apic, int id)
1348 int cpu; /* Logical CPU number */
1349 int oapic; /* Logical IO APIC number for other IO APIC */
1351 if ((u_int)id >= NAPICID)
1352 return 0; /* Out of range */
1354 for (cpu = 0; cpu <= mp_naps; cpu++) {
1355 if (CPU_TO_ID(cpu) == id)
1356 return 0; /* Conflict with CPU */
1359 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++) {
1360 if (IO_TO_ID(oapic) == id)
1361 return 0; /* Conflict with other APIC */
1364 return 1; /* ID is acceptable for IO APIC */
1369 io_apic_find_int_entry(int apic, int pin)
1373 /* search each of the possible INTerrupt sources */
1374 for (x = 0; x < nintrs; ++x) {
1375 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1376 (pin == io_apic_ints[x].dst_apic_int))
1377 return (&io_apic_ints[x]);
1383 * parse an Intel MP specification table
1390 int apic; /* IO APIC unit number */
1391 int freeid; /* Free physical APIC ID */
1392 int physid; /* Current physical IO APIC ID */
1394 int bus_0 = 0; /* Stop GCC warning */
1395 int bus_pci = 0; /* Stop GCC warning */
1399 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1400 * did it wrong. The MP spec says that when more than 1 PCI bus
1401 * exists the BIOS must begin with bus entries for the PCI bus and use
1402 * actual PCI bus numbering. This implies that when only 1 PCI bus
1403 * exists the BIOS can choose to ignore this ordering, and indeed many
1404 * MP motherboards do ignore it. This causes a problem when the PCI
1405 * sub-system makes requests of the MP sub-system based on PCI bus
1406 * numbers. So here we look for the situation and renumber the
1407 * busses and associated INTs in an effort to "make it right".
1410 /* find bus 0, PCI bus, count the number of PCI busses */
1411 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1412 if (bus_data[x].bus_id == 0) {
1415 if (bus_data[x].bus_type == PCI) {
1421 * bus_0 == slot of bus with ID of 0
1422 * bus_pci == slot of last PCI bus encountered
1425 /* check the 1 PCI bus case for sanity */
1426 /* if it is number 0 all is well */
1427 if (num_pci_bus == 1 &&
1428 bus_data[bus_pci].bus_id != 0) {
1430 /* mis-numbered, swap with whichever bus uses slot 0 */
1432 /* swap the bus entry types */
1433 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1434 bus_data[bus_0].bus_type = PCI;
1436 /* swap each relevant INTerrupt entry */
1437 id = bus_data[bus_pci].bus_id;
1438 for (x = 0; x < nintrs; ++x) {
1439 if (io_apic_ints[x].src_bus_id == id) {
1440 io_apic_ints[x].src_bus_id = 0;
1442 else if (io_apic_ints[x].src_bus_id == 0) {
1443 io_apic_ints[x].src_bus_id = id;
1448 /* Assign IO APIC IDs.
1450 * First try the existing ID. If a conflict is detected, try
1451 * the ID in the MP table. If a conflict is still detected, find
1454 * We cannot use the ID_TO_IO table before all conflicts has been
1455 * resolved and the table has been corrected.
1457 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1459 /* First try to use the value set by the BIOS */
1460 physid = io_apic_get_id(apic);
1461 if (io_apic_id_acceptable(apic, physid)) {
1462 if (IO_TO_ID(apic) != physid)
1463 swap_apic_id(apic, IO_TO_ID(apic), physid);
1467 /* Then check if the value in the MP table is acceptable */
1468 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1471 /* Last resort, find a free APIC ID and use it */
1472 freeid = first_free_apic_id();
1473 if (freeid >= NAPICID)
1474 panic("No free physical APIC IDs found");
1476 if (io_apic_id_acceptable(apic, freeid)) {
1477 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1480 panic("Free physical APIC ID not usable");
1482 fix_id_to_io_mapping();
1484 /* detect and fix broken Compaq MP table */
1485 if (apic_int_type(0, 0) == -1) {
1486 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1487 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1488 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1489 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1490 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1491 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1493 } else if (apic_int_type(0, 0) == 0) {
1494 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1495 for (x = 0; x < nintrs; ++x)
1496 if ((ID_TO_IO(io_apic_ints[x].dst_apic_id) == 0) &&
1497 (io_apic_ints[x].dst_apic_int) == 0) {
1498 io_apic_ints[x].int_type = 3;
1499 io_apic_ints[x].int_vector = 0xff;
1505 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1506 * controllers universally come in pairs. If IRQ 14 is specified
1507 * as an ISA interrupt, then IRQ 15 had better be too.
1509 * [ Shuttle XPC / AMD Athlon X2 ]
1510 * The MPTable is missing an entry for IRQ 15. Note that the
1511 * ACPI table has an entry for both 14 and 15.
1513 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1514 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1515 io14 = io_apic_find_int_entry(0, 14);
1516 io_apic_ints[nintrs] = *io14;
1517 io_apic_ints[nintrs].src_bus_irq = 15;
1518 io_apic_ints[nintrs].dst_apic_int = 15;
1523 /* Assign low level interrupt handlers */
1525 setup_apic_irq_mapping(void)
1531 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1532 int_to_apicintpin[x].ioapic = -1;
1533 int_to_apicintpin[x].int_pin = 0;
1534 int_to_apicintpin[x].apic_address = NULL;
1535 int_to_apicintpin[x].redirindex = 0;
1537 /* Default to masked */
1538 int_to_apicintpin[x].flags = IOAPIC_IM_FLAG_MASKED;
1541 /* First assign ISA/EISA interrupts */
1542 for (x = 0; x < nintrs; x++) {
1543 int_vector = io_apic_ints[x].src_bus_irq;
1544 if (int_vector < APIC_INTMAPSIZE &&
1545 io_apic_ints[x].int_vector == 0xff &&
1546 int_to_apicintpin[int_vector].ioapic == -1 &&
1547 (apic_int_is_bus_type(x, ISA) ||
1548 apic_int_is_bus_type(x, EISA)) &&
1549 io_apic_ints[x].int_type == 0) {
1550 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1551 io_apic_ints[x].dst_apic_int,
1556 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1557 for (x = 0; x < nintrs; x++) {
1558 if (io_apic_ints[x].dst_apic_int == 0 &&
1559 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1560 io_apic_ints[x].int_vector == 0xff &&
1561 int_to_apicintpin[0].ioapic == -1 &&
1562 io_apic_ints[x].int_type == 3) {
1563 assign_apic_irq(0, 0, 0);
1568 /* Assign PCI interrupts */
1569 for (x = 0; x < nintrs; ++x) {
1570 if (io_apic_ints[x].int_type == 0 &&
1571 io_apic_ints[x].int_vector == 0xff &&
1572 apic_int_is_bus_type(x, PCI))
1573 allocate_apic_irq(x);
1578 mp_set_cpuids(int cpu_id, int apic_id)
1580 CPU_TO_ID(cpu_id) = apic_id;
1581 ID_TO_CPU(apic_id) = cpu_id;
1585 processor_entry(const struct PROCENTRY *entry, int cpu)
1589 /* check for usability */
1590 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1593 /* check for BSP flag */
1594 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1595 mp_set_cpuids(0, entry->apic_id);
1596 return 0; /* its already been counted */
1599 /* add another AP to list, if less than max number of CPUs */
1600 else if (cpu < MAXCPU) {
1601 mp_set_cpuids(cpu, entry->apic_id);
1609 bus_entry(const struct BUSENTRY *entry, int bus)
1614 /* encode the name into an index */
1615 for (x = 0; x < 6; ++x) {
1616 if ((c = entry->bus_type[x]) == ' ')
1622 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1623 panic("unknown bus type: '%s'", name);
1625 bus_data[bus].bus_id = entry->bus_id;
1626 bus_data[bus].bus_type = x;
1632 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1634 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1637 IO_TO_ID(apic) = entry->apic_id;
1638 ID_TO_IO(entry->apic_id) = apic;
1644 lookup_bus_type(char *name)
1648 for (x = 0; x < MAX_BUSTYPE; ++x)
1649 if (strcmp(bus_type_table[x].name, name) == 0)
1650 return bus_type_table[x].type;
1652 return UNKNOWN_BUSTYPE;
1656 int_entry(const struct INTENTRY *entry, int intr)
1660 io_apic_ints[intr].int_type = entry->int_type;
1661 io_apic_ints[intr].int_flags = entry->int_flags;
1662 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1663 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1664 if (entry->dst_apic_id == 255) {
1665 /* This signal goes to all IO APICS. Select an IO APIC
1666 with sufficient number of interrupt pins */
1667 for (apic = 0; apic < mp_napics; apic++)
1668 if (((ioapic_read(apic, IOAPIC_VER) &
1669 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1670 entry->dst_apic_int)
1672 if (apic < mp_napics)
1673 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1675 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1677 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1678 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1684 apic_int_is_bus_type(int intr, int bus_type)
1688 for (bus = 0; bus < mp_nbusses; ++bus)
1689 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1690 && ((int) bus_data[bus].bus_type == bus_type))
1697 * Given a traditional ISA INT mask, return an APIC mask.
1700 isa_apic_mask(u_int isa_mask)
1705 #if defined(SKIP_IRQ15_REDIRECT)
1706 if (isa_mask == (1 << 15)) {
1707 kprintf("skipping ISA IRQ15 redirect\n");
1710 #endif /* SKIP_IRQ15_REDIRECT */
1712 isa_irq = ffs(isa_mask); /* find its bit position */
1713 if (isa_irq == 0) /* doesn't exist */
1715 --isa_irq; /* make it zero based */
1717 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1721 return (1 << apic_pin); /* convert pin# to a mask */
1725 * Determine which APIC pin an ISA/EISA INT is attached to.
1727 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1728 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1729 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1730 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1732 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1734 isa_apic_irq(int isa_irq)
1738 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1739 if (INTTYPE(intr) == 0) { /* standard INT */
1740 if (SRCBUSIRQ(intr) == isa_irq) {
1741 if (apic_int_is_bus_type(intr, ISA) ||
1742 apic_int_is_bus_type(intr, EISA)) {
1743 if (INTIRQ(intr) == 0xff)
1744 return -1; /* unassigned */
1745 return INTIRQ(intr); /* found */
1750 return -1; /* NOT found */
1755 * Determine which APIC pin a PCI INT is attached to.
1757 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1758 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1759 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1761 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1765 --pciInt; /* zero based */
1767 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1768 if ((INTTYPE(intr) == 0) /* standard INT */
1769 && (SRCBUSID(intr) == pciBus)
1770 && (SRCBUSDEVICE(intr) == pciDevice)
1771 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1772 if (apic_int_is_bus_type(intr, PCI)) {
1773 if (INTIRQ(intr) == 0xff) {
1774 kprintf("IOAPIC: pci_apic_irq() "
1776 return -1; /* unassigned */
1778 return INTIRQ(intr); /* exact match */
1783 return -1; /* NOT found */
1787 next_apic_irq(int irq)
1794 for (intr = 0; intr < nintrs; intr++) {
1795 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1797 bus = SRCBUSID(intr);
1798 bustype = apic_bus_type(bus);
1799 if (bustype != ISA &&
1805 if (intr >= nintrs) {
1808 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1809 if (INTTYPE(ointr) != 0)
1811 if (bus != SRCBUSID(ointr))
1813 if (bustype == PCI) {
1814 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1816 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1819 if (bustype == ISA || bustype == EISA) {
1820 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1823 if (INTPIN(intr) == INTPIN(ointr))
1827 if (ointr >= nintrs) {
1830 return INTIRQ(ointr);
1843 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1846 * Exactly what this means is unclear at this point. It is a solution
1847 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1848 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1849 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1853 undirect_isa_irq(int rirq)
1857 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1858 /** FIXME: tickle the MB redirector chip */
1862 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1869 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1872 undirect_pci_irq(int rirq)
1876 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1878 /** FIXME: tickle the MB redirector chip */
1882 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1890 * given a bus ID, return:
1891 * the bus type if found
1895 apic_bus_type(int id)
1899 for (x = 0; x < mp_nbusses; ++x)
1900 if (bus_data[x].bus_id == id)
1901 return bus_data[x].bus_type;
1907 * given a LOGICAL APIC# and pin#, return:
1908 * the associated src bus ID if found
1912 apic_src_bus_id(int apic, int pin)
1916 /* search each of the possible INTerrupt sources */
1917 for (x = 0; x < nintrs; ++x)
1918 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1919 (pin == io_apic_ints[x].dst_apic_int))
1920 return (io_apic_ints[x].src_bus_id);
1922 return -1; /* NOT found */
1926 * given a LOGICAL APIC# and pin#, return:
1927 * the associated src bus IRQ if found
1931 apic_src_bus_irq(int apic, int pin)
1935 for (x = 0; x < nintrs; x++)
1936 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1937 (pin == io_apic_ints[x].dst_apic_int))
1938 return (io_apic_ints[x].src_bus_irq);
1940 return -1; /* NOT found */
1945 * given a LOGICAL APIC# and pin#, return:
1946 * the associated INTerrupt type if found
1950 apic_int_type(int apic, int pin)
1954 /* search each of the possible INTerrupt sources */
1955 for (x = 0; x < nintrs; ++x) {
1956 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1957 (pin == io_apic_ints[x].dst_apic_int))
1958 return (io_apic_ints[x].int_type);
1960 return -1; /* NOT found */
1964 * Return the IRQ associated with an APIC pin
1967 apic_irq(int apic, int pin)
1972 for (x = 0; x < nintrs; ++x) {
1973 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1974 (pin == io_apic_ints[x].dst_apic_int)) {
1975 res = io_apic_ints[x].int_vector;
1978 if (apic != int_to_apicintpin[res].ioapic)
1979 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1980 if (pin != int_to_apicintpin[res].int_pin)
1981 panic("apic_irq inconsistent table (2)");
1990 * given a LOGICAL APIC# and pin#, return:
1991 * the associated trigger mode if found
1995 apic_trigger(int apic, int pin)
1999 /* search each of the possible INTerrupt sources */
2000 for (x = 0; x < nintrs; ++x)
2001 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2002 (pin == io_apic_ints[x].dst_apic_int))
2003 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2005 return -1; /* NOT found */
2010 * given a LOGICAL APIC# and pin#, return:
2011 * the associated 'active' level if found
2015 apic_polarity(int apic, int pin)
2019 /* search each of the possible INTerrupt sources */
2020 for (x = 0; x < nintrs; ++x)
2021 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2022 (pin == io_apic_ints[x].dst_apic_int))
2023 return (io_apic_ints[x].int_flags & 0x03);
2025 return -1; /* NOT found */
2029 * set data according to MP defaults
2030 * FIXME: probably not complete yet...
2033 mptable_default(int type)
2039 kprintf(" MP default config type: %d\n", type);
2042 kprintf(" bus: ISA, APIC: 82489DX\n");
2045 kprintf(" bus: EISA, APIC: 82489DX\n");
2048 kprintf(" bus: EISA, APIC: 82489DX\n");
2051 kprintf(" bus: MCA, APIC: 82489DX\n");
2054 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2057 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2060 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2063 kprintf(" future type\n");
2069 /* one and only IO APIC */
2070 io_apic_id = (ioapic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2073 * sanity check, refer to MP spec section 3.6.6, last paragraph
2074 * necessary as some hardware isn't properly setting up the IO APIC
2076 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2077 if (io_apic_id != 2) {
2079 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2080 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2081 io_apic_set_id(0, 2);
2084 IO_TO_ID(0) = io_apic_id;
2085 ID_TO_IO(io_apic_id) = 0;
2087 /* fill out bus entries */
2096 bus_data[0].bus_id = default_data[type - 1][1];
2097 bus_data[0].bus_type = default_data[type - 1][2];
2098 bus_data[1].bus_id = default_data[type - 1][3];
2099 bus_data[1].bus_type = default_data[type - 1][4];
2102 /* case 4: case 7: MCA NOT supported */
2103 default: /* illegal/reserved */
2104 panic("BAD default MP config: %d", type);
2108 /* general cases from MP v1.4, table 5-2 */
2109 for (pin = 0; pin < 16; ++pin) {
2110 io_apic_ints[pin].int_type = 0;
2111 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2112 io_apic_ints[pin].src_bus_id = 0;
2113 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2114 io_apic_ints[pin].dst_apic_id = io_apic_id;
2115 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2118 /* special cases from MP v1.4, table 5-2 */
2120 io_apic_ints[2].int_type = 0xff; /* N/C */
2121 io_apic_ints[13].int_type = 0xff; /* N/C */
2122 #if !defined(APIC_MIXED_MODE)
2124 panic("sorry, can't support type 2 default yet");
2125 #endif /* APIC_MIXED_MODE */
2128 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2131 io_apic_ints[0].int_type = 0xff; /* N/C */
2133 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2137 * Map a physical memory address representing I/O into KVA. The I/O
2138 * block is assumed not to cross a page boundary.
2141 permanent_io_mapping(vm_paddr_t pa)
2143 KKASSERT(pa < 0x100000000LL);
2145 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
2149 * start each AP in our list
2152 start_all_aps(u_int boot_addr)
2154 vm_offset_t va = boot_address + KERNBASE;
2155 u_int64_t *pt4, *pt3, *pt2;
2161 u_char mpbiosreason;
2162 u_long mpbioswarmvec;
2163 struct mdglobaldata *gd;
2164 struct privatespace *ps;
2166 POSTCODE(START_ALL_APS_POST);
2168 /* Initialize BSP's local APIC */
2169 apic_initialize(TRUE);
2172 MachIntrABI.finalize();
2174 /* install the AP 1st level boot code */
2175 pmap_kenter(va, boot_address);
2176 cpu_invlpg((void *)va); /* JG XXX */
2177 bcopy(mptramp_start, (void *)va, bootMP_size);
2179 /* Locate the page tables, they'll be below the trampoline */
2180 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2181 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2182 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2184 /* Create the initial 1GB replicated page tables */
2185 for (i = 0; i < 512; i++) {
2186 /* Each slot of the level 4 pages points to the same level 3 page */
2187 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2188 pt4[i] |= PG_V | PG_RW | PG_U;
2190 /* Each slot of the level 3 pages points to the same level 2 page */
2191 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2192 pt3[i] |= PG_V | PG_RW | PG_U;
2194 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2195 pt2[i] = i * (2 * 1024 * 1024);
2196 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2199 /* save the current value of the warm-start vector */
2200 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2201 outb(CMOS_REG, BIOS_RESET);
2202 mpbiosreason = inb(CMOS_DATA);
2204 /* setup a vector to our boot code */
2205 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2206 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2207 outb(CMOS_REG, BIOS_RESET);
2208 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2211 * If we have a TSC we can figure out the SMI interrupt rate.
2212 * The SMI does not necessarily use a constant rate. Spend
2213 * up to 250ms trying to figure it out.
2216 if (cpu_feature & CPUID_TSC) {
2217 set_apic_timer(275000);
2218 smilast = read_apic_timer();
2219 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2220 smicount = smitest();
2221 if (smibest == 0 || smilast - smicount < smibest)
2222 smibest = smilast - smicount;
2225 if (smibest > 250000)
2228 smibest = smibest * (int64_t)1000000 /
2229 get_apic_timer_frequency();
2233 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2234 1000000 / smibest, smibest);
2236 kprintf("SMP: Starting %d APs: ", mp_naps);
2238 for (x = 1; x <= mp_naps; ++x) {
2240 /* This is a bit verbose, it will go away soon. */
2242 /* first page of AP's private space */
2243 pg = x * x86_64_btop(sizeof(struct privatespace));
2245 /* allocate new private data page(s) */
2246 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2247 MDGLOBALDATA_BASEALLOC_SIZE);
2249 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2250 bzero(gd, sizeof(*gd));
2251 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2253 /* prime data page for it to use */
2254 mi_gdinit(&gd->mi, x);
2256 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2257 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2259 /* setup a vector to our boot code */
2260 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2261 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2262 outb(CMOS_REG, BIOS_RESET);
2263 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2266 * Setup the AP boot stack
2268 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2271 /* attempt to start the Application Processor */
2272 CHECK_INIT(99); /* setup checkpoints */
2273 if (!start_ap(gd, boot_addr, smibest)) {
2274 kprintf("\nAP #%d (PHY# %d) failed!\n",
2276 CHECK_PRINT("trace"); /* show checkpoints */
2277 /* better panic as the AP may be running loose */
2278 kprintf("panic y/n? [y] ");
2279 if (cngetc() != 'n')
2282 CHECK_PRINT("trace"); /* show checkpoints */
2284 /* record its version info */
2285 cpu_apic_versions[x] = cpu_apic_versions[0];
2288 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2291 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2292 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2295 ncpus2_shift = shift;
2296 ncpus2 = 1 << shift;
2297 ncpus2_mask = ncpus2 - 1;
2299 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2300 if ((1 << shift) < ncpus)
2302 ncpus_fit = 1 << shift;
2303 ncpus_fit_mask = ncpus_fit - 1;
2305 /* build our map of 'other' CPUs */
2306 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2307 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2308 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2310 /* fill in our (BSP) APIC version */
2311 cpu_apic_versions[0] = lapic->version;
2313 /* restore the warmstart vector */
2314 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2315 outb(CMOS_REG, BIOS_RESET);
2316 outb(CMOS_DATA, mpbiosreason);
2319 * NOTE! The idlestack for the BSP was setup by locore. Finish
2320 * up, clean out the P==V mapping we did earlier.
2324 /* number of APs actually started */
2330 * load the 1st level AP boot code into base memory.
2333 /* targets for relocation */
2334 extern void bigJump(void);
2335 extern void bootCodeSeg(void);
2336 extern void bootDataSeg(void);
2337 extern void MPentry(void);
2338 extern u_int MP_GDT;
2339 extern u_int mp_gdtbase;
2344 install_ap_tramp(u_int boot_addr)
2347 int size = *(int *) ((u_long) & bootMP_size);
2348 u_char *src = (u_char *) ((u_long) bootMP);
2349 u_char *dst = (u_char *) boot_addr + KERNBASE;
2350 u_int boot_base = (u_int) bootMP;
2355 POSTCODE(INSTALL_AP_TRAMP_POST);
2357 for (x = 0; x < size; ++x)
2361 * modify addresses in code we just moved to basemem. unfortunately we
2362 * need fairly detailed info about mpboot.s for this to work. changes
2363 * to mpboot.s might require changes here.
2366 /* boot code is located in KERNEL space */
2367 dst = (u_char *) boot_addr + KERNBASE;
2369 /* modify the lgdt arg */
2370 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2371 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2373 /* modify the ljmp target for MPentry() */
2374 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2375 *dst32 = ((u_int) MPentry - KERNBASE);
2377 /* modify the target for boot code segment */
2378 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2379 dst8 = (u_int8_t *) (dst16 + 1);
2380 *dst16 = (u_int) boot_addr & 0xffff;
2381 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2383 /* modify the target for boot data segment */
2384 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2385 dst8 = (u_int8_t *) (dst16 + 1);
2386 *dst16 = (u_int) boot_addr & 0xffff;
2387 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2393 * This function starts the AP (application processor) identified
2394 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2395 * to accomplish this. This is necessary because of the nuances
2396 * of the different hardware we might encounter. It ain't pretty,
2397 * but it seems to work.
2399 * NOTE: eventually an AP gets to ap_init(), which is called just
2400 * before the AP goes into the LWKT scheduler's idle loop.
2403 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2407 u_long icr_lo, icr_hi;
2409 POSTCODE(START_AP_POST);
2411 /* get the PHYSICAL APIC ID# */
2412 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2414 /* calculate the vector */
2415 vector = (boot_addr >> 12) & 0xff;
2417 /* We don't want anything interfering */
2420 /* Make sure the target cpu sees everything */
2424 * Try to detect when a SMI has occurred, wait up to 200ms.
2426 * If a SMI occurs during an AP reset but before we issue
2427 * the STARTUP command, the AP may brick. To work around
2428 * this problem we hold off doing the AP startup until
2429 * after we have detected the SMI. Hopefully another SMI
2430 * will not occur before we finish the AP startup.
2432 * Retries don't seem to help. SMIs have a window of opportunity
2433 * and if USB->legacy keyboard emulation is enabled in the BIOS
2434 * the interrupt rate can be quite high.
2436 * NOTE: Don't worry about the L1 cache load, it might bloat
2437 * ldelta a little but ndelta will be so huge when the SMI
2438 * occurs the detection logic will still work fine.
2441 set_apic_timer(200000);
2446 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2447 * and running the target CPU. OR this INIT IPI might be latched (P5
2448 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2451 * see apic/apicreg.h for icr bit definitions.
2453 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2457 * Setup the address for the target AP. We can setup
2458 * icr_hi once and then just trigger operations with
2461 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2462 icr_hi |= (physical_cpu << 24);
2463 icr_lo = lapic->icr_lo & 0xfff00000;
2464 lapic->icr_hi = icr_hi;
2467 * Do an INIT IPI: assert RESET
2469 * Use edge triggered mode to assert INIT
2471 lapic->icr_lo = icr_lo | 0x00004500;
2472 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2476 * The spec calls for a 10ms delay but we may have to use a
2477 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2478 * interrupt. We have other loops here too and dividing by 2
2479 * doesn't seem to be enough even after subtracting 350us,
2480 * so we divide by 4.
2482 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2483 * interrupt was detected we use the full 10ms.
2487 else if (smibest < 150 * 4 + 350)
2489 else if ((smibest - 350) / 4 < 10000)
2490 u_sleep((smibest - 350) / 4);
2495 * Do an INIT IPI: deassert RESET
2497 * Use level triggered mode to deassert. It is unclear
2498 * why we need to do this.
2500 lapic->icr_lo = icr_lo | 0x00008500;
2501 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2503 u_sleep(150); /* wait 150us */
2506 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2507 * latched, (P5 bug) this 1st STARTUP would then terminate
2508 * immediately, and the previously started INIT IPI would continue. OR
2509 * the previous INIT IPI has already run. and this STARTUP IPI will
2510 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2513 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2514 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2516 u_sleep(200); /* wait ~200uS */
2519 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2520 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2521 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2522 * recognized after hardware RESET or INIT IPI.
2524 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2525 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2528 /* Resume normal operation */
2531 /* wait for it to start, see ap_init() */
2532 set_apic_timer(5000000);/* == 5 seconds */
2533 while (read_apic_timer()) {
2534 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
2535 return 1; /* return SUCCESS */
2538 return 0; /* return FAILURE */
2553 while (read_apic_timer()) {
2555 for (count = 0; count < 100; ++count)
2556 ntsc = rdtsc(); /* force loop to occur */
2558 ndelta = ntsc - ltsc;
2559 if (ldelta > ndelta)
2561 if (ndelta > ldelta * 2)
2564 ldelta = ntsc - ltsc;
2567 return(read_apic_timer());
2571 * Synchronously flush the TLB on all other CPU's. The current cpu's
2572 * TLB is not flushed. If the caller wishes to flush the current cpu's
2573 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb().
2575 * NOTE: If for some reason we were unable to start all cpus we cannot
2576 * safely use broadcast IPIs.
2579 static cpumask_t smp_invltlb_req;
2581 #define SMP_INVLTLB_DEBUG
2587 struct mdglobaldata *md = mdcpu;
2588 #ifdef SMP_INVLTLB_DEBUG
2593 crit_enter_gd(&md->mi);
2594 md->gd_invltlb_ret = 0;
2595 ++md->mi.gd_cnt.v_smpinvltlb;
2596 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2597 #ifdef SMP_INVLTLB_DEBUG
2600 if (smp_startup_mask == smp_active_mask) {
2601 all_but_self_ipi(XINVLTLB_OFFSET);
2603 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
2604 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
2607 #ifdef SMP_INVLTLB_DEBUG
2609 kprintf("smp_invltlb: ipi sent\n");
2611 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
2612 (smp_active_mask & ~md->mi.gd_cpumask)) {
2615 #ifdef SMP_INVLTLB_DEBUG
2617 if (++count == 400000000) {
2618 print_backtrace(-1);
2619 kprintf("smp_invltlb: endless loop %08lx %08lx, "
2620 "rflags %016jx retry",
2621 (long)md->gd_invltlb_ret,
2622 (long)smp_invltlb_req,
2623 (intmax_t)read_rflags());
2624 __asm __volatile ("sti");
2627 lwkt_process_ipiq();
2629 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
2630 ~md->mi.gd_cpumask &
2634 kprintf("bcpu %d\n", bcpu);
2635 xgd = globaldata_find(bcpu);
2636 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
2639 Debugger("giving up");
2645 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2646 crit_exit_gd(&md->mi);
2653 * Called from Xinvltlb assembly with interrupts disabled. We didn't
2654 * bother to bump the critical section count or nested interrupt count
2655 * so only do very low level operations here.
2658 smp_invltlb_intr(void)
2660 struct mdglobaldata *md = mdcpu;
2661 struct mdglobaldata *omd;
2666 mask = smp_invltlb_req;
2669 cpu = BSFCPUMASK(mask);
2670 mask &= ~CPUMASK(cpu);
2671 omd = (struct mdglobaldata *)globaldata_find(cpu);
2672 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
2679 * When called the executing CPU will send an IPI to all other CPUs
2680 * requesting that they halt execution.
2682 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2684 * - Signals all CPUs in map to stop.
2685 * - Waits for each to stop.
2692 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2693 * from executing at same time.
2696 stop_cpus(cpumask_t map)
2698 map &= smp_active_mask;
2700 /* send the Xcpustop IPI to all CPUs in map */
2701 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2703 while ((stopped_cpus & map) != map)
2711 * Called by a CPU to restart stopped CPUs.
2713 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2715 * - Signals all CPUs in map to restart.
2716 * - Waits for each to restart.
2724 restart_cpus(cpumask_t map)
2726 /* signal other cpus to restart */
2727 started_cpus = map & smp_active_mask;
2729 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2736 * This is called once the mpboot code has gotten us properly relocated
2737 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2738 * and when it returns the scheduler will call the real cpu_idle() main
2739 * loop for the idlethread. Interrupts are disabled on entry and should
2740 * remain disabled at return.
2748 * Adjust smp_startup_mask to signal the BSP that we have started
2749 * up successfully. Note that we do not yet hold the BGL. The BSP
2750 * is waiting for our signal.
2752 * We can't set our bit in smp_active_mask yet because we are holding
2753 * interrupts physically disabled and remote cpus could deadlock
2754 * trying to send us an IPI.
2756 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
2760 * Interlock for finalization. Wait until mp_finish is non-zero,
2761 * then get the MP lock.
2763 * Note: We are in a critical section.
2765 * Note: we are the idle thread, we can only spin.
2767 * Note: The load fence is memory volatile and prevents the compiler
2768 * from improperly caching mp_finish, and the cpu from improperly
2771 while (mp_finish == 0)
2773 while (try_mplock() == 0)
2776 if (cpu_feature & CPUID_TSC) {
2778 * The BSP is constantly updating tsc0_offset, figure out
2779 * the relative difference to synchronize ktrdump.
2781 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2784 /* BSP may have changed PTD while we're waiting for the lock */
2787 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2791 /* Build our map of 'other' CPUs. */
2792 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2794 kprintf(" %d", mycpu->gd_cpuid);
2796 /* A quick check from sanity claus */
2797 apic_id = (apic_id_to_logical[(lapic->id & 0xff000000) >> 24]);
2798 if (mycpu->gd_cpuid != apic_id) {
2799 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2800 kprintf("SMP: apic_id = %d lapicid %d\n",
2801 apic_id, (lapic->id & 0xff000000) >> 24);
2803 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2805 panic("cpuid mismatch! boom!!");
2808 /* Initialize AP's local APIC for irq's */
2809 apic_initialize(FALSE);
2811 /* Set memory range attributes for this CPU to match the BSP */
2812 mem_range_AP_init();
2815 * Once we go active we must process any IPIQ messages that may
2816 * have been queued, because no actual IPI will occur until we
2817 * set our bit in the smp_active_mask. If we don't the IPI
2818 * message interlock could be left set which would also prevent
2821 * The idle loop doesn't expect the BGL to be held and while
2822 * lwkt_switch() normally cleans things up this is a special case
2823 * because we returning almost directly into the idle loop.
2825 * The idle thread is never placed on the runq, make sure
2826 * nothing we've done put it there.
2828 KKASSERT(get_mplock_count(curthread) == 1);
2829 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
2832 * Enable interrupts here. idle_restore will also do it, but
2833 * doing it here lets us clean up any strays that got posted to
2834 * the CPU during the AP boot while we are still in a critical
2837 __asm __volatile("sti; pause; pause"::);
2838 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
2840 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2841 lwkt_process_ipiq();
2844 * Releasing the mp lock lets the BSP finish up the SMP init
2847 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2851 * Get SMP fully working before we start initializing devices.
2859 kprintf("Finish MP startup\n");
2860 if (cpu_feature & CPUID_TSC)
2861 tsc0_offset = rdtsc();
2864 while (smp_active_mask != smp_startup_mask) {
2866 if (cpu_feature & CPUID_TSC)
2867 tsc0_offset = rdtsc();
2869 while (try_mplock() == 0)
2873 kprintf("Active CPU Mask: %016jx\n",
2874 (uintmax_t)smp_active_mask);
2878 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2881 cpu_send_ipiq(int dcpu)
2883 if (CPUMASK(dcpu) & smp_active_mask)
2884 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2887 #if 0 /* single_apic_ipi_passive() not working yet */
2889 * Returns 0 on failure, 1 on success
2892 cpu_send_ipiq_passive(int dcpu)
2895 if (CPUMASK(dcpu) & smp_active_mask) {
2896 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2897 APIC_DELMODE_FIXED);
2903 struct mptable_lapic_cbarg1 {
2906 u_int ht_apicid_mask;
2910 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2912 const struct PROCENTRY *ent;
2913 struct mptable_lapic_cbarg1 *arg = xarg;
2919 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2923 if (ent->apic_id < 32) {
2924 arg->ht_apicid_mask |= 1 << ent->apic_id;
2925 } else if (arg->ht_fixup) {
2926 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2932 struct mptable_lapic_cbarg2 {
2939 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2941 const struct PROCENTRY *ent;
2942 struct mptable_lapic_cbarg2 *arg = xarg;
2948 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2949 KKASSERT(!arg->found_bsp);
2953 if (processor_entry(ent, arg->cpu))
2956 if (arg->logical_cpus) {
2957 struct PROCENTRY proc;
2961 * Create fake mptable processor entries
2962 * and feed them to processor_entry() to
2963 * enumerate the logical CPUs.
2965 bzero(&proc, sizeof(proc));
2967 proc.cpu_flags = PROCENTRY_FLAG_EN;
2968 proc.apic_id = ent->apic_id;
2970 for (i = 1; i < arg->logical_cpus; i++) {
2972 processor_entry(&proc, arg->cpu);
2980 mptable_imcr(struct mptable_pos *mpt)
2982 /* record whether PIC or virtual-wire mode */
2983 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
2984 mpt->mp_fps->mpfb2 & 0x80);
2987 struct mptable_lapic_enumerator {
2988 struct lapic_enumerator enumerator;
2989 vm_paddr_t mpfps_paddr;
2993 mptable_lapic_default(void)
2995 int ap_apicid, bsp_apicid;
2997 mp_naps = 1; /* exclude BSP */
2999 /* Map local apic before the id field is accessed */
3000 lapic_map(DEFAULT_APIC_BASE);
3002 bsp_apicid = APIC_ID(lapic->id);
3003 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
3006 mp_set_cpuids(0, bsp_apicid);
3007 /* one and only AP */
3008 mp_set_cpuids(1, ap_apicid);
3014 * ID_TO_CPU(N), APIC ID to logical CPU table
3015 * CPU_TO_ID(N), logical CPU to APIC ID table
3018 mptable_lapic_enumerate(struct lapic_enumerator *e)
3020 struct mptable_pos mpt;
3021 struct mptable_lapic_cbarg1 arg1;
3022 struct mptable_lapic_cbarg2 arg2;
3024 int error, logical_cpus = 0;
3025 vm_offset_t lapic_addr;
3026 vm_paddr_t mpfps_paddr;
3028 mpfps_paddr = ((struct mptable_lapic_enumerator *)e)->mpfps_paddr;
3029 KKASSERT(mpfps_paddr != 0);
3031 error = mptable_map(&mpt, mpfps_paddr);
3033 panic("mptable_lapic_enumerate mptable_map failed\n");
3035 KKASSERT(mpt.mp_fps != NULL);
3038 * Check for use of 'default' configuration
3040 if (mpt.mp_fps->mpfb1 != 0) {
3041 mptable_lapic_default();
3042 mptable_unmap(&mpt);
3047 KKASSERT(cth != NULL);
3049 /* Save local apic address */
3050 lapic_addr = (vm_offset_t)cth->apic_address;
3051 KKASSERT(lapic_addr != 0);
3054 * Find out how many CPUs do we have
3056 bzero(&arg1, sizeof(arg1));
3057 arg1.ht_fixup = 1; /* Apply ht fixup by default */
3059 error = mptable_iterate_entries(cth,
3060 mptable_lapic_pass1_callback, &arg1);
3062 panic("mptable_iterate_entries(lapic_pass1) failed\n");
3063 KKASSERT(arg1.cpu_count != 0);
3065 /* See if we need to fixup HT logical CPUs. */
3066 if (arg1.ht_fixup) {
3067 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
3069 if (logical_cpus != 0)
3070 arg1.cpu_count *= logical_cpus;
3072 mp_naps = arg1.cpu_count;
3074 /* Qualify the numbers again, after possible HT fixup */
3075 if (mp_naps > MAXCPU) {
3076 kprintf("Warning: only using %d of %d available CPUs!\n",
3082 --mp_naps; /* subtract the BSP */
3085 * Link logical CPU id to local apic id
3087 bzero(&arg2, sizeof(arg2));
3089 arg2.logical_cpus = logical_cpus;
3091 error = mptable_iterate_entries(cth,
3092 mptable_lapic_pass2_callback, &arg2);
3094 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3095 KKASSERT(arg2.found_bsp);
3097 /* Map local apic */
3098 lapic_map(lapic_addr);
3100 mptable_unmap(&mpt);
3104 mptable_lapic_probe(struct lapic_enumerator *e)
3106 vm_paddr_t mpfps_paddr;
3108 mpfps_paddr = mptable_probe();
3109 if (mpfps_paddr == 0)
3112 ((struct mptable_lapic_enumerator *)e)->mpfps_paddr = mpfps_paddr;
3116 static struct mptable_lapic_enumerator mptable_lapic_enumerator = {
3118 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
3119 .lapic_probe = mptable_lapic_probe,
3120 .lapic_enumerate = mptable_lapic_enumerate
3125 mptable_apic_register(void)
3127 lapic_enumerator_register(&mptable_lapic_enumerator.enumerator);
3129 SYSINIT(madt, SI_BOOT2_PRESMP, SI_ORDER_ANY, mptable_apic_register, 0);