2 * Copyright (c) 2000 Berkeley Software Design, Inc.
3 * Copyright (c) 1997, 1998, 1999, 2000
4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/pci/if_pcn.c,v 1.5.2.10 2003/03/05 18:42:33 njl Exp $
34 * $DragonFly: src/sys/dev/netif/pcn/if_pcn.c,v 1.21 2005/06/13 18:43:58 joerg Exp $
38 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available
39 * from http://www.amd.com.
41 * Written by Bill Paul <wpaul@osd.bsdi.com>
45 * The AMD PCnet/PCI controllers are more advanced and functional
46 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain
47 * backwards compatibility with the LANCE and thus can be made
48 * to work with older LANCE drivers. This is in fact how the
49 * PCnet/PCI chips were supported in FreeBSD originally. The trouble
50 * is that the PCnet/PCI devices offer several performance enhancements
51 * which can't be exploited in LANCE compatibility mode. Chief among
52 * these enhancements is the ability to perform PCI DMA operations
53 * using 32-bit addressing (which eliminates the need for ISA
54 * bounce-buffering), and special receive buffer alignment (which
55 * allows the receive handler to pass packets to the upper protocol
56 * layers without copying on both the x86 and alpha platforms).
59 #include <sys/param.h>
60 #include <sys/systm.h>
61 #include <sys/sockio.h>
63 #include <sys/malloc.h>
64 #include <sys/kernel.h>
65 #include <sys/socket.h>
66 #include <sys/thread2.h>
69 #include <net/ifq_var.h>
70 #include <net/if_arp.h>
71 #include <net/ethernet.h>
72 #include <net/if_dl.h>
73 #include <net/if_media.h>
77 #include <vm/vm.h> /* for vtophys */
78 #include <vm/pmap.h> /* for vtophys */
79 #include <machine/clock.h> /* for DELAY */
80 #include <machine/bus_pio.h>
81 #include <machine/bus_memio.h>
82 #include <machine/bus.h>
83 #include <machine/resource.h>
87 #include "../mii_layer/mii.h"
88 #include "../mii_layer/miivar.h"
90 #include <bus/pci/pcireg.h>
91 #include <bus/pci/pcivar.h>
93 #define PCN_USEIOSPACE
95 #include "if_pcnreg.h"
97 /* "controller miibus0" required. See GENERIC if you get errors here. */
98 #include "miibus_if.h"
101 * Various supported device vendors/types and their names.
103 static struct pcn_type pcn_devs[] = {
104 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" },
105 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" },
109 static u_int32_t pcn_csr_read (struct pcn_softc *, int);
110 static u_int16_t pcn_csr_read16 (struct pcn_softc *, int);
111 static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int);
112 static void pcn_csr_write (struct pcn_softc *, int, int);
113 static u_int32_t pcn_bcr_read (struct pcn_softc *, int);
114 static void pcn_bcr_write (struct pcn_softc *, int, int);
116 static int pcn_probe (device_t);
117 static int pcn_attach (device_t);
118 static int pcn_detach (device_t);
120 static int pcn_newbuf (struct pcn_softc *, int, struct mbuf *);
121 static int pcn_encap (struct pcn_softc *,
122 struct mbuf *, u_int32_t *);
123 static void pcn_rxeof (struct pcn_softc *);
124 static void pcn_txeof (struct pcn_softc *);
125 static void pcn_intr (void *);
126 static void pcn_tick (void *);
127 static void pcn_start (struct ifnet *);
128 static int pcn_ioctl (struct ifnet *, u_long, caddr_t,
130 static void pcn_init (void *);
131 static void pcn_stop (struct pcn_softc *);
132 static void pcn_watchdog (struct ifnet *);
133 static void pcn_shutdown (device_t);
134 static int pcn_ifmedia_upd (struct ifnet *);
135 static void pcn_ifmedia_sts (struct ifnet *, struct ifmediareq *);
137 static int pcn_miibus_readreg (device_t, int, int);
138 static int pcn_miibus_writereg (device_t, int, int, int);
139 static void pcn_miibus_statchg (device_t);
141 static void pcn_setfilt (struct ifnet *);
142 static void pcn_setmulti (struct pcn_softc *);
143 static u_int32_t pcn_crc (caddr_t);
144 static void pcn_reset (struct pcn_softc *);
145 static int pcn_list_rx_init (struct pcn_softc *);
146 static int pcn_list_tx_init (struct pcn_softc *);
148 #ifdef PCN_USEIOSPACE
149 #define PCN_RES SYS_RES_IOPORT
150 #define PCN_RID PCN_PCI_LOIO
152 #define PCN_RES SYS_RES_MEMORY
153 #define PCN_RID PCN_PCI_LOMEM
156 static device_method_t pcn_methods[] = {
157 /* Device interface */
158 DEVMETHOD(device_probe, pcn_probe),
159 DEVMETHOD(device_attach, pcn_attach),
160 DEVMETHOD(device_detach, pcn_detach),
161 DEVMETHOD(device_shutdown, pcn_shutdown),
164 DEVMETHOD(bus_print_child, bus_generic_print_child),
165 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
168 DEVMETHOD(miibus_readreg, pcn_miibus_readreg),
169 DEVMETHOD(miibus_writereg, pcn_miibus_writereg),
170 DEVMETHOD(miibus_statchg, pcn_miibus_statchg),
175 static driver_t pcn_driver = {
178 sizeof(struct pcn_softc)
181 static devclass_t pcn_devclass;
183 DECLARE_DUMMY_MODULE(if_pcn);
184 DRIVER_MODULE(if_pcn, pci, pcn_driver, pcn_devclass, 0, 0);
185 DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0);
187 #define PCN_CSR_SETBIT(sc, reg, x) \
188 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x))
190 #define PCN_CSR_CLRBIT(sc, reg, x) \
191 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x))
193 #define PCN_BCR_SETBIT(sc, reg, x) \
194 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x))
196 #define PCN_BCR_CLRBIT(sc, reg, x) \
197 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x))
199 static u_int32_t pcn_csr_read(sc, reg)
200 struct pcn_softc *sc;
203 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
204 return(CSR_READ_4(sc, PCN_IO32_RDP));
207 static u_int16_t pcn_csr_read16(sc, reg)
208 struct pcn_softc *sc;
211 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
212 return(CSR_READ_2(sc, PCN_IO16_RDP));
215 static void pcn_csr_write(sc, reg, val)
216 struct pcn_softc *sc;
219 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
220 CSR_WRITE_4(sc, PCN_IO32_RDP, val);
224 static u_int32_t pcn_bcr_read(sc, reg)
225 struct pcn_softc *sc;
228 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
229 return(CSR_READ_4(sc, PCN_IO32_BDP));
232 static u_int16_t pcn_bcr_read16(sc, reg)
233 struct pcn_softc *sc;
236 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
237 return(CSR_READ_2(sc, PCN_IO16_BDP));
240 static void pcn_bcr_write(sc, reg, val)
241 struct pcn_softc *sc;
244 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
245 CSR_WRITE_4(sc, PCN_IO32_BDP, val);
249 static int pcn_miibus_readreg(dev, phy, reg)
253 struct pcn_softc *sc;
256 sc = device_get_softc(dev);
258 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr)
261 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
262 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF;
266 sc->pcn_phyaddr = phy;
271 static int pcn_miibus_writereg(dev, phy, reg, data)
275 struct pcn_softc *sc;
277 sc = device_get_softc(dev);
279 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
280 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data);
285 static void pcn_miibus_statchg(dev)
288 struct pcn_softc *sc;
289 struct mii_data *mii;
291 sc = device_get_softc(dev);
292 mii = device_get_softc(sc->pcn_miibus);
294 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
295 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
297 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
303 #define DC_POLY 0xEDB88320
305 static u_int32_t pcn_crc(addr)
308 u_int32_t idx, bit, data, crc;
310 /* Compute CRC for the address value. */
311 crc = 0xFFFFFFFF; /* initial value */
313 for (idx = 0; idx < 6; idx++) {
314 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
315 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0);
318 return ((crc >> 26) & 0x3F);
321 static void pcn_setmulti(sc)
322 struct pcn_softc *sc;
325 struct ifmultiaddr *ifma;
327 u_int16_t hashes[4] = { 0, 0, 0, 0 };
329 ifp = &sc->arpcom.ac_if;
331 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
333 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
334 for (i = 0; i < 4; i++)
335 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF);
336 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
340 /* first, zot all the existing hash bits */
341 for (i = 0; i < 4; i++)
342 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0);
344 /* now program new ones */
345 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
346 ifma = ifma->ifma_link.le_next) {
347 if (ifma->ifma_addr->sa_family != AF_LINK)
349 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
350 hashes[h >> 4] |= 1 << (h & 0xF);
353 for (i = 0; i < 4; i++)
354 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]);
356 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
361 static void pcn_reset(sc)
362 struct pcn_softc *sc;
365 * Issue a reset by reading from the RESET register.
366 * Note that we don't know if the chip is operating in
367 * 16-bit or 32-bit mode at this point, so we attempt
368 * to reset the chip both ways. If one fails, the other
371 CSR_READ_2(sc, PCN_IO16_RESET);
372 CSR_READ_4(sc, PCN_IO32_RESET);
374 /* Wait a little while for the chip to get its brains in order. */
377 /* Select 32-bit (DWIO) mode */
378 CSR_WRITE_4(sc, PCN_IO32_RDP, 0);
380 /* Select software style 3. */
381 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST);
387 * Probe for an AMD chip. Check the PCI vendor and device
388 * IDs against our list and return a device name if we find a match.
390 static int pcn_probe(dev)
394 struct pcn_softc *sc;
399 sc = device_get_softc(dev);
401 while(t->pcn_name != NULL) {
402 if ((pci_get_vendor(dev) == t->pcn_vid) &&
403 (pci_get_device(dev) == t->pcn_did)) {
405 * Temporarily map the I/O space
406 * so we can read the chip ID register.
409 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES,
411 if (sc->pcn_res == NULL) {
413 "couldn't map ports/memory\n");
416 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
417 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
419 * Note: we can *NOT* put the chip into
420 * 32-bit mode yet. The lnc driver will only
421 * work in 16-bit mode, and once the chip
422 * goes into 32-bit mode, the only way to
423 * get it out again is with a hardware reset.
424 * So if pcn_probe() is called before the
425 * lnc driver's probe routine, the chip will
426 * be locked into 32-bit operation and the lnc
427 * driver will be unable to attach to it.
428 * Note II: if the chip happens to already
429 * be in 32-bit mode, we still need to check
430 * the chip ID, but first we have to detect
431 * 32-bit mode using only 16-bit operations.
432 * The safest way to do this is to read the
433 * PCI subsystem ID from BCR23/24 and compare
434 * that with the value read from PCI config
437 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID);
439 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID);
441 * Note III: the test for 0x10001000 is a hack to
442 * pacify VMware, who's pseudo-PCnet interface is
443 * broken. Reading the subsystem register from PCI
444 * config space yeilds 0x00000000 while reading the
445 * same value from I/O space yeilds 0x10001000. It's
446 * not supposed to be that way.
448 if (chip_id == pci_read_config(dev,
449 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) {
450 /* We're in 16-bit mode. */
451 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1);
453 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0);
455 /* We're in 32-bit mode. */
456 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1);
458 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0);
460 bus_release_resource(dev, PCN_RES,
461 PCN_RID, sc->pcn_res);
463 sc->pcn_type = chip_id & PART_MASK;
464 switch(sc->pcn_type) {
476 device_set_desc(dev, t->pcn_name);
486 * Attach the interface. Allocate softc structures, do ifmedia
487 * setup and ethernet/BPF attach.
489 static int pcn_attach(dev)
492 uint8_t eaddr[ETHER_ADDR_LEN];
494 struct pcn_softc *sc;
496 int unit, error = 0, rid;
498 sc = device_get_softc(dev);
499 unit = device_get_unit(dev);
502 * Handle power management nonsense.
505 command = pci_read_config(dev, PCN_PCI_CAPID, 4) & 0x000000FF;
506 if (command == 0x01) {
508 command = pci_read_config(dev, PCN_PCI_PWRMGMTCTRL, 4);
509 if (command & PCN_PSTATE_MASK) {
510 u_int32_t iobase, membase, irq;
512 /* Save important PCI config data. */
513 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4);
514 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4);
515 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4);
517 /* Reset the power state. */
518 printf("pcn%d: chip is in D%d power mode "
519 "-- setting to D0\n", unit, command & PCN_PSTATE_MASK);
520 command &= 0xFFFFFFFC;
521 pci_write_config(dev, PCN_PCI_PWRMGMTCTRL, command, 4);
523 /* Restore PCI config data. */
524 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4);
525 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4);
526 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4);
531 * Map control/status registers.
533 command = pci_read_config(dev, PCIR_COMMAND, 4);
534 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
535 pci_write_config(dev, PCIR_COMMAND, command, 4);
536 command = pci_read_config(dev, PCIR_COMMAND, 4);
538 #ifdef PCN_USEIOSPACE
539 if (!(command & PCIM_CMD_PORTEN)) {
540 printf("pcn%d: failed to enable I/O ports!\n", unit);
545 if (!(command & PCIM_CMD_MEMEN)) {
546 printf("pcn%d: failed to enable memory mapping!\n", unit);
553 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
555 if (sc->pcn_res == NULL) {
556 printf("pcn%d: couldn't map ports/memory\n", unit);
561 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
562 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
564 /* Allocate interrupt */
566 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
567 RF_SHAREABLE | RF_ACTIVE);
569 if (sc->pcn_irq == NULL) {
570 printf("pcn%d: couldn't map interrupt\n", unit);
575 /* Reset the adapter. */
579 * Get station address from the EEPROM.
581 *(uint32_t *)eaddr = CSR_READ_4(sc, PCN_IO32_APROM00);
582 *(uint16_t *)(eaddr + 4) = CSR_READ_2(sc, PCN_IO32_APROM01);
585 callout_init(&sc->pcn_stat_timer);
587 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF,
588 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
590 if (sc->pcn_ldata == NULL) {
591 printf("pcn%d: no memory for list buffers!\n", unit);
595 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data));
597 ifp = &sc->arpcom.ac_if;
599 if_initname(ifp, "pcn", unit);
600 ifp->if_mtu = ETHERMTU;
601 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
602 ifp->if_ioctl = pcn_ioctl;
603 ifp->if_start = pcn_start;
604 ifp->if_watchdog = pcn_watchdog;
605 ifp->if_init = pcn_init;
606 ifp->if_baudrate = 10000000;
607 ifq_set_maxlen(&ifp->if_snd, PCN_TX_LIST_CNT - 1);
608 ifq_set_ready(&ifp->if_snd);
613 if (mii_phy_probe(dev, &sc->pcn_miibus,
614 pcn_ifmedia_upd, pcn_ifmedia_sts)) {
615 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit);
621 * Call MI attach routine.
623 ether_ifattach(ifp, eaddr);
625 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET,
626 pcn_intr, sc, &sc->pcn_intrhand, NULL);
629 device_printf(dev, "couldn't set up irq\n");
638 static int pcn_detach(dev)
641 struct pcn_softc *sc = device_get_softc(dev);
642 struct ifnet *ifp = &sc->arpcom.ac_if;
646 if (device_is_attached(dev)) {
652 if (sc->pcn_miibus != NULL)
653 device_delete_child(dev, sc->pcn_miibus);
654 bus_generic_detach(dev);
656 if (sc->pcn_intrhand)
657 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand);
662 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq);
664 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
667 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data),
675 * Initialize the transmit descriptors.
677 static int pcn_list_tx_init(sc)
678 struct pcn_softc *sc;
680 struct pcn_list_data *ld;
681 struct pcn_ring_data *cd;
687 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
688 cd->pcn_tx_chain[i] = NULL;
689 ld->pcn_tx_list[i].pcn_tbaddr = 0;
690 ld->pcn_tx_list[i].pcn_txctl = 0;
691 ld->pcn_tx_list[i].pcn_txstat = 0;
694 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0;
701 * Initialize the RX descriptors and allocate mbufs for them.
703 static int pcn_list_rx_init(sc)
704 struct pcn_softc *sc;
706 struct pcn_list_data *ld;
707 struct pcn_ring_data *cd;
713 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
714 if (pcn_newbuf(sc, i, NULL) == ENOBUFS)
724 * Initialize an RX descriptor and attach an MBUF cluster.
726 static int pcn_newbuf(sc, idx, m)
727 struct pcn_softc *sc;
731 struct mbuf *m_new = NULL;
732 struct pcn_rx_desc *c;
734 c = &sc->pcn_ldata->pcn_rx_list[idx];
737 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
741 MCLGET(m_new, MB_DONTWAIT);
742 if (!(m_new->m_flags & M_EXT)) {
746 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
749 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
750 m_new->m_data = m_new->m_ext.ext_buf;
753 m_adj(m_new, ETHER_ALIGN);
755 sc->pcn_cdata.pcn_rx_chain[idx] = m_new;
756 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t));
757 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ;
758 c->pcn_bufsz |= PCN_RXLEN_MBO;
759 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN;
765 * A frame has been uploaded: pass the resulting mbuf chain up to
766 * the higher level protocols.
768 static void pcn_rxeof(sc)
769 struct pcn_softc *sc;
773 struct pcn_rx_desc *cur_rx;
776 ifp = &sc->arpcom.ac_if;
777 i = sc->pcn_cdata.pcn_rx_prod;
779 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) {
780 cur_rx = &sc->pcn_ldata->pcn_rx_list[i];
781 m = sc->pcn_cdata.pcn_rx_chain[i];
782 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
785 * If an error occurs, update stats, clear the
786 * status word and leave the mbuf cluster in place:
787 * it should simply get re-used next time this descriptor
788 * comes up in the ring.
790 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) {
792 pcn_newbuf(sc, i, m);
793 PCN_INC(i, PCN_RX_LIST_CNT);
797 if (pcn_newbuf(sc, i, NULL)) {
798 /* Ran out of mbufs; recycle this one. */
799 pcn_newbuf(sc, i, m);
801 PCN_INC(i, PCN_RX_LIST_CNT);
805 PCN_INC(i, PCN_RX_LIST_CNT);
807 /* No errors; receive the packet. */
809 m->m_len = m->m_pkthdr.len =
810 cur_rx->pcn_rxlen - ETHER_CRC_LEN;
811 m->m_pkthdr.rcvif = ifp;
813 (*ifp->if_input)(ifp, m);
816 sc->pcn_cdata.pcn_rx_prod = i;
822 * A frame was downloaded to the chip. It's safe for us to clean up
826 static void pcn_txeof(sc)
827 struct pcn_softc *sc;
829 struct pcn_tx_desc *cur_tx = NULL;
833 ifp = &sc->arpcom.ac_if;
836 * Go through our tx list and free mbufs for those
837 * frames that have been transmitted.
839 idx = sc->pcn_cdata.pcn_tx_cons;
840 while (idx != sc->pcn_cdata.pcn_tx_prod) {
841 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx];
843 if (!PCN_OWN_TXDESC(cur_tx))
846 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) {
847 sc->pcn_cdata.pcn_tx_cnt--;
848 PCN_INC(idx, PCN_TX_LIST_CNT);
852 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) {
854 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF)
855 ifp->if_collisions++;
856 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY)
857 ifp->if_collisions++;
860 ifp->if_collisions +=
861 cur_tx->pcn_txstat & PCN_TXSTAT_TRC;
864 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) {
865 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]);
866 sc->pcn_cdata.pcn_tx_chain[idx] = NULL;
869 sc->pcn_cdata.pcn_tx_cnt--;
870 PCN_INC(idx, PCN_TX_LIST_CNT);
873 if (idx != sc->pcn_cdata.pcn_tx_cons) {
874 /* Some buffers have been freed. */
875 sc->pcn_cdata.pcn_tx_cons = idx;
876 ifp->if_flags &= ~IFF_OACTIVE;
878 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5;
883 static void pcn_tick(xsc)
886 struct pcn_softc *sc = xsc;
887 struct mii_data *mii;
888 struct ifnet *ifp = &sc->arpcom.ac_if;
892 mii = device_get_softc(sc->pcn_miibus);
895 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE))
900 if (mii->mii_media_status & IFM_ACTIVE &&
901 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
903 if (!ifq_is_empty(&ifp->if_snd))
907 callout_reset(&sc->pcn_stat_timer, hz, pcn_tick, sc);
912 static void pcn_intr(arg)
915 struct pcn_softc *sc;
920 ifp = &sc->arpcom.ac_if;
922 /* Supress unwanted interrupts */
923 if (!(ifp->if_flags & IFF_UP)) {
928 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR);
930 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) {
931 CSR_WRITE_4(sc, PCN_IO32_RDP, status);
933 if (status & PCN_CSR_RINT)
936 if (status & PCN_CSR_TINT)
939 if (status & PCN_CSR_ERR) {
945 if (!ifq_is_empty(&ifp->if_snd))
952 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
953 * pointers to the fragment pointers.
955 static int pcn_encap(sc, m_head, txidx)
956 struct pcn_softc *sc;
960 struct pcn_tx_desc *f = NULL;
962 int frag, cur, cnt = 0;
965 * Start packing the mbufs in this chain into
966 * the fragment pointers. Stop when we run out
967 * of fragments or hit the end of the mbuf chain.
972 for (m = m_head; m != NULL; m = m->m_next) {
974 if ((PCN_TX_LIST_CNT -
975 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2)
977 f = &sc->pcn_ldata->pcn_tx_list[frag];
978 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ;
979 f->pcn_txctl |= PCN_TXCTL_MBO;
980 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t));
982 f->pcn_txctl |= PCN_TXCTL_STP;
984 f->pcn_txctl |= PCN_TXCTL_OWN;
986 PCN_INC(frag, PCN_TX_LIST_CNT);
994 sc->pcn_cdata.pcn_tx_chain[cur] = m_head;
995 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |=
996 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT;
997 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN;
998 sc->pcn_cdata.pcn_tx_cnt += cnt;
1005 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1006 * to the mbuf data regions directly in the transmit lists. We also save a
1007 * copy of the pointers since the transmit list fragment pointers are
1008 * physical addresses.
1010 static void pcn_start(ifp)
1013 struct pcn_softc *sc;
1014 struct mbuf *m_head = NULL;
1022 idx = sc->pcn_cdata.pcn_tx_prod;
1024 if (ifp->if_flags & IFF_OACTIVE)
1027 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) {
1028 m_head = ifq_poll(&ifp->if_snd);
1032 if (pcn_encap(sc, m_head, &idx)) {
1033 ifp->if_flags |= IFF_OACTIVE;
1036 m_head = ifq_dequeue(&ifp->if_snd);
1038 BPF_MTAP(ifp, m_head);
1042 sc->pcn_cdata.pcn_tx_prod = idx;
1043 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN);
1046 * Set a timeout in case the chip goes out to lunch.
1053 void pcn_setfilt(ifp)
1056 struct pcn_softc *sc;
1060 /* If we want promiscuous mode, set the allframes bit. */
1061 if (ifp->if_flags & IFF_PROMISC) {
1062 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1064 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1067 /* Set the capture broadcast bit to capture broadcast frames. */
1068 if (ifp->if_flags & IFF_BROADCAST) {
1069 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1071 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1077 static void pcn_init(xsc)
1080 struct pcn_softc *sc = xsc;
1081 struct ifnet *ifp = &sc->arpcom.ac_if;
1082 struct mii_data *mii = NULL;
1087 * Cancel pending I/O and free all RX/TX buffers.
1092 mii = device_get_softc(sc->pcn_miibus);
1094 /* Set MAC address */
1095 pcn_csr_write(sc, PCN_CSR_PAR0,
1096 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
1097 pcn_csr_write(sc, PCN_CSR_PAR1,
1098 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
1099 pcn_csr_write(sc, PCN_CSR_PAR2,
1100 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
1102 /* Init circular RX list. */
1103 if (pcn_list_rx_init(sc) == ENOBUFS) {
1104 printf("pcn%d: initialization failed: no "
1105 "memory for rx buffers\n", sc->pcn_unit);
1112 /* Set up RX filter. */
1116 * Init tx descriptors.
1118 pcn_list_tx_init(sc);
1120 /* Set up the mode register. */
1121 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII);
1124 * Load the multicast filter.
1129 * Load the addresses of the RX and TX lists.
1131 pcn_csr_write(sc, PCN_CSR_RXADDR0,
1132 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF);
1133 pcn_csr_write(sc, PCN_CSR_RXADDR1,
1134 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF);
1135 pcn_csr_write(sc, PCN_CSR_TXADDR0,
1136 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF);
1137 pcn_csr_write(sc, PCN_CSR_TXADDR1,
1138 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF);
1140 /* Set the RX and TX ring sizes. */
1141 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1);
1142 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1);
1144 /* We're not using the initialization block. */
1145 pcn_csr_write(sc, PCN_CSR_IAB1, 0);
1147 /* Enable fast suspend mode. */
1148 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE);
1151 * Enable burst read and write. Also set the no underflow
1152 * bit. This will avoid transmit underruns in certain
1153 * conditions while still providing decent performance.
1155 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW|
1156 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE);
1158 /* Enable graceful recovery from underflow. */
1159 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO);
1161 /* Enable auto-padding of short TX frames. */
1162 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX);
1164 /* Disable MII autoneg (we handle this ourselves). */
1165 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS);
1167 if (sc->pcn_type == Am79C978)
1168 pcn_bcr_write(sc, PCN_BCR_PHYSEL,
1169 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA);
1171 /* Enable interrupts and start the controller running. */
1172 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START);
1176 ifp->if_flags |= IFF_RUNNING;
1177 ifp->if_flags &= ~IFF_OACTIVE;
1179 callout_reset(&sc->pcn_stat_timer, hz, pcn_tick, sc);
1185 * Set media options.
1187 static int pcn_ifmedia_upd(ifp)
1190 struct pcn_softc *sc;
1191 struct mii_data *mii;
1194 mii = device_get_softc(sc->pcn_miibus);
1197 if (mii->mii_instance) {
1198 struct mii_softc *miisc;
1199 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1200 miisc = LIST_NEXT(miisc, mii_list))
1201 mii_phy_reset(miisc);
1209 * Report current media status.
1211 static void pcn_ifmedia_sts(ifp, ifmr)
1213 struct ifmediareq *ifmr;
1215 struct pcn_softc *sc;
1216 struct mii_data *mii;
1220 mii = device_get_softc(sc->pcn_miibus);
1222 ifmr->ifm_active = mii->mii_media_active;
1223 ifmr->ifm_status = mii->mii_media_status;
1228 static int pcn_ioctl(ifp, command, data, cr)
1234 struct pcn_softc *sc = ifp->if_softc;
1235 struct ifreq *ifr = (struct ifreq *) data;
1236 struct mii_data *mii = NULL;
1243 if (ifp->if_flags & IFF_UP) {
1244 if (ifp->if_flags & IFF_RUNNING &&
1245 ifp->if_flags & IFF_PROMISC &&
1246 !(sc->pcn_if_flags & IFF_PROMISC)) {
1247 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1250 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1252 pcn_csr_write(sc, PCN_CSR_CSR,
1253 PCN_CSR_INTEN|PCN_CSR_START);
1254 } else if (ifp->if_flags & IFF_RUNNING &&
1255 !(ifp->if_flags & IFF_PROMISC) &&
1256 sc->pcn_if_flags & IFF_PROMISC) {
1257 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1260 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1262 pcn_csr_write(sc, PCN_CSR_CSR,
1263 PCN_CSR_INTEN|PCN_CSR_START);
1264 } else if (!(ifp->if_flags & IFF_RUNNING))
1267 if (ifp->if_flags & IFF_RUNNING)
1270 sc->pcn_if_flags = ifp->if_flags;
1280 mii = device_get_softc(sc->pcn_miibus);
1281 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1284 error = ether_ioctl(ifp, command, data);
1293 static void pcn_watchdog(ifp)
1296 struct pcn_softc *sc;
1301 printf("pcn%d: watchdog timeout\n", sc->pcn_unit);
1307 if (!ifq_is_empty(&ifp->if_snd))
1314 * Stop the adapter and free any mbufs allocated to the
1317 static void pcn_stop(sc)
1318 struct pcn_softc *sc;
1323 ifp = &sc->arpcom.ac_if;
1326 callout_stop(&sc->pcn_stat_timer);
1327 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP);
1331 * Free data in the RX lists.
1333 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
1334 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) {
1335 m_freem(sc->pcn_cdata.pcn_rx_chain[i]);
1336 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
1339 bzero((char *)&sc->pcn_ldata->pcn_rx_list,
1340 sizeof(sc->pcn_ldata->pcn_rx_list));
1343 * Free the TX list buffers.
1345 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
1346 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) {
1347 m_freem(sc->pcn_cdata.pcn_tx_chain[i]);
1348 sc->pcn_cdata.pcn_tx_chain[i] = NULL;
1352 bzero((char *)&sc->pcn_ldata->pcn_tx_list,
1353 sizeof(sc->pcn_ldata->pcn_tx_list));
1355 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1361 * Stop all chip I/O so that the kernel's probe routines don't
1362 * get confused by errant DMAs when rebooting.
1364 static void pcn_shutdown(dev)
1367 struct pcn_softc *sc;
1369 sc = device_get_softc(dev);