3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.14 2005/06/09 20:04:44 joerg Exp $
40 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver
42 * Written by Bill Paul <wpaul@windriver.com>
43 * Senior Networking Software Engineer
48 * This driver is designed to support RealTek's next generation of
49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
50 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S
53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
54 * with the older 8139 family, however it also supports a special
55 * C+ mode of operation that provides several new performance enhancing
56 * features. These include:
58 * o Descriptor based DMA mechanism. Each descriptor represents
59 * a single packet fragment. Data buffers may be aligned on
64 * o TCP/IP checksum offload for both RX and TX
66 * o High and normal priority transmit DMA rings
68 * o VLAN tag insertion and extraction
70 * o TCP large send (segmentation offload)
72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
73 * programming API is fairly straightforward. The RX filtering, EEPROM
74 * access and PHY access is the same as it is on the older 8139 series
77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
78 * same programming API and feature set as the 8139C+ with the following
79 * differences and additions:
85 * o GMII and TBI ports/registers for interfacing with copper
88 * o RX and TX DMA rings can have up to 1024 descriptors
89 * (the 8139C+ allows a maximum of 64)
91 * o Slight differences in register layout from the 8139C+
93 * The TX start and timer interrupt registers are at different locations
94 * on the 8169 than they are on the 8139C+. Also, the status word in the
95 * RX descriptor has a slightly different bit layout. The 8169 does not
96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
100 * (the 'S' stands for 'single-chip'). These devices have the same
101 * programming API as the older 8169, but also have some vendor-specific
102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
105 * This driver takes advantage of the RX and TX checksum offload and
106 * VLAN tag insertion/extraction features. It also implements TX
107 * interrupt moderation using the timer interrupt registers, which
108 * significantly reduces TX interrupt load. There is also support
109 * for jumbo frames, however the 8169/8169S/8110S can not transmit
110 * jumbo frames larger than 7.5K, so the max MTU possible with this
111 * driver is 7500 bytes.
114 #include <sys/param.h>
115 #include <sys/endian.h>
116 #include <sys/systm.h>
117 #include <sys/sockio.h>
118 #include <sys/mbuf.h>
119 #include <sys/malloc.h>
120 #include <sys/module.h>
121 #include <sys/kernel.h>
122 #include <sys/socket.h>
123 #include <sys/thread2.h>
126 #include <net/ifq_var.h>
127 #include <net/if_arp.h>
128 #include <net/ethernet.h>
129 #include <net/if_dl.h>
130 #include <net/if_media.h>
131 #include <net/if_types.h>
132 #include <net/vlan/if_vlan_var.h>
136 #include <machine/bus_pio.h>
137 #include <machine/bus_memio.h>
138 #include <machine/bus.h>
139 #include <machine/resource.h>
141 #include <sys/rman.h>
143 #include <dev/netif/mii_layer/mii.h>
144 #include <dev/netif/mii_layer/miivar.h>
146 #include <bus/pci/pcireg.h>
147 #include <bus/pci/pcivar.h>
149 /* "controller miibus0" required. See GENERIC if you get errors here. */
150 #include "miibus_if.h"
152 #include <dev/netif/re/if_rereg.h>
155 * The hardware supports checksumming but, as usual, some chipsets screw it
156 * all up and produce bogus packets, so we disable it by default.
158 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
159 #define RE_DISABLE_HWCSUM
162 * Various supported device vendors/types and their names.
164 static struct re_type re_devs[] = {
165 { RT_VENDORID, RT_DEVICEID_8139, RE_HWREV_8139CPLUS,
166 "RealTek 8139C+ 10/100BaseTX" },
167 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8169,
168 "RealTek 8169 Gigabit Ethernet" },
169 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8169S,
170 "RealTek 8169S Single-chip Gigabit Ethernet" },
171 { RT_VENDORID, RT_DEVICEID_8169, RE_HWREV_8110S,
172 "RealTek 8110S Single-chip Gigabit Ethernet" },
176 static struct re_hwrev re_hwrevs[] = {
177 { RE_HWREV_8139CPLUS, RE_8139CPLUS, "C+"},
178 { RE_HWREV_8169, RE_8169, "8169"},
179 { RE_HWREV_8169S, RE_8169, "8169S"},
180 { RE_HWREV_8110S, RE_8169, "8110S"},
184 static int re_probe(device_t);
185 static int re_attach(device_t);
186 static int re_detach(device_t);
188 static int re_encap(struct re_softc *, struct mbuf **, int *, int *);
190 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int);
191 static void re_dma_map_desc(void *, bus_dma_segment_t *, int,
193 static int re_allocmem(device_t, struct re_softc *);
194 static int re_newbuf(struct re_softc *, int, struct mbuf *);
195 static int re_rx_list_init(struct re_softc *);
196 static int re_tx_list_init(struct re_softc *);
197 static void re_rxeof(struct re_softc *);
198 static void re_txeof(struct re_softc *);
199 static void re_intr(void *);
200 static void re_tick(void *);
201 static void re_start(struct ifnet *);
202 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
203 static void re_init(void *);
204 static void re_stop(struct re_softc *);
205 static void re_watchdog(struct ifnet *);
206 static int re_suspend(device_t);
207 static int re_resume(device_t);
208 static void re_shutdown(device_t);
209 static int re_ifmedia_upd(struct ifnet *);
210 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
212 static void re_eeprom_putbyte(struct re_softc *, int);
213 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *);
214 static void re_read_eeprom(struct re_softc *, caddr_t, int, int, int);
215 static int re_gmii_readreg(device_t, int, int);
216 static int re_gmii_writereg(device_t, int, int, int);
218 static int re_miibus_readreg(device_t, int, int);
219 static int re_miibus_writereg(device_t, int, int, int);
220 static void re_miibus_statchg(device_t);
222 static void re_setmulti(struct re_softc *);
223 static void re_reset(struct re_softc *);
225 static int re_diag(struct re_softc *);
226 #ifdef DEVICE_POLLING
227 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
230 static device_method_t re_methods[] = {
231 /* Device interface */
232 DEVMETHOD(device_probe, re_probe),
233 DEVMETHOD(device_attach, re_attach),
234 DEVMETHOD(device_detach, re_detach),
235 DEVMETHOD(device_suspend, re_suspend),
236 DEVMETHOD(device_resume, re_resume),
237 DEVMETHOD(device_shutdown, re_shutdown),
240 DEVMETHOD(bus_print_child, bus_generic_print_child),
241 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
244 DEVMETHOD(miibus_readreg, re_miibus_readreg),
245 DEVMETHOD(miibus_writereg, re_miibus_writereg),
246 DEVMETHOD(miibus_statchg, re_miibus_statchg),
251 static driver_t re_driver = {
254 sizeof(struct re_softc)
257 static devclass_t re_devclass;
259 DECLARE_DUMMY_MODULE(if_re);
260 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0);
261 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0);
262 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
265 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
268 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
271 * Send a read command and address to the EEPROM, check for ACK.
274 re_eeprom_putbyte(struct re_softc *sc, int addr)
278 d = addr | sc->re_eecmd_read;
281 * Feed in each bit and strobe the clock.
283 for (i = 0x400; i != 0; i >>= 1) {
285 EE_SET(RE_EE_DATAIN);
287 EE_CLR(RE_EE_DATAIN);
297 * Read a word of data stored in the EEPROM at address 'addr.'
300 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest)
305 /* Enter EEPROM access mode. */
306 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_PROGRAM|RE_EE_SEL);
309 * Send address of word we want to read.
311 re_eeprom_putbyte(sc, addr);
313 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_PROGRAM|RE_EE_SEL);
316 * Start reading bits from EEPROM.
318 for (i = 0x8000; i != 0; i >>= 1) {
321 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT)
327 /* Turn off EEPROM access mode. */
328 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
334 * Read a sequence of words from the EEPROM.
337 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt, int swap)
340 uint16_t word = 0, *ptr;
342 for (i = 0; i < cnt; i++) {
343 re_eeprom_getword(sc, off + i, &word);
344 ptr = (u_int16_t *)(dest + (i * 2));
346 *ptr = be16toh(word);
353 re_gmii_readreg(device_t dev, int phy, int reg)
355 struct re_softc *sc = device_get_softc(dev);
362 /* Let the rgephy driver read the GMEDIASTAT register */
364 if (reg == RE_GMEDIASTAT)
365 return(CSR_READ_1(sc, RE_GMEDIASTAT));
367 CSR_WRITE_4(sc, RE_PHYAR, reg << 16);
370 for (i = 0; i < RE_TIMEOUT; i++) {
371 rval = CSR_READ_4(sc, RE_PHYAR);
372 if (rval & RE_PHYAR_BUSY)
377 if (i == RE_TIMEOUT) {
378 device_printf(dev, "PHY read failed\n");
382 return(rval & RE_PHYAR_PHYDATA);
386 re_gmii_writereg(device_t dev, int phy, int reg, int data)
388 struct re_softc *sc = device_get_softc(dev);
392 CSR_WRITE_4(sc, RE_PHYAR,
393 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY);
396 for (i = 0; i < RE_TIMEOUT; i++) {
397 rval = CSR_READ_4(sc, RE_PHYAR);
398 if ((rval & RE_PHYAR_BUSY) == 0)
404 device_printf(dev, "PHY write failed\n");
410 re_miibus_readreg(device_t dev, int phy, int reg)
412 struct re_softc *sc = device_get_softc(dev);
414 uint16_t re8139_reg = 0;
416 if (sc->re_type == RE_8169) {
417 rval = re_gmii_readreg(dev, phy, reg);
421 /* Pretend the internal PHY is only at address 0 */
427 re8139_reg = RE_BMCR;
430 re8139_reg = RE_BMSR;
433 re8139_reg = RE_ANAR;
436 re8139_reg = RE_ANER;
439 re8139_reg = RE_LPAR;
445 * Allow the rlphy driver to read the media status
446 * register. If we have a link partner which does not
447 * support NWAY, this is the register which will tell
448 * us the results of parallel detection.
451 return(CSR_READ_1(sc, RE_MEDIASTAT));
453 device_printf(dev, "bad phy register\n");
456 rval = CSR_READ_2(sc, re8139_reg);
461 re_miibus_writereg(device_t dev, int phy, int reg, int data)
463 struct re_softc *sc= device_get_softc(dev);
464 u_int16_t re8139_reg = 0;
466 if (sc->re_type == RE_8169)
467 return(re_gmii_writereg(dev, phy, reg, data));
469 /* Pretend the internal PHY is only at address 0 */
475 re8139_reg = RE_BMCR;
478 re8139_reg = RE_BMSR;
481 re8139_reg = RE_ANAR;
484 re8139_reg = RE_ANER;
487 re8139_reg = RE_LPAR;
493 device_printf(dev, "bad phy register\n");
496 CSR_WRITE_2(sc, re8139_reg, data);
501 re_miibus_statchg(device_t dev)
506 * Program the 64-bit multicast hash filter.
509 re_setmulti(struct re_softc *sc)
511 struct ifnet *ifp = &sc->arpcom.ac_if;
513 uint32_t hashes[2] = { 0, 0 };
514 struct ifmultiaddr *ifma;
518 rxfilt = CSR_READ_4(sc, RE_RXCFG);
520 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
521 rxfilt |= RE_RXCFG_RX_MULTI;
522 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
523 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF);
524 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF);
528 /* first, zot all the existing hash bits */
529 CSR_WRITE_4(sc, RE_MAR0, 0);
530 CSR_WRITE_4(sc, RE_MAR4, 0);
532 /* now program new ones */
533 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
534 if (ifma->ifma_addr->sa_family != AF_LINK)
536 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
537 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
539 hashes[0] |= (1 << h);
541 hashes[1] |= (1 << (h - 32));
546 rxfilt |= RE_RXCFG_RX_MULTI;
548 rxfilt &= ~RE_RXCFG_RX_MULTI;
550 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
551 CSR_WRITE_4(sc, RE_MAR0, hashes[0]);
552 CSR_WRITE_4(sc, RE_MAR4, hashes[1]);
556 re_reset(struct re_softc *sc)
560 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET);
562 for (i = 0; i < RE_TIMEOUT; i++) {
564 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0)
568 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
570 CSR_WRITE_1(sc, 0x82, 1);
574 * The following routine is designed to test for a defect on some
575 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
576 * lines connected to the bus, however for a 32-bit only card, they
577 * should be pulled high. The result of this defect is that the
578 * NIC will not work right if you plug it into a 64-bit slot: DMA
579 * operations will be done with 64-bit transfers, which will fail
580 * because the 64-bit data lines aren't connected.
582 * There's no way to work around this (short of talking a soldering
583 * iron to the board), however we can detect it. The method we use
584 * here is to put the NIC into digital loopback mode, set the receiver
585 * to promiscuous mode, and then try to send a frame. We then compare
586 * the frame data we sent to what was received. If the data matches,
587 * then the NIC is working correctly, otherwise we know the user has
588 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
589 * slot. In the latter case, there's no way the NIC can work correctly,
590 * so we print out a message on the console and abort the device attach.
594 re_diag(struct re_softc *sc)
596 struct ifnet *ifp = &sc->arpcom.ac_if;
598 struct ether_header *eh;
599 struct re_desc *cur_rx;
602 int total_len, i, error = 0;
603 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
604 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
606 /* Allocate a single mbuf */
608 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
613 * Initialize the NIC in test mode. This sets the chip up
614 * so that it can send and receive frames, but performs the
615 * following special functions:
616 * - Puts receiver in promiscuous mode
617 * - Enables digital loopback mode
618 * - Leaves interrupts turned off
621 ifp->if_flags |= IFF_PROMISC;
628 /* Put some data in the mbuf */
630 eh = mtod(m0, struct ether_header *);
631 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN);
632 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN);
633 eh->ether_type = htons(ETHERTYPE_IP);
634 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
637 * Queue the packet, start transmission.
638 * Note: ifq_handoff() ultimately calls re_start() for us.
641 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
642 error = ifq_handoff(ifp, m0, NULL);
649 /* Wait for it to propagate through the chip */
652 for (i = 0; i < RE_TIMEOUT; i++) {
653 status = CSR_READ_2(sc, RE_ISR);
654 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) ==
655 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK))
660 if (i == RE_TIMEOUT) {
661 if_printf(ifp, "diagnostic failed to receive packet "
662 "in loopback mode\n");
668 * The packet should have been dumped into the first
669 * entry in the RX DMA ring. Grab it from there.
672 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
673 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
674 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0],
675 BUS_DMASYNC_POSTWRITE);
676 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]);
678 m0 = sc->re_ldata.re_rx_mbuf[0];
679 sc->re_ldata.re_rx_mbuf[0] = NULL;
680 eh = mtod(m0, struct ether_header *);
682 cur_rx = &sc->re_ldata.re_rx_list[0];
683 total_len = RE_RXBYTES(cur_rx);
684 rxstat = le32toh(cur_rx->re_cmdstat);
686 if (total_len != ETHER_MIN_LEN) {
687 if_printf(ifp, "diagnostic failed, received short packet\n");
692 /* Test that the received packet data matches what we sent. */
694 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) ||
695 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) ||
696 be16toh(eh->ether_type) != ETHERTYPE_IP) {
697 if_printf(ifp, "WARNING, DMA FAILURE!\n");
698 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
699 dst, ":", src, ":", ETHERTYPE_IP);
700 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
701 eh->ether_dhost, ":", eh->ether_shost, ":",
702 ntohs(eh->ether_type));
703 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
704 "into a 64-bit PCI slot.\n");
705 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
706 "for proper operation.\n");
707 if_printf(ifp, "Read the re(4) man page for more details.\n");
712 /* Turn interface off, release resources */
715 ifp->if_flags &= ~IFF_PROMISC;
724 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
725 * IDs against our list and return a device name if we find a match.
728 re_probe(device_t dev)
734 uint16_t vendor, product;
738 vendor = pci_get_vendor(dev);
739 product = pci_get_device(dev);
741 for (t = re_devs; t->re_name != NULL; t++) {
742 if (product == t->re_did && vendor == t->re_vid)
747 * Check if we found a RealTek device.
749 if (t->re_name == NULL)
753 * Temporarily map the I/O space so we can read the chip ID register.
755 sc = malloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO);
757 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
759 if (sc->re_res == NULL) {
760 device_printf(dev, "couldn't map ports/memory\n");
765 sc->re_btag = rman_get_bustag(sc->re_res);
766 sc->re_bhandle = rman_get_bushandle(sc->re_res);
768 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
769 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res);
773 * and continue matching for the specific chip...
775 for (; t->re_name != NULL; t++) {
776 if (product == t->re_did && vendor == t->re_vid &&
777 t->re_basetype == hwrev) {
778 device_set_desc(dev, t->re_name);
786 * This routine takes the segment list provided as the result of
787 * a bus_dma_map_load() operation and assigns the addresses/lengths
788 * to RealTek DMA descriptors. This can be called either by the RX
789 * code or the TX code. In the RX case, we'll probably wind up mapping
790 * at most one segment. For the TX case, there could be any number of
791 * segments since TX packets may span multiple mbufs. In either case,
792 * if the number of segments is larger than the re_maxsegs limit
793 * specified by the caller, we abort the mapping operation. Sadly,
794 * whoever designed the buffer mapping API did not provide a way to
795 * return an error from here, so we have to fake it a bit.
799 re_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg,
800 bus_size_t mapsize, int error)
802 struct re_dmaload_arg *ctx;
803 struct re_desc *d = NULL;
812 /* Signal error to caller if there's too many segments */
813 if (nseg > ctx->re_maxsegs) {
819 * Map the segment array into descriptors. Note that we set the
820 * start-of-frame and end-of-frame markers for either TX or RX, but
821 * they really only have meaning in the TX case. (In the RX case,
822 * it's the chip that tells us where packets begin and end.)
823 * We also keep track of the end of the ring and set the
824 * end-of-ring bits as needed, and we set the ownership bits
825 * in all except the very first descriptor. (The caller will
826 * set this descriptor later when it start transmission or
831 d = &ctx->re_ring[idx];
832 if (le32toh(d->re_cmdstat) & RE_RDESC_STAT_OWN) {
836 cmdstat = segs[i].ds_len;
837 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
838 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
840 cmdstat |= RE_TDESC_CMD_SOF;
842 cmdstat |= RE_TDESC_CMD_OWN;
843 if (idx == (RE_RX_DESC_CNT - 1))
844 cmdstat |= RE_TDESC_CMD_EOR;
845 d->re_cmdstat = htole32(cmdstat | ctx->re_flags);
852 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
853 ctx->re_maxsegs = nseg;
858 * Map a single buffer address.
862 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
869 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
871 *addr = segs->ds_addr;
875 re_allocmem(device_t dev, struct re_softc *sc)
880 * Allocate map for RX mbufs.
883 error = bus_dma_tag_create(sc->re_parent_tag, ETHER_ALIGN, 0,
884 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
885 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
886 &sc->re_ldata.re_mtag);
888 device_printf(dev, "could not allocate dma tag\n");
893 * Allocate map for TX descriptor list.
895 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
896 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
897 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
898 &sc->re_ldata.re_tx_list_tag);
900 device_printf(dev, "could not allocate dma tag\n");
904 /* Allocate DMA'able memory for the TX ring */
906 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag,
907 (void **)&sc->re_ldata.re_tx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
908 &sc->re_ldata.re_tx_list_map);
910 device_printf(dev, "could not allocate TX ring\n");
914 /* Load the map for the TX ring. */
916 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag,
917 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list,
918 RE_TX_LIST_SZ, re_dma_map_addr,
919 &sc->re_ldata.re_tx_list_addr, BUS_DMA_NOWAIT);
921 device_printf(dev, "could not get addres of TX ring\n");
925 /* Create DMA maps for TX buffers */
927 for (i = 0; i < RE_TX_DESC_CNT; i++) {
928 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
929 &sc->re_ldata.re_tx_dmamap[i]);
931 device_printf(dev, "can't create DMA map for TX\n");
937 * Allocate map for RX descriptor list.
939 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
940 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
941 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
942 &sc->re_ldata.re_rx_list_tag);
944 device_printf(dev, "could not allocate dma tag\n");
948 /* Allocate DMA'able memory for the RX ring */
950 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag,
951 (void **)&sc->re_ldata.re_rx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
952 &sc->re_ldata.re_rx_list_map);
954 device_printf(dev, "could not allocate RX ring\n");
958 /* Load the map for the RX ring. */
960 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag,
961 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list,
962 RE_TX_LIST_SZ, re_dma_map_addr,
963 &sc->re_ldata.re_rx_list_addr, BUS_DMA_NOWAIT);
965 device_printf(dev, "could not get address of RX ring\n");
969 /* Create DMA maps for RX buffers */
971 for (i = 0; i < RE_RX_DESC_CNT; i++) {
972 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
973 &sc->re_ldata.re_rx_dmamap[i]);
975 device_printf(dev, "can't create DMA map for RX\n");
984 * Attach the interface. Allocate softc structures, do ifmedia
985 * setup and ethernet/BPF attach.
988 re_attach(device_t dev)
990 struct re_softc *sc = device_get_softc(dev);
992 struct re_hwrev *hw_rev;
993 uint8_t eaddr[ETHER_ADDR_LEN];
995 u_int16_t re_did = 0;
996 int error = 0, rid, i;
998 callout_init(&sc->re_timer);
1000 #ifndef BURN_BRIDGES
1002 * Handle power management nonsense.
1005 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1006 uint32_t membase, irq;
1008 /* Save important PCI config data. */
1009 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
1010 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1012 /* Reset the power state. */
1013 device_printf(dev, "chip is is in D%d power mode "
1014 "-- setting to D0\n", pci_get_powerstate(dev));
1016 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1018 /* Restore PCI config data. */
1019 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
1020 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1024 * Map control/status registers.
1026 pci_enable_busmaster(dev);
1029 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1032 if (sc->re_res == NULL) {
1033 device_printf(dev, "couldn't map ports/memory\n");
1038 sc->re_btag = rman_get_bustag(sc->re_res);
1039 sc->re_bhandle = rman_get_bushandle(sc->re_res);
1041 /* Allocate interrupt */
1043 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1044 RF_SHAREABLE | RF_ACTIVE);
1046 if (sc->re_irq == NULL) {
1047 device_printf(dev, "couldn't map interrupt\n");
1052 /* Reset the adapter. */
1055 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
1056 for (hw_rev = re_hwrevs; hw_rev->re_desc != NULL; hw_rev++) {
1057 if (hw_rev->re_rev == hwrev) {
1058 sc->re_type = hw_rev->re_type;
1063 if (sc->re_type == RE_8169) {
1064 /* Set RX length mask */
1065 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
1067 /* Force station address autoload from the EEPROM */
1068 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_AUTOLOAD);
1069 for (i = 0; i < RE_TIMEOUT; i++) {
1070 if ((CSR_READ_1(sc, RE_EECMD) & RE_EEMODE_AUTOLOAD) == 0)
1074 if (i == RE_TIMEOUT)
1075 device_printf(dev, "eeprom autoload timed out\n");
1077 for (i = 0; i < ETHER_ADDR_LEN; i++)
1078 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i);
1082 /* Set RX length mask */
1083 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
1085 sc->re_eecmd_read = RE_EECMD_READ_6BIT;
1086 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0);
1087 if (re_did != 0x8129)
1088 sc->re_eecmd_read = RE_EECMD_READ_8BIT;
1091 * Get station address from the EEPROM.
1093 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3, 0);
1094 for (i = 0; i < 3; i++) {
1095 eaddr[(i * 2) + 0] = as[i] & 0xff;
1096 eaddr[(i * 2) + 1] = as[i] >> 8;
1101 * Allocate the parent bus DMA tag appropriate for PCI.
1103 #define RE_NSEG_NEW 32
1104 error = bus_dma_tag_create(NULL, /* parent */
1105 1, 0, /* alignment, boundary */
1106 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1107 BUS_SPACE_MAXADDR, /* highaddr */
1108 NULL, NULL, /* filter, filterarg */
1109 MAXBSIZE, RE_NSEG_NEW, /* maxsize, nsegments */
1110 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1111 BUS_DMA_ALLOCNOW, /* flags */
1112 &sc->re_parent_tag);
1116 error = re_allocmem(dev, sc);
1122 if (mii_phy_probe(dev, &sc->re_miibus,
1123 re_ifmedia_upd, re_ifmedia_sts)) {
1124 device_printf(dev, "MII without any phy!\n");
1129 ifp = &sc->arpcom.ac_if;
1131 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1132 ifp->if_mtu = ETHERMTU;
1133 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1134 ifp->if_ioctl = re_ioctl;
1135 ifp->if_capabilities = IFCAP_VLAN_MTU;
1136 ifp->if_start = re_start;
1137 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1138 #ifdef DEVICE_POLLING
1139 ifp->if_poll = re_poll;
1141 ifp->if_watchdog = re_watchdog;
1142 ifp->if_init = re_init;
1143 if (sc->re_type == RE_8169)
1144 ifp->if_baudrate = 1000000000;
1146 ifp->if_baudrate = 100000000;
1147 ifq_set_maxlen(&ifp->if_snd, RE_IFQ_MAXLEN);
1148 ifq_set_ready(&ifp->if_snd);
1149 #ifdef RE_DISABLE_HWCSUM
1150 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1151 ifp->if_hwassist = 0;
1153 ifp->if_capenable = ifp->if_capabilities;
1154 ifp->if_hwassist = RE_CSUM_FEATURES;
1158 * Call MI attach routine.
1160 ether_ifattach(ifp, eaddr);
1162 /* Perform hardware diagnostic. */
1163 error = re_diag(sc);
1166 device_printf(dev, "hardware diagnostic failure\n");
1167 ether_ifdetach(ifp);
1171 /* Hook interrupt last to avoid having to lock softc */
1172 error = bus_setup_intr(dev, sc->re_irq, INTR_TYPE_NET, re_intr, sc,
1173 &sc->re_intrhand, NULL);
1176 device_printf(dev, "couldn't set up irq\n");
1177 ether_ifdetach(ifp);
1189 * Shutdown hardware and free up resources. This can be called any
1190 * time after the mutex has been initialized. It is called in both
1191 * the error case in attach and the normal detach case so it needs
1192 * to be careful about only freeing resources that have actually been
1196 re_detach(device_t dev)
1198 struct re_softc *sc = device_get_softc(dev);
1199 struct ifnet *ifp = &sc->arpcom.ac_if;
1204 /* These should only be active if attach succeeded */
1205 if (device_is_attached(dev)) {
1207 ether_ifdetach(ifp);
1210 device_delete_child(dev, sc->re_miibus);
1211 bus_generic_detach(dev);
1213 if (sc->re_intrhand)
1214 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
1219 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq);
1221 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO,
1224 /* Unload and free the RX DMA ring memory and map */
1226 if (sc->re_ldata.re_rx_list_tag) {
1227 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
1228 sc->re_ldata.re_rx_list_map);
1229 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1230 sc->re_ldata.re_rx_list,
1231 sc->re_ldata.re_rx_list_map);
1232 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1235 /* Unload and free the TX DMA ring memory and map */
1237 if (sc->re_ldata.re_tx_list_tag) {
1238 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
1239 sc->re_ldata.re_tx_list_map);
1240 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1241 sc->re_ldata.re_tx_list,
1242 sc->re_ldata.re_tx_list_map);
1243 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1246 /* Destroy all the RX and TX buffer maps */
1248 if (sc->re_ldata.re_mtag) {
1249 for (i = 0; i < RE_TX_DESC_CNT; i++)
1250 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1251 sc->re_ldata.re_tx_dmamap[i]);
1252 for (i = 0; i < RE_RX_DESC_CNT; i++)
1253 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1254 sc->re_ldata.re_rx_dmamap[i]);
1255 bus_dma_tag_destroy(sc->re_ldata.re_mtag);
1258 /* Unload and free the stats buffer and map */
1260 if (sc->re_ldata.re_stag) {
1261 bus_dmamap_unload(sc->re_ldata.re_stag,
1262 sc->re_ldata.re_rx_list_map);
1263 bus_dmamem_free(sc->re_ldata.re_stag,
1264 sc->re_ldata.re_stats,
1265 sc->re_ldata.re_smap);
1266 bus_dma_tag_destroy(sc->re_ldata.re_stag);
1269 if (sc->re_parent_tag)
1270 bus_dma_tag_destroy(sc->re_parent_tag);
1276 re_newbuf(struct re_softc *sc, int idx, struct mbuf *m)
1278 struct re_dmaload_arg arg;
1279 struct mbuf *n = NULL;
1283 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1288 m->m_data = m->m_ext.ext_buf;
1291 * Initialize mbuf length fields and fixup
1292 * alignment so that the frame payload is
1295 m->m_len = m->m_pkthdr.len = MCLBYTES;
1296 m_adj(m, ETHER_ALIGN);
1302 arg.re_ring = sc->re_ldata.re_rx_list;
1304 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag,
1305 sc->re_ldata.re_rx_dmamap[idx], m, re_dma_map_desc,
1306 &arg, BUS_DMA_NOWAIT);
1307 if (error || arg.re_maxsegs != 1) {
1313 sc->re_ldata.re_rx_list[idx].re_cmdstat |= htole32(RE_RDESC_CMD_OWN);
1314 sc->re_ldata.re_rx_mbuf[idx] = m;
1316 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[idx],
1317 BUS_DMASYNC_PREREAD);
1323 re_tx_list_init(struct re_softc *sc)
1325 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ);
1326 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *));
1328 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1329 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
1330 sc->re_ldata.re_tx_prodidx = 0;
1331 sc->re_ldata.re_tx_considx = 0;
1332 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT;
1338 re_rx_list_init(struct re_softc *sc)
1342 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ);
1343 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *));
1345 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1346 error = re_newbuf(sc, i, NULL);
1351 /* Flush the RX descriptors */
1353 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1354 sc->re_ldata.re_rx_list_map,
1355 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1357 sc->re_ldata.re_rx_prodidx = 0;
1358 sc->re_head = sc->re_tail = NULL;
1364 * RX handler for C+ and 8169. For the gigE chips, we support
1365 * the reception of jumbo frames that have been fragmented
1366 * across multiple 2K mbuf cluster buffers.
1369 re_rxeof(struct re_softc *sc)
1371 struct ifnet *ifp = &sc->arpcom.ac_if;
1373 struct re_desc *cur_rx;
1374 uint32_t rxstat, rxvlan;
1377 /* Invalidate the descriptor memory */
1379 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1380 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
1382 for (i = sc->re_ldata.re_rx_prodidx;
1383 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0 ; RE_DESC_INC(i)) {
1384 cur_rx = &sc->re_ldata.re_rx_list[i];
1385 m = sc->re_ldata.re_rx_mbuf[i];
1386 total_len = RE_RXBYTES(cur_rx);
1387 rxstat = le32toh(cur_rx->re_cmdstat);
1388 rxvlan = le32toh(cur_rx->re_vlanctl);
1390 /* Invalidate the RX mbuf and unload its map */
1392 bus_dmamap_sync(sc->re_ldata.re_mtag,
1393 sc->re_ldata.re_rx_dmamap[i],
1394 BUS_DMASYNC_POSTWRITE);
1395 bus_dmamap_unload(sc->re_ldata.re_mtag,
1396 sc->re_ldata.re_rx_dmamap[i]);
1398 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1399 m->m_len = MCLBYTES - ETHER_ALIGN;
1400 if (sc->re_head == NULL) {
1401 sc->re_head = sc->re_tail = m;
1403 sc->re_tail->m_next = m;
1406 re_newbuf(sc, i, NULL);
1411 * NOTE: for the 8139C+, the frame length field
1412 * is always 12 bits in size, but for the gigE chips,
1413 * it is 13 bits (since the max RX frame length is 16K).
1414 * Unfortunately, all 32 bits in the status word
1415 * were already used, so to make room for the extra
1416 * length bit, RealTek took out the 'frame alignment
1417 * error' bit and shifted the other status bits
1418 * over one slot. The OWN, EOR, FS and LS bits are
1419 * still in the same places. We have already extracted
1420 * the frame length and checked the OWN bit, so rather
1421 * than using an alternate bit mapping, we shift the
1422 * status bits one space to the right so we can evaluate
1423 * them using the 8169 status as though it was in the
1424 * same format as that of the 8139C+.
1426 if (sc->re_type == RE_8169)
1429 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
1432 * If this is part of a multi-fragment packet,
1433 * discard all the pieces.
1435 if (sc->re_head != NULL) {
1436 m_freem(sc->re_head);
1437 sc->re_head = sc->re_tail = NULL;
1439 re_newbuf(sc, i, m);
1444 * If allocating a replacement mbuf fails,
1445 * reload the current one.
1448 if (re_newbuf(sc, i, NULL)) {
1450 if (sc->re_head != NULL) {
1451 m_freem(sc->re_head);
1452 sc->re_head = sc->re_tail = NULL;
1454 re_newbuf(sc, i, m);
1458 if (sc->re_head != NULL) {
1459 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN);
1461 * Special case: if there's 4 bytes or less
1462 * in this buffer, the mbuf can be discarded:
1463 * the last 4 bytes is the CRC, which we don't
1464 * care about anyway.
1466 if (m->m_len <= ETHER_CRC_LEN) {
1467 sc->re_tail->m_len -=
1468 (ETHER_CRC_LEN - m->m_len);
1471 m->m_len -= ETHER_CRC_LEN;
1472 sc->re_tail->m_next = m;
1475 sc->re_head = sc->re_tail = NULL;
1476 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1478 m->m_pkthdr.len = m->m_len =
1479 (total_len - ETHER_CRC_LEN);
1482 m->m_pkthdr.rcvif = ifp;
1484 /* Do RX checksumming if enabled */
1486 if (ifp->if_capenable & IFCAP_RXCSUM) {
1488 /* Check IP header checksum */
1489 if (rxstat & RE_RDESC_STAT_PROTOID)
1490 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1491 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
1492 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1494 /* Check TCP/UDP checksum */
1495 if ((RE_TCPPKT(rxstat) &&
1496 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
1497 (RE_UDPPKT(rxstat) &&
1498 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) {
1499 m->m_pkthdr.csum_flags |=
1500 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1501 m->m_pkthdr.csum_data = 0xffff;
1505 if (rxvlan & RE_RDESC_VLANCTL_TAG)
1507 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA)));
1509 (*ifp->if_input)(ifp, m);
1512 /* Flush the RX DMA ring */
1514 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1515 sc->re_ldata.re_rx_list_map,
1516 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1518 sc->re_ldata.re_rx_prodidx = i;
1522 re_txeof(struct re_softc *sc)
1524 struct ifnet *ifp = &sc->arpcom.ac_if;
1528 /* Invalidate the TX descriptor list */
1530 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1531 sc->re_ldata.re_tx_list_map,
1532 BUS_DMASYNC_POSTREAD);
1534 for (idx = sc->re_ldata.re_tx_considx;
1535 idx != sc->re_ldata.re_tx_prodidx; RE_DESC_INC(idx)) {
1536 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
1537 if (txstat & RE_TDESC_CMD_OWN)
1541 * We only stash mbufs in the last descriptor
1542 * in a fragment chain, which also happens to
1543 * be the only place where the TX status bits
1546 if (txstat & RE_TDESC_CMD_EOF) {
1547 m_freem(sc->re_ldata.re_tx_mbuf[idx]);
1548 sc->re_ldata.re_tx_mbuf[idx] = NULL;
1549 bus_dmamap_unload(sc->re_ldata.re_mtag,
1550 sc->re_ldata.re_tx_dmamap[idx]);
1551 if (txstat & (RE_TDESC_STAT_EXCESSCOL|
1552 RE_TDESC_STAT_COLCNT))
1553 ifp->if_collisions++;
1554 if (txstat & RE_TDESC_STAT_TXERRSUM)
1559 sc->re_ldata.re_tx_free++;
1562 /* No changes made to the TX ring, so no flush needed */
1563 if (idx != sc->re_ldata.re_tx_considx) {
1564 sc->re_ldata.re_tx_considx = idx;
1565 ifp->if_flags &= ~IFF_OACTIVE;
1570 * If not all descriptors have been released reaped yet,
1571 * reload the timer so that we will eventually get another
1572 * interrupt that will cause us to re-enter this routine.
1573 * This is done in case the transmitter has gone idle.
1575 if (sc->re_ldata.re_tx_free != RE_TX_DESC_CNT)
1576 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
1582 struct re_softc *sc = xsc;
1583 struct mii_data *mii;
1587 mii = device_get_softc(sc->re_miibus);
1590 callout_reset(&sc->re_timer, hz, re_tick, sc);
1595 #ifdef DEVICE_POLLING
1598 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1600 struct re_softc *sc = ifp->if_softc;
1604 /* disable interrupts */
1605 CSR_WRITE_2(sc, RE_IMR, 0x0000);
1607 case POLL_DEREGISTER:
1608 /* enable interrupts */
1609 CSR_WRITE_2(sc, RE_IMR, RE_INTRS_CPLUS);
1612 sc->rxcycles = count;
1616 if (!ifq_is_empty(&ifp->if_snd))
1617 (*ifp->if_start)(ifp);
1619 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1622 status = CSR_READ_2(sc, RE_ISR);
1623 if (status == 0xffff)
1626 CSR_WRITE_2(sc, RE_ISR, status);
1629 * XXX check behaviour on receiver stalls.
1632 if (status & RE_ISR_SYSTEM_ERR) {
1640 #endif /* DEVICE_POLLING */
1645 struct re_softc *sc = arg;
1646 struct ifnet *ifp = &sc->arpcom.ac_if;
1649 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0)
1653 status = CSR_READ_2(sc, RE_ISR);
1654 /* If the card has gone away the read returns 0xffff. */
1655 if (status == 0xffff)
1658 CSR_WRITE_2(sc, RE_ISR, status);
1660 if ((status & RE_INTRS_CPLUS) == 0)
1663 if (status & RE_ISR_RX_OK)
1666 if (status & RE_ISR_RX_ERR)
1669 if ((status & RE_ISR_TIMEOUT_EXPIRED) ||
1670 (status & RE_ISR_TX_ERR) ||
1671 (status & RE_ISR_TX_DESC_UNAVAIL))
1674 if (status & RE_ISR_SYSTEM_ERR) {
1679 if (status & RE_ISR_LINKCHG)
1683 if (!ifq_is_empty(&ifp->if_snd))
1684 (*ifp->if_start)(ifp);
1688 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx, int *called_defrag)
1690 struct ifnet *ifp = &sc->arpcom.ac_if;
1691 struct mbuf *m, *m_new = NULL;
1692 struct re_dmaload_arg arg;
1697 if (sc->re_ldata.re_tx_free <= 4)
1703 * Set up checksum offload. Note: checksum offload bits must
1704 * appear in all descriptors of a multi-descriptor transmit
1705 * attempt. (This is according to testing done with an 8169
1706 * chip. I'm not sure if this is a requirement or a bug.)
1711 if (m->m_pkthdr.csum_flags & CSUM_IP)
1712 arg.re_flags |= RE_TDESC_CMD_IPCSUM;
1713 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1714 arg.re_flags |= RE_TDESC_CMD_TCPCSUM;
1715 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1716 arg.re_flags |= RE_TDESC_CMD_UDPCSUM;
1720 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1721 if (arg.re_maxsegs > 4)
1722 arg.re_maxsegs -= 4;
1723 arg.re_ring = sc->re_ldata.re_tx_list;
1725 map = sc->re_ldata.re_tx_dmamap[*idx];
1726 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1727 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1729 if (error && error != EFBIG) {
1730 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1734 /* Too many segments to map, coalesce into a single mbuf */
1736 if (error || arg.re_maxsegs == 0) {
1737 m_new = m_defrag_nofree(m, MB_DONTWAIT);
1748 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1749 arg.re_ring = sc->re_ldata.re_tx_list;
1751 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1752 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1755 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1761 * Insure that the map for this transmission
1762 * is placed at the array index of the last descriptor
1765 sc->re_ldata.re_tx_dmamap[*idx] =
1766 sc->re_ldata.re_tx_dmamap[arg.re_idx];
1767 sc->re_ldata.re_tx_dmamap[arg.re_idx] = map;
1769 sc->re_ldata.re_tx_mbuf[arg.re_idx] = m;
1770 sc->re_ldata.re_tx_free -= arg.re_maxsegs;
1773 * Set up hardware VLAN tagging. Note: vlan tag info must
1774 * appear in the first descriptor of a multi-descriptor
1775 * transmission attempt.
1778 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1779 m->m_pkthdr.rcvif != NULL &&
1780 m->m_pkthdr.rcvif->if_type == IFT_L2VLAN) {
1782 ifv = m->m_pkthdr.rcvif->if_softc;
1784 sc->re_ldata.re_tx_list[*idx].re_vlanctl =
1785 htole32(htobe16(ifv->ifv_tag) | RE_TDESC_VLANCTL_TAG);
1788 /* Transfer ownership of packet to the chip. */
1790 sc->re_ldata.re_tx_list[arg.re_idx].re_cmdstat |=
1791 htole32(RE_TDESC_CMD_OWN);
1792 if (*idx != arg.re_idx)
1793 sc->re_ldata.re_tx_list[*idx].re_cmdstat |=
1794 htole32(RE_TDESC_CMD_OWN);
1796 RE_DESC_INC(arg.re_idx);
1803 * Main transmit routine for C+ and gigE NICs.
1807 re_start(struct ifnet *ifp)
1809 struct re_softc *sc = ifp->if_softc;
1810 struct mbuf *m_head = NULL, *m_head2;
1811 int called_defrag, idx;
1815 idx = sc->re_ldata.re_tx_prodidx;
1817 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
1818 m_head = ifq_poll(&ifp->if_snd);
1822 if (re_encap(sc, &m_head, &idx, &called_defrag)) {
1823 if (called_defrag) {
1824 m_head2 = ifq_dequeue(&ifp->if_snd);
1827 ifp->if_flags |= IFF_OACTIVE;
1831 m_head2 = ifq_dequeue(&ifp->if_snd);
1836 * If there's a BPF listener, bounce a copy of this frame
1839 BPF_MTAP(ifp, m_head);
1842 /* Flush the TX descriptors */
1843 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1844 sc->re_ldata.re_tx_list_map,
1845 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1847 sc->re_ldata.re_tx_prodidx = idx;
1850 * RealTek put the TX poll request register in a different
1851 * location on the 8169 gigE chip. I don't know why.
1853 if (sc->re_type == RE_8169)
1854 CSR_WRITE_2(sc, RE_GTXSTART, RE_TXSTART_START);
1856 CSR_WRITE_2(sc, RE_TXSTART, RE_TXSTART_START);
1859 * Use the countdown timer for interrupt moderation.
1860 * 'TX done' interrupts are disabled. Instead, we reset the
1861 * countdown timer, which will begin counting until it hits
1862 * the value in the TIMERINT register, and then trigger an
1863 * interrupt. Each time we write to the TIMERCNT register,
1864 * the timer count is reset to 0.
1866 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
1869 * Set a timeout in case the chip goes out to lunch.
1879 struct re_softc *sc = xsc;
1880 struct ifnet *ifp = &sc->arpcom.ac_if;
1881 struct mii_data *mii;
1886 mii = device_get_softc(sc->re_miibus);
1889 * Cancel pending I/O and free all RX/TX buffers.
1894 * Enable C+ RX and TX mode, as well as VLAN stripping and
1895 * RX checksum offload. We must configure the C+ register
1896 * before all others.
1898 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB |
1899 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP |
1900 (ifp->if_capenable & IFCAP_RXCSUM ?
1901 RE_CPLUSCMD_RXCSUM_ENB : 0));
1904 * Init our MAC address. Even though the chipset
1905 * documentation doesn't mention it, we need to enter "Config
1906 * register write enable" mode to modify the ID registers.
1908 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG);
1909 CSR_WRITE_STREAM_4(sc, RE_IDR0,
1910 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1911 CSR_WRITE_STREAM_4(sc, RE_IDR4,
1912 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1913 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
1916 * For C+ mode, initialize the RX descriptors and mbufs.
1918 re_rx_list_init(sc);
1919 re_tx_list_init(sc);
1922 * Enable transmit and receive.
1924 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
1927 * Set the initial TX and RX configuration.
1929 if (sc->re_testmode) {
1930 if (sc->re_type == RE_8169)
1931 CSR_WRITE_4(sc, RE_TXCFG,
1932 RE_TXCFG_CONFIG | RE_LOOPTEST_ON);
1934 CSR_WRITE_4(sc, RE_TXCFG,
1935 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS);
1937 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
1938 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
1940 /* Set the individual bit to receive frames for this host only. */
1941 rxcfg = CSR_READ_4(sc, RE_RXCFG);
1942 rxcfg |= RE_RXCFG_RX_INDIV;
1944 /* If we want promiscuous mode, set the allframes bit. */
1945 if (ifp->if_flags & IFF_PROMISC) {
1946 rxcfg |= RE_RXCFG_RX_ALLPHYS;
1947 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1949 rxcfg &= ~RE_RXCFG_RX_ALLPHYS;
1950 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1954 * Set capture broadcast bit to capture broadcast frames.
1956 if (ifp->if_flags & IFF_BROADCAST) {
1957 rxcfg |= RE_RXCFG_RX_BROAD;
1958 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1960 rxcfg &= ~RE_RXCFG_RX_BROAD;
1961 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1965 * Program the multicast filter, if necessary.
1969 #ifdef DEVICE_POLLING
1971 * Disable interrupts if we are polling.
1973 if (ifp->if_flags & IFF_POLLING)
1974 CSR_WRITE_2(sc, RE_IMR, 0);
1975 else /* otherwise ... */
1976 #endif /* DEVICE_POLLING */
1978 * Enable interrupts.
1980 if (sc->re_testmode)
1981 CSR_WRITE_2(sc, RE_IMR, 0);
1983 CSR_WRITE_2(sc, RE_IMR, RE_INTRS_CPLUS);
1985 /* Set initial TX threshold */
1986 sc->re_txthresh = RE_TX_THRESH_INIT;
1988 /* Start RX/TX process. */
1989 CSR_WRITE_4(sc, RE_MISSEDPKT, 0);
1991 /* Enable receiver and transmitter. */
1992 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
1995 * Load the addresses of the RX and TX lists into the chip.
1998 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
1999 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
2000 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
2001 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
2003 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
2004 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
2005 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
2006 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
2008 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 16);
2011 * Initialize the timer interrupt register so that
2012 * a timer interrupt will be generated once the timer
2013 * reaches a certain number of ticks. The timer is
2014 * reloaded on each transmit. This gives us TX interrupt
2015 * moderation, which dramatically improves TX frame rate.
2018 if (sc->re_type == RE_8169)
2019 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800);
2021 CSR_WRITE_4(sc, RE_TIMERINT, 0x400);
2024 * For 8169 gigE NICs, set the max allowed RX packet
2025 * size so we can receive jumbo frames.
2027 if (sc->re_type == RE_8169)
2028 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383);
2030 if (sc->re_testmode) {
2037 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX);
2039 ifp->if_flags |= IFF_RUNNING;
2040 ifp->if_flags &= ~IFF_OACTIVE;
2042 callout_reset(&sc->re_timer, hz, re_tick, sc);
2048 * Set media options.
2051 re_ifmedia_upd(struct ifnet *ifp)
2053 struct re_softc *sc = ifp->if_softc;
2054 struct mii_data *mii;
2056 mii = device_get_softc(sc->re_miibus);
2063 * Report current media status.
2066 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2068 struct re_softc *sc = ifp->if_softc;
2069 struct mii_data *mii;
2071 mii = device_get_softc(sc->re_miibus);
2074 ifmr->ifm_active = mii->mii_media_active;
2075 ifmr->ifm_status = mii->mii_media_status;
2079 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2081 struct re_softc *sc = ifp->if_softc;
2082 struct ifreq *ifr = (struct ifreq *) data;
2083 struct mii_data *mii;
2090 if (ifr->ifr_mtu > RE_JUMBO_MTU)
2092 ifp->if_mtu = ifr->ifr_mtu;
2095 if (ifp->if_flags & IFF_UP)
2097 else if (ifp->if_flags & IFF_RUNNING)
2108 mii = device_get_softc(sc->re_miibus);
2109 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2112 ifp->if_capenable &= ~(IFCAP_HWCSUM);
2113 ifp->if_capenable |=
2114 ifr->ifr_reqcap & (IFCAP_HWCSUM);
2115 if (ifp->if_capenable & IFCAP_TXCSUM)
2116 ifp->if_hwassist = RE_CSUM_FEATURES;
2118 ifp->if_hwassist = 0;
2119 if (ifp->if_flags & IFF_RUNNING)
2123 error = ether_ioctl(ifp, command, data);
2133 re_watchdog(struct ifnet *ifp)
2135 struct re_softc *sc = ifp->if_softc;
2137 if_printf(ifp, "watchdog timeout\n");
2152 * Stop the adapter and free any mbufs allocated to the
2156 re_stop(struct re_softc *sc)
2158 struct ifnet *ifp = &sc->arpcom.ac_if;
2164 callout_stop(&sc->re_timer);
2166 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2168 CSR_WRITE_1(sc, RE_COMMAND, 0x00);
2169 CSR_WRITE_2(sc, RE_IMR, 0x0000);
2171 if (sc->re_head != NULL) {
2172 m_freem(sc->re_head);
2173 sc->re_head = sc->re_tail = NULL;
2176 /* Free the TX list buffers. */
2177 for (i = 0; i < RE_TX_DESC_CNT; i++) {
2178 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
2179 bus_dmamap_unload(sc->re_ldata.re_mtag,
2180 sc->re_ldata.re_tx_dmamap[i]);
2181 m_freem(sc->re_ldata.re_tx_mbuf[i]);
2182 sc->re_ldata.re_tx_mbuf[i] = NULL;
2186 /* Free the RX list buffers. */
2187 for (i = 0; i < RE_RX_DESC_CNT; i++) {
2188 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
2189 bus_dmamap_unload(sc->re_ldata.re_mtag,
2190 sc->re_ldata.re_rx_dmamap[i]);
2191 m_freem(sc->re_ldata.re_rx_mbuf[i]);
2192 sc->re_ldata.re_rx_mbuf[i] = NULL;
2200 * Device suspend routine. Stop the interface and save some PCI
2201 * settings in case the BIOS doesn't restore them properly on
2205 re_suspend(device_t dev)
2207 #ifndef BURN_BRIDGES
2210 struct re_softc *sc = device_get_softc(dev);
2214 #ifndef BURN_BRIDGES
2215 for (i = 0; i < 5; i++)
2216 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2217 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2218 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2219 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2220 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2229 * Device resume routine. Restore some PCI settings in case the BIOS
2230 * doesn't, re-enable busmastering, and restart the interface if
2234 re_resume(device_t dev)
2236 struct re_softc *sc = device_get_softc(dev);
2237 struct ifnet *ifp = &sc->arpcom.ac_if;
2238 #ifndef BURN_BRIDGES
2242 #ifndef BURN_BRIDGES
2243 /* better way to do this? */
2244 for (i = 0; i < 5; i++)
2245 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
2246 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
2247 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
2248 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
2249 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
2251 /* reenable busmastering */
2252 pci_enable_busmaster(dev);
2253 pci_enable_io(dev, SYS_RES_IOPORT);
2256 /* reinitialize interface if necessary */
2257 if (ifp->if_flags & IFF_UP)
2266 * Stop all chip I/O so that the kernel's probe routines don't
2267 * get confused by errant DMAs when rebooting.
2270 re_shutdown(device_t dev)
2272 struct re_softc *sc = device_get_softc(dev);