bnx: Implement multiple RX/TX rings and MSI-X support for 5718/57785
[dragonfly.git] / sys / dev / netif / bnx / if_bnx.c
1 /*
2  * Copyright (c) 2001 Wind River Systems
3  * Copyright (c) 1997, 1998, 1999, 2001
4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *      This product includes software developed by Bill Paul.
17  * 4. Neither the name of the author nor the names of any co-contributors
18  *    may be used to endorse or promote products derived from this software
19  *    without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31  * THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
34  */
35
36 #include "opt_bnx.h"
37 #include "opt_ifpoll.h"
38
39 #include <sys/param.h>
40 #include <sys/bus.h>
41 #include <sys/endian.h>
42 #include <sys/kernel.h>
43 #include <sys/interrupt.h>
44 #include <sys/mbuf.h>
45 #include <sys/malloc.h>
46 #include <sys/queue.h>
47 #include <sys/rman.h>
48 #include <sys/serialize.h>
49 #include <sys/socket.h>
50 #include <sys/sockio.h>
51 #include <sys/sysctl.h>
52
53 #include <netinet/ip.h>
54 #include <netinet/tcp.h>
55
56 #include <net/bpf.h>
57 #include <net/ethernet.h>
58 #include <net/if.h>
59 #include <net/if_arp.h>
60 #include <net/if_dl.h>
61 #include <net/if_media.h>
62 #include <net/if_poll.h>
63 #include <net/if_types.h>
64 #include <net/ifq_var.h>
65 #include <net/toeplitz.h>
66 #include <net/toeplitz2.h>
67 #include <net/vlan/if_vlan_var.h>
68 #include <net/vlan/if_vlan_ether.h>
69
70 #include <dev/netif/mii_layer/mii.h>
71 #include <dev/netif/mii_layer/miivar.h>
72 #include <dev/netif/mii_layer/brgphyreg.h>
73
74 #include <bus/pci/pcidevs.h>
75 #include <bus/pci/pcireg.h>
76 #include <bus/pci/pcivar.h>
77
78 #include <dev/netif/bge/if_bgereg.h>
79 #include <dev/netif/bnx/if_bnxvar.h>
80
81 /* "device miibus" required.  See GENERIC if you get errors here. */
82 #include "miibus_if.h"
83
84 #define BNX_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
85
86 #define BNX_INTR_CKINTVL        ((10 * hz) / 1000)      /* 10ms */
87
88 #ifdef BNX_RSS_DEBUG
89 #define BNX_RSS_DPRINTF(sc, lvl, fmt, ...) \
90 do { \
91         if (sc->bnx_rss_debug >= lvl) \
92                 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
93 } while (0)
94 #else   /* !BNX_RSS_DEBUG */
95 #define BNX_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
96 #endif  /* BNX_RSS_DEBUG */
97
98 static const struct bnx_type {
99         uint16_t                bnx_vid;
100         uint16_t                bnx_did;
101         char                    *bnx_name;
102 } bnx_devs[] = {
103         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717,
104                 "Broadcom BCM5717 Gigabit Ethernet" },
105         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717C,
106                 "Broadcom BCM5717C Gigabit Ethernet" },
107         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718,
108                 "Broadcom BCM5718 Gigabit Ethernet" },
109         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5719,
110                 "Broadcom BCM5719 Gigabit Ethernet" },
111         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720_ALT,
112                 "Broadcom BCM5720 Gigabit Ethernet" },
113
114         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5725,
115                 "Broadcom BCM5725 Gigabit Ethernet" },
116         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5727,
117                 "Broadcom BCM5727 Gigabit Ethernet" },
118         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5762,
119                 "Broadcom BCM5762 Gigabit Ethernet" },
120
121         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761,
122                 "Broadcom BCM57761 Gigabit Ethernet" },
123         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57762,
124                 "Broadcom BCM57762 Gigabit Ethernet" },
125         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57765,
126                 "Broadcom BCM57765 Gigabit Ethernet" },
127         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57766,
128                 "Broadcom BCM57766 Gigabit Ethernet" },
129         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57781,
130                 "Broadcom BCM57781 Gigabit Ethernet" },
131         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57782,
132                 "Broadcom BCM57782 Gigabit Ethernet" },
133         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57785,
134                 "Broadcom BCM57785 Gigabit Ethernet" },
135         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57786,
136                 "Broadcom BCM57786 Gigabit Ethernet" },
137         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57791,
138                 "Broadcom BCM57791 Fast Ethernet" },
139         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57795,
140                 "Broadcom BCM57795 Fast Ethernet" },
141
142         { 0, 0, NULL }
143 };
144
145 static const int bnx_tx_mailbox[BNX_TX_RING_MAX] = {
146         BGE_MBX_TX_HOST_PROD0_LO,
147         BGE_MBX_TX_HOST_PROD0_HI,
148         BGE_MBX_TX_HOST_PROD1_LO,
149         BGE_MBX_TX_HOST_PROD1_HI
150 };
151
152 #define BNX_IS_JUMBO_CAPABLE(sc)        ((sc)->bnx_flags & BNX_FLAG_JUMBO)
153 #define BNX_IS_5717_PLUS(sc)            ((sc)->bnx_flags & BNX_FLAG_5717_PLUS)
154 #define BNX_IS_57765_PLUS(sc)           ((sc)->bnx_flags & BNX_FLAG_57765_PLUS)
155 #define BNX_IS_57765_FAMILY(sc)  \
156         ((sc)->bnx_flags & BNX_FLAG_57765_FAMILY)
157
158 typedef int     (*bnx_eaddr_fcn_t)(struct bnx_softc *, uint8_t[]);
159
160 static int      bnx_probe(device_t);
161 static int      bnx_attach(device_t);
162 static int      bnx_detach(device_t);
163 static void     bnx_shutdown(device_t);
164 static int      bnx_suspend(device_t);
165 static int      bnx_resume(device_t);
166 static int      bnx_miibus_readreg(device_t, int, int);
167 static int      bnx_miibus_writereg(device_t, int, int, int);
168 static void     bnx_miibus_statchg(device_t);
169
170 static void     bnx_handle_status(struct bnx_softc *);
171 #ifdef IFPOLL_ENABLE
172 static void     bnx_npoll(struct ifnet *, struct ifpoll_info *);
173 static void     bnx_npoll_rx(struct ifnet *, void *, int);
174 static void     bnx_npoll_tx(struct ifnet *, void *, int);
175 static void     bnx_npoll_tx_notag(struct ifnet *, void *, int);
176 static void     bnx_npoll_status(struct ifnet *);
177 static void     bnx_npoll_status_notag(struct ifnet *);
178 #endif
179 static void     bnx_intr_legacy(void *);
180 static void     bnx_msi(void *);
181 static void     bnx_intr(struct bnx_softc *);
182 static void     bnx_msix_status(void *);
183 static void     bnx_msix_tx_status(void *);
184 static void     bnx_msix_rx(void *);
185 static void     bnx_msix_rxtx(void *);
186 static void     bnx_enable_intr(struct bnx_softc *);
187 static void     bnx_disable_intr(struct bnx_softc *);
188 static void     bnx_txeof(struct bnx_tx_ring *, uint16_t);
189 static void     bnx_rxeof(struct bnx_rx_ret_ring *, uint16_t, int);
190 static int      bnx_alloc_intr(struct bnx_softc *);
191 static int      bnx_setup_intr(struct bnx_softc *);
192 static void     bnx_free_intr(struct bnx_softc *);
193 static void     bnx_teardown_intr(struct bnx_softc *, int);
194 static int      bnx_alloc_msix(struct bnx_softc *);
195 static void     bnx_free_msix(struct bnx_softc *, boolean_t);
196 static void     bnx_check_intr_rxtx(void *);
197 static void     bnx_check_intr_rx(void *);
198 static void     bnx_check_intr_tx(void *);
199 static void     bnx_rx_std_refill_ithread(void *);
200 static void     bnx_rx_std_refill(void *, void *);
201 static void     bnx_rx_std_refill_sched_ipi(void *);
202 static void     bnx_rx_std_refill_stop(void *);
203 static void     bnx_rx_std_refill_sched(struct bnx_rx_ret_ring *,
204                     struct bnx_rx_std_ring *);
205
206 static void     bnx_start(struct ifnet *, struct ifaltq_subque *);
207 static int      bnx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
208 static void     bnx_init(void *);
209 static void     bnx_stop(struct bnx_softc *);
210 static void     bnx_watchdog(struct ifaltq_subque *);
211 static int      bnx_ifmedia_upd(struct ifnet *);
212 static void     bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
213 static void     bnx_tick(void *);
214 static void     bnx_serialize(struct ifnet *, enum ifnet_serialize);
215 static void     bnx_deserialize(struct ifnet *, enum ifnet_serialize);
216 static int      bnx_tryserialize(struct ifnet *, enum ifnet_serialize);
217 #ifdef INVARIANTS
218 static void     bnx_serialize_assert(struct ifnet *, enum ifnet_serialize,
219                     boolean_t);
220 #endif
221 static void     bnx_serialize_skipmain(struct bnx_softc *);
222 static void     bnx_deserialize_skipmain(struct bnx_softc *sc);
223
224 static int      bnx_alloc_jumbo_mem(struct bnx_softc *);
225 static void     bnx_free_jumbo_mem(struct bnx_softc *);
226 static struct bnx_jslot
227                 *bnx_jalloc(struct bnx_softc *);
228 static void     bnx_jfree(void *);
229 static void     bnx_jref(void *);
230 static int      bnx_newbuf_std(struct bnx_rx_ret_ring *, int, int);
231 static int      bnx_newbuf_jumbo(struct bnx_softc *, int, int);
232 static void     bnx_setup_rxdesc_std(struct bnx_rx_std_ring *, int);
233 static void     bnx_setup_rxdesc_jumbo(struct bnx_softc *, int);
234 static int      bnx_init_rx_ring_std(struct bnx_rx_std_ring *);
235 static void     bnx_free_rx_ring_std(struct bnx_rx_std_ring *);
236 static int      bnx_init_rx_ring_jumbo(struct bnx_softc *);
237 static void     bnx_free_rx_ring_jumbo(struct bnx_softc *);
238 static void     bnx_free_tx_ring(struct bnx_tx_ring *);
239 static int      bnx_init_tx_ring(struct bnx_tx_ring *);
240 static int      bnx_create_tx_ring(struct bnx_tx_ring *);
241 static void     bnx_destroy_tx_ring(struct bnx_tx_ring *);
242 static int      bnx_create_rx_ret_ring(struct bnx_rx_ret_ring *);
243 static void     bnx_destroy_rx_ret_ring(struct bnx_rx_ret_ring *);
244 static int      bnx_dma_alloc(device_t);
245 static void     bnx_dma_free(struct bnx_softc *);
246 static int      bnx_dma_block_alloc(struct bnx_softc *, bus_size_t,
247                     bus_dma_tag_t *, bus_dmamap_t *, void **, bus_addr_t *);
248 static void     bnx_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
249 static struct mbuf *
250                 bnx_defrag_shortdma(struct mbuf *);
251 static int      bnx_encap(struct bnx_tx_ring *, struct mbuf **,
252                     uint32_t *, int *);
253 static int      bnx_setup_tso(struct bnx_tx_ring *, struct mbuf **,
254                     uint16_t *, uint16_t *);
255 static void     bnx_setup_serialize(struct bnx_softc *);
256 static void     bnx_set_tick_cpuid(struct bnx_softc *, boolean_t);
257 static void     bnx_setup_ring_cnt(struct bnx_softc *);
258
259 static void     bnx_init_rss(struct bnx_softc *);
260 static void     bnx_reset(struct bnx_softc *);
261 static int      bnx_chipinit(struct bnx_softc *);
262 static int      bnx_blockinit(struct bnx_softc *);
263 static void     bnx_stop_block(struct bnx_softc *, bus_size_t, uint32_t);
264 static void     bnx_enable_msi(struct bnx_softc *, boolean_t);
265 static void     bnx_setmulti(struct bnx_softc *);
266 static void     bnx_setpromisc(struct bnx_softc *);
267 static void     bnx_stats_update_regs(struct bnx_softc *);
268 static uint32_t bnx_dma_swap_options(struct bnx_softc *);
269
270 static uint32_t bnx_readmem_ind(struct bnx_softc *, uint32_t);
271 static void     bnx_writemem_ind(struct bnx_softc *, uint32_t, uint32_t);
272 #ifdef notdef
273 static uint32_t bnx_readreg_ind(struct bnx_softc *, uint32_t);
274 #endif
275 static void     bnx_writemem_direct(struct bnx_softc *, uint32_t, uint32_t);
276 static void     bnx_writembx(struct bnx_softc *, int, int);
277 static int      bnx_read_nvram(struct bnx_softc *, caddr_t, int, int);
278 static uint8_t  bnx_eeprom_getbyte(struct bnx_softc *, uint32_t, uint8_t *);
279 static int      bnx_read_eeprom(struct bnx_softc *, caddr_t, uint32_t, size_t);
280
281 static void     bnx_tbi_link_upd(struct bnx_softc *, uint32_t);
282 static void     bnx_copper_link_upd(struct bnx_softc *, uint32_t);
283 static void     bnx_autopoll_link_upd(struct bnx_softc *, uint32_t);
284 static void     bnx_link_poll(struct bnx_softc *);
285
286 static int      bnx_get_eaddr_mem(struct bnx_softc *, uint8_t[]);
287 static int      bnx_get_eaddr_nvram(struct bnx_softc *, uint8_t[]);
288 static int      bnx_get_eaddr_eeprom(struct bnx_softc *, uint8_t[]);
289 static int      bnx_get_eaddr(struct bnx_softc *, uint8_t[]);
290
291 static void     bnx_coal_change(struct bnx_softc *);
292 static int      bnx_sysctl_force_defrag(SYSCTL_HANDLER_ARGS);
293 static int      bnx_sysctl_tx_wreg(SYSCTL_HANDLER_ARGS);
294 static int      bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
295 static int      bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
296 static int      bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
297 static int      bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
298 static int      bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
299 static int      bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
300 static int      bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
301                     int, int, uint32_t);
302 #ifdef IFPOLL_ENABLE
303 static int      bnx_sysctl_npoll_offset(SYSCTL_HANDLER_ARGS);
304 static int      bnx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
305 static int      bnx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
306 #endif
307 static int      bnx_sysctl_std_refill(SYSCTL_HANDLER_ARGS);
308
309 static int      bnx_msi_enable = 1;
310 static int      bnx_msix_enable = 1;
311
312 static int      bnx_rx_rings = 0; /* auto */
313 static int      bnx_tx_rings = 0; /* auto */
314
315 TUNABLE_INT("hw.bnx.msi.enable", &bnx_msi_enable);
316 TUNABLE_INT("hw.bnx.msix.enable", &bnx_msix_enable);
317 TUNABLE_INT("hw.bnx.rx_rings", &bnx_rx_rings);
318 TUNABLE_INT("hw.bnx.tx_rings", &bnx_tx_rings);
319
320 static device_method_t bnx_methods[] = {
321         /* Device interface */
322         DEVMETHOD(device_probe,         bnx_probe),
323         DEVMETHOD(device_attach,        bnx_attach),
324         DEVMETHOD(device_detach,        bnx_detach),
325         DEVMETHOD(device_shutdown,      bnx_shutdown),
326         DEVMETHOD(device_suspend,       bnx_suspend),
327         DEVMETHOD(device_resume,        bnx_resume),
328
329         /* bus interface */
330         DEVMETHOD(bus_print_child,      bus_generic_print_child),
331         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
332
333         /* MII interface */
334         DEVMETHOD(miibus_readreg,       bnx_miibus_readreg),
335         DEVMETHOD(miibus_writereg,      bnx_miibus_writereg),
336         DEVMETHOD(miibus_statchg,       bnx_miibus_statchg),
337
338         DEVMETHOD_END
339 };
340
341 static DEFINE_CLASS_0(bnx, bnx_driver, bnx_methods, sizeof(struct bnx_softc));
342 static devclass_t bnx_devclass;
343
344 DECLARE_DUMMY_MODULE(if_bnx);
345 DRIVER_MODULE(if_bnx, pci, bnx_driver, bnx_devclass, NULL, NULL);
346 DRIVER_MODULE(miibus, bnx, miibus_driver, miibus_devclass, NULL, NULL);
347
348 static uint32_t
349 bnx_readmem_ind(struct bnx_softc *sc, uint32_t off)
350 {
351         device_t dev = sc->bnx_dev;
352         uint32_t val;
353
354         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
355         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
356         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
357         return (val);
358 }
359
360 static void
361 bnx_writemem_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
362 {
363         device_t dev = sc->bnx_dev;
364
365         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
366         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
367         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
368 }
369
370 static void
371 bnx_writemem_direct(struct bnx_softc *sc, uint32_t off, uint32_t val)
372 {
373         CSR_WRITE_4(sc, off, val);
374 }
375
376 static void
377 bnx_writembx(struct bnx_softc *sc, int off, int val)
378 {
379         CSR_WRITE_4(sc, off, val);
380 }
381
382 /*
383  * Read a sequence of bytes from NVRAM.
384  */
385 static int
386 bnx_read_nvram(struct bnx_softc *sc, caddr_t dest, int off, int cnt)
387 {
388         return (1);
389 }
390
391 /*
392  * Read a byte of data stored in the EEPROM at address 'addr.' The
393  * BCM570x supports both the traditional bitbang interface and an
394  * auto access interface for reading the EEPROM. We use the auto
395  * access method.
396  */
397 static uint8_t
398 bnx_eeprom_getbyte(struct bnx_softc *sc, uint32_t addr, uint8_t *dest)
399 {
400         int i;
401         uint32_t byte = 0;
402
403         /*
404          * Enable use of auto EEPROM access so we can avoid
405          * having to use the bitbang method.
406          */
407         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
408
409         /* Reset the EEPROM, load the clock period. */
410         CSR_WRITE_4(sc, BGE_EE_ADDR,
411             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
412         DELAY(20);
413
414         /* Issue the read EEPROM command. */
415         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
416
417         /* Wait for completion */
418         for(i = 0; i < BNX_TIMEOUT * 10; i++) {
419                 DELAY(10);
420                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
421                         break;
422         }
423
424         if (i == BNX_TIMEOUT) {
425                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
426                 return(1);
427         }
428
429         /* Get result. */
430         byte = CSR_READ_4(sc, BGE_EE_DATA);
431
432         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
433
434         return(0);
435 }
436
437 /*
438  * Read a sequence of bytes from the EEPROM.
439  */
440 static int
441 bnx_read_eeprom(struct bnx_softc *sc, caddr_t dest, uint32_t off, size_t len)
442 {
443         size_t i;
444         int err;
445         uint8_t byte;
446
447         for (byte = 0, err = 0, i = 0; i < len; i++) {
448                 err = bnx_eeprom_getbyte(sc, off + i, &byte);
449                 if (err)
450                         break;
451                 *(dest + i) = byte;
452         }
453
454         return(err ? 1 : 0);
455 }
456
457 static int
458 bnx_miibus_readreg(device_t dev, int phy, int reg)
459 {
460         struct bnx_softc *sc = device_get_softc(dev);
461         uint32_t val;
462         int i;
463
464         KASSERT(phy == sc->bnx_phyno,
465             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
466
467         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
468         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
469                 CSR_WRITE_4(sc, BGE_MI_MODE,
470                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
471                 DELAY(80);
472         }
473
474         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
475             BGE_MIPHY(phy) | BGE_MIREG(reg));
476
477         /* Poll for the PHY register access to complete. */
478         for (i = 0; i < BNX_TIMEOUT; i++) {
479                 DELAY(10);
480                 val = CSR_READ_4(sc, BGE_MI_COMM);
481                 if ((val & BGE_MICOMM_BUSY) == 0) {
482                         DELAY(5);
483                         val = CSR_READ_4(sc, BGE_MI_COMM);
484                         break;
485                 }
486         }
487         if (i == BNX_TIMEOUT) {
488                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
489                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
490                 val = 0;
491         }
492
493         /* Restore the autopoll bit if necessary. */
494         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
495                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
496                 DELAY(80);
497         }
498
499         if (val & BGE_MICOMM_READFAIL)
500                 return 0;
501
502         return (val & 0xFFFF);
503 }
504
505 static int
506 bnx_miibus_writereg(device_t dev, int phy, int reg, int val)
507 {
508         struct bnx_softc *sc = device_get_softc(dev);
509         int i;
510
511         KASSERT(phy == sc->bnx_phyno,
512             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
513
514         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
515         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
516                 CSR_WRITE_4(sc, BGE_MI_MODE,
517                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
518                 DELAY(80);
519         }
520
521         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
522             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
523
524         for (i = 0; i < BNX_TIMEOUT; i++) {
525                 DELAY(10);
526                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
527                         DELAY(5);
528                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
529                         break;
530                 }
531         }
532         if (i == BNX_TIMEOUT) {
533                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
534                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
535         }
536
537         /* Restore the autopoll bit if necessary. */
538         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
539                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
540                 DELAY(80);
541         }
542
543         return 0;
544 }
545
546 static void
547 bnx_miibus_statchg(device_t dev)
548 {
549         struct bnx_softc *sc;
550         struct mii_data *mii;
551
552         sc = device_get_softc(dev);
553         mii = device_get_softc(sc->bnx_miibus);
554
555         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
556             (IFM_ACTIVE | IFM_AVALID)) {
557                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
558                 case IFM_10_T:
559                 case IFM_100_TX:
560                         sc->bnx_link = 1;
561                         break;
562                 case IFM_1000_T:
563                 case IFM_1000_SX:
564                 case IFM_2500_SX:
565                         sc->bnx_link = 1;
566                         break;
567                 default:
568                         sc->bnx_link = 0;
569                         break;
570                 }
571         } else {
572                 sc->bnx_link = 0;
573         }
574         if (sc->bnx_link == 0)
575                 return;
576
577         BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
578         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
579             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
580                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
581         } else {
582                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
583         }
584
585         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
586                 BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
587         } else {
588                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
589         }
590 }
591
592 /*
593  * Memory management for jumbo frames.
594  */
595 static int
596 bnx_alloc_jumbo_mem(struct bnx_softc *sc)
597 {
598         struct ifnet *ifp = &sc->arpcom.ac_if;
599         struct bnx_jslot *entry;
600         uint8_t *ptr;
601         bus_addr_t paddr;
602         int i, error;
603
604         /*
605          * Create tag for jumbo mbufs.
606          * This is really a bit of a kludge. We allocate a special
607          * jumbo buffer pool which (thanks to the way our DMA
608          * memory allocation works) will consist of contiguous
609          * pages. This means that even though a jumbo buffer might
610          * be larger than a page size, we don't really need to
611          * map it into more than one DMA segment. However, the
612          * default mbuf tag will result in multi-segment mappings,
613          * so we have to create a special jumbo mbuf tag that
614          * lets us get away with mapping the jumbo buffers as
615          * a single segment. I think eventually the driver should
616          * be changed so that it uses ordinary mbufs and cluster
617          * buffers, i.e. jumbo frames can span multiple DMA
618          * descriptors. But that's a project for another day.
619          */
620
621         /*
622          * Create DMA stuffs for jumbo RX ring.
623          */
624         error = bnx_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
625                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
626                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_map,
627                                     (void *)&sc->bnx_ldata.bnx_rx_jumbo_ring,
628                                     &sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
629         if (error) {
630                 if_printf(ifp, "could not create jumbo RX ring\n");
631                 return error;
632         }
633
634         /*
635          * Create DMA stuffs for jumbo buffer block.
636          */
637         error = bnx_dma_block_alloc(sc, BNX_JMEM,
638                                     &sc->bnx_cdata.bnx_jumbo_tag,
639                                     &sc->bnx_cdata.bnx_jumbo_map,
640                                     (void **)&sc->bnx_ldata.bnx_jumbo_buf,
641                                     &paddr);
642         if (error) {
643                 if_printf(ifp, "could not create jumbo buffer\n");
644                 return error;
645         }
646
647         SLIST_INIT(&sc->bnx_jfree_listhead);
648
649         /*
650          * Now divide it up into 9K pieces and save the addresses
651          * in an array. Note that we play an evil trick here by using
652          * the first few bytes in the buffer to hold the the address
653          * of the softc structure for this interface. This is because
654          * bnx_jfree() needs it, but it is called by the mbuf management
655          * code which will not pass it to us explicitly.
656          */
657         for (i = 0, ptr = sc->bnx_ldata.bnx_jumbo_buf; i < BNX_JSLOTS; i++) {
658                 entry = &sc->bnx_cdata.bnx_jslots[i];
659                 entry->bnx_sc = sc;
660                 entry->bnx_buf = ptr;
661                 entry->bnx_paddr = paddr;
662                 entry->bnx_inuse = 0;
663                 entry->bnx_slot = i;
664                 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, entry, jslot_link);
665
666                 ptr += BNX_JLEN;
667                 paddr += BNX_JLEN;
668         }
669         return 0;
670 }
671
672 static void
673 bnx_free_jumbo_mem(struct bnx_softc *sc)
674 {
675         /* Destroy jumbo RX ring. */
676         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
677                            sc->bnx_cdata.bnx_rx_jumbo_ring_map,
678                            sc->bnx_ldata.bnx_rx_jumbo_ring);
679
680         /* Destroy jumbo buffer block. */
681         bnx_dma_block_free(sc->bnx_cdata.bnx_jumbo_tag,
682                            sc->bnx_cdata.bnx_jumbo_map,
683                            sc->bnx_ldata.bnx_jumbo_buf);
684 }
685
686 /*
687  * Allocate a jumbo buffer.
688  */
689 static struct bnx_jslot *
690 bnx_jalloc(struct bnx_softc *sc)
691 {
692         struct bnx_jslot *entry;
693
694         lwkt_serialize_enter(&sc->bnx_jslot_serializer);
695         entry = SLIST_FIRST(&sc->bnx_jfree_listhead);
696         if (entry) {
697                 SLIST_REMOVE_HEAD(&sc->bnx_jfree_listhead, jslot_link);
698                 entry->bnx_inuse = 1;
699         } else {
700                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
701         }
702         lwkt_serialize_exit(&sc->bnx_jslot_serializer);
703         return(entry);
704 }
705
706 /*
707  * Adjust usage count on a jumbo buffer.
708  */
709 static void
710 bnx_jref(void *arg)
711 {
712         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
713         struct bnx_softc *sc = entry->bnx_sc;
714
715         if (sc == NULL)
716                 panic("bnx_jref: can't find softc pointer!");
717
718         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
719                 panic("bnx_jref: asked to reference buffer "
720                     "that we don't manage!");
721         } else if (entry->bnx_inuse == 0) {
722                 panic("bnx_jref: buffer already free!");
723         } else {
724                 atomic_add_int(&entry->bnx_inuse, 1);
725         }
726 }
727
728 /*
729  * Release a jumbo buffer.
730  */
731 static void
732 bnx_jfree(void *arg)
733 {
734         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
735         struct bnx_softc *sc = entry->bnx_sc;
736
737         if (sc == NULL)
738                 panic("bnx_jfree: can't find softc pointer!");
739
740         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
741                 panic("bnx_jfree: asked to free buffer that we don't manage!");
742         } else if (entry->bnx_inuse == 0) {
743                 panic("bnx_jfree: buffer already free!");
744         } else {
745                 /*
746                  * Possible MP race to 0, use the serializer.  The atomic insn
747                  * is still needed for races against bnx_jref().
748                  */
749                 lwkt_serialize_enter(&sc->bnx_jslot_serializer);
750                 atomic_subtract_int(&entry->bnx_inuse, 1);
751                 if (entry->bnx_inuse == 0) {
752                         SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, 
753                                           entry, jslot_link);
754                 }
755                 lwkt_serialize_exit(&sc->bnx_jslot_serializer);
756         }
757 }
758
759
760 /*
761  * Intialize a standard receive ring descriptor.
762  */
763 static int
764 bnx_newbuf_std(struct bnx_rx_ret_ring *ret, int i, int init)
765 {
766         struct mbuf *m_new = NULL;
767         bus_dma_segment_t seg;
768         bus_dmamap_t map;
769         int error, nsegs;
770         struct bnx_rx_buf *rb;
771
772         rb = &ret->bnx_std->bnx_rx_std_buf[i];
773         KASSERT(!rb->bnx_rx_refilled, ("RX buf %dth has been refilled", i));
774
775         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
776         if (m_new == NULL) {
777                 error = ENOBUFS;
778                 goto back;
779         }
780         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
781         m_adj(m_new, ETHER_ALIGN);
782
783         error = bus_dmamap_load_mbuf_segment(ret->bnx_rx_mtag,
784             ret->bnx_rx_tmpmap, m_new, &seg, 1, &nsegs, BUS_DMA_NOWAIT);
785         if (error) {
786                 m_freem(m_new);
787                 goto back;
788         }
789
790         if (!init) {
791                 bus_dmamap_sync(ret->bnx_rx_mtag, rb->bnx_rx_dmamap,
792                     BUS_DMASYNC_POSTREAD);
793                 bus_dmamap_unload(ret->bnx_rx_mtag, rb->bnx_rx_dmamap);
794         }
795
796         map = ret->bnx_rx_tmpmap;
797         ret->bnx_rx_tmpmap = rb->bnx_rx_dmamap;
798
799         rb->bnx_rx_dmamap = map;
800         rb->bnx_rx_mbuf = m_new;
801         rb->bnx_rx_paddr = seg.ds_addr;
802         rb->bnx_rx_len = m_new->m_len;
803 back:
804         cpu_sfence();
805         rb->bnx_rx_refilled = 1;
806         return error;
807 }
808
809 static void
810 bnx_setup_rxdesc_std(struct bnx_rx_std_ring *std, int i)
811 {
812         struct bnx_rx_buf *rb;
813         struct bge_rx_bd *r;
814         bus_addr_t paddr;
815         int len;
816
817         rb = &std->bnx_rx_std_buf[i];
818         KASSERT(rb->bnx_rx_refilled, ("RX buf %dth is not refilled", i));
819
820         paddr = rb->bnx_rx_paddr;
821         len = rb->bnx_rx_len;
822
823         cpu_mfence();
824
825         rb->bnx_rx_refilled = 0;
826
827         r = &std->bnx_rx_std_ring[i];
828         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(paddr);
829         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(paddr);
830         r->bge_len = len;
831         r->bge_idx = i;
832         r->bge_flags = BGE_RXBDFLAG_END;
833 }
834
835 /*
836  * Initialize a jumbo receive ring descriptor. This allocates
837  * a jumbo buffer from the pool managed internally by the driver.
838  */
839 static int
840 bnx_newbuf_jumbo(struct bnx_softc *sc, int i, int init)
841 {
842         struct mbuf *m_new = NULL;
843         struct bnx_jslot *buf;
844         bus_addr_t paddr;
845
846         /* Allocate the mbuf. */
847         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
848         if (m_new == NULL)
849                 return ENOBUFS;
850
851         /* Allocate the jumbo buffer */
852         buf = bnx_jalloc(sc);
853         if (buf == NULL) {
854                 m_freem(m_new);
855                 return ENOBUFS;
856         }
857
858         /* Attach the buffer to the mbuf. */
859         m_new->m_ext.ext_arg = buf;
860         m_new->m_ext.ext_buf = buf->bnx_buf;
861         m_new->m_ext.ext_free = bnx_jfree;
862         m_new->m_ext.ext_ref = bnx_jref;
863         m_new->m_ext.ext_size = BNX_JUMBO_FRAMELEN;
864
865         m_new->m_flags |= M_EXT;
866
867         m_new->m_data = m_new->m_ext.ext_buf;
868         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
869
870         paddr = buf->bnx_paddr;
871         m_adj(m_new, ETHER_ALIGN);
872         paddr += ETHER_ALIGN;
873
874         /* Save necessary information */
875         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_rx_mbuf = m_new;
876         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_rx_paddr = paddr;
877
878         /* Set up the descriptor. */
879         bnx_setup_rxdesc_jumbo(sc, i);
880         return 0;
881 }
882
883 static void
884 bnx_setup_rxdesc_jumbo(struct bnx_softc *sc, int i)
885 {
886         struct bge_rx_bd *r;
887         struct bnx_rx_buf *rc;
888
889         r = &sc->bnx_ldata.bnx_rx_jumbo_ring[i];
890         rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
891
892         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_rx_paddr);
893         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_rx_paddr);
894         r->bge_len = rc->bnx_rx_mbuf->m_len;
895         r->bge_idx = i;
896         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
897 }
898
899 static int
900 bnx_init_rx_ring_std(struct bnx_rx_std_ring *std)
901 {
902         int i, error;
903
904         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
905                 /* Use the first RX return ring's tmp RX mbuf DMA map */
906                 error = bnx_newbuf_std(&std->bnx_sc->bnx_rx_ret_ring[0], i, 1);
907                 if (error)
908                         return error;
909                 bnx_setup_rxdesc_std(std, i);
910         }
911
912         std->bnx_rx_std_refill = 0;
913         std->bnx_rx_std_running = 0;
914         cpu_sfence();
915         lwkt_serialize_handler_enable(&std->bnx_rx_std_serialize);
916
917         std->bnx_rx_std = BGE_STD_RX_RING_CNT - 1;
918         bnx_writembx(std->bnx_sc, BGE_MBX_RX_STD_PROD_LO, std->bnx_rx_std);
919
920         return(0);
921 }
922
923 static void
924 bnx_free_rx_ring_std(struct bnx_rx_std_ring *std)
925 {
926         int i;
927
928         lwkt_serialize_handler_disable(&std->bnx_rx_std_serialize);
929
930         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
931                 struct bnx_rx_buf *rb = &std->bnx_rx_std_buf[i];
932
933                 rb->bnx_rx_refilled = 0;
934                 if (rb->bnx_rx_mbuf != NULL) {
935                         bus_dmamap_unload(std->bnx_rx_mtag, rb->bnx_rx_dmamap);
936                         m_freem(rb->bnx_rx_mbuf);
937                         rb->bnx_rx_mbuf = NULL;
938                 }
939                 bzero(&std->bnx_rx_std_ring[i], sizeof(struct bge_rx_bd));
940         }
941 }
942
943 static int
944 bnx_init_rx_ring_jumbo(struct bnx_softc *sc)
945 {
946         struct bge_rcb *rcb;
947         int i, error;
948
949         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
950                 error = bnx_newbuf_jumbo(sc, i, 1);
951                 if (error)
952                         return error;
953         }
954
955         sc->bnx_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
956
957         rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
958         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
959         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
960
961         bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
962
963         return(0);
964 }
965
966 static void
967 bnx_free_rx_ring_jumbo(struct bnx_softc *sc)
968 {
969         int i;
970
971         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
972                 struct bnx_rx_buf *rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
973
974                 if (rc->bnx_rx_mbuf != NULL) {
975                         m_freem(rc->bnx_rx_mbuf);
976                         rc->bnx_rx_mbuf = NULL;
977                 }
978                 bzero(&sc->bnx_ldata.bnx_rx_jumbo_ring[i],
979                     sizeof(struct bge_rx_bd));
980         }
981 }
982
983 static void
984 bnx_free_tx_ring(struct bnx_tx_ring *txr)
985 {
986         int i;
987
988         for (i = 0; i < BGE_TX_RING_CNT; i++) {
989                 struct bnx_tx_buf *buf = &txr->bnx_tx_buf[i];
990
991                 if (buf->bnx_tx_mbuf != NULL) {
992                         bus_dmamap_unload(txr->bnx_tx_mtag,
993                             buf->bnx_tx_dmamap);
994                         m_freem(buf->bnx_tx_mbuf);
995                         buf->bnx_tx_mbuf = NULL;
996                 }
997                 bzero(&txr->bnx_tx_ring[i], sizeof(struct bge_tx_bd));
998         }
999         txr->bnx_tx_saved_considx = BNX_TXCONS_UNSET;
1000 }
1001
1002 static int
1003 bnx_init_tx_ring(struct bnx_tx_ring *txr)
1004 {
1005         txr->bnx_tx_cnt = 0;
1006         txr->bnx_tx_saved_considx = 0;
1007         txr->bnx_tx_prodidx = 0;
1008
1009         /* Initialize transmit producer index for host-memory send ring. */
1010         bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, txr->bnx_tx_prodidx);
1011
1012         return(0);
1013 }
1014
1015 static void
1016 bnx_setmulti(struct bnx_softc *sc)
1017 {
1018         struct ifnet *ifp;
1019         struct ifmultiaddr *ifma;
1020         uint32_t hashes[4] = { 0, 0, 0, 0 };
1021         int h, i;
1022
1023         ifp = &sc->arpcom.ac_if;
1024
1025         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1026                 for (i = 0; i < 4; i++)
1027                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1028                 return;
1029         }
1030
1031         /* First, zot all the existing filters. */
1032         for (i = 0; i < 4; i++)
1033                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1034
1035         /* Now program new ones. */
1036         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1037                 if (ifma->ifma_addr->sa_family != AF_LINK)
1038                         continue;
1039                 h = ether_crc32_le(
1040                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1041                     ETHER_ADDR_LEN) & 0x7f;
1042                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1043         }
1044
1045         for (i = 0; i < 4; i++)
1046                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1047 }
1048
1049 /*
1050  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1051  * self-test results.
1052  */
1053 static int
1054 bnx_chipinit(struct bnx_softc *sc)
1055 {
1056         uint32_t dma_rw_ctl, mode_ctl;
1057         int i;
1058
1059         /* Set endian type before we access any non-PCI registers. */
1060         pci_write_config(sc->bnx_dev, BGE_PCI_MISC_CTL,
1061             BGE_INIT | BGE_PCIMISCCTL_TAGGED_STATUS, 4);
1062
1063         /* Clear the MAC control register */
1064         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1065
1066         /*
1067          * Clear the MAC statistics block in the NIC's
1068          * internal memory.
1069          */
1070         for (i = BGE_STATS_BLOCK;
1071             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1072                 BNX_MEMWIN_WRITE(sc, i, 0);
1073
1074         for (i = BGE_STATUS_BLOCK;
1075             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1076                 BNX_MEMWIN_WRITE(sc, i, 0);
1077
1078         if (BNX_IS_57765_FAMILY(sc)) {
1079                 uint32_t val;
1080
1081                 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) {
1082                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1083                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1084
1085                         /* Access the lower 1K of PL PCI-E block registers. */
1086                         CSR_WRITE_4(sc, BGE_MODE_CTL,
1087                             val | BGE_MODECTL_PCIE_PL_SEL);
1088
1089                         val = CSR_READ_4(sc, BGE_PCIE_PL_LO_PHYCTL5);
1090                         val |= BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ;
1091                         CSR_WRITE_4(sc, BGE_PCIE_PL_LO_PHYCTL5, val);
1092
1093                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1094                 }
1095                 if (sc->bnx_chiprev != BGE_CHIPREV_57765_AX) {
1096                         /* Fix transmit hangs */
1097                         val = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL);
1098                         val |= BGE_CPMU_PADRNG_CTL_RDIV2;
1099                         CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, val);
1100
1101                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1102                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1103
1104                         /* Access the lower 1K of DL PCI-E block registers. */
1105                         CSR_WRITE_4(sc, BGE_MODE_CTL,
1106                             val | BGE_MODECTL_PCIE_DL_SEL);
1107
1108                         val = CSR_READ_4(sc, BGE_PCIE_DL_LO_FTSMAX);
1109                         val &= ~BGE_PCIE_DL_LO_FTSMAX_MASK;
1110                         val |= BGE_PCIE_DL_LO_FTSMAX_VAL;
1111                         CSR_WRITE_4(sc, BGE_PCIE_DL_LO_FTSMAX, val);
1112
1113                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1114                 }
1115
1116                 val = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
1117                 val &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK;
1118                 val |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
1119                 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, val);
1120         }
1121
1122         /*
1123          * Set up the PCI DMA control register.
1124          */
1125         dma_rw_ctl = pci_read_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, 4);
1126         /*
1127          * Disable 32bytes cache alignment for DMA write to host memory
1128          *
1129          * NOTE:
1130          * 64bytes cache alignment for DMA write to host memory is still
1131          * enabled.
1132          */
1133         dma_rw_ctl |= BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1134         if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
1135                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1136         /*
1137          * Enable HW workaround for controllers that misinterpret
1138          * a status tag update and leave interrupts permanently
1139          * disabled.
1140          */
1141         if (sc->bnx_asicrev != BGE_ASICREV_BCM5717 &&
1142             sc->bnx_asicrev != BGE_ASICREV_BCM5762 &&
1143             !BNX_IS_57765_FAMILY(sc))
1144                 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1145         if (bootverbose) {
1146                 if_printf(&sc->arpcom.ac_if, "DMA read/write %#x\n",
1147                     dma_rw_ctl);
1148         }
1149         pci_write_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1150
1151         /*
1152          * Set up general mode register.
1153          */
1154         mode_ctl = bnx_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR |
1155             BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM;
1156         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1157
1158         /*
1159          * Disable memory write invalidate.  Apparently it is not supported
1160          * properly by these devices.  Also ensure that INTx isn't disabled,
1161          * as these chips need it even when using MSI.
1162          */
1163         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_CMD,
1164             (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1165
1166         /* Set the timer prescaler (always 66Mhz) */
1167         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1168
1169         return(0);
1170 }
1171
1172 static int
1173 bnx_blockinit(struct bnx_softc *sc)
1174 {
1175         struct bnx_intr_data *intr;
1176         struct bge_rcb *rcb;
1177         bus_size_t vrcb;
1178         bge_hostaddr taddr;
1179         uint32_t val;
1180         int i, limit;
1181
1182         /*
1183          * Initialize the memory window pointer register so that
1184          * we can access the first 32K of internal NIC RAM. This will
1185          * allow us to set up the TX send ring RCBs and the RX return
1186          * ring RCBs, plus other things which live in NIC memory.
1187          */
1188         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1189
1190         /* Configure mbuf pool watermarks */
1191         if (BNX_IS_57765_PLUS(sc)) {
1192                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1193                 if (sc->arpcom.ac_if.if_mtu > ETHERMTU) {
1194                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1195                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1196                 } else {
1197                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1198                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1199                 }
1200         } else {
1201                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1202                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1203                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1204         }
1205
1206         /* Configure DMA resource watermarks */
1207         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1208         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1209
1210         /* Enable buffer manager */
1211         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1212         /*
1213          * Change the arbitration algorithm of TXMBUF read request to
1214          * round-robin instead of priority based for BCM5719.  When
1215          * TXFIFO is almost empty, RDMA will hold its request until
1216          * TXFIFO is not almost empty.
1217          */
1218         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719)
1219                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1220         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1221             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0 ||
1222             sc->bnx_chipid == BGE_CHIPID_BCM5720_A0)
1223                 val |= BGE_BMANMODE_LOMBUF_ATTN;
1224         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1225
1226         /* Poll for buffer manager start indication */
1227         for (i = 0; i < BNX_TIMEOUT; i++) {
1228                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1229                         break;
1230                 DELAY(10);
1231         }
1232
1233         if (i == BNX_TIMEOUT) {
1234                 if_printf(&sc->arpcom.ac_if,
1235                           "buffer manager failed to start\n");
1236                 return(ENXIO);
1237         }
1238
1239         /* Enable flow-through queues */
1240         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1241         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1242
1243         /* Wait until queue initialization is complete */
1244         for (i = 0; i < BNX_TIMEOUT; i++) {
1245                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1246                         break;
1247                 DELAY(10);
1248         }
1249
1250         if (i == BNX_TIMEOUT) {
1251                 if_printf(&sc->arpcom.ac_if,
1252                           "flow-through queue init failed\n");
1253                 return(ENXIO);
1254         }
1255
1256         /*
1257          * Summary of rings supported by the controller:
1258          *
1259          * Standard Receive Producer Ring
1260          * - This ring is used to feed receive buffers for "standard"
1261          *   sized frames (typically 1536 bytes) to the controller.
1262          *
1263          * Jumbo Receive Producer Ring
1264          * - This ring is used to feed receive buffers for jumbo sized
1265          *   frames (i.e. anything bigger than the "standard" frames)
1266          *   to the controller.
1267          *
1268          * Mini Receive Producer Ring
1269          * - This ring is used to feed receive buffers for "mini"
1270          *   sized frames to the controller.
1271          * - This feature required external memory for the controller
1272          *   but was never used in a production system.  Should always
1273          *   be disabled.
1274          *
1275          * Receive Return Ring
1276          * - After the controller has placed an incoming frame into a
1277          *   receive buffer that buffer is moved into a receive return
1278          *   ring.  The driver is then responsible to passing the
1279          *   buffer up to the stack.  Many versions of the controller
1280          *   support multiple RR rings.
1281          *
1282          * Send Ring
1283          * - This ring is used for outgoing frames.  Many versions of
1284          *   the controller support multiple send rings.
1285          */
1286
1287         /* Initialize the standard receive producer ring control block. */
1288         rcb = &sc->bnx_ldata.bnx_info.bnx_std_rx_rcb;
1289         rcb->bge_hostaddr.bge_addr_lo =
1290             BGE_ADDR_LO(sc->bnx_rx_std_ring.bnx_rx_std_ring_paddr);
1291         rcb->bge_hostaddr.bge_addr_hi =
1292             BGE_ADDR_HI(sc->bnx_rx_std_ring.bnx_rx_std_ring_paddr);
1293         if (BNX_IS_57765_PLUS(sc)) {
1294                 /*
1295                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1296                  * Bits 15-2 : Maximum RX frame size
1297                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
1298                  * Bit 0     : Reserved
1299                  */
1300                 rcb->bge_maxlen_flags =
1301                     BGE_RCB_MAXLEN_FLAGS(512, BNX_MAX_FRAMELEN << 2);
1302         } else {
1303                 /*
1304                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1305                  * Bits 15-2 : Reserved (should be 0)
1306                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1307                  * Bit 0     : Reserved
1308                  */
1309                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1310         }
1311         if (BNX_IS_5717_PLUS(sc))
1312                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1313         else
1314                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1315         /* Write the standard receive producer ring control block. */
1316         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1317         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1318         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1319         if (!BNX_IS_5717_PLUS(sc))
1320                 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1321         /* Reset the standard receive producer ring producer index. */
1322         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1323
1324         /*
1325          * Initialize the jumbo RX producer ring control
1326          * block.  We set the 'ring disabled' bit in the
1327          * flags field until we're actually ready to start
1328          * using this ring (i.e. once we set the MTU
1329          * high enough to require it).
1330          */
1331         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1332                 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
1333                 /* Get the jumbo receive producer ring RCB parameters. */
1334                 rcb->bge_hostaddr.bge_addr_lo =
1335                     BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1336                 rcb->bge_hostaddr.bge_addr_hi =
1337                     BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1338                 rcb->bge_maxlen_flags =
1339                     BGE_RCB_MAXLEN_FLAGS(BNX_MAX_FRAMELEN,
1340                     BGE_RCB_FLAG_RING_DISABLED);
1341                 if (BNX_IS_5717_PLUS(sc))
1342                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1343                 else
1344                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1345                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1346                     rcb->bge_hostaddr.bge_addr_hi);
1347                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1348                     rcb->bge_hostaddr.bge_addr_lo);
1349                 /* Program the jumbo receive producer ring RCB parameters. */
1350                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1351                     rcb->bge_maxlen_flags);
1352                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1353                 /* Reset the jumbo receive producer ring producer index. */
1354                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1355         }
1356
1357         /*
1358          * The BD ring replenish thresholds control how often the
1359          * hardware fetches new BD's from the producer rings in host
1360          * memory.  Setting the value too low on a busy system can
1361          * starve the hardware and recue the throughpout.
1362          *
1363          * Set the BD ring replentish thresholds. The recommended
1364          * values are 1/8th the number of descriptors allocated to
1365          * each ring.
1366          */
1367         val = 8;
1368         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1369         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1370                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1371                     BGE_JUMBO_RX_RING_CNT/8);
1372         }
1373         if (BNX_IS_57765_PLUS(sc)) {
1374                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1375                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1376         }
1377
1378         /*
1379          * Disable all send rings by setting the 'ring disabled' bit
1380          * in the flags field of all the TX send ring control blocks,
1381          * located in NIC memory.
1382          */
1383         if (BNX_IS_5717_PLUS(sc))
1384                 limit = 4;
1385         else if (BNX_IS_57765_FAMILY(sc) ||
1386             sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1387                 limit = 2;
1388         else
1389                 limit = 1;
1390         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1391         for (i = 0; i < limit; i++) {
1392                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1393                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1394                 vrcb += sizeof(struct bge_rcb);
1395         }
1396
1397         /*
1398          * Configure send ring RCBs
1399          */
1400         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1401         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
1402                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
1403
1404                 BGE_HOSTADDR(taddr, txr->bnx_tx_ring_paddr);
1405                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi,
1406                     taddr.bge_addr_hi);
1407                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo,
1408                     taddr.bge_addr_lo);
1409                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1410                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1411                 vrcb += sizeof(struct bge_rcb);
1412         }
1413
1414         /*
1415          * Disable all receive return rings by setting the
1416          * 'ring disabled' bit in the flags field of all the receive
1417          * return ring control blocks, located in NIC memory.
1418          */
1419         if (BNX_IS_5717_PLUS(sc)) {
1420                 /* Should be 17, use 16 until we get an SRAM map. */
1421                 limit = 16;
1422         } else if (BNX_IS_57765_FAMILY(sc) ||
1423             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1424                 limit = 4;
1425         } else {
1426                 limit = 1;
1427         }
1428         /* Disable all receive return rings. */
1429         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1430         for (i = 0; i < limit; i++) {
1431                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1432                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1433                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1434                     BGE_RCB_FLAG_RING_DISABLED);
1435                 bnx_writembx(sc, BGE_MBX_RX_CONS0_LO +
1436                     (i * (sizeof(uint64_t))), 0);
1437                 vrcb += sizeof(struct bge_rcb);
1438         }
1439
1440         /*
1441          * Set up receive return rings.  Note that the NIC address
1442          * for RX return rings is 0x0.  The return rings live entirely
1443          * within the host, so the nicaddr field in the RCB isn't used.
1444          */
1445         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1446         for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
1447                 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i];
1448
1449                 BGE_HOSTADDR(taddr, ret->bnx_rx_ret_ring_paddr);
1450                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi,
1451                     taddr.bge_addr_hi);
1452                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo,
1453                     taddr.bge_addr_lo);
1454                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1455                     BGE_RCB_MAXLEN_FLAGS(BNX_RETURN_RING_CNT, 0));
1456                 vrcb += sizeof(struct bge_rcb);
1457         }
1458
1459         /* Set random backoff seed for TX */
1460         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1461             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1462             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1463             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1464             BGE_TX_BACKOFF_SEED_MASK);
1465
1466         /* Set inter-packet gap */
1467         val = 0x2620;
1468         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1469             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1470                 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
1471                     (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
1472         }
1473         CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
1474
1475         /*
1476          * Specify which ring to use for packets that don't match
1477          * any RX rules.
1478          */
1479         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1480
1481         /*
1482          * Configure number of RX lists. One interrupt distribution
1483          * list, sixteen active lists, one bad frames class.
1484          */
1485         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1486
1487         /* Inialize RX list placement stats mask. */
1488         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1489         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1490
1491         /* Disable host coalescing until we get it set up */
1492         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1493
1494         /* Poll to make sure it's shut down. */
1495         for (i = 0; i < BNX_TIMEOUT; i++) {
1496                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1497                         break;
1498                 DELAY(10);
1499         }
1500
1501         if (i == BNX_TIMEOUT) {
1502                 if_printf(&sc->arpcom.ac_if,
1503                           "host coalescing engine failed to idle\n");
1504                 return(ENXIO);
1505         }
1506
1507         /* Set up host coalescing defaults */
1508         sc->bnx_coal_chg = BNX_RX_COAL_TICKS_CHG |
1509             BNX_TX_COAL_TICKS_CHG |
1510             BNX_RX_COAL_BDS_CHG |
1511             BNX_TX_COAL_BDS_CHG |
1512             BNX_RX_COAL_BDS_INT_CHG |
1513             BNX_TX_COAL_BDS_INT_CHG;
1514         bnx_coal_change(sc);
1515
1516         /*
1517          * Set up addresses of status blocks
1518          */
1519         intr = &sc->bnx_intr_data[0];
1520         bzero(intr->bnx_status_block, BGE_STATUS_BLK_SZ);
1521         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1522             BGE_ADDR_HI(intr->bnx_status_block_paddr));
1523         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1524             BGE_ADDR_LO(intr->bnx_status_block_paddr));
1525         for (i = 1; i < sc->bnx_intr_cnt; ++i) {
1526                 intr = &sc->bnx_intr_data[i];
1527                 bzero(intr->bnx_status_block, BGE_STATUS_BLK_SZ);
1528                 CSR_WRITE_4(sc, BGE_VEC1_STATUSBLK_ADDR_HI + ((i - 1) * 8),
1529                     BGE_ADDR_HI(intr->bnx_status_block_paddr));
1530                 CSR_WRITE_4(sc, BGE_VEC1_STATUSBLK_ADDR_LO + ((i - 1) * 8),
1531                     BGE_ADDR_LO(intr->bnx_status_block_paddr));
1532         }
1533
1534         /* Set up status block partail update size. */
1535         val = BGE_STATBLKSZ_32BYTE;
1536 #if 0
1537         /*
1538          * Does not seem to have visible effect in both
1539          * bulk data (1472B UDP datagram) and tiny data
1540          * (18B UDP datagram) TX tests.
1541          */
1542         val |= BGE_HCCMODE_CLRTICK_TX;
1543 #endif
1544         /* Turn on host coalescing state machine */
1545         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1546
1547         /* Turn on RX BD completion state machine and enable attentions */
1548         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1549             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1550
1551         /* Turn on RX list placement state machine */
1552         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1553
1554         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1555             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1556             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1557             BGE_MACMODE_FRMHDR_DMA_ENB;
1558
1559         if (sc->bnx_flags & BNX_FLAG_TBI)
1560                 val |= BGE_PORTMODE_TBI;
1561         else if (sc->bnx_flags & BNX_FLAG_MII_SERDES)
1562                 val |= BGE_PORTMODE_GMII;
1563         else
1564                 val |= BGE_PORTMODE_MII;
1565
1566         /* Turn on DMA, clear stats */
1567         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1568
1569         /* Set misc. local control, enable interrupts on attentions */
1570         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1571
1572 #ifdef notdef
1573         /* Assert GPIO pins for PHY reset */
1574         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1575             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1576         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1577             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1578 #endif
1579
1580         if (sc->bnx_intr_type == PCI_INTR_TYPE_MSIX)
1581                 bnx_enable_msi(sc, TRUE);
1582
1583         /* Turn on write DMA state machine */
1584         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1585         /* Enable host coalescing bug fix. */
1586         val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1587         if (sc->bnx_asicrev == BGE_ASICREV_BCM5785) {
1588                 /* Request larger DMA burst size to get better performance. */
1589                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1590         }
1591         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1592         DELAY(40);
1593
1594         if (BNX_IS_57765_PLUS(sc)) {
1595                 uint32_t dmactl, dmactl_reg;
1596
1597                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1598                         dmactl_reg = BGE_RDMA_RSRVCTRL2;
1599                 else
1600                         dmactl_reg = BGE_RDMA_RSRVCTRL;
1601
1602                 dmactl = CSR_READ_4(sc, dmactl_reg);
1603                 /*
1604                  * Adjust tx margin to prevent TX data corruption and
1605                  * fix internal FIFO overflow.
1606                  */
1607                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1608                     sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1609                     sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1610                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
1611                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
1612                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
1613                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
1614                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
1615                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
1616                 }
1617                 /*
1618                  * Enable fix for read DMA FIFO overruns.
1619                  * The fix is to limit the number of RX BDs
1620                  * the hardware would fetch at a fime.
1621                  */
1622                 CSR_WRITE_4(sc, dmactl_reg,
1623                     dmactl | BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1624         }
1625
1626         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719) {
1627                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1628                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1629                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
1630                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1631         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1632             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1633                 uint32_t ctrl_reg;
1634
1635                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1636                         ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL2;
1637                 else
1638                         ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL;
1639
1640                 /*
1641                  * Allow 4KB burst length reads for non-LSO frames.
1642                  * Enable 512B burst length reads for buffer descriptors.
1643                  */
1644                 CSR_WRITE_4(sc, ctrl_reg,
1645                     CSR_READ_4(sc, ctrl_reg) |
1646                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
1647                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1648         }
1649
1650         /* Turn on read DMA state machine */
1651         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1652         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717)
1653                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
1654         if (sc->bnx_asicrev == BGE_ASICREV_BCM5784 ||
1655             sc->bnx_asicrev == BGE_ASICREV_BCM5785 ||
1656             sc->bnx_asicrev == BGE_ASICREV_BCM57780) {
1657                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1658                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1659                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1660         }
1661         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1662             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1663                 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
1664                     BGE_RDMAMODE_H2BNC_VLAN_DET;
1665                 /*
1666                  * Allow multiple outstanding read requests from
1667                  * non-LSO read DMA engine.
1668                  */
1669                 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
1670         }
1671         if (sc->bnx_asicrev == BGE_ASICREV_BCM57766)
1672                 val |= BGE_RDMAMODE_JMB_2K_MMRR;
1673         if (sc->bnx_flags & BNX_FLAG_TSO)
1674                 val |= BGE_RDMAMODE_TSO4_ENABLE;
1675         val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1676         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1677         DELAY(40);
1678
1679         /* Turn on RX data completion state machine */
1680         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1681
1682         /* Turn on RX BD initiator state machine */
1683         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1684
1685         /* Turn on RX data and RX BD initiator state machine */
1686         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1687
1688         /* Turn on send BD completion state machine */
1689         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1690
1691         /* Turn on send data completion state machine */
1692         val = BGE_SDCMODE_ENABLE;
1693         if (sc->bnx_asicrev == BGE_ASICREV_BCM5761)
1694                 val |= BGE_SDCMODE_CDELAY; 
1695         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1696
1697         /* Turn on send data initiator state machine */
1698         if (sc->bnx_flags & BNX_FLAG_TSO) {
1699                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
1700                     BGE_SDIMODE_HW_LSO_PRE_DMA);
1701         } else {
1702                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1703         }
1704
1705         /* Turn on send BD initiator state machine */
1706         val = BGE_SBDIMODE_ENABLE;
1707         if (sc->bnx_tx_ringcnt > 1)
1708                 val |= BGE_SBDIMODE_MULTI_TXR;
1709         CSR_WRITE_4(sc, BGE_SBDI_MODE, val);
1710
1711         /* Turn on send BD selector state machine */
1712         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1713
1714         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1715         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1716             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1717
1718         /* ack/clear link change events */
1719         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1720             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1721             BGE_MACSTAT_LINK_CHANGED);
1722         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1723
1724         /*
1725          * Enable attention when the link has changed state for
1726          * devices that use auto polling.
1727          */
1728         if (sc->bnx_flags & BNX_FLAG_TBI) {
1729                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1730         } else {
1731                 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1732                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
1733                         DELAY(80);
1734                 }
1735         }
1736
1737         /*
1738          * Clear any pending link state attention.
1739          * Otherwise some link state change events may be lost until attention
1740          * is cleared by bnx_intr() -> bnx_softc.bnx_link_upd() sequence.
1741          * It's not necessary on newer BCM chips - perhaps enabling link
1742          * state change attentions implies clearing pending attention.
1743          */
1744         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1745             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1746             BGE_MACSTAT_LINK_CHANGED);
1747
1748         /* Enable link state change attentions. */
1749         BNX_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1750
1751         return(0);
1752 }
1753
1754 /*
1755  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1756  * against our list and return its name if we find a match. Note
1757  * that since the Broadcom controller contains VPD support, we
1758  * can get the device name string from the controller itself instead
1759  * of the compiled-in string. This is a little slow, but it guarantees
1760  * we'll always announce the right product name.
1761  */
1762 static int
1763 bnx_probe(device_t dev)
1764 {
1765         const struct bnx_type *t;
1766         uint16_t product, vendor;
1767
1768         if (!pci_is_pcie(dev))
1769                 return ENXIO;
1770
1771         product = pci_get_device(dev);
1772         vendor = pci_get_vendor(dev);
1773
1774         for (t = bnx_devs; t->bnx_name != NULL; t++) {
1775                 if (vendor == t->bnx_vid && product == t->bnx_did)
1776                         break;
1777         }
1778         if (t->bnx_name == NULL)
1779                 return ENXIO;
1780
1781         device_set_desc(dev, t->bnx_name);
1782         return 0;
1783 }
1784
1785 static int
1786 bnx_attach(device_t dev)
1787 {
1788         struct ifnet *ifp;
1789         struct bnx_softc *sc;
1790         struct bnx_rx_std_ring *std;
1791         uint32_t hwcfg = 0;
1792         int error = 0, rid, capmask, i, std_cpuid, std_cpuid_def;
1793         uint8_t ether_addr[ETHER_ADDR_LEN];
1794         uint16_t product;
1795         uintptr_t mii_priv = 0;
1796 #if defined(BNX_TSO_DEBUG) || defined(BNX_RSS_DEBUG) || defined(BNX_TSS_DEBUG)
1797         char desc[32];
1798 #endif
1799 #ifdef IFPOLL_ENABLE
1800         int offset, offset_def;
1801 #endif
1802
1803         sc = device_get_softc(dev);
1804         sc->bnx_dev = dev;
1805         callout_init_mp(&sc->bnx_tick_timer);
1806         lwkt_serialize_init(&sc->bnx_jslot_serializer);
1807         lwkt_serialize_init(&sc->bnx_main_serialize);
1808
1809         /* Always setup interrupt mailboxes */
1810         for (i = 0; i < BNX_INTR_MAX; ++i) {
1811                 callout_init_mp(&sc->bnx_intr_data[i].bnx_intr_timer);
1812                 sc->bnx_intr_data[i].bnx_sc = sc;
1813                 sc->bnx_intr_data[i].bnx_intr_mbx = BGE_MBX_IRQ0_LO + (i * 8);
1814                 sc->bnx_intr_data[i].bnx_intr_rid = -1;
1815                 sc->bnx_intr_data[i].bnx_intr_cpuid = -1;
1816         }
1817
1818         product = pci_get_device(dev);
1819
1820 #ifndef BURN_BRIDGES
1821         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1822                 uint32_t irq, mem;
1823
1824                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1825                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1826
1827                 device_printf(dev, "chip is in D%d power mode "
1828                     "-- setting to D0\n", pci_get_powerstate(dev));
1829
1830                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1831
1832                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1833                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1834         }
1835 #endif  /* !BURN_BRIDGE */
1836
1837         /*
1838          * Map control/status registers.
1839          */
1840         pci_enable_busmaster(dev);
1841
1842         rid = BGE_PCI_BAR0;
1843         sc->bnx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1844             RF_ACTIVE);
1845
1846         if (sc->bnx_res == NULL) {
1847                 device_printf(dev, "couldn't map memory\n");
1848                 return ENXIO;
1849         }
1850
1851         sc->bnx_btag = rman_get_bustag(sc->bnx_res);
1852         sc->bnx_bhandle = rman_get_bushandle(sc->bnx_res);
1853
1854         /* Save various chip information */
1855         sc->bnx_chipid =
1856             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1857             BGE_PCIMISCCTL_ASICREV_SHIFT;
1858         if (BGE_ASICREV(sc->bnx_chipid) == BGE_ASICREV_USE_PRODID_REG) {
1859                 /* All chips having dedicated ASICREV register have CPMU */
1860                 sc->bnx_flags |= BNX_FLAG_CPMU;
1861
1862                 switch (product) {
1863                 case PCI_PRODUCT_BROADCOM_BCM5717:
1864                 case PCI_PRODUCT_BROADCOM_BCM5717C:
1865                 case PCI_PRODUCT_BROADCOM_BCM5718:
1866                 case PCI_PRODUCT_BROADCOM_BCM5719:
1867                 case PCI_PRODUCT_BROADCOM_BCM5720_ALT:
1868                 case PCI_PRODUCT_BROADCOM_BCM5725:
1869                 case PCI_PRODUCT_BROADCOM_BCM5727:
1870                 case PCI_PRODUCT_BROADCOM_BCM5762:
1871                         sc->bnx_chipid = pci_read_config(dev,
1872                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
1873                         break;
1874
1875                 case PCI_PRODUCT_BROADCOM_BCM57761:
1876                 case PCI_PRODUCT_BROADCOM_BCM57762:
1877                 case PCI_PRODUCT_BROADCOM_BCM57765:
1878                 case PCI_PRODUCT_BROADCOM_BCM57766:
1879                 case PCI_PRODUCT_BROADCOM_BCM57781:
1880                 case PCI_PRODUCT_BROADCOM_BCM57782:
1881                 case PCI_PRODUCT_BROADCOM_BCM57785:
1882                 case PCI_PRODUCT_BROADCOM_BCM57786:
1883                 case PCI_PRODUCT_BROADCOM_BCM57791:
1884                 case PCI_PRODUCT_BROADCOM_BCM57795:
1885                         sc->bnx_chipid = pci_read_config(dev,
1886                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
1887                         break;
1888
1889                 default:
1890                         sc->bnx_chipid = pci_read_config(dev,
1891                             BGE_PCI_PRODID_ASICREV, 4);
1892                         break;
1893                 }
1894         }
1895         if (sc->bnx_chipid == BGE_CHIPID_BCM5717_C0)
1896                 sc->bnx_chipid = BGE_CHIPID_BCM5720_A0;
1897
1898         sc->bnx_asicrev = BGE_ASICREV(sc->bnx_chipid);
1899         sc->bnx_chiprev = BGE_CHIPREV(sc->bnx_chipid);
1900
1901         switch (sc->bnx_asicrev) {
1902         case BGE_ASICREV_BCM5717:
1903         case BGE_ASICREV_BCM5719:
1904         case BGE_ASICREV_BCM5720:
1905                 sc->bnx_flags |= BNX_FLAG_5717_PLUS | BNX_FLAG_57765_PLUS;
1906                 break;
1907
1908         case BGE_ASICREV_BCM5762:
1909                 sc->bnx_flags |= BNX_FLAG_57765_PLUS;
1910                 break;
1911
1912         case BGE_ASICREV_BCM57765:
1913         case BGE_ASICREV_BCM57766:
1914                 sc->bnx_flags |= BNX_FLAG_57765_FAMILY | BNX_FLAG_57765_PLUS;
1915                 break;
1916         }
1917
1918         sc->bnx_flags |= BNX_FLAG_TSO;
1919         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 &&
1920             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0)
1921                 sc->bnx_flags &= ~BNX_FLAG_TSO;
1922
1923         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1924             BNX_IS_57765_FAMILY(sc)) {
1925                 /*
1926                  * All BCM57785 and BCM5718 families chips have a bug that
1927                  * under certain situation interrupt will not be enabled
1928                  * even if status tag is written to interrupt mailbox.
1929                  *
1930                  * While BCM5719 and BCM5720 have a hardware workaround
1931                  * which could fix the above bug.
1932                  * See the comment near BGE_PCIDMARWCTL_TAGGED_STATUS_WA in
1933                  * bnx_chipinit().
1934                  *
1935                  * For the rest of the chips in these two families, we will
1936                  * have to poll the status block at high rate (10ms currently)
1937                  * to check whether the interrupt is hosed or not.
1938                  * See bnx_check_intr_*() for details.
1939                  */
1940                 sc->bnx_flags |= BNX_FLAG_STATUSTAG_BUG;
1941         }
1942
1943         sc->bnx_pciecap = pci_get_pciecap_ptr(sc->bnx_dev);
1944         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1945             sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1946                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_2048);
1947         else
1948                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1949         device_printf(dev, "CHIP ID 0x%08x; "
1950                       "ASIC REV 0x%02x; CHIP REV 0x%02x\n",
1951                       sc->bnx_chipid, sc->bnx_asicrev, sc->bnx_chiprev);
1952
1953         /*
1954          * Set various PHY quirk flags.
1955          */
1956
1957         capmask = MII_CAPMASK_DEFAULT;
1958         if (product == PCI_PRODUCT_BROADCOM_BCM57791 ||
1959             product == PCI_PRODUCT_BROADCOM_BCM57795) {
1960                 /* 10/100 only */
1961                 capmask &= ~BMSR_EXTSTAT;
1962         }
1963
1964         mii_priv |= BRGPHY_FLAG_WIRESPEED;
1965         if (sc->bnx_chipid == BGE_CHIPID_BCM5762_A0)
1966                 mii_priv |= BRGPHY_FLAG_5762_A0;
1967
1968         /* Initialize if_name earlier, so if_printf could be used */
1969         ifp = &sc->arpcom.ac_if;
1970         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1971
1972         /* Try to reset the chip. */
1973         bnx_reset(sc);
1974
1975         if (bnx_chipinit(sc)) {
1976                 device_printf(dev, "chip initialization failed\n");
1977                 error = ENXIO;
1978                 goto fail;
1979         }
1980
1981         /*
1982          * Get station address
1983          */
1984         error = bnx_get_eaddr(sc, ether_addr);
1985         if (error) {
1986                 device_printf(dev, "failed to read station address\n");
1987                 goto fail;
1988         }
1989
1990         /* Setup RX/TX and interrupt count */
1991         bnx_setup_ring_cnt(sc);
1992
1993         if ((sc->bnx_rx_retcnt == 1 && sc->bnx_tx_ringcnt == 1) ||
1994             (sc->bnx_rx_retcnt > 1 && sc->bnx_tx_ringcnt > 1)) {
1995                 /*
1996                  * The RX ring and the corresponding TX ring processing
1997                  * should be on the same CPU, since they share the same
1998                  * status block.
1999                  */
2000                 sc->bnx_flags |= BNX_FLAG_RXTX_BUNDLE;
2001                 if (bootverbose)
2002                         device_printf(dev, "RX/TX bundle\n");
2003                 if (sc->bnx_tx_ringcnt > 1) {
2004                         /*
2005                          * Multiple TX rings do not share status block
2006                          * with link status, so link status will have
2007                          * to save its own status_tag.
2008                          */
2009                         sc->bnx_flags |= BNX_FLAG_STATUS_HASTAG;
2010                         if (bootverbose)
2011                                 device_printf(dev, "status needs tag\n");
2012                 }
2013         } else {
2014                 KKASSERT(sc->bnx_rx_retcnt > 1 && sc->bnx_tx_ringcnt == 1);
2015                 if (bootverbose)
2016                         device_printf(dev, "RX/TX not bundled\n");
2017         }
2018
2019         error = bnx_dma_alloc(dev);
2020         if (error)
2021                 goto fail;
2022
2023 #ifdef IFPOLL_ENABLE
2024         if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) {
2025                 /*
2026                  * NPOLLING RX/TX CPU offset
2027                  */
2028                 if (sc->bnx_rx_retcnt == ncpus2) {
2029                         offset = 0;
2030                 } else {
2031                         offset_def =
2032                         (sc->bnx_rx_retcnt * device_get_unit(dev)) % ncpus2;
2033                         offset = device_getenv_int(dev, "npoll.offset",
2034                             offset_def);
2035                         if (offset >= ncpus2 ||
2036                             offset % sc->bnx_rx_retcnt != 0) {
2037                                 device_printf(dev, "invalid npoll.offset %d, "
2038                                     "use %d\n", offset, offset_def);
2039                                 offset = offset_def;
2040                         }
2041                 }
2042                 sc->bnx_npoll_rxoff = offset;
2043                 sc->bnx_npoll_txoff = offset;
2044         } else {
2045                 /*
2046                  * NPOLLING RX CPU offset
2047                  */
2048                 if (sc->bnx_rx_retcnt == ncpus2) {
2049                         offset = 0;
2050                 } else {
2051                         offset_def =
2052                         (sc->bnx_rx_retcnt * device_get_unit(dev)) % ncpus2;
2053                         offset = device_getenv_int(dev, "npoll.rxoff",
2054                             offset_def);
2055                         if (offset >= ncpus2 ||
2056                             offset % sc->bnx_rx_retcnt != 0) {
2057                                 device_printf(dev, "invalid npoll.rxoff %d, "
2058                                     "use %d\n", offset, offset_def);
2059                                 offset = offset_def;
2060                         }
2061                 }
2062                 sc->bnx_npoll_rxoff = offset;
2063
2064                 /*
2065                  * NPOLLING TX CPU offset
2066                  */
2067                 offset_def = device_get_unit(dev) % ncpus2;
2068                 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
2069                 if (offset >= ncpus2) {
2070                         device_printf(dev, "invalid npoll.txoff %d, use %d\n",
2071                             offset, offset_def);
2072                         offset = offset_def;
2073                 }
2074                 sc->bnx_npoll_txoff = offset;
2075         }
2076 #endif  /* IFPOLL_ENABLE */
2077
2078         /*
2079          * Allocate interrupt
2080          */
2081         error = bnx_alloc_intr(sc);
2082         if (error)
2083                 goto fail;
2084
2085         /* Setup serializers */
2086         bnx_setup_serialize(sc);
2087
2088         /* Set default tuneable values. */
2089         sc->bnx_rx_coal_ticks = BNX_RX_COAL_TICKS_DEF;
2090         sc->bnx_tx_coal_ticks = BNX_TX_COAL_TICKS_DEF;
2091         sc->bnx_rx_coal_bds = BNX_RX_COAL_BDS_DEF;
2092         sc->bnx_tx_coal_bds = BNX_TX_COAL_BDS_DEF;
2093         sc->bnx_rx_coal_bds_int = BNX_RX_COAL_BDS_INT_DEF;
2094         sc->bnx_tx_coal_bds_int = BNX_TX_COAL_BDS_INT_DEF;
2095
2096         /* Set up ifnet structure */
2097         ifp->if_softc = sc;
2098         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2099         ifp->if_ioctl = bnx_ioctl;
2100         ifp->if_start = bnx_start;
2101 #ifdef IFPOLL_ENABLE
2102         ifp->if_npoll = bnx_npoll;
2103 #endif
2104         ifp->if_init = bnx_init;
2105         ifp->if_serialize = bnx_serialize;
2106         ifp->if_deserialize = bnx_deserialize;
2107         ifp->if_tryserialize = bnx_tryserialize;
2108 #ifdef INVARIANTS
2109         ifp->if_serialize_assert = bnx_serialize_assert;
2110 #endif
2111         ifp->if_mtu = ETHERMTU;
2112         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2113
2114         ifp->if_capabilities |= IFCAP_HWCSUM;
2115         ifp->if_hwassist = BNX_CSUM_FEATURES;
2116         if (sc->bnx_flags & BNX_FLAG_TSO) {
2117                 ifp->if_capabilities |= IFCAP_TSO;
2118                 ifp->if_hwassist |= CSUM_TSO;
2119         }
2120         ifp->if_capenable = ifp->if_capabilities;
2121
2122         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2123         ifq_set_ready(&ifp->if_snd);
2124         ifq_set_subq_cnt(&ifp->if_snd, sc->bnx_tx_ringcnt);
2125
2126         if (sc->bnx_tx_ringcnt > 1) {
2127                 ifp->if_mapsubq = ifq_mapsubq_mask;
2128                 ifq_set_subq_mask(&ifp->if_snd, sc->bnx_tx_ringcnt - 1);
2129         }
2130
2131         /*
2132          * Figure out what sort of media we have by checking the
2133          * hardware config word in the first 32k of NIC internal memory,
2134          * or fall back to examining the EEPROM if necessary.
2135          * Note: on some BCM5700 cards, this value appears to be unset.
2136          * If that's the case, we have to rely on identifying the NIC
2137          * by its PCI subsystem ID, as we do below for the SysKonnect
2138          * SK-9D41.
2139          */
2140         if (bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
2141                 hwcfg = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2142         } else {
2143                 if (bnx_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2144                                     sizeof(hwcfg))) {
2145                         device_printf(dev, "failed to read EEPROM\n");
2146                         error = ENXIO;
2147                         goto fail;
2148                 }
2149                 hwcfg = ntohl(hwcfg);
2150         }
2151
2152         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2153         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2154             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2155                 sc->bnx_flags |= BNX_FLAG_TBI;
2156
2157         /* Setup MI MODE */
2158         if (sc->bnx_flags & BNX_FLAG_CPMU)
2159                 sc->bnx_mi_mode = BGE_MIMODE_500KHZ_CONST;
2160         else
2161                 sc->bnx_mi_mode = BGE_MIMODE_BASE;
2162
2163         /* Setup link status update stuffs */
2164         if (sc->bnx_flags & BNX_FLAG_TBI) {
2165                 sc->bnx_link_upd = bnx_tbi_link_upd;
2166                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2167         } else if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
2168                 sc->bnx_link_upd = bnx_autopoll_link_upd;
2169                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2170         } else {
2171                 sc->bnx_link_upd = bnx_copper_link_upd;
2172                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2173         }
2174
2175         /* Set default PHY address */
2176         sc->bnx_phyno = 1;
2177
2178         /*
2179          * PHY address mapping for various devices.
2180          *
2181          *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
2182          * ---------+-------+-------+-------+-------+
2183          * BCM57XX  |   1   |   X   |   X   |   X   |
2184          * BCM5704  |   1   |   X   |   1   |   X   |
2185          * BCM5717  |   1   |   8   |   2   |   9   |
2186          * BCM5719  |   1   |   8   |   2   |   9   |
2187          * BCM5720  |   1   |   8   |   2   |   9   |
2188          *
2189          * Other addresses may respond but they are not
2190          * IEEE compliant PHYs and should be ignored.
2191          */
2192         if (BNX_IS_5717_PLUS(sc)) {
2193                 int f;
2194
2195                 f = pci_get_function(dev);
2196                 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_A0) {
2197                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
2198                             BGE_SGDIGSTS_IS_SERDES)
2199                                 sc->bnx_phyno = f + 8;
2200                         else
2201                                 sc->bnx_phyno = f + 1;
2202                 } else {
2203                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
2204                             BGE_CPMU_PHY_STRAP_IS_SERDES)
2205                                 sc->bnx_phyno = f + 8;
2206                         else
2207                                 sc->bnx_phyno = f + 1;
2208                 }
2209         }
2210
2211         if (sc->bnx_flags & BNX_FLAG_TBI) {
2212                 ifmedia_init(&sc->bnx_ifmedia, IFM_IMASK,
2213                     bnx_ifmedia_upd, bnx_ifmedia_sts);
2214                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2215                 ifmedia_add(&sc->bnx_ifmedia,
2216                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2217                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2218                 ifmedia_set(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO);
2219                 sc->bnx_ifmedia.ifm_media = sc->bnx_ifmedia.ifm_cur->ifm_media;
2220         } else {
2221                 struct mii_probe_args mii_args;
2222
2223                 mii_probe_args_init(&mii_args, bnx_ifmedia_upd, bnx_ifmedia_sts);
2224                 mii_args.mii_probemask = 1 << sc->bnx_phyno;
2225                 mii_args.mii_capmask = capmask;
2226                 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2227                 mii_args.mii_priv = mii_priv;
2228
2229                 error = mii_probe(dev, &sc->bnx_miibus, &mii_args);
2230                 if (error) {
2231                         device_printf(dev, "MII without any PHY!\n");
2232                         goto fail;
2233                 }
2234         }
2235
2236         /*
2237          * Create sysctl nodes.
2238          */
2239         sysctl_ctx_init(&sc->bnx_sysctl_ctx);
2240         sc->bnx_sysctl_tree = SYSCTL_ADD_NODE(&sc->bnx_sysctl_ctx,
2241                                               SYSCTL_STATIC_CHILDREN(_hw),
2242                                               OID_AUTO,
2243                                               device_get_nameunit(dev),
2244                                               CTLFLAG_RD, 0, "");
2245         if (sc->bnx_sysctl_tree == NULL) {
2246                 device_printf(dev, "can't add sysctl node\n");
2247                 error = ENXIO;
2248                 goto fail;
2249         }
2250
2251         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2252             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2253             "rx_rings", CTLFLAG_RD, &sc->bnx_rx_retcnt, 0, "# of RX rings");
2254         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2255             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2256             "tx_rings", CTLFLAG_RD, &sc->bnx_tx_ringcnt, 0, "# of TX rings");
2257
2258         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2259                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2260                         OID_AUTO, "rx_coal_ticks",
2261                         CTLTYPE_INT | CTLFLAG_RW,
2262                         sc, 0, bnx_sysctl_rx_coal_ticks, "I",
2263                         "Receive coalescing ticks (usec).");
2264         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2265                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2266                         OID_AUTO, "tx_coal_ticks",
2267                         CTLTYPE_INT | CTLFLAG_RW,
2268                         sc, 0, bnx_sysctl_tx_coal_ticks, "I",
2269                         "Transmit coalescing ticks (usec).");
2270         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2271                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2272                         OID_AUTO, "rx_coal_bds",
2273                         CTLTYPE_INT | CTLFLAG_RW,
2274                         sc, 0, bnx_sysctl_rx_coal_bds, "I",
2275                         "Receive max coalesced BD count.");
2276         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2277                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2278                         OID_AUTO, "tx_coal_bds",
2279                         CTLTYPE_INT | CTLFLAG_RW,
2280                         sc, 0, bnx_sysctl_tx_coal_bds, "I",
2281                         "Transmit max coalesced BD count.");
2282         /*
2283          * A common design characteristic for many Broadcom
2284          * client controllers is that they only support a
2285          * single outstanding DMA read operation on the PCIe
2286          * bus. This means that it will take twice as long to
2287          * fetch a TX frame that is split into header and
2288          * payload buffers as it does to fetch a single,
2289          * contiguous TX frame (2 reads vs. 1 read). For these
2290          * controllers, coalescing buffers to reduce the number
2291          * of memory reads is effective way to get maximum
2292          * performance(about 940Mbps).  Without collapsing TX
2293          * buffers the maximum TCP bulk transfer performance
2294          * is about 850Mbps. However forcing coalescing mbufs
2295          * consumes a lot of CPU cycles, so leave it off by
2296          * default.
2297          */
2298         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2299             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2300             "force_defrag", CTLTYPE_INT | CTLFLAG_RW,
2301             sc, 0, bnx_sysctl_force_defrag, "I",
2302             "Force defragment on TX path");
2303
2304         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2305             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2306             "tx_wreg", CTLTYPE_INT | CTLFLAG_RW,
2307             sc, 0, bnx_sysctl_tx_wreg, "I",
2308             "# of segments before writing to hardware register");
2309
2310         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2311             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2312             "std_refill", CTLTYPE_INT | CTLFLAG_RW,
2313             sc, 0, bnx_sysctl_std_refill, "I",
2314             "# of packets received before scheduling standard refilling");
2315
2316         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2317             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2318             "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2319             sc, 0, bnx_sysctl_rx_coal_bds_int, "I",
2320             "Receive max coalesced BD count during interrupt.");
2321         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2322             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2323             "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2324             sc, 0, bnx_sysctl_tx_coal_bds_int, "I",
2325             "Transmit max coalesced BD count during interrupt.");
2326
2327 #ifdef IFPOLL_ENABLE
2328         if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) {
2329                 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2330                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2331                     "npoll_offset", CTLTYPE_INT | CTLFLAG_RW,
2332                     sc, 0, bnx_sysctl_npoll_offset, "I",
2333                     "NPOLLING cpu offset");
2334         } else {
2335                 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2336                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2337                     "npoll_rxoff", CTLTYPE_INT | CTLFLAG_RW,
2338                     sc, 0, bnx_sysctl_npoll_rxoff, "I",
2339                     "NPOLLING RX cpu offset");
2340                 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2341                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2342                     "npoll_txoff", CTLTYPE_INT | CTLFLAG_RW,
2343                     sc, 0, bnx_sysctl_npoll_txoff, "I",
2344                     "NPOLLING TX cpu offset");
2345         }
2346 #endif
2347
2348 #ifdef BNX_RSS_DEBUG
2349         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2350             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2351             "std_refill_mask", CTLFLAG_RD,
2352             &sc->bnx_rx_std_ring.bnx_rx_std_refill, 0, "");
2353         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2354             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2355             "rss_debug", CTLFLAG_RW, &sc->bnx_rss_debug, 0, "");
2356         for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
2357                 ksnprintf(desc, sizeof(desc), "rx_pkt%d", i);
2358                 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2359                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2360                     desc, CTLFLAG_RW, &sc->bnx_rx_ret_ring[i].bnx_rx_pkt, "");
2361         }
2362 #endif
2363 #ifdef BNX_TSS_DEBUG
2364         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
2365                 ksnprintf(desc, sizeof(desc), "tx_pkt%d", i);
2366                 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2367                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2368                     desc, CTLFLAG_RW, &sc->bnx_tx_ring[i].bnx_tx_pkt, "");
2369         }
2370 #endif
2371
2372         SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2373             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2374             "norxbds", CTLFLAG_RW, &sc->bnx_norxbds, "");
2375
2376         SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2377             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2378             "errors", CTLFLAG_RW, &sc->bnx_errors, "");
2379
2380 #ifdef BNX_TSO_DEBUG
2381         for (i = 0; i < BNX_TSO_NSTATS; ++i) {
2382                 ksnprintf(desc, sizeof(desc), "tso%d", i + 1);
2383                 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2384                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2385                     desc, CTLFLAG_RW, &sc->bnx_tsosegs[i], "");
2386         }
2387 #endif
2388
2389         /*
2390          * Call MI attach routine.
2391          */
2392         ether_ifattach(ifp, ether_addr, NULL);
2393
2394         /* Setup TX rings and subqueues */
2395         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
2396                 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i);
2397                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
2398
2399                 ifsq_set_cpuid(ifsq, txr->bnx_tx_cpuid);
2400                 ifsq_set_hw_serialize(ifsq, &txr->bnx_tx_serialize);
2401                 ifsq_set_priv(ifsq, txr);
2402                 txr->bnx_ifsq = ifsq;
2403
2404                 ifsq_watchdog_init(&txr->bnx_tx_watchdog, ifsq, bnx_watchdog);
2405
2406                 if (bootverbose) {
2407                         device_printf(dev, "txr %d -> cpu%d\n", i,
2408                             txr->bnx_tx_cpuid);
2409                 }
2410         }
2411
2412         error = bnx_setup_intr(sc);
2413         if (error) {
2414                 ether_ifdetach(ifp);
2415                 goto fail;
2416         }
2417         bnx_set_tick_cpuid(sc, FALSE);
2418
2419         /*
2420          * Create RX standard ring refilling thread
2421          */
2422         std_cpuid_def = device_get_unit(dev) % ncpus;
2423         std_cpuid = device_getenv_int(dev, "std.cpuid", std_cpuid_def);
2424         if (std_cpuid < 0 || std_cpuid >= ncpus) {
2425                 device_printf(dev, "invalid std.cpuid %d, use %d\n",
2426                     std_cpuid, std_cpuid_def);
2427                 std_cpuid = std_cpuid_def;
2428         }
2429
2430         std = &sc->bnx_rx_std_ring;
2431         lwkt_create(bnx_rx_std_refill_ithread, std, NULL,
2432             &std->bnx_rx_std_ithread, TDF_NOSTART | TDF_INTTHREAD, std_cpuid,
2433             "%s std", device_get_nameunit(dev));
2434         lwkt_setpri(&std->bnx_rx_std_ithread, TDPRI_INT_MED);
2435         std->bnx_rx_std_ithread.td_preemptable = lwkt_preempt;
2436         sc->bnx_flags |= BNX_FLAG_STD_THREAD;
2437
2438         return(0);
2439 fail:
2440         bnx_detach(dev);
2441         return(error);
2442 }
2443
2444 static int
2445 bnx_detach(device_t dev)
2446 {
2447         struct bnx_softc *sc = device_get_softc(dev);
2448
2449         if (device_is_attached(dev)) {
2450                 struct ifnet *ifp = &sc->arpcom.ac_if;
2451
2452                 ifnet_serialize_all(ifp);
2453                 bnx_stop(sc);
2454                 bnx_reset(sc);
2455                 bnx_teardown_intr(sc, sc->bnx_intr_cnt);
2456                 ifnet_deserialize_all(ifp);
2457
2458                 ether_ifdetach(ifp);
2459         }
2460
2461         if (sc->bnx_flags & BNX_FLAG_STD_THREAD) {
2462                 struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring;
2463
2464                 tsleep_interlock(std, 0);
2465
2466                 if (std->bnx_rx_std_ithread.td_gd == mycpu) {
2467                         bnx_rx_std_refill_stop(std);
2468                 } else {
2469                         lwkt_send_ipiq(std->bnx_rx_std_ithread.td_gd,
2470                             bnx_rx_std_refill_stop, std);
2471                 }
2472
2473                 tsleep(std, PINTERLOCKED, "bnx_detach", 0);
2474                 if (bootverbose)
2475                         device_printf(dev, "RX std ithread exited\n");
2476
2477                 lwkt_synchronize_ipiqs("bnx_detach_ipiq");
2478         }
2479
2480         if (sc->bnx_flags & BNX_FLAG_TBI)
2481                 ifmedia_removeall(&sc->bnx_ifmedia);
2482         if (sc->bnx_miibus)
2483                 device_delete_child(dev, sc->bnx_miibus);
2484         bus_generic_detach(dev);
2485
2486         bnx_free_intr(sc);
2487
2488         if (sc->bnx_msix_mem_res != NULL) {
2489                 bus_release_resource(dev, SYS_RES_MEMORY, sc->bnx_msix_mem_rid,
2490                     sc->bnx_msix_mem_res);
2491         }
2492         if (sc->bnx_res != NULL) {
2493                 bus_release_resource(dev, SYS_RES_MEMORY,
2494                     BGE_PCI_BAR0, sc->bnx_res);
2495         }
2496
2497         if (sc->bnx_sysctl_tree != NULL)
2498                 sysctl_ctx_free(&sc->bnx_sysctl_ctx);
2499
2500         bnx_dma_free(sc);
2501
2502         if (sc->bnx_serialize != NULL)
2503                 kfree(sc->bnx_serialize, M_DEVBUF);
2504
2505         return 0;
2506 }
2507
2508 static void
2509 bnx_reset(struct bnx_softc *sc)
2510 {
2511         device_t dev;
2512         uint32_t cachesize, command, pcistate, reset;
2513         void (*write_op)(struct bnx_softc *, uint32_t, uint32_t);
2514         int i, val = 0;
2515         uint16_t devctl;
2516
2517         dev = sc->bnx_dev;
2518
2519         write_op = bnx_writemem_direct;
2520
2521         /* Save some important PCI state. */
2522         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2523         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2524         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2525
2526         pci_write_config(dev, BGE_PCI_MISC_CTL,
2527             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2528             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2529             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2530
2531         /* Disable fastboot on controllers that support it. */
2532         if (bootverbose)
2533                 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2534         CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2535
2536         /*
2537          * Write the magic number to SRAM at offset 0xB50.
2538          * When firmware finishes its initialization it will
2539          * write ~BGE_MAGIC_NUMBER to the same location.
2540          */
2541         bnx_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2542
2543         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2544
2545         /* XXX: Broadcom Linux driver. */
2546         /* Force PCI-E 1.0a mode */
2547         if (!BNX_IS_57765_PLUS(sc) &&
2548             CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2549             (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2550              BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2551                 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2552                     BGE_PCIE_PHY_TSTCTL_PSCRAM);
2553         }
2554         if (sc->bnx_chipid != BGE_CHIPID_BCM5750_A0) {
2555                 /* Prevent PCIE link training during global reset */
2556                 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2557                 reset |= (1<<29);
2558         }
2559
2560         /* 
2561          * Set GPHY Power Down Override to leave GPHY
2562          * powered up in D0 uninitialized.
2563          */
2564         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0)
2565                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2566
2567         /* Issue global reset */
2568         write_op(sc, BGE_MISC_CFG, reset);
2569
2570         DELAY(1000);
2571
2572         /* XXX: Broadcom Linux driver. */
2573         if (sc->bnx_chipid == BGE_CHIPID_BCM5750_A0) {
2574                 uint32_t v;
2575
2576                 DELAY(500000); /* wait for link training to complete */
2577                 v = pci_read_config(dev, 0xc4, 4);
2578                 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2579         }
2580
2581         devctl = pci_read_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL, 2);
2582
2583         /* Disable no snoop and disable relaxed ordering. */
2584         devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2585
2586         /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2587         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0) {
2588                 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2589                 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2590         }
2591
2592         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL,
2593             devctl, 2);
2594
2595         /* Clear error status. */
2596         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVSTS,
2597             PCIEM_DEVSTS_CORR_ERR |
2598             PCIEM_DEVSTS_NFATAL_ERR |
2599             PCIEM_DEVSTS_FATAL_ERR |
2600             PCIEM_DEVSTS_UNSUPP_REQ, 2);
2601
2602         /* Reset some of the PCI state that got zapped by reset */
2603         pci_write_config(dev, BGE_PCI_MISC_CTL,
2604             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2605             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2606             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2607         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2608         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2609         write_op(sc, BGE_MISC_CFG, (65 << 1));
2610
2611         /* Enable memory arbiter */
2612         CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2613
2614         /*
2615          * Poll until we see the 1's complement of the magic number.
2616          * This indicates that the firmware initialization is complete.
2617          */
2618         for (i = 0; i < BNX_FIRMWARE_TIMEOUT; i++) {
2619                 val = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2620                 if (val == ~BGE_MAGIC_NUMBER)
2621                         break;
2622                 DELAY(10);
2623         }
2624         if (i == BNX_FIRMWARE_TIMEOUT) {
2625                 if_printf(&sc->arpcom.ac_if, "firmware handshake "
2626                           "timed out, found 0x%08x\n", val);
2627         }
2628
2629         /* BCM57765 A0 needs additional time before accessing. */
2630         if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
2631                 DELAY(10 * 1000);
2632
2633         /*
2634          * XXX Wait for the value of the PCISTATE register to
2635          * return to its original pre-reset state. This is a
2636          * fairly good indicator of reset completion. If we don't
2637          * wait for the reset to fully complete, trying to read
2638          * from the device's non-PCI registers may yield garbage
2639          * results.
2640          */
2641         for (i = 0; i < BNX_TIMEOUT; i++) {
2642                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2643                         break;
2644                 DELAY(10);
2645         }
2646
2647         /* Fix up byte swapping */
2648         CSR_WRITE_4(sc, BGE_MODE_CTL, bnx_dma_swap_options(sc));
2649
2650         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2651
2652         /*
2653          * The 5704 in TBI mode apparently needs some special
2654          * adjustment to insure the SERDES drive level is set
2655          * to 1.2V.
2656          */
2657         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704 &&
2658             (sc->bnx_flags & BNX_FLAG_TBI)) {
2659                 uint32_t serdescfg;
2660
2661                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2662                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2663                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2664         }
2665
2666         CSR_WRITE_4(sc, BGE_MI_MODE,
2667             sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
2668         DELAY(80);
2669
2670         /* XXX: Broadcom Linux driver. */
2671         if (!BNX_IS_57765_PLUS(sc)) {
2672                 uint32_t v;
2673
2674                 /* Enable Data FIFO protection. */
2675                 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
2676                 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
2677         }
2678
2679         DELAY(10000);
2680
2681         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
2682                 BNX_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
2683                     CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
2684         }
2685 }
2686
2687 /*
2688  * Frame reception handling. This is called if there's a frame
2689  * on the receive return list.
2690  *
2691  * Note: we have to be able to handle two possibilities here:
2692  * 1) the frame is from the jumbo recieve ring
2693  * 2) the frame is from the standard receive ring
2694  */
2695
2696 static void
2697 bnx_rxeof(struct bnx_rx_ret_ring *ret, uint16_t rx_prod, int count)
2698 {
2699         struct bnx_softc *sc = ret->bnx_sc;
2700         struct bnx_rx_std_ring *std = ret->bnx_std;
2701         struct ifnet *ifp = &sc->arpcom.ac_if;
2702
2703         while (ret->bnx_rx_saved_considx != rx_prod && count != 0) {
2704                 struct bge_rx_bd *cur_rx;
2705                 struct bnx_rx_buf *rb;
2706                 uint32_t rxidx;
2707                 struct mbuf *m = NULL;
2708                 uint16_t vlan_tag = 0;
2709                 int have_tag = 0;
2710
2711                 --count;
2712
2713                 cur_rx = &ret->bnx_rx_ret_ring[ret->bnx_rx_saved_considx];
2714
2715                 rxidx = cur_rx->bge_idx;
2716                 KKASSERT(rxidx < BGE_STD_RX_RING_CNT);
2717
2718                 BNX_INC(ret->bnx_rx_saved_considx, BNX_RETURN_RING_CNT);
2719 #ifdef BNX_RSS_DEBUG
2720                 ret->bnx_rx_pkt++;
2721 #endif
2722
2723                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2724                         have_tag = 1;
2725                         vlan_tag = cur_rx->bge_vlan_tag;
2726                 }
2727
2728                 if (ret->bnx_rx_cnt >= ret->bnx_rx_cntmax)
2729                         bnx_rx_std_refill_sched(ret, std);
2730                 ret->bnx_rx_cnt++;
2731
2732                 rb = &std->bnx_rx_std_buf[rxidx];
2733                 m = rb->bnx_rx_mbuf;
2734                 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2735                         IFNET_STAT_INC(ifp, ierrors, 1);
2736                         cpu_sfence();
2737                         rb->bnx_rx_refilled = 1;
2738                         continue;
2739                 }
2740                 if (bnx_newbuf_std(ret, rxidx, 0)) {
2741                         IFNET_STAT_INC(ifp, ierrors, 1);
2742                         continue;
2743                 }
2744
2745                 IFNET_STAT_INC(ifp, ipackets, 1);
2746                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2747                 m->m_pkthdr.rcvif = ifp;
2748
2749                 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2750                     (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
2751                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2752                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2753                                 if ((cur_rx->bge_error_flag &
2754                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
2755                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2756                         }
2757                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2758                                 m->m_pkthdr.csum_data =
2759                                     cur_rx->bge_tcp_udp_csum;
2760                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2761                                     CSUM_PSEUDO_HDR;
2762                         }
2763                 }
2764
2765                 /*
2766                  * If we received a packet with a vlan tag, pass it
2767                  * to vlan_input() instead of ether_input().
2768                  */
2769                 if (have_tag) {
2770                         m->m_flags |= M_VLANTAG;
2771                         m->m_pkthdr.ether_vlantag = vlan_tag;
2772                 }
2773                 ifp->if_input(ifp, m);
2774         }
2775         bnx_writembx(sc, ret->bnx_rx_mbx, ret->bnx_rx_saved_considx);
2776
2777         if (ret->bnx_rx_cnt > 0)
2778                 bnx_rx_std_refill_sched(ret, std);
2779 }
2780
2781 static void
2782 bnx_txeof(struct bnx_tx_ring *txr, uint16_t tx_cons)
2783 {
2784         struct ifnet *ifp = &txr->bnx_sc->arpcom.ac_if;
2785
2786         /*
2787          * Go through our tx ring and free mbufs for those
2788          * frames that have been sent.
2789          */
2790         while (txr->bnx_tx_saved_considx != tx_cons) {
2791                 struct bnx_tx_buf *buf;
2792                 uint32_t idx = 0;
2793
2794                 idx = txr->bnx_tx_saved_considx;
2795                 buf = &txr->bnx_tx_buf[idx];
2796                 if (buf->bnx_tx_mbuf != NULL) {
2797                         IFNET_STAT_INC(ifp, opackets, 1);
2798 #ifdef BNX_TSS_DEBUG
2799                         txr->bnx_tx_pkt++;
2800 #endif
2801                         bus_dmamap_unload(txr->bnx_tx_mtag,
2802                             buf->bnx_tx_dmamap);
2803                         m_freem(buf->bnx_tx_mbuf);
2804                         buf->bnx_tx_mbuf = NULL;
2805                 }
2806                 txr->bnx_tx_cnt--;
2807                 BNX_INC(txr->bnx_tx_saved_considx, BGE_TX_RING_CNT);
2808         }
2809
2810         if ((BGE_TX_RING_CNT - txr->bnx_tx_cnt) >=
2811             (BNX_NSEG_RSVD + BNX_NSEG_SPARE))
2812                 ifsq_clr_oactive(txr->bnx_ifsq);
2813
2814         if (txr->bnx_tx_cnt == 0)
2815                 txr->bnx_tx_watchdog.wd_timer = 0;
2816
2817         if (!ifsq_is_empty(txr->bnx_ifsq))
2818                 ifsq_devstart(txr->bnx_ifsq);
2819 }
2820
2821 static void
2822 bnx_handle_status(struct bnx_softc *sc)
2823 {
2824         uint32_t status;
2825
2826         status = *sc->bnx_hw_status;
2827
2828         if (status & BGE_STATFLAG_ERROR) {
2829                 uint32_t val;
2830                 int reset = 0;
2831
2832                 sc->bnx_errors++;
2833
2834                 val = CSR_READ_4(sc, BGE_FLOW_ATTN);
2835                 if (val & ~BGE_FLOWATTN_MB_LOWAT) {
2836                         if_printf(&sc->arpcom.ac_if,
2837                             "flow attn 0x%08x\n", val);
2838                         reset = 1;
2839                 }
2840
2841                 val = CSR_READ_4(sc, BGE_MSI_STATUS);
2842                 if (val & ~BGE_MSISTAT_MSI_PCI_REQ) {
2843                         if_printf(&sc->arpcom.ac_if,
2844                             "msi status 0x%08x\n", val);
2845                         reset = 1;
2846                 }
2847
2848                 val = CSR_READ_4(sc, BGE_RDMA_STATUS);
2849                 if (val) {
2850                         if_printf(&sc->arpcom.ac_if,
2851                             "rmda status 0x%08x\n", val);
2852                         reset = 1;
2853                 }
2854
2855                 val = CSR_READ_4(sc, BGE_WDMA_STATUS);
2856                 if (val) {
2857                         if_printf(&sc->arpcom.ac_if,
2858                             "wdma status 0x%08x\n", val);
2859                         reset = 1;
2860                 }
2861
2862                 if (reset) {
2863                         bnx_serialize_skipmain(sc);
2864                         bnx_init(sc);
2865                         bnx_deserialize_skipmain(sc);
2866                 }
2867         }
2868
2869         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bnx_link_evt)
2870                 bnx_link_poll(sc);
2871 }
2872
2873 #ifdef IFPOLL_ENABLE
2874
2875 static void
2876 bnx_npoll_rx(struct ifnet *ifp __unused, void *xret, int cycle)
2877 {
2878         struct bnx_rx_ret_ring *ret = xret;
2879         uint16_t rx_prod;
2880
2881         ASSERT_SERIALIZED(&ret->bnx_rx_ret_serialize);
2882
2883         ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag;
2884         cpu_lfence();
2885
2886         rx_prod = *ret->bnx_rx_considx;
2887         if (ret->bnx_rx_saved_considx != rx_prod)
2888                 bnx_rxeof(ret, rx_prod, cycle);
2889 }
2890
2891 static void
2892 bnx_npoll_tx_notag(struct ifnet *ifp __unused, void *xtxr, int cycle __unused)
2893 {
2894         struct bnx_tx_ring *txr = xtxr;
2895         uint16_t tx_cons;
2896
2897         ASSERT_SERIALIZED(&txr->bnx_tx_serialize);
2898
2899         tx_cons = *txr->bnx_tx_considx;
2900         if (txr->bnx_tx_saved_considx != tx_cons)
2901                 bnx_txeof(txr, tx_cons);
2902 }
2903
2904 static void
2905 bnx_npoll_tx(struct ifnet *ifp, void *xtxr, int cycle)
2906 {
2907         struct bnx_tx_ring *txr = xtxr;
2908
2909         ASSERT_SERIALIZED(&txr->bnx_tx_serialize);
2910
2911         txr->bnx_saved_status_tag = *txr->bnx_hw_status_tag;
2912         cpu_lfence();
2913         bnx_npoll_tx_notag(ifp, txr, cycle);
2914 }
2915
2916 static void
2917 bnx_npoll_status_notag(struct ifnet *ifp)
2918 {
2919         struct bnx_softc *sc = ifp->if_softc;
2920
2921         ASSERT_SERIALIZED(&sc->bnx_main_serialize);
2922
2923         bnx_handle_status(sc);
2924 }
2925
2926 static void
2927 bnx_npoll_status(struct ifnet *ifp)
2928 {
2929         struct bnx_softc *sc = ifp->if_softc;
2930
2931         ASSERT_SERIALIZED(&sc->bnx_main_serialize);
2932
2933         sc->bnx_saved_status_tag = *sc->bnx_hw_status_tag;
2934         cpu_lfence();
2935         bnx_npoll_status_notag(ifp);
2936 }
2937
2938 static void
2939 bnx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
2940 {
2941         struct bnx_softc *sc = ifp->if_softc;
2942         int i;
2943
2944         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2945
2946         if (info != NULL) {
2947                 if (sc->bnx_flags & BNX_FLAG_STATUS_HASTAG)
2948                         info->ifpi_status.status_func = bnx_npoll_status;
2949                 else
2950                         info->ifpi_status.status_func = bnx_npoll_status_notag;
2951                 info->ifpi_status.serializer = &sc->bnx_main_serialize;
2952
2953                 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
2954                         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
2955                         int idx = i + sc->bnx_npoll_txoff;
2956
2957                         KKASSERT(idx < ncpus2);
2958                         if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) {
2959                                 info->ifpi_tx[idx].poll_func =
2960                                     bnx_npoll_tx_notag;
2961                         } else {
2962                                 info->ifpi_tx[idx].poll_func = bnx_npoll_tx;
2963                         }
2964                         info->ifpi_tx[idx].arg = txr;
2965                         info->ifpi_tx[idx].serializer = &txr->bnx_tx_serialize;
2966                         ifsq_set_cpuid(txr->bnx_ifsq, idx);
2967                 }
2968
2969                 for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
2970                         struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i];
2971                         int idx = i + sc->bnx_npoll_rxoff;
2972
2973                         KKASSERT(idx < ncpus2);
2974                         info->ifpi_rx[idx].poll_func = bnx_npoll_rx;
2975                         info->ifpi_rx[idx].arg = ret;
2976                         info->ifpi_rx[idx].serializer =
2977                             &ret->bnx_rx_ret_serialize;
2978                 }
2979
2980                 if (ifp->if_flags & IFF_RUNNING) {
2981                         bnx_disable_intr(sc);
2982                         bnx_set_tick_cpuid(sc, TRUE);
2983                 }
2984         } else {
2985                 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
2986                         ifsq_set_cpuid(sc->bnx_tx_ring[i].bnx_ifsq,
2987                             sc->bnx_tx_ring[i].bnx_tx_cpuid);
2988                 }
2989                 if (ifp->if_flags & IFF_RUNNING) {
2990                         bnx_enable_intr(sc);
2991                         bnx_set_tick_cpuid(sc, FALSE);
2992                 }
2993         }
2994 }
2995
2996 #endif  /* IFPOLL_ENABLE */
2997
2998 static void
2999 bnx_intr_legacy(void *xsc)
3000 {
3001         struct bnx_softc *sc = xsc;
3002         struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0];
3003
3004         if (ret->bnx_saved_status_tag == *ret->bnx_hw_status_tag) {
3005                 uint32_t val;
3006
3007                 val = pci_read_config(sc->bnx_dev, BGE_PCI_PCISTATE, 4);
3008                 if (val & BGE_PCISTAT_INTR_NOTACT)
3009                         return;
3010         }
3011
3012         /*
3013          * NOTE:
3014          * Interrupt will have to be disabled if tagged status
3015          * is used, else interrupt will always be asserted on
3016          * certain chips (at least on BCM5750 AX/BX).
3017          */
3018         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3019
3020         bnx_intr(sc);
3021 }
3022
3023 static void
3024 bnx_msi(void *xsc)
3025 {
3026         bnx_intr(xsc);
3027 }
3028
3029 static void
3030 bnx_intr(struct bnx_softc *sc)
3031 {
3032         struct ifnet *ifp = &sc->arpcom.ac_if;
3033         struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0];
3034
3035         ASSERT_SERIALIZED(&sc->bnx_main_serialize);
3036
3037         ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag;
3038         /*
3039          * Use a load fence to ensure that status_tag is saved 
3040          * before rx_prod, tx_cons and status.
3041          */
3042         cpu_lfence();
3043
3044         bnx_handle_status(sc);
3045
3046         if (ifp->if_flags & IFF_RUNNING) {
3047                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
3048                 uint16_t rx_prod, tx_cons;
3049
3050                 lwkt_serialize_enter(&ret->bnx_rx_ret_serialize);
3051                 rx_prod = *ret->bnx_rx_considx;
3052                 if (ret->bnx_rx_saved_considx != rx_prod)
3053                         bnx_rxeof(ret, rx_prod, -1);
3054                 lwkt_serialize_exit(&ret->bnx_rx_ret_serialize);
3055
3056                 lwkt_serialize_enter(&txr->bnx_tx_serialize);
3057                 tx_cons = *txr->bnx_tx_considx;
3058                 if (txr->bnx_tx_saved_considx != tx_cons)
3059                         bnx_txeof(txr, tx_cons);
3060                 lwkt_serialize_exit(&txr->bnx_tx_serialize);
3061         }
3062
3063         bnx_writembx(sc, BGE_MBX_IRQ0_LO, ret->bnx_saved_status_tag << 24);
3064 }
3065
3066 static void
3067 bnx_msix_tx_status(void *xtxr)
3068 {
3069         struct bnx_tx_ring *txr = xtxr;
3070         struct bnx_softc *sc = txr->bnx_sc;
3071         struct ifnet *ifp = &sc->arpcom.ac_if;
3072
3073         ASSERT_SERIALIZED(&sc->bnx_main_serialize);
3074
3075         txr->bnx_saved_status_tag = *txr->bnx_hw_status_tag;
3076         /*
3077          * Use a load fence to ensure that status_tag is saved 
3078          * before tx_cons and status.
3079          */
3080         cpu_lfence();
3081
3082         bnx_handle_status(sc);
3083
3084         if (ifp->if_flags & IFF_RUNNING) {
3085                 uint16_t tx_cons;
3086
3087                 lwkt_serialize_enter(&txr->bnx_tx_serialize);
3088                 tx_cons = *txr->bnx_tx_considx;
3089                 if (txr->bnx_tx_saved_considx != tx_cons)
3090                         bnx_txeof(txr, tx_cons);
3091                 lwkt_serialize_exit(&txr->bnx_tx_serialize);
3092         }
3093
3094         bnx_writembx(sc, BGE_MBX_IRQ0_LO, txr->bnx_saved_status_tag << 24);
3095 }
3096
3097 static void
3098 bnx_msix_rx(void *xret)
3099 {
3100         struct bnx_rx_ret_ring *ret = xret;
3101         uint16_t rx_prod;
3102
3103         ASSERT_SERIALIZED(&ret->bnx_rx_ret_serialize);
3104
3105         ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag;
3106         /*
3107          * Use a load fence to ensure that status_tag is saved
3108          * before rx_prod.
3109          */
3110         cpu_lfence();
3111
3112         rx_prod = *ret->bnx_rx_considx;
3113         if (ret->bnx_rx_saved_considx != rx_prod)
3114                 bnx_rxeof(ret, rx_prod, -1);
3115
3116         bnx_writembx(ret->bnx_sc, ret->bnx_msix_mbx,
3117             ret->bnx_saved_status_tag << 24);
3118 }
3119
3120 static void
3121 bnx_msix_rxtx(void *xret)
3122 {
3123         struct bnx_rx_ret_ring *ret = xret;
3124         struct bnx_tx_ring *txr = ret->bnx_txr;
3125         uint16_t rx_prod, tx_cons;
3126
3127         ASSERT_SERIALIZED(&ret->bnx_rx_ret_serialize);
3128
3129         ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag;
3130         /*
3131          * Use a load fence to ensure that status_tag is saved
3132          * before rx_prod and tx_cons.
3133          */
3134         cpu_lfence();
3135
3136         rx_prod = *ret->bnx_rx_considx;
3137         if (ret->bnx_rx_saved_considx != rx_prod)
3138                 bnx_rxeof(ret, rx_prod, -1);
3139
3140         lwkt_serialize_enter(&txr->bnx_tx_serialize);
3141         tx_cons = *txr->bnx_tx_considx;
3142         if (txr->bnx_tx_saved_considx != tx_cons)
3143                 bnx_txeof(txr, tx_cons);
3144         lwkt_serialize_exit(&txr->bnx_tx_serialize);
3145
3146         bnx_writembx(ret->bnx_sc, ret->bnx_msix_mbx,
3147             ret->bnx_saved_status_tag << 24);
3148 }
3149
3150 static void
3151 bnx_msix_status(void *xsc)
3152 {
3153         struct bnx_softc *sc = xsc;
3154
3155         ASSERT_SERIALIZED(&sc->bnx_main_serialize);
3156
3157         sc->bnx_saved_status_tag = *sc->bnx_hw_status_tag;
3158         /*
3159          * Use a load fence to ensure that status_tag is saved
3160          * before status.
3161          */
3162         cpu_lfence();
3163
3164         bnx_handle_status(sc);
3165
3166         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_saved_status_tag << 24);
3167 }
3168
3169 static void
3170 bnx_tick(void *xsc)
3171 {
3172         struct bnx_softc *sc = xsc;
3173
3174         lwkt_serialize_enter(&sc->bnx_main_serialize);
3175
3176         bnx_stats_update_regs(sc);
3177
3178         if (sc->bnx_flags & BNX_FLAG_TBI) {
3179                 /*
3180                  * Since in TBI mode auto-polling can't be used we should poll
3181                  * link status manually. Here we register pending link event
3182                  * and trigger interrupt.
3183                  */
3184                 sc->bnx_link_evt++;
3185                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3186         } else if (!sc->bnx_link) {
3187                 mii_tick(device_get_softc(sc->bnx_miibus));
3188         }
3189
3190         callout_reset_bycpu(&sc->bnx_tick_timer, hz, bnx_tick, sc,
3191             sc->bnx_tick_cpuid);
3192
3193         lwkt_serialize_exit(&sc->bnx_main_serialize);
3194 }
3195
3196 static void
3197 bnx_stats_update_regs(struct bnx_softc *sc)
3198 {
3199         struct ifnet *ifp = &sc->arpcom.ac_if;
3200         struct bge_mac_stats_regs stats;
3201         uint32_t *s, val;
3202         int i;
3203
3204         s = (uint32_t *)&stats;
3205         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
3206                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
3207                 s++;
3208         }
3209
3210         IFNET_STAT_SET(ifp, collisions,
3211            (stats.dot3StatsSingleCollisionFrames +
3212            stats.dot3StatsMultipleCollisionFrames +
3213            stats.dot3StatsExcessiveCollisions +
3214            stats.dot3StatsLateCollisions));
3215
3216         val = CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
3217         sc->bnx_norxbds += val;
3218 }
3219
3220 /*
3221  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
3222  * pointers to descriptors.
3223  */
3224 static int
3225 bnx_encap(struct bnx_tx_ring *txr, struct mbuf **m_head0, uint32_t *txidx,
3226     int *segs_used)
3227 {
3228         struct bge_tx_bd *d = NULL;
3229         uint16_t csum_flags = 0, vlan_tag = 0, mss = 0;
3230         bus_dma_segment_t segs[BNX_NSEG_NEW];
3231         bus_dmamap_t map;
3232         int error, maxsegs, nsegs, idx, i;
3233         struct mbuf *m_head = *m_head0, *m_new;
3234
3235         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3236 #ifdef BNX_TSO_DEBUG
3237                 int tso_nsegs;
3238 #endif
3239
3240                 error = bnx_setup_tso(txr, m_head0, &mss, &csum_flags);
3241                 if (error)
3242                         return error;
3243                 m_head = *m_head0;
3244
3245 #ifdef BNX_TSO_DEBUG
3246                 tso_nsegs = (m_head->m_pkthdr.len /
3247                     m_head->m_pkthdr.tso_segsz) - 1;
3248                 if (tso_nsegs > (BNX_TSO_NSTATS - 1))
3249                         tso_nsegs = BNX_TSO_NSTATS - 1;
3250                 else if (tso_nsegs < 0)
3251                         tso_nsegs = 0;
3252                 txr->bnx_sc->bnx_tsosegs[tso_nsegs]++;
3253 #endif
3254         } else if (m_head->m_pkthdr.csum_flags & BNX_CSUM_FEATURES) {
3255                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3256                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3257                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
3258                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3259                 if (m_head->m_flags & M_LASTFRAG)
3260                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3261                 else if (m_head->m_flags & M_FRAG)
3262                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3263         }
3264         if (m_head->m_flags & M_VLANTAG) {
3265                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
3266                 vlan_tag = m_head->m_pkthdr.ether_vlantag;
3267         }
3268
3269         idx = *txidx;
3270         map = txr->bnx_tx_buf[idx].bnx_tx_dmamap;
3271
3272         maxsegs = (BGE_TX_RING_CNT - txr->bnx_tx_cnt) - BNX_NSEG_RSVD;
3273         KASSERT(maxsegs >= BNX_NSEG_SPARE,
3274                 ("not enough segments %d", maxsegs));
3275
3276         if (maxsegs > BNX_NSEG_NEW)
3277                 maxsegs = BNX_NSEG_NEW;
3278
3279         /*
3280          * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
3281          * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
3282          * but when such padded frames employ the bge IP/TCP checksum
3283          * offload, the hardware checksum assist gives incorrect results
3284          * (possibly from incorporating its own padding into the UDP/TCP
3285          * checksum; who knows).  If we pad such runts with zeros, the
3286          * onboard checksum comes out correct.
3287          */
3288         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
3289             m_head->m_pkthdr.len < BNX_MIN_FRAMELEN) {
3290                 error = m_devpad(m_head, BNX_MIN_FRAMELEN);
3291                 if (error)
3292                         goto back;
3293         }
3294
3295         if ((txr->bnx_tx_flags & BNX_TX_FLAG_SHORTDMA) &&
3296             m_head->m_next != NULL) {
3297                 m_new = bnx_defrag_shortdma(m_head);
3298                 if (m_new == NULL) {
3299                         error = ENOBUFS;
3300                         goto back;
3301                 }
3302                 *m_head0 = m_head = m_new;
3303         }
3304         if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
3305             (txr->bnx_tx_flags & BNX_TX_FLAG_FORCE_DEFRAG) &&
3306             m_head->m_next != NULL) {
3307                 /*
3308                  * Forcefully defragment mbuf chain to overcome hardware
3309                  * limitation which only support a single outstanding
3310                  * DMA read operation.  If it fails, keep moving on using
3311                  * the original mbuf chain.
3312                  */
3313                 m_new = m_defrag(m_head, MB_DONTWAIT);
3314                 if (m_new != NULL)
3315                         *m_head0 = m_head = m_new;
3316         }
3317
3318         error = bus_dmamap_load_mbuf_defrag(txr->bnx_tx_mtag, map,
3319             m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3320         if (error)
3321                 goto back;
3322         *segs_used += nsegs;
3323
3324         m_head = *m_head0;
3325         bus_dmamap_sync(txr->bnx_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3326
3327         for (i = 0; ; i++) {
3328                 d = &txr->bnx_tx_ring[idx];
3329
3330                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3331                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3332                 d->bge_len = segs[i].ds_len;
3333                 d->bge_flags = csum_flags;
3334                 d->bge_vlan_tag = vlan_tag;
3335                 d->bge_mss = mss;
3336
3337                 if (i == nsegs - 1)
3338                         break;
3339                 BNX_INC(idx, BGE_TX_RING_CNT);
3340         }
3341         /* Mark the last segment as end of packet... */
3342         d->bge_flags |= BGE_TXBDFLAG_END;
3343
3344         /*
3345          * Insure that the map for this transmission is placed at
3346          * the array index of the last descriptor in this chain.
3347          */
3348         txr->bnx_tx_buf[*txidx].bnx_tx_dmamap = txr->bnx_tx_buf[idx].bnx_tx_dmamap;
3349         txr->bnx_tx_buf[idx].bnx_tx_dmamap = map;
3350         txr->bnx_tx_buf[idx].bnx_tx_mbuf = m_head;
3351         txr->bnx_tx_cnt += nsegs;
3352
3353         BNX_INC(idx, BGE_TX_RING_CNT);
3354         *txidx = idx;
3355 back:
3356         if (error) {
3357                 m_freem(*m_head0);
3358                 *m_head0 = NULL;
3359         }
3360         return error;
3361 }
3362
3363 /*
3364  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3365  * to the mbuf data regions directly in the transmit descriptors.
3366  */
3367 static void
3368 bnx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
3369 {
3370         struct bnx_tx_ring *txr = ifsq_get_priv(ifsq);
3371         struct mbuf *m_head = NULL;
3372         uint32_t prodidx;
3373         int nsegs = 0;
3374
3375         KKASSERT(txr->bnx_ifsq == ifsq);
3376         ASSERT_SERIALIZED(&txr->bnx_tx_serialize);
3377
3378         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
3379                 return;
3380
3381         prodidx = txr->bnx_tx_prodidx;
3382
3383         while (txr->bnx_tx_buf[prodidx].bnx_tx_mbuf == NULL) {
3384                 /*
3385                  * Sanity check: avoid coming within BGE_NSEG_RSVD
3386                  * descriptors of the end of the ring.  Also make
3387                  * sure there are BGE_NSEG_SPARE descriptors for
3388                  * jumbo buffers' or TSO segments' defragmentation.
3389                  */
3390                 if ((BGE_TX_RING_CNT - txr->bnx_tx_cnt) <
3391                     (BNX_NSEG_RSVD + BNX_NSEG_SPARE)) {
3392                         ifsq_set_oactive(ifsq);
3393                         break;
3394                 }
3395
3396                 m_head = ifsq_dequeue(ifsq, NULL);
3397                 if (m_head == NULL)
3398                         break;
3399
3400                 /*
3401                  * Pack the data into the transmit ring. If we
3402                  * don't have room, set the OACTIVE flag and wait
3403                  * for the NIC to drain the ring.
3404                  */
3405                 if (bnx_encap(txr, &m_head, &prodidx, &nsegs)) {
3406                         ifsq_set_oactive(ifsq);
3407                         IFNET_STAT_INC(ifp, oerrors, 1);
3408                         break;
3409                 }
3410
3411                 if (nsegs >= txr->bnx_tx_wreg) {
3412                         /* Transmit */
3413                         bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, prodidx);
3414                         nsegs = 0;
3415                 }
3416
3417                 ETHER_BPF_MTAP(ifp, m_head);
3418
3419                 /*
3420                  * Set a timeout in case the chip goes out to lunch.
3421                  */
3422                 txr->bnx_tx_watchdog.wd_timer = 5;
3423         }
3424
3425         if (nsegs > 0) {
3426                 /* Transmit */
3427                 bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, prodidx);
3428         }
3429         txr->bnx_tx_prodidx = prodidx;
3430 }
3431
3432 static void
3433 bnx_init(void *xsc)
3434 {
3435         struct bnx_softc *sc = xsc;
3436         struct ifnet *ifp = &sc->arpcom.ac_if;
3437         uint16_t *m;
3438         uint32_t mode;
3439         int i;
3440         boolean_t polling;
3441
3442         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3443
3444         /* Cancel pending I/O and flush buffers. */
3445         bnx_stop(sc);
3446         bnx_reset(sc);
3447         bnx_chipinit(sc);
3448
3449         /*
3450          * Init the various state machines, ring
3451          * control blocks and firmware.
3452          */
3453         if (bnx_blockinit(sc)) {
3454                 if_printf(ifp, "initialization failure\n");
3455                 bnx_stop(sc);
3456                 return;
3457         }
3458
3459         /* Specify MTU. */
3460         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3461             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3462
3463         /* Load our MAC address. */
3464         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3465         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3466         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3467
3468         /* Enable or disable promiscuous mode as needed. */
3469         bnx_setpromisc(sc);
3470
3471         /* Program multicast filter. */
3472         bnx_setmulti(sc);
3473
3474         /* Init RX ring. */
3475         if (bnx_init_rx_ring_std(&sc->bnx_rx_std_ring)) {
3476                 if_printf(ifp, "RX ring initialization failed\n");
3477                 bnx_stop(sc);
3478                 return;
3479         }
3480
3481         /* Init jumbo RX ring. */
3482         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3483                 if (bnx_init_rx_ring_jumbo(sc)) {
3484                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
3485                         bnx_stop(sc);
3486                         return;
3487                 }
3488         }
3489
3490         /* Init our RX return ring index */
3491         for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
3492                 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i];
3493
3494                 ret->bnx_rx_saved_considx = 0;
3495                 ret->bnx_rx_cnt = 0;
3496         }
3497
3498         /* Init TX ring. */
3499         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3500                 bnx_init_tx_ring(&sc->bnx_tx_ring[i]);
3501
3502         /* Enable TX MAC state machine lockup fix. */
3503         mode = CSR_READ_4(sc, BGE_TX_MODE);
3504         mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3505         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
3506             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
3507                 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3508                 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
3509                     (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3510         }
3511         /* Turn on transmitter */
3512         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3513
3514         /* Initialize RSS */
3515         mode = BGE_RXMODE_ENABLE;
3516         if (BNX_RSS_ENABLED(sc)) {
3517                 bnx_init_rss(sc);
3518                 mode |= BGE_RXMODE_RSS_ENABLE |
3519                     BGE_RXMODE_RSS_HASH_MASK_BITS |
3520                     BGE_RXMODE_RSS_IPV4_HASH |
3521                     BGE_RXMODE_RSS_TCP_IPV4_HASH;
3522         }
3523         /* Turn on receiver */
3524         BNX_SETBIT(sc, BGE_RX_MODE, mode);
3525
3526         /*
3527          * Set the number of good frames to receive after RX MBUF
3528          * Low Watermark has been reached.  After the RX MAC receives
3529          * this number of frames, it will drop subsequent incoming
3530          * frames until the MBUF High Watermark is reached.
3531          */
3532         if (BNX_IS_57765_FAMILY(sc))
3533                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
3534         else
3535                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3536
3537         if (sc->bnx_intr_type == PCI_INTR_TYPE_MSI ||
3538             sc->bnx_intr_type == PCI_INTR_TYPE_MSIX) {
3539                 if (bootverbose) {
3540                         if_printf(ifp, "MSI_MODE: %#x\n",
3541                             CSR_READ_4(sc, BGE_MSI_MODE));
3542                 }
3543         }
3544
3545         /* Tell firmware we're alive. */
3546         BNX_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3547
3548         /* Enable host interrupts if polling(4) is not enabled. */
3549         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3550
3551         polling = FALSE;
3552 #ifdef IFPOLL_ENABLE
3553         if (ifp->if_flags & IFF_NPOLLING)
3554                 polling = TRUE;
3555 #endif
3556         if (polling)
3557                 bnx_disable_intr(sc);
3558         else
3559                 bnx_enable_intr(sc);
3560         bnx_set_tick_cpuid(sc, polling);
3561
3562         bnx_ifmedia_upd(ifp);
3563
3564         ifp->if_flags |= IFF_RUNNING;
3565         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3566                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3567
3568                 ifsq_clr_oactive(txr->bnx_ifsq);
3569                 ifsq_watchdog_start(&txr->bnx_tx_watchdog);
3570         }
3571
3572         callout_reset_bycpu(&sc->bnx_tick_timer, hz, bnx_tick, sc,
3573             sc->bnx_tick_cpuid);
3574 }
3575
3576 /*
3577  * Set media options.
3578  */
3579 static int
3580 bnx_ifmedia_upd(struct ifnet *ifp)
3581 {
3582         struct bnx_softc *sc = ifp->if_softc;
3583
3584         /* If this is a 1000baseX NIC, enable the TBI port. */
3585         if (sc->bnx_flags & BNX_FLAG_TBI) {
3586                 struct ifmedia *ifm = &sc->bnx_ifmedia;
3587
3588                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3589                         return(EINVAL);
3590
3591                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3592                 case IFM_AUTO:
3593                         break;
3594
3595                 case IFM_1000_SX:
3596                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3597                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3598                                     BGE_MACMODE_HALF_DUPLEX);
3599                         } else {
3600                                 BNX_SETBIT(sc, BGE_MAC_MODE,
3601                                     BGE_MACMODE_HALF_DUPLEX);
3602                         }
3603                         break;
3604                 default:
3605                         return(EINVAL);
3606                 }
3607         } else {
3608                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3609
3610                 sc->bnx_link_evt++;
3611                 sc->bnx_link = 0;
3612                 if (mii->mii_instance) {
3613                         struct mii_softc *miisc;
3614
3615                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3616                                 mii_phy_reset(miisc);
3617                 }
3618                 mii_mediachg(mii);
3619
3620                 /*
3621                  * Force an interrupt so that we will call bnx_link_upd
3622                  * if needed and clear any pending link state attention.
3623                  * Without this we are not getting any further interrupts
3624                  * for link state changes and thus will not UP the link and
3625                  * not be able to send in bnx_start.  The only way to get
3626                  * things working was to receive a packet and get an RX
3627                  * intr.
3628                  *
3629                  * bnx_tick should help for fiber cards and we might not
3630                  * need to do this here if BNX_FLAG_TBI is set but as
3631                  * we poll for fiber anyway it should not harm.
3632                  */
3633                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3634         }
3635         return(0);
3636 }
3637
3638 /*
3639  * Report current media status.
3640  */
3641 static void
3642 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3643 {
3644         struct bnx_softc *sc = ifp->if_softc;
3645
3646         if (sc->bnx_flags & BNX_FLAG_TBI) {
3647                 ifmr->ifm_status = IFM_AVALID;
3648                 ifmr->ifm_active = IFM_ETHER;
3649                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3650                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3651                         ifmr->ifm_status |= IFM_ACTIVE;
3652                 } else {
3653                         ifmr->ifm_active |= IFM_NONE;
3654                         return;
3655                 }
3656
3657                 ifmr->ifm_active |= IFM_1000_SX;
3658                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3659                         ifmr->ifm_active |= IFM_HDX;    
3660                 else
3661                         ifmr->ifm_active |= IFM_FDX;
3662         } else {
3663                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3664
3665                 mii_pollstat(mii);
3666                 ifmr->ifm_active = mii->mii_media_active;
3667                 ifmr->ifm_status = mii->mii_media_status;
3668         }
3669 }
3670
3671 static int
3672 bnx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3673 {
3674         struct bnx_softc *sc = ifp->if_softc;
3675         struct ifreq *ifr = (struct ifreq *)data;
3676         int mask, error = 0;
3677
3678         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3679
3680         switch (command) {
3681         case SIOCSIFMTU:
3682                 if ((!BNX_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3683                     (BNX_IS_JUMBO_CAPABLE(sc) &&
3684                      ifr->ifr_mtu > BNX_JUMBO_MTU)) {
3685                         error = EINVAL;
3686                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3687                         ifp->if_mtu = ifr->ifr_mtu;
3688                         if (ifp->if_flags & IFF_RUNNING)
3689                                 bnx_init(sc);
3690                 }
3691                 break;
3692         case SIOCSIFFLAGS:
3693                 if (ifp->if_flags & IFF_UP) {
3694                         if (ifp->if_flags & IFF_RUNNING) {
3695                                 mask = ifp->if_flags ^ sc->bnx_if_flags;
3696
3697                                 /*
3698                                  * If only the state of the PROMISC flag
3699                                  * changed, then just use the 'set promisc
3700                                  * mode' command instead of reinitializing
3701                                  * the entire NIC. Doing a full re-init
3702                                  * means reloading the firmware and waiting
3703                                  * for it to start up, which may take a
3704                                  * second or two.  Similarly for ALLMULTI.
3705                                  */
3706                                 if (mask & IFF_PROMISC)
3707                                         bnx_setpromisc(sc);
3708                                 if (mask & IFF_ALLMULTI)
3709                                         bnx_setmulti(sc);
3710                         } else {
3711                                 bnx_init(sc);
3712                         }
3713                 } else if (ifp->if_flags & IFF_RUNNING) {
3714                         bnx_stop(sc);
3715                 }
3716                 sc->bnx_if_flags = ifp->if_flags;
3717                 break;
3718         case SIOCADDMULTI:
3719         case SIOCDELMULTI:
3720                 if (ifp->if_flags & IFF_RUNNING)
3721                         bnx_setmulti(sc);
3722                 break;
3723         case SIOCSIFMEDIA:
3724         case SIOCGIFMEDIA:
3725                 if (sc->bnx_flags & BNX_FLAG_TBI) {
3726                         error = ifmedia_ioctl(ifp, ifr,
3727                             &sc->bnx_ifmedia, command);
3728                 } else {
3729                         struct mii_data *mii;
3730
3731                         mii = device_get_softc(sc->bnx_miibus);
3732                         error = ifmedia_ioctl(ifp, ifr,
3733                                               &mii->mii_media, command);
3734                 }
3735                 break;
3736         case SIOCSIFCAP:
3737                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3738                 if (mask & IFCAP_HWCSUM) {
3739                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3740                         if (ifp->if_capenable & IFCAP_TXCSUM)
3741                                 ifp->if_hwassist |= BNX_CSUM_FEATURES;
3742                         else
3743                                 ifp->if_hwassist &= ~BNX_CSUM_FEATURES;
3744                 }
3745                 if (mask & IFCAP_TSO) {
3746                         ifp->if_capenable ^= (mask & IFCAP_TSO);
3747                         if (ifp->if_capenable & IFCAP_TSO)
3748                                 ifp->if_hwassist |= CSUM_TSO;
3749                         else
3750                                 ifp->if_hwassist &= ~CSUM_TSO;
3751                 }
3752                 break;
3753         default:
3754                 error = ether_ioctl(ifp, command, data);
3755                 break;
3756         }
3757         return error;
3758 }
3759
3760 static void
3761 bnx_watchdog(struct ifaltq_subque *ifsq)
3762 {
3763         struct ifnet *ifp = ifsq_get_ifp(ifsq);
3764         struct bnx_softc *sc = ifp->if_softc;
3765         int i;
3766
3767         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3768
3769         if_printf(ifp, "watchdog timeout -- resetting\n");
3770
3771         bnx_init(sc);
3772
3773         IFNET_STAT_INC(ifp, oerrors, 1);
3774
3775         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3776                 ifsq_devstart_sched(sc->bnx_tx_ring[i].bnx_ifsq);
3777 }
3778
3779 /*
3780  * Stop the adapter and free any mbufs allocated to the
3781  * RX and TX lists.
3782  */
3783 static void
3784 bnx_stop(struct bnx_softc *sc)
3785 {
3786         struct ifnet *ifp = &sc->arpcom.ac_if;
3787         int i;
3788
3789         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3790
3791         callout_stop(&sc->bnx_tick_timer);
3792
3793         /*
3794          * Disable all of the receiver blocks
3795          */
3796         bnx_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3797         bnx_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3798         bnx_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3799         bnx_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3800         bnx_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3801         bnx_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3802
3803         /*
3804          * Disable all of the transmit blocks
3805          */
3806         bnx_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3807         bnx_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3808         bnx_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3809         bnx_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3810         bnx_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3811         bnx_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3812
3813         /*
3814          * Shut down all of the memory managers and related
3815          * state machines.
3816          */
3817         bnx_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3818         bnx_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3819         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3820         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3821
3822         /* Disable host interrupts. */
3823         bnx_disable_intr(sc);
3824
3825         /*
3826          * Tell firmware we're shutting down.
3827          */
3828         BNX_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3829
3830         /* Free the RX lists. */
3831         bnx_free_rx_ring_std(&sc->bnx_rx_std_ring);
3832
3833         /* Free jumbo RX list. */
3834         if (BNX_IS_JUMBO_CAPABLE(sc))
3835                 bnx_free_rx_ring_jumbo(sc);
3836
3837         /* Free TX buffers. */
3838         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3839                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3840
3841                 txr->bnx_saved_status_tag = 0;
3842                 bnx_free_tx_ring(txr);
3843         }
3844
3845         /* Clear saved status tag */
3846         for (i = 0; i < sc->bnx_rx_retcnt; ++i)
3847                 sc->bnx_rx_ret_ring[i].bnx_saved_status_tag = 0;
3848
3849         sc->bnx_link = 0;
3850         sc->bnx_coal_chg = 0;
3851
3852         ifp->if_flags &= ~IFF_RUNNING;
3853         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3854                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3855
3856                 ifsq_clr_oactive(txr->bnx_ifsq);
3857                 ifsq_watchdog_stop(&txr->bnx_tx_watchdog);
3858         }
3859 }
3860
3861 /*
3862  * Stop all chip I/O so that the kernel's probe routines don't
3863  * get confused by errant DMAs when rebooting.
3864  */
3865 static void
3866 bnx_shutdown(device_t dev)
3867 {
3868         struct bnx_softc *sc = device_get_softc(dev);
3869         struct ifnet *ifp = &sc->arpcom.ac_if;
3870
3871         ifnet_serialize_all(ifp);
3872         bnx_stop(sc);
3873         bnx_reset(sc);
3874         ifnet_deserialize_all(ifp);
3875 }
3876
3877 static int
3878 bnx_suspend(device_t dev)
3879 {
3880         struct bnx_softc *sc = device_get_softc(dev);
3881         struct ifnet *ifp = &sc->arpcom.ac_if;
3882
3883         ifnet_serialize_all(ifp);
3884         bnx_stop(sc);
3885         ifnet_deserialize_all(ifp);
3886
3887         return 0;
3888 }
3889
3890 static int
3891 bnx_resume(device_t dev)
3892 {
3893         struct bnx_softc *sc = device_get_softc(dev);
3894         struct ifnet *ifp = &sc->arpcom.ac_if;
3895
3896         ifnet_serialize_all(ifp);
3897
3898         if (ifp->if_flags & IFF_UP) {
3899                 int i;
3900
3901                 bnx_init(sc);
3902                 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3903                         ifsq_devstart_sched(sc->bnx_tx_ring[i].bnx_ifsq);
3904         }
3905
3906         ifnet_deserialize_all(ifp);
3907
3908         return 0;
3909 }
3910
3911 static void
3912 bnx_setpromisc(struct bnx_softc *sc)
3913 {
3914         struct ifnet *ifp = &sc->arpcom.ac_if;
3915
3916         if (ifp->if_flags & IFF_PROMISC)
3917                 BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3918         else
3919                 BNX_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3920 }
3921
3922 static void
3923 bnx_dma_free(struct bnx_softc *sc)
3924 {
3925         struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring;
3926         int i;
3927
3928         /* Destroy RX return rings */
3929         if (sc->bnx_rx_ret_ring != NULL) {
3930                 for (i = 0; i < sc->bnx_rx_retcnt; ++i)
3931                         bnx_destroy_rx_ret_ring(&sc->bnx_rx_ret_ring[i]);
3932                 kfree(sc->bnx_rx_ret_ring, M_DEVBUF);
3933         }
3934
3935         /* Destroy RX mbuf DMA stuffs. */
3936         if (std->bnx_rx_mtag != NULL) {
3937                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3938                         KKASSERT(std->bnx_rx_std_buf[i].bnx_rx_mbuf == NULL);
3939                         bus_dmamap_destroy(std->bnx_rx_mtag,
3940                             std->bnx_rx_std_buf[i].bnx_rx_dmamap);
3941                 }
3942                 bus_dma_tag_destroy(std->bnx_rx_mtag);
3943         }
3944
3945         /* Destroy standard RX ring */
3946         bnx_dma_block_free(std->bnx_rx_std_ring_tag,
3947             std->bnx_rx_std_ring_map, std->bnx_rx_std_ring);
3948
3949         /* Destroy TX rings */
3950         if (sc->bnx_tx_ring != NULL) {
3951                 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3952                         bnx_destroy_tx_ring(&sc->bnx_tx_ring[i]);
3953                 kfree(sc->bnx_tx_ring, M_DEVBUF);
3954         }
3955
3956         if (BNX_IS_JUMBO_CAPABLE(sc))
3957                 bnx_free_jumbo_mem(sc);
3958
3959         /* Destroy status blocks */
3960         for (i = 0; i < sc->bnx_intr_cnt; ++i) {
3961                 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
3962
3963                 bnx_dma_block_free(intr->bnx_status_tag,
3964                     intr->bnx_status_map, intr->bnx_status_block);
3965         }
3966
3967         /* Destroy the parent tag */
3968         if (sc->bnx_cdata.bnx_parent_tag != NULL)
3969                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_parent_tag);
3970 }
3971
3972 static int
3973 bnx_dma_alloc(device_t dev)
3974 {
3975         struct bnx_softc *sc = device_get_softc(dev);
3976         struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring;
3977         int i, error, mbx;
3978
3979         /*
3980          * Allocate the parent bus DMA tag appropriate for PCI.
3981          *
3982          * All of the NetExtreme/NetLink controllers have 4GB boundary
3983          * DMA bug.
3984          * Whenever an address crosses a multiple of the 4GB boundary
3985          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3986          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3987          * state machine will lockup and cause the device to hang.
3988          */
3989         error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
3990             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
3991             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3992             0, &sc->bnx_cdata.bnx_parent_tag);
3993         if (error) {
3994                 device_printf(dev, "could not create parent DMA tag\n");
3995                 return error;
3996         }
3997
3998         /*
3999          * Create DMA stuffs for status blocks.
4000          */
4001         for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4002                 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
4003
4004                 error = bnx_dma_block_alloc(sc,
4005                     __VM_CACHELINE_ALIGN(BGE_STATUS_BLK_SZ),
4006                     &intr->bnx_status_tag, &intr->bnx_status_map,
4007                     (void *)&intr->bnx_status_block,
4008                     &intr->bnx_status_block_paddr);
4009                 if (error) {
4010                         device_printf(dev,
4011                             "could not create %dth status block\n", i);
4012                         return error;
4013                 }
4014         }
4015         sc->bnx_hw_status = &sc->bnx_intr_data[0].bnx_status_block->bge_status;
4016         if (sc->bnx_flags & BNX_FLAG_STATUS_HASTAG) {
4017                 sc->bnx_hw_status_tag =
4018                     &sc->bnx_intr_data[0].bnx_status_block->bge_status_tag;
4019         }
4020
4021         /*
4022          * Create DMA tag and maps for RX mbufs.