2 * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 * 3. Neither the names of the above-listed copyright holders nor the names
16 * of any contributors may be used to endorse or promote products derived
17 * from this software without specific prior written permission.
19 * Alternatively, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") version 2 as published by the Free
21 * Software Foundation.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
36 * $FreeBSD: src/sys/dev/ath/if_ath.c,v 1.94.2.23 2006/07/10 01:15:24 sam Exp $
37 * $DragonFly: src/sys/dev/netif/ath/ath/if_ath.c,v 1.9 2008/05/14 11:59:18 sephe Exp $
41 * Driver for the Atheros Wireless LAN controller.
43 * This software is derived from work of Atsushi Onoe; his contribution
44 * is greatly appreciated.
49 #include <sys/param.h>
50 #include <sys/systm.h>
51 #include <sys/sysctl.h>
53 #include <sys/malloc.h>
54 #include <sys/kernel.h>
55 #include <sys/socket.h>
56 #include <sys/sockio.h>
57 #include <sys/errno.h>
58 #include <sys/callout.h>
60 #include <sys/endian.h>
61 #include <sys/kthread.h>
62 #include <sys/serialize.h>
65 #include <sys/interrupt.h>
68 #include <net/if_dl.h>
69 #include <net/if_media.h>
70 #include <net/if_types.h>
71 #include <net/if_arp.h>
72 #include <net/ethernet.h>
73 #include <net/if_llc.h>
74 #include <net/ifq_var.h>
76 #include <netproto/802_11/ieee80211_var.h>
84 #include <dev/netif/ath/ath/if_athvar.h>
85 #include <dev/netif/ath/hal/ath_hal/ah_desc.h>
86 #include <dev/netif/ath/hal/ath_hal/ah_devid.h> /* XXX for softled */
88 /* unaligned little endian access */
89 #define LE_READ_2(p) \
91 ((((uint8_t *)(p))[0] ) | (((uint8_t *)(p))[1] << 8)))
92 #define LE_READ_4(p) \
94 ((((uint8_t *)(p))[0] ) | (((uint8_t *)(p))[1] << 8) | \
95 (((uint8_t *)(p))[2] << 16) | (((uint8_t *)(p))[3] << 24)))
103 static void ath_init(void *);
104 static void ath_stop_no_pwchg(struct ifnet *);
105 static void ath_stop(struct ifnet *);
106 static void ath_start(struct ifnet *);
107 static int ath_reset(struct ifnet *);
108 static int ath_media_change(struct ifnet *);
109 static void ath_watchdog(struct ifnet *);
110 static int ath_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
111 static void ath_fatal_proc(struct ath_softc *);
112 static void ath_rxorn_proc(struct ath_softc *);
113 static void ath_bmiss_proc(struct ath_softc *);
114 static int ath_key_alloc(struct ieee80211com *,
115 const struct ieee80211_key *,
116 ieee80211_keyix *, ieee80211_keyix *);
117 static int ath_key_delete(struct ieee80211com *,
118 const struct ieee80211_key *);
119 static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *,
120 const uint8_t mac[IEEE80211_ADDR_LEN]);
121 static void ath_key_update_begin(struct ieee80211com *);
122 static void ath_key_update_end(struct ieee80211com *);
123 static void ath_mode_init(struct ath_softc *);
124 static void ath_setslottime(struct ath_softc *);
125 static void ath_updateslot(struct ifnet *);
126 static int ath_beaconq_setup(struct ath_hal *);
127 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *);
128 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *);
129 static void ath_beacon_proc(struct ath_softc *);
130 static void ath_bstuck_proc(struct ath_softc *);
131 static void ath_beacon_free(struct ath_softc *);
132 static void ath_beacon_config(struct ath_softc *);
133 static void ath_descdma_cleanup(struct ath_softc *sc,
134 struct ath_descdma *, ath_bufhead *);
135 static int ath_desc_alloc(struct ath_softc *);
136 static void ath_desc_free(struct ath_softc *);
137 static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *);
138 static void ath_node_free(struct ieee80211_node *);
139 static uint8_t ath_node_getrssi(const struct ieee80211_node *);
140 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *);
141 static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m,
142 struct ieee80211_node *ni,
143 int subtype, int rssi, uint32_t rstamp);
144 static void ath_setdefantenna(struct ath_softc *, u_int);
145 static void ath_rx_proc(struct ath_softc *);
146 static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int);
147 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype);
148 static int ath_tx_setup(struct ath_softc *, int, int);
149 static int ath_wme_update(struct ieee80211com *);
150 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *);
151 static void ath_tx_cleanup(struct ath_softc *);
152 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *,
153 struct ath_buf *, struct mbuf *);
154 static void ath_tx_proc_q0(struct ath_softc *);
155 static void ath_tx_proc_q0123(struct ath_softc *);
156 static void ath_tx_proc(struct ath_softc *);
157 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *);
158 static void ath_draintxq(struct ath_softc *);
159 static void ath_stoprecv(struct ath_softc *);
160 static int ath_startrecv(struct ath_softc *);
161 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *);
162 static void ath_next_scan(void *);
163 static void ath_calibrate(void *);
164 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int);
165 static void ath_setup_stationkey(struct ieee80211_node *);
166 static void ath_newassoc(struct ieee80211_node *, int);
167 static int ath_getchannels(struct ath_softc *, u_int cc,
168 HAL_BOOL outdoor, HAL_BOOL xchanmode);
169 static void ath_led_event(struct ath_softc *, int);
170 static void ath_update_txpow(struct ath_softc *);
172 static int ath_rate_setup(struct ath_softc *, u_int mode);
173 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode);
175 static void ath_sysctlattach(struct ath_softc *);
176 static void ath_bpfattach(struct ath_softc *);
177 static void ath_announce(struct ath_softc *);
179 static void ath_dma_map_mbuf(void *, bus_dma_segment_t *, int, bus_size_t,
182 SYSCTL_DECL(_hw_ath);
184 /* XXX validate sysctl values */
185 static int ath_dwelltime = 200; /* 5 channels/second */
186 SYSCTL_INT(_hw_ath, OID_AUTO, dwell, CTLFLAG_RW, &ath_dwelltime,
187 0, "channel dwell time (ms) for AP/station scanning");
188 static int ath_calinterval = 30; /* calibrate every 30 secs */
189 SYSCTL_INT(_hw_ath, OID_AUTO, calibrate, CTLFLAG_RW, &ath_calinterval,
190 0, "chip calibration interval (secs)");
191 static int ath_outdoor = AH_TRUE; /* outdoor operation */
192 SYSCTL_INT(_hw_ath, OID_AUTO, outdoor, CTLFLAG_RD, &ath_outdoor,
193 0, "outdoor operation");
194 TUNABLE_INT("hw.ath.outdoor", &ath_outdoor);
195 static int ath_xchanmode = AH_TRUE; /* extended channel use */
196 SYSCTL_INT(_hw_ath, OID_AUTO, xchanmode, CTLFLAG_RD, &ath_xchanmode,
197 0, "extended channel mode");
198 TUNABLE_INT("hw.ath.xchanmode", &ath_xchanmode);
199 static int ath_countrycode = CTRY_DEFAULT; /* country code */
200 SYSCTL_INT(_hw_ath, OID_AUTO, countrycode, CTLFLAG_RD, &ath_countrycode,
202 TUNABLE_INT("hw.ath.countrycode", &ath_countrycode);
203 static int ath_regdomain = 0; /* regulatory domain */
204 SYSCTL_INT(_hw_ath, OID_AUTO, regdomain, CTLFLAG_RD, &ath_regdomain,
205 0, "regulatory domain");
207 static int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */
208 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RD, &ath_rxbuf,
209 0, "rx buffers allocated");
210 TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf);
211 static int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */
212 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RD, &ath_txbuf,
213 0, "tx buffers allocated");
214 TUNABLE_INT("hw.ath.txbuf", &ath_txbuf);
217 static int ath_debug = 0;
218 SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug,
219 0, "control debugging kprintfs");
220 TUNABLE_INT("hw.ath.debug", &ath_debug);
222 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
223 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */
224 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */
225 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */
226 ATH_DEBUG_RATE = 0x00000010, /* rate control */
227 ATH_DEBUG_RESET = 0x00000020, /* reset processing */
228 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */
229 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */
230 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */
231 ATH_DEBUG_INTR = 0x00001000, /* ISR */
232 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */
233 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */
234 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */
235 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */
236 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */
237 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */
238 ATH_DEBUG_NODE = 0x00080000, /* node management */
239 ATH_DEBUG_LED = 0x00100000, /* led management */
240 ATH_DEBUG_FF = 0x00200000, /* fast frames */
241 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */
242 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */
243 ATH_DEBUG_ANY = 0xffffffff
245 #define IFF_DUMPPKTS(sc, m) \
246 ((sc->sc_debug & (m)) || \
247 (sc->sc_ic.ic_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
248 #define DPRINTF(sc, m, fmt, ...) do { \
249 if (sc->sc_debug & (m)) \
250 kprintf(fmt, __VA_ARGS__); \
252 #define KEYPRINTF(sc, ix, hk, mac) do { \
253 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \
254 ath_keyprint(sc, __func__, ix, hk, mac); \
256 static void ath_printrxbuf(const struct ath_buf *bf, u_int ix, int);
257 static void ath_printtxbuf(const struct ath_buf *bf, u_int qnum, u_int ix, int done);
259 #define IFF_DUMPPKTS(sc, m) \
260 ((sc->sc_ic.ic_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
261 #define DPRINTF(sc, m, fmt, ...) do { \
264 #define KEYPRINTF(sc, k, ix, mac) do { \
269 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers");
272 ath_attach(uint16_t devid, struct ath_softc *sc)
274 struct ieee80211com *ic = &sc->sc_ic;
275 struct ifnet *ifp = &ic->ic_if;
276 struct ath_hal *ah = NULL;
280 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid);
282 /* set these up early for if_printf use */
283 if_initname(ifp, device_get_name(sc->sc_dev),
284 device_get_unit(sc->sc_dev));
287 * Mark device invalid so any interrupts (shared or otherwise)
288 * that arrive before the HAL is setup are discarded.
293 * Arrange interrupt line.
296 sc->sc_irq = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ,
298 RF_SHAREABLE | RF_ACTIVE);
299 if (sc->sc_irq == NULL) {
300 if_printf(ifp, "could not map interrupt\n");
304 sysctl_ctx_init(&sc->sc_sysctl_ctx);
305 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
306 SYSCTL_STATIC_CHILDREN(_hw),
308 device_get_nameunit(sc->sc_dev),
310 if (sc->sc_sysctl_tree == NULL) {
311 if_printf(ifp, "could not add sysctl node\n");
316 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status);
318 if_printf(ifp, "unable to attach hardware; HAL status %u\n",
325 if (ah->ah_abi != HAL_ABI_VERSION) {
326 if_printf(ifp, "HAL ABI mismatch detected "
327 "(HAL:0x%x != driver:0x%x)\n",
328 ah->ah_abi, HAL_ABI_VERSION);
332 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */
335 * Check if the MAC has multi-rate retry support.
336 * We do this by trying to setup a fake extended
337 * descriptor. MAC's that don't have support will
338 * return false w/o doing anything. MAC's that do
339 * support it will return true w/o doing anything.
341 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0);
344 * Check if the device has hardware counters for PHY
345 * errors. If so we need to enable the MIB interrupt
346 * so we can act on stat triggers.
348 if (ath_hal_hwphycounters(ah))
352 * Get the hardware key cache size.
354 sc->sc_keymax = ath_hal_keycachesize(ah);
355 if (sc->sc_keymax > ATH_KEYMAX) {
356 if_printf(ifp, "Warning, using only %u of %u key cache slots\n",
357 ATH_KEYMAX, sc->sc_keymax);
358 sc->sc_keymax = ATH_KEYMAX;
361 * Reset the key cache since some parts do not
362 * reset the contents on initial power up.
364 for (i = 0; i < sc->sc_keymax; i++)
365 ath_hal_keyreset(ah, i);
368 * Collect the channel list using the default country
369 * code and including outdoor channels. The 802.11 layer
370 * is resposible for filtering this list based on settings
373 error = ath_getchannels(sc, ath_countrycode,
374 ath_outdoor, ath_xchanmode);
379 * Setup rate tables for all potential media types.
381 ath_rate_setup(sc, IEEE80211_MODE_11A);
382 ath_rate_setup(sc, IEEE80211_MODE_11B);
383 ath_rate_setup(sc, IEEE80211_MODE_11G);
384 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A);
385 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G);
387 /* NB: setup here so ath_rate_update is happy */
388 ath_setcurmode(sc, IEEE80211_MODE_11A);
391 * Allocate tx+rx descriptors and populate the lists.
393 error = ath_desc_alloc(sc);
395 if_printf(ifp, "failed to allocate descriptors: %d\n", error);
399 callout_init(&sc->sc_scan_ch);
400 callout_init(&sc->sc_cal_ch);
401 callout_init(&sc->sc_dfs_ch);
404 * Allocate hardware transmit queues: one queue for
405 * beacon frames and one data queue for each QoS
406 * priority. Note that the hal handles reseting
407 * these queues at the needed time.
411 sc->sc_bhalq = ath_beaconq_setup(ah);
412 if (sc->sc_bhalq == (u_int)-1) {
413 if_printf(ifp, "unable to setup a beacon xmit queue!\n");
418 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
419 if (sc->sc_cabq == NULL) {
420 if_printf(ifp, "unable to setup CAB xmit queue!\n");
425 ath_txq_init(sc, &sc->sc_mcastq, -1); /* NB: s/w q, qnum not used */
427 /* NB: insure BK queue is the lowest priority h/w queue */
428 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) {
429 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n",
430 ieee80211_wme_acnames[WME_AC_BK]);
434 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) ||
435 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) ||
436 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) {
438 * Not enough hardware tx queues to properly do WME;
439 * just punt and assign them all to the same h/w queue.
440 * We could do a better job of this if, for example,
441 * we allocate queues when we switch from station to
444 if (sc->sc_ac2q[WME_AC_VI] != NULL)
445 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]);
446 if (sc->sc_ac2q[WME_AC_BE] != NULL)
447 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]);
448 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK];
449 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK];
450 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK];
454 * Special case certain configurations. Note the
455 * CAB queue is handled by these specially so don't
456 * include them when checking the txq setup mask.
458 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) {
460 sc->sc_tx_proc = ath_tx_proc_q0;
462 if_printf(ifp, "single TX queue\n");
465 sc->sc_tx_proc = ath_tx_proc_q0123;
467 if_printf(ifp, "four TX queues\n");
470 sc->sc_tx_proc = ath_tx_proc;
475 * Setup rate control. Some rate control modules
476 * call back to change the anntena state so expose
477 * the necessary entry points.
478 * XXX maybe belongs in struct ath_ratectrl?
480 sc->sc_setdefantenna = ath_setdefantenna;
481 sc->sc_rc = ath_rate_attach(sc);
482 if (sc->sc_rc == NULL) {
489 sc->sc_ledon = 0; /* low true */
490 sc->sc_ledidle = (2700 * hz) / 1000; /* 2.7sec */
491 callout_init(&sc->sc_ledtimer);
494 * Auto-enable soft led processing for IBM cards and for
495 * 5211 minipci cards. Users can also manually enable/disable
496 * support with a sysctl.
498 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID);
499 if (sc->sc_softled) {
500 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin);
501 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon);
505 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
506 ifp->if_start = ath_start;
507 ifp->if_watchdog = ath_watchdog;
508 ifp->if_ioctl = ath_ioctl;
509 ifp->if_init = ath_init;
510 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
511 ifq_set_ready(&ifp->if_snd);
513 ic->ic_reset = ath_reset;
514 ic->ic_newassoc = ath_newassoc;
515 ic->ic_updateslot = ath_updateslot;
516 ic->ic_wme.wme_update = ath_wme_update;
517 /* XXX not right but it's not used anywhere important */
518 ic->ic_phytype = IEEE80211_T_OFDM;
519 ic->ic_opmode = IEEE80211_M_STA;
521 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
522 | IEEE80211_C_HOSTAP /* hostap mode */
523 | IEEE80211_C_MONITOR /* monitor mode */
524 | IEEE80211_C_AHDEMO /* adhoc demo mode */
525 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
526 | IEEE80211_C_SHSLOT /* short slot time supported */
527 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
530 * Query the hal to figure out h/w crypto support.
532 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP))
533 ic->ic_caps |= IEEE80211_C_WEP;
534 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB))
535 ic->ic_caps |= IEEE80211_C_AES;
536 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM))
537 ic->ic_caps |= IEEE80211_C_AES_CCM;
538 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP))
539 ic->ic_caps |= IEEE80211_C_CKIP;
540 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) {
541 ic->ic_caps |= IEEE80211_C_TKIP;
543 * Check if h/w does the MIC and/or whether the
544 * separate key cache entries are required to
545 * handle both tx+rx MIC keys.
547 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC))
548 ic->ic_caps |= IEEE80211_C_TKIPMIC;
550 * If the h/w supports storing tx+rx MIC keys
551 * in one cache slot automatically enable use.
553 if (ath_hal_hastkipsplit(ah) ||
554 !ath_hal_settkipsplit(ah, AH_FALSE))
557 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR);
558 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah);
560 * Mark key cache slots associated with global keys
561 * as in use. If we knew TKIP was not to be used we
562 * could leave the +32, +64, and +32+64 slots free.
564 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
565 setbit(sc->sc_keymap, i);
566 setbit(sc->sc_keymap, i+64);
567 if (sc->sc_splitmic) {
568 setbit(sc->sc_keymap, i+32);
569 setbit(sc->sc_keymap, i+32+64);
573 * TPC support can be done either with a global cap or
574 * per-packet support. The latter is not available on
575 * all parts. We're a bit pedantic here as all parts
576 * support a global cap.
578 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah))
579 ic->ic_caps |= IEEE80211_C_TXPMGT;
582 * Mark WME capability only if we have sufficient
583 * hardware queues to do proper priority scheduling.
585 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK])
586 ic->ic_caps |= IEEE80211_C_WME;
588 * Check for misc other capabilities.
590 if (ath_hal_hasbursting(ah))
591 ic->ic_caps |= IEEE80211_C_BURST;
594 * Indicate we need the 802.11 header padded to a
595 * 32-bit boundary for 4-address and QoS frames.
597 ic->ic_flags |= IEEE80211_F_DATAPAD;
600 * Query the hal about antenna support.
602 sc->sc_defant = ath_hal_getdefantenna(ah);
605 * Not all chips have the VEOL support we want to
606 * use with IBSS beacons; check here for it.
608 sc->sc_hasveol = ath_hal_hasveol(ah);
610 /* get mac address from hardware */
611 ath_hal_getmac(ah, ic->ic_myaddr);
613 /* call MI attach routine. */
614 ieee80211_ifattach(ic);
615 sc->sc_opmode = ic->ic_opmode;
616 /* override default methods */
617 ic->ic_node_alloc = ath_node_alloc;
618 sc->sc_node_free = ic->ic_node_free;
619 ic->ic_node_free = ath_node_free;
620 ic->ic_node_getrssi = ath_node_getrssi;
621 sc->sc_recv_mgmt = ic->ic_recv_mgmt;
622 ic->ic_recv_mgmt = ath_recv_mgmt;
623 sc->sc_newstate = ic->ic_newstate;
624 ic->ic_newstate = ath_newstate;
625 ic->ic_crypto.cs_max_keyix = sc->sc_keymax;
626 ic->ic_crypto.cs_key_alloc = ath_key_alloc;
627 ic->ic_crypto.cs_key_delete = ath_key_delete;
628 ic->ic_crypto.cs_key_set = ath_key_set;
629 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin;
630 ic->ic_crypto.cs_key_update_end = ath_key_update_end;
631 /* complete initialization */
632 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status);
636 * Setup dynamic sysctl's now that country code and
637 * regdomain are available from the hal.
639 ath_sysctlattach(sc);
641 error = bus_setup_intr(sc->sc_dev, sc->sc_irq, INTR_MPSAFE, ath_intr,
642 sc, &sc->sc_ih, ifp->if_serializer);
644 if_printf(ifp, "could not establish interrupt\n");
646 ieee80211_ifdetach(ic);
650 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->sc_irq));
651 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
654 ieee80211_announce(ic);
664 ath_detach(struct ath_softc *sc)
666 struct ifnet *ifp = &sc->sc_ic.ic_if;
668 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
669 __func__, ifp->if_flags);
672 * NB: the order of these is important:
673 * o call the 802.11 layer before detaching the hal to
674 * insure callbacks into the driver to delete global
675 * key cache entries can be handled
676 * o reclaim the tx queue data structures after calling
677 * the 802.11 layer as we'll get called back to reclaim
678 * node state and potentially want to use them
679 * o to cleanup the tx queues the hal is called, so detach
681 * Other than that, it's straightforward...
684 if (device_is_attached(sc->sc_dev)) {
685 lwkt_serialize_enter(ifp->if_serializer);
687 ath_rate_stop(sc->sc_rc);
690 * It seems power changing in ath_stop() will freeze
691 * ath_hal_releasetxqueue(), which is called by
692 * ath_tx_cleanup() below.
695 ath_stop_no_pwchg(ifp);
699 bus_teardown_intr(sc->sc_dev, sc->sc_irq, sc->sc_ih);
701 lwkt_serialize_exit(ifp->if_serializer);
704 ieee80211_ifdetach(&sc->sc_ic);
707 if (sc->sc_rc != NULL)
708 ath_rate_detach(sc->sc_rc);
715 ath_hal_detach(sc->sc_ah);
717 if (sc->sc_irq != NULL) {
718 bus_release_resource(sc->sc_dev, SYS_RES_IRQ, sc->sc_irq_rid,
722 if (sc->sc_sysctl_tree != NULL)
723 sysctl_ctx_free(&sc->sc_sysctl_ctx);
729 ath_suspend(struct ath_softc *sc)
731 struct ifnet *ifp = &sc->sc_ic.ic_if;
733 lwkt_serialize_enter(ifp->if_serializer);
735 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
736 __func__, ifp->if_flags);
739 lwkt_serialize_exit(ifp->if_serializer);
743 ath_resume(struct ath_softc *sc)
745 struct ifnet *ifp = &sc->sc_ic.ic_if;
747 lwkt_serialize_enter(ifp->if_serializer);
749 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
750 __func__, ifp->if_flags);
752 if (ifp->if_flags & IFF_UP) {
754 if (ifp->if_flags & IFF_RUNNING)
757 if (sc->sc_softled) {
758 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin);
759 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
762 lwkt_serialize_exit(ifp->if_serializer);
766 ath_shutdown(struct ath_softc *sc)
768 struct ifnet *ifp = &sc->sc_ic.ic_if;
770 lwkt_serialize_enter(ifp->if_serializer);
772 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
773 __func__, ifp->if_flags);
776 lwkt_serialize_exit(ifp->if_serializer);
780 * Interrupt handler. Most of the actual processing is deferred.
785 struct ath_softc *sc = arg;
786 struct ifnet *ifp = &sc->sc_ic.ic_if;
787 struct ath_hal *ah = sc->sc_ah;
790 if (sc->sc_invalid) {
792 * The hardware is not ready/present, don't touch anything.
793 * Note this can happen early on if the IRQ is shared.
795 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__);
798 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */
800 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) !=
801 (IFF_UP | IFF_RUNNING)) {
802 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
803 __func__, ifp->if_flags);
804 ath_hal_getisr(ah, &status); /* clear ISR */
805 ath_hal_intrset(ah, 0); /* disable further intr's */
809 * Figure out the reason(s) for the interrupt. Note
810 * that the hal returns a pseudo-ISR that may include
811 * bits we haven't explicitly enabled so we mask the
812 * value to insure we only process bits we requested.
814 ath_hal_getisr(ah, &status); /* NB: clears ISR too */
815 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status);
816 status &= sc->sc_imask; /* discard unasked for bits */
817 if (status & HAL_INT_FATAL) {
819 * Fatal errors are unrecoverable. Typically
820 * these are caused by DMA errors. Unfortunately
821 * the exact reason is not (presently) returned
824 sc->sc_stats.ast_hardware++;
825 ath_hal_intrset(ah, 0); /* disable intr's until reset */
827 } else if (status & HAL_INT_RXORN) {
828 sc->sc_stats.ast_rxorn++;
829 ath_hal_intrset(ah, 0); /* disable intr's until reset */
832 if (status & HAL_INT_SWBA) {
834 * Software beacon alert--time to send a beacon.
835 * Handle beacon transmission directly; deferring
836 * this is too slow to meet timing constraints
841 if (status & HAL_INT_RXEOL) {
843 * NB: the hardware should re-read the link when
844 * RXE bit is written, but it doesn't work at
845 * least on older hardware revs.
847 sc->sc_stats.ast_rxeol++;
848 sc->sc_rxlink = NULL;
850 if (status & HAL_INT_TXURN) {
851 sc->sc_stats.ast_txurn++;
852 /* bump tx trigger level */
853 ath_hal_updatetxtriglevel(ah, AH_TRUE);
855 if (status & HAL_INT_RX)
857 if (status & HAL_INT_TX)
859 if (status & HAL_INT_BMISS) {
860 sc->sc_stats.ast_bmiss++;
863 if (status & HAL_INT_MIB) {
864 sc->sc_stats.ast_mib++;
866 * Disable interrupts until we service the MIB
867 * interrupt; otherwise it will continue to fire.
869 ath_hal_intrset(ah, 0);
871 * Let the hal handle the event. We assume it will
872 * clear whatever condition caused the interrupt.
874 ath_hal_mibevent(ah, &sc->sc_halstats);
875 ath_hal_intrset(ah, sc->sc_imask);
881 ath_fatal_proc(struct ath_softc *sc)
883 struct ifnet *ifp = &sc->sc_ic.ic_if;
887 if_printf(ifp, "hardware error; resetting\n");
890 * Fatal errors are unrecoverable. Typically these
891 * are caused by DMA errors. Collect h/w state from
892 * the hal so we can diagnose what's going on.
894 if (ath_hal_getfatalstate(sc->sc_ah, &state, &len)) {
895 KASSERT(len >= (6 * sizeof(uint32_t)), ("len %u bytes", len));
896 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n",
897 state[0], state[1] , state[2], state[3],
905 ath_rxorn_proc(struct ath_softc *sc)
907 struct ifnet *ifp = &sc->sc_ic.ic_if;
909 if_printf(ifp, "rx FIFO overrun; resetting\n");
914 ath_bmiss_proc(struct ath_softc *sc)
916 struct ieee80211com *ic = &sc->sc_ic;
918 DPRINTF(sc, ATH_DEBUG_ANY, "%s\n", __func__);
919 KASSERT(ic->ic_opmode == IEEE80211_M_STA,
920 ("unexpect operating mode %u", ic->ic_opmode));
921 if (ic->ic_state == IEEE80211_S_RUN) {
922 uint64_t lastrx = sc->sc_lastrx;
923 uint64_t tsf = ath_hal_gettsf64(sc->sc_ah);
925 ic->ic_bmissthreshold * ic->ic_bss->ni_intval * 1024;
927 DPRINTF(sc, ATH_DEBUG_BEACON,
928 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n",
929 __func__, (unsigned long long) tsf,
930 (unsigned long long)(tsf - lastrx),
931 (unsigned long long) lastrx, bmisstimeout);
933 * Workaround phantom bmiss interrupts by sanity-checking
934 * the time of our last rx'd frame. If it is within the
935 * beacon miss interval then ignore the interrupt. If it's
936 * truly a bmiss we'll get another interrupt soon and that'll
937 * be dispatched up for processing.
939 if (tsf - lastrx > bmisstimeout)
940 ieee80211_beacon_miss(ic);
942 sc->sc_stats.ast_bmiss_phantom++;
947 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan)
949 #define N(a) (sizeof(a) / sizeof(a[0]))
950 static const u_int modeflags[] = {
951 0, /* IEEE80211_MODE_AUTO */
952 CHANNEL_A, /* IEEE80211_MODE_11A */
953 CHANNEL_B, /* IEEE80211_MODE_11B */
954 CHANNEL_PUREG, /* IEEE80211_MODE_11G */
955 0, /* IEEE80211_MODE_FH */
956 CHANNEL_ST, /* IEEE80211_MODE_TURBO_A */
957 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */
959 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan);
961 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode));
962 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode));
963 return modeflags[mode];
967 /* XXX error cleanup */
971 struct ath_softc *sc = arg;
972 struct ieee80211com *ic = &sc->sc_ic;
973 struct ifnet *ifp = &ic->ic_if;
974 struct ath_hal *ah = sc->sc_ah;
977 ASSERT_SERIALIZED(ifp->if_serializer);
979 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
980 __func__, ifp->if_flags);
983 * Stop anything previously setup. This is safe
984 * whether this is the first time through or not.
986 ath_stop_no_pwchg(ifp);
989 * The basic interface to setting the hardware in a good
990 * state is ``reset''. On return the hardware is known to
991 * be powered up and with interrupts disabled. This must
992 * be followed by initialization of the appropriate bits
993 * and then setup of the interrupt mask.
995 sc->sc_curchan.channel = ic->ic_curchan->ic_freq;
996 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan);
997 if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_FALSE,
999 if_printf(ifp, "unable to reset hardware; hal status %u\n",
1005 * This is needed only to setup initial state
1006 * but it's best done after a reset.
1008 ath_update_txpow(sc);
1010 * Likewise this is set during reset so update
1011 * state cached in the driver.
1013 sc->sc_diversity = ath_hal_getdiversity(ah);
1014 sc->sc_calinterval = 1;
1015 sc->sc_caltries = 0;
1018 * Setup the hardware after reset: the key cache
1019 * is filled as needed and the receive engine is
1020 * set going. Frame transmit is handled entirely
1021 * in the frame output path; there's nothing to do
1022 * here except setup the interrupt mask.
1024 if (ath_startrecv(sc) != 0) {
1025 if_printf(ifp, "unable to start recv logic\n");
1030 * Enable interrupts.
1032 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
1033 | HAL_INT_RXEOL | HAL_INT_RXORN
1034 | HAL_INT_FATAL | HAL_INT_GLOBAL;
1036 * Enable MIB interrupts when there are hardware phy counters.
1037 * Note we only do this (at the moment) for station mode.
1039 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA)
1040 sc->sc_imask |= HAL_INT_MIB;
1041 ath_hal_intrset(ah, sc->sc_imask);
1043 ifp->if_flags |= IFF_RUNNING;
1044 ic->ic_state = IEEE80211_S_INIT;
1047 * The hardware should be ready to go now so it's safe
1048 * to kick the 802.11 state machine as it's likely to
1049 * immediately call back to us to send mgmt frames.
1051 ath_chan_change(sc, ic->ic_curchan);
1052 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1053 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
1054 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
1056 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
1061 ath_stop_no_pwchg(struct ifnet *ifp)
1063 struct ath_softc *sc = ifp->if_softc;
1064 struct ieee80211com *ic = &sc->sc_ic;
1065 struct ath_hal *ah = sc->sc_ah;
1067 ASSERT_SERIALIZED(ifp->if_serializer);
1069 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n",
1070 __func__, sc->sc_invalid, ifp->if_flags);
1072 if (ifp->if_flags & IFF_RUNNING) {
1074 * Shutdown the hardware and driver:
1075 * reset 802.11 state machine
1077 * disable interrupts
1078 * turn off the radio
1079 * clear transmit machinery
1080 * clear receive machinery
1081 * drain and release tx queues
1082 * reclaim beacon resources
1083 * power down hardware
1085 * Note that some of this work is not possible if the
1086 * hardware is gone (invalid).
1088 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
1089 ifp->if_flags &= ~IFF_RUNNING;
1091 if (!sc->sc_invalid) {
1092 if (sc->sc_softled) {
1093 callout_stop(&sc->sc_ledtimer);
1094 ath_hal_gpioset(ah, sc->sc_ledpin,
1096 sc->sc_blinking = 0;
1098 ath_hal_intrset(ah, 0);
1101 if (!sc->sc_invalid) {
1103 ath_hal_phydisable(ah);
1105 sc->sc_rxlink = NULL;
1107 ifq_purge(&ifp->if_snd);
1109 ath_beacon_free(sc);
1114 ath_stop(struct ifnet *ifp)
1116 struct ath_softc *sc = ifp->if_softc;
1118 ASSERT_SERIALIZED(ifp->if_serializer);
1120 ath_stop_no_pwchg(ifp);
1121 if (!sc->sc_invalid) {
1123 * Set the chip in full sleep mode. Note that we are
1124 * careful to do this only when bringing the interface
1125 * completely to a stop. When the chip is in this state
1126 * it must be carefully woken up or references to
1127 * registers in the PCI clock domain may freeze the bus
1128 * (and system). This varies by chip and is mostly an
1129 * issue with newer parts that go to sleep more quickly.
1131 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP);
1136 * Reset the hardware w/o losing operational state. This is
1137 * basically a more efficient way of doing ath_stop, ath_init,
1138 * followed by state transitions to the current 802.11
1139 * operational state. Used to recover from various errors and
1140 * to reset or reload hardware state.
1143 ath_reset(struct ifnet *ifp)
1145 struct ath_softc *sc = ifp->if_softc;
1146 struct ieee80211com *ic = &sc->sc_ic;
1147 struct ath_hal *ah = sc->sc_ah;
1148 struct ieee80211_channel *c;
1151 ASSERT_SERIALIZED(ifp->if_serializer);
1154 * Convert to a HAL channel description with the flags
1155 * constrained to reflect the current operating mode.
1158 sc->sc_curchan.channel = c->ic_freq;
1159 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c);
1161 ath_hal_intrset(ah, 0); /* disable interrupts */
1162 ath_draintxq(sc); /* stop xmit side */
1163 ath_stoprecv(sc); /* stop recv side */
1164 /* NB: indicate channel change so we do a full reset */
1165 if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_TRUE,
1167 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n",
1170 ath_update_txpow(sc); /* update tx power state */
1171 sc->sc_diversity = ath_hal_getdiversity(ah);
1172 sc->sc_calinterval = 1;
1173 sc->sc_caltries = 0;
1175 * We may be doing a reset in response to an ioctl
1176 * that changes the channel so update any state that
1177 * might change as a result.
1179 ath_chan_change(sc, c);
1180 if (ath_startrecv(sc) != 0) /* restart recv */
1181 if_printf(ifp, "%s: unable to start recv logic\n", __func__);
1182 if (ic->ic_state == IEEE80211_S_RUN)
1183 ath_beacon_config(sc); /* restart beacons */
1184 ath_hal_intrset(ah, sc->sc_imask);
1186 ifp->if_start(ifp); /* restart xmit */
1191 ath_start(struct ifnet *ifp)
1193 struct ath_softc *sc = ifp->if_softc;
1194 struct ath_hal *ah = sc->sc_ah;
1195 struct ieee80211com *ic = &sc->sc_ic;
1196 struct ieee80211_node *ni;
1199 struct ieee80211_frame *wh;
1200 struct ether_header *eh;
1202 if (sc->sc_invalid) {
1203 ifq_purge(&ifp->if_snd);
1204 ieee80211_drain_mgtq(&ic->ic_mgtq);
1208 if ((ifp->if_flags & IFF_RUNNING) == 0)
1213 * Grab a TX buffer and associated resources.
1215 bf = STAILQ_FIRST(&sc->sc_txbuf);
1217 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list);
1219 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n",
1221 sc->sc_stats.ast_tx_qstop++;
1222 ifp->if_flags |= IFF_OACTIVE;
1226 * Poll the management queue for frames; they
1227 * have priority over normal data frames.
1229 IF_DEQUEUE(&ic->ic_mgtq, m);
1232 * No data frames go out unless we're associated.
1234 if (ic->ic_state != IEEE80211_S_RUN) {
1235 DPRINTF(sc, ATH_DEBUG_XMIT,
1236 "%s: discard data packet, state %s\n",
1238 ieee80211_state_name[ic->ic_state]);
1239 sc->sc_stats.ast_tx_discard++;
1240 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1241 ifq_purge(&ifp->if_snd);
1244 m = ifq_dequeue(&ifp->if_snd, NULL);
1246 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1250 * Find the node for the destination so we can do
1251 * things like power save and fast frames aggregation.
1253 if (m->m_len < sizeof(struct ether_header) &&
1254 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) {
1255 ic->ic_stats.is_tx_nobuf++; /* XXX */
1259 eh = mtod(m, struct ether_header *);
1260 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
1262 /* NB: ieee80211_find_txnode does stat+msg */
1266 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) &&
1267 (m->m_flags & M_PWR_SAV) == 0) {
1269 * Station in power save mode; pass the frame
1270 * to the 802.11 layer and continue. We'll get
1271 * the frame back when the time is right.
1273 ieee80211_pwrsave(ic, ni, m);
1276 /* calculate priority so we can find the tx queue */
1277 if (ieee80211_classify(ic, m, ni)) {
1278 DPRINTF(sc, ATH_DEBUG_XMIT,
1279 "%s: discard, classification failure\n",
1287 * Encapsulate the packet in prep for transmission.
1289 m = ieee80211_encap(ic, m, ni);
1291 DPRINTF(sc, ATH_DEBUG_XMIT,
1292 "%s: encapsulation failure\n",
1294 sc->sc_stats.ast_tx_encap++;
1299 * Hack! The referenced node pointer is in the
1300 * rcvif field of the packet header. This is
1301 * placed there by ieee80211_mgmt_output because
1302 * we need to hold the reference with the frame
1303 * and there's no other way (other than packet
1304 * tags which we consider too expensive to use)
1307 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1308 m->m_pkthdr.rcvif = NULL;
1310 wh = mtod(m, struct ieee80211_frame *);
1311 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
1312 IEEE80211_FC0_SUBTYPE_PROBE_RESP) {
1313 /* fill time stamp */
1317 tsf = ath_hal_gettsf64(ah);
1318 /* XXX: adjust 100us delay to xmit */
1320 tstamp = (uint32_t *)&wh[1];
1321 tstamp[0] = htole32(tsf & 0xffffffff);
1322 tstamp[1] = htole32(tsf >> 32);
1324 sc->sc_stats.ast_tx_mgmt++;
1327 if (ath_tx_start(sc, ni, bf, m)) {
1331 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1333 ieee80211_free_node(ni);
1337 sc->sc_tx_timer = 5;
1343 ath_media_change(struct ifnet *ifp)
1345 #define IS_UP(ifp) \
1346 ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_RUNNING | IFF_UP))
1349 error = ieee80211_media_change(ifp);
1350 if (error == ENETRESET) {
1351 struct ath_softc *sc = ifp->if_softc;
1352 struct ieee80211com *ic = &sc->sc_ic;
1354 if (ic->ic_opmode == IEEE80211_M_AHDEMO) {
1356 * Adhoc demo mode is just ibss mode w/o beacons
1357 * (mostly). The hal knows nothing about it;
1358 * tell it we're operating in ibss mode.
1360 sc->sc_opmode = HAL_M_IBSS;
1362 sc->sc_opmode = ic->ic_opmode;
1364 ath_init(ifp->if_softc); /* XXX lose error */
1373 ath_keyprint(struct ath_softc *sc, const char *tag, u_int ix,
1374 const HAL_KEYVAL *hk, const uint8_t mac[IEEE80211_ADDR_LEN])
1376 static const char *ciphers[] = {
1386 kprintf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]);
1387 for (i = 0, n = hk->kv_len; i < n; i++)
1388 kprintf("%02x", hk->kv_val[i]);
1389 kprintf(" mac %6D", mac, ":");
1390 if (hk->kv_type == HAL_CIPHER_TKIP) {
1391 kprintf(" %s ", sc->sc_splitmic ? "mic" : "rxmic");
1392 for (i = 0; i < sizeof(hk->kv_mic); i++)
1393 kprintf("%02x", hk->kv_mic[i]);
1394 #if HAL_ABI_VERSION > 0x06052200
1395 if (!sc->sc_splitmic) {
1397 for (i = 0; i < sizeof(hk->kv_txmic); i++)
1398 kprintf("%02x", hk->kv_txmic[i]);
1407 * Set a TKIP key into the hardware. This handles the
1408 * potential distribution of key state to multiple key
1409 * cache slots for TKIP.
1412 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k,
1413 HAL_KEYVAL *hk, const uint8_t mac[IEEE80211_ADDR_LEN])
1415 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV)
1416 static const uint8_t zerobssid[IEEE80211_ADDR_LEN];
1417 struct ath_hal *ah = sc->sc_ah;
1419 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP,
1420 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher));
1421 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) {
1422 if (sc->sc_splitmic) {
1424 * TX key goes at first index, RX key at the rx index.
1425 * The hal handles the MIC keys at index+64.
1427 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic));
1428 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid);
1429 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid))
1432 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic));
1433 KEYPRINTF(sc, k->wk_keyix+32, hk, mac);
1434 /* XXX delete tx key on failure? */
1435 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac);
1438 * Room for both TX+RX MIC keys in one key cache
1439 * slot, just set key at the first index; the hal
1440 * will handle the reset.
1442 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic));
1443 #if HAL_ABI_VERSION > 0x06052200
1444 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic));
1446 KEYPRINTF(sc, k->wk_keyix, hk, mac);
1447 return ath_hal_keyset(ah, k->wk_keyix, hk, mac);
1449 } else if (k->wk_flags & IEEE80211_KEY_XR) {
1451 * TX/RX key goes at first index.
1452 * The hal handles the MIC keys are index+64.
1454 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ?
1455 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic));
1456 KEYPRINTF(sc, k->wk_keyix, hk, mac);
1457 return ath_hal_keyset(ah, k->wk_keyix, hk, mac);
1460 #undef IEEE80211_KEY_XR
1464 * Set a net80211 key into the hardware. This handles the
1465 * potential distribution of key state to multiple key
1466 * cache slots for TKIP with hardware MIC support.
1469 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k,
1470 const uint8_t mac0[IEEE80211_ADDR_LEN],
1471 struct ieee80211_node *bss)
1473 #define N(a) (sizeof(a)/sizeof(a[0]))
1474 static const uint8_t ciphermap[] = {
1475 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */
1476 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */
1477 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */
1478 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */
1479 (uint8_t) -1, /* 4 is not allocated */
1480 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */
1481 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */
1483 struct ath_hal *ah = sc->sc_ah;
1484 const struct ieee80211_cipher *cip = k->wk_cipher;
1485 uint8_t gmac[IEEE80211_ADDR_LEN];
1489 memset(&hk, 0, sizeof(hk));
1491 * Software crypto uses a "clear key" so non-crypto
1492 * state kept in the key cache are maintained and
1493 * so that rx frames have an entry to match.
1495 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) {
1496 KASSERT(cip->ic_cipher < N(ciphermap),
1497 ("invalid cipher type %u", cip->ic_cipher));
1498 hk.kv_type = ciphermap[cip->ic_cipher];
1499 hk.kv_len = k->wk_keylen;
1500 memcpy(hk.kv_val, k->wk_key, k->wk_keylen);
1502 hk.kv_type = HAL_CIPHER_CLR;
1504 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) {
1506 * Group keys on hardware that supports multicast frame
1507 * key search use a mac that is the sender's address with
1508 * the high bit set instead of the app-specified address.
1510 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr);
1516 if (hk.kv_type == HAL_CIPHER_TKIP &&
1517 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) {
1518 return ath_keyset_tkip(sc, k, &hk, mac);
1520 KEYPRINTF(sc, k->wk_keyix, &hk, mac);
1521 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac);
1527 * Allocate tx/rx key slots for TKIP. We allocate two slots for
1528 * each key, one for decrypt/encrypt and the other for the MIC.
1531 key_alloc_2pair(struct ath_softc *sc,
1532 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
1534 #define N(a) (sizeof(a)/sizeof(a[0]))
1537 KASSERT(sc->sc_splitmic, ("key cache !split"));
1538 /* XXX could optimize */
1539 for (i = 0; i < N(sc->sc_keymap)/4; i++) {
1540 uint8_t b = sc->sc_keymap[i];
1543 * One or more slots in this byte are free.
1551 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */
1552 if (isset(sc->sc_keymap, keyix+32) ||
1553 isset(sc->sc_keymap, keyix+64) ||
1554 isset(sc->sc_keymap, keyix+32+64)) {
1555 /* full pair unavailable */
1557 if (keyix == (i+1)*NBBY) {
1558 /* no slots were appropriate, advance */
1563 setbit(sc->sc_keymap, keyix);
1564 setbit(sc->sc_keymap, keyix+64);
1565 setbit(sc->sc_keymap, keyix+32);
1566 setbit(sc->sc_keymap, keyix+32+64);
1567 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
1568 "%s: key pair %u,%u %u,%u\n",
1569 __func__, keyix, keyix+64,
1570 keyix+32, keyix+32+64);
1572 *rxkeyix = keyix+32;
1576 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__);
1582 * Allocate tx/rx key slots for TKIP. We allocate two slots for
1583 * each key, one for decrypt/encrypt and the other for the MIC.
1586 key_alloc_pair(struct ath_softc *sc,
1587 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
1589 #define N(a) (sizeof(a)/sizeof(a[0]))
1592 KASSERT(!sc->sc_splitmic, ("key cache split"));
1593 /* XXX could optimize */
1594 for (i = 0; i < N(sc->sc_keymap)/4; i++) {
1595 uint8_t b = sc->sc_keymap[i];
1598 * One or more slots in this byte are free.
1606 if (isset(sc->sc_keymap, keyix+64)) {
1607 /* full pair unavailable */
1609 if (keyix == (i+1)*NBBY) {
1610 /* no slots were appropriate, advance */
1615 setbit(sc->sc_keymap, keyix);
1616 setbit(sc->sc_keymap, keyix+64);
1617 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
1618 "%s: key pair %u,%u\n",
1619 __func__, keyix, keyix+64);
1620 *txkeyix = *rxkeyix = keyix;
1624 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__);
1630 * Allocate a single key cache slot.
1633 key_alloc_single(struct ath_softc *sc,
1634 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
1636 #define N(a) (sizeof(a)/sizeof(a[0]))
1639 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */
1640 for (i = 0; i < N(sc->sc_keymap); i++) {
1641 uint8_t b = sc->sc_keymap[i];
1644 * One or more slots are free.
1649 setbit(sc->sc_keymap, keyix);
1650 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n",
1652 *txkeyix = *rxkeyix = keyix;
1656 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__);
1662 * Allocate one or more key cache slots for a uniacst key. The
1663 * key itself is needed only to identify the cipher. For hardware
1664 * TKIP with split cipher+MIC keys we allocate two key cache slot
1665 * pairs so that we can setup separate TX and RX MIC keys. Note
1666 * that the MIC key for a TKIP key at slot i is assumed by the
1667 * hardware to be at slot i+64. This limits TKIP keys to the first
1671 ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k,
1672 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix)
1674 struct ath_softc *sc = ic->ic_ifp->if_softc;
1677 * Group key allocation must be handled specially for
1678 * parts that do not support multicast key cache search
1679 * functionality. For those parts the key id must match
1680 * the h/w key index so lookups find the right key. On
1681 * parts w/ the key search facility we install the sender's
1682 * mac address (with the high bit set) and let the hardware
1683 * find the key w/o using the key id. This is preferred as
1684 * it permits us to support multiple users for adhoc and/or
1685 * multi-station operation.
1687 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) {
1688 if (!(&ic->ic_nw_keys[0] <= k &&
1689 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) {
1690 /* should not happen */
1691 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
1692 "%s: bogus group key\n", __func__);
1696 * XXX we pre-allocate the global keys so
1697 * have no way to check if they've already been allocated.
1699 *keyix = *rxkeyix = k - ic->ic_nw_keys;
1704 * We allocate two pair for TKIP when using the h/w to do
1705 * the MIC. For everything else, including software crypto,
1706 * we allocate a single entry. Note that s/w crypto requires
1707 * a pass-through slot on the 5211 and 5212. The 5210 does
1708 * not support pass-through cache entries and we map all
1709 * those requests to slot 0.
1711 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) {
1712 return key_alloc_single(sc, keyix, rxkeyix);
1713 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP &&
1714 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) {
1715 if (sc->sc_splitmic)
1716 return key_alloc_2pair(sc, keyix, rxkeyix);
1718 return key_alloc_pair(sc, keyix, rxkeyix);
1720 return key_alloc_single(sc, keyix, rxkeyix);
1725 * Delete an entry in the key cache allocated by ath_key_alloc.
1728 ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k)
1730 struct ath_softc *sc = ic->ic_ifp->if_softc;
1731 struct ath_hal *ah = sc->sc_ah;
1732 const struct ieee80211_cipher *cip = k->wk_cipher;
1733 u_int keyix = k->wk_keyix;
1735 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix);
1737 ath_hal_keyreset(ah, keyix);
1739 * Handle split tx/rx keying required for TKIP with h/w MIC.
1741 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP &&
1742 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic)
1743 ath_hal_keyreset(ah, keyix+32); /* RX key */
1744 if (keyix >= IEEE80211_WEP_NKID) {
1746 * Don't touch keymap entries for global keys so
1747 * they are never considered for dynamic allocation.
1749 clrbit(sc->sc_keymap, keyix);
1750 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP &&
1751 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) {
1752 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */
1753 if (sc->sc_splitmic) {
1754 /* +32 for RX key, +32+64 for RX key MIC */
1755 clrbit(sc->sc_keymap, keyix+32);
1756 clrbit(sc->sc_keymap, keyix+32+64);
1764 * Set the key cache contents for the specified key. Key cache
1765 * slot(s) must already have been allocated by ath_key_alloc.
1768 ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k,
1769 const uint8_t mac[IEEE80211_ADDR_LEN])
1771 struct ath_softc *sc = ic->ic_ifp->if_softc;
1773 return ath_keyset(sc, k, mac, ic->ic_bss);
1777 * Block/unblock tx+rx processing while a key change is done.
1778 * We assume the caller serializes key management operations
1779 * so we only need to worry about synchronization with other
1780 * uses that originate in the driver.
1783 ath_key_update_begin(struct ieee80211com *ic)
1785 struct ifnet *ifp = ic->ic_ifp;
1786 struct ath_softc *sc = ifp->if_softc;
1788 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
1790 tasklet_disable(&sc->sc_rxtq);
1791 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */
1796 ath_key_update_end(struct ieee80211com *ic)
1798 struct ifnet *ifp = ic->ic_ifp;
1799 struct ath_softc *sc = ifp->if_softc;
1801 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
1803 IF_UNLOCK(&ifp->if_snd);
1804 tasklet_enable(&sc->sc_rxtq);
1809 * Calculate the receive filter according to the
1810 * operating mode and state:
1812 * o always accept unicast, broadcast, and multicast traffic
1813 * o maintain current state of phy error reception (the hal
1814 * may enable phy error frames for noise immunity work)
1815 * o probe request frames are accepted only when operating in
1816 * hostap, adhoc, or monitor modes
1817 * o enable promiscuous mode according to the interface state
1819 * - when operating in adhoc mode so the 802.11 layer creates
1820 * node table entries for peers,
1821 * - when operating in station mode for collecting rssi data when
1822 * the station is otherwise quiet, or
1824 * o accept control frames:
1825 * - when in monitor mode
1828 ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state)
1830 #define RX_FILTER_PRESERVE (HAL_RX_FILTER_PHYERR | HAL_RX_FILTER_PHYRADAR)
1831 struct ieee80211com *ic = &sc->sc_ic;
1832 struct ath_hal *ah = sc->sc_ah;
1833 struct ifnet *ifp = &ic->ic_if;
1836 rfilt = (ath_hal_getrxfilter(ah) & RX_FILTER_PRESERVE)
1837 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST;
1838 if (ic->ic_opmode != IEEE80211_M_STA)
1839 rfilt |= HAL_RX_FILTER_PROBEREQ;
1840 if (ic->ic_opmode != IEEE80211_M_HOSTAP &&
1841 (ifp->if_flags & IFF_PROMISC))
1842 rfilt |= HAL_RX_FILTER_PROM;
1843 if (ic->ic_opmode == IEEE80211_M_STA ||
1844 ic->ic_opmode == IEEE80211_M_IBSS ||
1845 state == IEEE80211_S_SCAN)
1846 rfilt |= HAL_RX_FILTER_BEACON;
1847 if (ic->ic_opmode == IEEE80211_M_MONITOR)
1848 rfilt |= HAL_RX_FILTER_CONTROL;
1850 #undef RX_FILTER_PRESERVE
1854 ath_mode_init(struct ath_softc *sc)
1856 struct ieee80211com *ic = &sc->sc_ic;
1857 struct ath_hal *ah = sc->sc_ah;
1858 struct ifnet *ifp = &ic->ic_if;
1859 uint32_t rfilt, mfilt[2], val;
1861 struct ifmultiaddr *ifma;
1863 /* configure rx filter */
1864 rfilt = ath_calcrxfilter(sc, ic->ic_state);
1865 ath_hal_setrxfilter(ah, rfilt);
1867 /* configure operational mode */
1868 ath_hal_setopmode(ah);
1871 * Handle any link-level address change. Note that we only
1872 * need to force ic_myaddr; any other addresses are handled
1873 * as a byproduct of the ifnet code marking the interface
1876 * XXX should get from lladdr instead of arpcom but that's more work
1878 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp));
1879 ath_hal_setmac(ah, ic->ic_myaddr);
1881 /* calculate and install multicast filter */
1882 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
1883 mfilt[0] = mfilt[1] = 0;
1884 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1887 /* calculate XOR of eight 6bit values */
1888 dl = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
1889 val = LE_READ_4(dl + 0);
1890 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
1891 val = LE_READ_4(dl + 3);
1892 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
1894 mfilt[pos / 32] |= (1 << (pos % 32));
1897 mfilt[0] = mfilt[1] = ~0;
1899 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]);
1900 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n",
1901 __func__, rfilt, mfilt[0], mfilt[1]);
1905 * Set the slot time based on the current setting.
1908 ath_setslottime(struct ath_softc *sc)
1910 struct ieee80211com *ic = &sc->sc_ic;
1911 struct ath_hal *ah = sc->sc_ah;
1913 if (ic->ic_flags & IEEE80211_F_SHSLOT)
1914 ath_hal_setslottime(ah, HAL_SLOT_TIME_9);
1916 ath_hal_setslottime(ah, HAL_SLOT_TIME_20);
1917 sc->sc_updateslot = OK;
1921 * Callback from the 802.11 layer to update the
1922 * slot time based on the current setting.
1925 ath_updateslot(struct ifnet *ifp)
1927 struct ath_softc *sc = ifp->if_softc;
1928 struct ieee80211com *ic = &sc->sc_ic;
1931 * When not coordinating the BSS, change the hardware
1932 * immediately. For other operation we defer the change
1933 * until beacon updates have propagated to the stations.
1935 if (ic->ic_opmode == IEEE80211_M_HOSTAP)
1936 sc->sc_updateslot = UPDATE;
1938 ath_setslottime(sc);
1942 * Setup a h/w transmit queue for beacons.
1945 ath_beaconq_setup(struct ath_hal *ah)
1949 memset(&qi, 0, sizeof(qi));
1950 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
1951 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
1952 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
1953 /* NB: for dynamic turbo, don't enable any other interrupts */
1954 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE;
1955 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi);
1959 * Setup the transmit queue parameters for the beacon queue.
1962 ath_beaconq_config(struct ath_softc *sc)
1964 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1)
1965 struct ieee80211com *ic = &sc->sc_ic;
1966 struct ath_hal *ah = sc->sc_ah;
1969 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi);
1970 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
1972 * Always burst out beacon and CAB traffic.
1974 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT;
1975 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT;
1976 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT;
1978 struct wmeParams *wmep =
1979 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE];
1981 * Adhoc mode; important thing is to use 2x cwmin.
1983 qi.tqi_aifs = wmep->wmep_aifsn;
1984 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
1985 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
1988 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) {
1989 device_printf(sc->sc_dev, "unable to update parameters for "
1990 "beacon hardware queue!\n");
1993 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */
1996 #undef ATH_EXPONENT_TO_VALUE
2000 * Allocate and setup an initial beacon frame.
2003 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni)
2005 struct ieee80211com *ic = ni->ni_ic;
2010 bf = STAILQ_FIRST(&sc->sc_bbuf);
2012 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__);
2013 sc->sc_stats.ast_be_nombuf++; /* XXX */
2014 return ENOMEM; /* XXX */
2017 * NB: the beacon data buffer must be 32-bit aligned;
2018 * we assume the mbuf routines will return us something
2019 * with this alignment (perhaps should assert).
2021 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff);
2023 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n",
2025 sc->sc_stats.ast_be_nombuf++;
2029 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m,
2030 ath_dma_map_mbuf, bf, BUS_DMA_NOWAIT);
2033 bf->bf_node = ieee80211_ref_node(ni);
2041 * Setup the beacon frame for transmit.
2044 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf)
2046 #define USE_SHPREAMBLE(_ic) \
2047 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\
2048 == IEEE80211_F_SHPREAMBLE)
2049 struct ieee80211_node *ni = bf->bf_node;
2050 struct ieee80211com *ic = ni->ni_ic;
2051 struct mbuf *m = bf->bf_m;
2052 struct ath_hal *ah = sc->sc_ah;
2053 struct ath_desc *ds;
2055 const HAL_RATE_TABLE *rt;
2058 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n",
2059 __func__, m, m->m_len);
2061 /* setup descriptors */
2064 flags = HAL_TXDESC_NOACK;
2065 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) {
2066 ds->ds_link = bf->bf_daddr; /* self-linked */
2067 flags |= HAL_TXDESC_VEOL;
2069 * Let hardware handle antenna switching.
2071 antenna = sc->sc_txantenna;
2075 * Switch antenna every 4 beacons.
2076 * XXX assumes two antenna
2078 antenna = sc->sc_txantenna != 0 ? sc->sc_txantenna
2079 : (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1);
2082 KASSERT(bf->bf_nseg == 1,
2083 ("multi-segment beacon frame; nseg %u", bf->bf_nseg));
2084 ds->ds_data = bf->bf_segs[0].ds_addr;
2086 * Calculate rate code.
2087 * XXX everything at min xmit rate
2089 rix = sc->sc_minrateix;
2090 rt = sc->sc_currates;
2091 rate = rt->info[rix].rateCode;
2092 if (USE_SHPREAMBLE(ic))
2093 rate |= rt->info[rix].shortPreamble;
2094 ath_hal_setuptxdesc(ah, ds
2095 , m->m_len + IEEE80211_CRC_LEN /* frame length */
2096 , sizeof(struct ieee80211_frame)/* header length */
2097 , HAL_PKT_TYPE_BEACON /* Atheros packet type */
2098 , ni->ni_txpower /* txpower XXX */
2099 , rate, 1 /* series 0 rate/tries */
2100 , HAL_TXKEYIX_INVALID /* no encryption */
2101 , antenna /* antenna mode */
2102 , flags /* no ack, veol for beacons */
2103 , 0 /* rts/cts rate */
2104 , 0 /* rts/cts duration */
2106 /* NB: beacon's BufLen must be a multiple of 4 bytes */
2107 ath_hal_filltxdesc(ah, ds
2108 , roundup(m->m_len, 4) /* buffer length */
2109 , AH_TRUE /* first segment */
2110 , AH_TRUE /* last segment */
2111 , ds /* first descriptor */
2113 #undef USE_SHPREAMBLE
2117 * Append the contents of src to dst; both queues
2118 * are assumed to be locked.
2121 ath_txqmove(struct ath_txq *dst, struct ath_txq *src)
2123 STAILQ_CONCAT(&dst->axq_q, &src->axq_q);
2124 dst->axq_link = src->axq_link;
2125 src->axq_link = NULL;
2126 dst->axq_depth += src->axq_depth;
2131 * Transmit a beacon frame at SWBA. Dynamic updates to the
2132 * frame contents are done as needed and the slot time is
2133 * also adjusted based on current state.
2136 ath_beacon_proc(struct ath_softc *sc)
2138 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf);
2139 struct ieee80211_node *ni = bf->bf_node;
2140 struct ieee80211com *ic = ni->ni_ic;
2141 struct ath_hal *ah = sc->sc_ah;
2142 struct ath_txq *cabq = sc->sc_cabq;
2144 int ncabq, nmcastq, error, otherant;
2146 if (ic->ic_opmode == IEEE80211_M_STA ||
2147 ic->ic_opmode == IEEE80211_M_MONITOR ||
2148 bf == NULL || bf->bf_m == NULL) {
2149 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n",
2150 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL);
2154 * Check if the previous beacon has gone out. If
2155 * not don't try to post another, skip this period
2156 * and wait for the next. Missed beacons indicate
2157 * a problem and should not occur. If we miss too
2158 * many consecutive beacons reset the device.
2160 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
2161 sc->sc_bmisscount++;
2162 DPRINTF(sc, ATH_DEBUG_BEACON,
2163 "%s: missed %u consecutive beacons\n",
2164 __func__, sc->sc_bmisscount);
2165 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */
2166 ath_bstuck_proc(sc);
2169 if (sc->sc_bmisscount != 0) {
2170 DPRINTF(sc, ATH_DEBUG_BEACON,
2171 "%s: resume beacon xmit after %u misses\n",
2172 __func__, sc->sc_bmisscount);
2173 sc->sc_bmisscount = 0;
2177 * Update dynamic beacon contents. If this returns
2178 * non-zero then we need to remap the memory because
2179 * the beacon frame changed size (probably because
2180 * of the TIM bitmap).
2183 nmcastq = sc->sc_mcastq.axq_depth;
2184 ncabq = ath_hal_numtxpending(ah, cabq->axq_qnum);
2185 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m,
2187 /* XXX too conservative? */
2188 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2189 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m,
2190 ath_dma_map_mbuf, bf,
2193 if_printf(ic->ic_ifp,
2194 "%s: bus_dmamap_load_mbuf failed, error %u\n",
2200 if (ncabq && (sc->sc_boff.bo_tim[4] & 1)) {
2202 * CABQ traffic from the previous DTIM is still pending.
2203 * This is ok for now but when there are multiple vap's
2204 * and we are using staggered beacons we'll want to drain
2205 * the cabq before loading frames for the different vap.
2207 DPRINTF(sc, ATH_DEBUG_BEACON,
2208 "%s: cabq did not drain, mcastq %u cabq %u/%u\n",
2209 __func__, nmcastq, ncabq, cabq->axq_depth);
2210 sc->sc_stats.ast_cabq_busy++;
2214 * Handle slot time change when a non-ERP station joins/leaves
2215 * an 11g network. The 802.11 layer notifies us via callback,
2216 * we mark updateslot, then wait one beacon before effecting
2217 * the change. This gives associated stations at least one
2218 * beacon interval to note the state change.
2221 if (sc->sc_updateslot == UPDATE)
2222 sc->sc_updateslot = COMMIT; /* commit next beacon */
2223 else if (sc->sc_updateslot == COMMIT)
2224 ath_setslottime(sc); /* commit change to h/w */
2227 * Check recent per-antenna transmit statistics and flip
2228 * the default antenna if noticeably more frames went out
2229 * on the non-default antenna.
2230 * XXX assumes 2 anntenae
2232 otherant = sc->sc_defant & 1 ? 2 : 1;
2233 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
2234 ath_setdefantenna(sc, otherant);
2235 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
2238 * Construct tx descriptor.
2240 ath_beacon_setup(sc, bf);
2243 * Stop any current dma and put the new frame on the queue.
2244 * This should never fail since we check above that no frames
2245 * are still pending on the queue.
2247 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) {
2248 DPRINTF(sc, ATH_DEBUG_ANY,
2249 "%s: beacon queue %u did not stop?\n",
2250 __func__, sc->sc_bhalq);
2252 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
2255 * Enable the CAB queue before the beacon queue to
2256 * insure cab frames are triggered by this beacon.
2258 if (sc->sc_boff.bo_tim_len && (sc->sc_boff.bo_tim[4] & 1)) {
2259 /* NB: only at DTIM */
2261 struct ath_buf *bfm;
2264 * Move frames from the s/w mcast q to the h/w cab q.
2266 bfm = STAILQ_FIRST(&sc->sc_mcastq.axq_q);
2267 if (cabq->axq_link != NULL) {
2268 *cabq->axq_link = bfm->bf_daddr;
2270 ath_hal_puttxbuf(ah, cabq->axq_qnum,
2273 ath_txqmove(cabq, &sc->sc_mcastq);
2275 sc->sc_stats.ast_cabq_xmit += nmcastq;
2277 /* NB: gated by beacon so safe to start here */
2278 ath_hal_txstart(ah, cabq->axq_qnum);
2280 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
2281 ath_hal_txstart(ah, sc->sc_bhalq);
2282 DPRINTF(sc, ATH_DEBUG_BEACON_PROC,
2283 "%s: TXDP[%u] = %p (%p)\n", __func__,
2284 sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc);
2286 sc->sc_stats.ast_be_xmit++;
2290 * Reset the hardware after detecting beacons have stopped.
2293 ath_bstuck_proc(struct ath_softc *sc)
2295 struct ifnet *ifp = &sc->sc_ic.ic_if;
2297 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n",
2303 * Reclaim beacon resources.
2306 ath_beacon_free(struct ath_softc *sc)
2310 ASSERT_SERIALIZED(sc->sc_ic.ic_if.if_serializer);
2312 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) {
2313 if (bf->bf_m != NULL) {
2314 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2318 if (bf->bf_node != NULL) {
2319 ieee80211_free_node(bf->bf_node);
2326 * Configure the beacon and sleep timers.
2328 * When operating as an AP this resets the TSF and sets
2329 * up the hardware to notify us when we need to issue beacons.
2331 * When operating in station mode this sets up the beacon
2332 * timers according to the timestamp of the last received
2333 * beacon and the current TSF, configures PCF and DTIM
2334 * handling, programs the sleep registers so the hardware
2335 * will wakeup in time to receive beacons, and configures
2336 * the beacon miss handling so we'll receive a BMISS
2337 * interrupt when we stop seeing beacons from the AP
2338 * we've associated with.
2341 ath_beacon_config(struct ath_softc *sc)
2343 #define TSF_TO_TU(_h,_l) \
2344 ((((uint32_t)(_h)) << 22) | (((uint32_t)(_l)) >> 10))
2346 struct ath_hal *ah = sc->sc_ah;
2347 struct ieee80211com *ic = &sc->sc_ic;
2348 struct ieee80211_node *ni = ic->ic_bss;
2349 uint32_t nexttbtt, intval, tsftu;
2352 /* extract tstamp from last beacon and convert to TU */
2353 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4),
2354 LE_READ_4(ni->ni_tstamp.data));
2355 /* NB: the beacon interval is kept internally in TU's */
2356 intval = ni->ni_intval & HAL_BEACON_PERIOD;
2357 if (nexttbtt == 0) /* e.g. for ap mode */
2359 else if (intval) /* NB: can be 0 for monitor mode */
2360 nexttbtt = roundup(nexttbtt, intval);
2361 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
2362 __func__, nexttbtt, intval, ni->ni_intval);
2363 if (ic->ic_opmode == IEEE80211_M_STA) {
2364 HAL_BEACON_STATE bs;
2365 int dtimperiod, dtimcount;
2366 int cfpperiod, cfpcount;
2369 * Setup dtim and cfp parameters according to
2370 * last beacon we received (which may be none).
2372 dtimperiod = ni->ni_dtim_period;
2373 if (dtimperiod <= 0) /* NB: 0 if not known */
2375 dtimcount = ni->ni_dtim_count;
2376 if (dtimcount >= dtimperiod) /* NB: sanity check */
2377 dtimcount = 0; /* XXX? */
2378 cfpperiod = 1; /* NB: no PCF support yet */
2381 * Pull nexttbtt forward to reflect the current
2382 * TSF and calculate dtim+cfp state for the result.
2384 tsf = ath_hal_gettsf64(ah);
2385 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
2388 if (--dtimcount < 0) {
2389 dtimcount = dtimperiod - 1;
2391 cfpcount = cfpperiod - 1;
2393 } while (nexttbtt < tsftu);
2394 memset(&bs, 0, sizeof(bs));
2395 bs.bs_intval = intval;
2396 bs.bs_nexttbtt = nexttbtt;
2397 bs.bs_dtimperiod = dtimperiod*intval;
2398 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
2399 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
2400 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
2401 bs.bs_cfpmaxduration = 0;
2404 * The 802.11 layer records the offset to the DTIM
2405 * bitmap while receiving beacons; use it here to
2406 * enable h/w detection of our AID being marked in
2407 * the bitmap vector (to indicate frames for us are
2408 * pending at the AP).
2409 * XXX do DTIM handling in s/w to WAR old h/w bugs
2410 * XXX enable based on h/w rev for newer chips
2412 bs.bs_timoffset = ni->ni_timoff;
2415 * Calculate the number of consecutive beacons to miss
2416 * before taking a BMISS interrupt. The configuration
2417 * is specified in ms, so we need to convert that to
2418 * TU's and then calculate based on the beacon interval.
2419 * Note that we clamp the result to at most 10 beacons.
2421 bs.bs_bmissthreshold = ic->ic_bmissthreshold;
2422 if (bs.bs_bmissthreshold > 10)
2423 bs.bs_bmissthreshold = 10;
2424 else if (bs.bs_bmissthreshold <= 0)
2425 bs.bs_bmissthreshold = 1;
2428 * Calculate sleep duration. The configuration is
2429 * given in ms. We insure a multiple of the beacon
2430 * period is used. Also, if the sleep duration is
2431 * greater than the DTIM period then it makes senses
2432 * to make it a multiple of that.
2434 * XXX fixed at 100ms
2436 bs.bs_sleepduration =
2437 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval);
2438 if (bs.bs_sleepduration > bs.bs_dtimperiod)
2439 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod);
2441 DPRINTF(sc, ATH_DEBUG_BEACON,
2442 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n"
2449 , bs.bs_bmissthreshold
2450 , bs.bs_sleepduration
2452 , bs.bs_cfpmaxduration
2456 ath_hal_intrset(ah, 0);
2457 ath_hal_beacontimers(ah, &bs);
2458 sc->sc_imask |= HAL_INT_BMISS;
2459 ath_hal_intrset(ah, sc->sc_imask);
2461 ath_hal_intrset(ah, 0);
2462 if (nexttbtt == intval)
2463 intval |= HAL_BEACON_RESET_TSF;
2464 if (ic->ic_opmode == IEEE80211_M_IBSS) {
2466 * In IBSS mode enable the beacon timers but only
2467 * enable SWBA interrupts if we need to manually
2468 * prepare beacon frames. Otherwise we use a
2469 * self-linked tx descriptor and let the hardware
2472 intval |= HAL_BEACON_ENA;
2473 if (!sc->sc_hasveol)
2474 sc->sc_imask |= HAL_INT_SWBA;
2475 if ((intval & HAL_BEACON_RESET_TSF) == 0) {
2477 * Pull nexttbtt forward to reflect
2480 tsf = ath_hal_gettsf64(ah);
2481 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
2484 } while (nexttbtt < tsftu);
2486 ath_beaconq_config(sc);
2487 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
2489 * In AP mode we enable the beacon timers and
2490 * SWBA interrupts to prepare beacon frames.
2492 intval |= HAL_BEACON_ENA;
2493 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */
2494 ath_beaconq_config(sc);
2496 ath_hal_beaconinit(ah, nexttbtt, intval);
2497 sc->sc_bmisscount = 0;
2498 ath_hal_intrset(ah, sc->sc_imask);
2500 * When using a self-linked beacon descriptor in
2501 * ibss mode load it once here.
2503 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol)
2504 ath_beacon_proc(sc);
2506 sc->sc_syncbeacon = 0;
2512 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
2514 bus_addr_t *paddr = (bus_addr_t*) arg;
2515 KASSERT(error == 0, ("error %u on bus_dma callback", error));
2516 *paddr = segs->ds_addr;
2520 ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
2521 ath_bufhead *head, const char *name, int nbuf, int ndesc)
2523 #define DS2PHYS(_dd, _ds) \
2524 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2525 struct ifnet *ifp = &sc->sc_ic.ic_if;
2526 struct ath_desc *ds;
2528 int i, bsize, error;
2530 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n",
2531 __func__, name, nbuf, ndesc);
2534 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
2538 * Setup DMA descriptor area.
2540 error = bus_dma_tag_create(NULL, /* parent */
2541 PAGE_SIZE, 0, /* alignment, bounds */
2542 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
2543 BUS_SPACE_MAXADDR, /* highaddr */
2544 NULL, NULL, /* filter, filterarg */
2545 dd->dd_desc_len, /* maxsize */
2547 dd->dd_desc_len, /* maxsegsize */
2548 BUS_DMA_ALLOCNOW, /* flags */
2551 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name);
2555 /* allocate descriptors */
2556 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_WAITOK, &dd->dd_dmamap);
2558 if_printf(ifp, "unable to create dmamap for %s descriptors, "
2559 "error %u\n", dd->dd_name, error);
2563 error = bus_dmamem_alloc(dd->dd_dmat, (void **)&dd->dd_desc,
2564 BUS_DMA_WAITOK, &dd->dd_dmamap);
2566 if_printf(ifp, "unable to alloc memory for %u %s descriptors, "
2567 "error %u\n", nbuf * ndesc, dd->dd_name, error);
2571 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap,
2572 dd->dd_desc, dd->dd_desc_len,
2573 ath_load_cb, &dd->dd_desc_paddr,
2576 if_printf(ifp, "unable to map %s descriptors, error %u\n",
2577 dd->dd_name, error);
2579 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
2585 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n",
2586 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len,
2587 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len);
2589 /* allocate rx buffers */
2590 bsize = sizeof(struct ath_buf) * nbuf;
2591 bf = kmalloc(bsize, M_ATHDEV, M_WAITOK | M_ZERO);
2594 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2596 bf->bf_daddr = DS2PHYS(dd, ds);
2597 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_WAITOK,
2600 if_printf(ifp, "unable to create dmamap for %s "
2601 "buffer %u, error %u\n", dd->dd_name, i, error);
2602 ath_descdma_cleanup(sc, dd, head);
2605 STAILQ_INSERT_TAIL(head, bf, bf_list);
2611 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
2613 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
2615 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
2617 bus_dma_tag_destroy(dd->dd_dmat);
2618 memset(dd, 0, sizeof(*dd));
2625 ath_descdma_cleanup(struct ath_softc *sc,
2626 struct ath_descdma *dd, ath_bufhead *head)
2629 struct ieee80211_node *ni;
2631 if (dd->dd_desc != NULL) {
2632 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
2633 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
2637 if (dd->dd_dmamap != NULL) {
2638 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
2639 dd->dd_dmamap = NULL;
2642 if (dd->dd_dmat != NULL) {
2643 bus_dma_tag_destroy(dd->dd_dmat);
2647 STAILQ_FOREACH(bf, head, bf_list) {
2652 if (bf->bf_dmamap != NULL) {
2653 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap);
2654 bf->bf_dmamap = NULL;
2660 * Reclaim node reference.
2662 ieee80211_free_node(ni);
2667 if (dd->dd_bufptr != NULL)
2668 kfree(dd->dd_bufptr, M_ATHDEV);
2669 memset(dd, 0, sizeof(*dd));
2673 ath_desc_alloc(struct ath_softc *sc)
2677 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
2678 "rx", ath_rxbuf, 1);
2682 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
2683 "tx", ath_txbuf, ATH_TXDESC);
2687 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
2695 ath_desc_free(struct ath_softc *sc)
2698 if (sc->sc_bdma.dd_desc_len != 0) {
2699 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
2700 sc->sc_bdma.dd_desc_len = 0;
2702 if (sc->sc_txdma.dd_desc_len != 0) {
2703 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
2704 sc->sc_txdma.dd_desc_len = 0;
2706 if (sc->sc_rxdma.dd_desc_len != 0) {
2707 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
2708 sc->sc_rxdma.dd_desc_len = 0;
2712 static struct ieee80211_node *
2713 ath_node_alloc(struct ieee80211_node_table *nt)
2715 struct ieee80211com *ic = nt->nt_ic;
2716 struct ath_softc *sc = ic->ic_ifp->if_softc;
2717 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space;
2718 struct ath_node *an;
2720 an = kmalloc(space, M_80211_NODE, M_NOWAIT|M_ZERO);
2725 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER;
2726 ath_rate_node_init(sc, an);
2728 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an);
2729 return &an->an_node;
2733 ath_node_free(struct ieee80211_node *ni)
2735 struct ieee80211com *ic = ni->ni_ic;
2736 struct ath_softc *sc = ic->ic_ifp->if_softc;
2738 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni);
2740 ath_rate_node_cleanup(sc, ATH_NODE(ni));
2741 sc->sc_node_free(ni);
2745 ath_node_getrssi(const struct ieee80211_node *ni)
2747 #define HAL_EP_RND(x, mul) \
2748 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
2749 uint32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi;
2753 * When only one frame is received there will be no state in
2754 * avgrssi so fallback on the value recorded by the 802.11 layer.
2756 if (avgrssi != ATH_RSSI_DUMMY_MARKER)
2757 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER);
2760 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi;
2765 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
2767 struct ath_hal *ah = sc->sc_ah;
2770 struct ath_desc *ds;
2775 * NB: by assigning a page to the rx dma buffer we
2776 * implicitly satisfy the Atheros requirement that
2777 * this buffer be cache-line-aligned and sized to be
2778 * multiple of the cache line size. Not doing this
2779 * causes weird stuff to happen (for the 5210 at least).
2781 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
2783 DPRINTF(sc, ATH_DEBUG_ANY,
2784 "%s: no mbuf/cluster\n", __func__);
2785 sc->sc_stats.ast_rx_nombuf++;
2788 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
2790 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m,
2791 ath_dma_map_mbuf, bf,
2794 DPRINTF(sc, ATH_DEBUG_ANY,
2795 "%s: bus_dmamap_load_mbuf failed; error %d\n",
2797 sc->sc_stats.ast_rx_busdma++;
2801 KASSERT(bf->bf_nseg == 1,
2802 ("multi-segment packet; nseg %u", bf->bf_nseg));
2805 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD);
2808 * Setup descriptors. For receive we always terminate
2809 * the descriptor list with a self-linked entry so we'll
2810 * not get overrun under high load (as can happen with a
2811 * 5212 when ANI processing enables PHY error frames).
2813 * To insure the last descriptor is self-linked we create
2814 * each descriptor as self-linked and add it to the end. As
2815 * each additional descriptor is added the previous self-linked
2816 * entry is ``fixed'' naturally. This should be safe even
2817 * if DMA is happening. When processing RX interrupts we
2818 * never remove/process the last, self-linked, entry on the
2819 * descriptor list. This insures the hardware always has
2820 * someplace to write a new frame.
2823 ds->ds_link = bf->bf_daddr; /* link to self */
2824 ds->ds_data = bf->bf_segs[0].ds_addr;
2825 ath_hal_setuprxdesc(ah, ds
2826 , m->m_len /* buffer size */
2830 if (sc->sc_rxlink != NULL)
2831 *sc->sc_rxlink = bf->bf_daddr;
2832 sc->sc_rxlink = &ds->ds_link;
2837 * Extend 15-bit time stamp from rx descriptor to
2838 * a full 64-bit TSF using the specified TSF.
2840 static __inline uint64_t
2841 ath_extend_tsf(uint32_t rstamp, uint64_t tsf)
2843 if ((tsf & 0x7fff) < rstamp)
2845 return ((tsf &~ 0x7fff) | rstamp);
2849 * Intercept management frames to collect beacon rssi data
2850 * and to do ibss merges.
2853 ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m,
2854 struct ieee80211_node *ni,
2855 int subtype, int rssi, uint32_t rstamp)
2857 struct ath_softc *sc = ic->ic_ifp->if_softc;
2860 * Call up first so subsequent work can use information
2861 * potentially stored in the node (e.g. for ibss merge).
2863 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp);
2865 case IEEE80211_FC0_SUBTYPE_BEACON:
2866 /* update rssi statistics for use by the hal */
2867 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi);
2868 if (sc->sc_syncbeacon &&
2869 ni == ic->ic_bss && ic->ic_state == IEEE80211_S_RUN) {
2871 * Resync beacon timers using the tsf of the beacon
2872 * frame we just received.
2874 ath_beacon_config(sc);
2877 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
2878 if (ic->ic_opmode == IEEE80211_M_IBSS &&
2879 ic->ic_state == IEEE80211_S_RUN) {
2880 uint64_t tsf = ath_extend_tsf(rstamp,
2881 ath_hal_gettsf64(sc->sc_ah));
2883 * Handle ibss merge as needed; check the tsf on the
2884 * frame before attempting the merge. The 802.11 spec
2885 * says the station should change it's bssid to match
2886 * the oldest station with the same ssid, where oldest
2887 * is determined by the tsf. Note that hardware
2888 * reconfiguration happens through callback to
2889 * ath_newstate as the state machine will go from
2890 * RUN -> RUN when this happens.
2892 if (le64toh(ni->ni_tstamp.tsf) >= tsf) {
2893 DPRINTF(sc, ATH_DEBUG_STATE,
2894 "ibss merge, rstamp %u tsf %ju "
2895 "tstamp %ju\n", rstamp, (uintmax_t)tsf,
2896 (uintmax_t)ni->ni_tstamp.tsf);
2897 ieee80211_ibss_merge(ni);
2905 * Set the default antenna.
2908 ath_setdefantenna(struct ath_softc *sc, u_int antenna)
2910 struct ath_hal *ah = sc->sc_ah;
2912 /* XXX block beacon interrupts */
2913 ath_hal_setdefantenna(ah, antenna);
2914 if (sc->sc_defant != antenna)
2915 sc->sc_stats.ast_ant_defswitch++;
2916 sc->sc_defant = antenna;
2917 sc->sc_rxotherant = 0;
2921 ath_rx_tap(struct ath_softc *sc, struct mbuf *m,
2922 const struct ath_rx_status *rs, uint64_t tsf, int16_t nf)
2926 KASSERT(sc->sc_drvbpf != NULL, ("no tap"));
2929 * Discard anything shorter than an ack or cts.
2931 if (m->m_pkthdr.len < IEEE80211_ACK_LEN) {
2932 DPRINTF(sc, ATH_DEBUG_RECV, "%s: runt packet %d\n",
2933 __func__, m->m_pkthdr.len);
2934 sc->sc_stats.ast_rx_tooshort++;
2937 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(rs->rs_tstamp, tsf));
2939 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags;
2940 if (rs->rs_status & HAL_RXERR_CRC)
2941 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS;
2942 /* XXX propagate other error flags from descriptor */
2943 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate;
2944 sc->sc_rx_th.wr_antsignal = rs->rs_rssi + nf;
2945 sc->sc_rx_th.wr_antnoise = nf;
2946 sc->sc_rx_th.wr_antenna = rs->rs_antenna;
2948 bpf_ptap(sc->sc_drvbpf, m, &sc->sc_rx_th, sc->sc_rx_th_len);
2954 ath_rx_proc(struct ath_softc *sc)
2956 #define PA2DESC(_sc, _pa) \
2957 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
2958 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
2960 struct ieee80211com *ic = &sc->sc_ic;
2961 struct ifnet *ifp = &ic->ic_if;
2962 struct ath_hal *ah = sc->sc_ah;
2963 struct ath_desc *ds;
2964 struct ath_rx_status *rs;
2966 struct ieee80211_node *ni;
2967 struct ath_node *an;
2968 int len, type, ngood;
2975 nf = ath_hal_getchannoise(ah, &sc->sc_curchan);
2976 tsf = ath_hal_gettsf64(ah);
2978 bf = STAILQ_FIRST(&sc->sc_rxbuf);
2979 if (bf == NULL) { /* NB: shouldn't happen */
2980 if_printf(ifp, "%s: no buffer!\n", __func__);
2984 if (m == NULL) { /* NB: shouldn't happen */
2986 * If mbuf allocation failed previously there
2987 * will be no mbuf; try again to re-populate it.
2989 /* XXX make debug msg */
2990 if_printf(ifp, "%s: no mbuf!\n", __func__);
2991 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list);
2995 if (ds->ds_link == bf->bf_daddr) {
2996 /* NB: never process the self-linked entry at the end */
2999 /* XXX sync descriptor memory */
3001 * Must provide the virtual address of the current
3002 * descriptor, the physical address, and the virtual
3003 * address of the next descriptor in the h/w chain.
3004 * This allows the HAL to look ahead to see if the
3005 * hardware is done with a descriptor by checking the
3006 * done bit in the following descriptor and the address
3007 * of the current descriptor the DMA engine is working
3008 * on. All this is necessary because of our use of
3009 * a self-linked list to avoid rx overruns.
3011 rs = &bf->bf_status.ds_rxstat;
3012 status = ath_hal_rxprocdesc(ah, ds,
3013 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
3015 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
3016 ath_printrxbuf(bf, 0, status == HAL_OK);
3018 if (status == HAL_EINPROGRESS)
3020 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list);
3023 * Frame spans multiple descriptors; this
3024 * cannot happen yet as we don't support
3025 * jumbograms. If not in monitor mode,
3026 * discard the frame.
3028 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
3029 sc->sc_stats.ast_rx_toobig++;
3032 /* fall thru for monitor mode handling... */
3033 } else if (rs->rs_status != 0) {
3034 if (rs->rs_status & HAL_RXERR_CRC)
3035 sc->sc_stats.ast_rx_crcerr++;
3036 if (rs->rs_status & HAL_RXERR_FIFO)
3037 sc->sc_stats.ast_rx_fifoerr++;
3038 if (rs->rs_status & HAL_RXERR_PHY) {
3039 sc->sc_stats.ast_rx_phyerr++;
3040 phyerr = rs->rs_phyerr & 0x1f;
3041 sc->sc_stats.ast_rx_phy[phyerr]++;
3044 if (rs->rs_status & HAL_RXERR_DECRYPT) {
3046 * Decrypt error. If the error occurred
3047 * because there was no hardware key, then
3048 * let the frame through so the upper layers
3049 * can process it. This is necessary for 5210
3050 * parts which have no way to setup a ``clear''
3053 * XXX do key cache faulting
3055 if (rs->rs_keyix == HAL_RXKEYIX_INVALID)
3057 sc->sc_stats.ast_rx_badcrypt++;
3059 if (rs->rs_status & HAL_RXERR_MIC) {
3060 sc->sc_stats.ast_rx_badmic++;
3062 * Do minimal work required to hand off
3063 * the 802.11 header for notifcation.
3065 /* XXX frag's and qos frames */
3066 len = rs->rs_datalen;
3067 if (len >= sizeof (struct ieee80211_frame)) {
3068 bus_dmamap_sync(sc->sc_dmat,
3070 BUS_DMASYNC_POSTREAD);
3071 ieee80211_notify_michael_failure(ic,
3072 mtod(m, struct ieee80211_frame *),
3074 rs->rs_keyix-32 : rs->rs_keyix
3080 * When a tap is present pass error frames
3081 * that have been requested. By default we
3082 * pass decrypt+mic errors but others may be
3083 * interesting (e.g. crc).
3085 if (sc->sc_drvbpf != NULL &&
3086 (rs->rs_status & sc->sc_monpass)) {
3087 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3088 BUS_DMASYNC_POSTREAD);
3089 /* NB: bpf needs the mbuf length setup */
3090 len = rs->rs_datalen;
3091 m->m_pkthdr.len = m->m_len = len;
3092 ath_rx_tap(sc, m, rs, tsf, nf);
3094 /* XXX pass MIC errors up for s/w reclaculation */
3099 * Sync and unmap the frame. At this point we're
3100 * committed to passing the mbuf somewhere so clear
3101 * bf_m; this means a new mbuf must be allocated
3102 * when the rx descriptor is setup again to receive
3105 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3106 BUS_DMASYNC_POSTREAD);
3107 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3110 m->m_pkthdr.rcvif = ifp;
3111 len = rs->rs_datalen;
3112 m->m_pkthdr.len = m->m_len = len;
3114 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++;
3116 if (sc->sc_drvbpf != NULL && !ath_rx_tap(sc, m, rs, tsf, nf)) {
3117 m_freem(m); /* XXX reclaim */
3122 * From this point on we assume the frame is at least
3123 * as large as ieee80211_frame_min; verify that.
3125 if (len < IEEE80211_MIN_LEN) {
3126 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n",
3128 sc->sc_stats.ast_rx_tooshort++;
3133 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) {
3134 ieee80211_dump_pkt(mtod(m, caddr_t), len,
3135 sc->sc_hwmap[rs->rs_rate].ieeerate,
3139 m_adj(m, -IEEE80211_CRC_LEN);
3142 * Locate the node for sender, track state, and then
3143 * pass the (referenced) node up to the 802.11 layer
3146 ni = ieee80211_find_rxnode_withkey(ic,
3147 mtod(m, const struct ieee80211_frame_min *),
3148 rs->rs_keyix == HAL_RXKEYIX_INVALID ?
3149 IEEE80211_KEYIX_NONE : rs->rs_keyix);
3151 * Track rx rssi and do any rx antenna management.
3154 ATH_RSSI_LPF(an->an_avgrssi, rs->rs_rssi);
3155 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi);
3157 * Send frame up for processing.
3159 type = ieee80211_input(ic, m, ni, rs->rs_rssi, rs->rs_tstamp);
3160 ieee80211_free_node(ni);
3161 if (sc->sc_diversity) {
3163 * When using fast diversity, change the default rx
3164 * antenna if diversity chooses the other antenna 3
3167 if (sc->sc_defant != rs->rs_antenna) {
3168 if (++sc->sc_rxotherant >= 3)
3169 ath_setdefantenna(sc, rs->rs_antenna);
3171 sc->sc_rxotherant = 0;
3173 if (sc->sc_softled) {
3175 * Blink for any data frame. Otherwise do a
3176 * heartbeat-style blink when idle. The latter
3177 * is mainly for station mode where we depend on
3178 * periodic beacon frames to trigger the poll event.
3180 if (type == IEEE80211_FC0_TYPE_DATA) {
3181 sc->sc_rxrate = rs->rs_rate;
3182 ath_led_event(sc, ATH_LED_RX);
3183 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle)
3184 ath_led_event(sc, ATH_LED_POLL);
3187 * Arrange to update the last rx timestamp only for
3188 * frames from our ap when operating in station mode.
3189 * This assumes the rx key is always setup when associated.
3191 if (ic->ic_opmode == IEEE80211_M_STA &&
3192 rs->rs_keyix != HAL_RXKEYIX_INVALID)
3195 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
3196 } while (ath_rxbuf_init(sc, bf) == 0);
3198 /* rx signal state monitoring */
3199 ath_hal_rxmonitor(ah, &sc->sc_halstats, &sc->sc_curchan);
3201 sc->sc_lastrx = tsf;
3206 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum)
3208 txq->axq_qnum = qnum;
3210 txq->axq_intrcnt = 0;
3211 txq->axq_link = NULL;
3212 STAILQ_INIT(&txq->axq_q);
3216 * Setup a h/w transmit queue.
3218 static struct ath_txq *
3219 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
3221 #define N(a) (sizeof(a)/sizeof(a[0]))
3222 struct ath_hal *ah = sc->sc_ah;
3226 memset(&qi, 0, sizeof(qi));
3227 qi.tqi_subtype = subtype;
3228 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
3229 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
3230 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
3232 * Enable interrupts only for EOL and DESC conditions.
3233 * We mark tx descriptors to receive a DESC interrupt
3234 * when a tx queue gets deep; otherwise waiting for the
3235 * EOL to reap descriptors. Note that this is done to
3236 * reduce interrupt load and this only defers reaping
3237 * descriptors, never transmitting frames. Aside from
3238 * reducing interrupts this also permits more concurrency.
3239 * The only potential downside is if the tx queue backs
3240 * up in which case the top half of the kernel may backup
3241 * due to a lack of tx descriptors.
3243 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE;
3244 qnum = ath_hal_setuptxqueue(ah, qtype, &qi);
3247 * NB: don't print a message, this happens
3248 * normally on parts with too few tx queues
3252 if (qnum >= N(sc->sc_txq)) {
3253 device_printf(sc->sc_dev,
3254 "hal qnum %u out of range, max %zu!\n",
3255 qnum, N(sc->sc_txq));
3256 ath_hal_releasetxqueue(ah, qnum);
3259 if (!IS_ATH_TXQ_SETUP(sc, qnum)) {
3260 ath_txq_init(sc, &sc->sc_txq[qnum], qnum);
3261 ATH_TXQ_SETUP(sc, qnum);
3263 return &sc->sc_txq[qnum];
3268 * Setup a hardware data transmit queue for the specified
3269 * access control. The hal may not support all requested
3270 * queues in which case it will return a reference to a
3271 * previously setup queue. We record the mapping from ac's
3272 * to h/w queues for use by ath_tx_start and also track
3273 * the set of h/w queues being used to optimize work in the
3274 * transmit interrupt handler and related routines.
3277 ath_tx_setup(struct ath_softc *sc, int ac, int haltype)
3279 #define N(a) (sizeof(a)/sizeof(a[0]))
3280 struct ath_txq *txq;
3282 if (ac >= N(sc->sc_ac2q)) {
3283 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n",
3284 ac, N(sc->sc_ac2q));
3287 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
3289 sc->sc_ac2q[ac] = txq;
3298 * Update WME parameters for a transmit queue.
3301 ath_txq_update(struct ath_softc *sc, int ac)
3303 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1)
3304 #define ATH_TXOP_TO_US(v) (v<<5)
3305 struct ieee80211com *ic = &sc->sc_ic;
3306 struct ath_txq *txq = sc->sc_ac2q[ac];
3307 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac];
3308 struct ath_hal *ah = sc->sc_ah;
3311 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi);
3312 qi.tqi_aifs = wmep->wmep_aifsn;
3313 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
3314 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
3315 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit);
3317 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) {
3318 device_printf(sc->sc_dev, "unable to update hardware queue "
3319 "parameters for %s traffic!\n",
3320 ieee80211_wme_acnames[ac]);
3323 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */
3326 #undef ATH_TXOP_TO_US
3327 #undef ATH_EXPONENT_TO_VALUE
3331 * Callback from the 802.11 layer to update WME parameters.
3334 ath_wme_update(struct ieee80211com *ic)
3336 struct ath_softc *sc = ic->ic_ifp->if_softc;
3338 return !ath_txq_update(sc, WME_AC_BE) ||
3339 !ath_txq_update(sc, WME_AC_BK) ||
3340 !ath_txq_update(sc, WME_AC_VI) ||
3341 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0;
3345 * Reclaim resources for a setup queue.
3348 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
3350 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum);
3351 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
3355 * Reclaim all tx queue resources.
3358 ath_tx_cleanup(struct ath_softc *sc)
3362 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3363 if (IS_ATH_TXQ_SETUP(sc, i))
3364 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
3368 * Defragment an mbuf chain, returning at most maxfrags separate
3369 * mbufs+clusters. If this is not possible NULL is returned and
3370 * the original mbuf chain is left in it's present (potentially
3371 * modified) state. We use two techniques: collapsing consecutive
3372 * mbufs and replacing consecutive mbufs by a cluster.
3374 static struct mbuf *
3375 ath_defrag(struct mbuf *m0, int how, int maxfrags)
3377 struct mbuf *m, *n, *n2, **prev;
3381 * Calculate the current number of frags.
3384 for (m = m0; m != NULL; m = m->m_next)
3387 * First, try to collapse mbufs. Note that we always collapse
3388 * towards the front so we don't need to deal with moving the
3389 * pkthdr. This may be suboptimal if the first mbuf has much
3390 * less data than the following.
3398 if (n->m_len < M_TRAILINGSPACE(m)) {
3399 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len,
3401 m->m_len += n->m_len;
3402 m->m_next = n->m_next;
3404 if (--curfrags <= maxfrags)
3409 KASSERT(maxfrags > 1,
3410 ("maxfrags %u, but normal collapse failed", maxfrags));
3412 * Collapse consecutive mbufs to a cluster.
3414 prev = &m0->m_next; /* NB: not the first mbuf */
3415 while ((n = *prev) != NULL) {
3416 if ((n2 = n->m_next) != NULL &&
3417 n->m_len + n2->m_len < MCLBYTES) {
3418 m = m_getcl(how, MT_DATA, 0);
3421 bcopy(mtod(n, void *), mtod(m, void *), n->m_len);
3422 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len,
3424 m->m_len = n->m_len + n2->m_len;
3425 m->m_next = n2->m_next;
3429 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */
3432 * Still not there, try the normal collapse
3433 * again before we allocate another cluster.
3440 * No place where we can collapse to a cluster; punt.
3441 * This can occur if, for example, you request 2 frags
3442 * but the packet requires that both be clusters (we
3443 * never reallocate the first mbuf to avoid moving the
3451 * Return h/w rate index for an IEEE rate (w/o basic rate bit).
3454 ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate)
3458 for (i = 0; i < rt->rateCount; i++)
3459 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate)
3461 return 0; /* NB: lowest rate */
3465 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni,
3466 struct ath_buf *bf, struct mbuf *m0)
3468 struct ieee80211com *ic = &sc->sc_ic;
3469 struct ath_hal *ah = sc->sc_ah;
3470 struct ifnet *ifp = &ic->ic_if;
3471 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams;
3472 int i, error, iswep, ismcast, ismrr;
3473 int keyix, hdrlen, pktlen, try0;
3474 uint8_t rix, txrate, ctsrate;
3475 uint8_t cix = 0xff; /* NB: silence compiler */
3476 struct ath_desc *ds, *ds0;
3477 struct ath_txq *txq;
3478 struct ieee80211_frame *wh;
3479 u_int subtype, flags, ctsduration;
3481 const HAL_RATE_TABLE *rt;
3482 HAL_BOOL shortPreamble;
3483 struct ath_node *an;
3487 wh = mtod(m0, struct ieee80211_frame *);
3488 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
3489 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
3490 hdrlen = ieee80211_anyhdrsize(wh);
3492 * Packet length must not include any
3493 * pad bytes; deduct them here.
3495 pktlen = m0->m_pkthdr.len - (hdrlen & 3);
3498 const struct ieee80211_cipher *cip;
3499 struct ieee80211_key *k;
3502 * Construct the 802.11 header+trailer for an encrypted
3503 * frame. The only reason this can fail is because of an
3504 * unknown or unsupported cipher/key type.
3506 k = ieee80211_crypto_encap(ic, ni, m0);
3509 * This can happen when the key is yanked after the
3510 * frame was queued. Just discard the frame; the
3511 * 802.11 layer counts failures and provides
3512 * debugging/diagnostics.
3518 * Adjust the packet + header lengths for the crypto
3519 * additions and calculate the h/w key index. When
3520 * a s/w mic is done the frame will have had any mic
3521 * added to it prior to entry so m0->m_pkthdr.len above will
3522 * account for it. Otherwise we need to add it to the
3526 hdrlen += cip->ic_header;
3527 pktlen += cip->ic_header + cip->ic_trailer;
3528 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0)
3529 pktlen += cip->ic_miclen;
3530 keyix = k->wk_keyix;
3532 /* packet header may have moved, reset our local pointer */
3533 wh = mtod(m0, struct ieee80211_frame *);
3534 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) {
3536 * Use station key cache slot, if assigned.
3538 keyix = ni->ni_ucastkey.wk_keyix;
3539 if (keyix == IEEE80211_KEYIX_NONE)
3540 keyix = HAL_TXKEYIX_INVALID;
3542 keyix = HAL_TXKEYIX_INVALID;
3544 pktlen += IEEE80211_CRC_LEN;
3547 * Load the DMA map so any coalescing is done. This
3548 * also calculates the number of descriptors we need.
3550 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0,
3551 ath_dma_map_mbuf, bf, BUS_DMA_NOWAIT);
3552 if (error == EFBIG) {
3553 /* XXX packet requires too many descriptors */
3554 bf->bf_nseg = ATH_TXDESC+1;
3555 } else if (error != 0) {
3556 sc->sc_stats.ast_tx_busdma++;
3561 * Discard null packets and check for packets that
3562 * require too many TX descriptors. We try to convert
3563 * the latter to a cluster.
3565 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */
3566 sc->sc_stats.ast_tx_linear++;
3567 m = ath_defrag(m0, MB_DONTWAIT, ATH_TXDESC);
3570 sc->sc_stats.ast_tx_nombuf++;
3574 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0,
3575 ath_dma_map_mbuf, bf,
3578 sc->sc_stats.ast_tx_busdma++;
3582 KASSERT(bf->bf_nseg <= ATH_TXDESC,
3583 ("too many segments after defrag; nseg %u", bf->bf_nseg));
3584 } else if (bf->bf_nseg == 0) { /* null packet, discard */
3585 sc->sc_stats.ast_tx_nodata++;
3589 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen);
3590 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
3592 bf->bf_node = ni; /* NB: held reference */
3594 /* setup descriptors */
3596 rt = sc->sc_currates;
3597 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
3600 * NB: the 802.11 layer marks whether or not we should
3601 * use short preamble based on the current mode and
3602 * negotiated parameters.
3604 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
3605 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) {
3606 shortPreamble = AH_TRUE;
3607 sc->sc_stats.ast_tx_shortpre++;
3609 shortPreamble = AH_FALSE;
3613 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */
3614 ismrr = 0; /* default no multi-rate retry*/
3616 * Calculate Atheros packet type from IEEE80211 packet header,
3617 * setup for rate calculations, and select h/w transmit queue.
3619 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
3620 case IEEE80211_FC0_TYPE_MGT:
3621 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
3622 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON)
3623 atype = HAL_PKT_TYPE_BEACON;
3624 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
3625 atype = HAL_PKT_TYPE_PROBE_RESP;
3626 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
3627 atype = HAL_PKT_TYPE_ATIM;
3629 atype = HAL_PKT_TYPE_NORMAL; /* XXX */
3630 rix = sc->sc_minrateix;
3631 txrate = rt->info[rix].rateCode;
3633 txrate |= rt->info[rix].shortPreamble;
3634 try0 = ATH_TXMGTTRY;
3635 /* NB: force all management frames to highest queue */
3636 if (ni->ni_flags & IEEE80211_NODE_QOS) {
3637 /* NB: force all management frames to highest queue */
3641 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
3643 case IEEE80211_FC0_TYPE_CTL:
3644 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */
3645 rix = sc->sc_minrateix;
3646 txrate = rt->info[rix].rateCode;
3648 txrate |= rt->info[rix].shortPreamble;
3649 try0 = ATH_TXMGTTRY;
3650 /* NB: force all ctl frames to highest queue */
3651 if (ni->ni_flags & IEEE80211_NODE_QOS) {
3652 /* NB: force all ctl frames to highest queue */
3656 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
3658 case IEEE80211_FC0_TYPE_DATA:
3659 atype = HAL_PKT_TYPE_NORMAL; /* default */
3661 * Data frames: multicast frames go out at a fixed rate,
3662 * otherwise consult the rate control module for the
3667 * Check mcast rate setting in case it's changed.
3668 * XXX move out of fastpath
3670 if (ic->ic_mcast_rate != sc->sc_mcastrate) {
3672 ath_tx_findrix(rt, ic->ic_mcast_rate);
3673 sc->sc_mcastrate = ic->ic_mcast_rate;
3675 rix = sc->sc_mcastrix;
3676 txrate = rt->info[rix].rateCode;
3678 txrate |= rt->info[rix].shortPreamble;
3681 ath_rate_findrate(sc, an, shortPreamble, pktlen,
3682 &rix, &try0, &txrate);
3683 sc->sc_txrate = txrate; /* for LED blinking */
3684 if (try0 != ATH_TXMAXTRY)
3687 pri = M_WME_GETAC(m0);
3688 if (cap->cap_wmeParams[pri].wmep_noackPolicy)
3689 flags |= HAL_TXDESC_NOACK;
3692 if_printf(ifp, "bogus frame type 0x%x (%s)\n",
3693 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__);
3698 txq = sc->sc_ac2q[pri];
3701 * When servicing one or more stations in power-save mode
3702 * (or) if there is some mcast data waiting on the mcast
3703 * queue (to prevent out of order delivery) multicast
3704 * frames must be buffered until after the beacon.
3706 if (ismcast && (ic->ic_ps_sta || sc->sc_mcastq.axq_depth)) {
3707 txq = &sc->sc_mcastq;
3708 /* XXX? more bit in 802.11 frame header */
3712 * Calculate miscellaneous flags.
3715 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */
3716 } else if (pktlen > ic->ic_rtsthreshold) {
3717 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */
3718 cix = rt->info[rix].controlRate;
3719 sc->sc_stats.ast_tx_rts++;
3721 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */
3722 sc->sc_stats.ast_tx_noack++;
3725 * If 802.11g protection is enabled, determine whether
3726 * to use RTS/CTS or just CTS. Note that this is only
3727 * done for OFDM unicast frames.
3729 if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
3730 rt->info[rix].phy == IEEE80211_T_OFDM &&
3731 (flags & HAL_TXDESC_NOACK) == 0) {
3732 /* XXX fragments must use CCK rates w/ protection */
3733 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
3734 flags |= HAL_TXDESC_RTSENA;
3735 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
3736 flags |= HAL_TXDESC_CTSENA;
3737 cix = rt->info[sc->sc_protrix].controlRate;
3738 sc->sc_stats.ast_tx_protect++;
3742 * Calculate duration. This logically belongs in the 802.11
3743 * layer but it lacks sufficient information to calculate it.
3745 if ((flags & HAL_TXDESC_NOACK) == 0 &&
3746 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) {
3749 * XXX not right with fragmentation.
3752 dur = rt->info[rix].spAckDuration;
3754 dur = rt->info[rix].lpAckDuration;
3755 *(uint16_t *)wh->i_dur = htole16(dur);
3759 * Calculate RTS/CTS rate and duration if needed.
3762 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) {
3764 * CTS transmit rate is derived from the transmit rate
3765 * by looking in the h/w rate table. We must also factor
3766 * in whether or not a short preamble is to be used.
3768 /* NB: cix is set above where RTS/CTS is enabled */
3769 KASSERT(cix != 0xff, ("cix not setup"));
3770 ctsrate = rt->info[cix].rateCode;
3772 * Compute the transmit duration based on the frame
3773 * size and the size of an ACK frame. We call into the
3774 * HAL to do the computation since it depends on the
3775 * characteristics of the actual PHY being used.
3777 * NB: CTS is assumed the same size as an ACK so we can
3778 * use the precalculated ACK durations.
3780 if (shortPreamble) {
3781 ctsrate |= rt->info[cix].shortPreamble;
3782 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
3783 ctsduration += rt->info[cix].spAckDuration;
3784 ctsduration += ath_hal_computetxtime(ah,
3785 rt, pktlen, rix, AH_TRUE);
3786 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
3787 ctsduration += rt->info[rix].spAckDuration;
3789 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
3790 ctsduration += rt->info[cix].lpAckDuration;
3791 ctsduration += ath_hal_computetxtime(ah,
3792 rt, pktlen, rix, AH_FALSE);
3793 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
3794 ctsduration += rt->info[rix].lpAckDuration;
3797 * Must disable multi-rate retry when using RTS/CTS.
3800 try0 = ATH_TXMGTTRY; /* XXX */
3804 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
3805 ieee80211_dump_pkt(mtod(m0, caddr_t), m0->m_len,
3806 sc->sc_hwmap[txrate].ieeerate, -1);
3809 bpf_mtap(ic->ic_rawbpf, m0);
3810 if (sc->sc_drvbpf) {
3811 uint64_t tsf = ath_hal_gettsf64(ah);
3813 sc->sc_tx_th.wt_tsf = htole64(tsf);
3814 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags;
3816 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3817 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate;
3818 sc->sc_tx_th.wt_txpower = ni->ni_txpower;
3819 sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
3821 bpf_ptap(sc->sc_drvbpf, m0, &sc->sc_tx_th, sc->sc_tx_th_len);
3825 * Determine if a tx interrupt should be generated for
3826 * this descriptor. We take a tx interrupt to reap
3827 * descriptors when the h/w hits an EOL condition or
3828 * when the descriptor is specifically marked to generate
3829 * an interrupt. We periodically mark descriptors in this
3830 * way to insure timely replenishing of the supply needed
3831 * for sending frames. Defering interrupts reduces system
3832 * load and potentially allows more concurrent work to be
3833 * done but if done to aggressively can cause senders to
3836 * NB: use >= to deal with sc_txintrperiod changing
3837 * dynamically through sysctl.
3839 if (flags & HAL_TXDESC_INTREQ) {
3840 txq->axq_intrcnt = 0;
3841 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) {
3842 flags |= HAL_TXDESC_INTREQ;
3843 txq->axq_intrcnt = 0;
3847 * Formulate first tx descriptor with tx controls.
3849 /* XXX check return value? */
3850 ath_hal_setuptxdesc(ah, ds
3851 , pktlen /* packet length */
3852 , hdrlen /* header length */
3853 , atype /* Atheros packet type */
3854 , ni->ni_txpower /* txpower */
3855 , txrate, try0 /* series 0 rate/tries */
3856 , keyix /* key cache index */
3857 , sc->sc_txantenna /* antenna mode */
3859 , ctsrate /* rts/cts rate */
3860 , ctsduration /* rts/cts duration */
3862 bf->bf_flags = flags;
3864 * Setup the multi-rate retry state only when we're
3865 * going to use it. This assumes ath_hal_setuptxdesc
3866 * initializes the descriptors (so we don't have to)
3867 * when the hardware supports multi-rate retry and
3871 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix);
3874 * Fillin the remainder of the descriptor info.
3877 for (i = 0; i < bf->bf_nseg; i++, ds++) {
3878 ds->ds_data = bf->bf_segs[i].ds_addr;
3879 if (i == bf->bf_nseg - 1)
3882 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1);
3883 ath_hal_filltxdesc(ah, ds
3884 , bf->bf_segs[i].ds_len /* segment length */
3885 , i == 0 /* first segment */
3886 , i == bf->bf_nseg - 1 /* last segment */
3887 , ds0 /* first descriptor */
3889 DPRINTF(sc, ATH_DEBUG_XMIT,
3890 "%s: %d: %08x %08x %08x %08x %08x %08x\n",
3891 __func__, i, ds->ds_link, ds->ds_data,
3892 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]);
3895 * Insert the frame on the outbound list and pass it on
3896 * to the hardware. Multicast frames buffered for power
3897 * save stations and transmit from the CAB queue are stored
3898 * on a s/w only queue and loaded on to the CAB queue in
3899 * the SWBA handler since frames only go out on DTIM and
3900 * to avoid possible races.
3902 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
3903 if (txq != &sc->sc_mcastq) {
3904 if (txq->axq_link == NULL) {
3905 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
3906 DPRINTF(sc, ATH_DEBUG_XMIT,
3907 "%s: TXDP[%u] = %p (%p) depth %d\n", __func__,
3908 txq->axq_qnum, (caddr_t)bf->bf_daddr, bf->bf_desc,
3911 *txq->axq_link = bf->bf_daddr;
3912 DPRINTF(sc, ATH_DEBUG_XMIT,
3913 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__,
3914 txq->axq_qnum, txq->axq_link,
3915 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth);
3917 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link;
3918 ath_hal_txstart(ah, txq->axq_qnum);
3920 if (txq->axq_link != NULL)
3921 *txq->axq_link = bf->bf_daddr;
3922 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link;
3929 * Process completed xmit descriptors from the specified queue.
3932 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
3934 struct ath_hal *ah = sc->sc_ah;
3935 struct ieee80211com *ic = &sc->sc_ic;
3937 struct ath_desc *ds, *ds0;
3938 struct ath_tx_status *ts;
3939 struct ieee80211_node *ni;
3940 struct ath_node *an;
3941 int sr, lr, pri, nacked;
3944 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
3945 __func__, txq->axq_qnum,
3946 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
3950 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
3951 bf = STAILQ_FIRST(&txq->axq_q);
3954 ds0 = &bf->bf_desc[0];
3955 ds = &bf->bf_desc[bf->bf_nseg - 1];
3956 ts = &bf->bf_status.ds_txstat;
3957 status = ath_hal_txprocdesc(ah, ds, ts);
3959 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
3960 ath_printtxbuf(bf, txq->axq_qnum, 0, status == HAL_OK);
3962 if (status == HAL_EINPROGRESS)
3964 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
3965 if (txq->axq_depth == 0)
3966 txq->axq_link = NULL;
3971 if (ts->ts_status == 0) {
3972 uint8_t txant = ts->ts_antenna;
3973 sc->sc_stats.ast_ant_tx[txant]++;
3974 sc->sc_ant_tx[txant]++;
3975 if (ts->ts_rate & HAL_TXSTAT_ALTRATE)
3976 sc->sc_stats.ast_tx_altrate++;
3977 sc->sc_stats.ast_tx_rssi = ts->ts_rssi;
3978 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
3980 pri = M_WME_GETAC(bf->bf_m);
3981 if (pri >= WME_AC_VO)
3982 ic->ic_wme.wme_hipri_traffic++;
3983 ni->ni_inact = ni->ni_inact_reload;
3985 if (ts->ts_status & HAL_TXERR_XRETRY)
3986 sc->sc_stats.ast_tx_xretries++;
3987 if (ts->ts_status & HAL_TXERR_FIFO)
3988 sc->sc_stats.ast_tx_fifoerr++;
3989 if (ts->ts_status & HAL_TXERR_FILT)
3990 sc->sc_stats.ast_tx_filtered++;
3992 sr = ts->ts_shortretry;
3993 lr = ts->ts_longretry;
3994 sc->sc_stats.ast_tx_shortretry += sr;
3995 sc->sc_stats.ast_tx_longretry += lr;
3997 * Hand the descriptor to the rate control algorithm.
3999 if ((ts->ts_status & HAL_TXERR_FILT) == 0 &&
4000 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
4002 * If frame was ack'd update the last rx time
4003 * used to workaround phantom bmiss interrupts.
4005 if (ts->ts_status == 0)
4007 ath_rate_tx_complete(sc, an, bf);
4010 * Reclaim reference to node.
4012 * NB: the node may be reclaimed here if, for example
4013 * this is a DEAUTH message that was sent and the
4014 * node was timed out due to inactivity.
4016 ieee80211_free_node(ni);
4018 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
4019 BUS_DMASYNC_POSTWRITE);
4020 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
4025 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
4031 txqactive(struct ath_hal *ah, int qnum)
4033 uint32_t txqs = 1<<qnum;
4034 ath_hal_gettxintrtxqs(ah, &txqs);
4035 return (txqs & (1<<qnum));
4039 * Deferred processing of transmit interrupt; special-cased
4040 * for a single hardware transmit queue (e.g. 5210 and 5211).
4043 ath_tx_proc_q0(struct ath_softc *sc)
4045 struct ifnet *ifp = &sc->sc_ic.ic_if;
4047 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0]))
4048 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4049 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum))
4050 ath_tx_processq(sc, sc->sc_cabq);
4051 ifp->if_flags &= ~IFF_OACTIVE;
4052 sc->sc_tx_timer = 0;
4055 ath_led_event(sc, ATH_LED_TX);
4061 * Deferred processing of transmit interrupt; special-cased
4062 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support).
4065 ath_tx_proc_q0123(struct ath_softc *sc)
4067 struct ifnet *ifp = &sc->sc_ic.ic_if;
4071 * Process each active queue.
4074 if (txqactive(sc->sc_ah, 0))
4075 nacked += ath_tx_processq(sc, &sc->sc_txq[0]);
4076 if (txqactive(sc->sc_ah, 1))
4077 nacked += ath_tx_processq(sc, &sc->sc_txq[1]);
4078 if (txqactive(sc->sc_ah, 2))
4079 nacked += ath_tx_processq(sc, &sc->sc_txq[2]);
4080 if (txqactive(sc->sc_ah, 3))
4081 nacked += ath_tx_processq(sc, &sc->sc_txq[3]);
4082 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum))
4083 ath_tx_processq(sc, sc->sc_cabq);
4085 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4087 ifp->if_flags &= ~IFF_OACTIVE;
4088 sc->sc_tx_timer = 0;
4091 ath_led_event(sc, ATH_LED_TX);
4097 * Deferred processing of transmit interrupt.
4100 ath_tx_proc(struct ath_softc *sc)
4102 struct ifnet *ifp = &sc->sc_ic.ic_if;
4106 * Process each active queue.
4109 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4110 if (IS_ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i))
4111 nacked += ath_tx_processq(sc, &sc->sc_txq[i]);
4113 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4115 ifp->if_flags &= ~IFF_OACTIVE;
4116 sc->sc_tx_timer = 0;
4119 ath_led_event(sc, ATH_LED_TX);
4125 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq)
4128 struct ath_hal *ah = sc->sc_ah;
4130 struct ieee80211_node *ni;
4135 * NB: this assumes output has been stopped and
4136 * we do not need to block ath_tx_tasklet
4138 for (ix = 0;; ix++) {
4139 bf = STAILQ_FIRST(&txq->axq_q);
4141 txq->axq_link = NULL;
4144 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
4146 if (sc->sc_debug & ATH_DEBUG_RESET) {
4147 ath_printtxbuf(bf, txq->axq_qnum, ix,
4148 ath_hal_txprocdesc(ah, bf->bf_desc,
4149 &bf->bf_status.ds_txstat) == HAL_OK);
4150 ieee80211_dump_pkt(mtod(bf->bf_m, caddr_t),
4151 bf->bf_m->m_len, 0, -1);
4153 #endif /* ATH_DEBUG */
4154 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
4161 * Reclaim node reference.
4163 ieee80211_free_node(ni);
4165 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
4170 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
4172 struct ath_hal *ah = sc->sc_ah;
4174 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
4175 __func__, txq->axq_qnum,
4176 (caddr_t)(uintptr_t)ath_hal_gettxbuf(ah, txq->axq_qnum),
4178 ath_hal_stoptxdma(ah, txq->axq_qnum);
4182 * Drain the transmit queues and reclaim resources.
4185 ath_draintxq(struct ath_softc *sc)
4187 struct ath_hal *ah = sc->sc_ah;
4188 struct ifnet *ifp = &sc->sc_ic.ic_if;
4191 ASSERT_SERIALIZED(ifp->if_serializer);
4193 /* XXX return value */
4194 if (!sc->sc_invalid) {
4195 /* don't touch the hardware if marked invalid */
4196 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p\n",
4197 __func__, sc->sc_bhalq,
4198 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq));
4199 ath_hal_stoptxdma(ah, sc->sc_bhalq);
4200 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4201 if (IS_ATH_TXQ_SETUP(sc, i))
4202 ath_tx_stopdma(sc, &sc->sc_txq[i]);
4204 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4205 if (IS_ATH_TXQ_SETUP(sc, i))
4206 ath_tx_draintxq(sc, &sc->sc_txq[i]);
4207 ath_tx_draintxq(sc, &sc->sc_mcastq);
4209 if (sc->sc_debug & ATH_DEBUG_RESET) {
4210 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf);
4211 if (bf != NULL && bf->bf_m != NULL) {
4212 ath_printtxbuf(bf, sc->sc_bhalq, 0,
4213 ath_hal_txprocdesc(ah, bf->bf_desc,
4214 &bf->bf_status.ds_txstat) == HAL_OK);
4215 ieee80211_dump_pkt(mtod(bf->bf_m, caddr_t),
4216 bf->bf_m->m_len, 0, -1);
4219 #endif /* ATH_DEBUG */
4220 ifp->if_flags &= ~IFF_OACTIVE;
4221 sc->sc_tx_timer = 0;
4225 * Disable the receive h/w in preparation for a reset.
4228 ath_stoprecv(struct ath_softc *sc)
4230 #define PA2DESC(_sc, _pa) \
4231 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
4232 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
4233 struct ath_hal *ah = sc->sc_ah;
4235 ASSERT_SERIALIZED(sc->sc_ic.ic_if.if_serializer);
4237 ath_hal_stoppcurecv(ah); /* disable PCU */
4238 ath_hal_setrxfilter(ah, 0); /* clear recv filter */
4239 ath_hal_stopdmarecv(ah); /* disable DMA engine */
4240 DELAY(3000); /* 3ms is long enough for 1 frame */
4242 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) {
4246 kprintf("%s: rx queue %p, link %p\n", __func__,
4247 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah),
4250 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
4251 struct ath_desc *ds = bf->bf_desc;
4252 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat;
4255 status = ath_hal_rxprocdesc(ah, ds, bf->bf_daddr,
4256 PA2DESC(sc, ds->ds_link),
4258 if (status == HAL_OK ||
4259 (sc->sc_debug & ATH_DEBUG_FATAL))
4260 ath_printrxbuf(bf, ix, status == HAL_OK);
4265 sc->sc_rxlink = NULL; /* just in case */
4270 * Enable the receive h/w following a reset.
4273 ath_startrecv(struct ath_softc *sc)
4275 struct ath_hal *ah = sc->sc_ah;
4278 ASSERT_SERIALIZED(sc->sc_ic.ic_if.if_serializer);
4280 sc->sc_rxlink = NULL;
4281 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
4282 int error = ath_rxbuf_init(sc, bf);
4284 DPRINTF(sc, ATH_DEBUG_RECV,
4285 "%s: ath_rxbuf_init failed %d\n",
4291 bf = STAILQ_FIRST(&sc->sc_rxbuf);
4292 ath_hal_putrxbuf(ah, bf->bf_daddr);
4293 ath_hal_rxena(ah); /* enable recv descriptors */
4294 ath_mode_init(sc); /* set filters, etc. */
4295 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */
4300 * Update internal state after a channel change.
4303 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan)
4305 struct ieee80211com *ic = &sc->sc_ic;
4306 enum ieee80211_phymode mode;
4310 * Change channels and update the h/w rate map
4311 * if we're switching; e.g. 11a to 11b/g.
4313 mode = ieee80211_chan2mode(ic, chan);
4314 if (mode != sc->sc_curmode)
4315 ath_setcurmode(sc, mode);
4317 * Update BPF state. NB: ethereal et. al. don't handle
4318 * merged flags well so pick a unique mode for their use.
4320 if (IEEE80211_IS_CHAN_A(chan))
4321 flags = IEEE80211_CHAN_A;
4322 /* XXX 11g schizophrenia */
4323 else if (IEEE80211_IS_CHAN_G(chan) ||
4324 IEEE80211_IS_CHAN_PUREG(chan))
4325 flags = IEEE80211_CHAN_G;
4327 flags = IEEE80211_CHAN_B;
4328 if (IEEE80211_IS_CHAN_T(chan))
4329 flags |= IEEE80211_CHAN_TURBO;
4330 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq =
4331 htole16(chan->ic_freq);
4332 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags =
4337 * Poll for a channel clear indication; this is required
4338 * for channels requiring DFS and not previously visited
4339 * and/or with a recent radar detection.
4343 ath_dfswait(void *arg)
4345 struct ath_softc *sc = arg;
4346 struct ath_hal *ah = sc->sc_ah;
4347 struct ifnet *ifp = &sc->sc_ic.ic_if;
4350 lwkt_serialize_enter(ifp->if_serializer);
4352 ath_hal_radar_wait(ah, &hchan);
4353 DPRINTF(sc, ATH_DEBUG_DFS, "%s: radar_wait %u/%x/%x\n",
4354 __func__, hchan.channel, hchan.channelFlags, hchan.privFlags);
4356 if (hchan.privFlags & CHANNEL_INTERFERENCE) {
4357 if_printf(ifp, "channel %u/0x%x/0x%x has interference\n",
4358 hchan.channel, hchan.channelFlags, hchan.privFlags);
4361 if ((hchan.privFlags & CHANNEL_DFS) == 0) {
4362 /* XXX should not happen */
4365 if (hchan.privFlags & CHANNEL_DFS_CLEAR) {
4366 sc->sc_curchan.privFlags |= CHANNEL_DFS_CLEAR;
4367 ifp->if_flags &= ~IFF_OACTIVE;
4368 if_printf(ifp, "channel %u/0x%x/0x%x marked clear\n",
4369 hchan.channel, hchan.channelFlags, hchan.privFlags);
4371 callout_reset(&sc->sc_dfs_ch, 2 * hz, ath_dfswait, sc);
4375 lwkt_serialize_exit(ifp->if_serializer);
4380 * Set/change channels. If the channel is really being changed,
4381 * it's done by reseting the chip. To accomplish this we must
4382 * first cleanup any pending DMA, then restart stuff after a la
4386 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
4388 struct ath_hal *ah = sc->sc_ah;
4389 struct ieee80211com *ic = &sc->sc_ic;
4390 struct ifnet *ifp = &ic->ic_if;
4394 * Convert to a HAL channel description with
4395 * the flags constrained to reflect the current
4398 hchan.channel = chan->ic_freq;
4399 hchan.channelFlags = ath_chan2flags(ic, chan);
4401 DPRINTF(sc, ATH_DEBUG_RESET,
4402 "%s: %u (%u MHz, hal flags 0x%x) -> %u (%u MHz, hal flags 0x%x)\n",
4404 ath_hal_mhz2ieee(ah, sc->sc_curchan.channel,
4405 sc->sc_curchan.channelFlags),
4406 sc->sc_curchan.channel, sc->sc_curchan.channelFlags,
4407 ath_hal_mhz2ieee(ah, hchan.channel, hchan.channelFlags),
4408 hchan.channel, hchan.channelFlags);
4409 if (hchan.channel != sc->sc_curchan.channel ||
4410 hchan.channelFlags != sc->sc_curchan.channelFlags) {
4414 * To switch channels clear any pending DMA operations;
4415 * wait long enough for the RX fifo to drain, reset the
4416 * hardware at the new frequency, and then re-enable
4417 * the relevant bits of the h/w.
4419 ath_hal_intrset(ah, 0); /* disable interrupts */
4420 ath_draintxq(sc); /* clear pending tx frames */
4421 ath_stoprecv(sc); /* turn off frame recv */
4422 if (!ath_hal_reset(ah, sc->sc_opmode, &hchan, AH_FALSE, &status)) {
4423 if_printf(ifp, "%s: unable to reset "
4424 "channel %u (%u Mhz, flags 0x%x hal flags 0x%x)\n",
4425 __func__, ieee80211_chan2ieee(ic, chan),
4426 chan->ic_freq, chan->ic_flags, hchan.channelFlags);
4429 sc->sc_curchan = hchan;
4430 ath_update_txpow(sc); /* update tx power state */
4431 sc->sc_diversity = ath_hal_getdiversity(ah);
4432 sc->sc_calinterval = 1;
4433 sc->sc_caltries = 0;
4436 * Re-enable rx framework.
4438 if (ath_startrecv(sc) != 0) {
4439 if_printf(ic->ic_ifp,
4440 "%s: unable to restart recv logic\n", __func__);
4445 * Change channels and update the h/w rate map
4446 * if we're switching; e.g. 11a to 11b/g.
4448 ic->ic_ibss_chan = chan;
4449 ath_chan_change(sc, chan);
4453 * Handle DFS required waiting period to determine
4454 * if channel is clear of radar traffic.
4456 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
4457 #define DFS_AND_NOT_CLEAR(_c) \
4458 (((_c)->privFlags & (CHANNEL_DFS | CHANNEL_DFS_CLEAR)) == CHANNEL_DFS)
4459 if (DFS_AND_NOT_CLEAR(&sc->sc_curchan)) {
4461 "wait for DFS clear channel signal\n");
4463 ifp->if_flags |= IFF_OACTIVE;
4464 callout_reset(&sc->sc_dfs_ch,
4465 2 * hz, ath_dfswait, sc);
4467 callout_stop(&sc->sc_dfs_ch);
4469 #undef DFS_NOT_CLEAR
4474 * Re-enable interrupts.
4476 ath_hal_intrset(ah, sc->sc_imask);
4482 ath_next_scan(void *arg)
4484 struct ath_softc *sc = arg;
4485 struct ieee80211com *ic = &sc->sc_ic;
4486 struct ifnet *ifp = &ic->ic_if;
4488 lwkt_serialize_enter(ifp->if_serializer);
4490 if (ic->ic_state == IEEE80211_S_SCAN)
4491 ieee80211_next_scan(ic);
4493 lwkt_serialize_exit(ifp->if_serializer);
4497 * Periodically recalibrate the PHY to account
4498 * for temperature/environment changes.
4501 ath_calibrate(void *arg)
4503 struct ath_softc *sc = arg;
4504 struct ath_hal *ah = sc->sc_ah;
4505 struct ifnet *ifp = &sc->sc_ic.ic_if;
4508 lwkt_serialize_enter(ifp->if_serializer);
4510 sc->sc_stats.ast_per_cal++;
4512 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) {
4514 * Rfgain is out of bounds, reset the chip
4515 * to load new gain values.
4517 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
4518 "%s: rfgain change\n", __func__);
4519 sc->sc_stats.ast_per_rfgain++;
4520 ath_reset(&sc->sc_ic.ic_if);
4522 if (!ath_hal_calibrate(ah, &sc->sc_curchan, &iqCalDone)) {
4523 DPRINTF(sc, ATH_DEBUG_ANY,
4524 "%s: calibration of channel %u failed\n",
4525 __func__, sc->sc_curchan.channel);
4526 sc->sc_stats.ast_per_calfail++;
4529 * Calibrate noise floor data again in case of change.
4531 ath_hal_process_noisefloor(ah);
4533 * Poll more frequently when the IQ calibration is in
4534 * progress to speedup loading the final settings.
4535 * We temper this aggressive polling with an exponential
4536 * back off after 4 tries up to ath_calinterval.
4538 if (iqCalDone || sc->sc_calinterval >= ath_calinterval) {
4539 sc->sc_caltries = 0;
4540 sc->sc_calinterval = ath_calinterval;
4541 } else if (sc->sc_caltries > 4) {
4542 sc->sc_caltries = 0;
4543 sc->sc_calinterval <<= 1;
4544 if (sc->sc_calinterval > ath_calinterval)
4545 sc->sc_calinterval = ath_calinterval;
4547 KASSERT(0 < sc->sc_calinterval && sc->sc_calinterval <= ath_calinterval,
4548 ("bad calibration interval %u", sc->sc_calinterval));
4550 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
4551 "%s: next +%u (%siqCalDone tries %u)\n", __func__,
4552 sc->sc_calinterval, iqCalDone ? "" : "!", sc->sc_caltries);
4554 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz,
4557 lwkt_serialize_exit(ifp->if_serializer);
4561 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
4563 struct ifnet *ifp = ic->ic_ifp;
4564 struct ath_softc *sc = ifp->if_softc;
4565 struct ath_hal *ah = sc->sc_ah;
4566 struct ieee80211_node *ni;
4568 const uint8_t *bssid;
4570 static const HAL_LED_STATE leds[] = {
4571 HAL_LED_INIT, /* IEEE80211_S_INIT */
4572 HAL_LED_SCAN, /* IEEE80211_S_SCAN */
4573 HAL_LED_AUTH, /* IEEE80211_S_AUTH */
4574 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */
4575 HAL_LED_RUN, /* IEEE80211_S_RUN */
4578 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__,
4579 ieee80211_state_name[ic->ic_state],
4580 ieee80211_state_name[nstate]);
4582 callout_stop(&sc->sc_scan_ch);
4583 callout_stop(&sc->sc_cal_ch);
4584 callout_stop(&sc->sc_dfs_ch);
4585 ath_hal_setledstate(ah, leds[nstate]); /* set LED */
4587 if (nstate == IEEE80211_S_INIT) {
4588 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
4590 * NB: disable interrupts so we don't rx frames.
4592 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL);
4594 * Notify the rate control algorithm.
4596 ath_rate_newstate(sc, nstate);
4600 error = ath_chan_set(sc, ic->ic_curchan);
4603 rfilt = ath_calcrxfilter(sc, nstate);
4604 if (nstate == IEEE80211_S_SCAN)
4605 bssid = ifp->if_broadcastaddr;
4607 bssid = ni->ni_bssid;
4608 ath_hal_setrxfilter(ah, rfilt);
4609 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %6D\n",
4610 __func__, rfilt, bssid, ":");
4612 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA)
4613 ath_hal_setassocid(ah, bssid, ni->ni_associd);
4615 ath_hal_setassocid(ah, bssid, 0);
4616 if (ic->ic_flags & IEEE80211_F_PRIVACY) {
4617 for (i = 0; i < IEEE80211_WEP_NKID; i++)
4618 if (ath_hal_keyisvalid(ah, i))
4619 ath_hal_keysetmac(ah, i, bssid);
4623 * Notify the rate control algorithm so rates
4624 * are setup should ath_beacon_alloc be called.
4626 ath_rate_newstate(sc, nstate);
4628 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
4629 /* nothing to do */;
4630 } else if (nstate == IEEE80211_S_RUN) {
4631 DPRINTF(sc, ATH_DEBUG_STATE,
4632 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%6D "
4633 "capinfo=0x%04x chan=%d\n"
4639 , ieee80211_chan2ieee(ic, ic->ic_curchan));
4641 switch (ic->ic_opmode) {
4642 case IEEE80211_M_HOSTAP:
4643 case IEEE80211_M_IBSS:
4645 * Allocate and setup the beacon frame.
4647 * Stop any previous beacon DMA. This may be
4648 * necessary, for example, when an ibss merge
4649 * causes reconfiguration; there will be a state
4650 * transition from RUN->RUN that means we may
4651 * be called with beacon transmission active.
4653 ath_hal_stoptxdma(ah, sc->sc_bhalq);
4654 ath_beacon_free(sc);
4655 error = ath_beacon_alloc(sc, ni);
4659 * If joining an adhoc network defer beacon timer
4660 * configuration to the next beacon frame so we
4661 * have a current TSF to use. Otherwise we're
4662 * starting an ibss/bss so there's no need to delay.
4664 if (ic->ic_opmode == IEEE80211_M_IBSS &&
4665 ic->ic_bss->ni_tstamp.tsf != 0)
4666 sc->sc_syncbeacon = 1;
4668 ath_beacon_config(sc);
4670 case IEEE80211_M_STA:
4672 * Allocate a key cache slot to the station.
4674 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 &&
4676 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE)
4677 ath_setup_stationkey(ni);
4679 * Defer beacon timer configuration to the next
4680 * beacon frame so we have a current TSF to use
4681 * (any TSF collected when scanning is likely old).
4683 sc->sc_syncbeacon = 1;
4690 * Let the hal process statistics collected during a
4691 * scan so it can provide calibrated noise floor data.
4693 ath_hal_process_noisefloor(ah);
4695 * Reset rssi stats; maybe not the best place...
4697 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
4698 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
4699 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
4702 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS));
4703 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
4707 * Invoke the parent method to complete the work.
4709 error = sc->sc_newstate(ic, nstate, arg);
4711 * Finally, start any timers.
4713 if (nstate == IEEE80211_S_RUN) {
4714 /* start periodic recalibration timer */
4715 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz,
4717 } else if (nstate == IEEE80211_S_SCAN) {
4718 /* start ap/neighbor scan timer */
4719 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000,
4727 * Allocate a key cache slot to the station so we can
4728 * setup a mapping from key index to node. The key cache
4729 * slot is needed for managing antenna state and for
4730 * compression when stations do not use crypto. We do
4731 * it uniliaterally here; if crypto is employed this slot
4732 * will be reassigned.
4735 ath_setup_stationkey(struct ieee80211_node *ni)
4737 struct ieee80211com *ic = ni->ni_ic;
4738 struct ath_softc *sc = ic->ic_ifp->if_softc;
4739 ieee80211_keyix keyix, rxkeyix;
4741 if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) {
4743 * Key cache is full; we'll fall back to doing
4744 * the more expensive lookup in software. Note
4745 * this also means no h/w compression.
4747 /* XXX msg+statistic */
4750 ni->ni_ucastkey.wk_keyix = keyix;
4751 ni->ni_ucastkey.wk_rxkeyix = rxkeyix;
4752 /* NB: this will create a pass-thru key entry */
4753 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss);
4758 * Setup driver-specific state for a newly associated node.
4759 * Note that we're called also on a re-associate, the isnew
4760 * param tells us if this is the first time or not.
4763 ath_newassoc(struct ieee80211_node *ni, int isnew)
4765 struct ieee80211com *ic = ni->ni_ic;
4766 struct ath_softc *sc = ic->ic_ifp->if_softc;
4768 ath_rate_newassoc(sc, ATH_NODE(ni), isnew);
4770 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) {
4771 KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE,
4772 ("new assoc with a unicast key already setup (keyix %u)",
4773 ni->ni_ucastkey.wk_keyix));
4774 ath_setup_stationkey(ni);
4779 ath_getchannels(struct ath_softc *sc, u_int cc,
4780 HAL_BOOL outdoor, HAL_BOOL xchanmode)
4782 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE)
4783 struct ieee80211com *ic = &sc->sc_ic;
4784 struct ifnet *ifp = &ic->ic_if;
4785 struct ath_hal *ah = sc->sc_ah;
4789 chans = kmalloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), M_TEMP,
4792 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan,
4794 cc, HAL_MODE_ALL, outdoor, xchanmode)) {
4797 (void) ath_hal_getregdomain(ah, &rd);
4798 if_printf(ifp, "unable to collect channel list from hal; "
4799 "regdomain likely %u country code %u\n", rd, cc);
4800 kfree(chans, M_TEMP);
4805 * Convert HAL channels to ieee80211 ones and insert
4806 * them in the table according to their channel number.
4808 for (i = 0; i < nchan; i++) {
4809 HAL_CHANNEL *c = &chans[i];
4812 ix = ath_hal_mhz2ieee(ah, c->channel, c->channelFlags);
4813 if (ix > IEEE80211_CHAN_MAX) {
4814 if_printf(ifp, "bad hal channel %d (%u/%x) ignored\n",
4815 ix, c->channel, c->channelFlags);
4819 /* XXX can't handle stuff <2400 right now */
4821 if_printf(ifp, "hal channel %d (%u/%x) "
4822 "cannot be handled; ignored\n",
4823 ix, c->channel, c->channelFlags);
4827 * Calculate net80211 flags; most are compatible
4828 * but some need massaging. Note the static turbo
4829 * conversion can be removed once net80211 is updated
4830 * to understand static vs. dynamic turbo.
4832 flags = c->channelFlags & COMPAT;
4833 if (c->channelFlags & CHANNEL_STURBO)
4834 flags |= IEEE80211_CHAN_TURBO;
4835 if (ic->ic_channels[ix].ic_freq == 0) {
4836 ic->ic_channels[ix].ic_freq = c->channel;
4837 ic->ic_channels[ix].ic_flags = flags;
4839 /* channels overlap; e.g. 11g and 11b */
4840 ic->ic_channels[ix].ic_flags |= flags;
4843 kfree(chans, M_TEMP);
4849 ath_led_done(void *arg)
4851 struct ath_softc *sc = arg;
4853 sc->sc_blinking = 0;
4857 * Turn the LED off: flip the pin and then set a timer so no
4858 * update will happen for the specified duration.
4861 ath_led_off(void *arg)
4863 struct ath_softc *sc = arg;
4865 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
4866 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc);
4870 * Blink the LED according to the specified on/off times.
4873 ath_led_blink(struct ath_softc *sc, int on, int off)
4875 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off);
4876 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon);
4877 sc->sc_blinking = 1;
4878 sc->sc_ledoff = off;
4879 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc);
4883 ath_led_event(struct ath_softc *sc, int event)
4886 sc->sc_ledevent = ticks; /* time of last event */
4887 if (sc->sc_blinking) /* don't interrupt active blink */
4891 ath_led_blink(sc, sc->sc_hwmap[0].ledon,
4892 sc->sc_hwmap[0].ledoff);
4895 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon,
4896 sc->sc_hwmap[sc->sc_txrate].ledoff);
4899 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon,
4900 sc->sc_hwmap[sc->sc_rxrate].ledoff);
4906 ath_update_txpow(struct ath_softc *sc)
4908 struct ieee80211com *ic = &sc->sc_ic;
4909 struct ath_hal *ah = sc->sc_ah;
4912 if (sc->sc_curtxpow != ic->ic_txpowlimit) {
4913 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit);
4914 /* read back in case value is clamped */
4915 (void) ath_hal_gettxpowlimit(ah, &txpow);
4916 ic->ic_txpowlimit = sc->sc_curtxpow = txpow;
4919 * Fetch max tx power level for status requests.
4921 (void) ath_hal_getmaxtxpow(sc->sc_ah, &txpow);
4922 ic->ic_bss->ni_txpower = txpow;
4926 rate_setup(struct ath_softc *sc,
4927 const HAL_RATE_TABLE *rt, struct ieee80211_rateset *rs)
4931 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) {
4932 DPRINTF(sc, ATH_DEBUG_ANY,
4933 "%s: rate table too small (%u > %u)\n",
4934 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE);
4935 maxrates = IEEE80211_RATE_MAXSIZE;
4937 maxrates = rt->rateCount;
4938 for (i = 0; i < maxrates; i++)
4939 rs->rs_rates[i] = rt->info[i].dot11Rate;
4940 rs->rs_nrates = maxrates;
4944 ath_rate_setup(struct ath_softc *sc, u_int mode)
4946 struct ath_hal *ah = sc->sc_ah;
4947 struct ieee80211com *ic = &sc->sc_ic;
4948 const HAL_RATE_TABLE *rt;
4951 case IEEE80211_MODE_11A:
4952 rt = ath_hal_getratetable(ah, HAL_MODE_11A);
4954 case IEEE80211_MODE_11B:
4955 rt = ath_hal_getratetable(ah, HAL_MODE_11B);
4957 case IEEE80211_MODE_11G:
4958 rt = ath_hal_getratetable(ah, HAL_MODE_11G);
4960 case IEEE80211_MODE_TURBO_A:
4961 /* XXX until static/dynamic turbo is fixed */
4962 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO);
4964 case IEEE80211_MODE_TURBO_G:
4965 rt = ath_hal_getratetable(ah, HAL_MODE_108G);
4968 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n",
4972 sc->sc_rates[mode] = rt;
4974 rate_setup(sc, rt, &ic->ic_sup_rates[mode]);
4981 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode)
4983 #define N(a) (sizeof(a)/sizeof(a[0]))
4984 /* NB: on/off times from the Atheros NDIS driver, w/ permission */
4985 static const struct {
4986 u_int rate; /* tx/rx 802.11 rate */
4987 uint16_t timeOn; /* LED on time (ms) */
4988 uint16_t timeOff; /* LED off time (ms) */
5005 const HAL_RATE_TABLE *rt;
5008 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
5009 rt = sc->sc_rates[mode];
5010 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
5011 for (i = 0; i < rt->rateCount; i++)
5012 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i;
5013 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap));
5014 for (i = 0; i < 32; i++) {
5015 uint8_t ix = rt->rateCodeToIndex[i];
5017 sc->sc_hwmap[i].ledon = (500 * hz) / 1000;
5018 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000;
5021 sc->sc_hwmap[i].ieeerate =
5022 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL;
5023 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
5024 if (rt->info[ix].shortPreamble ||
5025 rt->info[ix].phy == IEEE80211_T_OFDM)
5026 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE;
5027 /* NB: receive frames include FCS */
5028 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags |
5029 IEEE80211_RADIOTAP_F_FCS;
5030 /* setup blink rate table to avoid per-packet lookup */
5031 for (j = 0; j < N(blinkrates)-1; j++)
5032 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate)
5034 /* NB: this uses the last entry if the rate isn't found */
5035 /* XXX beware of overlow */
5036 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000;
5037 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000;
5039 sc->sc_currates = rt;
5040 sc->sc_curmode = mode;
5042 * All protection frames are transmited at 2Mb/s for
5043 * 11g, otherwise at 1Mb/s.
5045 if (mode == IEEE80211_MODE_11G)
5046 sc->sc_protrix = ath_tx_findrix(rt, 2 * 2);
5048 sc->sc_protrix = ath_tx_findrix(rt, 2 * 1);
5049 /* rate index used to send management frames */
5050 sc->sc_minrateix = 0;
5052 * Setup multicast rate state.
5054 /* XXX layering violation */
5055 sc->sc_mcastrix = ath_tx_findrix(rt, sc->sc_ic.ic_mcast_rate);
5056 sc->sc_mcastrate = sc->sc_ic.ic_mcast_rate;
5057 /* NB: caller is responsible for reseting rate control state */
5063 ath_printrxbuf(const struct ath_buf *bf, u_int ix, int done)
5065 const struct ath_rx_status *rs = &bf->bf_status.ds_rxstat;
5066 const struct ath_desc *ds;
5069 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
5070 kprintf("R[%2u] (DS.V:%p DS.P:%p) L:%08x D:%08x%s\n"
5071 " %08x %08x %08x %08x\n",
5072 ix, ds, (const struct ath_desc *)bf->bf_daddr + i,
5073 ds->ds_link, ds->ds_data,
5074 !done ? "" : (rs->rs_status == 0) ? " *" : " !",
5075 ds->ds_ctl0, ds->ds_ctl1,
5076 ds->ds_hw[0], ds->ds_hw[1]);
5081 ath_printtxbuf(const struct ath_buf *bf, u_int qnum, u_int ix, int done)
5083 const struct ath_tx_status *ts = &bf->bf_status.ds_txstat;
5084 const struct ath_desc *ds;
5087 kprintf("Q%u[%3u]", qnum, ix);
5088 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
5089 kprintf(" (DS.V:%p DS.P:%p) L:%08x D:%08x F:04%x%s\n"
5090 " %08x %08x %08x %08x %08x %08x\n",
5091 ds, (const struct ath_desc *)bf->bf_daddr + i,
5092 ds->ds_link, ds->ds_data, bf->bf_flags,
5093 !done ? "" : (ts->ts_status == 0) ? " *" : " !",
5094 ds->ds_ctl0, ds->ds_ctl1,
5095 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3]);
5098 #endif /* ATH_DEBUG */
5101 ath_watchdog(struct ifnet *ifp)
5103 struct ath_softc *sc = ifp->if_softc;
5104 struct ieee80211com *ic = &sc->sc_ic;
5107 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid)
5109 if (sc->sc_tx_timer) {
5110 if (--sc->sc_tx_timer == 0) {
5111 if_printf(ifp, "device timeout\n");
5114 sc->sc_stats.ast_watchdog++;
5118 ieee80211_watchdog(ic);
5123 * Diagnostic interface to the HAL. This is used by various
5124 * tools to do things like retrieve register contents for
5125 * debugging. The mechanism is intentionally opaque so that
5126 * it can change frequently w/o concern for compatiblity.
5129 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad)
5131 struct ath_hal *ah = sc->sc_ah;
5132 u_int id = ad->ad_id & ATH_DIAG_ID;
5133 void *indata = NULL;
5134 void *outdata = NULL;
5135 uint32_t insize = ad->ad_in_size;
5136 uint32_t outsize = ad->ad_out_size;
5139 if (ad->ad_id & ATH_DIAG_IN) {
5143 indata = kmalloc(insize, M_TEMP, M_NOWAIT);
5144 if (indata == NULL) {
5148 error = copyin(ad->ad_in_data, indata, insize);
5152 if (ad->ad_id & ATH_DIAG_DYN) {
5154 * Allocate a buffer for the results (otherwise the HAL
5155 * returns a pointer to a buffer where we can read the
5156 * results). Note that we depend on the HAL leaving this
5157 * pointer for us to use below in reclaiming the buffer;
5158 * may want to be more defensive.
5160 outdata = kmalloc(outsize, M_TEMP, M_NOWAIT);
5161 if (outdata == NULL) {
5166 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) {
5167 if (outsize < ad->ad_out_size)
5168 ad->ad_out_size = outsize;
5169 if (outdata != NULL)
5170 error = copyout(outdata, ad->ad_out_data,
5176 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL)
5177 kfree(indata, M_TEMP);
5178 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL)
5179 kfree(outdata, M_TEMP);
5182 #endif /* ATH_DIAGAPI */
5185 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
5187 #define IS_RUNNING(ifp) \
5188 ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING))
5189 struct ath_softc *sc = ifp->if_softc;
5190 struct ieee80211com *ic = &sc->sc_ic;
5191 struct ifreq *ifr = (struct ifreq *)data;
5194 ASSERT_SERIALIZED(ifp->if_serializer);
5198 if (IS_RUNNING(ifp)) {
5200 * To avoid rescanning another access point,
5201 * do not call ath_init() here. Instead,
5202 * only reflect promisc mode settings.
5205 } else if (ifp->if_flags & IFF_UP) {
5207 * Beware of being called during attach/detach
5208 * to reset promiscuous mode. In that case we
5209 * will still be marked UP but not RUNNING.
5210 * However trying to re-init the interface
5211 * is the wrong thing to do as we've already
5212 * torn down much of our state. There's
5213 * probably a better way to deal with this.
5215 if (!sc->sc_invalid && ic->ic_bss != NULL)
5216 ath_init(sc); /* XXX lose error */
5218 ath_stop_no_pwchg(ifp);
5223 * The upper layer has already installed/removed
5224 * the multicast address(es), just recalculate the
5225 * multicast filter for the card.
5227 if (ifp->if_flags & IFF_RUNNING)
5231 /* NB: embed these numbers to get a consistent view */
5232 sc->sc_stats.ast_tx_packets = ifp->if_opackets;
5233 sc->sc_stats.ast_rx_packets = ifp->if_ipackets;
5234 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic);
5235 sc->sc_stats.ast_rx_noise =
5236 ath_hal_getchannoise(sc->sc_ah, &sc->sc_curchan);
5237 sc->sc_stats.ast_tx_rate = sc->sc_hwmap[sc->sc_txrate].ieeerate;
5238 return copyout(&sc->sc_stats,
5239 ifr->ifr_data, sizeof (sc->sc_stats));
5242 error = ath_ioctl_diag(sc, (struct ath_diag *)ifr);
5246 error = ieee80211_ioctl(ic, cmd, data, cr);
5247 if (error == ENETRESET) {
5248 if (IS_RUNNING(ifp) &&
5249 ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
5250 ath_init(sc); /* XXX lose error */
5253 if (error == ERESTART)
5254 error = IS_RUNNING(ifp) ? ath_reset(ifp) : 0;
5262 ath_sysctl_slottime(SYSCTL_HANDLER_ARGS)
5264 struct ath_softc *sc = arg1;
5265 struct ifnet *ifp = &sc->sc_ic.ic_if;
5269 lwkt_serialize_enter(ifp->if_serializer);
5271 slottime = ath_hal_getslottime(sc->sc_ah);
5272 error = sysctl_handle_int(oidp, &slottime, 0, req);
5273 if (error || !req->newptr)
5275 error = !ath_hal_setslottime(sc->sc_ah, slottime) ? EINVAL : 0;
5277 lwkt_serialize_exit(ifp->if_serializer);
5282 ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS)
5284 struct ath_softc *sc = arg1;
5285 struct ifnet *ifp = &sc->sc_ic.ic_if;
5289 lwkt_serialize_enter(ifp->if_serializer);
5291 acktimeout = ath_hal_getacktimeout(sc->sc_ah);
5292 error = sysctl_handle_int(oidp, &acktimeout, 0, req);
5293 if (error || !req->newptr)
5295 error = !ath_hal_setacktimeout(sc->sc_ah, acktimeout) ? EINVAL : 0;
5297 lwkt_serialize_exit(ifp->if_serializer);
5302 ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS)
5304 struct ath_softc *sc = arg1;
5305 struct ifnet *ifp = &sc->sc_ic.ic_if;
5309 lwkt_serialize_enter(ifp->if_serializer);
5311 ctstimeout = ath_hal_getctstimeout(sc->sc_ah);
5312 error = sysctl_handle_int(oidp, &ctstimeout, 0, req);
5313 if (error || !req->newptr)
5315 error = !ath_hal_setctstimeout(sc->sc_ah, ctstimeout) ? EINVAL : 0;
5317 lwkt_serialize_exit(ifp->if_serializer);
5322 ath_sysctl_softled(SYSCTL_HANDLER_ARGS)
5324 struct ath_softc *sc = arg1;
5325 struct ifnet *ifp = &sc->sc_ic.ic_if;
5329 lwkt_serialize_enter(ifp->if_serializer);
5331 softled = sc->sc_softled;
5332 error = sysctl_handle_int(oidp, &softled, 0, req);
5333 if (error || !req->newptr)
5335 softled = (softled != 0);
5336 if (softled != sc->sc_softled) {
5338 /* NB: handle any sc_ledpin change */
5339 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin);
5340 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin,
5343 sc->sc_softled = softled;
5346 lwkt_serialize_exit(ifp->if_serializer);
5351 ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS)
5353 struct ath_softc *sc = arg1;
5354 struct ifnet *ifp = &sc->sc_ic.ic_if;
5358 lwkt_serialize_enter(ifp->if_serializer);
5360 defantenna = ath_hal_getdefantenna(sc->sc_ah);
5361 error = sysctl_handle_int(oidp, &defantenna, 0, req);
5362 if (!error && req->newptr)
5363 ath_hal_setdefantenna(sc->sc_ah, defantenna);
5365 lwkt_serialize_exit(ifp->if_serializer);
5370 ath_sysctl_diversity(SYSCTL_HANDLER_ARGS)
5372 struct ath_softc *sc = arg1;
5373 struct ifnet *ifp = &sc->sc_ic.ic_if;
5377 lwkt_serialize_enter(ifp->if_serializer);
5379 diversity = ath_hal_getdiversity(sc->sc_ah);
5380 error = sysctl_handle_int(oidp, &diversity, 0, req);
5381 if (error || !req->newptr)
5383 if (!ath_hal_setdiversity(sc->sc_ah, diversity)) {
5387 sc->sc_diversity = diversity;
5390 lwkt_serialize_exit(ifp->if_serializer);
5395 ath_sysctl_diag(SYSCTL_HANDLER_ARGS)
5397 struct ath_softc *sc = arg1;
5398 struct ifnet *ifp = &sc->sc_ic.ic_if;
5402 lwkt_serialize_enter(ifp->if_serializer);
5404 if (!ath_hal_getdiag(sc->sc_ah, &diag)) {
5408 error = sysctl_handle_int(oidp, &diag, 0, req);
5409 if (error || !req->newptr)
5411 error = !ath_hal_setdiag(sc->sc_ah, diag) ? EINVAL : 0;
5413 lwkt_serialize_exit(ifp->if_serializer);
5418 ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS)
5420 struct ath_softc *sc = arg1;
5421 struct ifnet *ifp = &sc->sc_ic.ic_if;
5425 lwkt_serialize_enter(ifp->if_serializer);
5427 (void) ath_hal_gettpscale(sc->sc_ah, &scale);
5428 error = sysctl_handle_int(oidp, &scale, 0, req);
5429 if (error || !req->newptr)
5431 error = !ath_hal_settpscale(sc->sc_ah, scale) ? EINVAL : ath_reset(ifp);
5433 lwkt_serialize_exit(ifp->if_serializer);
5438 ath_sysctl_tpc(SYSCTL_HANDLER_ARGS)
5440 struct ath_softc *sc = arg1;
5441 struct ifnet *ifp = &sc->sc_ic.ic_if;
5445 lwkt_serialize_enter(ifp->if_serializer);
5447 tpc = ath_hal_gettpc(sc->sc_ah);
5448 error = sysctl_handle_int(oidp, &tpc, 0, req);
5449 if (error || !req->newptr)
5451 error = !ath_hal_settpc(sc->sc_ah, tpc) ? EINVAL : 0;
5453 lwkt_serialize_exit(ifp->if_serializer);
5458 ath_sysctl_rfkill(SYSCTL_HANDLER_ARGS)
5460 struct ath_softc *sc = arg1;
5461 struct ifnet *ifp = &sc->sc_ic.ic_if;
5462 struct ath_hal *ah = sc->sc_ah;
5466 lwkt_serialize_enter(ifp->if_serializer);
5468 rfkill = ath_hal_getrfkill(ah);
5469 error = sysctl_handle_int(oidp, &rfkill, 0, req);
5470 if (error || !req->newptr)
5475 if (rfkill == ath_hal_getrfkill(ah)) /* unchanged */
5478 if (!ath_hal_setrfkill(ah, rfkill) || ath_reset(&sc->sc_ic.ic_if) != 0)
5481 lwkt_serialize_exit(ifp->if_serializer);
5486 ath_sysctl_rfsilent(SYSCTL_HANDLER_ARGS)
5488 struct ath_softc *sc = arg1;
5489 struct ifnet *ifp = &sc->sc_ic.ic_if;
5493 lwkt_serialize_enter(ifp->if_serializer);
5495 (void) ath_hal_getrfsilent(sc->sc_ah, &rfsilent);
5496 error = sysctl_handle_int(oidp, &rfsilent, 0, req);
5497 if (error || !req->newptr)
5499 if (!ath_hal_setrfsilent(sc->sc_ah, rfsilent)) {
5503 sc->sc_rfsilentpin = rfsilent & 0x1c;
5504 sc->sc_rfsilentpol = (rfsilent & 0x2) != 0;
5507 lwkt_serialize_exit(ifp->if_serializer);
5512 ath_sysctl_regdomain(SYSCTL_HANDLER_ARGS)
5514 struct ath_softc *sc = arg1;
5515 struct ifnet *ifp = &sc->sc_ic.ic_if;
5519 lwkt_serialize_enter(ifp->if_serializer);
5521 if (!ath_hal_getregdomain(sc->sc_ah, &rd)) {
5525 error = sysctl_handle_int(oidp, &rd, 0, req);
5526 if (error || !req->newptr)
5528 error = !ath_hal_setregdomain(sc->sc_ah, rd) ? EINVAL : 0;
5530 lwkt_serialize_exit(ifp->if_serializer);
5535 ath_sysctl_tpack(SYSCTL_HANDLER_ARGS)
5537 struct ath_softc *sc = arg1;
5538 struct ifnet *ifp = &sc->sc_ic.ic_if;
5542 lwkt_serialize_enter(ifp->if_serializer);
5544 (void) ath_hal_gettpack(sc->sc_ah, &tpack);
5545 error = sysctl_handle_int(oidp, &tpack, 0, req);
5546 if (error || !req->newptr)
5548 error = !ath_hal_settpack(sc->sc_ah, tpack) ? EINVAL : 0;
5550 lwkt_serialize_exit(ifp->if_serializer);
5555 ath_sysctl_tpcts(SYSCTL_HANDLER_ARGS)
5557 struct ath_softc *sc = arg1;
5558 struct ifnet *ifp = &sc->sc_ic.ic_if;
5562 lwkt_serialize_enter(ifp->if_serializer);
5564 (void) ath_hal_gettpcts(sc->sc_ah, &tpcts);
5565 error = sysctl_handle_int(oidp, &tpcts, 0, req);
5566 if (error || !req->newptr)
5568 error = !ath_hal_settpcts(sc->sc_ah, tpcts) ? EINVAL : 0;
5570 lwkt_serialize_exit(ifp->if_serializer);
5575 ath_sysctlattach(struct ath_softc *sc)
5577 struct sysctl_ctx_list *ctx = &sc->sc_sysctl_ctx;
5578 struct sysctl_oid *tree = sc->sc_sysctl_tree;
5579 struct ath_hal *ah = sc->sc_ah;
5581 ath_hal_getcountrycode(sc->sc_ah, &sc->sc_countrycode);
5582 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5583 "countrycode", CTLFLAG_RD, &sc->sc_countrycode, 0,
5584 "EEPROM country code");
5585 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5586 "regdomain", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5587 ath_sysctl_regdomain, "I", "EEPROM regdomain code");
5589 sc->sc_debug = ath_debug;
5590 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5591 "debug", CTLFLAG_RW, &sc->sc_debug, 0,
5592 "control debugging kprintfs");
5594 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5595 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5596 ath_sysctl_slottime, "I", "802.11 slot time (us)");
5597 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5598 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5599 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)");
5600 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5601 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5602 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)");
5603 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5604 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5605 ath_sysctl_softled, "I", "enable/disable software LED support");
5606 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5607 "ledpin", CTLFLAG_RW, &sc->sc_ledpin, 0,
5608 "GPIO pin connected to LED");
5609 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5610 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0,
5611 "setting to turn LED on");
5612 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5613 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0,
5614 "idle time for inactivity LED (ticks)");
5615 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5616 "txantenna", CTLFLAG_RW, &sc->sc_txantenna, 0,
5617 "tx antenna (0=auto)");
5618 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5619 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5620 ath_sysctl_rxantenna, "I", "default/rx antenna");
5621 if (ath_hal_hasdiversity(ah))
5622 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5623 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5624 ath_sysctl_diversity, "I", "antenna diversity");
5625 sc->sc_txintrperiod = ATH_TXINTR_PERIOD;
5626 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5627 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0,
5628 "tx descriptor batching");
5629 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5630 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5631 ath_sysctl_diag, "I", "h/w diagnostic control");
5632 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5633 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5634 ath_sysctl_tpscale, "I", "tx power scaling");
5635 if (ath_hal_hastpc(ah)) {
5636 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5637 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5638 ath_sysctl_tpc, "I", "enable/disable per-packet TPC");
5639 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5640 "tpack", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5641 ath_sysctl_tpack, "I", "tx power for ack frames");
5642 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5643 "tpcts", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5644 ath_sysctl_tpcts, "I", "tx power for cts frames");
5646 if (ath_hal_hasrfsilent(ah)) {
5647 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5648 "rfsilent", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5649 ath_sysctl_rfsilent, "I", "h/w RF silent config");
5650 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5651 "rfkill", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5652 ath_sysctl_rfkill, "I", "enable/disable RF kill switch");
5654 sc->sc_monpass = HAL_RXERR_DECRYPT | HAL_RXERR_MIC;
5655 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5656 "monpass", CTLFLAG_RW, &sc->sc_monpass, 0,
5657 "mask of error frames to pass when monitoring");
5661 ath_bpfattach(struct ath_softc *sc)
5663 struct ifnet *ifp = &sc->sc_ic.ic_if;
5665 bpfattach_dlt(ifp, DLT_IEEE802_11_RADIO,
5666 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th),
5669 * Initialize constant fields.
5670 * XXX make header lengths a multiple of 32-bits so subsequent
5671 * headers are properly aligned; this is a kludge to keep
5672 * certain applications happy.
5674 * NB: the channel is setup each time we transition to the
5675 * RUN state to avoid filling it in for each frame.
5677 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(uint32_t));
5678 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len);
5679 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT);
5681 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(uint32_t));
5682 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len);
5683 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT);
5687 * Announce various information on device/driver attach.
5690 ath_announce(struct ath_softc *sc)
5692 #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B)
5693 struct ifnet *ifp = &sc->sc_ic.ic_if;
5694 struct ath_hal *ah = sc->sc_ah;
5697 if_printf(ifp, "mac %d.%d phy %d.%d",
5698 ah->ah_macVersion, ah->ah_macRev,
5699 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);
5701 * Print radio revision(s). We check the wireless modes
5702 * to avoid falsely printing revs for inoperable parts.
5703 * Dual-band radio revs are returned in the 5Ghz rev number.
5705 ath_hal_getcountrycode(ah, &cc);
5706 modes = ath_hal_getwirelessmodes(ah, cc);
5707 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) {
5708 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev)
5709 kprintf(" 5ghz radio %d.%d 2ghz radio %d.%d",
5710 ah->ah_analog5GhzRev >> 4,
5711 ah->ah_analog5GhzRev & 0xf,
5712 ah->ah_analog2GhzRev >> 4,
5713 ah->ah_analog2GhzRev & 0xf);
5715 kprintf(" radio %d.%d", ah->ah_analog5GhzRev >> 4,
5716 ah->ah_analog5GhzRev & 0xf);
5718 kprintf(" radio %d.%d", ah->ah_analog5GhzRev >> 4,
5719 ah->ah_analog5GhzRev & 0xf);
5723 for (i = 0; i <= WME_AC_VO; i++) {
5724 struct ath_txq *txq = sc->sc_ac2q[i];
5725 if_printf(ifp, "Use hw queue %u for %s traffic\n",
5726 txq->axq_qnum, ieee80211_wme_acnames[i]);
5728 if_printf(ifp, "Use hw queue %u for CAB traffic\n",
5729 sc->sc_cabq->axq_qnum);
5730 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq);
5732 if (ath_rxbuf != ATH_RXBUF)
5733 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf);
5734 if (ath_txbuf != ATH_TXBUF)
5735 if_printf(ifp, "using %u tx buffers\n", ath_txbuf);
5736 #undef HAL_MODE_DUALBAND
5740 ath_dma_map_mbuf(void *arg, bus_dma_segment_t *segs, int nseg,
5741 bus_size_t mapsize, int error)
5743 struct ath_buf *bf = arg;
5748 KASSERT(nseg <= ATH_MAX_SCATTER, ("too many DMA segments"));
5749 bcopy(segs, bf->bf_segs, nseg * sizeof(bus_dma_segment_t));