69d2559b211efec3d17ab2e1b0c7ab9887934ce8
[dragonfly.git] / sys / dev / netif / bce / if_bce.c
1 /*-
2  * Copyright (c) 2006-2007 Broadcom Corporation
3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  *
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
15  *    may be used to endorse or promote products derived from this software
16  *    without specific prior written consent.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28  * THE POSSIBILITY OF SUCH DAMAGE.
29  *
30  * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
31  */
32
33 /*
34  * The following controllers are supported by this driver:
35  *   BCM5706C A2, A3
36  *   BCM5706S A2, A3
37  *   BCM5708C B1, B2
38  *   BCM5708S B1, B2
39  *   BCM5709C A1, C0
40  *   BCM5716  C0
41  *
42  * The following controllers are not supported by this driver:
43  *   BCM5706C A0, A1
44  *   BCM5706S A0, A1
45  *   BCM5708C A0, B0
46  *   BCM5708S A0, B0
47  *   BCM5709C A0, B0, B1
48  *   BCM5709S A0, A1, B0, B1, B2, C0
49  */
50
51 #include "opt_bce.h"
52 #include "opt_polling.h"
53
54 #include <sys/param.h>
55 #include <sys/bus.h>
56 #include <sys/endian.h>
57 #include <sys/kernel.h>
58 #include <sys/interrupt.h>
59 #include <sys/mbuf.h>
60 #include <sys/malloc.h>
61 #include <sys/queue.h>
62 #ifdef BCE_DEBUG
63 #include <sys/random.h>
64 #endif
65 #include <sys/rman.h>
66 #include <sys/serialize.h>
67 #include <sys/socket.h>
68 #include <sys/sockio.h>
69 #include <sys/sysctl.h>
70
71 #include <net/bpf.h>
72 #include <net/ethernet.h>
73 #include <net/if.h>
74 #include <net/if_arp.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
77 #include <net/if_types.h>
78 #include <net/ifq_var.h>
79 #include <net/vlan/if_vlan_var.h>
80 #include <net/vlan/if_vlan_ether.h>
81
82 #include <dev/netif/mii_layer/mii.h>
83 #include <dev/netif/mii_layer/miivar.h>
84
85 #include <bus/pci/pcireg.h>
86 #include <bus/pci/pcivar.h>
87
88 #include "miibus_if.h"
89
90 #include <dev/netif/bce/if_bcereg.h>
91 #include <dev/netif/bce/if_bcefw.h>
92
93 /****************************************************************************/
94 /* BCE Debug Options                                                        */
95 /****************************************************************************/
96 #ifdef BCE_DEBUG
97
98 static uint32_t bce_debug = BCE_WARN;
99
100 /*
101  *          0 = Never             
102  *          1 = 1 in 2,147,483,648
103  *        256 = 1 in     8,388,608
104  *       2048 = 1 in     1,048,576
105  *      65536 = 1 in        32,768
106  *    1048576 = 1 in         2,048
107  *  268435456 = 1 in             8
108  *  536870912 = 1 in             4
109  * 1073741824 = 1 in             2
110  *
111  * bce_debug_l2fhdr_status_check:
112  *     How often the l2_fhdr frame error check will fail.
113  *
114  * bce_debug_unexpected_attention:
115  *     How often the unexpected attention check will fail.
116  *
117  * bce_debug_mbuf_allocation_failure:
118  *     How often to simulate an mbuf allocation failure.
119  *
120  * bce_debug_dma_map_addr_failure:
121  *     How often to simulate a DMA mapping failure.
122  *
123  * bce_debug_bootcode_running_failure:
124  *     How often to simulate a bootcode failure.
125  */
126 static int      bce_debug_l2fhdr_status_check = 0;
127 static int      bce_debug_unexpected_attention = 0;
128 static int      bce_debug_mbuf_allocation_failure = 0;
129 static int      bce_debug_dma_map_addr_failure = 0;
130 static int      bce_debug_bootcode_running_failure = 0;
131
132 #endif  /* BCE_DEBUG */
133
134
135 /****************************************************************************/
136 /* PCI Device ID Table                                                      */
137 /*                                                                          */
138 /* Used by bce_probe() to identify the devices supported by this driver.    */
139 /****************************************************************************/
140 #define BCE_DEVDESC_MAX         64
141
142 static struct bce_type bce_devs[] = {
143         /* BCM5706C Controllers and OEM boards. */
144         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
145                 "HP NC370T Multifunction Gigabit Server Adapter" },
146         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
147                 "HP NC370i Multifunction Gigabit Server Adapter" },
148         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
149                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
150         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
151                 "HP NC371i Multifunction Gigabit Server Adapter" },
152         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
153                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
154
155         /* BCM5706S controllers and OEM boards. */
156         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
157                 "HP NC370F Multifunction Gigabit Server Adapter" },
158         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
159                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
160
161         /* BCM5708C controllers and OEM boards. */
162         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
163                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
164         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
165                 "HP NC373i Multifunction Gigabit Server Adapter" },
166         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
167                 "HP NC374m PCIe Multifunction Adapter" },
168         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
169                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
170
171         /* BCM5708S controllers and OEM boards. */
172         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
173                 "HP NC373m Multifunction Gigabit Server Adapter" },
174         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
175                 "HP NC373i Multifunction Gigabit Server Adapter" },
176         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
177                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
178         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
179                 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
180
181         /* BCM5709C controllers and OEM boards. */
182         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
183                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
184         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
185                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
186         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
187                 "Broadcom NetXtreme II BCM5709 1000Base-T" },
188
189         /* BCM5709S controllers and OEM boards. */
190         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
191                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
192         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
193                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
194         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
195                 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
196
197         /* BCM5716 controllers and OEM boards. */
198         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,   PCI_ANY_ID,  PCI_ANY_ID,
199                 "Broadcom NetXtreme II BCM5716 1000Base-T" },
200
201         { 0, 0, 0, 0, NULL }
202 };
203
204
205 /****************************************************************************/
206 /* Supported Flash NVRAM device data.                                       */
207 /****************************************************************************/
208 static const struct flash_spec flash_table[] =
209 {
210 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
211 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
212
213         /* Slow EEPROM */
214         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
215          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
216          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
217          "EEPROM - slow"},
218         /* Expansion entry 0001 */
219         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
220          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
221          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
222          "Entry 0001"},
223         /* Saifun SA25F010 (non-buffered flash) */
224         /* strap, cfg1, & write1 need updates */
225         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
226          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
227          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
228          "Non-buffered flash (128kB)"},
229         /* Saifun SA25F020 (non-buffered flash) */
230         /* strap, cfg1, & write1 need updates */
231         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
232          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
233          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
234          "Non-buffered flash (256kB)"},
235         /* Expansion entry 0100 */
236         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
237          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
238          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
239          "Entry 0100"},
240         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
241         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
242          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
243          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
244          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
245         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
246         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
247          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
248          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
249          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
250         /* Saifun SA25F005 (non-buffered flash) */
251         /* strap, cfg1, & write1 need updates */
252         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
253          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
254          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
255          "Non-buffered flash (64kB)"},
256         /* Fast EEPROM */
257         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
258          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
259          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
260          "EEPROM - fast"},
261         /* Expansion entry 1001 */
262         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
263          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
264          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
265          "Entry 1001"},
266         /* Expansion entry 1010 */
267         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
268          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
269          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
270          "Entry 1010"},
271         /* ATMEL AT45DB011B (buffered flash) */
272         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
273          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
274          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
275          "Buffered flash (128kB)"},
276         /* Expansion entry 1100 */
277         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
278          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
279          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
280          "Entry 1100"},
281         /* Expansion entry 1101 */
282         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
283          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
284          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
285          "Entry 1101"},
286         /* Ateml Expansion entry 1110 */
287         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
288          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
289          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
290          "Entry 1110 (Atmel)"},
291         /* ATMEL AT45DB021B (buffered flash) */
292         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
293          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
294          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
295          "Buffered flash (256kB)"},
296 };
297
298 /*
299  * The BCM5709 controllers transparently handle the
300  * differences between Atmel 264 byte pages and all
301  * flash devices which use 256 byte pages, so no
302  * logical-to-physical mapping is required in the
303  * driver.
304  */
305 static struct flash_spec flash_5709 = {
306         .flags          = BCE_NV_BUFFERED,
307         .page_bits      = BCM5709_FLASH_PAGE_BITS,
308         .page_size      = BCM5709_FLASH_PAGE_SIZE,
309         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
310         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
311         .name           = "5709/5716 buffered flash (256kB)",
312 };
313
314
315 /****************************************************************************/
316 /* DragonFly device entry points.                                           */
317 /****************************************************************************/
318 static int      bce_probe(device_t);
319 static int      bce_attach(device_t);
320 static int      bce_detach(device_t);
321 static void     bce_shutdown(device_t);
322
323 /****************************************************************************/
324 /* BCE Debug Data Structure Dump Routines                                   */
325 /****************************************************************************/
326 #ifdef BCE_DEBUG
327 static void     bce_dump_mbuf(struct bce_softc *, struct mbuf *);
328 static void     bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
329 static void     bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
330 static void     bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
331 static void     bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
332 static void     bce_dump_l2fhdr(struct bce_softc *, int,
333                                 struct l2_fhdr *) __unused;
334 static void     bce_dump_tx_chain(struct bce_softc *, int, int);
335 static void     bce_dump_rx_chain(struct bce_softc *, int, int);
336 static void     bce_dump_status_block(struct bce_softc *);
337 static void     bce_dump_driver_state(struct bce_softc *);
338 static void     bce_dump_stats_block(struct bce_softc *) __unused;
339 static void     bce_dump_hw_state(struct bce_softc *);
340 static void     bce_dump_txp_state(struct bce_softc *);
341 static void     bce_dump_rxp_state(struct bce_softc *) __unused;
342 static void     bce_dump_tpat_state(struct bce_softc *) __unused;
343 static void     bce_freeze_controller(struct bce_softc *) __unused;
344 static void     bce_unfreeze_controller(struct bce_softc *) __unused;
345 static void     bce_breakpoint(struct bce_softc *);
346 #endif  /* BCE_DEBUG */
347
348
349 /****************************************************************************/
350 /* BCE Register/Memory Access Routines                                      */
351 /****************************************************************************/
352 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
353 static void     bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
354 static void     bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
355 static uint32_t bce_shmem_rd(struct bce_softc *, u32);
356 static void     bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
357 static int      bce_miibus_read_reg(device_t, int, int);
358 static int      bce_miibus_write_reg(device_t, int, int, int);
359 static void     bce_miibus_statchg(device_t);
360
361
362 /****************************************************************************/
363 /* BCE NVRAM Access Routines                                                */
364 /****************************************************************************/
365 static int      bce_acquire_nvram_lock(struct bce_softc *);
366 static int      bce_release_nvram_lock(struct bce_softc *);
367 static void     bce_enable_nvram_access(struct bce_softc *);
368 static void     bce_disable_nvram_access(struct bce_softc *);
369 static int      bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
370                                      uint32_t);
371 static int      bce_init_nvram(struct bce_softc *);
372 static int      bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
373 static int      bce_nvram_test(struct bce_softc *);
374
375 /****************************************************************************/
376 /* BCE DMA Allocate/Free Routines                                           */
377 /****************************************************************************/
378 static int      bce_dma_alloc(struct bce_softc *);
379 static void     bce_dma_free(struct bce_softc *);
380 static void     bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
381
382 /****************************************************************************/
383 /* BCE Firmware Synchronization and Load                                    */
384 /****************************************************************************/
385 static int      bce_fw_sync(struct bce_softc *, uint32_t);
386 static void     bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
387                                  uint32_t, uint32_t);
388 static void     bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
389                                 struct fw_info *);
390 static void     bce_init_rxp_cpu(struct bce_softc *);
391 static void     bce_init_txp_cpu(struct bce_softc *);
392 static void     bce_init_tpat_cpu(struct bce_softc *);
393 static void     bce_init_cp_cpu(struct bce_softc *);
394 static void     bce_init_com_cpu(struct bce_softc *);
395 static void     bce_init_cpus(struct bce_softc *);
396
397 static void     bce_stop(struct bce_softc *);
398 static int      bce_reset(struct bce_softc *, uint32_t);
399 static int      bce_chipinit(struct bce_softc *);
400 static int      bce_blockinit(struct bce_softc *);
401 static int      bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
402                                uint32_t *, int);
403 static void     bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
404 static void     bce_probe_pci_caps(struct bce_softc *);
405 static void     bce_print_adapter_info(struct bce_softc *);
406 static void     bce_get_media(struct bce_softc *);
407
408 static void     bce_init_tx_context(struct bce_softc *);
409 static int      bce_init_tx_chain(struct bce_softc *);
410 static void     bce_init_rx_context(struct bce_softc *);
411 static int      bce_init_rx_chain(struct bce_softc *);
412 static void     bce_free_rx_chain(struct bce_softc *);
413 static void     bce_free_tx_chain(struct bce_softc *);
414
415 static int      bce_encap(struct bce_softc *, struct mbuf **);
416 static void     bce_start(struct ifnet *);
417 static int      bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
418 static void     bce_watchdog(struct ifnet *);
419 static int      bce_ifmedia_upd(struct ifnet *);
420 static void     bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
421 static void     bce_init(void *);
422 static void     bce_mgmt_init(struct bce_softc *);
423
424 static void     bce_init_ctx(struct bce_softc *);
425 static void     bce_get_mac_addr(struct bce_softc *);
426 static void     bce_set_mac_addr(struct bce_softc *);
427 static void     bce_phy_intr(struct bce_softc *);
428 static void     bce_rx_intr(struct bce_softc *, int);
429 static void     bce_tx_intr(struct bce_softc *);
430 static void     bce_disable_intr(struct bce_softc *);
431 static void     bce_enable_intr(struct bce_softc *, int);
432
433 #ifdef DEVICE_POLLING
434 static void     bce_poll(struct ifnet *, enum poll_cmd, int);
435 #endif
436 static void     bce_intr(void *);
437 static void     bce_set_rx_mode(struct bce_softc *);
438 static void     bce_stats_update(struct bce_softc *);
439 static void     bce_tick(void *);
440 static void     bce_tick_serialized(struct bce_softc *);
441 static void     bce_pulse(void *);
442 static void     bce_add_sysctls(struct bce_softc *);
443
444 static void     bce_coal_change(struct bce_softc *);
445 static int      bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
446 static int      bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
447 static int      bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
448 static int      bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
449 static int      bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
450 static int      bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
451 static int      bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
452 static int      bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
453 static int      bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
454                                        uint32_t *, uint32_t);
455
456 /*
457  * NOTE:
458  * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023.  Linux's bnx2
459  * takes 1023 as the TX ticks limit.  However, using 1023 will
460  * cause 5708(B2) to generate extra interrupts (~2000/s) even when
461  * there is _no_ network activity on the NIC.
462  */
463 static uint32_t bce_tx_bds_int = 255;           /* bcm: 20 */
464 static uint32_t bce_tx_bds = 255;               /* bcm: 20 */
465 static uint32_t bce_tx_ticks_int = 1022;        /* bcm: 80 */
466 static uint32_t bce_tx_ticks = 1022;            /* bcm: 80 */
467 static uint32_t bce_rx_bds_int = 128;           /* bcm: 6 */
468 static uint32_t bce_rx_bds = 128;               /* bcm: 6 */
469 static uint32_t bce_rx_ticks_int = 125;         /* bcm: 18 */
470 static uint32_t bce_rx_ticks = 125;             /* bcm: 18 */
471
472 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
473 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
474 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
475 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
476 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
477 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
478 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
479 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
480
481 /****************************************************************************/
482 /* DragonFly device dispatch table.                                         */
483 /****************************************************************************/
484 static device_method_t bce_methods[] = {
485         /* Device interface */
486         DEVMETHOD(device_probe,         bce_probe),
487         DEVMETHOD(device_attach,        bce_attach),
488         DEVMETHOD(device_detach,        bce_detach),
489         DEVMETHOD(device_shutdown,      bce_shutdown),
490
491         /* bus interface */
492         DEVMETHOD(bus_print_child,      bus_generic_print_child),
493         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
494
495         /* MII interface */
496         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
497         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
498         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
499
500         { 0, 0 }
501 };
502
503 static driver_t bce_driver = {
504         "bce",
505         bce_methods,
506         sizeof(struct bce_softc)
507 };
508
509 static devclass_t bce_devclass;
510
511
512 DECLARE_DUMMY_MODULE(if_bce);
513 MODULE_DEPEND(bce, miibus, 1, 1, 1);
514 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
515 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
516
517
518 /****************************************************************************/
519 /* Device probe function.                                                   */
520 /*                                                                          */
521 /* Compares the device to the driver's list of supported devices and        */
522 /* reports back to the OS whether this is the right driver for the device.  */
523 /*                                                                          */
524 /* Returns:                                                                 */
525 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
526 /****************************************************************************/
527 static int
528 bce_probe(device_t dev)
529 {
530         struct bce_type *t;
531         uint16_t vid, did, svid, sdid;
532
533         /* Get the data for the device to be probed. */
534         vid  = pci_get_vendor(dev);
535         did  = pci_get_device(dev);
536         svid = pci_get_subvendor(dev);
537         sdid = pci_get_subdevice(dev);
538
539         /* Look through the list of known devices for a match. */
540         for (t = bce_devs; t->bce_name != NULL; ++t) {
541                 if (vid == t->bce_vid && did == t->bce_did && 
542                     (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
543                     (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
544                         uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
545                         char *descbuf;
546
547                         descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
548
549                         /* Print out the device identity. */
550                         ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
551                                   t->bce_name,
552                                   ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
553
554                         device_set_desc_copy(dev, descbuf);
555                         kfree(descbuf, M_TEMP);
556                         return 0;
557                 }
558         }
559         return ENXIO;
560 }
561
562
563 /****************************************************************************/
564 /* PCI Capabilities Probe Function.                                         */
565 /*                                                                          */
566 /* Walks the PCI capabiites list for the device to find what features are   */
567 /* supported.                                                               */
568 /*                                                                          */
569 /* Returns:                                                                 */
570 /*   None.                                                                  */
571 /****************************************************************************/
572 static void
573 bce_print_adapter_info(struct bce_softc *sc)
574 {
575         device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
576
577         kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
578                 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
579
580         /* Bus info. */
581         if (sc->bce_flags & BCE_PCIE_FLAG) {
582                 kprintf("Bus (PCIe x%d, ", sc->link_width);
583                 switch (sc->link_speed) {
584                 case 1:
585                         kprintf("2.5Gbps); ");
586                         break;
587                 case 2:
588                         kprintf("5Gbps); ");
589                         break;
590                 default:
591                         kprintf("Unknown link speed); ");
592                         break;
593                 }
594         } else {
595                 kprintf("Bus (PCI%s, %s, %dMHz); ",
596                     ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
597                     ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
598                     sc->bus_speed_mhz);
599         }
600
601         /* Firmware version and device features. */
602         kprintf("B/C (%s)", sc->bce_bc_ver);
603
604         if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
605             (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
606                 kprintf("; Flags(");
607                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
608                         kprintf("MFW[%s]", sc->bce_mfw_ver);
609                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
610                         kprintf(" 2.5G");
611                 kprintf(")");
612         }
613         kprintf("\n");
614 }
615
616
617 /****************************************************************************/
618 /* PCI Capabilities Probe Function.                                         */
619 /*                                                                          */
620 /* Walks the PCI capabiites list for the device to find what features are   */
621 /* supported.                                                               */
622 /*                                                                          */
623 /* Returns:                                                                 */
624 /*   None.                                                                  */
625 /****************************************************************************/
626 static void
627 bce_probe_pci_caps(struct bce_softc *sc)
628 {
629         device_t dev = sc->bce_dev;
630         uint8_t ptr;
631
632         if (pci_is_pcix(dev))
633                 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
634
635         ptr = pci_get_pciecap_ptr(dev);
636         if (ptr) {
637                 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
638
639                 sc->link_speed = link_status & 0xf;
640                 sc->link_width = (link_status >> 4) & 0x3f;
641                 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
642                 sc->bce_flags |= BCE_PCIE_FLAG;
643         }
644 }
645
646
647 /****************************************************************************/
648 /* Device attach function.                                                  */
649 /*                                                                          */
650 /* Allocates device resources, performs secondary chip identification,      */
651 /* resets and initializes the hardware, and initializes driver instance     */
652 /* variables.                                                               */
653 /*                                                                          */
654 /* Returns:                                                                 */
655 /*   0 on success, positive value on failure.                               */
656 /****************************************************************************/
657 static int
658 bce_attach(device_t dev)
659 {
660         struct bce_softc *sc = device_get_softc(dev);
661         struct ifnet *ifp = &sc->arpcom.ac_if;
662         uint32_t val;
663         int rid, rc = 0;
664         int i, j;
665 #ifdef notyet
666         int count;
667 #endif
668
669         sc->bce_dev = dev;
670         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
671
672         pci_enable_busmaster(dev);
673
674         bce_probe_pci_caps(sc);
675
676         /* Allocate PCI memory resources. */
677         rid = PCIR_BAR(0);
678         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
679                                                  RF_ACTIVE | PCI_RF_DENSE);
680         if (sc->bce_res_mem == NULL) {
681                 device_printf(dev, "PCI memory allocation failed\n");
682                 return ENXIO;
683         }
684         sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
685         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
686
687         /* Allocate PCI IRQ resources. */
688 #ifdef notyet
689         count = pci_msi_count(dev);
690         if (count == 1 && pci_alloc_msi(dev, &count) == 0) {
691                 rid = 1;
692                 sc->bce_flags |= BCE_USING_MSI_FLAG;
693         } else
694 #endif
695         rid = 0;
696         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
697                                                  RF_SHAREABLE | RF_ACTIVE);
698         if (sc->bce_res_irq == NULL) {
699                 device_printf(dev, "PCI map interrupt failed\n");
700                 rc = ENXIO;
701                 goto fail;
702         }
703
704         /*
705          * Configure byte swap and enable indirect register access.
706          * Rely on CPU to do target byte swapping on big endian systems.
707          * Access to registers outside of PCI configurtion space are not
708          * valid until this is done.
709          */
710         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
711                          BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
712                          BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
713
714         /* Save ASIC revsion info. */
715         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
716
717         /* Weed out any non-production controller revisions. */
718         switch (BCE_CHIP_ID(sc)) {
719         case BCE_CHIP_ID_5706_A0:
720         case BCE_CHIP_ID_5706_A1:
721         case BCE_CHIP_ID_5708_A0:
722         case BCE_CHIP_ID_5708_B0:
723         case BCE_CHIP_ID_5709_A0:
724         case BCE_CHIP_ID_5709_B0:
725         case BCE_CHIP_ID_5709_B1:
726 #ifdef foo
727         /* 5709C B2 seems to work fine */
728         case BCE_CHIP_ID_5709_B2:
729 #endif
730                 device_printf(dev, "Unsupported chip id 0x%08x!\n",
731                               BCE_CHIP_ID(sc));
732                 rc = ENODEV;
733                 goto fail;
734         }
735
736         /*
737          * Find the base address for shared memory access.
738          * Newer versions of bootcode use a signature and offset
739          * while older versions use a fixed address.
740          */
741         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
742         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
743             BCE_SHM_HDR_SIGNATURE_SIG) {
744                 /* Multi-port devices use different offsets in shared memory. */
745                 sc->bce_shmem_base = REG_RD_IND(sc,
746                     BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
747         } else {
748                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
749         }
750         DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
751
752         /* Fetch the bootcode revision. */
753         val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
754         for (i = 0, j = 0; i < 3; i++) {
755                 uint8_t num;
756                 int k, skip0;
757
758                 num = (uint8_t)(val >> (24 - (i * 8)));
759                 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
760                         if (num >= k || !skip0 || k == 1) {
761                                 sc->bce_bc_ver[j++] = (num / k) + '0';
762                                 skip0 = 0;
763                         }
764                 }
765                 if (i != 2)
766                         sc->bce_bc_ver[j++] = '.';
767         }
768
769         /* Check if any management firwmare is running. */
770         val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
771         if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
772                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
773
774                 /* Allow time for firmware to enter the running state. */
775                 for (i = 0; i < 30; i++) {
776                         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
777                         if (val & BCE_CONDITION_MFW_RUN_MASK)
778                                 break;
779                         DELAY(10000);
780                 }
781         }
782
783         /* Check the current bootcode state. */
784         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
785             BCE_CONDITION_MFW_RUN_MASK;
786         if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
787             val != BCE_CONDITION_MFW_RUN_NONE) {
788                 uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
789
790                 for (i = 0, j = 0; j < 3; j++) {
791                         val = bce_reg_rd_ind(sc, addr + j * 4);
792                         val = bswap32(val);
793                         memcpy(&sc->bce_mfw_ver[i], &val, 4);
794                         i += 4;
795                 }
796         }
797
798         /* Get PCI bus information (speed and type). */
799         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
800         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
801                 uint32_t clkreg;
802
803                 sc->bce_flags |= BCE_PCIX_FLAG;
804
805                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
806                          BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
807                 switch (clkreg) {
808                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
809                         sc->bus_speed_mhz = 133;
810                         break;
811
812                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
813                         sc->bus_speed_mhz = 100;
814                         break;
815
816                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
817                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
818                         sc->bus_speed_mhz = 66;
819                         break;
820
821                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
822                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
823                         sc->bus_speed_mhz = 50;
824                         break;
825
826                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
827                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
828                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
829                         sc->bus_speed_mhz = 33;
830                         break;
831                 }
832         } else {
833                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
834                         sc->bus_speed_mhz = 66;
835                 else
836                         sc->bus_speed_mhz = 33;
837         }
838
839         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
840                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
841
842         /* Reset the controller. */
843         rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
844         if (rc != 0)
845                 goto fail;
846
847         /* Initialize the controller. */
848         rc = bce_chipinit(sc);
849         if (rc != 0) {
850                 device_printf(dev, "Controller initialization failed!\n");
851                 goto fail;
852         }
853
854         /* Perform NVRAM test. */
855         rc = bce_nvram_test(sc);
856         if (rc != 0) {
857                 device_printf(dev, "NVRAM test failed!\n");
858                 goto fail;
859         }
860
861         /* Fetch the permanent Ethernet MAC address. */
862         bce_get_mac_addr(sc);
863
864         /*
865          * Trip points control how many BDs
866          * should be ready before generating an
867          * interrupt while ticks control how long
868          * a BD can sit in the chain before
869          * generating an interrupt.  Set the default 
870          * values for the RX and TX rings.
871          */
872
873 #ifdef BCE_DRBUG
874         /* Force more frequent interrupts. */
875         sc->bce_tx_quick_cons_trip_int = 1;
876         sc->bce_tx_quick_cons_trip     = 1;
877         sc->bce_tx_ticks_int           = 0;
878         sc->bce_tx_ticks               = 0;
879
880         sc->bce_rx_quick_cons_trip_int = 1;
881         sc->bce_rx_quick_cons_trip     = 1;
882         sc->bce_rx_ticks_int           = 0;
883         sc->bce_rx_ticks               = 0;
884 #else
885         sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
886         sc->bce_tx_quick_cons_trip     = bce_tx_bds;
887         sc->bce_tx_ticks_int           = bce_tx_ticks_int;
888         sc->bce_tx_ticks               = bce_tx_ticks;
889
890         sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
891         sc->bce_rx_quick_cons_trip     = bce_rx_bds;
892         sc->bce_rx_ticks_int           = bce_rx_ticks_int;
893         sc->bce_rx_ticks               = bce_rx_ticks;
894 #endif
895
896         /* Update statistics once every second. */
897         sc->bce_stats_ticks = 1000000 & 0xffff00;
898
899         /* Find the media type for the adapter. */
900         bce_get_media(sc);
901
902         /* Allocate DMA memory resources. */
903         rc = bce_dma_alloc(sc);
904         if (rc != 0) {
905                 device_printf(dev, "DMA resource allocation failed!\n");
906                 goto fail;
907         }
908
909         /* Initialize the ifnet interface. */
910         ifp->if_softc = sc;
911         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
912         ifp->if_ioctl = bce_ioctl;
913         ifp->if_start = bce_start;
914         ifp->if_init = bce_init;
915         ifp->if_watchdog = bce_watchdog;
916 #ifdef DEVICE_POLLING
917         ifp->if_poll = bce_poll;
918 #endif
919         ifp->if_mtu = ETHERMTU;
920         ifp->if_hwassist = BCE_IF_HWASSIST;
921         ifp->if_capabilities = BCE_IF_CAPABILITIES;
922         ifp->if_capenable = ifp->if_capabilities;
923         ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD);
924         ifq_set_ready(&ifp->if_snd);
925
926         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
927                 ifp->if_baudrate = IF_Gbps(2.5);
928         else
929                 ifp->if_baudrate = IF_Gbps(1);
930
931         /* Assume a standard 1500 byte MTU size for mbuf allocations. */
932         sc->mbuf_alloc_size  = MCLBYTES;
933
934         /* Look for our PHY. */
935         rc = mii_phy_probe(dev, &sc->bce_miibus,
936                            bce_ifmedia_upd, bce_ifmedia_sts);
937         if (rc != 0) {
938                 device_printf(dev, "PHY probe failed!\n");
939                 goto fail;
940         }
941
942         /* Attach to the Ethernet interface list. */
943         ether_ifattach(ifp, sc->eaddr, NULL);
944
945         callout_init(&sc->bce_tick_callout);
946         callout_init(&sc->bce_pulse_callout);
947
948         /* Hookup IRQ last. */
949         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, bce_intr, sc,
950                             &sc->bce_intrhand, ifp->if_serializer);
951         if (rc != 0) {
952                 device_printf(dev, "Failed to setup IRQ!\n");
953                 ether_ifdetach(ifp);
954                 goto fail;
955         }
956
957         ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bce_res_irq));
958         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
959
960         /* Print some important debugging info. */
961         DBRUN(BCE_INFO, bce_dump_driver_state(sc));
962
963         /* Add the supported sysctls to the kernel. */
964         bce_add_sysctls(sc);
965
966         /*
967          * The chip reset earlier notified the bootcode that
968          * a driver is present.  We now need to start our pulse
969          * routine so that the bootcode is reminded that we're
970          * still running.
971          */
972         bce_pulse(sc);
973
974         /* Get the firmware running so IPMI still works */
975         bce_mgmt_init(sc);
976
977         bce_print_adapter_info(sc);
978
979         return 0;
980 fail:
981         bce_detach(dev);
982         return(rc);
983 }
984
985
986 /****************************************************************************/
987 /* Device detach function.                                                  */
988 /*                                                                          */
989 /* Stops the controller, resets the controller, and releases resources.     */
990 /*                                                                          */
991 /* Returns:                                                                 */
992 /*   0 on success, positive value on failure.                               */
993 /****************************************************************************/
994 static int
995 bce_detach(device_t dev)
996 {
997         struct bce_softc *sc = device_get_softc(dev);
998
999         if (device_is_attached(dev)) {
1000                 struct ifnet *ifp = &sc->arpcom.ac_if;
1001                 uint32_t msg;
1002
1003                 /* Stop and reset the controller. */
1004                 lwkt_serialize_enter(ifp->if_serializer);
1005                 callout_stop(&sc->bce_pulse_callout);
1006                 bce_stop(sc);
1007                 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1008                         msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1009                 else
1010                         msg = BCE_DRV_MSG_CODE_UNLOAD;
1011                 bce_reset(sc, msg);
1012                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
1013                 lwkt_serialize_exit(ifp->if_serializer);
1014
1015                 ether_ifdetach(ifp);
1016         }
1017
1018         /* If we have a child device on the MII bus remove it too. */
1019         if (sc->bce_miibus)
1020                 device_delete_child(dev, sc->bce_miibus);
1021         bus_generic_detach(dev);
1022
1023         if (sc->bce_res_irq != NULL) {
1024                 bus_release_resource(dev, SYS_RES_IRQ,
1025                         sc->bce_flags & BCE_USING_MSI_FLAG ? 1 : 0,
1026                         sc->bce_res_irq);
1027         }
1028
1029 #ifdef notyet
1030         if (sc->bce_flags & BCE_USING_MSI_FLAG)
1031                 pci_release_msi(dev);
1032 #endif
1033
1034         if (sc->bce_res_mem != NULL) {
1035                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
1036                                      sc->bce_res_mem);
1037         }
1038
1039         bce_dma_free(sc);
1040
1041         if (sc->bce_sysctl_tree != NULL)
1042                 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1043
1044         return 0;
1045 }
1046
1047
1048 /****************************************************************************/
1049 /* Device shutdown function.                                                */
1050 /*                                                                          */
1051 /* Stops and resets the controller.                                         */
1052 /*                                                                          */
1053 /* Returns:                                                                 */
1054 /*   Nothing                                                                */
1055 /****************************************************************************/
1056 static void
1057 bce_shutdown(device_t dev)
1058 {
1059         struct bce_softc *sc = device_get_softc(dev);
1060         struct ifnet *ifp = &sc->arpcom.ac_if;
1061         uint32_t msg;
1062
1063         lwkt_serialize_enter(ifp->if_serializer);
1064         bce_stop(sc);
1065         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1066                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1067         else
1068                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1069         bce_reset(sc, msg);
1070         lwkt_serialize_exit(ifp->if_serializer);
1071 }
1072
1073
1074 /****************************************************************************/
1075 /* Indirect register read.                                                  */
1076 /*                                                                          */
1077 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1078 /* configuration space.  Using this mechanism avoids issues with posted     */
1079 /* reads but is much slower than memory-mapped I/O.                         */
1080 /*                                                                          */
1081 /* Returns:                                                                 */
1082 /*   The value of the register.                                             */
1083 /****************************************************************************/
1084 static uint32_t
1085 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1086 {
1087         device_t dev = sc->bce_dev;
1088
1089         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1090 #ifdef BCE_DEBUG
1091         {
1092                 uint32_t val;
1093                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1094                 DBPRINT(sc, BCE_EXCESSIVE,
1095                         "%s(); offset = 0x%08X, val = 0x%08X\n",
1096                         __func__, offset, val);
1097                 return val;
1098         }
1099 #else
1100         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1101 #endif
1102 }
1103
1104
1105 /****************************************************************************/
1106 /* Indirect register write.                                                 */
1107 /*                                                                          */
1108 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1109 /* configuration space.  Using this mechanism avoids issues with posted     */
1110 /* writes but is muchh slower than memory-mapped I/O.                       */
1111 /*                                                                          */
1112 /* Returns:                                                                 */
1113 /*   Nothing.                                                               */
1114 /****************************************************************************/
1115 static void
1116 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1117 {
1118         device_t dev = sc->bce_dev;
1119
1120         DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1121                 __func__, offset, val);
1122
1123         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1124         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1125 }
1126
1127
1128 /****************************************************************************/
1129 /* Shared memory write.                                                     */
1130 /*                                                                          */
1131 /* Writes NetXtreme II shared memory region.                                */
1132 /*                                                                          */
1133 /* Returns:                                                                 */
1134 /*   Nothing.                                                               */
1135 /****************************************************************************/
1136 static void
1137 bce_shmem_wr(struct bce_softc *sc, uint32_t offset, uint32_t val)
1138 {
1139         bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1140 }
1141
1142
1143 /****************************************************************************/
1144 /* Shared memory read.                                                      */
1145 /*                                                                          */
1146 /* Reads NetXtreme II shared memory region.                                 */
1147 /*                                                                          */
1148 /* Returns:                                                                 */
1149 /*   The 32 bit value read.                                                 */
1150 /****************************************************************************/
1151 static u32
1152 bce_shmem_rd(struct bce_softc *sc, uint32_t offset)
1153 {
1154         return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1155 }
1156
1157
1158 /****************************************************************************/
1159 /* Context memory write.                                                    */
1160 /*                                                                          */
1161 /* The NetXtreme II controller uses context memory to track connection      */
1162 /* information for L2 and higher network protocols.                         */
1163 /*                                                                          */
1164 /* Returns:                                                                 */
1165 /*   Nothing.                                                               */
1166 /****************************************************************************/
1167 static void
1168 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1169     uint32_t ctx_val)
1170 {
1171         uint32_t idx, offset = ctx_offset + cid_addr;
1172         uint32_t val, retry_cnt = 5;
1173
1174         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1175             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1176                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1177                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1178
1179                 for (idx = 0; idx < retry_cnt; idx++) {
1180                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1181                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1182                                 break;
1183                         DELAY(5);
1184                 }
1185
1186                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1187                         device_printf(sc->bce_dev,
1188                             "Unable to write CTX memory: "
1189                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1190                             cid_addr, ctx_offset);
1191                 }
1192         } else {
1193                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1194                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1195         }
1196 }
1197
1198
1199 /****************************************************************************/
1200 /* PHY register read.                                                       */
1201 /*                                                                          */
1202 /* Implements register reads on the MII bus.                                */
1203 /*                                                                          */
1204 /* Returns:                                                                 */
1205 /*   The value of the register.                                             */
1206 /****************************************************************************/
1207 static int
1208 bce_miibus_read_reg(device_t dev, int phy, int reg)
1209 {
1210         struct bce_softc *sc = device_get_softc(dev);
1211         uint32_t val;
1212         int i;
1213
1214         /* Make sure we are accessing the correct PHY address. */
1215         if (phy != sc->bce_phy_addr) {
1216                 DBPRINT(sc, BCE_VERBOSE,
1217                         "Invalid PHY address %d for PHY read!\n", phy);
1218                 return 0;
1219         }
1220
1221         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1222                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1223                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1224
1225                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1226                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1227
1228                 DELAY(40);
1229         }
1230
1231         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1232               BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1233               BCE_EMAC_MDIO_COMM_START_BUSY;
1234         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1235
1236         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1237                 DELAY(10);
1238
1239                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1240                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1241                         DELAY(5);
1242
1243                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1244                         val &= BCE_EMAC_MDIO_COMM_DATA;
1245                         break;
1246                 }
1247         }
1248
1249         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1250                 if_printf(&sc->arpcom.ac_if,
1251                           "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1252                           phy, reg);
1253                 val = 0x0;
1254         } else {
1255                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1256         }
1257
1258         DBPRINT(sc, BCE_EXCESSIVE,
1259                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1260                 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1261
1262         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1263                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1264                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1265
1266                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1267                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1268
1269                 DELAY(40);
1270         }
1271         return (val & 0xffff);
1272 }
1273
1274
1275 /****************************************************************************/
1276 /* PHY register write.                                                      */
1277 /*                                                                          */
1278 /* Implements register writes on the MII bus.                               */
1279 /*                                                                          */
1280 /* Returns:                                                                 */
1281 /*   The value of the register.                                             */
1282 /****************************************************************************/
1283 static int
1284 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1285 {
1286         struct bce_softc *sc = device_get_softc(dev);
1287         uint32_t val1;
1288         int i;
1289
1290         /* Make sure we are accessing the correct PHY address. */
1291         if (phy != sc->bce_phy_addr) {
1292                 DBPRINT(sc, BCE_WARN,
1293                         "Invalid PHY address %d for PHY write!\n", phy);
1294                 return(0);
1295         }
1296
1297         DBPRINT(sc, BCE_EXCESSIVE,
1298                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1299                 __func__, phy, (uint16_t)(reg & 0xffff),
1300                 (uint16_t)(val & 0xffff));
1301
1302         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1303                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1304                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1305
1306                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1307                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1308
1309                 DELAY(40);
1310         }
1311
1312         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1313                 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1314                 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1315         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1316
1317         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1318                 DELAY(10);
1319
1320                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1321                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1322                         DELAY(5);
1323                         break;
1324                 }
1325         }
1326
1327         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1328                 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1329
1330         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1331                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1332                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1333
1334                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1335                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1336
1337                 DELAY(40);
1338         }
1339         return 0;
1340 }
1341
1342
1343 /****************************************************************************/
1344 /* MII bus status change.                                                   */
1345 /*                                                                          */
1346 /* Called by the MII bus driver when the PHY establishes link to set the    */
1347 /* MAC interface registers.                                                 */
1348 /*                                                                          */
1349 /* Returns:                                                                 */
1350 /*   Nothing.                                                               */
1351 /****************************************************************************/
1352 static void
1353 bce_miibus_statchg(device_t dev)
1354 {
1355         struct bce_softc *sc = device_get_softc(dev);
1356         struct mii_data *mii = device_get_softc(sc->bce_miibus);
1357
1358         DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1359                 mii->mii_media_active);
1360
1361 #ifdef BCE_DEBUG
1362         /* Decode the interface media flags. */
1363         if_printf(&sc->arpcom.ac_if, "Media: ( ");
1364         switch(IFM_TYPE(mii->mii_media_active)) {
1365         case IFM_ETHER:
1366                 kprintf("Ethernet )");
1367                 break;
1368         default:
1369                 kprintf("Unknown )");
1370                 break;
1371         }
1372
1373         kprintf(" Media Options: ( ");
1374         switch(IFM_SUBTYPE(mii->mii_media_active)) {
1375         case IFM_AUTO:
1376                 kprintf("Autoselect )");
1377                 break;
1378         case IFM_MANUAL:
1379                 kprintf("Manual )");
1380                 break;
1381         case IFM_NONE:
1382                 kprintf("None )");
1383                 break;
1384         case IFM_10_T:
1385                 kprintf("10Base-T )");
1386                 break;
1387         case IFM_100_TX:
1388                 kprintf("100Base-TX )");
1389                 break;
1390         case IFM_1000_SX:
1391                 kprintf("1000Base-SX )");
1392                 break;
1393         case IFM_1000_T:
1394                 kprintf("1000Base-T )");
1395                 break;
1396         default:
1397                 kprintf("Other )");
1398                 break;
1399         }
1400
1401         kprintf(" Global Options: (");
1402         if (mii->mii_media_active & IFM_FDX)
1403                 kprintf(" FullDuplex");
1404         if (mii->mii_media_active & IFM_HDX)
1405                 kprintf(" HalfDuplex");
1406         if (mii->mii_media_active & IFM_LOOP)
1407                 kprintf(" Loopback");
1408         if (mii->mii_media_active & IFM_FLAG0)
1409                 kprintf(" Flag0");
1410         if (mii->mii_media_active & IFM_FLAG1)
1411                 kprintf(" Flag1");
1412         if (mii->mii_media_active & IFM_FLAG2)
1413                 kprintf(" Flag2");
1414         kprintf(" )\n");
1415 #endif
1416
1417         BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1418
1419         /*
1420          * Set MII or GMII interface based on the speed negotiated
1421          * by the PHY.
1422          */
1423         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 
1424             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1425                 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1426                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1427         } else {
1428                 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1429                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1430         }
1431
1432         /*
1433          * Set half or full duplex based on the duplicity negotiated
1434          * by the PHY.
1435          */
1436         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1437                 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1438                 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1439         } else {
1440                 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1441                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1442         }
1443 }
1444
1445
1446 /****************************************************************************/
1447 /* Acquire NVRAM lock.                                                      */
1448 /*                                                                          */
1449 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
1450 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1451 /* for use by the driver.                                                   */
1452 /*                                                                          */
1453 /* Returns:                                                                 */
1454 /*   0 on success, positive value on failure.                               */
1455 /****************************************************************************/
1456 static int
1457 bce_acquire_nvram_lock(struct bce_softc *sc)
1458 {
1459         uint32_t val;
1460         int j;
1461
1462         DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1463
1464         /* Request access to the flash interface. */
1465         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1466         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1467                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1468                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1469                         break;
1470
1471                 DELAY(5);
1472         }
1473
1474         if (j >= NVRAM_TIMEOUT_COUNT) {
1475                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1476                 return EBUSY;
1477         }
1478         return 0;
1479 }
1480
1481
1482 /****************************************************************************/
1483 /* Release NVRAM lock.                                                      */
1484 /*                                                                          */
1485 /* When the caller is finished accessing NVRAM the lock must be released.   */
1486 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1487 /* for use by the driver.                                                   */
1488 /*                                                                          */
1489 /* Returns:                                                                 */
1490 /*   0 on success, positive value on failure.                               */
1491 /****************************************************************************/
1492 static int
1493 bce_release_nvram_lock(struct bce_softc *sc)
1494 {
1495         int j;
1496         uint32_t val;
1497
1498         DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1499
1500         /*
1501          * Relinquish nvram interface.
1502          */
1503         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1504
1505         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1506                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1507                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1508                         break;
1509
1510                 DELAY(5);
1511         }
1512
1513         if (j >= NVRAM_TIMEOUT_COUNT) {
1514                 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1515                 return EBUSY;
1516         }
1517         return 0;
1518 }
1519
1520
1521 /****************************************************************************/
1522 /* Enable NVRAM access.                                                     */
1523 /*                                                                          */
1524 /* Before accessing NVRAM for read or write operations the caller must      */
1525 /* enabled NVRAM access.                                                    */
1526 /*                                                                          */
1527 /* Returns:                                                                 */
1528 /*   Nothing.                                                               */
1529 /****************************************************************************/
1530 static void
1531 bce_enable_nvram_access(struct bce_softc *sc)
1532 {
1533         uint32_t val;
1534
1535         DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1536
1537         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1538         /* Enable both bits, even on read. */
1539         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1540                val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1541 }
1542
1543
1544 /****************************************************************************/
1545 /* Disable NVRAM access.                                                    */
1546 /*                                                                          */
1547 /* When the caller is finished accessing NVRAM access must be disabled.     */
1548 /*                                                                          */
1549 /* Returns:                                                                 */
1550 /*   Nothing.                                                               */
1551 /****************************************************************************/
1552 static void
1553 bce_disable_nvram_access(struct bce_softc *sc)
1554 {
1555         uint32_t val;
1556
1557         DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1558
1559         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1560
1561         /* Disable both bits, even after read. */
1562         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1563                val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1564 }
1565
1566
1567 /****************************************************************************/
1568 /* Read a dword (32 bits) from NVRAM.                                       */
1569 /*                                                                          */
1570 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
1571 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
1572 /*                                                                          */
1573 /* Returns:                                                                 */
1574 /*   0 on success and the 32 bit value read, positive value on failure.     */
1575 /****************************************************************************/
1576 static int
1577 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1578                      uint32_t cmd_flags)
1579 {
1580         uint32_t cmd;
1581         int i, rc = 0;
1582
1583         /* Build the command word. */
1584         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1585
1586         /* Calculate the offset for buffered flash. */
1587         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1588                 offset = ((offset / sc->bce_flash_info->page_size) <<
1589                           sc->bce_flash_info->page_bits) +
1590                          (offset % sc->bce_flash_info->page_size);
1591         }
1592
1593         /*
1594          * Clear the DONE bit separately, set the address to read,
1595          * and issue the read.
1596          */
1597         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1598         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1599         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1600
1601         /* Wait for completion. */
1602         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1603                 uint32_t val;
1604
1605                 DELAY(5);
1606
1607                 val = REG_RD(sc, BCE_NVM_COMMAND);
1608                 if (val & BCE_NVM_COMMAND_DONE) {
1609                         val = REG_RD(sc, BCE_NVM_READ);
1610
1611                         val = be32toh(val);
1612                         memcpy(ret_val, &val, 4);
1613                         break;
1614                 }
1615         }
1616
1617         /* Check for errors. */
1618         if (i >= NVRAM_TIMEOUT_COUNT) {
1619                 if_printf(&sc->arpcom.ac_if,
1620                           "Timeout error reading NVRAM at offset 0x%08X!\n",
1621                           offset);
1622                 rc = EBUSY;
1623         }
1624         return rc;
1625 }
1626
1627
1628 /****************************************************************************/
1629 /* Initialize NVRAM access.                                                 */
1630 /*                                                                          */
1631 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
1632 /* access that device.                                                      */
1633 /*                                                                          */
1634 /* Returns:                                                                 */
1635 /*   0 on success, positive value on failure.                               */
1636 /****************************************************************************/
1637 static int
1638 bce_init_nvram(struct bce_softc *sc)
1639 {
1640         uint32_t val;
1641         int j, entry_count, rc = 0;
1642         const struct flash_spec *flash;
1643
1644         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1645
1646         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1647             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1648                 sc->bce_flash_info = &flash_5709;
1649                 goto bce_init_nvram_get_flash_size;
1650         }
1651
1652         /* Determine the selected interface. */
1653         val = REG_RD(sc, BCE_NVM_CFG1);
1654
1655         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1656
1657         /*
1658          * Flash reconfiguration is required to support additional
1659          * NVRAM devices not directly supported in hardware.
1660          * Check if the flash interface was reconfigured
1661          * by the bootcode.
1662          */
1663
1664         if (val & 0x40000000) {
1665                 /* Flash interface reconfigured by bootcode. */
1666
1667                 DBPRINT(sc, BCE_INFO_LOAD, 
1668                         "%s(): Flash WAS reconfigured.\n", __func__);
1669
1670                 for (j = 0, flash = flash_table; j < entry_count;
1671                      j++, flash++) {
1672                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
1673                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1674                                 sc->bce_flash_info = flash;
1675                                 break;
1676                         }
1677                 }
1678         } else {
1679                 /* Flash interface not yet reconfigured. */
1680                 uint32_t mask;
1681
1682                 DBPRINT(sc, BCE_INFO_LOAD, 
1683                         "%s(): Flash was NOT reconfigured.\n", __func__);
1684
1685                 if (val & (1 << 23))
1686                         mask = FLASH_BACKUP_STRAP_MASK;
1687                 else
1688                         mask = FLASH_STRAP_MASK;
1689
1690                 /* Look for the matching NVRAM device configuration data. */
1691                 for (j = 0, flash = flash_table; j < entry_count;
1692                      j++, flash++) {
1693                         /* Check if the device matches any of the known devices. */
1694                         if ((val & mask) == (flash->strapping & mask)) {
1695                                 /* Found a device match. */
1696                                 sc->bce_flash_info = flash;
1697
1698                                 /* Request access to the flash interface. */
1699                                 rc = bce_acquire_nvram_lock(sc);
1700                                 if (rc != 0)
1701                                         return rc;
1702
1703                                 /* Reconfigure the flash interface. */
1704                                 bce_enable_nvram_access(sc);
1705                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1706                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1707                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1708                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1709                                 bce_disable_nvram_access(sc);
1710                                 bce_release_nvram_lock(sc);
1711                                 break;
1712                         }
1713                 }
1714         }
1715
1716         /* Check if a matching device was found. */
1717         if (j == entry_count) {
1718                 sc->bce_flash_info = NULL;
1719                 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1720                 rc = ENODEV;
1721         }
1722
1723 bce_init_nvram_get_flash_size:
1724         /* Write the flash config data to the shared memory interface. */
1725         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2) &
1726             BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1727         if (val)
1728                 sc->bce_flash_size = val;
1729         else
1730                 sc->bce_flash_size = sc->bce_flash_info->total_size;
1731
1732         DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1733                 __func__, sc->bce_flash_info->total_size);
1734
1735         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1736
1737         return rc;
1738 }
1739
1740
1741 /****************************************************************************/
1742 /* Read an arbitrary range of data from NVRAM.                              */
1743 /*                                                                          */
1744 /* Prepares the NVRAM interface for access and reads the requested data     */
1745 /* into the supplied buffer.                                                */
1746 /*                                                                          */
1747 /* Returns:                                                                 */
1748 /*   0 on success and the data read, positive value on failure.             */
1749 /****************************************************************************/
1750 static int
1751 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1752                int buf_size)
1753 {
1754         uint32_t cmd_flags, offset32, len32, extra;
1755         int rc = 0;
1756
1757         if (buf_size == 0)
1758                 return 0;
1759
1760         /* Request access to the flash interface. */
1761         rc = bce_acquire_nvram_lock(sc);
1762         if (rc != 0)
1763                 return rc;
1764
1765         /* Enable access to flash interface */
1766         bce_enable_nvram_access(sc);
1767
1768         len32 = buf_size;
1769         offset32 = offset;
1770         extra = 0;
1771
1772         cmd_flags = 0;
1773
1774         /* XXX should we release nvram lock if read_dword() fails? */
1775         if (offset32 & 3) {
1776                 uint8_t buf[4];
1777                 uint32_t pre_len;
1778
1779                 offset32 &= ~3;
1780                 pre_len = 4 - (offset & 3);
1781
1782                 if (pre_len >= len32) {
1783                         pre_len = len32;
1784                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1785                 } else {
1786                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1787                 }
1788
1789                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1790                 if (rc)
1791                         return rc;
1792
1793                 memcpy(ret_buf, buf + (offset & 3), pre_len);
1794
1795                 offset32 += 4;
1796                 ret_buf += pre_len;
1797                 len32 -= pre_len;
1798         }
1799
1800         if (len32 & 3) {
1801                 extra = 4 - (len32 & 3);
1802                 len32 = (len32 + 4) & ~3;
1803         }
1804
1805         if (len32 == 4) {
1806                 uint8_t buf[4];
1807
1808                 if (cmd_flags)
1809                         cmd_flags = BCE_NVM_COMMAND_LAST;
1810                 else
1811                         cmd_flags = BCE_NVM_COMMAND_FIRST |
1812                                     BCE_NVM_COMMAND_LAST;
1813
1814                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1815
1816                 memcpy(ret_buf, buf, 4 - extra);
1817         } else if (len32 > 0) {
1818                 uint8_t buf[4];
1819
1820                 /* Read the first word. */
1821                 if (cmd_flags)
1822                         cmd_flags = 0;
1823                 else
1824                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1825
1826                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1827
1828                 /* Advance to the next dword. */
1829                 offset32 += 4;
1830                 ret_buf += 4;
1831                 len32 -= 4;
1832
1833                 while (len32 > 4 && rc == 0) {
1834                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1835
1836                         /* Advance to the next dword. */
1837                         offset32 += 4;
1838                         ret_buf += 4;
1839                         len32 -= 4;
1840                 }
1841
1842                 if (rc)
1843                         goto bce_nvram_read_locked_exit;
1844
1845                 cmd_flags = BCE_NVM_COMMAND_LAST;
1846                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1847
1848                 memcpy(ret_buf, buf, 4 - extra);
1849         }
1850
1851 bce_nvram_read_locked_exit:
1852         /* Disable access to flash interface and release the lock. */
1853         bce_disable_nvram_access(sc);
1854         bce_release_nvram_lock(sc);
1855
1856         return rc;
1857 }
1858
1859
1860 /****************************************************************************/
1861 /* Verifies that NVRAM is accessible and contains valid data.               */
1862 /*                                                                          */
1863 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
1864 /* correct.                                                                 */
1865 /*                                                                          */
1866 /* Returns:                                                                 */
1867 /*   0 on success, positive value on failure.                               */
1868 /****************************************************************************/
1869 static int
1870 bce_nvram_test(struct bce_softc *sc)
1871 {
1872         uint32_t buf[BCE_NVRAM_SIZE / 4];
1873         uint32_t magic, csum;
1874         uint8_t *data = (uint8_t *)buf;
1875         int rc = 0;
1876
1877         /*
1878          * Check that the device NVRAM is valid by reading
1879          * the magic value at offset 0.
1880          */
1881         rc = bce_nvram_read(sc, 0, data, 4);
1882         if (rc != 0)
1883                 return rc;
1884
1885         magic = be32toh(buf[0]);
1886         if (magic != BCE_NVRAM_MAGIC) {
1887                 if_printf(&sc->arpcom.ac_if,
1888                           "Invalid NVRAM magic value! Expected: 0x%08X, "
1889                           "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1890                 return ENODEV;
1891         }
1892
1893         /*
1894          * Verify that the device NVRAM includes valid
1895          * configuration data.
1896          */
1897         rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1898         if (rc != 0)
1899                 return rc;
1900
1901         csum = ether_crc32_le(data, 0x100);
1902         if (csum != BCE_CRC32_RESIDUAL) {
1903                 if_printf(&sc->arpcom.ac_if,
1904                           "Invalid Manufacturing Information NVRAM CRC! "
1905                           "Expected: 0x%08X, Found: 0x%08X\n",
1906                           BCE_CRC32_RESIDUAL, csum);
1907                 return ENODEV;
1908         }
1909
1910         csum = ether_crc32_le(data + 0x100, 0x100);
1911         if (csum != BCE_CRC32_RESIDUAL) {
1912                 if_printf(&sc->arpcom.ac_if,
1913                           "Invalid Feature Configuration Information "
1914                           "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1915                           BCE_CRC32_RESIDUAL, csum);
1916                 rc = ENODEV;
1917         }
1918         return rc;
1919 }
1920
1921
1922 /****************************************************************************/
1923 /* Identifies the current media type of the controller and sets the PHY     */
1924 /* address.                                                                 */
1925 /*                                                                          */
1926 /* Returns:                                                                 */
1927 /*   Nothing.                                                               */
1928 /****************************************************************************/
1929 static void
1930 bce_get_media(struct bce_softc *sc)
1931 {
1932         uint32_t val;
1933
1934         sc->bce_phy_addr = 1;
1935
1936         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1937             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1938                 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1939                 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1940                 uint32_t strap;
1941
1942                 /*
1943                  * The BCM5709S is software configurable
1944                  * for Copper or SerDes operation.
1945                  */
1946                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1947                         return;
1948                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1949                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1950                         return;
1951                 }
1952
1953                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1954                         strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1955                 } else {
1956                         strap =
1957                         (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1958                 }
1959
1960                 if (pci_get_function(sc->bce_dev) == 0) {
1961                         switch (strap) {
1962                         case 0x4:
1963                         case 0x5:
1964                         case 0x6:
1965                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1966                                 break;
1967                         }
1968                 } else {
1969                         switch (strap) {
1970                         case 0x1:
1971                         case 0x2:
1972                         case 0x4:
1973                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1974                                 break;
1975                         }
1976                 }
1977         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
1978                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1979         }
1980
1981         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
1982                 sc->bce_flags |= BCE_NO_WOL_FLAG;
1983                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
1984                         sc->bce_phy_addr = 2;
1985                         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
1986                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
1987                                 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
1988                 }
1989         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
1990             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
1991                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
1992         }
1993 }
1994
1995
1996 /****************************************************************************/
1997 /* Free any DMA memory owned by the driver.                                 */
1998 /*                                                                          */
1999 /* Scans through each data structre that requires DMA memory and frees      */
2000 /* the memory if allocated.                                                 */
2001 /*                                                                          */
2002 /* Returns:                                                                 */
2003 /*   Nothing.                                                               */
2004 /****************************************************************************/
2005 static void
2006 bce_dma_free(struct bce_softc *sc)
2007 {
2008         int i;
2009
2010         /* Destroy the status block. */
2011         if (sc->status_tag != NULL) {
2012                 if (sc->status_block != NULL) {
2013                         bus_dmamap_unload(sc->status_tag, sc->status_map);
2014                         bus_dmamem_free(sc->status_tag, sc->status_block,
2015                                         sc->status_map);
2016                 }
2017                 bus_dma_tag_destroy(sc->status_tag);
2018         }
2019
2020
2021         /* Destroy the statistics block. */
2022         if (sc->stats_tag != NULL) {
2023                 if (sc->stats_block != NULL) {
2024                         bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2025                         bus_dmamem_free(sc->stats_tag, sc->stats_block,
2026                                         sc->stats_map);
2027                 }
2028                 bus_dma_tag_destroy(sc->stats_tag);
2029         }
2030
2031         /* Destroy the CTX DMA stuffs. */
2032         if (sc->ctx_tag != NULL) {
2033                 for (i = 0; i < sc->ctx_pages; i++) {
2034                         if (sc->ctx_block[i] != NULL) {
2035                                 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
2036                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2037                                                 sc->ctx_map[i]);
2038                         }
2039                 }
2040                 bus_dma_tag_destroy(sc->ctx_tag);
2041         }
2042
2043         /* Destroy the TX buffer descriptor DMA stuffs. */
2044         if (sc->tx_bd_chain_tag != NULL) {
2045                 for (i = 0; i < TX_PAGES; i++) {
2046                         if (sc->tx_bd_chain[i] != NULL) {
2047                                 bus_dmamap_unload(sc->tx_bd_chain_tag,
2048                                                   sc->tx_bd_chain_map[i]);
2049                                 bus_dmamem_free(sc->tx_bd_chain_tag,
2050                                                 sc->tx_bd_chain[i],
2051                                                 sc->tx_bd_chain_map[i]);
2052                         }
2053                 }
2054                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2055         }
2056
2057         /* Destroy the RX buffer descriptor DMA stuffs. */
2058         if (sc->rx_bd_chain_tag != NULL) {
2059                 for (i = 0; i < RX_PAGES; i++) {
2060                         if (sc->rx_bd_chain[i] != NULL) {
2061                                 bus_dmamap_unload(sc->rx_bd_chain_tag,
2062                                                   sc->rx_bd_chain_map[i]);
2063                                 bus_dmamem_free(sc->rx_bd_chain_tag,
2064                                                 sc->rx_bd_chain[i],
2065                                                 sc->rx_bd_chain_map[i]);
2066                         }
2067                 }
2068                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2069         }
2070
2071         /* Destroy the TX mbuf DMA stuffs. */
2072         if (sc->tx_mbuf_tag != NULL) {
2073                 for (i = 0; i < TOTAL_TX_BD; i++) {
2074                         /* Must have been unloaded in bce_stop() */
2075                         KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2076                         bus_dmamap_destroy(sc->tx_mbuf_tag,
2077                                            sc->tx_mbuf_map[i]);
2078                 }
2079                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2080         }
2081
2082         /* Destroy the RX mbuf DMA stuffs. */
2083         if (sc->rx_mbuf_tag != NULL) {
2084                 for (i = 0; i < TOTAL_RX_BD; i++) {
2085                         /* Must have been unloaded in bce_stop() */
2086                         KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2087                         bus_dmamap_destroy(sc->rx_mbuf_tag,
2088                                            sc->rx_mbuf_map[i]);
2089                 }
2090                 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
2091                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2092         }
2093
2094         /* Destroy the parent tag */
2095         if (sc->parent_tag != NULL)
2096                 bus_dma_tag_destroy(sc->parent_tag);
2097 }
2098
2099
2100 /****************************************************************************/
2101 /* Get DMA memory from the OS.                                              */
2102 /*                                                                          */
2103 /* Validates that the OS has provided DMA buffers in response to a          */
2104 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
2105 /* When the callback is used the OS will return 0 for the mapping function  */
2106 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
2107 /* failures back to the caller.                                             */
2108 /*                                                                          */
2109 /* Returns:                                                                 */
2110 /*   Nothing.                                                               */
2111 /****************************************************************************/
2112 static void
2113 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2114 {
2115         bus_addr_t *busaddr = arg;
2116
2117         /*
2118          * Simulate a mapping failure.
2119          * XXX not correct.
2120          */
2121         DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2122                 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2123                         __FILE__, __LINE__);
2124                 error = ENOMEM);
2125                 
2126         /* Check for an error and signal the caller that an error occurred. */
2127         if (error)
2128                 return;
2129
2130         KASSERT(nseg == 1, ("only one segment is allowed\n"));
2131         *busaddr = segs->ds_addr;
2132 }
2133
2134
2135 /****************************************************************************/
2136 /* Allocate any DMA memory needed by the driver.                            */
2137 /*                                                                          */
2138 /* Allocates DMA memory needed for the various global structures needed by  */
2139 /* hardware.                                                                */
2140 /*                                                                          */
2141 /* Memory alignment requirements:                                           */
2142 /* -----------------+----------+----------+----------+----------+           */
2143 /*  Data Structure  |   5706   |   5708   |   5709   |   5716   |           */
2144 /* -----------------+----------+----------+----------+----------+           */
2145 /* Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2146 /* Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2147 /* RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |           */
2148 /* PG Buffers       |   none   |   none   |   none   |   none   |           */
2149 /* TX Buffers       |   none   |   none   |   none   |   none   |           */
2150 /* Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |           */
2151 /* Context Pages(1) |   N/A    |   N/A    |   4KiB   |   4KiB   |           */
2152 /* -----------------+----------+----------+----------+----------+           */
2153 /*                                                                          */
2154 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
2155 /*                                                                          */
2156 /* Returns:                                                                 */
2157 /*   0 for success, positive value for failure.                             */
2158 /****************************************************************************/
2159 static int
2160 bce_dma_alloc(struct bce_softc *sc)
2161 {
2162         struct ifnet *ifp = &sc->arpcom.ac_if;
2163         int i, j, rc = 0;
2164         bus_addr_t busaddr, max_busaddr;
2165         bus_size_t status_align, stats_align;
2166
2167         /* 
2168          * The embedded PCIe to PCI-X bridge (EPB) 
2169          * in the 5708 cannot address memory above 
2170          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 
2171          */
2172         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2173                 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2174         else
2175                 max_busaddr = BUS_SPACE_MAXADDR;
2176
2177         /*
2178          * BCM5709 and BCM5716 uses host memory as cache for context memory.
2179          */
2180         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2181             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2182                 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2183                 if (sc->ctx_pages == 0)
2184                         sc->ctx_pages = 1;
2185                 if (sc->ctx_pages > BCE_CTX_PAGES) {
2186                         device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2187                             sc->ctx_pages);
2188                         return ENOMEM;
2189                 }
2190                 status_align = 16;
2191                 stats_align = 16;
2192         } else {
2193                 status_align = 8;
2194                 stats_align = 8;
2195         }
2196
2197         /*
2198          * Allocate the parent bus DMA tag appropriate for PCI.
2199          */
2200         rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2201                                 max_busaddr, BUS_SPACE_MAXADDR,
2202                                 NULL, NULL,
2203                                 BUS_SPACE_MAXSIZE_32BIT, 0,
2204                                 BUS_SPACE_MAXSIZE_32BIT,
2205                                 0, &sc->parent_tag);
2206         if (rc != 0) {
2207                 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2208                 return rc;
2209         }
2210
2211         /*
2212          * Allocate status block.
2213          */
2214         sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2215                                 status_align, BCE_STATUS_BLK_SZ,
2216                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2217                                 &sc->status_tag, &sc->status_map,
2218                                 &sc->status_block_paddr);
2219         if (sc->status_block == NULL) {
2220                 if_printf(ifp, "Could not allocate status block!\n");
2221                 return ENOMEM;
2222         }
2223
2224         /*
2225          * Allocate statistics block.
2226          */
2227         sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2228                                 stats_align, BCE_STATS_BLK_SZ,
2229                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2230                                 &sc->stats_tag, &sc->stats_map,
2231                                 &sc->stats_block_paddr);
2232         if (sc->stats_block == NULL) {
2233                 if_printf(ifp, "Could not allocate statistics block!\n");
2234                 return ENOMEM;
2235         }
2236
2237         /*
2238          * Allocate context block, if needed
2239          */
2240         if (sc->ctx_pages != 0) {
2241                 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2242                                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2243                                         NULL, NULL,
2244                                         BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2245                                         0, &sc->ctx_tag);
2246                 if (rc != 0) {
2247                         if_printf(ifp, "Could not allocate "
2248                                   "context block DMA tag!\n");
2249                         return rc;
2250                 }
2251
2252                 for (i = 0; i < sc->ctx_pages; i++) {
2253                         rc = bus_dmamem_alloc(sc->ctx_tag,
2254                                               (void **)&sc->ctx_block[i],
2255                                               BUS_DMA_WAITOK | BUS_DMA_ZERO |
2256                                               BUS_DMA_COHERENT,
2257                                               &sc->ctx_map[i]);
2258                         if (rc != 0) {
2259                                 if_printf(ifp, "Could not allocate %dth context "
2260                                           "DMA memory!\n", i);
2261                                 return rc;
2262                         }
2263
2264                         rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2265                                              sc->ctx_block[i], BCM_PAGE_SIZE,
2266                                              bce_dma_map_addr, &busaddr,
2267                                              BUS_DMA_WAITOK);
2268                         if (rc != 0) {
2269                                 if (rc == EINPROGRESS) {
2270                                         panic("%s coherent memory loading "
2271                                               "is still in progress!", ifp->if_xname);
2272                                 }
2273                                 if_printf(ifp, "Could not map %dth context "
2274                                           "DMA memory!\n", i);
2275                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2276                                                 sc->ctx_map[i]);
2277                                 sc->ctx_block[i] = NULL;
2278                                 return rc;
2279                         }
2280                         sc->ctx_paddr[i] = busaddr;
2281                 }
2282         }
2283
2284         /*
2285          * Create a DMA tag for the TX buffer descriptor chain,
2286          * allocate and clear the  memory, and fetch the
2287          * physical address of the block.
2288          */
2289         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2290                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2291                                 NULL, NULL,
2292                                 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2293                                 0, &sc->tx_bd_chain_tag);
2294         if (rc != 0) {
2295                 if_printf(ifp, "Could not allocate "
2296                           "TX descriptor chain DMA tag!\n");
2297                 return rc;
2298         }
2299
2300         for (i = 0; i < TX_PAGES; i++) {
2301                 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2302                                       (void **)&sc->tx_bd_chain[i],
2303                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2304                                       BUS_DMA_COHERENT,
2305                                       &sc->tx_bd_chain_map[i]);
2306                 if (rc != 0) {
2307                         if_printf(ifp, "Could not allocate %dth TX descriptor "
2308                                   "chain DMA memory!\n", i);
2309                         return rc;
2310                 }
2311
2312                 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2313                                      sc->tx_bd_chain_map[i],
2314                                      sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2315                                      bce_dma_map_addr, &busaddr,
2316                                      BUS_DMA_WAITOK);
2317                 if (rc != 0) {
2318                         if (rc == EINPROGRESS) {
2319                                 panic("%s coherent memory loading "
2320                                       "is still in progress!", ifp->if_xname);
2321                         }
2322                         if_printf(ifp, "Could not map %dth TX descriptor "
2323                                   "chain DMA memory!\n", i);
2324                         bus_dmamem_free(sc->tx_bd_chain_tag,
2325                                         sc->tx_bd_chain[i],
2326                                         sc->tx_bd_chain_map[i]);
2327                         sc->tx_bd_chain[i] = NULL;
2328                         return rc;
2329                 }
2330
2331                 sc->tx_bd_chain_paddr[i] = busaddr;
2332                 /* DRC - Fix for 64 bit systems. */
2333                 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 
2334                         i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2335         }
2336
2337         /* Create a DMA tag for TX mbufs. */
2338         rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2339                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2340                                 NULL, NULL,
2341                                 /* BCE_MAX_JUMBO_ETHER_MTU_VLAN */MCLBYTES,
2342                                 BCE_MAX_SEGMENTS, MCLBYTES,
2343                                 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2344                                 BUS_DMA_ONEBPAGE,
2345                                 &sc->tx_mbuf_tag);
2346         if (rc != 0) {
2347                 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2348                 return rc;
2349         }
2350
2351         /* Create DMA maps for the TX mbufs clusters. */
2352         for (i = 0; i < TOTAL_TX_BD; i++) {
2353                 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2354                                        BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2355                                        &sc->tx_mbuf_map[i]);
2356                 if (rc != 0) {
2357                         for (j = 0; j < i; ++j) {
2358                                 bus_dmamap_destroy(sc->tx_mbuf_tag,
2359                                                    sc->tx_mbuf_map[i]);
2360                         }
2361                         bus_dma_tag_destroy(sc->tx_mbuf_tag);
2362                         sc->tx_mbuf_tag = NULL;
2363
2364                         if_printf(ifp, "Unable to create "
2365                                   "%dth TX mbuf DMA map!\n", i);
2366                         return rc;
2367                 }
2368         }
2369
2370         /*
2371          * Create a DMA tag for the RX buffer descriptor chain,
2372          * allocate and clear the  memory, and fetch the physical
2373          * address of the blocks.
2374          */
2375         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2376                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2377                                 NULL, NULL,
2378                                 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2379                                 0, &sc->rx_bd_chain_tag);
2380         if (rc != 0) {
2381                 if_printf(ifp, "Could not allocate "
2382                           "RX descriptor chain DMA tag!\n");
2383                 return rc;
2384         }
2385
2386         for (i = 0; i < RX_PAGES; i++) {
2387                 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2388                                       (void **)&sc->rx_bd_chain[i],
2389                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2390                                       BUS_DMA_COHERENT,
2391                                       &sc->rx_bd_chain_map[i]);
2392                 if (rc != 0) {
2393                         if_printf(ifp, "Could not allocate %dth RX descriptor "
2394                                   "chain DMA memory!\n", i);
2395                         return rc;
2396                 }
2397
2398                 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2399                                      sc->rx_bd_chain_map[i],
2400                                      sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2401                                      bce_dma_map_addr, &busaddr,
2402                                      BUS_DMA_WAITOK);
2403                 if (rc != 0) {
2404                         if (rc == EINPROGRESS) {
2405                                 panic("%s coherent memory loading "
2406                                       "is still in progress!", ifp->if_xname);
2407                         }
2408                         if_printf(ifp, "Could not map %dth RX descriptor "
2409                                   "chain DMA memory!\n", i);
2410                         bus_dmamem_free(sc->rx_bd_chain_tag,
2411                                         sc->rx_bd_chain[i],
2412                                         sc->rx_bd_chain_map[i]);
2413                         sc->rx_bd_chain[i] = NULL;
2414                         return rc;
2415                 }
2416
2417                 sc->rx_bd_chain_paddr[i] = busaddr;
2418                 /* DRC - Fix for 64 bit systems. */
2419                 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2420                         i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2421         }
2422
2423         /* Create a DMA tag for RX mbufs. */
2424         rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2425                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2426                                 NULL, NULL,
2427                                 MCLBYTES, 1, MCLBYTES,
2428                                 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2429                                 BUS_DMA_WAITOK,
2430                                 &sc->rx_mbuf_tag);
2431         if (rc != 0) {
2432                 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2433                 return rc;
2434         }
2435
2436         /* Create tmp DMA map for RX mbuf clusters. */
2437         rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2438                                &sc->rx_mbuf_tmpmap);
2439         if (rc != 0) {
2440                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2441                 sc->rx_mbuf_tag = NULL;
2442
2443                 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2444                 return rc;
2445         }
2446
2447         /* Create DMA maps for the RX mbuf clusters. */
2448         for (i = 0; i < TOTAL_RX_BD; i++) {
2449                 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2450                                        &sc->rx_mbuf_map[i]);
2451                 if (rc != 0) {
2452                         for (j = 0; j < i; ++j) {
2453                                 bus_dmamap_destroy(sc->rx_mbuf_tag,
2454                                                    sc->rx_mbuf_map[j]);
2455                         }
2456                         bus_dma_tag_destroy(sc->rx_mbuf_tag);
2457                         sc->rx_mbuf_tag = NULL;
2458
2459                         if_printf(ifp, "Unable to create "
2460                                   "%dth RX mbuf DMA map!\n", i);
2461                         return rc;
2462                 }
2463         }
2464         return 0;
2465 }
2466
2467
2468 /****************************************************************************/
2469 /* Firmware synchronization.                                                */
2470 /*                                                                          */
2471 /* Before performing certain events such as a chip reset, synchronize with  */
2472 /* the firmware first.                                                      */
2473 /*                                                                          */
2474 /* Returns:                                                                 */
2475 /*   0 for success, positive value for failure.                             */
2476 /****************************************************************************/
2477 static int
2478 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2479 {
2480         int i, rc = 0;
2481         uint32_t val;
2482
2483         /* Don't waste any time if we've timed out before. */
2484         if (sc->bce_fw_timed_out)
2485                 return EBUSY;
2486
2487         /* Increment the message sequence number. */
2488         sc->bce_fw_wr_seq++;
2489         msg_data |= sc->bce_fw_wr_seq;
2490
2491         DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2492
2493         /* Send the message to the bootcode driver mailbox. */
2494         bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2495
2496         /* Wait for the bootcode to acknowledge the message. */
2497         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2498                 /* Check for a response in the bootcode firmware mailbox. */
2499                 val = bce_shmem_rd(sc, BCE_FW_MB);
2500                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2501                         break;
2502                 DELAY(1000);
2503         }
2504
2505         /* If we've timed out, tell the bootcode that we've stopped waiting. */
2506         if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2507             (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2508                 if_printf(&sc->arpcom.ac_if,
2509                           "Firmware synchronization timeout! "
2510                           "msg_data = 0x%08X\n", msg_data);
2511
2512                 msg_data &= ~BCE_DRV_MSG_CODE;
2513                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2514
2515                 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2516
2517                 sc->bce_fw_timed_out = 1;
2518                 rc = EBUSY;
2519         }
2520         return rc;
2521 }
2522
2523
2524 /****************************************************************************/
2525 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
2526 /*                                                                          */
2527 /* Returns:                                                                 */
2528 /*   Nothing.                                                               */
2529 /****************************************************************************/
2530 static void
2531 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2532                  uint32_t rv2p_code_len, uint32_t rv2p_proc)
2533 {
2534         int i;
2535         uint32_t val;
2536
2537         for (i = 0; i < rv2p_code_len; i += 8) {
2538                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2539                 rv2p_code++;
2540                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2541                 rv2p_code++;
2542
2543                 if (rv2p_proc == RV2P_PROC1) {
2544                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2545                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2546                 } else {
2547                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2548                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2549                 }
2550         }
2551
2552         /* Reset the processor, un-stall is done later. */
2553         if (rv2p_proc == RV2P_PROC1)
2554                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2555         else
2556                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2557 }
2558
2559
2560 /****************************************************************************/
2561 /* Load RISC processor firmware.                                            */
2562 /*                                                                          */
2563 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
2564 /* associated with a particular processor.                                  */
2565 /*                                                                          */
2566 /* Returns:                                                                 */
2567 /*   Nothing.                                                               */
2568 /****************************************************************************/
2569 static void
2570 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2571                 struct fw_info *fw)
2572 {
2573         uint32_t offset, val;
2574         int j;
2575
2576         /* Halt the CPU. */
2577         val = REG_RD_IND(sc, cpu_reg->mode);
2578         val |= cpu_reg->mode_value_halt;
2579         REG_WR_IND(sc, cpu_reg->mode, val);
2580         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2581
2582         /* Load the Text area. */
2583         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2584         if (fw->text) {
2585                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2586                         REG_WR_IND(sc, offset, fw->text[j]);
2587         }
2588
2589         /* Load the Data area. */
2590         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2591         if (fw->data) {
2592                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2593                         REG_WR_IND(sc, offset, fw->data[j]);
2594         }
2595
2596         /* Load the SBSS area. */
2597         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2598         if (fw->sbss) {
2599                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2600                         REG_WR_IND(sc, offset, fw->sbss[j]);
2601         }
2602
2603         /* Load the BSS area. */
2604         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2605         if (fw->bss) {
2606                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2607                         REG_WR_IND(sc, offset, fw->bss[j]);
2608         }
2609
2610         /* Load the Read-Only area. */
2611         offset = cpu_reg->spad_base +
2612                 (fw->rodata_addr - cpu_reg->mips_view_base);
2613         if (fw->rodata) {
2614                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2615                         REG_WR_IND(sc, offset, fw->rodata[j]);
2616         }
2617
2618         /* Clear the pre-fetch instruction. */
2619         REG_WR_IND(sc, cpu_reg->inst, 0);
2620         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2621
2622         /* Start the CPU. */
2623         val = REG_RD_IND(sc, cpu_reg->mode);
2624         val &= ~cpu_reg->mode_value_halt;
2625         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2626         REG_WR_IND(sc, cpu_reg->mode, val);
2627 }
2628
2629
2630 /****************************************************************************/
2631 /* Initialize the RX CPU.                                                   */
2632 /*                                                                          */
2633 /* Returns:                                                                 */
2634 /*   Nothing.                                                               */
2635 /****************************************************************************/
2636 static void
2637 bce_init_rxp_cpu(struct bce_softc *sc)
2638 {
2639         struct cpu_reg cpu_reg;
2640         struct fw_info fw;
2641
2642         cpu_reg.mode = BCE_RXP_CPU_MODE;
2643         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2644         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2645         cpu_reg.state = BCE_RXP_CPU_STATE;
2646         cpu_reg.state_value_clear = 0xffffff;
2647         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2648         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2649         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2650         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2651         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2652         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2653         cpu_reg.mips_view_base = 0x8000000;
2654
2655         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2656             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2657                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2658                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2659                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2660                 fw.start_addr = bce_RXP_b09FwStartAddr;
2661
2662                 fw.text_addr = bce_RXP_b09FwTextAddr;
2663                 fw.text_len = bce_RXP_b09FwTextLen;
2664                 fw.text_index = 0;
2665                 fw.text = bce_RXP_b09FwText;
2666
2667                 fw.data_addr = bce_RXP_b09FwDataAddr;
2668                 fw.data_len = bce_RXP_b09FwDataLen;
2669                 fw.data_index = 0;
2670                 fw.data = bce_RXP_b09FwData;
2671
2672                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2673                 fw.sbss_len = bce_RXP_b09FwSbssLen;
2674                 fw.sbss_index = 0;
2675                 fw.sbss = bce_RXP_b09FwSbss;
2676
2677                 fw.bss_addr = bce_RXP_b09FwBssAddr;
2678                 fw.bss_len = bce_RXP_b09FwBssLen;
2679                 fw.bss_index = 0;
2680                 fw.bss = bce_RXP_b09FwBss;
2681
2682                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2683                 fw.rodata_len = bce_RXP_b09FwRodataLen;
2684                 fw.rodata_index = 0;
2685                 fw.rodata = bce_RXP_b09FwRodata;
2686         } else {
2687                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2688                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2689                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2690                 fw.start_addr = bce_RXP_b06FwStartAddr;
2691
2692                 fw.text_addr = bce_RXP_b06FwTextAddr;
2693                 fw.text_len = bce_RXP_b06FwTextLen;
2694                 fw.text_index = 0;
2695                 fw.text = bce_RXP_b06FwText;
2696
2697                 fw.data_addr = bce_RXP_b06FwDataAddr;
2698                 fw.data_len = bce_RXP_b06FwDataLen;
2699                 fw.data_index = 0;
2700                 fw.data = bce_RXP_b06FwData;
2701
2702                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2703                 fw.sbss_len = bce_RXP_b06FwSbssLen;
2704                 fw.sbss_index = 0;
2705                 fw.sbss = bce_RXP_b06FwSbss;
2706
2707                 fw.bss_addr = bce_RXP_b06FwBssAddr;
2708                 fw.bss_len = bce_RXP_b06FwBssLen;
2709                 fw.bss_index = 0;
2710                 fw.bss = bce_RXP_b06FwBss;
2711
2712                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2713                 fw.rodata_len = bce_RXP_b06FwRodataLen;
2714                 fw.rodata_index = 0;
2715                 fw.rodata = bce_RXP_b06FwRodata;
2716         }
2717
2718         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2719         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2720 }
2721
2722
2723 /****************************************************************************/
2724 /* Initialize the TX CPU.                                                   */
2725 /*                                                                          */
2726 /* Returns:                                                                 */
2727 /*   Nothing.                                                               */
2728 /****************************************************************************/
2729 static void
2730 bce_init_txp_cpu(struct bce_softc *sc)
2731 {
2732         struct cpu_reg cpu_reg;
2733         struct fw_info fw;
2734
2735         cpu_reg.mode = BCE_TXP_CPU_MODE;
2736         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2737         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2738         cpu_reg.state = BCE_TXP_CPU_STATE;
2739         cpu_reg.state_value_clear = 0xffffff;
2740         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2741         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2742         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2743         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2744         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2745         cpu_reg.spad_base = BCE_TXP_SCRATCH;
2746         cpu_reg.mips_view_base = 0x8000000;
2747
2748         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2749             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2750                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2751                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2752                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2753                 fw.start_addr = bce_TXP_b09FwStartAddr;
2754
2755                 fw.text_addr = bce_TXP_b09FwTextAddr;
2756                 fw.text_len = bce_TXP_b09FwTextLen;
2757                 fw.text_index = 0;
2758                 fw.text = bce_TXP_b09FwText;
2759
2760                 fw.data_addr = bce_TXP_b09FwDataAddr;
2761                 fw.data_len = bce_TXP_b09FwDataLen;
2762                 fw.data_index = 0;
2763                 fw.data = bce_TXP_b09FwData;
2764
2765                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2766                 fw.sbss_len = bce_TXP_b09FwSbssLen;
2767                 fw.sbss_index = 0;
2768                 fw.sbss = bce_TXP_b09FwSbss;
2769
2770                 fw.bss_addr = bce_TXP_b09FwBssAddr;
2771                 fw.bss_len = bce_TXP_b09FwBssLen;
2772                 fw.bss_index = 0;
2773                 fw.bss = bce_TXP_b09FwBss;
2774
2775                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2776                 fw.rodata_len = bce_TXP_b09FwRodataLen;
2777                 fw.rodata_index = 0;
2778                 fw.rodata = bce_TXP_b09FwRodata;
2779         } else {
2780                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2781                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2782                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2783                 fw.start_addr = bce_TXP_b06FwStartAddr;
2784
2785                 fw.text_addr = bce_TXP_b06FwTextAddr;
2786                 fw.text_len = bce_TXP_b06FwTextLen;
2787                 fw.text_index = 0;
2788                 fw.text = bce_TXP_b06FwText;
2789
2790                 fw.data_addr = bce_TXP_b06FwDataAddr;
2791                 fw.data_len = bce_TXP_b06FwDataLen;
2792                 fw.data_index = 0;
2793                 fw.data = bce_TXP_b06FwData;
2794
2795                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2796                 fw.sbss_len = bce_TXP_b06FwSbssLen;
2797                 fw.sbss_index = 0;
2798                 fw.sbss = bce_TXP_b06FwSbss;
2799
2800                 fw.bss_addr = bce_TXP_b06FwBssAddr;
2801                 fw.bss_len = bce_TXP_b06FwBssLen;
2802                 fw.bss_index = 0;
2803                 fw.bss = bce_TXP_b06FwBss;
2804
2805                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2806                 fw.rodata_len = bce_TXP_b06FwRodataLen;
2807                 fw.rodata_index = 0;
2808                 fw.rodata = bce_TXP_b06FwRodata;
2809         }
2810
2811         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2812         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2813 }
2814
2815
2816 /****************************************************************************/
2817 /* Initialize the TPAT CPU.                                                 */
2818 /*                                                                          */
2819 /* Returns:                                                                 */
2820 /*   Nothing.                                                               */
2821 /****************************************************************************/
2822 static void
2823 bce_init_tpat_cpu(struct bce_softc *sc)
2824 {
2825         struct cpu_reg cpu_reg;
2826         struct fw_info fw;
2827
2828         cpu_reg.mode = BCE_TPAT_CPU_MODE;
2829         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2830         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2831         cpu_reg.state = BCE_TPAT_CPU_STATE;
2832         cpu_reg.state_value_clear = 0xffffff;
2833         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2834         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2835         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2836         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2837         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2838         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2839         cpu_reg.mips_view_base = 0x8000000;
2840
2841         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2842             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2843                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
2844                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
2845                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
2846                 fw.start_addr = bce_TPAT_b09FwStartAddr;
2847
2848                 fw.text_addr = bce_TPAT_b09FwTextAddr;
2849                 fw.text_len = bce_TPAT_b09FwTextLen;
2850                 fw.text_index = 0;
2851                 fw.text = bce_TPAT_b09FwText;
2852
2853                 fw.data_addr = bce_TPAT_b09FwDataAddr;
2854                 fw.data_len = bce_TPAT_b09FwDataLen;
2855                 fw.data_index = 0;
2856                 fw.data = bce_TPAT_b09FwData;
2857
2858                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
2859                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
2860                 fw.sbss_index = 0;
2861                 fw.sbss = bce_TPAT_b09FwSbss;
2862
2863                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
2864                 fw.bss_len = bce_TPAT_b09FwBssLen;
2865                 fw.bss_index = 0;
2866                 fw.bss = bce_TPAT_b09FwBss;
2867
2868                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
2869                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
2870                 fw.rodata_index = 0;
2871                 fw.rodata = bce_TPAT_b09FwRodata;
2872         } else {
2873                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
2874                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
2875                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
2876                 fw.start_addr = bce_TPAT_b06FwStartAddr;
2877
2878                 fw.text_addr = bce_TPAT_b06FwTextAddr;
2879                 fw.text_len = bce_TPAT_b06FwTextLen;
2880                 fw.text_index = 0;
2881                 fw.text = bce_TPAT_b06FwText;
2882
2883                 fw.data_addr = bce_TPAT_b06FwDataAddr;
2884                 fw.data_len = bce_TPAT_b06FwDataLen;
2885                 fw.data_index = 0;
2886                 fw.data = bce_TPAT_b06FwData;
2887
2888                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
2889                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
2890                 fw.sbss_index = 0;
2891                 fw.sbss = bce_TPAT_b06FwSbss;
2892
2893                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
2894                 fw.bss_len = bce_TPAT_b06FwBssLen;
2895                 fw.bss_index = 0;
2896                 fw.bss = bce_TPAT_b06FwBss;
2897
2898                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
2899                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
2900                 fw.rodata_index = 0;
2901                 fw.rodata = bce_TPAT_b06FwRodata;
2902         }
2903
2904         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
2905         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2906 }
2907
2908
2909 /****************************************************************************/
2910 /* Initialize the CP CPU.                                                   */
2911 /*                                                                          */
2912 /* Returns:                                                                 */
2913 /*   Nothing.                                                               */
2914 /****************************************************************************/
2915 static void
2916 bce_init_cp_cpu(struct bce_softc *sc)
2917 {
2918         struct cpu_reg cpu_reg;
2919         struct fw_info fw;
2920
2921         cpu_reg.mode = BCE_CP_CPU_MODE;
2922         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
2923         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
2924         cpu_reg.state = BCE_CP_CPU_STATE;
2925         cpu_reg.state_value_clear = 0xffffff;
2926         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
2927         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
2928         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
2929         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
2930         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
2931         cpu_reg.spad_base = BCE_CP_SCRATCH;
2932         cpu_reg.mips_view_base = 0x8000000;
2933
2934         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2935             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2936                 fw.ver_major = bce_CP_b09FwReleaseMajor;
2937                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
2938                 fw.ver_fix = bce_CP_b09FwReleaseFix;
2939                 fw.start_addr = bce_CP_b09FwStartAddr;
2940
2941                 fw.text_addr = bce_CP_b09FwTextAddr;
2942                 fw.text_len = bce_CP_b09FwTextLen;
2943                 fw.text_index = 0;
2944                 fw.text = bce_CP_b09FwText;
2945
2946                 fw.data_addr = bce_CP_b09FwDataAddr;
2947                 fw.data_len = bce_CP_b09FwDataLen;
2948                 fw.data_index = 0;
2949                 fw.data = bce_CP_b09FwData;
2950
2951                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
2952                 fw.sbss_len = bce_CP_b09FwSbssLen;
2953                 fw.sbss_index = 0;
2954                 fw.sbss = bce_CP_b09FwSbss;
2955
2956                 fw.bss_addr = bce_CP_b09FwBssAddr;
2957                 fw.bss_len = bce_CP_b09FwBssLen;
2958                 fw.bss_index = 0;
2959                 fw.bss = bce_CP_b09FwBss;
2960
2961                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
2962                 fw.rodata_len = bce_CP_b09FwRodataLen;
2963                 fw.rodata_index = 0;
2964                 fw.rodata = bce_CP_b09FwRodata;
2965         } else {
2966                 fw.ver_major = bce_CP_b06FwReleaseMajor;
2967                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
2968                 fw.ver_fix = bce_CP_b06FwReleaseFix;
2969                 fw.start_addr = bce_CP_b06FwStartAddr;
2970
2971                 fw.text_addr = bce_CP_b06FwTextAddr;
2972                 fw.text_len = bce_CP_b06FwTextLen;
2973                 fw.text_index = 0;
2974                 fw.text = bce_CP_b06FwText;
2975
2976                 fw.data_addr = bce_CP_b06FwDataAddr;
2977                 fw.data_len = bce_CP_b06FwDataLen;
2978                 fw.data_index = 0;
2979                 fw.data = bce_CP_b06FwData;
2980
2981                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
2982                 fw.sbss_len = bce_CP_b06FwSbssLen;
2983                 fw.sbss_index = 0;
2984                 fw.sbss = bce_CP_b06FwSbss;
2985
2986                 fw.bss_addr = bce_CP_b06FwBssAddr;
2987                 fw.bss_len = bce_CP_b06FwBssLen;
2988                 fw.bss_index = 0;
2989                 fw.bss = bce_CP_b06FwBss;
2990
2991                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
2992                 fw.rodata_len = bce_CP_b06FwRodataLen;
2993                 fw.rodata_index = 0;
2994                 fw.rodata = bce_CP_b06FwRodata;
2995         }
2996
2997         DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
2998         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2999 }
3000
3001
3002 /****************************************************************************/
3003 /* Initialize the COM CPU.                                                 */
3004 /*                                                                          */
3005 /* Returns:                                                                 */
3006 /*   Nothing.                                                               */
3007 /****************************************************************************/
3008 static void
3009 bce_init_com_cpu(struct bce_softc *sc)
3010 {
3011         struct cpu_reg cpu_reg;
3012         struct fw_info fw;
3013
3014         cpu_reg.mode = BCE_COM_CPU_MODE;
3015         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3016         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3017         cpu_reg.state = BCE_COM_CPU_STATE;
3018         cpu_reg.state_value_clear = 0xffffff;
3019         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3020         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3021         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3022         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3023         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3024         cpu_reg.spad_base = BCE_COM_SCRATCH;
3025         cpu_reg.mips_view_base = 0x8000000;
3026
3027         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3028             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3029                 fw.ver_major = bce_COM_b09FwReleaseMajor;
3030                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
3031                 fw.ver_fix = bce_COM_b09FwReleaseFix;
3032                 fw.start_addr = bce_COM_b09FwStartAddr;
3033
3034                 fw.text_addr = bce_COM_b09FwTextAddr;
3035                 fw.text_len = bce_COM_b09FwTextLen;
3036                 fw.text_index = 0;
3037                 fw.text = bce_COM_b09FwText;
3038
3039                 fw.data_addr = bce_COM_b09FwDataAddr;
3040                 fw.data_len = bce_COM_b09FwDataLen;
3041                 fw.data_index = 0;
3042                 fw.data = bce_COM_b09FwData;
3043
3044                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
3045                 fw.sbss_len = bce_COM_b09FwSbssLen;
3046                 fw.sbss_index = 0;
3047                 fw.sbss = bce_COM_b09FwSbss;
3048
3049                 fw.bss_addr = bce_COM_b09FwBssAddr;
3050                 fw.bss_len = bce_COM_b09FwBssLen;
3051                 fw.bss_index = 0;
3052                 fw.bss = bce_COM_b09FwBss;
3053
3054                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
3055                 fw.rodata_len = bce_COM_b09FwRodataLen;
3056                 fw.rodata_index = 0;
3057                 fw.rodata = bce_COM_b09FwRodata;
3058         } else {
3059                 fw.ver_major = bce_COM_b06FwReleaseMajor;
3060                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3061                 fw.ver_fix = bce_COM_b06FwReleaseFix;
3062                 fw.start_addr = bce_COM_b06FwStartAddr;
3063
3064                 fw.text_addr = bce_COM_b06FwTextAddr;
3065                 fw.text_len = bce_COM_b06FwTextLen;
3066                 fw.text_index = 0;
3067                 fw.text = bce_COM_b06FwText;
3068
3069                 fw.data_addr = bce_COM_b06FwDataAddr;
3070                 fw.data_len = bce_COM_b06FwDataLen;
3071                 fw.data_index = 0;
3072                 fw.data = bce_COM_b06FwData;
3073
3074                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3075                 fw.sbss_len = bce_COM_b06FwSbssLen;
3076                 fw.sbss_index = 0;
3077                 fw.sbss = bce_COM_b06FwSbss;
3078
3079                 fw.bss_addr = bce_COM_b06FwBssAddr;
3080                 fw.bss_len = bce_COM_b06FwBssLen;
3081                 fw.bss_index = 0;
3082                 fw.bss = bce_COM_b06FwBss;
3083
3084                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3085                 fw.rodata_len = bce_COM_b06FwRodataLen;
3086                 fw.rodata_index = 0;
3087                 fw.rodata = bce_COM_b06FwRodata;
3088         }
3089
3090         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3091         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3092 }
3093
3094
3095 /****************************************************************************/
3096 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
3097 /*                                                                          */
3098 /* Loads the firmware for each CPU and starts the CPU.                      */
3099 /*                                                                          */
3100 /* Returns:                                                                 */
3101 /*   Nothing.                                                               */
3102 /****************************************************************************/
3103 static void
3104 bce_init_cpus(struct bce_softc *sc)
3105 {
3106         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3107             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3108                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3109                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3110                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3111                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3112                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3113                 } else {
3114                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3115                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3116                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3117                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3118                 }
3119         } else {
3120                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3121                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
3122                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3123                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
3124         }
3125
3126         bce_init_rxp_cpu(sc);
3127         bce_init_txp_cpu(sc);
3128         bce_init_tpat_cpu(sc);
3129         bce_init_com_cpu(sc);
3130         bce_init_cp_cpu(sc);
3131 }
3132
3133
3134 /****************************************************************************/
3135 /* Initialize context memory.                                               */
3136 /*                                                                          */
3137 /* Clears the memory associated with each Context ID (CID).                 */
3138 /*                                                                          */
3139 /* Returns:                                                                 */
3140 /*   Nothing.                                                               */
3141 /****************************************************************************/
3142 static void
3143 bce_init_ctx(struct bce_softc *sc)
3144 {
3145         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3146             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3147                 /* DRC: Replace this constant value with a #define. */
3148                 int i, retry_cnt = 10;
3149                 uint32_t val;
3150
3151                 /*
3152                  * BCM5709 context memory may be cached
3153                  * in host memory so prepare the host memory
3154                  * for access.
3155                  */
3156                 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3157                     (1 << 12);
3158                 val |= (BCM_PAGE_BITS - 8) << 16;
3159                 REG_WR(sc, BCE_CTX_COMMAND, val);
3160
3161                 /* Wait for mem init command to complete. */
3162                 for (i = 0; i < retry_cnt; i++) {
3163                         val = REG_RD(sc, BCE_CTX_COMMAND);
3164                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3165                                 break;
3166                         DELAY(2);
3167                 }
3168
3169                 for (i = 0; i < sc->ctx_pages; i++) {
3170                         int j;
3171
3172                         /*
3173                          * Set the physical address of the context
3174                          * memory cache.
3175                          */
3176                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3177                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3178                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3179                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3180                             BCE_ADDR_HI(sc->ctx_paddr[i]));
3181                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3182                             i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3183
3184                         /*
3185                          * Verify that the context memory write was successful.
3186                          */
3187                         for (j = 0; j < retry_cnt; j++) {
3188                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3189                                 if ((val &
3190                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3191                                         break;
3192                                 DELAY(5);
3193                         }
3194                 }
3195         } else {
3196                 uint32_t vcid_addr, offset;
3197
3198                 /*
3199                  * For the 5706/5708, context memory is local to
3200                  * the controller, so initialize the controller
3201                  * context memory.
3202                  */
3203
3204                 vcid_addr = GET_CID_ADDR(96);
3205                 while (vcid_addr) {
3206                         vcid_addr -= PHY_CTX_SIZE;
3207
3208                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3209                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3210
3211                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3212                                 CTX_WR(sc, 0x00, offset, 0);
3213
3214                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3215                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3216                 }
3217         }
3218 }
3219
3220
3221 /****************************************************************************/
3222 /* Fetch the permanent MAC address of the controller.                       */
3223 /*                                                                          */
3224 /* Returns:                                                                 */
3225 /*   Nothing.                                                               */
3226 /****************************************************************************/
3227 static void
3228 bce_get_mac_addr(struct bce_softc *sc)
3229 {
3230         uint32_t mac_lo = 0, mac_hi = 0;
3231
3232         /*
3233          * The NetXtreme II bootcode populates various NIC
3234          * power-on and runtime configuration items in a
3235          * shared memory area.  The factory configured MAC
3236          * address is available from both NVRAM and the
3237          * shared memory area so we'll read the value from
3238          * shared memory for speed.
3239          */
3240
3241         mac_hi = bce_shmem_rd(sc,  BCE_PORT_HW_CFG_MAC_UPPER);
3242         mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
3243
3244         if (mac_lo == 0 && mac_hi == 0) {
3245                 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3246         } else {
3247                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3248                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3249                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3250                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3251                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3252                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3253         }
3254
3255         DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3256 }
3257
3258
3259 /****************************************************************************/
3260 /* Program the MAC address.                                                 */
3261 /*                                                                          */
3262 /* Returns:                                                                 */
3263 /*   Nothing.                                                               */
3264 /****************************************************************************/
3265 static void
3266 bce_set_mac_addr(struct bce_softc *sc)
3267 {
3268         const uint8_t *mac_addr = sc->eaddr;
3269         uint32_t val;
3270
3271         DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3272                 sc->eaddr, ":");
3273
3274         val = (mac_addr[0] << 8) | mac_addr[1];
3275         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3276
3277         val = (mac_addr[2] << 24) |
3278               (mac_addr[3] << 16) |
3279               (mac_addr[4] << 8) |
3280               mac_addr[5];
3281         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3282 }
3283
3284
3285 /****************************************************************************/
3286 /* Stop the controller.                                                     */
3287 /*                                                                          */
3288 /* Returns:                                                                 */
3289 /*   Nothing.                                                               */
3290 /****************************************************************************/
3291 static void
3292 bce_stop(struct bce_softc *sc)
3293 {
3294         struct ifnet *ifp = &sc->arpcom.ac_if;
3295         struct mii_data *mii = device_get_softc(sc->bce_miibus);
3296         struct ifmedia_entry *ifm;
3297         int mtmp, itmp;
3298
3299         ASSERT_SERIALIZED(ifp->if_serializer);
3300
3301         callout_stop(&sc->bce_tick_callout);
3302
3303         /* Disable the transmit/receive blocks. */
3304         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3305         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3306         DELAY(20);
3307
3308         bce_disable_intr(sc);
3309
3310         /* Free the RX lists. */
3311         bce_free_rx_chain(sc);
3312
3313         /* Free TX buffers. */
3314         bce_free_tx_chain(sc);
3315
3316         /*
3317          * Isolate/power down the PHY, but leave the media selection
3318          * unchanged so that things will be put back to normal when
3319          * we bring the interface back up.
3320          *
3321          * 'mii' may be NULL if bce_stop() is called by bce_detach().
3322          */
3323         if (mii != NULL) {
3324                 itmp = ifp->if_flags;
3325                 ifp->if_flags |= IFF_UP;
3326                 ifm = mii->mii_media.ifm_cur;
3327                 mtmp = ifm->ifm_media;
3328                 ifm->ifm_media = IFM_ETHER | IFM_NONE;
3329                 mii_mediachg(mii);
3330                 ifm->ifm_media = mtmp;
3331                 ifp->if_flags = itmp;
3332         }
3333
3334         sc->bce_link = 0;
3335         sc->bce_coalchg_mask = 0;
3336
3337         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3338         ifp->if_timer = 0;
3339 }
3340
3341
3342 static int
3343 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3344 {
3345         uint32_t val;
3346         int i, rc = 0;
3347
3348         /* Wait for pending PCI transactions to complete. */
3349         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3350                BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3351                BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3352                BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3353                BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3354         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3355         DELAY(5);
3356
3357         /* Disable DMA */
3358         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3359             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3360                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3361                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3362                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3363         }
3364
3365         /* Assume bootcode is running. */
3366         sc->bce_fw_timed_out = 0;
3367
3368         /* Give the firmware a chance to prepare for the reset. */
3369         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3370         if (rc) {
3371                 if_printf(&sc->arpcom.ac_if,
3372                           "Firmware is not ready for reset\n");
3373                 return rc;
3374         }
3375
3376         /* Set a firmware reminder that this is a soft reset. */
3377         bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE,
3378             BCE_DRV_RESET_SIGNATURE_MAGIC);
3379
3380         /* Dummy read to force the chip to complete all current transactions. */
3381         val = REG_RD(sc, BCE_MISC_ID);
3382
3383         /* Chip reset. */
3384         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3385             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3386                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3387                 REG_RD(sc, BCE_MISC_COMMAND);
3388                 DELAY(5);
3389
3390                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3391                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3392
3393                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3394         } else {
3395                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3396                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3397                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3398                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3399
3400                 /* Allow up to 30us for reset to complete. */
3401                 for (i = 0; i < 10; i++) {
3402                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3403                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3404                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3405                                 break;
3406                         DELAY(10);
3407                 }
3408
3409                 /* Check that reset completed successfully. */
3410                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3411                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3412                         if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3413                         return EBUSY;
3414                 }
3415         }
3416
3417         /* Make sure byte swapping is properly configured. */
3418         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3419         if (val != 0x01020304) {
3420                 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3421                 return ENODEV;
3422         }
3423
3424         /* Just completed a reset, assume that firmware is running again. */
3425         sc->bce_fw_timed_out = 0;
3426
3427         /* Wait for the firmware to finish its initialization. */
3428         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3429         if (rc) {
3430                 if_printf(&sc->arpcom.ac_if,
3431                           "Firmware did not complete initialization!\n");
3432         }
3433         return rc;
3434 }
3435
3436
3437 static int
3438 bce_chipinit(struct bce_softc *sc)
3439 {
3440         uint32_t val;
3441         int rc = 0;
3442
3443         /* Make sure the interrupt is not active. */
3444         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3445         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3446
3447         /*
3448          * Initialize DMA byte/word swapping, configure the number of DMA
3449          * channels and PCI clock compensation delay.
3450          */
3451         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3452               BCE_DMA_CONFIG_DATA_WORD_SWAP |
3453 #if BYTE_ORDER == BIG_ENDIAN
3454               BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3455 #endif
3456               BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3457               DMA_READ_CHANS << 12 |
3458               DMA_WRITE_CHANS << 16;
3459
3460         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3461
3462         if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3463                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3464
3465         /*
3466          * This setting resolves a problem observed on certain Intel PCI
3467          * chipsets that cannot handle multiple outstanding DMA operations.
3468          * See errata E9_5706A1_65.
3469          */
3470         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3471             BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3472             !(sc->bce_flags & BCE_PCIX_FLAG))
3473                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3474
3475         REG_WR(sc, BCE_DMA_CONFIG, val);
3476
3477         /* Enable the RX_V2P and Context state machines before access. */
3478         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3479                BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3480                BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3481                BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3482
3483         /* Initialize context mapping and zero out the quick contexts. */
3484         bce_init_ctx(sc);
3485
3486         /* Initialize the on-boards CPUs */
3487         bce_init_cpus(sc);
3488
3489         /* Prepare NVRAM for access. */
3490         rc = bce_init_nvram(sc);
3491         if (rc != 0)
3492                 return rc;
3493
3494         /* Set the kernel bypass block size */
3495         val = REG_RD(sc, BCE_MQ_CONFIG);
3496         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3497         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3498
3499         /* Enable bins used on the 5709/5716. */
3500         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3501             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3502                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3503                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3504                         val |= BCE_MQ_CONFIG_HALT_DIS;
3505         }
3506
3507         REG_WR(sc, BCE_MQ_CONFIG, val);
3508
3509         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3510         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3511         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3512
3513         /* Set the page size and clear the RV2P processor stall bits. */
3514         val = (BCM_PAGE_BITS - 8) << 24;
3515         REG_WR(sc, BCE_RV2P_CONFIG, val);
3516
3517         /* Configure page size. */
3518         val = REG_RD(sc, BCE_TBDR_CONFIG);
3519         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3520         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3521         REG_WR(sc, BCE_TBDR_CONFIG, val);
3522
3523         /* Set the perfect match control register to default. */
3524         REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
3525
3526         return 0;
3527 }
3528
3529
3530 /****************************************************************************/
3531 /* Initialize the controller in preparation to send/receive traffic.        */
3532 /*                                                                          */
3533 /* Returns:                                                                 */
3534 /*   0 for success, positive value for failure.                             */
3535 /****************************************************************************/
3536 static int
3537 bce_blockinit(struct bce_softc *sc)
3538 {
3539         uint32_t reg, val;
3540         int rc = 0;
3541
3542         /* Load the hardware default MAC address. */
3543         bce_set_mac_addr(sc);
3544
3545         /* Set the Ethernet backoff seed value */
3546         val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3547               sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3548         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3549
3550         sc->last_status_idx = 0;
3551         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3552
3553         /* Set up link change interrupt generation. */
3554         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3555
3556         /* Program the physical address of the status block. */
3557         REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3558         REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3559
3560         /* Program the physical address of the statistics block. */
3561         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3562                BCE_ADDR_LO(sc->stats_block_paddr));
3563         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3564                BCE_ADDR_HI(sc->stats_block_paddr));
3565
3566         /* Program various host coalescing parameters. */
3567         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3568                (sc->bce_tx_quick_cons_trip_int << 16) |
3569                sc->bce_tx_quick_cons_trip);
3570         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3571                (sc->bce_rx_quick_cons_trip_int << 16) |
3572                sc->bce_rx_quick_cons_trip);
3573         REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3574                (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3575         REG_WR(sc, BCE_HC_TX_TICKS,
3576                (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3577         REG_WR(sc, BCE_HC_RX_TICKS,
3578                (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3579         REG_WR(sc, BCE_HC_COM_TICKS,
3580                (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3581         REG_WR(sc, BCE_HC_CMD_TICKS,
3582                (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3583         REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3584         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);   /* 3ms */
3585         REG_WR(sc, BCE_HC_CONFIG,
3586                BCE_HC_CONFIG_TX_TMR_MODE |
3587                BCE_HC_CONFIG_COLLECT_STATS);
3588
3589         /* Clear the internal statistics counters. */
3590         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3591
3592         /* Verify that bootcode is running. */
3593         reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
3594
3595         DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3596                 if_printf(&sc->arpcom.ac_if,
3597                           "%s(%d): Simulating bootcode failure.\n",
3598                           __FILE__, __LINE__);
3599                 reg = 0);
3600
3601         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3602             BCE_DEV_INFO_SIGNATURE_MAGIC) {
3603                 if_printf(&sc->arpcom.ac_if,
3604                           "Bootcode not running! Found: 0x%08X, "
3605                           "Expected: 08%08X\n",
3606                           reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3607                           BCE_DEV_INFO_SIGNATURE_MAGIC);
3608                 return ENODEV;
3609         }
3610
3611         /* Enable DMA */
3612         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3613             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3614                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3615                 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3616                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3617         }
3618
3619         /* Allow bootcode to apply any additional fixes before enabling MAC. */
3620         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3621
3622         /* Enable link state change interrupt generation. */
3623         REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3624
3625         /* Enable all remaining blocks in the MAC. */
3626         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3627             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3628                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3629                     BCE_MISC_ENABLE_DEFAULT_XI);
3630         } else {
3631                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
3632         }
3633         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3634         DELAY(20);
3635
3636         /* Save the current host coalescing block settings. */
3637         sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
3638
3639         return 0;
3640 }
3641
3642
3643 /****************************************************************************/
3644 /* Encapsulate an mbuf cluster into the rx_bd chain.                        */
3645 /*                                                                          */
3646 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's.     */
3647 /* This routine will map an mbuf cluster into 1 or more rx_bd's as          */
3648 /* necessary.                                                               */
3649 /*                                                                          */
3650 /* Returns:                                                                 */
3651 /*   0 for success, positive value for failure.                             */
3652 /****************************************************************************/
3653 static int
3654 bce_newbuf_std(struct bce_softc *sc, uint16_t *prod, uint16_t *chain_prod,
3655                uint32_t *prod_bseq, int init)
3656 {
3657         bus_dmamap_t map;
3658         bus_dma_segment_t seg;
3659         struct mbuf *m_new;
3660         int error, nseg;
3661 #ifdef BCE_DEBUG
3662         uint16_t debug_chain_prod = *chain_prod;
3663 #endif
3664
3665         /* Make sure the inputs are valid. */
3666         DBRUNIF((*chain_prod > MAX_RX_BD),
3667                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3668                           "RX producer out of range: 0x%04X > 0x%04X\n",
3669                           __FILE__, __LINE__,
3670                           *chain_prod, (uint16_t)MAX_RX_BD));
3671
3672         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3673                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3674
3675         DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3676                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3677                           "Simulating mbuf allocation failure.\n",
3678                           __FILE__, __LI