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32 ******************************************************************************/
36 * 82543GC Gigabit Ethernet Controller (Fiber)
37 * 82543GC Gigabit Ethernet Controller (Copper)
38 * 82544EI Gigabit Ethernet Controller (Copper)
39 * 82544EI Gigabit Ethernet Controller (Fiber)
40 * 82544GC Gigabit Ethernet Controller (Copper)
41 * 82544GC Gigabit Ethernet Controller (LOM)
44 #include "e1000_api.h"
46 static s32 e1000_init_phy_params_82543(struct e1000_hw *hw);
47 static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw);
48 static s32 e1000_init_mac_params_82543(struct e1000_hw *hw);
49 static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset,
51 static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset,
53 static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw);
54 static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw);
55 static s32 e1000_reset_hw_82543(struct e1000_hw *hw);
56 static s32 e1000_init_hw_82543(struct e1000_hw *hw);
57 static s32 e1000_setup_link_82543(struct e1000_hw *hw);
58 static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw);
59 static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw);
60 static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw);
61 static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw);
62 static s32 e1000_led_on_82543(struct e1000_hw *hw);
63 static s32 e1000_led_off_82543(struct e1000_hw *hw);
64 static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset,
66 static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw);
67 static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw);
68 static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw);
69 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
70 static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw);
71 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
72 static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw);
73 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
75 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw);
76 static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state);
79 * e1000_init_phy_params_82543 - Init PHY func ptrs.
80 * @hw: pointer to the HW structure
82 static s32 e1000_init_phy_params_82543(struct e1000_hw *hw)
84 struct e1000_phy_info *phy = &hw->phy;
85 s32 ret_val = E1000_SUCCESS;
87 DEBUGFUNC("e1000_init_phy_params_82543");
89 if (hw->phy.media_type != e1000_media_type_copper) {
90 phy->type = e1000_phy_none;
93 phy->ops.power_up = e1000_power_up_phy_copper;
94 phy->ops.power_down = e1000_power_down_phy_copper;
98 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
99 phy->reset_delay_us = 10000;
100 phy->type = e1000_phy_m88;
102 /* Function Pointers */
103 phy->ops.check_polarity = e1000_check_polarity_m88;
104 phy->ops.commit = e1000_phy_sw_reset_generic;
105 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82543;
106 phy->ops.get_cable_length = e1000_get_cable_length_m88;
107 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
108 phy->ops.read_reg = (hw->mac.type == e1000_82543)
109 ? e1000_read_phy_reg_82543
110 : e1000_read_phy_reg_m88;
111 phy->ops.reset = (hw->mac.type == e1000_82543)
112 ? e1000_phy_hw_reset_82543
113 : e1000_phy_hw_reset_generic;
114 phy->ops.write_reg = (hw->mac.type == e1000_82543)
115 ? e1000_write_phy_reg_82543
116 : e1000_write_phy_reg_m88;
117 phy->ops.get_info = e1000_get_phy_info_m88;
120 * The external PHY of the 82543 can be in a funky state.
121 * Resetting helps us read the PHY registers for acquiring
124 if (!e1000_init_phy_disabled_82543(hw)) {
125 ret_val = phy->ops.reset(hw);
127 DEBUGOUT("Resetting PHY during init failed.\n");
133 ret_val = e1000_get_phy_id(hw);
138 switch (hw->mac.type) {
140 if (phy->id != M88E1000_E_PHY_ID) {
141 ret_val = -E1000_ERR_PHY;
146 if (phy->id != M88E1000_I_PHY_ID) {
147 ret_val = -E1000_ERR_PHY;
152 ret_val = -E1000_ERR_PHY;
162 * e1000_init_nvm_params_82543 - Init NVM func ptrs.
163 * @hw: pointer to the HW structure
165 static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw)
167 struct e1000_nvm_info *nvm = &hw->nvm;
169 DEBUGFUNC("e1000_init_nvm_params_82543");
171 nvm->type = e1000_nvm_eeprom_microwire;
173 nvm->delay_usec = 50;
174 nvm->address_bits = 6;
175 nvm->opcode_bits = 3;
177 /* Function Pointers */
178 nvm->ops.read = e1000_read_nvm_microwire;
179 nvm->ops.update = e1000_update_nvm_checksum_generic;
180 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
181 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
182 nvm->ops.write = e1000_write_nvm_microwire;
184 return E1000_SUCCESS;
188 * e1000_init_mac_params_82543 - Init MAC func ptrs.
189 * @hw: pointer to the HW structure
191 static s32 e1000_init_mac_params_82543(struct e1000_hw *hw)
193 struct e1000_mac_info *mac = &hw->mac;
195 DEBUGFUNC("e1000_init_mac_params_82543");
198 switch (hw->device_id) {
199 case E1000_DEV_ID_82543GC_FIBER:
200 case E1000_DEV_ID_82544EI_FIBER:
201 hw->phy.media_type = e1000_media_type_fiber;
204 hw->phy.media_type = e1000_media_type_copper;
208 /* Set mta register count */
209 mac->mta_reg_count = 128;
210 /* Set rar entry count */
211 mac->rar_entry_count = E1000_RAR_ENTRIES;
213 /* Function pointers */
215 /* bus type/speed/width */
216 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
218 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
220 mac->ops.reset_hw = e1000_reset_hw_82543;
221 /* hw initialization */
222 mac->ops.init_hw = e1000_init_hw_82543;
224 mac->ops.setup_link = e1000_setup_link_82543;
225 /* physical interface setup */
226 mac->ops.setup_physical_interface =
227 (hw->phy.media_type == e1000_media_type_copper)
228 ? e1000_setup_copper_link_82543
229 : e1000_setup_fiber_link_82543;
231 mac->ops.check_for_link =
232 (hw->phy.media_type == e1000_media_type_copper)
233 ? e1000_check_for_copper_link_82543
234 : e1000_check_for_fiber_link_82543;
236 mac->ops.get_link_up_info =
237 (hw->phy.media_type == e1000_media_type_copper)
238 ? e1000_get_speed_and_duplex_copper_generic
239 : e1000_get_speed_and_duplex_fiber_serdes_generic;
240 /* multicast address update */
241 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
243 mac->ops.write_vfta = e1000_write_vfta_82543;
245 mac->ops.clear_vfta = e1000_clear_vfta_generic;
246 /* turn on/off LED */
247 mac->ops.led_on = e1000_led_on_82543;
248 mac->ops.led_off = e1000_led_off_82543;
249 /* clear hardware counters */
250 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82543;
252 /* Set tbi compatibility */
253 if ((hw->mac.type != e1000_82543) ||
254 (hw->phy.media_type == e1000_media_type_fiber))
255 e1000_set_tbi_compatibility_82543(hw, FALSE);
257 return E1000_SUCCESS;
261 * e1000_init_function_pointers_82543 - Init func ptrs.
262 * @hw: pointer to the HW structure
264 * Called to initialize all function pointers and parameters.
266 void e1000_init_function_pointers_82543(struct e1000_hw *hw)
268 DEBUGFUNC("e1000_init_function_pointers_82543");
270 hw->mac.ops.init_params = e1000_init_mac_params_82543;
271 hw->nvm.ops.init_params = e1000_init_nvm_params_82543;
272 hw->phy.ops.init_params = e1000_init_phy_params_82543;
276 * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status
277 * @hw: pointer to the HW structure
279 * Returns the current status of 10-bit Interface (TBI) compatibility
280 * (enabled/disabled).
282 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw)
284 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
287 DEBUGFUNC("e1000_tbi_compatibility_enabled_82543");
289 if (hw->mac.type != e1000_82543) {
290 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
294 state = (dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED)
302 * e1000_set_tbi_compatibility_82543 - Set TBI compatibility
303 * @hw: pointer to the HW structure
304 * @state: enable/disable TBI compatibility
306 * Enables or disabled 10-bit Interface (TBI) compatibility.
308 void e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state)
310 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
312 DEBUGFUNC("e1000_set_tbi_compatibility_82543");
314 if (hw->mac.type != e1000_82543) {
315 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
320 dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED;
322 dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED;
329 * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status
330 * @hw: pointer to the HW structure
332 * Returns the current status of 10-bit Interface (TBI) store bad packet (SBP)
333 * (enabled/disabled).
335 bool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw)
337 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
340 DEBUGFUNC("e1000_tbi_sbp_enabled_82543");
342 if (hw->mac.type != e1000_82543) {
343 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
347 state = (dev_spec->tbi_compatibility & TBI_SBP_ENABLED)
355 * e1000_set_tbi_sbp_82543 - Set TBI SBP
356 * @hw: pointer to the HW structure
357 * @state: enable/disable TBI store bad packet
359 * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP).
361 static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state)
363 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
365 DEBUGFUNC("e1000_set_tbi_sbp_82543");
367 if (state && e1000_tbi_compatibility_enabled_82543(hw))
368 dev_spec->tbi_compatibility |= TBI_SBP_ENABLED;
370 dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED;
376 * e1000_init_phy_disabled_82543 - Returns init PHY status
377 * @hw: pointer to the HW structure
379 * Returns the current status of whether PHY initialization is disabled.
380 * True if PHY initialization is disabled else FALSE.
382 static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw)
384 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
387 DEBUGFUNC("e1000_init_phy_disabled_82543");
389 if (hw->mac.type != e1000_82543) {
394 ret_val = dev_spec->init_phy_disabled;
401 * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled
402 * @hw: pointer to the HW structure
403 * @stats: Struct containing statistic register values
404 * @frame_len: The length of the frame in question
405 * @mac_addr: The Ethernet destination address of the frame in question
406 * @max_frame_size: The maximum frame size
408 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
410 void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw,
411 struct e1000_hw_stats *stats, u32 frame_len,
412 u8 *mac_addr, u32 max_frame_size)
414 if (!(e1000_tbi_sbp_enabled_82543(hw)))
417 /* First adjust the frame length. */
420 * We need to adjust the statistics counters, since the hardware
421 * counters overcount this packet as a CRC error and undercount
422 * the packet as a good packet
424 /* This packet should not be counted as a CRC error. */
426 /* This packet does count as a Good Packet Received. */
429 /* Adjust the Good Octets received counters */
430 stats->gorc += frame_len;
433 * Is this a broadcast or multicast? Check broadcast first,
434 * since the test for a multicast frame will test positive on
437 if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff))
438 /* Broadcast packet */
440 else if (*mac_addr & 0x01)
441 /* Multicast packet */
445 * In this case, the hardware has overcounted the number of
448 if ((frame_len == max_frame_size) && (stats->roc > 0))
452 * Adjust the bin counters when the extra byte put the frame in the
453 * wrong bin. Remember that the frame_len was adjusted above.
455 if (frame_len == 64) {
458 } else if (frame_len == 127) {
461 } else if (frame_len == 255) {
464 } else if (frame_len == 511) {
467 } else if (frame_len == 1023) {
470 } else if (frame_len == 1522) {
479 * e1000_read_phy_reg_82543 - Read PHY register
480 * @hw: pointer to the HW structure
481 * @offset: register offset to be read
482 * @data: pointer to the read data
484 * Reads the PHY at offset and stores the information read to data.
486 static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data)
489 s32 ret_val = E1000_SUCCESS;
491 DEBUGFUNC("e1000_read_phy_reg_82543");
493 if (offset > MAX_PHY_REG_ADDRESS) {
494 DEBUGOUT1("PHY Address %d is out of range\n", offset);
495 ret_val = -E1000_ERR_PARAM;
500 * We must first send a preamble through the MDIO pin to signal the
501 * beginning of an MII instruction. This is done by sending 32
502 * consecutive "1" bits.
504 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
507 * Now combine the next few fields that are required for a read
508 * operation. We use this method instead of calling the
509 * e1000_shift_out_mdi_bits routine five different times. The format
510 * of an MII read instruction consists of a shift out of 14 bits and
511 * is defined as follows:
512 * <Preamble><SOF><Op Code><Phy Addr><Offset>
513 * followed by a shift in of 18 bits. This first two bits shifted in
514 * are TurnAround bits used to avoid contention on the MDIO pin when a
515 * READ operation is performed. These two bits are thrown away
516 * followed by a shift in of 16 bits which contains the desired data.
518 mdic = (offset | (hw->phy.addr << 5) |
519 (PHY_OP_READ << 10) | (PHY_SOF << 12));
521 e1000_shift_out_mdi_bits_82543(hw, mdic, 14);
524 * Now that we've shifted out the read command to the MII, we need to
525 * "shift in" the 16-bit value (18 total bits) of the requested PHY
528 *data = e1000_shift_in_mdi_bits_82543(hw);
535 * e1000_write_phy_reg_82543 - Write PHY register
536 * @hw: pointer to the HW structure
537 * @offset: register offset to be written
538 * @data: pointer to the data to be written at offset
540 * Writes data to the PHY at offset.
542 static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data)
545 s32 ret_val = E1000_SUCCESS;
547 DEBUGFUNC("e1000_write_phy_reg_82543");
549 if (offset > MAX_PHY_REG_ADDRESS) {
550 DEBUGOUT1("PHY Address %d is out of range\n", offset);
551 ret_val = -E1000_ERR_PARAM;
556 * We'll need to use the SW defined pins to shift the write command
557 * out to the PHY. We first send a preamble to the PHY to signal the
558 * beginning of the MII instruction. This is done by sending 32
559 * consecutive "1" bits.
561 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
564 * Now combine the remaining required fields that will indicate a
565 * write operation. We use this method instead of calling the
566 * e1000_shift_out_mdi_bits routine for each field in the command. The
567 * format of a MII write instruction is as follows:
568 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
570 mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) |
571 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
575 e1000_shift_out_mdi_bits_82543(hw, mdic, 32);
582 * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock
583 * @hw: pointer to the HW structure
584 * @ctrl: pointer to the control register
586 * Raise the management data input clock by setting the MDC bit in the control
589 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
592 * Raise the clock input to the Management Data Clock (by setting the
593 * MDC bit), and then delay a sufficient amount of time.
595 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC));
596 E1000_WRITE_FLUSH(hw);
601 * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock
602 * @hw: pointer to the HW structure
603 * @ctrl: pointer to the control register
605 * Lower the management data input clock by clearing the MDC bit in the
608 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
611 * Lower the clock input to the Management Data Clock (by clearing the
612 * MDC bit), and then delay a sufficient amount of time.
614 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC));
615 E1000_WRITE_FLUSH(hw);
620 * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY
621 * @hw: pointer to the HW structure
622 * @data: data to send to the PHY
623 * @count: number of bits to shift out
625 * We need to shift 'count' bits out to the PHY. So, the value in the
626 * "data" parameter will be shifted out to the PHY one bit at a time.
627 * In order to do this, "data" must be broken down into bits.
629 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
635 * We need to shift "count" number of bits out to the PHY. So, the
636 * value in the "data" parameter will be shifted out to the PHY one
637 * bit at a time. In order to do this, "data" must be broken down
643 ctrl = E1000_READ_REG(hw, E1000_CTRL);
645 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
646 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
650 * A "1" is shifted out to the PHY by setting the MDIO bit to
651 * "1" and then raising and lowering the Management Data Clock.
652 * A "0" is shifted out to the PHY by setting the MDIO bit to
653 * "0" and then raising and lowering the clock.
655 if (data & mask) ctrl |= E1000_CTRL_MDIO;
656 else ctrl &= ~E1000_CTRL_MDIO;
658 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
659 E1000_WRITE_FLUSH(hw);
663 e1000_raise_mdi_clk_82543(hw, &ctrl);
664 e1000_lower_mdi_clk_82543(hw, &ctrl);
671 * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY
672 * @hw: pointer to the HW structure
674 * In order to read a register from the PHY, we need to shift 18 bits
675 * in from the PHY. Bits are "shifted in" by raising the clock input to
676 * the PHY (setting the MDC bit), and then reading the value of the data out
679 static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw)
686 * In order to read a register from the PHY, we need to shift in a
687 * total of 18 bits from the PHY. The first two bit (turnaround)
688 * times are used to avoid contention on the MDIO pin when a read
689 * operation is performed. These two bits are ignored by us and
690 * thrown away. Bits are "shifted in" by raising the input to the
691 * Management Data Clock (setting the MDC bit) and then reading the
692 * value of the MDIO bit.
694 ctrl = E1000_READ_REG(hw, E1000_CTRL);
697 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as
700 ctrl &= ~E1000_CTRL_MDIO_DIR;
701 ctrl &= ~E1000_CTRL_MDIO;
703 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
704 E1000_WRITE_FLUSH(hw);
707 * Raise and lower the clock before reading in the data. This accounts
708 * for the turnaround bits. The first clock occurred when we clocked
709 * out the last bit of the Register Address.
711 e1000_raise_mdi_clk_82543(hw, &ctrl);
712 e1000_lower_mdi_clk_82543(hw, &ctrl);
714 for (data = 0, i = 0; i < 16; i++) {
716 e1000_raise_mdi_clk_82543(hw, &ctrl);
717 ctrl = E1000_READ_REG(hw, E1000_CTRL);
718 /* Check to see if we shifted in a "1". */
719 if (ctrl & E1000_CTRL_MDIO)
721 e1000_lower_mdi_clk_82543(hw, &ctrl);
724 e1000_raise_mdi_clk_82543(hw, &ctrl);
725 e1000_lower_mdi_clk_82543(hw, &ctrl);
731 * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY
732 * @hw: pointer to the HW structure
734 * Calls the function to force speed and duplex for the m88 PHY, and
735 * if the PHY is not auto-negotiating and the speed is forced to 10Mbit,
736 * then call the function for polarity reversal workaround.
738 static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw)
742 DEBUGFUNC("e1000_phy_force_speed_duplex_82543");
744 ret_val = e1000_phy_force_speed_duplex_m88(hw);
748 if (!hw->mac.autoneg &&
749 (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED))
750 ret_val = e1000_polarity_reversal_workaround_82543(hw);
757 * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal
758 * @hw: pointer to the HW structure
760 * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity
761 * inadvertently. To workaround the issue, we disable the transmitter on
762 * the PHY until we have established the link partner's link parameters.
764 static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw)
766 s32 ret_val = E1000_SUCCESS;
771 if (!(hw->phy.ops.write_reg))
774 /* Polarity reversal workaround for forced 10F/10H links. */
776 /* Disable the transmitter on the PHY */
778 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
781 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
785 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
790 * This loop will early-out if the NO link condition has been met.
791 * In other words, DO NOT use e1000_phy_has_link_generic() here.
793 for (i = PHY_FORCE_TIME; i > 0; i--) {
795 * Read the MII Status Register and wait for Link Status bit
799 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
803 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
807 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
812 /* Recommended delay time after link has been lost */
813 msec_delay_irq(1000);
815 /* Now we will re-enable the transmitter on the PHY */
817 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
821 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
825 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
829 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
833 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
838 * Read the MII Status Register and wait for Link Status bit
841 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link);
850 * e1000_phy_hw_reset_82543 - PHY hardware reset
851 * @hw: pointer to the HW structure
853 * Sets the PHY_RESET_DIR bit in the extended device control register
854 * to put the PHY into a reset and waits for completion. Once the reset
855 * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out
858 static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw)
863 DEBUGFUNC("e1000_phy_hw_reset_82543");
866 * Read the Extended Device Control Register, assert the PHY_RESET_DIR
867 * bit to put the PHY into reset...
869 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
870 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
871 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
872 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
873 E1000_WRITE_FLUSH(hw);
877 /* ...then take it out of reset. */
878 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
879 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
880 E1000_WRITE_FLUSH(hw);
884 if (!(hw->phy.ops.get_cfg_done))
885 return E1000_SUCCESS;
887 ret_val = hw->phy.ops.get_cfg_done(hw);
893 * e1000_reset_hw_82543 - Reset hardware
894 * @hw: pointer to the HW structure
896 * This resets the hardware into a known state.
898 static s32 e1000_reset_hw_82543(struct e1000_hw *hw)
901 s32 ret_val = E1000_SUCCESS;
903 DEBUGFUNC("e1000_reset_hw_82543");
905 DEBUGOUT("Masking off all interrupts\n");
906 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
908 E1000_WRITE_REG(hw, E1000_RCTL, 0);
909 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
910 E1000_WRITE_FLUSH(hw);
912 e1000_set_tbi_sbp_82543(hw, FALSE);
915 * Delay to allow any outstanding PCI transactions to complete before
916 * resetting the device
920 ctrl = E1000_READ_REG(hw, E1000_CTRL);
922 DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n");
923 if (hw->mac.type == e1000_82543) {
924 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
927 * The 82544 can't ACK the 64-bit write when issuing the
928 * reset, so use IO-mapping as a workaround.
930 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
934 * After MAC reset, force reload of NVM to restore power-on
935 * settings to device.
937 hw->nvm.ops.reload(hw);
940 /* Masking off and clearing any pending interrupts */
941 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
942 icr = E1000_READ_REG(hw, E1000_ICR);
948 * e1000_init_hw_82543 - Initialize hardware
949 * @hw: pointer to the HW structure
951 * This inits the hardware readying it for operation.
953 static s32 e1000_init_hw_82543(struct e1000_hw *hw)
955 struct e1000_mac_info *mac = &hw->mac;
956 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
961 DEBUGFUNC("e1000_init_hw_82543");
963 /* Disabling VLAN filtering */
964 E1000_WRITE_REG(hw, E1000_VET, 0);
965 mac->ops.clear_vfta(hw);
967 /* Setup the receive address. */
968 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
970 /* Zero out the Multicast HASH table */
971 DEBUGOUT("Zeroing the MTA\n");
972 for (i = 0; i < mac->mta_reg_count; i++) {
973 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
974 E1000_WRITE_FLUSH(hw);
978 * Set the PCI priority bit correctly in the CTRL register. This
979 * determines if the adapter gives priority to receives, or if it
980 * gives equal priority to transmits and receives.
982 if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) {
983 ctrl = E1000_READ_REG(hw, E1000_CTRL);
984 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
987 e1000_pcix_mmrbc_workaround_generic(hw);
989 /* Setup link and flow control */
990 ret_val = mac->ops.setup_link(hw);
993 * Clear all of the statistics registers (clear on read). It is
994 * important that we do this after we have tried to establish link
995 * because the symbol error count will increment wildly if there
998 e1000_clear_hw_cntrs_82543(hw);
1004 * e1000_setup_link_82543 - Setup flow control and link settings
1005 * @hw: pointer to the HW structure
1007 * Read the EEPROM to determine the initial polarity value and write the
1008 * extended device control register with the information before calling
1009 * the generic setup link function, which does the following:
1010 * Determines which flow control settings to use, then configures flow
1011 * control. Calls the appropriate media-specific link configuration
1012 * function. Assuming the adapter has a valid link partner, a valid link
1013 * should be established. Assumes the hardware has previously been reset
1014 * and the transmitter and receiver are not enabled.
1016 static s32 e1000_setup_link_82543(struct e1000_hw *hw)
1022 DEBUGFUNC("e1000_setup_link_82543");
1025 * Take the 4 bits from NVM word 0xF that determine the initial
1026 * polarity value for the SW controlled pins, and setup the
1027 * Extended Device Control reg with that info.
1028 * This is needed because one of the SW controlled pins is used for
1029 * signal detection. So this should be done before phy setup.
1031 if (hw->mac.type == e1000_82543) {
1032 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1034 DEBUGOUT("NVM Read Error\n");
1035 ret_val = -E1000_ERR_NVM;
1038 ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) <<
1039 NVM_SWDPIO_EXT_SHIFT);
1040 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1043 ret_val = e1000_setup_link_generic(hw);
1050 * e1000_setup_copper_link_82543 - Configure copper link settings
1051 * @hw: pointer to the HW structure
1053 * Configures the link for auto-neg or forced speed and duplex. Then we check
1054 * for link, once link is established calls to configure collision distance
1055 * and flow control are called.
1057 static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw)
1063 DEBUGFUNC("e1000_setup_copper_link_82543");
1065 ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU;
1067 * With 82543, we need to force speed and duplex on the MAC
1068 * equal to what the PHY speed and duplex configuration is.
1069 * In addition, we need to perform a hardware reset on the
1070 * PHY to take it out of reset.
1072 if (hw->mac.type == e1000_82543) {
1073 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1074 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1075 ret_val = hw->phy.ops.reset(hw);
1078 hw->phy.reset_disable = FALSE;
1080 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1081 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1084 /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */
1085 ret_val = e1000_copper_link_setup_m88(hw);
1089 if (hw->mac.autoneg) {
1091 * Setup autoneg and flow control advertisement and perform
1094 ret_val = e1000_copper_link_autoneg(hw);
1099 * PHY will be set to 10H, 10F, 100H or 100F
1100 * depending on user settings.
1102 DEBUGOUT("Forcing Speed and Duplex\n");
1103 ret_val = e1000_phy_force_speed_duplex_82543(hw);
1105 DEBUGOUT("Error Forcing Speed and Duplex\n");
1111 * Check link status. Wait up to 100 microseconds for link to become
1114 ret_val = e1000_phy_has_link_generic(hw,
1115 COPPER_LINK_UP_LIMIT,
1123 DEBUGOUT("Valid link established!!!\n");
1124 /* Config the MAC and PHY after link is up */
1125 if (hw->mac.type == e1000_82544) {
1126 e1000_config_collision_dist_generic(hw);
1128 ret_val = e1000_config_mac_to_phy_82543(hw);
1132 ret_val = e1000_config_fc_after_link_up_generic(hw);
1134 DEBUGOUT("Unable to establish link!!!\n");
1142 * e1000_setup_fiber_link_82543 - Setup link for fiber
1143 * @hw: pointer to the HW structure
1145 * Configures collision distance and flow control for fiber links. Upon
1146 * successful setup, poll for link.
1148 static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw)
1153 DEBUGFUNC("e1000_setup_fiber_link_82543");
1155 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1157 /* Take the link out of reset */
1158 ctrl &= ~E1000_CTRL_LRST;
1160 e1000_config_collision_dist_generic(hw);
1162 ret_val = e1000_commit_fc_settings_generic(hw);
1166 DEBUGOUT("Auto-negotiation enabled\n");
1168 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1169 E1000_WRITE_FLUSH(hw);
1173 * For these adapters, the SW definable pin 1 is cleared when the
1174 * optics detect a signal. If we have a signal, then poll for a
1175 * "Link-Up" indication.
1177 if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1178 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1180 DEBUGOUT("No signal detected\n");
1188 * e1000_check_for_copper_link_82543 - Check for link (Copper)
1189 * @hw: pointer to the HW structure
1191 * Checks the phy for link, if link exists, do the following:
1192 * - check for downshift
1193 * - do polarity workaround (if necessary)
1194 * - configure collision distance
1195 * - configure flow control after link up
1196 * - configure tbi compatibility
1198 static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw)
1200 struct e1000_mac_info *mac = &hw->mac;
1206 DEBUGFUNC("e1000_check_for_copper_link_82543");
1208 if (!mac->get_link_status) {
1209 ret_val = E1000_SUCCESS;
1213 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1218 goto out; /* No link detected */
1220 mac->get_link_status = FALSE;
1222 e1000_check_downshift_generic(hw);
1225 * If we are forcing speed/duplex, then we can return since
1226 * we have already determined whether we have link or not.
1228 if (!mac->autoneg) {
1230 * If speed and duplex are forced to 10H or 10F, then we will
1231 * implement the polarity reversal workaround. We disable
1232 * interrupts first, and upon returning, place the devices
1233 * interrupt state to its previous value except for the link
1234 * status change interrupt which will happened due to the
1235 * execution of this workaround.
1237 if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) {
1238 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
1239 ret_val = e1000_polarity_reversal_workaround_82543(hw);
1240 icr = E1000_READ_REG(hw, E1000_ICR);
1241 E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC));
1242 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
1245 ret_val = -E1000_ERR_CONFIG;
1250 * We have a M88E1000 PHY and Auto-Neg is enabled. If we
1251 * have Si on board that is 82544 or newer, Auto
1252 * Speed Detection takes care of MAC speed/duplex
1253 * configuration. So we only need to configure Collision
1254 * Distance in the MAC. Otherwise, we need to force
1255 * speed/duplex on the MAC to the current PHY speed/duplex
1258 if (mac->type == e1000_82544)
1259 e1000_config_collision_dist_generic(hw);
1261 ret_val = e1000_config_mac_to_phy_82543(hw);
1263 DEBUGOUT("Error configuring MAC to PHY settings\n");
1269 * Configure Flow Control now that Auto-Neg has completed.
1270 * First, we need to restore the desired flow control
1271 * settings because we may have had to re-autoneg with a
1272 * different link partner.
1274 ret_val = e1000_config_fc_after_link_up_generic(hw);
1276 DEBUGOUT("Error configuring flow control\n");
1280 * At this point we know that we are on copper and we have
1281 * auto-negotiated link. These are conditions for checking the link
1282 * partner capability register. We use the link speed to determine if
1283 * TBI compatibility needs to be turned on or off. If the link is not
1284 * at gigabit speed, then TBI compatibility is not needed. If we are
1285 * at gigabit speed, we turn on TBI compatibility.
1287 if (e1000_tbi_compatibility_enabled_82543(hw)) {
1288 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1290 DEBUGOUT("Error getting link speed and duplex\n");
1293 if (speed != SPEED_1000) {
1295 * If link speed is not set to gigabit speed,
1296 * we do not need to enable TBI compatibility.
1298 if (e1000_tbi_sbp_enabled_82543(hw)) {
1300 * If we previously were in the mode,
1303 e1000_set_tbi_sbp_82543(hw, FALSE);
1304 rctl = E1000_READ_REG(hw, E1000_RCTL);
1305 rctl &= ~E1000_RCTL_SBP;
1306 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1310 * If TBI compatibility is was previously off,
1311 * turn it on. For compatibility with a TBI link
1312 * partner, we will store bad packets. Some
1313 * frames have an additional byte on the end and
1314 * will look like CRC errors to to the hardware.
1316 if (!e1000_tbi_sbp_enabled_82543(hw)) {
1317 e1000_set_tbi_sbp_82543(hw, TRUE);
1318 rctl = E1000_READ_REG(hw, E1000_RCTL);
1319 rctl |= E1000_RCTL_SBP;
1320 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1329 * e1000_check_for_fiber_link_82543 - Check for link (Fiber)
1330 * @hw: pointer to the HW structure
1332 * Checks for link up on the hardware. If link is not up and we have
1333 * a signal, then we need to force link up.
1335 static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw)
1337 struct e1000_mac_info *mac = &hw->mac;
1338 u32 rxcw, ctrl, status;
1339 s32 ret_val = E1000_SUCCESS;
1341 DEBUGFUNC("e1000_check_for_fiber_link_82543");
1343 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1344 status = E1000_READ_REG(hw, E1000_STATUS);
1345 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1348 * If we don't have link (auto-negotiation failed or link partner
1349 * cannot auto-negotiate), the cable is plugged in (we have signal),
1350 * and our link partner is not trying to auto-negotiate with us (we
1351 * are receiving idles or data), we need to force link up. We also
1352 * need to give auto-negotiation time to complete, in case the cable
1353 * was just plugged in. The autoneg_failed flag does this.
1355 /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */
1356 if ((!(ctrl & E1000_CTRL_SWDPIN1)) &&
1357 (!(status & E1000_STATUS_LU)) &&
1358 (!(rxcw & E1000_RXCW_C))) {
1359 if (mac->autoneg_failed == 0) {
1360 mac->autoneg_failed = 1;
1364 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
1366 /* Disable auto-negotiation in the TXCW register */
1367 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1369 /* Force link-up and also force full-duplex. */
1370 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1371 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1372 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1374 /* Configure Flow Control after forcing link up. */
1375 ret_val = e1000_config_fc_after_link_up_generic(hw);
1377 DEBUGOUT("Error configuring flow control\n");
1380 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
1382 * If we are forcing link and we are receiving /C/ ordered
1383 * sets, re-enable auto-negotiation in the TXCW register
1384 * and disable forced link in the Device Control register
1385 * in an attempt to auto-negotiate with our link partner.
1387 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
1388 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1389 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
1391 mac->serdes_has_link = TRUE;
1399 * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings
1400 * @hw: pointer to the HW structure
1402 * For the 82543 silicon, we need to set the MAC to match the settings
1403 * of the PHY, even if the PHY is auto-negotiating.
1405 static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw)
1408 s32 ret_val = E1000_SUCCESS;
1411 DEBUGFUNC("e1000_config_mac_to_phy_82543");
1413 if (!(hw->phy.ops.read_reg))
1416 /* Set the bits to force speed and duplex */
1417 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1418 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1419 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1422 * Set up duplex in the Device Control and Transmit Control
1423 * registers depending on negotiated values.
1425 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1429 ctrl &= ~E1000_CTRL_FD;
1430 if (phy_data & M88E1000_PSSR_DPLX)
1431 ctrl |= E1000_CTRL_FD;
1433 e1000_config_collision_dist_generic(hw);
1436 * Set up speed in the Device Control register depending on
1437 * negotiated values.
1439 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1440 ctrl |= E1000_CTRL_SPD_1000;
1441 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1442 ctrl |= E1000_CTRL_SPD_100;
1444 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1451 * e1000_write_vfta_82543 - Write value to VLAN filter table
1452 * @hw: pointer to the HW structure
1453 * @offset: the 32-bit offset in which to write the value to.
1454 * @value: the 32-bit value to write at location offset.
1456 * This writes a 32-bit value to a 32-bit offset in the VLAN filter
1459 static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value)
1463 DEBUGFUNC("e1000_write_vfta_82543");
1465 if ((hw->mac.type == e1000_82544) && (offset & 1)) {
1466 temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1);
1467 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
1468 E1000_WRITE_FLUSH(hw);
1469 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp);
1470 E1000_WRITE_FLUSH(hw);
1472 e1000_write_vfta_generic(hw, offset, value);
1477 * e1000_led_on_82543 - Turn on SW controllable LED
1478 * @hw: pointer to the HW structure
1480 * Turns the SW defined LED on.
1482 static s32 e1000_led_on_82543(struct e1000_hw *hw)
1484 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1486 DEBUGFUNC("e1000_led_on_82543");
1488 if (hw->mac.type == e1000_82544 &&
1489 hw->phy.media_type == e1000_media_type_copper) {
1490 /* Clear SW-definable Pin 0 to turn on the LED */
1491 ctrl &= ~E1000_CTRL_SWDPIN0;
1492 ctrl |= E1000_CTRL_SWDPIO0;
1494 /* Fiber 82544 and all 82543 use this method */
1495 ctrl |= E1000_CTRL_SWDPIN0;
1496 ctrl |= E1000_CTRL_SWDPIO0;
1498 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1500 return E1000_SUCCESS;
1504 * e1000_led_off_82543 - Turn off SW controllable LED
1505 * @hw: pointer to the HW structure
1507 * Turns the SW defined LED off.
1509 static s32 e1000_led_off_82543(struct e1000_hw *hw)
1511 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1513 DEBUGFUNC("e1000_led_off_82543");
1515 if (hw->mac.type == e1000_82544 &&
1516 hw->phy.media_type == e1000_media_type_copper) {
1517 /* Set SW-definable Pin 0 to turn off the LED */
1518 ctrl |= E1000_CTRL_SWDPIN0;
1519 ctrl |= E1000_CTRL_SWDPIO0;
1521 ctrl &= ~E1000_CTRL_SWDPIN0;
1522 ctrl |= E1000_CTRL_SWDPIO0;
1524 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1526 return E1000_SUCCESS;
1530 * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters
1531 * @hw: pointer to the HW structure
1533 * Clears the hardware counters by reading the counter registers.
1535 static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw)
1537 DEBUGFUNC("e1000_clear_hw_cntrs_82543");
1539 e1000_clear_hw_cntrs_base_generic(hw);
1541 E1000_READ_REG(hw, E1000_PRC64);
1542 E1000_READ_REG(hw, E1000_PRC127);
1543 E1000_READ_REG(hw, E1000_PRC255);
1544 E1000_READ_REG(hw, E1000_PRC511);
1545 E1000_READ_REG(hw, E1000_PRC1023);
1546 E1000_READ_REG(hw, E1000_PRC1522);
1547 E1000_READ_REG(hw, E1000_PTC64);
1548 E1000_READ_REG(hw, E1000_PTC127);
1549 E1000_READ_REG(hw, E1000_PTC255);
1550 E1000_READ_REG(hw, E1000_PTC511);
1551 E1000_READ_REG(hw, E1000_PTC1023);
1552 E1000_READ_REG(hw, E1000_PTC1522);
1554 E1000_READ_REG(hw, E1000_ALGNERRC);
1555 E1000_READ_REG(hw, E1000_RXERRC);
1556 E1000_READ_REG(hw, E1000_TNCRS);
1557 E1000_READ_REG(hw, E1000_CEXTERR);
1558 E1000_READ_REG(hw, E1000_TSCTC);
1559 E1000_READ_REG(hw, E1000_TSCTFC);