1 /******************************************************************************
3 Copyright (c) 2001-2009, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ******************************************************************************/
35 #include "e1000_api.h"
37 #ifdef NO_82542_SUPPORT
38 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw);
40 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
41 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
44 * e1000_init_mac_ops_generic - Initialize MAC function pointers
45 * @hw: pointer to the HW structure
47 * Setups up the function pointers to no-op functions
49 void e1000_init_mac_ops_generic(struct e1000_hw *hw)
51 struct e1000_mac_info *mac = &hw->mac;
52 DEBUGFUNC("e1000_init_mac_ops_generic");
55 mac->ops.init_params = e1000_null_ops_generic;
56 mac->ops.init_hw = e1000_null_ops_generic;
57 mac->ops.reset_hw = e1000_null_ops_generic;
58 mac->ops.setup_physical_interface = e1000_null_ops_generic;
59 mac->ops.get_bus_info = e1000_null_ops_generic;
60 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;
61 mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
62 mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
63 mac->ops.clear_hw_cntrs = e1000_null_mac_generic;
65 mac->ops.cleanup_led = e1000_null_ops_generic;
66 mac->ops.setup_led = e1000_null_ops_generic;
67 mac->ops.blink_led = e1000_null_ops_generic;
68 mac->ops.led_on = e1000_null_ops_generic;
69 mac->ops.led_off = e1000_null_ops_generic;
71 mac->ops.setup_link = e1000_null_ops_generic;
72 mac->ops.get_link_up_info = e1000_null_link_info;
73 mac->ops.check_for_link = e1000_null_ops_generic;
74 mac->ops.wait_autoneg = e1000_wait_autoneg_generic;
76 mac->ops.check_mng_mode = e1000_null_mng_mode;
77 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic;
78 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic;
79 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic;
81 mac->ops.update_mc_addr_list = e1000_null_update_mc;
82 mac->ops.clear_vfta = e1000_null_mac_generic;
83 mac->ops.write_vfta = e1000_null_write_vfta;
84 mac->ops.rar_set = e1000_rar_set_generic;
85 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
89 * e1000_null_ops_generic - No-op function, returns 0
90 * @hw: pointer to the HW structure
92 s32 e1000_null_ops_generic(struct e1000_hw *hw)
94 DEBUGFUNC("e1000_null_ops_generic");
99 * e1000_null_mac_generic - No-op function, return void
100 * @hw: pointer to the HW structure
102 void e1000_null_mac_generic(struct e1000_hw *hw)
104 DEBUGFUNC("e1000_null_mac_generic");
109 * e1000_null_link_info - No-op function, return 0
110 * @hw: pointer to the HW structure
112 s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d)
114 DEBUGFUNC("e1000_null_link_info");
115 return E1000_SUCCESS;
119 * e1000_null_mng_mode - No-op function, return FALSE
120 * @hw: pointer to the HW structure
122 bool e1000_null_mng_mode(struct e1000_hw *hw)
124 DEBUGFUNC("e1000_null_mng_mode");
129 * e1000_null_update_mc - No-op function, return void
130 * @hw: pointer to the HW structure
132 void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a)
134 DEBUGFUNC("e1000_null_update_mc");
139 * e1000_null_write_vfta - No-op function, return void
140 * @hw: pointer to the HW structure
142 void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b)
144 DEBUGFUNC("e1000_null_write_vfta");
149 * e1000_null_rar_set - No-op function, return void
150 * @hw: pointer to the HW structure
152 void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a)
154 DEBUGFUNC("e1000_null_rar_set");
159 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information
160 * @hw: pointer to the HW structure
162 * Determines and stores the system bus information for a particular
163 * network interface. The following bus information is determined and stored:
164 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
166 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
168 struct e1000_mac_info *mac = &hw->mac;
169 struct e1000_bus_info *bus = &hw->bus;
170 u32 status = E1000_READ_REG(hw, E1000_STATUS);
171 s32 ret_val = E1000_SUCCESS;
173 DEBUGFUNC("e1000_get_bus_info_pci_generic");
176 bus->type = (status & E1000_STATUS_PCIX_MODE)
177 ? e1000_bus_type_pcix
178 : e1000_bus_type_pci;
181 if (bus->type == e1000_bus_type_pci) {
182 bus->speed = (status & E1000_STATUS_PCI66)
184 : e1000_bus_speed_33;
186 switch (status & E1000_STATUS_PCIX_SPEED) {
187 case E1000_STATUS_PCIX_SPEED_66:
188 bus->speed = e1000_bus_speed_66;
190 case E1000_STATUS_PCIX_SPEED_100:
191 bus->speed = e1000_bus_speed_100;
193 case E1000_STATUS_PCIX_SPEED_133:
194 bus->speed = e1000_bus_speed_133;
197 bus->speed = e1000_bus_speed_reserved;
203 bus->width = (status & E1000_STATUS_BUS64)
205 : e1000_bus_width_32;
207 /* Which PCI(-X) function? */
208 mac->ops.set_lan_id(hw);
214 * e1000_get_bus_info_pcie_generic - Get PCIe bus information
215 * @hw: pointer to the HW structure
217 * Determines and stores the system bus information for a particular
218 * network interface. The following bus information is determined and stored:
219 * bus speed, bus width, type (PCIe), and PCIe function.
221 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
223 struct e1000_mac_info *mac = &hw->mac;
224 struct e1000_bus_info *bus = &hw->bus;
226 u16 pcie_link_status;
228 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
230 bus->type = e1000_bus_type_pci_express;
232 ret_val = e1000_read_pcie_cap_reg(hw,
236 bus->width = e1000_bus_width_unknown;
237 bus->speed = e1000_bus_speed_unknown;
239 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) {
240 case PCIE_LINK_SPEED_2500:
241 bus->speed = e1000_bus_speed_2500;
243 case PCIE_LINK_SPEED_5000:
244 bus->speed = e1000_bus_speed_5000;
247 bus->speed = e1000_bus_speed_unknown;
251 bus->width = (enum e1000_bus_width)((pcie_link_status &
252 PCIE_LINK_WIDTH_MASK) >>
253 PCIE_LINK_WIDTH_SHIFT);
256 mac->ops.set_lan_id(hw);
258 return E1000_SUCCESS;
262 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
264 * @hw: pointer to the HW structure
266 * Determines the LAN function id by reading memory-mapped registers
267 * and swaps the port value if requested.
269 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
271 struct e1000_bus_info *bus = &hw->bus;
275 * The status register reports the correct function number
276 * for the device regardless of function swap state.
278 reg = E1000_READ_REG(hw, E1000_STATUS);
279 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
283 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices
284 * @hw: pointer to the HW structure
286 * Determines the LAN function id by reading PCI config space.
288 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
290 struct e1000_bus_info *bus = &hw->bus;
294 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
295 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
296 status = E1000_READ_REG(hw, E1000_STATUS);
297 bus->func = (status & E1000_STATUS_FUNC_MASK)
298 >> E1000_STATUS_FUNC_SHIFT;
305 * e1000_set_lan_id_single_port - Set LAN id for a single port device
306 * @hw: pointer to the HW structure
308 * Sets the LAN function id to zero for a single port device.
310 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
312 struct e1000_bus_info *bus = &hw->bus;
318 * e1000_clear_vfta_generic - Clear VLAN filter table
319 * @hw: pointer to the HW structure
321 * Clears the register array which contains the VLAN filter table by
322 * setting all the values to 0.
324 void e1000_clear_vfta_generic(struct e1000_hw *hw)
328 DEBUGFUNC("e1000_clear_vfta_generic");
330 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
331 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
332 E1000_WRITE_FLUSH(hw);
337 * e1000_write_vfta_generic - Write value to VLAN filter table
338 * @hw: pointer to the HW structure
339 * @offset: register offset in VLAN filter table
340 * @value: register value written to VLAN filter table
342 * Writes value at the given offset in the register array which stores
343 * the VLAN filter table.
345 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
347 DEBUGFUNC("e1000_write_vfta_generic");
349 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
350 E1000_WRITE_FLUSH(hw);
354 * e1000_init_rx_addrs_generic - Initialize receive address's
355 * @hw: pointer to the HW structure
356 * @rar_count: receive address registers
358 * Setups the receive address registers by setting the base receive address
359 * register to the devices MAC address and clearing all the other receive
360 * address registers to 0.
362 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
365 u8 mac_addr[ETH_ADDR_LEN] = {0};
367 DEBUGFUNC("e1000_init_rx_addrs_generic");
369 /* Setup the receive address */
370 DEBUGOUT("Programming MAC Address into RAR[0]\n");
372 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
374 /* Zero out the other (rar_entry_count - 1) receive addresses */
375 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
376 for (i = 1; i < rar_count; i++)
377 hw->mac.ops.rar_set(hw, mac_addr, i);
381 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
382 * @hw: pointer to the HW structure
384 * Checks the nvm for an alternate MAC address. An alternate MAC address
385 * can be setup by pre-boot software and must be treated like a permanent
386 * address and must override the actual permanent MAC address. If an
387 * alternate MAC address is found it is programmed into RAR0, replacing
388 * the permanent address that was installed into RAR0 by the Si on reset.
389 * This function will return SUCCESS unless it encounters an error while
390 * reading the EEPROM.
392 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
395 s32 ret_val = E1000_SUCCESS;
396 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
397 u8 alt_mac_addr[ETH_ADDR_LEN];
399 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
401 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
405 /* Check for LOM (vs. NIC) or one of two valid mezzanine cards */
406 if (!((nvm_data & NVM_COMPAT_LOM) ||
407 (hw->device_id == E1000_DEV_ID_82571EB_SERDES_DUAL) ||
408 (hw->device_id == E1000_DEV_ID_82571EB_SERDES_QUAD)))
411 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
412 &nvm_alt_mac_addr_offset);
414 DEBUGOUT("NVM Read Error\n");
418 if (nvm_alt_mac_addr_offset == 0xFFFF) {
419 /* There is no Alternate MAC Address */
423 if (hw->bus.func == E1000_FUNC_1)
424 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
425 if (hw->bus.func == E1000_FUNC_2)
426 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
428 if (hw->bus.func == E1000_FUNC_3)
429 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
430 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
431 offset = nvm_alt_mac_addr_offset + (i >> 1);
432 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
434 DEBUGOUT("NVM Read Error\n");
438 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
439 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
442 /* if multicast bit is set, the alternate address will not be used */
443 if (alt_mac_addr[0] & 0x01) {
444 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
449 * We have a valid alternate MAC address, and we want to treat it the
450 * same as the normal permanent MAC address stored by the HW into the
451 * RAR. Do this by mapping this address into RAR0.
453 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
460 * e1000_rar_set_generic - Set receive address register
461 * @hw: pointer to the HW structure
462 * @addr: pointer to the receive address
463 * @index: receive address array register
465 * Sets the receive address array register at index to the address passed
468 void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
470 u32 rar_low, rar_high;
472 DEBUGFUNC("e1000_rar_set_generic");
475 * HW expects these in little endian so we reverse the byte order
476 * from network order (big endian) to little endian
478 rar_low = ((u32) addr[0] |
479 ((u32) addr[1] << 8) |
480 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
482 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
484 /* If MAC address zero, no need to set the AV bit */
485 if (rar_low || rar_high)
486 rar_high |= E1000_RAH_AV;
489 * Some bridges will combine consecutive 32-bit writes into
490 * a single burst write, which will malfunction on some parts.
491 * The flushes avoid this.
493 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
494 E1000_WRITE_FLUSH(hw);
495 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
496 E1000_WRITE_FLUSH(hw);
500 * e1000_update_mc_addr_list_generic - Update Multicast addresses
501 * @hw: pointer to the HW structure
502 * @mc_addr_list: array of multicast addresses to program
503 * @mc_addr_count: number of multicast addresses to program
505 * Updates entire Multicast Table Array.
506 * The caller must have a packed mc_addr_list of multicast addresses.
508 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
509 u8 *mc_addr_list, u32 mc_addr_count)
511 u32 hash_value, hash_bit, hash_reg;
514 DEBUGFUNC("e1000_update_mc_addr_list_generic");
516 /* clear mta_shadow */
517 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
519 /* update mta_shadow from mc_addr_list */
520 for (i = 0; (u32) i < mc_addr_count; i++) {
521 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
523 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
524 hash_bit = hash_value & 0x1F;
526 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
527 mc_addr_list += (ETH_ADDR_LEN);
530 /* replace the entire MTA table */
531 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
532 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
533 E1000_WRITE_FLUSH(hw);
537 * e1000_hash_mc_addr_generic - Generate a multicast hash value
538 * @hw: pointer to the HW structure
539 * @mc_addr: pointer to a multicast address
541 * Generates a multicast address hash value which is used to determine
542 * the multicast filter table array address and new table value.
544 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
546 u32 hash_value, hash_mask;
549 DEBUGFUNC("e1000_hash_mc_addr_generic");
551 /* Register count multiplied by bits per register */
552 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
555 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
556 * where 0xFF would still fall within the hash mask.
558 while (hash_mask >> bit_shift != 0xFF)
562 * The portion of the address that is used for the hash table
563 * is determined by the mc_filter_type setting.
564 * The algorithm is such that there is a total of 8 bits of shifting.
565 * The bit_shift for a mc_filter_type of 0 represents the number of
566 * left-shifts where the MSB of mc_addr[5] would still fall within
567 * the hash_mask. Case 0 does this exactly. Since there are a total
568 * of 8 bits of shifting, then mc_addr[4] will shift right the
569 * remaining number of bits. Thus 8 - bit_shift. The rest of the
570 * cases are a variation of this algorithm...essentially raising the
571 * number of bits to shift mc_addr[5] left, while still keeping the
572 * 8-bit shifting total.
574 * For example, given the following Destination MAC Address and an
575 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
576 * we can see that the bit_shift for case 0 is 4. These are the hash
577 * values resulting from each mc_filter_type...
578 * [0] [1] [2] [3] [4] [5]
582 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
583 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
584 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
585 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
587 switch (hw->mac.mc_filter_type) {
602 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
603 (((u16) mc_addr[5]) << bit_shift)));
609 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
610 * @hw: pointer to the HW structure
612 * In certain situations, a system BIOS may report that the PCIx maximum
613 * memory read byte count (MMRBC) value is higher than than the actual
614 * value. We check the PCIx command register with the current PCIx status
617 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
621 u16 pcix_stat_hi_word;
624 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic");
626 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
627 if (hw->bus.type != e1000_bus_type_pcix)
630 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
631 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
632 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
633 PCIX_COMMAND_MMRBC_SHIFT;
634 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
635 PCIX_STATUS_HI_MMRBC_SHIFT;
636 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
637 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
638 if (cmd_mmrbc > stat_mmrbc) {
639 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
640 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
641 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
646 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
647 * @hw: pointer to the HW structure
649 * Clears the base hardware counters by reading the counter registers.
651 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
653 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
655 E1000_READ_REG(hw, E1000_CRCERRS);
656 E1000_READ_REG(hw, E1000_SYMERRS);
657 E1000_READ_REG(hw, E1000_MPC);
658 E1000_READ_REG(hw, E1000_SCC);
659 E1000_READ_REG(hw, E1000_ECOL);
660 E1000_READ_REG(hw, E1000_MCC);
661 E1000_READ_REG(hw, E1000_LATECOL);
662 E1000_READ_REG(hw, E1000_COLC);
663 E1000_READ_REG(hw, E1000_DC);
664 E1000_READ_REG(hw, E1000_SEC);
665 E1000_READ_REG(hw, E1000_RLEC);
666 E1000_READ_REG(hw, E1000_XONRXC);
667 E1000_READ_REG(hw, E1000_XONTXC);
668 E1000_READ_REG(hw, E1000_XOFFRXC);
669 E1000_READ_REG(hw, E1000_XOFFTXC);
670 E1000_READ_REG(hw, E1000_FCRUC);
671 E1000_READ_REG(hw, E1000_GPRC);
672 E1000_READ_REG(hw, E1000_BPRC);
673 E1000_READ_REG(hw, E1000_MPRC);
674 E1000_READ_REG(hw, E1000_GPTC);
675 E1000_READ_REG(hw, E1000_GORCL);
676 E1000_READ_REG(hw, E1000_GORCH);
677 E1000_READ_REG(hw, E1000_GOTCL);
678 E1000_READ_REG(hw, E1000_GOTCH);
679 E1000_READ_REG(hw, E1000_RNBC);
680 E1000_READ_REG(hw, E1000_RUC);
681 E1000_READ_REG(hw, E1000_RFC);
682 E1000_READ_REG(hw, E1000_ROC);
683 E1000_READ_REG(hw, E1000_RJC);
684 E1000_READ_REG(hw, E1000_TORL);
685 E1000_READ_REG(hw, E1000_TORH);
686 E1000_READ_REG(hw, E1000_TOTL);
687 E1000_READ_REG(hw, E1000_TOTH);
688 E1000_READ_REG(hw, E1000_TPR);
689 E1000_READ_REG(hw, E1000_TPT);
690 E1000_READ_REG(hw, E1000_MPTC);
691 E1000_READ_REG(hw, E1000_BPTC);
695 * e1000_check_for_copper_link_generic - Check for link (Copper)
696 * @hw: pointer to the HW structure
698 * Checks to see of the link status of the hardware has changed. If a
699 * change in link status has been detected, then we read the PHY registers
700 * to get the current speed/duplex if link exists.
702 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
704 struct e1000_mac_info *mac = &hw->mac;
708 DEBUGFUNC("e1000_check_for_copper_link");
711 * We only want to go out to the PHY registers to see if Auto-Neg
712 * has completed and/or if our link status has changed. The
713 * get_link_status flag is set upon receiving a Link Status
714 * Change or Rx Sequence Error interrupt.
716 if (!mac->get_link_status) {
717 ret_val = E1000_SUCCESS;
722 * First we want to see if the MII Status Register reports
723 * link. If so, then we want to get the current speed/duplex
726 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
731 goto out; /* No link detected */
733 mac->get_link_status = FALSE;
736 * Check if there was DownShift, must be checked
737 * immediately after link-up
739 e1000_check_downshift_generic(hw);
742 * If we are forcing speed/duplex, then we simply return since
743 * we have already determined whether we have link or not.
746 ret_val = -E1000_ERR_CONFIG;
751 * Auto-Neg is enabled. Auto Speed Detection takes care
752 * of MAC speed/duplex configuration. So we only need to
753 * configure Collision Distance in the MAC.
755 mac->ops.config_collision_dist(hw);
758 * Configure Flow Control now that Auto-Neg has completed.
759 * First, we need to restore the desired flow control
760 * settings because we may have had to re-autoneg with a
761 * different link partner.
763 ret_val = e1000_config_fc_after_link_up_generic(hw);
765 DEBUGOUT("Error configuring flow control\n");
772 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
773 * @hw: pointer to the HW structure
775 * Checks for link up on the hardware. If link is not up and we have
776 * a signal, then we need to force link up.
778 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
780 struct e1000_mac_info *mac = &hw->mac;
784 s32 ret_val = E1000_SUCCESS;
786 DEBUGFUNC("e1000_check_for_fiber_link_generic");
788 ctrl = E1000_READ_REG(hw, E1000_CTRL);
789 status = E1000_READ_REG(hw, E1000_STATUS);
790 rxcw = E1000_READ_REG(hw, E1000_RXCW);
793 * If we don't have link (auto-negotiation failed or link partner
794 * cannot auto-negotiate), the cable is plugged in (we have signal),
795 * and our link partner is not trying to auto-negotiate with us (we
796 * are receiving idles or data), we need to force link up. We also
797 * need to give auto-negotiation time to complete, in case the cable
798 * was just plugged in. The autoneg_failed flag does this.
800 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
801 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
802 (!(rxcw & E1000_RXCW_C))) {
803 if (mac->autoneg_failed == 0) {
804 mac->autoneg_failed = 1;
807 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
809 /* Disable auto-negotiation in the TXCW register */
810 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
812 /* Force link-up and also force full-duplex. */
813 ctrl = E1000_READ_REG(hw, E1000_CTRL);
814 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
815 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
817 /* Configure Flow Control after forcing link up. */
818 ret_val = e1000_config_fc_after_link_up_generic(hw);
820 DEBUGOUT("Error configuring flow control\n");
823 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
825 * If we are forcing link and we are receiving /C/ ordered
826 * sets, re-enable auto-negotiation in the TXCW register
827 * and disable forced link in the Device Control register
828 * in an attempt to auto-negotiate with our link partner.
830 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
831 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
832 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
834 mac->serdes_has_link = TRUE;
842 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
843 * @hw: pointer to the HW structure
845 * Checks for link up on the hardware. If link is not up and we have
846 * a signal, then we need to force link up.
848 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
850 struct e1000_mac_info *mac = &hw->mac;
854 s32 ret_val = E1000_SUCCESS;
856 DEBUGFUNC("e1000_check_for_serdes_link_generic");
858 ctrl = E1000_READ_REG(hw, E1000_CTRL);
859 status = E1000_READ_REG(hw, E1000_STATUS);
860 rxcw = E1000_READ_REG(hw, E1000_RXCW);
863 * If we don't have link (auto-negotiation failed or link partner
864 * cannot auto-negotiate), and our link partner is not trying to
865 * auto-negotiate with us (we are receiving idles or data),
866 * we need to force link up. We also need to give auto-negotiation
869 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
870 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
871 if (mac->autoneg_failed == 0) {
872 mac->autoneg_failed = 1;
875 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
877 /* Disable auto-negotiation in the TXCW register */
878 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
880 /* Force link-up and also force full-duplex. */
881 ctrl = E1000_READ_REG(hw, E1000_CTRL);
882 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
883 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
885 /* Configure Flow Control after forcing link up. */
886 ret_val = e1000_config_fc_after_link_up_generic(hw);
888 DEBUGOUT("Error configuring flow control\n");
891 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
893 * If we are forcing link and we are receiving /C/ ordered
894 * sets, re-enable auto-negotiation in the TXCW register
895 * and disable forced link in the Device Control register
896 * in an attempt to auto-negotiate with our link partner.
898 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
899 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
900 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
902 mac->serdes_has_link = TRUE;
903 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
905 * If we force link for non-auto-negotiation switch, check
906 * link status based on MAC synchronization for internal
909 /* SYNCH bit and IV bit are sticky. */
911 rxcw = E1000_READ_REG(hw, E1000_RXCW);
912 if (rxcw & E1000_RXCW_SYNCH) {
913 if (!(rxcw & E1000_RXCW_IV)) {
914 mac->serdes_has_link = TRUE;
915 DEBUGOUT("SERDES: Link up - forced.\n");
918 mac->serdes_has_link = FALSE;
919 DEBUGOUT("SERDES: Link down - force failed.\n");
923 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
924 status = E1000_READ_REG(hw, E1000_STATUS);
925 if (status & E1000_STATUS_LU) {
926 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
928 rxcw = E1000_READ_REG(hw, E1000_RXCW);
929 if (rxcw & E1000_RXCW_SYNCH) {
930 if (!(rxcw & E1000_RXCW_IV)) {
931 mac->serdes_has_link = TRUE;
932 DEBUGOUT("SERDES: Link up - autoneg "
933 "completed sucessfully.\n");
935 mac->serdes_has_link = FALSE;
936 DEBUGOUT("SERDES: Link down - invalid"
937 "codewords detected in autoneg.\n");
940 mac->serdes_has_link = FALSE;
941 DEBUGOUT("SERDES: Link down - no sync.\n");
944 mac->serdes_has_link = FALSE;
945 DEBUGOUT("SERDES: Link down - autoneg failed\n");
954 * e1000_setup_link_generic - Setup flow control and link settings
955 * @hw: pointer to the HW structure
957 * Determines which flow control settings to use, then configures flow
958 * control. Calls the appropriate media-specific link configuration
959 * function. Assuming the adapter has a valid link partner, a valid link
960 * should be established. Assumes the hardware has previously been reset
961 * and the transmitter and receiver are not enabled.
963 s32 e1000_setup_link_generic(struct e1000_hw *hw)
965 s32 ret_val = E1000_SUCCESS;
967 DEBUGFUNC("e1000_setup_link_generic");
970 * In the case of the phy reset being blocked, we already have a link.
971 * We do not need to set it up again.
973 if (e1000_check_reset_block(hw))
977 * If requested flow control is set to default, set flow control
978 * based on the EEPROM flow control settings.
980 if (hw->fc.requested_mode == e1000_fc_default) {
981 ret_val = e1000_set_default_fc_generic(hw);
987 * Save off the requested flow control mode for use later. Depending
988 * on the link partner's capabilities, we may or may not use this mode.
990 hw->fc.current_mode = hw->fc.requested_mode;
992 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
993 hw->fc.current_mode);
995 /* Call the necessary media_type subroutine to configure the link. */
996 ret_val = hw->mac.ops.setup_physical_interface(hw);
1001 * Initialize the flow control address, type, and PAUSE timer
1002 * registers to their default values. This is done even if flow
1003 * control is disabled, because it does not hurt anything to
1004 * initialize these registers.
1006 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1007 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
1008 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1009 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
1011 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
1013 ret_val = e1000_set_fc_watermarks_generic(hw);
1020 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1021 * @hw: pointer to the HW structure
1023 * Configures collision distance and flow control for fiber and serdes
1024 * links. Upon successful setup, poll for link.
1026 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1028 struct e1000_mac_info *mac = &hw->mac;
1030 s32 ret_val = E1000_SUCCESS;
1032 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1034 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1036 /* Take the link out of reset */
1037 ctrl &= ~E1000_CTRL_LRST;
1039 mac->ops.config_collision_dist(hw);
1041 ret_val = e1000_commit_fc_settings_generic(hw);
1046 * Since auto-negotiation is enabled, take the link out of reset (the
1047 * link will be in reset, because we previously reset the chip). This
1048 * will restart auto-negotiation. If auto-negotiation is successful
1049 * then the link-up status bit will be set and the flow control enable
1050 * bits (RFCE and TFCE) will be set according to their negotiated value.
1052 DEBUGOUT("Auto-negotiation enabled\n");
1054 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1055 E1000_WRITE_FLUSH(hw);
1059 * For these adapters, the SW definable pin 1 is set when the optics
1060 * detect a signal. If we have a signal, then poll for a "Link-Up"
1063 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1064 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1065 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1067 DEBUGOUT("No signal detected\n");
1075 * e1000_config_collision_dist_generic - Configure collision distance
1076 * @hw: pointer to the HW structure
1078 * Configures the collision distance to the default value and is used
1079 * during link setup.
1081 void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1085 DEBUGFUNC("e1000_config_collision_dist_generic");
1087 tctl = E1000_READ_REG(hw, E1000_TCTL);
1089 tctl &= ~E1000_TCTL_COLD;
1090 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1092 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1093 E1000_WRITE_FLUSH(hw);
1097 * e1000_poll_fiber_serdes_link_generic - Poll for link up
1098 * @hw: pointer to the HW structure
1100 * Polls for link up by reading the status register, if link fails to come
1101 * up with auto-negotiation, then the link is forced if a signal is detected.
1103 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1105 struct e1000_mac_info *mac = &hw->mac;
1107 s32 ret_val = E1000_SUCCESS;
1109 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
1112 * If we have a signal (the cable is plugged in, or assumed TRUE for
1113 * serdes media) then poll for a "Link-Up" indication in the Device
1114 * Status Register. Time-out if a link isn't seen in 500 milliseconds
1115 * seconds (Auto-negotiation should complete in less than 500
1116 * milliseconds even if the other end is doing it in SW).
1118 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1120 status = E1000_READ_REG(hw, E1000_STATUS);
1121 if (status & E1000_STATUS_LU)
1124 if (i == FIBER_LINK_UP_LIMIT) {
1125 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1126 mac->autoneg_failed = 1;
1128 * AutoNeg failed to achieve a link, so we'll call
1129 * mac->check_for_link. This routine will force the
1130 * link up if we detect a signal. This will allow us to
1131 * communicate with non-autonegotiating link partners.
1133 ret_val = mac->ops.check_for_link(hw);
1135 DEBUGOUT("Error while checking for link\n");
1138 mac->autoneg_failed = 0;
1140 mac->autoneg_failed = 0;
1141 DEBUGOUT("Valid Link Found\n");
1149 * e1000_commit_fc_settings_generic - Configure flow control
1150 * @hw: pointer to the HW structure
1152 * Write the flow control settings to the Transmit Config Word Register (TXCW)
1153 * base on the flow control settings in e1000_mac_info.
1155 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1157 struct e1000_mac_info *mac = &hw->mac;
1159 s32 ret_val = E1000_SUCCESS;
1161 DEBUGFUNC("e1000_commit_fc_settings_generic");
1164 * Check for a software override of the flow control settings, and
1165 * setup the device accordingly. If auto-negotiation is enabled, then
1166 * software will have to set the "PAUSE" bits to the correct value in
1167 * the Transmit Config Word Register (TXCW) and re-start auto-
1168 * negotiation. However, if auto-negotiation is disabled, then
1169 * software will have to manually configure the two flow control enable
1170 * bits in the CTRL register.
1172 * The possible values of the "fc" parameter are:
1173 * 0: Flow control is completely disabled
1174 * 1: Rx flow control is enabled (we can receive pause frames,
1175 * but not send pause frames).
1176 * 2: Tx flow control is enabled (we can send pause frames but we
1177 * do not support receiving pause frames).
1178 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1180 switch (hw->fc.current_mode) {
1182 /* Flow control completely disabled by a software over-ride. */
1183 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1185 case e1000_fc_rx_pause:
1187 * Rx Flow control is enabled and Tx Flow control is disabled
1188 * by a software over-ride. Since there really isn't a way to
1189 * advertise that we are capable of Rx Pause ONLY, we will
1190 * advertise that we support both symmetric and asymmetric Rx
1191 * PAUSE. Later, we will disable the adapter's ability to send
1194 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1196 case e1000_fc_tx_pause:
1198 * Tx Flow control is enabled, and Rx Flow control is disabled,
1199 * by a software over-ride.
1201 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1205 * Flow control (both Rx and Tx) is enabled by a software
1208 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1211 DEBUGOUT("Flow control param set incorrectly\n");
1212 ret_val = -E1000_ERR_CONFIG;
1217 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1225 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1226 * @hw: pointer to the HW structure
1228 * Sets the flow control high/low threshold (watermark) registers. If
1229 * flow control XON frame transmission is enabled, then set XON frame
1230 * transmission as well.
1232 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1234 u32 fcrtl = 0, fcrth = 0;
1236 DEBUGFUNC("e1000_set_fc_watermarks_generic");
1239 * Set the flow control receive threshold registers. Normally,
1240 * these registers will be set to a default threshold that may be
1241 * adjusted later by the driver's runtime code. However, if the
1242 * ability to transmit pause frames is not enabled, then these
1243 * registers will be set to 0.
1245 if (hw->fc.current_mode & e1000_fc_tx_pause) {
1247 * We need to set up the Receive Threshold high and low water
1248 * marks as well as (optionally) enabling the transmission of
1251 fcrtl = hw->fc.low_water;
1252 if (hw->fc.send_xon)
1253 fcrtl |= E1000_FCRTL_XONE;
1255 fcrth = hw->fc.high_water;
1257 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1258 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1260 return E1000_SUCCESS;
1264 * e1000_set_default_fc_generic - Set flow control default values
1265 * @hw: pointer to the HW structure
1267 * Read the EEPROM for the default values for flow control and store the
1270 #ifdef NO_82542_SUPPORT
1271 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
1273 s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
1276 s32 ret_val = E1000_SUCCESS;
1279 DEBUGFUNC("e1000_set_default_fc_generic");
1282 * Read and store word 0x0F of the EEPROM. This word contains bits
1283 * that determine the hardware's default PAUSE (flow control) mode,
1284 * a bit that determines whether the HW defaults to enabling or
1285 * disabling auto-negotiation, and the direction of the
1286 * SW defined pins. If there is no SW over-ride of the flow
1287 * control setting, then the variable hw->fc will
1288 * be initialized based on a value in the EEPROM.
1290 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
1293 DEBUGOUT("NVM Read Error\n");
1297 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
1298 hw->fc.requested_mode = e1000_fc_none;
1299 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
1301 hw->fc.requested_mode = e1000_fc_tx_pause;
1303 hw->fc.requested_mode = e1000_fc_full;
1310 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1311 * @hw: pointer to the HW structure
1313 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1314 * device control register to reflect the adapter settings. TFCE and RFCE
1315 * need to be explicitly set by software when a copper PHY is used because
1316 * autonegotiation is managed by the PHY rather than the MAC. Software must
1317 * also configure these bits when link is forced on a fiber connection.
1319 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1322 s32 ret_val = E1000_SUCCESS;
1324 DEBUGFUNC("e1000_force_mac_fc_generic");
1326 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1329 * Because we didn't get link via the internal auto-negotiation
1330 * mechanism (we either forced link or we got link via PHY
1331 * auto-neg), we have to manually enable/disable transmit an
1332 * receive flow control.
1334 * The "Case" statement below enables/disable flow control
1335 * according to the "hw->fc.current_mode" parameter.
1337 * The possible values of the "fc" parameter are:
1338 * 0: Flow control is completely disabled
1339 * 1: Rx flow control is enabled (we can receive pause
1340 * frames but not send pause frames).
1341 * 2: Tx flow control is enabled (we can send pause frames
1342 * frames but we do not receive pause frames).
1343 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1344 * other: No other values should be possible at this point.
1346 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1348 switch (hw->fc.current_mode) {
1350 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1352 case e1000_fc_rx_pause:
1353 ctrl &= (~E1000_CTRL_TFCE);
1354 ctrl |= E1000_CTRL_RFCE;
1356 case e1000_fc_tx_pause:
1357 ctrl &= (~E1000_CTRL_RFCE);
1358 ctrl |= E1000_CTRL_TFCE;
1361 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1364 DEBUGOUT("Flow control param set incorrectly\n");
1365 ret_val = -E1000_ERR_CONFIG;
1369 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1376 * e1000_config_fc_after_link_up_generic - Configures flow control after link
1377 * @hw: pointer to the HW structure
1379 * Checks the status of auto-negotiation after link up to ensure that the
1380 * speed and duplex were not forced. If the link needed to be forced, then
1381 * flow control needs to be forced also. If auto-negotiation is enabled
1382 * and did not fail, then we configure flow control based on our link
1385 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1387 struct e1000_mac_info *mac = &hw->mac;
1388 s32 ret_val = E1000_SUCCESS;
1389 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1392 DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1395 * Check for the case where we have fiber media and auto-neg failed
1396 * so we had to force link. In this case, we need to force the
1397 * configuration of the MAC to match the "fc" parameter.
1399 if (mac->autoneg_failed) {
1400 if (hw->phy.media_type == e1000_media_type_fiber ||
1401 hw->phy.media_type == e1000_media_type_internal_serdes)
1402 ret_val = e1000_force_mac_fc_generic(hw);
1404 if (hw->phy.media_type == e1000_media_type_copper)
1405 ret_val = e1000_force_mac_fc_generic(hw);
1409 DEBUGOUT("Error forcing flow control settings\n");
1414 * Check for the case where we have copper media and auto-neg is
1415 * enabled. In this case, we need to check and see if Auto-Neg
1416 * has completed, and if so, how the PHY and link partner has
1417 * flow control configured.
1419 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1421 * Read the MII Status Register and check to see if AutoNeg
1422 * has completed. We read this twice because this reg has
1423 * some "sticky" (latched) bits.
1425 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1428 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1432 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1433 DEBUGOUT("Copper PHY and Auto Neg "
1434 "has not completed.\n");
1439 * The AutoNeg process has completed, so we now need to
1440 * read both the Auto Negotiation Advertisement
1441 * Register (Address 4) and the Auto_Negotiation Base
1442 * Page Ability Register (Address 5) to determine how
1443 * flow control was negotiated.
1445 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1449 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1450 &mii_nway_lp_ability_reg);
1455 * Two bits in the Auto Negotiation Advertisement Register
1456 * (Address 4) and two bits in the Auto Negotiation Base
1457 * Page Ability Register (Address 5) determine flow control
1458 * for both the PHY and the link partner. The following
1459 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1460 * 1999, describes these PAUSE resolution bits and how flow
1461 * control is determined based upon these settings.
1462 * NOTE: DC = Don't Care
1464 * LOCAL DEVICE | LINK PARTNER
1465 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1466 *-------|---------|-------|---------|--------------------
1467 * 0 | 0 | DC | DC | e1000_fc_none
1468 * 0 | 1 | 0 | DC | e1000_fc_none
1469 * 0 | 1 | 1 | 0 | e1000_fc_none
1470 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1471 * 1 | 0 | 0 | DC | e1000_fc_none
1472 * 1 | DC | 1 | DC | e1000_fc_full
1473 * 1 | 1 | 0 | 0 | e1000_fc_none
1474 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1476 * Are both PAUSE bits set to 1? If so, this implies
1477 * Symmetric Flow Control is enabled at both ends. The
1478 * ASM_DIR bits are irrelevant per the spec.
1480 * For Symmetric Flow Control:
1482 * LOCAL DEVICE | LINK PARTNER
1483 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1484 *-------|---------|-------|---------|--------------------
1485 * 1 | DC | 1 | DC | E1000_fc_full
1488 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1489 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1491 * Now we need to check if the user selected Rx ONLY
1492 * of pause frames. In this case, we had to advertise
1493 * FULL flow control because we could not advertise Rx
1494 * ONLY. Hence, we must now check to see if we need to
1495 * turn OFF the TRANSMISSION of PAUSE frames.
1497 if (hw->fc.requested_mode == e1000_fc_full) {
1498 hw->fc.current_mode = e1000_fc_full;
1499 DEBUGOUT("Flow Control = FULL.\r\n");
1501 hw->fc.current_mode = e1000_fc_rx_pause;
1502 DEBUGOUT("Flow Control = "
1503 "Rx PAUSE frames only.\r\n");
1507 * For receiving PAUSE frames ONLY.
1509 * LOCAL DEVICE | LINK PARTNER
1510 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1511 *-------|---------|-------|---------|--------------------
1512 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1514 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1515 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1516 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1517 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1518 hw->fc.current_mode = e1000_fc_tx_pause;
1519 DEBUGOUT("Flow Control = Tx PAUSE frames only.\r\n");
1522 * For transmitting PAUSE frames ONLY.
1524 * LOCAL DEVICE | LINK PARTNER
1525 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1526 *-------|---------|-------|---------|--------------------
1527 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1529 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1530 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1531 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1532 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1533 hw->fc.current_mode = e1000_fc_rx_pause;
1534 DEBUGOUT("Flow Control = Rx PAUSE frames only.\r\n");
1537 * Per the IEEE spec, at this point flow control
1538 * should be disabled.
1540 hw->fc.current_mode = e1000_fc_none;
1541 DEBUGOUT("Flow Control = NONE.\r\n");
1545 * Now we need to do one last check... If we auto-
1546 * negotiated to HALF DUPLEX, flow control should not be
1547 * enabled per IEEE 802.3 spec.
1549 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1551 DEBUGOUT("Error getting link speed and duplex\n");
1555 if (duplex == HALF_DUPLEX)
1556 hw->fc.current_mode = e1000_fc_none;
1559 * Now we call a subroutine to actually force the MAC
1560 * controller to use the correct flow control settings.
1562 ret_val = e1000_force_mac_fc_generic(hw);
1564 DEBUGOUT("Error forcing flow control settings\n");
1574 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1575 * @hw: pointer to the HW structure
1576 * @speed: stores the current speed
1577 * @duplex: stores the current duplex
1579 * Read the status register for the current speed/duplex and store the current
1580 * speed and duplex for copper connections.
1582 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1587 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1589 status = E1000_READ_REG(hw, E1000_STATUS);
1590 if (status & E1000_STATUS_SPEED_1000) {
1591 *speed = SPEED_1000;
1592 DEBUGOUT("1000 Mbs, ");
1593 } else if (status & E1000_STATUS_SPEED_100) {
1595 DEBUGOUT("100 Mbs, ");
1598 DEBUGOUT("10 Mbs, ");
1601 if (status & E1000_STATUS_FD) {
1602 *duplex = FULL_DUPLEX;
1603 DEBUGOUT("Full Duplex\n");
1605 *duplex = HALF_DUPLEX;
1606 DEBUGOUT("Half Duplex\n");
1609 return E1000_SUCCESS;
1613 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1614 * @hw: pointer to the HW structure
1615 * @speed: stores the current speed
1616 * @duplex: stores the current duplex
1618 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1619 * for fiber/serdes links.
1621 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
1622 u16 *speed, u16 *duplex)
1624 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1626 *speed = SPEED_1000;
1627 *duplex = FULL_DUPLEX;
1629 return E1000_SUCCESS;
1633 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1634 * @hw: pointer to the HW structure
1636 * Acquire the HW semaphore to access the PHY or NVM
1638 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1641 s32 ret_val = E1000_SUCCESS;
1642 s32 timeout = hw->nvm.word_size + 1;
1645 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1647 /* Get the SW semaphore */
1648 while (i < timeout) {
1649 swsm = E1000_READ_REG(hw, E1000_SWSM);
1650 if (!(swsm & E1000_SWSM_SMBI))
1658 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1659 ret_val = -E1000_ERR_NVM;
1663 /* Get the FW semaphore. */
1664 for (i = 0; i < timeout; i++) {
1665 swsm = E1000_READ_REG(hw, E1000_SWSM);
1666 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1668 /* Semaphore acquired if bit latched */
1669 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1676 /* Release semaphores */
1677 e1000_put_hw_semaphore_generic(hw);
1678 DEBUGOUT("Driver can't access the NVM\n");
1679 ret_val = -E1000_ERR_NVM;
1688 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1689 * @hw: pointer to the HW structure
1691 * Release hardware semaphore used to access the PHY or NVM
1693 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1697 DEBUGFUNC("e1000_put_hw_semaphore_generic");
1699 swsm = E1000_READ_REG(hw, E1000_SWSM);
1701 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1703 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1707 * e1000_get_auto_rd_done_generic - Check for auto read completion
1708 * @hw: pointer to the HW structure
1710 * Check EEPROM for Auto Read done bit.
1712 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1715 s32 ret_val = E1000_SUCCESS;
1717 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1719 while (i < AUTO_READ_DONE_TIMEOUT) {
1720 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1726 if (i == AUTO_READ_DONE_TIMEOUT) {
1727 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1728 ret_val = -E1000_ERR_RESET;
1737 * e1000_valid_led_default_generic - Verify a valid default LED config
1738 * @hw: pointer to the HW structure
1739 * @data: pointer to the NVM (EEPROM)
1741 * Read the EEPROM for the current default LED configuration. If the
1742 * LED configuration is not valid, set to a valid LED configuration.
1744 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1748 DEBUGFUNC("e1000_valid_led_default_generic");
1750 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1752 DEBUGOUT("NVM Read Error\n");
1756 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1757 *data = ID_LED_DEFAULT;
1764 * e1000_id_led_init_generic -
1765 * @hw: pointer to the HW structure
1768 s32 e1000_id_led_init_generic(struct e1000_hw *hw)
1770 struct e1000_mac_info *mac = &hw->mac;
1772 const u32 ledctl_mask = 0x000000FF;
1773 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1774 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1776 const u16 led_mask = 0x0F;
1778 DEBUGFUNC("e1000_id_led_init_generic");
1780 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1784 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1785 mac->ledctl_mode1 = mac->ledctl_default;
1786 mac->ledctl_mode2 = mac->ledctl_default;
1788 for (i = 0; i < 4; i++) {
1789 temp = (data >> (i << 2)) & led_mask;
1791 case ID_LED_ON1_DEF2:
1792 case ID_LED_ON1_ON2:
1793 case ID_LED_ON1_OFF2:
1794 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1795 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1797 case ID_LED_OFF1_DEF2:
1798 case ID_LED_OFF1_ON2:
1799 case ID_LED_OFF1_OFF2:
1800 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1801 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1808 case ID_LED_DEF1_ON2:
1809 case ID_LED_ON1_ON2:
1810 case ID_LED_OFF1_ON2:
1811 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1812 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1814 case ID_LED_DEF1_OFF2:
1815 case ID_LED_ON1_OFF2:
1816 case ID_LED_OFF1_OFF2:
1817 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1818 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1831 * e1000_setup_led_generic - Configures SW controllable LED
1832 * @hw: pointer to the HW structure
1834 * This prepares the SW controllable LED for use and saves the current state
1835 * of the LED so it can be later restored.
1837 s32 e1000_setup_led_generic(struct e1000_hw *hw)
1840 s32 ret_val = E1000_SUCCESS;
1842 DEBUGFUNC("e1000_setup_led_generic");
1844 if (hw->mac.ops.setup_led != e1000_setup_led_generic) {
1845 ret_val = -E1000_ERR_CONFIG;
1849 if (hw->phy.media_type == e1000_media_type_fiber) {
1850 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1851 hw->mac.ledctl_default = ledctl;
1853 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1854 E1000_LEDCTL_LED0_BLINK |
1855 E1000_LEDCTL_LED0_MODE_MASK);
1856 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1857 E1000_LEDCTL_LED0_MODE_SHIFT);
1858 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1859 } else if (hw->phy.media_type == e1000_media_type_copper) {
1860 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1868 * e1000_cleanup_led_generic - Set LED config to default operation
1869 * @hw: pointer to the HW structure
1871 * Remove the current LED configuration and set the LED configuration
1872 * to the default value, saved from the EEPROM.
1874 s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1876 DEBUGFUNC("e1000_cleanup_led_generic");
1878 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1879 return E1000_SUCCESS;
1883 * e1000_blink_led_generic - Blink LED
1884 * @hw: pointer to the HW structure
1886 * Blink the LEDs which are set to be on.
1888 s32 e1000_blink_led_generic(struct e1000_hw *hw)
1890 u32 ledctl_blink = 0;
1893 DEBUGFUNC("e1000_blink_led_generic");
1895 if (hw->phy.media_type == e1000_media_type_fiber) {
1896 /* always blink LED0 for PCI-E fiber */
1897 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1898 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1901 * set the blink bit for each LED that's "on" (0x0E)
1904 ledctl_blink = hw->mac.ledctl_mode2;
1905 for (i = 0; i < 4; i++)
1906 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1907 E1000_LEDCTL_MODE_LED_ON)
1908 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1912 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1914 return E1000_SUCCESS;
1918 * e1000_led_on_generic - Turn LED on
1919 * @hw: pointer to the HW structure
1923 s32 e1000_led_on_generic(struct e1000_hw *hw)
1927 DEBUGFUNC("e1000_led_on_generic");
1929 switch (hw->phy.media_type) {
1930 case e1000_media_type_fiber:
1931 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1932 ctrl &= ~E1000_CTRL_SWDPIN0;
1933 ctrl |= E1000_CTRL_SWDPIO0;
1934 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1936 case e1000_media_type_copper:
1937 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
1943 return E1000_SUCCESS;
1947 * e1000_led_off_generic - Turn LED off
1948 * @hw: pointer to the HW structure
1952 s32 e1000_led_off_generic(struct e1000_hw *hw)
1956 DEBUGFUNC("e1000_led_off_generic");
1958 switch (hw->phy.media_type) {
1959 case e1000_media_type_fiber:
1960 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1961 ctrl |= E1000_CTRL_SWDPIN0;
1962 ctrl |= E1000_CTRL_SWDPIO0;
1963 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1965 case e1000_media_type_copper:
1966 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1972 return E1000_SUCCESS;
1976 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
1977 * @hw: pointer to the HW structure
1978 * @no_snoop: bitmap of snoop events
1980 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1982 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
1986 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
1988 if (hw->bus.type != e1000_bus_type_pci_express)
1992 gcr = E1000_READ_REG(hw, E1000_GCR);
1993 gcr &= ~(PCIE_NO_SNOOP_ALL);
1995 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2002 * e1000_disable_pcie_master_generic - Disables PCI-express master access
2003 * @hw: pointer to the HW structure
2005 * Returns E1000_SUCCESS if successful, else returns -10
2006 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
2007 * the master requests to be disabled.
2009 * Disables PCI-Express master access and verifies there are no pending
2012 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
2015 s32 timeout = MASTER_DISABLE_TIMEOUT;
2016 s32 ret_val = E1000_SUCCESS;
2018 DEBUGFUNC("e1000_disable_pcie_master_generic");
2020 if (hw->bus.type != e1000_bus_type_pci_express)
2023 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2024 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
2025 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2028 if (!(E1000_READ_REG(hw, E1000_STATUS) &
2029 E1000_STATUS_GIO_MASTER_ENABLE))
2036 DEBUGOUT("Master requests are pending.\n");
2037 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
2045 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
2046 * @hw: pointer to the HW structure
2048 * Reset the Adaptive Interframe Spacing throttle to default values.
2050 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2052 struct e1000_mac_info *mac = &hw->mac;
2054 DEBUGFUNC("e1000_reset_adaptive_generic");
2056 if (!mac->adaptive_ifs) {
2057 DEBUGOUT("Not in Adaptive IFS mode!\n");
2061 mac->current_ifs_val = 0;
2062 mac->ifs_min_val = IFS_MIN;
2063 mac->ifs_max_val = IFS_MAX;
2064 mac->ifs_step_size = IFS_STEP;
2065 mac->ifs_ratio = IFS_RATIO;
2067 mac->in_ifs_mode = FALSE;
2068 E1000_WRITE_REG(hw, E1000_AIT, 0);
2074 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
2075 * @hw: pointer to the HW structure
2077 * Update the Adaptive Interframe Spacing Throttle value based on the
2078 * time between transmitted packets and time between collisions.
2080 void e1000_update_adaptive_generic(struct e1000_hw *hw)
2082 struct e1000_mac_info *mac = &hw->mac;
2084 DEBUGFUNC("e1000_update_adaptive_generic");
2086 if (!mac->adaptive_ifs) {
2087 DEBUGOUT("Not in Adaptive IFS mode!\n");
2091 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2092 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2093 mac->in_ifs_mode = TRUE;
2094 if (mac->current_ifs_val < mac->ifs_max_val) {
2095 if (!mac->current_ifs_val)
2096 mac->current_ifs_val = mac->ifs_min_val;
2098 mac->current_ifs_val +=
2100 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val);
2104 if (mac->in_ifs_mode &&
2105 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2106 mac->current_ifs_val = 0;
2107 mac->in_ifs_mode = FALSE;
2108 E1000_WRITE_REG(hw, E1000_AIT, 0);
2116 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2117 * @hw: pointer to the HW structure
2119 * Verify that when not using auto-negotiation that MDI/MDIx is correctly
2120 * set, which is forced to MDI mode only.
2122 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2124 s32 ret_val = E1000_SUCCESS;
2126 DEBUGFUNC("e1000_validate_mdi_setting_generic");
2128 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2129 DEBUGOUT("Invalid MDI setting detected\n");
2131 ret_val = -E1000_ERR_CONFIG;