2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * __FBSDID("$FreeBSD: src/sys/dev/pci/pci.c,v 1.355.2.9.2.1 2009/04/15 03:14:26 kensmith Exp $");
30 #include <sys/cdefs.h>
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/linker.h>
39 #include <sys/fcntl.h>
41 #include <sys/kernel.h>
42 #include <sys/queue.h>
43 #include <sys/sysctl.h>
44 #include <sys/endian.h>
47 #include <machine/smp.h>
52 #include <vm/vm_extern.h>
56 #include <sys/device.h>
58 #include <sys/pciio.h>
59 #include <bus/pci/pcireg.h>
60 #include <bus/pci/pcivar.h>
61 #include <bus/pci/pci_private.h>
67 #include <contrib/dev/acpica/acpi.h>
70 #define ACPI_PWR_FOR_SLEEP(x, y, z)
73 typedef void (*pci_read_cap_t)(device_t, int, int, pcicfgregs *);
75 static uint32_t pci_mapbase(unsigned mapreg);
76 static const char *pci_maptype(unsigned mapreg);
77 static int pci_mapsize(unsigned testval);
78 static int pci_maprange(unsigned mapreg);
79 static void pci_fixancient(pcicfgregs *cfg);
81 static int pci_porten(device_t pcib, int b, int s, int f);
82 static int pci_memen(device_t pcib, int b, int s, int f);
83 static void pci_assign_interrupt(device_t bus, device_t dev,
85 static int pci_add_map(device_t pcib, device_t bus, device_t dev,
86 int b, int s, int f, int reg,
87 struct resource_list *rl, int force, int prefetch);
88 static int pci_probe(device_t dev);
89 static int pci_attach(device_t dev);
90 static void pci_child_detached(device_t, device_t);
91 static void pci_load_vendor_data(void);
92 static int pci_describe_parse_line(char **ptr, int *vendor,
93 int *device, char **desc);
94 static char *pci_describe_device(device_t dev);
95 static int pci_modevent(module_t mod, int what, void *arg);
96 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
98 static void pci_read_capabilities(device_t pcib, pcicfgregs *cfg);
99 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
100 int reg, uint32_t *data);
102 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
103 int reg, uint32_t data);
105 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
106 static void pci_disable_msi(device_t dev);
107 static void pci_enable_msi(device_t dev, uint64_t address,
109 static void pci_enable_msix(device_t dev, u_int index,
110 uint64_t address, uint32_t data);
111 static void pci_mask_msix(device_t dev, u_int index);
112 static void pci_unmask_msix(device_t dev, u_int index);
113 static int pci_msi_blacklisted(void);
114 static void pci_resume_msi(device_t dev);
115 static void pci_resume_msix(device_t dev);
117 static void pci_read_cap_pmgt(device_t, int, int, pcicfgregs *);
118 static void pci_read_cap_ht(device_t, int, int, pcicfgregs *);
119 static void pci_read_cap_msi(device_t, int, int, pcicfgregs *);
120 static void pci_read_cap_msix(device_t, int, int, pcicfgregs *);
121 static void pci_read_cap_vpd(device_t, int, int, pcicfgregs *);
122 static void pci_read_cap_subvendor(device_t, int, int,
124 static void pci_read_cap_pcix(device_t, int, int, pcicfgregs *);
125 static void pci_read_cap_pcie(device_t, int, int, pcicfgregs *);
127 static device_method_t pci_methods[] = {
128 /* Device interface */
129 DEVMETHOD(device_probe, pci_probe),
130 DEVMETHOD(device_attach, pci_attach),
131 DEVMETHOD(device_detach, bus_generic_detach),
132 DEVMETHOD(device_shutdown, bus_generic_shutdown),
133 DEVMETHOD(device_suspend, pci_suspend),
134 DEVMETHOD(device_resume, pci_resume),
137 DEVMETHOD(bus_print_child, pci_print_child),
138 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
139 DEVMETHOD(bus_read_ivar, pci_read_ivar),
140 DEVMETHOD(bus_write_ivar, pci_write_ivar),
141 DEVMETHOD(bus_driver_added, pci_driver_added),
142 DEVMETHOD(bus_child_detached, pci_child_detached),
143 DEVMETHOD(bus_setup_intr, pci_setup_intr),
144 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
146 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
147 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
148 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
149 DEVMETHOD(bus_delete_resource, pci_delete_resource),
150 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
151 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
152 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
153 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
154 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
155 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
158 DEVMETHOD(pci_read_config, pci_read_config_method),
159 DEVMETHOD(pci_write_config, pci_write_config_method),
160 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
161 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
162 DEVMETHOD(pci_enable_io, pci_enable_io_method),
163 DEVMETHOD(pci_disable_io, pci_disable_io_method),
164 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
165 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
166 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
167 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
168 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
169 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
170 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
171 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
172 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
173 DEVMETHOD(pci_release_msi, pci_release_msi_method),
174 DEVMETHOD(pci_msi_count, pci_msi_count_method),
175 DEVMETHOD(pci_msix_count, pci_msix_count_method),
180 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
182 static devclass_t pci_devclass;
183 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
184 MODULE_VERSION(pci, 1);
186 static char *pci_vendordata;
187 static size_t pci_vendordata_size;
190 static const struct pci_read_cap {
192 pci_read_cap_t read_cap;
193 } pci_read_caps[] = {
194 { PCIY_PMG, pci_read_cap_pmgt },
195 { PCIY_HT, pci_read_cap_ht },
196 { PCIY_MSI, pci_read_cap_msi },
197 { PCIY_MSIX, pci_read_cap_msix },
198 { PCIY_VPD, pci_read_cap_vpd },
199 { PCIY_SUBVENDOR, pci_read_cap_subvendor },
200 { PCIY_PCIX, pci_read_cap_pcix },
201 { PCIY_EXPRESS, pci_read_cap_pcie },
202 { 0, NULL } /* required last entry */
206 uint32_t devid; /* Vendor/device of the card */
208 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
209 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
214 struct pci_quirk pci_quirks[] = {
215 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
216 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
217 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
218 /* As does the Serverworks OSB4 (the SMBus mapping register) */
219 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
222 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
223 * or the CMIC-SL (AKA ServerWorks GC_LE).
225 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
226 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
229 * MSI doesn't work on earlier Intel chipsets including
230 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
232 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
233 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
234 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
235 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
236 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
237 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
238 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
241 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
244 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
249 /* map register information */
250 #define PCI_MAPMEM 0x01 /* memory map */
251 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
252 #define PCI_MAPPORT 0x04 /* port map */
254 struct devlist pci_devq;
255 uint32_t pci_generation;
256 uint32_t pci_numdevs = 0;
257 static int pcie_chipset, pcix_chipset;
260 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
262 static int pci_enable_io_modes = 1;
263 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
264 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
265 &pci_enable_io_modes, 1,
266 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
267 enable these bits correctly. We'd like to do this all the time, but there\n\
268 are some peripherals that this causes problems with.");
270 static int pci_do_power_nodriver = 0;
271 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
272 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
273 &pci_do_power_nodriver, 0,
274 "Place a function into D3 state when no driver attaches to it. 0 means\n\
275 disable. 1 means conservatively place devices into D3 state. 2 means\n\
276 aggressively place devices into D3 state. 3 means put absolutely everything\n\
279 static int pci_do_power_resume = 1;
280 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
281 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
282 &pci_do_power_resume, 1,
283 "Transition from D3 -> D0 on resume.");
285 static int pci_do_msi = 1;
286 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
287 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
288 "Enable support for MSI interrupts");
290 static int pci_do_msix = 1;
291 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
292 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
293 "Enable support for MSI-X interrupts");
295 static int pci_honor_msi_blacklist = 1;
296 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
297 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
298 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
300 /* Find a device_t by bus/slot/function in domain 0 */
303 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
306 return (pci_find_dbsf(0, bus, slot, func));
309 /* Find a device_t by domain/bus/slot/function */
312 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
314 struct pci_devinfo *dinfo;
316 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
317 if ((dinfo->cfg.domain == domain) &&
318 (dinfo->cfg.bus == bus) &&
319 (dinfo->cfg.slot == slot) &&
320 (dinfo->cfg.func == func)) {
321 return (dinfo->cfg.dev);
328 /* Find a device_t by vendor/device ID */
331 pci_find_device(uint16_t vendor, uint16_t device)
333 struct pci_devinfo *dinfo;
335 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
336 if ((dinfo->cfg.vendor == vendor) &&
337 (dinfo->cfg.device == device)) {
338 return (dinfo->cfg.dev);
345 /* return base address of memory or port map */
348 pci_mapbase(uint32_t mapreg)
351 if (PCI_BAR_MEM(mapreg))
352 return (mapreg & PCIM_BAR_MEM_BASE);
354 return (mapreg & PCIM_BAR_IO_BASE);
357 /* return map type of memory or port map */
360 pci_maptype(unsigned mapreg)
363 if (PCI_BAR_IO(mapreg))
365 if (mapreg & PCIM_BAR_MEM_PREFETCH)
366 return ("Prefetchable Memory");
370 /* return log2 of map size decoded for memory or port map */
373 pci_mapsize(uint32_t testval)
377 testval = pci_mapbase(testval);
380 while ((testval & 1) == 0)
389 /* return log2 of address range supported by map register */
392 pci_maprange(unsigned mapreg)
396 if (PCI_BAR_IO(mapreg))
399 switch (mapreg & PCIM_BAR_MEM_TYPE) {
400 case PCIM_BAR_MEM_32:
403 case PCIM_BAR_MEM_1MB:
406 case PCIM_BAR_MEM_64:
413 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
416 pci_fixancient(pcicfgregs *cfg)
418 if (cfg->hdrtype != 0)
421 /* PCI to PCI bridges use header type 1 */
422 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
426 /* extract header type specific config data */
429 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
431 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
432 switch (cfg->hdrtype) {
434 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
435 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
436 cfg->nummaps = PCI_MAXMAPS_0;
439 cfg->nummaps = PCI_MAXMAPS_1;
442 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
443 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
444 cfg->nummaps = PCI_MAXMAPS_2;
450 /* read configuration header into pcicfgregs structure */
452 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
454 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
455 pcicfgregs *cfg = NULL;
456 struct pci_devinfo *devlist_entry;
457 struct devlist *devlist_head;
459 devlist_head = &pci_devq;
461 devlist_entry = NULL;
463 if (REG(PCIR_DEVVENDOR, 4) != -1) {
464 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
466 cfg = &devlist_entry->cfg;
472 cfg->vendor = REG(PCIR_VENDOR, 2);
473 cfg->device = REG(PCIR_DEVICE, 2);
474 cfg->cmdreg = REG(PCIR_COMMAND, 2);
475 cfg->statreg = REG(PCIR_STATUS, 2);
476 cfg->baseclass = REG(PCIR_CLASS, 1);
477 cfg->subclass = REG(PCIR_SUBCLASS, 1);
478 cfg->progif = REG(PCIR_PROGIF, 1);
479 cfg->revid = REG(PCIR_REVID, 1);
480 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
481 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
482 cfg->lattimer = REG(PCIR_LATTIMER, 1);
483 cfg->intpin = REG(PCIR_INTPIN, 1);
484 cfg->intline = REG(PCIR_INTLINE, 1);
488 * If using the APIC the intpin is probably wrong, since it
489 * is often setup by the BIOS with the PIC in mind.
491 if (cfg->intpin != 0) {
494 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
496 /* PCI specific entry found in MP table */
497 if (airq != cfg->intline) {
498 undirect_pci_irq(cfg->intline);
503 * PCI interrupts might be redirected to the
504 * ISA bus according to some MP tables. Use the
505 * same methods as used by the ISA devices
506 * devices to find the proper IOAPIC int pin.
508 airq = isa_apic_irq(cfg->intline);
509 if ((airq >= 0) && (airq != cfg->intline)) {
510 /* XXX: undirect_pci_irq() ? */
511 undirect_isa_irq(cfg->intline);
518 cfg->mingnt = REG(PCIR_MINGNT, 1);
519 cfg->maxlat = REG(PCIR_MAXLAT, 1);
521 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
522 cfg->hdrtype &= ~PCIM_MFDEV;
525 pci_hdrtypedata(pcib, b, s, f, cfg);
527 pci_read_capabilities(pcib, cfg);
529 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
531 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
532 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
533 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
534 devlist_entry->conf.pc_sel.pc_func = cfg->func;
535 devlist_entry->conf.pc_hdr = cfg->hdrtype;
537 devlist_entry->conf.pc_subvendor = cfg->subvendor;
538 devlist_entry->conf.pc_subdevice = cfg->subdevice;
539 devlist_entry->conf.pc_vendor = cfg->vendor;
540 devlist_entry->conf.pc_device = cfg->device;
542 devlist_entry->conf.pc_class = cfg->baseclass;
543 devlist_entry->conf.pc_subclass = cfg->subclass;
544 devlist_entry->conf.pc_progif = cfg->progif;
545 devlist_entry->conf.pc_revid = cfg->revid;
550 return (devlist_entry);
555 pci_fixup_nextptr(int *nextptr0)
557 int nextptr = *nextptr0;
559 /* "Next pointer" is only one byte */
560 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
564 * PCI local bus spec 3.0:
566 * "... The bottom two bits of all pointers are reserved
567 * and must be implemented as 00b although software must
568 * mask them to allow for future uses of these bits ..."
571 kprintf("Illegal PCI extended capability "
572 "offset, fixup 0x%02x -> 0x%02x\n",
573 nextptr, nextptr & ~0x3);
579 if (nextptr < 0x40) {
581 kprintf("Illegal PCI extended capability "
582 "offset 0x%02x", nextptr);
590 pci_read_cap_pmgt(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
593 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
595 struct pcicfg_pp *pp = &cfg->pp;
600 pp->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
601 pp->pp_status = ptr + PCIR_POWER_STATUS;
602 pp->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
604 if ((nextptr - ptr) > PCIR_POWER_DATA) {
607 * We should write to data_select and read back from
608 * data_scale to determine whether data register is
612 pp->pp_data = ptr + PCIR_POWER_DATA;
622 pci_read_cap_ht(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
625 #if defined(__i386__) || defined(__amd64__)
628 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
630 struct pcicfg_ht *ht = &cfg->ht;
634 /* Determine HT-specific capability type. */
635 val = REG(ptr + PCIR_HT_COMMAND, 2);
637 if ((val & PCIM_HTCMD_CAP_MASK) != PCIM_HTCAP_MSI_MAPPING)
640 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
641 /* Sanity check the mapping window. */
642 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 4);
644 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 4);
645 if (addr != MSI_INTEL_ADDR_BASE) {
646 device_printf(pcib, "HT Bridge at pci%d:%d:%d:%d "
647 "has non-default MSI window 0x%llx\n",
648 cfg->domain, cfg->bus, cfg->slot, cfg->func,
652 addr = MSI_INTEL_ADDR_BASE;
656 ht->ht_msictrl = val;
657 ht->ht_msiaddr = addr;
661 #endif /* __i386__ || __amd64__ */
666 pci_read_cap_msi(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
669 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
671 struct pcicfg_msi *msi = &cfg->msi;
673 msi->msi_location = ptr;
674 msi->msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
675 msi->msi_msgnum = 1 << ((msi->msi_ctrl & PCIM_MSICTRL_MMC_MASK) >> 1);
681 pci_read_cap_msix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
684 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
686 struct pcicfg_msix *msix = &cfg->msix;
689 msix->msix_location = ptr;
690 msix->msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
691 msix->msix_msgnum = (msix->msix_ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
693 val = REG(ptr + PCIR_MSIX_TABLE, 4);
694 msix->msix_table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
695 msix->msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
697 val = REG(ptr + PCIR_MSIX_PBA, 4);
698 msix->msix_pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
699 msix->msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
705 pci_read_cap_vpd(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
707 cfg->vpd.vpd_reg = ptr;
711 pci_read_cap_subvendor(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
714 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
716 /* Should always be true. */
717 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
720 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
721 cfg->subvendor = val & 0xffff;
722 cfg->subdevice = val >> 16;
729 pci_read_cap_pcix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
732 * Assume we have a PCI-X chipset if we have
733 * at least one PCI-PCI bridge with a PCI-X
734 * capability. Note that some systems with
735 * PCI-express or HT chipsets might match on
736 * this check as well.
738 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
743 pci_read_cap_pcie(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
746 * Assume we have a PCI-express chipset if we have
747 * at least one PCI-express device.
753 pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
755 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
756 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
761 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
762 /* No capabilities */
766 switch (cfg->hdrtype & PCIM_HDRTYPE) {
769 ptrptr = PCIR_CAP_PTR;
772 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
775 return; /* no capabilities support */
777 nextptr = REG(ptrptr, 1); /* sanity check? */
780 * Read capability entries.
782 while (pci_fixup_nextptr(&nextptr)) {
783 const struct pci_read_cap *rc;
786 /* Find the next entry */
787 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
789 /* Process this entry */
790 val = REG(ptr + PCICAP_ID, 1);
791 for (rc = pci_read_caps; rc->read_cap != NULL; ++rc) {
792 if (rc->cap == val) {
793 rc->read_cap(pcib, ptr, nextptr, cfg);
798 /* REG and WREG use carry through to next functions */
802 * PCI Vital Product Data
805 #define PCI_VPD_TIMEOUT 1000000
808 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
810 int count = PCI_VPD_TIMEOUT;
812 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
814 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
816 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
819 DELAY(1); /* limit looping */
821 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
828 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
830 int count = PCI_VPD_TIMEOUT;
832 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
834 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
835 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
836 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
839 DELAY(1); /* limit looping */
846 #undef PCI_VPD_TIMEOUT
848 struct vpd_readstate {
858 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
863 if (vrs->bytesinval == 0) {
864 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
866 vrs->val = le32toh(reg);
868 byte = vrs->val & 0xff;
871 vrs->val = vrs->val >> 8;
872 byte = vrs->val & 0xff;
882 pcie_set_max_readrq(device_t dev, uint16_t rqsize)
886 rqsize &= PCIEM_DEVCTL_MAX_READRQ_MASK;
887 if (rqsize > PCIEM_DEVCTL_MAX_READRQ_4096) {
888 panic("%s: invalid max read request size 0x%02x\n",
889 device_get_nameunit(dev), rqsize);
891 #warning "this code is incorrect, I think"
892 pci_find_extcap_method(device_get_parent(dev), dev, PCIY_EXPRESS, &expr_ptr);
894 panic("%s: not PCI Express\n", device_get_nameunit(dev));
895 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
896 if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) != rqsize) {
898 device_printf(dev, "adjust device control 0x%04x", val);
899 val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK;
901 pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2);
904 kprintf(" -> 0x%04x\n", val);
909 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
911 struct vpd_readstate vrs;
916 int alloc, off; /* alloc/off for RO/W arrays */
922 /* init vpd reader */
930 name = remain = i = 0; /* shut up stupid gcc */
931 alloc = off = 0; /* shut up stupid gcc */
932 dflen = 0; /* shut up stupid gcc */
935 if (vpd_nextbyte(&vrs, &byte)) {
940 kprintf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
941 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
942 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
945 case 0: /* item name */
947 if (vpd_nextbyte(&vrs, &byte2)) {
952 if (vpd_nextbyte(&vrs, &byte2)) {
956 remain |= byte2 << 8;
957 if (remain > (0x7f*4 - vrs.off)) {
960 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
961 cfg->domain, cfg->bus, cfg->slot,
967 name = (byte >> 3) & 0xf;
970 case 0x2: /* String */
971 cfg->vpd.vpd_ident = kmalloc(remain + 1,
979 case 0x10: /* VPD-R */
982 cfg->vpd.vpd_ros = kmalloc(alloc *
983 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
987 case 0x11: /* VPD-W */
990 cfg->vpd.vpd_w = kmalloc(alloc *
991 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
995 default: /* Invalid data, abort */
1001 case 1: /* Identifier String */
1002 cfg->vpd.vpd_ident[i++] = byte;
1005 cfg->vpd.vpd_ident[i] = '\0';
1010 case 2: /* VPD-R Keyword Header */
1012 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1013 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
1014 M_DEVBUF, M_WAITOK | M_ZERO);
1016 cfg->vpd.vpd_ros[off].keyword[0] = byte;
1017 if (vpd_nextbyte(&vrs, &byte2)) {
1021 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
1022 if (vpd_nextbyte(&vrs, &byte2)) {
1028 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
1031 * if this happens, we can't trust the rest
1035 "pci%d:%d:%d:%d: bad keyword length: %d\n",
1036 cfg->domain, cfg->bus, cfg->slot,
1041 } else if (dflen == 0) {
1042 cfg->vpd.vpd_ros[off].value = kmalloc(1 *
1043 sizeof(*cfg->vpd.vpd_ros[off].value),
1044 M_DEVBUF, M_WAITOK);
1045 cfg->vpd.vpd_ros[off].value[0] = '\x00';
1047 cfg->vpd.vpd_ros[off].value = kmalloc(
1049 sizeof(*cfg->vpd.vpd_ros[off].value),
1050 M_DEVBUF, M_WAITOK);
1053 /* keep in sync w/ state 3's transistions */
1054 if (dflen == 0 && remain == 0)
1056 else if (dflen == 0)
1062 case 3: /* VPD-R Keyword Value */
1063 cfg->vpd.vpd_ros[off].value[i++] = byte;
1064 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1065 "RV", 2) == 0 && cksumvalid == -1) {
1071 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
1072 cfg->domain, cfg->bus,
1073 cfg->slot, cfg->func,
1082 /* keep in sync w/ state 2's transistions */
1084 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1085 if (dflen == 0 && remain == 0) {
1086 cfg->vpd.vpd_rocnt = off;
1087 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1088 off * sizeof(*cfg->vpd.vpd_ros),
1089 M_DEVBUF, M_WAITOK | M_ZERO);
1091 } else if (dflen == 0)
1101 case 5: /* VPD-W Keyword Header */
1103 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1104 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1105 M_DEVBUF, M_WAITOK | M_ZERO);
1107 cfg->vpd.vpd_w[off].keyword[0] = byte;
1108 if (vpd_nextbyte(&vrs, &byte2)) {
1112 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1113 if (vpd_nextbyte(&vrs, &byte2)) {
1117 cfg->vpd.vpd_w[off].len = dflen = byte2;
1118 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1119 cfg->vpd.vpd_w[off].value = kmalloc((dflen + 1) *
1120 sizeof(*cfg->vpd.vpd_w[off].value),
1121 M_DEVBUF, M_WAITOK);
1124 /* keep in sync w/ state 6's transistions */
1125 if (dflen == 0 && remain == 0)
1127 else if (dflen == 0)
1133 case 6: /* VPD-W Keyword Value */
1134 cfg->vpd.vpd_w[off].value[i++] = byte;
1137 /* keep in sync w/ state 5's transistions */
1139 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1140 if (dflen == 0 && remain == 0) {
1141 cfg->vpd.vpd_wcnt = off;
1142 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1143 off * sizeof(*cfg->vpd.vpd_w),
1144 M_DEVBUF, M_WAITOK | M_ZERO);
1146 } else if (dflen == 0)
1151 kprintf("pci%d:%d:%d:%d: invalid state: %d\n",
1152 cfg->domain, cfg->bus, cfg->slot, cfg->func,
1159 if (cksumvalid == 0 || state < -1) {
1160 /* read-only data bad, clean up */
1161 if (cfg->vpd.vpd_ros != NULL) {
1162 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1163 kfree(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1164 kfree(cfg->vpd.vpd_ros, M_DEVBUF);
1165 cfg->vpd.vpd_ros = NULL;
1169 /* I/O error, clean up */
1170 kprintf("pci%d:%d:%d:%d: failed to read VPD data.\n",
1171 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1172 if (cfg->vpd.vpd_ident != NULL) {
1173 kfree(cfg->vpd.vpd_ident, M_DEVBUF);
1174 cfg->vpd.vpd_ident = NULL;
1176 if (cfg->vpd.vpd_w != NULL) {
1177 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1178 kfree(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1179 kfree(cfg->vpd.vpd_w, M_DEVBUF);
1180 cfg->vpd.vpd_w = NULL;
1183 cfg->vpd.vpd_cached = 1;
1189 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1191 struct pci_devinfo *dinfo = device_get_ivars(child);
1192 pcicfgregs *cfg = &dinfo->cfg;
1194 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1195 pci_read_vpd(device_get_parent(dev), cfg);
1197 *identptr = cfg->vpd.vpd_ident;
1199 if (*identptr == NULL)
1206 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1209 struct pci_devinfo *dinfo = device_get_ivars(child);
1210 pcicfgregs *cfg = &dinfo->cfg;
1213 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1214 pci_read_vpd(device_get_parent(dev), cfg);
1216 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1217 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1218 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1219 *vptr = cfg->vpd.vpd_ros[i].value;
1222 if (i != cfg->vpd.vpd_rocnt)
1230 * Return the offset in configuration space of the requested extended
1231 * capability entry or 0 if the specified capability was not found.
1234 pci_find_extcap_method(device_t dev, device_t child, int capability,
1237 struct pci_devinfo *dinfo = device_get_ivars(child);
1238 pcicfgregs *cfg = &dinfo->cfg;
1243 * Check the CAP_LIST bit of the PCI status register first.
1245 status = pci_read_config(child, PCIR_STATUS, 2);
1246 if (!(status & PCIM_STATUS_CAPPRESENT))
1250 * Determine the start pointer of the capabilities list.
1252 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1258 ptr = PCIR_CAP_PTR_2;
1262 return (ENXIO); /* no extended capabilities support */
1264 ptr = pci_read_config(child, ptr, 1);
1267 * Traverse the capabilities list.
1270 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1275 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1282 * Support for MSI-X message interrupts.
1285 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1287 struct pci_devinfo *dinfo = device_get_ivars(dev);
1288 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1291 KASSERT(msix->msix_table_len > index, ("bogus index"));
1292 offset = msix->msix_table_offset + index * 16;
1293 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1294 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1295 bus_write_4(msix->msix_table_res, offset + 8, data);
1297 /* Enable MSI -> HT mapping. */
1298 pci_ht_map_msi(dev, address);
1302 pci_mask_msix(device_t dev, u_int index)
1304 struct pci_devinfo *dinfo = device_get_ivars(dev);
1305 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1306 uint32_t offset, val;
1308 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1309 offset = msix->msix_table_offset + index * 16 + 12;
1310 val = bus_read_4(msix->msix_table_res, offset);
1311 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1312 val |= PCIM_MSIX_VCTRL_MASK;
1313 bus_write_4(msix->msix_table_res, offset, val);
1318 pci_unmask_msix(device_t dev, u_int index)
1320 struct pci_devinfo *dinfo = device_get_ivars(dev);
1321 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1322 uint32_t offset, val;
1324 KASSERT(msix->msix_table_len > index, ("bogus index"));
1325 offset = msix->msix_table_offset + index * 16 + 12;
1326 val = bus_read_4(msix->msix_table_res, offset);
1327 if (val & PCIM_MSIX_VCTRL_MASK) {
1328 val &= ~PCIM_MSIX_VCTRL_MASK;
1329 bus_write_4(msix->msix_table_res, offset, val);
1334 pci_pending_msix(device_t dev, u_int index)
1336 struct pci_devinfo *dinfo = device_get_ivars(dev);
1337 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1338 uint32_t offset, bit;
1340 KASSERT(msix->msix_table_len > index, ("bogus index"));
1341 offset = msix->msix_pba_offset + (index / 32) * 4;
1342 bit = 1 << index % 32;
1343 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1347 * Restore MSI-X registers and table during resume. If MSI-X is
1348 * enabled then walk the virtual table to restore the actual MSI-X
1352 pci_resume_msix(device_t dev)
1354 struct pci_devinfo *dinfo = device_get_ivars(dev);
1355 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1356 struct msix_table_entry *mte;
1357 struct msix_vector *mv;
1360 if (msix->msix_alloc > 0) {
1361 /* First, mask all vectors. */
1362 for (i = 0; i < msix->msix_msgnum; i++)
1363 pci_mask_msix(dev, i);
1365 /* Second, program any messages with at least one handler. */
1366 for (i = 0; i < msix->msix_table_len; i++) {
1367 mte = &msix->msix_table[i];
1368 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1370 mv = &msix->msix_vectors[mte->mte_vector - 1];
1371 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1372 pci_unmask_msix(dev, i);
1375 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1376 msix->msix_ctrl, 2);
1380 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1381 * returned in *count. After this function returns, each message will be
1382 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1385 pci_alloc_msix_method(device_t dev, device_t child, int *count)
1387 struct pci_devinfo *dinfo = device_get_ivars(child);
1388 pcicfgregs *cfg = &dinfo->cfg;
1389 struct resource_list_entry *rle;
1390 int actual, error, i, irq, max;
1392 /* Don't let count == 0 get us into trouble. */
1396 /* If rid 0 is allocated, then fail. */
1397 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1398 if (rle != NULL && rle->res != NULL)
1401 /* Already have allocated messages? */
1402 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1405 /* If MSI is blacklisted for this system, fail. */
1406 if (pci_msi_blacklisted())
1409 /* MSI-X capability present? */
1410 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1413 /* Make sure the appropriate BARs are mapped. */
1414 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1415 cfg->msix.msix_table_bar);
1416 if (rle == NULL || rle->res == NULL ||
1417 !(rman_get_flags(rle->res) & RF_ACTIVE))
1419 cfg->msix.msix_table_res = rle->res;
1420 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1421 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1422 cfg->msix.msix_pba_bar);
1423 if (rle == NULL || rle->res == NULL ||
1424 !(rman_get_flags(rle->res) & RF_ACTIVE))
1427 cfg->msix.msix_pba_res = rle->res;
1430 device_printf(child,
1431 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1432 *count, cfg->msix.msix_msgnum);
1433 max = min(*count, cfg->msix.msix_msgnum);
1434 for (i = 0; i < max; i++) {
1435 /* Allocate a message. */
1436 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1439 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1445 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1447 device_printf(child, "using IRQ %lu for MSI-X\n",
1453 * Be fancy and try to print contiguous runs of
1454 * IRQ values as ranges. 'irq' is the previous IRQ.
1455 * 'run' is true if we are in a range.
1457 device_printf(child, "using IRQs %lu", rle->start);
1460 for (i = 1; i < actual; i++) {
1461 rle = resource_list_find(&dinfo->resources,
1462 SYS_RES_IRQ, i + 1);
1464 /* Still in a run? */
1465 if (rle->start == irq + 1) {
1471 /* Finish previous range. */
1473 kprintf("-%d", irq);
1477 /* Start new range. */
1478 kprintf(",%lu", rle->start);
1482 /* Unfinished range? */
1484 kprintf("-%d", irq);
1485 kprintf(" for MSI-X\n");
1489 /* Mask all vectors. */
1490 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1491 pci_mask_msix(child, i);
1493 /* Allocate and initialize vector data and virtual table. */
1494 cfg->msix.msix_vectors = kmalloc(sizeof(struct msix_vector) * actual,
1495 M_DEVBUF, M_WAITOK | M_ZERO);
1496 cfg->msix.msix_table = kmalloc(sizeof(struct msix_table_entry) * actual,
1497 M_DEVBUF, M_WAITOK | M_ZERO);
1498 for (i = 0; i < actual; i++) {
1499 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1500 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1501 cfg->msix.msix_table[i].mte_vector = i + 1;
1504 /* Update control register to enable MSI-X. */
1505 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1506 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1507 cfg->msix.msix_ctrl, 2);
1509 /* Update counts of alloc'd messages. */
1510 cfg->msix.msix_alloc = actual;
1511 cfg->msix.msix_table_len = actual;
1517 * By default, pci_alloc_msix() will assign the allocated IRQ
1518 * resources consecutively to the first N messages in the MSI-X table.
1519 * However, device drivers may want to use different layouts if they
1520 * either receive fewer messages than they asked for, or they wish to
1521 * populate the MSI-X table sparsely. This method allows the driver
1522 * to specify what layout it wants. It must be called after a
1523 * successful pci_alloc_msix() but before any of the associated
1524 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1526 * The 'vectors' array contains 'count' message vectors. The array
1527 * maps directly to the MSI-X table in that index 0 in the array
1528 * specifies the vector for the first message in the MSI-X table, etc.
1529 * The vector value in each array index can either be 0 to indicate
1530 * that no vector should be assigned to a message slot, or it can be a
1531 * number from 1 to N (where N is the count returned from a
1532 * succcessful call to pci_alloc_msix()) to indicate which message
1533 * vector (IRQ) to be used for the corresponding message.
1535 * On successful return, each message with a non-zero vector will have
1536 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1537 * 1. Additionally, if any of the IRQs allocated via the previous
1538 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1539 * will be kfreed back to the system automatically.
1541 * For example, suppose a driver has a MSI-X table with 6 messages and
1542 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1543 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1544 * C. After the call to pci_alloc_msix(), the device will be setup to
1545 * have an MSI-X table of ABC--- (where - means no vector assigned).
1546 * If the driver ten passes a vector array of { 1, 0, 1, 2, 0, 2 },
1547 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1548 * be kfreed back to the system. This device will also have valid
1549 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1551 * In any case, the SYS_RES_IRQ rid X will always map to the message
1552 * at MSI-X table index X - 1 and will only be valid if a vector is
1553 * assigned to that table entry.
1556 pci_remap_msix_method(device_t dev, device_t child, int count,
1557 const u_int *vectors)
1559 struct pci_devinfo *dinfo = device_get_ivars(child);
1560 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1561 struct resource_list_entry *rle;
1562 int i, irq, j, *used;
1565 * Have to have at least one message in the table but the
1566 * table can't be bigger than the actual MSI-X table in the
1569 if (count == 0 || count > msix->msix_msgnum)
1572 /* Sanity check the vectors. */
1573 for (i = 0; i < count; i++)
1574 if (vectors[i] > msix->msix_alloc)
1578 * Make sure there aren't any holes in the vectors to be used.
1579 * It's a big pain to support it, and it doesn't really make
1580 * sense anyway. Also, at least one vector must be used.
1582 used = kmalloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1584 for (i = 0; i < count; i++)
1585 if (vectors[i] != 0)
1586 used[vectors[i] - 1] = 1;
1587 for (i = 0; i < msix->msix_alloc - 1; i++)
1588 if (used[i] == 0 && used[i + 1] == 1) {
1589 kfree(used, M_DEVBUF);
1593 kfree(used, M_DEVBUF);
1597 /* Make sure none of the resources are allocated. */
1598 for (i = 0; i < msix->msix_table_len; i++) {
1599 if (msix->msix_table[i].mte_vector == 0)
1601 if (msix->msix_table[i].mte_handlers > 0)
1603 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1604 KASSERT(rle != NULL, ("missing resource"));
1605 if (rle->res != NULL)
1609 /* Free the existing resource list entries. */
1610 for (i = 0; i < msix->msix_table_len; i++) {
1611 if (msix->msix_table[i].mte_vector == 0)
1613 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1617 * Build the new virtual table keeping track of which vectors are
1620 kfree(msix->msix_table, M_DEVBUF);
1621 msix->msix_table = kmalloc(sizeof(struct msix_table_entry) * count,
1622 M_DEVBUF, M_WAITOK | M_ZERO);
1623 for (i = 0; i < count; i++)
1624 msix->msix_table[i].mte_vector = vectors[i];
1625 msix->msix_table_len = count;
1627 /* Free any unused IRQs and resize the vectors array if necessary. */
1628 j = msix->msix_alloc - 1;
1630 struct msix_vector *vec;
1632 while (used[j] == 0) {
1633 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1634 msix->msix_vectors[j].mv_irq);
1637 vec = kmalloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
1639 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1641 kfree(msix->msix_vectors, M_DEVBUF);
1642 msix->msix_vectors = vec;
1643 msix->msix_alloc = j + 1;
1645 kfree(used, M_DEVBUF);
1647 /* Map the IRQs onto the rids. */
1648 for (i = 0; i < count; i++) {
1649 if (vectors[i] == 0)
1651 irq = msix->msix_vectors[vectors[i]].mv_irq;
1652 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1657 device_printf(child, "Remapped MSI-X IRQs as: ");
1658 for (i = 0; i < count; i++) {
1661 if (vectors[i] == 0)
1665 msix->msix_vectors[vectors[i]].mv_irq);
1674 pci_release_msix(device_t dev, device_t child)
1676 struct pci_devinfo *dinfo = device_get_ivars(child);
1677 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1678 struct resource_list_entry *rle;
1681 /* Do we have any messages to release? */
1682 if (msix->msix_alloc == 0)
1685 /* Make sure none of the resources are allocated. */
1686 for (i = 0; i < msix->msix_table_len; i++) {
1687 if (msix->msix_table[i].mte_vector == 0)
1689 if (msix->msix_table[i].mte_handlers > 0)
1691 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1692 KASSERT(rle != NULL, ("missing resource"));
1693 if (rle->res != NULL)
1697 /* Update control register to disable MSI-X. */
1698 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1699 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1700 msix->msix_ctrl, 2);
1702 /* Free the resource list entries. */
1703 for (i = 0; i < msix->msix_table_len; i++) {
1704 if (msix->msix_table[i].mte_vector == 0)
1706 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1708 kfree(msix->msix_table, M_DEVBUF);
1709 msix->msix_table_len = 0;
1711 /* Release the IRQs. */
1712 for (i = 0; i < msix->msix_alloc; i++)
1713 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1714 msix->msix_vectors[i].mv_irq);
1715 kfree(msix->msix_vectors, M_DEVBUF);
1716 msix->msix_alloc = 0;
1721 * Return the max supported MSI-X messages this device supports.
1722 * Basically, assuming the MD code can alloc messages, this function
1723 * should return the maximum value that pci_alloc_msix() can return.
1724 * Thus, it is subject to the tunables, etc.
1727 pci_msix_count_method(device_t dev, device_t child)
1729 struct pci_devinfo *dinfo = device_get_ivars(child);
1730 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1732 if (pci_do_msix && msix->msix_location != 0)
1733 return (msix->msix_msgnum);
1738 * HyperTransport MSI mapping control
1741 pci_ht_map_msi(device_t dev, uint64_t addr)
1743 struct pci_devinfo *dinfo = device_get_ivars(dev);
1744 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1749 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1750 ht->ht_msiaddr >> 20 == addr >> 20) {
1751 /* Enable MSI -> HT mapping. */
1752 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1753 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1757 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
1758 /* Disable MSI -> HT mapping. */
1759 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1760 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1766 * Support for MSI message signalled interrupts.
1769 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1771 struct pci_devinfo *dinfo = device_get_ivars(dev);
1772 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1774 /* Write data and address values. */
1775 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1776 address & 0xffffffff, 4);
1777 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1778 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1780 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1783 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1786 /* Enable MSI in the control register. */
1787 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1788 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1791 /* Enable MSI -> HT mapping. */
1792 pci_ht_map_msi(dev, address);
1796 pci_disable_msi(device_t dev)
1798 struct pci_devinfo *dinfo = device_get_ivars(dev);
1799 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1801 /* Disable MSI -> HT mapping. */
1802 pci_ht_map_msi(dev, 0);
1804 /* Disable MSI in the control register. */
1805 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1806 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1811 * Restore MSI registers during resume. If MSI is enabled then
1812 * restore the data and address registers in addition to the control
1816 pci_resume_msi(device_t dev)
1818 struct pci_devinfo *dinfo = device_get_ivars(dev);
1819 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1823 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1824 address = msi->msi_addr;
1825 data = msi->msi_data;
1826 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1827 address & 0xffffffff, 4);
1828 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1829 pci_write_config(dev, msi->msi_location +
1830 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1831 pci_write_config(dev, msi->msi_location +
1832 PCIR_MSI_DATA_64BIT, data, 2);
1834 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1837 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1842 pci_remap_msi_irq(device_t dev, u_int irq)
1844 struct pci_devinfo *dinfo = device_get_ivars(dev);
1845 pcicfgregs *cfg = &dinfo->cfg;
1846 struct resource_list_entry *rle;
1847 struct msix_table_entry *mte;
1848 struct msix_vector *mv;
1854 bus = device_get_parent(dev);
1857 * Handle MSI first. We try to find this IRQ among our list
1858 * of MSI IRQs. If we find it, we request updated address and
1859 * data registers and apply the results.
1861 if (cfg->msi.msi_alloc > 0) {
1863 /* If we don't have any active handlers, nothing to do. */
1864 if (cfg->msi.msi_handlers == 0)
1866 for (i = 0; i < cfg->msi.msi_alloc; i++) {
1867 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
1869 if (rle->start == irq) {
1870 error = PCIB_MAP_MSI(device_get_parent(bus),
1871 dev, irq, &addr, &data);
1874 pci_disable_msi(dev);
1875 dinfo->cfg.msi.msi_addr = addr;
1876 dinfo->cfg.msi.msi_data = data;
1877 pci_enable_msi(dev, addr, data);
1885 * For MSI-X, we check to see if we have this IRQ. If we do,
1886 * we request the updated mapping info. If that works, we go
1887 * through all the slots that use this IRQ and update them.
1889 if (cfg->msix.msix_alloc > 0) {
1890 for (i = 0; i < cfg->msix.msix_alloc; i++) {
1891 mv = &cfg->msix.msix_vectors[i];
1892 if (mv->mv_irq == irq) {
1893 error = PCIB_MAP_MSI(device_get_parent(bus),
1894 dev, irq, &addr, &data);
1897 mv->mv_address = addr;
1899 for (j = 0; j < cfg->msix.msix_table_len; j++) {
1900 mte = &cfg->msix.msix_table[j];
1901 if (mte->mte_vector != i + 1)
1903 if (mte->mte_handlers == 0)
1905 pci_mask_msix(dev, j);
1906 pci_enable_msix(dev, j, addr, data);
1907 pci_unmask_msix(dev, j);
1918 * Returns true if the specified device is blacklisted because MSI
1922 pci_msi_device_blacklisted(device_t dev)
1924 struct pci_quirk *q;
1926 if (!pci_honor_msi_blacklist)
1929 for (q = &pci_quirks[0]; q->devid; q++) {
1930 if (q->devid == pci_get_devid(dev) &&
1931 q->type == PCI_QUIRK_DISABLE_MSI)
1938 * Determine if MSI is blacklisted globally on this sytem. Currently,
1939 * we just check for blacklisted chipsets as represented by the
1940 * host-PCI bridge at device 0:0:0. In the future, it may become
1941 * necessary to check other system attributes, such as the kenv values
1942 * that give the motherboard manufacturer and model number.
1945 pci_msi_blacklisted(void)
1949 if (!pci_honor_msi_blacklist)
1952 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
1953 if (!(pcie_chipset || pcix_chipset))
1956 dev = pci_find_bsf(0, 0, 0);
1958 return (pci_msi_device_blacklisted(dev));
1963 * Attempt to allocate *count MSI messages. The actual number allocated is
1964 * returned in *count. After this function returns, each message will be
1965 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
1968 pci_alloc_msi_method(device_t dev, device_t child, int *count)
1970 struct pci_devinfo *dinfo = device_get_ivars(child);
1971 pcicfgregs *cfg = &dinfo->cfg;
1972 struct resource_list_entry *rle;
1973 int actual, error, i, irqs[32];
1976 /* Don't let count == 0 get us into trouble. */
1980 /* If rid 0 is allocated, then fail. */
1981 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1982 if (rle != NULL && rle->res != NULL)
1985 /* Already have allocated messages? */
1986 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1989 /* If MSI is blacklisted for this system, fail. */
1990 if (pci_msi_blacklisted())
1993 /* MSI capability present? */
1994 if (cfg->msi.msi_location == 0 || !pci_do_msi)
1998 device_printf(child,
1999 "attempting to allocate %d MSI vectors (%d supported)\n",
2000 *count, cfg->msi.msi_msgnum);
2002 /* Don't ask for more than the device supports. */
2003 actual = min(*count, cfg->msi.msi_msgnum);
2005 /* Don't ask for more than 32 messages. */
2006 actual = min(actual, 32);
2008 /* MSI requires power of 2 number of messages. */
2009 if (!powerof2(actual))
2013 /* Try to allocate N messages. */
2014 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
2015 cfg->msi.msi_msgnum, irqs);
2026 * We now have N actual messages mapped onto SYS_RES_IRQ
2027 * resources in the irqs[] array, so add new resources
2028 * starting at rid 1.
2030 for (i = 0; i < actual; i++)
2031 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
2032 irqs[i], irqs[i], 1);
2036 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
2041 * Be fancy and try to print contiguous runs
2042 * of IRQ values as ranges. 'run' is true if
2043 * we are in a range.
2045 device_printf(child, "using IRQs %d", irqs[0]);
2047 for (i = 1; i < actual; i++) {
2049 /* Still in a run? */
2050 if (irqs[i] == irqs[i - 1] + 1) {
2055 /* Finish previous range. */
2057 kprintf("-%d", irqs[i - 1]);
2061 /* Start new range. */
2062 kprintf(",%d", irqs[i]);
2065 /* Unfinished range? */
2067 kprintf("-%d", irqs[actual - 1]);
2068 kprintf(" for MSI\n");
2072 /* Update control register with actual count. */
2073 ctrl = cfg->msi.msi_ctrl;
2074 ctrl &= ~PCIM_MSICTRL_MME_MASK;
2075 ctrl |= (ffs(actual) - 1) << 4;
2076 cfg->msi.msi_ctrl = ctrl;
2077 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2079 /* Update counts of alloc'd messages. */
2080 cfg->msi.msi_alloc = actual;
2081 cfg->msi.msi_handlers = 0;
2086 /* Release the MSI messages associated with this device. */
2088 pci_release_msi_method(device_t dev, device_t child)
2090 struct pci_devinfo *dinfo = device_get_ivars(child);
2091 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2092 struct resource_list_entry *rle;
2093 int error, i, irqs[32];
2095 /* Try MSI-X first. */
2096 error = pci_release_msix(dev, child);
2097 if (error != ENODEV)
2100 /* Do we have any messages to release? */
2101 if (msi->msi_alloc == 0)
2103 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2105 /* Make sure none of the resources are allocated. */
2106 if (msi->msi_handlers > 0)
2108 for (i = 0; i < msi->msi_alloc; i++) {
2109 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2110 KASSERT(rle != NULL, ("missing MSI resource"));
2111 if (rle->res != NULL)
2113 irqs[i] = rle->start;
2116 /* Update control register with 0 count. */
2117 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2118 ("%s: MSI still enabled", __func__));
2119 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2120 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2123 /* Release the messages. */
2124 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
2125 for (i = 0; i < msi->msi_alloc; i++)
2126 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2128 /* Update alloc count. */
2136 * Return the max supported MSI messages this device supports.
2137 * Basically, assuming the MD code can alloc messages, this function
2138 * should return the maximum value that pci_alloc_msi() can return.
2139 * Thus, it is subject to the tunables, etc.
2142 pci_msi_count_method(device_t dev, device_t child)
2144 struct pci_devinfo *dinfo = device_get_ivars(child);
2145 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2147 if (pci_do_msi && msi->msi_location != 0)
2148 return (msi->msi_msgnum);
2152 /* kfree pcicfgregs structure and all depending data structures */
2155 pci_freecfg(struct pci_devinfo *dinfo)
2157 struct devlist *devlist_head;
2160 devlist_head = &pci_devq;
2162 if (dinfo->cfg.vpd.vpd_reg) {
2163 kfree(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2164 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2165 kfree(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2166 kfree(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2167 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2168 kfree(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2169 kfree(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2171 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2172 kfree(dinfo, M_DEVBUF);
2174 /* increment the generation count */
2177 /* we're losing one device */
2183 * PCI power manangement
2186 pci_set_powerstate_method(device_t dev, device_t child, int state)
2188 struct pci_devinfo *dinfo = device_get_ivars(child);
2189 pcicfgregs *cfg = &dinfo->cfg;
2191 int result, oldstate, highest, delay;
2193 if (cfg->pp.pp_cap == 0)
2194 return (EOPNOTSUPP);
2197 * Optimize a no state change request away. While it would be OK to
2198 * write to the hardware in theory, some devices have shown odd
2199 * behavior when going from D3 -> D3.
2201 oldstate = pci_get_powerstate(child);
2202 if (oldstate == state)
2206 * The PCI power management specification states that after a state
2207 * transition between PCI power states, system software must
2208 * guarantee a minimal delay before the function accesses the device.
2209 * Compute the worst case delay that we need to guarantee before we
2210 * access the device. Many devices will be responsive much more
2211 * quickly than this delay, but there are some that don't respond
2212 * instantly to state changes. Transitions to/from D3 state require
2213 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2214 * is done below with DELAY rather than a sleeper function because
2215 * this function can be called from contexts where we cannot sleep.
2217 highest = (oldstate > state) ? oldstate : state;
2218 if (highest == PCI_POWERSTATE_D3)
2220 else if (highest == PCI_POWERSTATE_D2)
2224 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2225 & ~PCIM_PSTAT_DMASK;
2228 case PCI_POWERSTATE_D0:
2229 status |= PCIM_PSTAT_D0;
2231 case PCI_POWERSTATE_D1:
2232 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2233 return (EOPNOTSUPP);
2234 status |= PCIM_PSTAT_D1;
2236 case PCI_POWERSTATE_D2:
2237 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2238 return (EOPNOTSUPP);
2239 status |= PCIM_PSTAT_D2;
2241 case PCI_POWERSTATE_D3:
2242 status |= PCIM_PSTAT_D3;
2250 "pci%d:%d:%d:%d: Transition from D%d to D%d\n",
2251 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2252 dinfo->cfg.func, oldstate, state);
2254 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2261 pci_get_powerstate_method(device_t dev, device_t child)
2263 struct pci_devinfo *dinfo = device_get_ivars(child);
2264 pcicfgregs *cfg = &dinfo->cfg;
2268 if (cfg->pp.pp_cap != 0) {
2269 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2270 switch (status & PCIM_PSTAT_DMASK) {
2272 result = PCI_POWERSTATE_D0;
2275 result = PCI_POWERSTATE_D1;
2278 result = PCI_POWERSTATE_D2;
2281 result = PCI_POWERSTATE_D3;
2284 result = PCI_POWERSTATE_UNKNOWN;
2288 /* No support, device is always at D0 */
2289 result = PCI_POWERSTATE_D0;
2295 * Some convenience functions for PCI device drivers.
2298 static __inline void
2299 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2303 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2305 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2308 static __inline void
2309 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2313 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2315 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2319 pci_enable_busmaster_method(device_t dev, device_t child)
2321 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2326 pci_disable_busmaster_method(device_t dev, device_t child)
2328 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2333 pci_enable_io_method(device_t dev, device_t child, int space)
2343 case SYS_RES_IOPORT:
2344 bit = PCIM_CMD_PORTEN;
2347 case SYS_RES_MEMORY:
2348 bit = PCIM_CMD_MEMEN;
2354 pci_set_command_bit(dev, child, bit);
2355 /* Some devices seem to need a brief stall here, what do to? */
2356 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2359 device_printf(child, "failed to enable %s mapping!\n", error);
2364 pci_disable_io_method(device_t dev, device_t child, int space)
2374 case SYS_RES_IOPORT:
2375 bit = PCIM_CMD_PORTEN;
2378 case SYS_RES_MEMORY:
2379 bit = PCIM_CMD_MEMEN;
2385 pci_clear_command_bit(dev, child, bit);
2386 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2387 if (command & bit) {
2388 device_printf(child, "failed to disable %s mapping!\n", error);
2395 * New style pci driver. Parent device is either a pci-host-bridge or a
2396 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2400 pci_print_verbose(struct pci_devinfo *dinfo)
2404 pcicfgregs *cfg = &dinfo->cfg;
2406 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2407 cfg->vendor, cfg->device, cfg->revid);
2408 kprintf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2409 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2410 kprintf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2411 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2413 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2414 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2415 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2416 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2417 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2418 if (cfg->intpin > 0)
2419 kprintf("\tintpin=%c, irq=%d\n",
2420 cfg->intpin +'a' -1, cfg->intline);
2421 if (cfg->pp.pp_cap) {
2424 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2425 kprintf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2426 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2427 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2428 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2429 status & PCIM_PSTAT_DMASK);
2431 if (cfg->msi.msi_location) {
2434 ctrl = cfg->msi.msi_ctrl;
2435 kprintf("\tMSI supports %d message%s%s%s\n",
2436 cfg->msi.msi_msgnum,
2437 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2438 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2439 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2441 if (cfg->msix.msix_location) {
2442 kprintf("\tMSI-X supports %d message%s ",
2443 cfg->msix.msix_msgnum,
2444 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2445 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2446 kprintf("in map 0x%x\n",
2447 cfg->msix.msix_table_bar);
2449 kprintf("in maps 0x%x and 0x%x\n",
2450 cfg->msix.msix_table_bar,
2451 cfg->msix.msix_pba_bar);
2457 pci_porten(device_t pcib, int b, int s, int f)
2459 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2460 & PCIM_CMD_PORTEN) != 0;
2464 pci_memen(device_t pcib, int b, int s, int f)
2466 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2467 & PCIM_CMD_MEMEN) != 0;
2471 * Add a resource based on a pci map register. Return 1 if the map
2472 * register is a 32bit map register or 2 if it is a 64bit register.
2475 pci_add_map(device_t pcib, device_t bus, device_t dev,
2476 int b, int s, int f, int reg, struct resource_list *rl, int force,
2481 pci_addr_t start, end, count;
2488 struct resource *res;
2490 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2491 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
2492 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2493 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
2495 if (PCI_BAR_MEM(map)) {
2496 type = SYS_RES_MEMORY;
2497 if (map & PCIM_BAR_MEM_PREFETCH)
2500 type = SYS_RES_IOPORT;
2501 ln2size = pci_mapsize(testval);
2502 ln2range = pci_maprange(testval);
2503 base = pci_mapbase(map);
2504 barlen = ln2range == 64 ? 2 : 1;
2507 * For I/O registers, if bottom bit is set, and the next bit up
2508 * isn't clear, we know we have a BAR that doesn't conform to the
2509 * spec, so ignore it. Also, sanity check the size of the data
2510 * areas to the type of memory involved. Memory must be at least
2511 * 16 bytes in size, while I/O ranges must be at least 4.
2513 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2515 if ((type == SYS_RES_MEMORY && ln2size < 4) ||
2516 (type == SYS_RES_IOPORT && ln2size < 2))
2520 /* Read the other half of a 64bit map register */
2521 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
2523 kprintf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2524 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
2525 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2526 kprintf(", port disabled\n");
2527 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2528 kprintf(", memory disabled\n");
2530 kprintf(", enabled\n");
2534 * If base is 0, then we have problems. It is best to ignore
2535 * such entries for the moment. These will be allocated later if
2536 * the driver specifically requests them. However, some
2537 * removable busses look better when all resources are allocated,
2538 * so allow '0' to be overriden.
2540 * Similarly treat maps whose values is the same as the test value
2541 * read back. These maps have had all f's written to them by the
2542 * BIOS in an attempt to disable the resources.
2544 if (!force && (base == 0 || map == testval))
2546 if ((u_long)base != base) {
2548 "pci%d:%d:%d:%d bar %#x too many address bits",
2549 pci_get_domain(dev), b, s, f, reg);
2554 * This code theoretically does the right thing, but has
2555 * undesirable side effects in some cases where peripherals
2556 * respond oddly to having these bits enabled. Let the user
2557 * be able to turn them off (since pci_enable_io_modes is 1 by
2560 if (pci_enable_io_modes) {
2561 /* Turn on resources that have been left off by a lazy BIOS */
2562 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
2563 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2564 cmd |= PCIM_CMD_PORTEN;
2565 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2567 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
2568 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2569 cmd |= PCIM_CMD_MEMEN;
2570 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2573 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2575 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2579 count = 1 << ln2size;
2580 if (base == 0 || base == pci_mapbase(testval)) {
2581 start = 0; /* Let the parent decide. */
2585 end = base + (1 << ln2size) - 1;
2587 resource_list_add(rl, type, reg, start, end, count);
2590 * Try to allocate the resource for this BAR from our parent
2591 * so that this resource range is already reserved. The
2592 * driver for this device will later inherit this resource in
2593 * pci_alloc_resource().
2595 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
2596 prefetch ? RF_PREFETCHABLE : 0);
2599 * If the allocation fails, clear the BAR and delete
2600 * the resource list entry to force
2601 * pci_alloc_resource() to allocate resources from the
2604 resource_list_delete(rl, type, reg);
2607 start = rman_get_start(res);
2608 pci_write_config(dev, reg, start, 4);
2610 pci_write_config(dev, reg + 4, start >> 32, 4);
2615 * For ATA devices we need to decide early what addressing mode to use.
2616 * Legacy demands that the primary and secondary ATA ports sits on the
2617 * same addresses that old ISA hardware did. This dictates that we use
2618 * those addresses and ignore the BAR's if we cannot set PCI native
2622 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
2623 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask)
2625 int rid, type, progif;
2627 /* if this device supports PCI native addressing use it */
2628 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2629 if ((progif & 0x8a) == 0x8a) {
2630 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2631 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2632 kprintf("Trying ATA native PCI addressing mode\n");
2633 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2637 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2638 type = SYS_RES_IOPORT;
2639 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2640 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force,
2641 prefetchmask & (1 << 0));
2642 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force,
2643 prefetchmask & (1 << 1));
2646 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
2647 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
2650 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
2651 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
2654 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2655 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force,
2656 prefetchmask & (1 << 2));
2657 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force,
2658 prefetchmask & (1 << 3));
2661 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
2662 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
2665 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
2666 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
2669 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force,
2670 prefetchmask & (1 << 4));
2671 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force,
2672 prefetchmask & (1 << 5));
2676 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2678 struct pci_devinfo *dinfo = device_get_ivars(dev);
2679 pcicfgregs *cfg = &dinfo->cfg;
2680 char tunable_name[64];
2683 /* Has to have an intpin to have an interrupt. */
2684 if (cfg->intpin == 0)
2687 /* Let the user override the IRQ with a tunable. */
2688 irq = PCI_INVALID_IRQ;
2689 ksnprintf(tunable_name, sizeof(tunable_name),
2690 "hw.pci%d.%d.%d.INT%c.irq",
2691 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2692 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2693 irq = PCI_INVALID_IRQ;
2696 * If we didn't get an IRQ via the tunable, then we either use the
2697 * IRQ value in the intline register or we ask the bus to route an
2698 * interrupt for us. If force_route is true, then we only use the
2699 * value in the intline register if the bus was unable to assign an
2702 if (!PCI_INTERRUPT_VALID(irq)) {
2703 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2704 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2705 if (!PCI_INTERRUPT_VALID(irq))
2709 /* If after all that we don't have an IRQ, just bail. */
2710 if (!PCI_INTERRUPT_VALID(irq))
2713 /* Update the config register if it changed. */
2714 if (irq != cfg->intline) {
2716 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2719 /* Add this IRQ as rid 0 interrupt resource. */
2720 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
2724 pci_add_resources(device_t pcib, device_t bus, device_t dev, int force, uint32_t prefetchmask)
2726 struct pci_devinfo *dinfo = device_get_ivars(dev);
2727 pcicfgregs *cfg = &dinfo->cfg;
2728 struct resource_list *rl = &dinfo->resources;
2729 struct pci_quirk *q;
2736 /* ATA devices needs special map treatment */
2737 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2738 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
2739 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2740 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2741 !pci_read_config(dev, PCIR_BAR(2), 4))) )
2742 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask);
2744 for (i = 0; i < cfg->nummaps;)
2745 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
2746 rl, force, prefetchmask & (1 << i));
2749 * Add additional, quirked resources.
2751 for (q = &pci_quirks[0]; q->devid; q++) {
2752 if (q->devid == ((cfg->device << 16) | cfg->vendor)
2753 && q->type == PCI_QUIRK_MAP_REG)
2754 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl,
2758 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2759 #ifdef __PCI_REROUTE_INTERRUPT
2761 * Try to re-route interrupts. Sometimes the BIOS or
2762 * firmware may leave bogus values in these registers.
2763 * If the re-route fails, then just stick with what we
2766 pci_assign_interrupt(bus, dev, 1);
2768 pci_assign_interrupt(bus, dev, 0);
2774 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
2776 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
2777 device_t pcib = device_get_parent(dev);
2778 struct pci_devinfo *dinfo;
2780 int s, f, pcifunchigh;
2783 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2784 ("dinfo_size too small"));
2785 maxslots = PCIB_MAXSLOTS(pcib);
2786 for (s = 0; s <= maxslots; s++) {
2790 hdrtype = REG(PCIR_HDRTYPE, 1);
2791 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2793 if (hdrtype & PCIM_MFDEV)
2794 pcifunchigh = PCI_FUNCMAX;
2795 for (f = 0; f <= pcifunchigh; f++) {
2796 dinfo = pci_read_device(pcib, domain, busno, s, f,
2798 if (dinfo != NULL) {
2799 pci_add_child(dev, dinfo);
2807 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2811 pcib = device_get_parent(bus);
2812 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2813 device_set_ivars(dinfo->cfg.dev, dinfo);
2814 resource_list_init(&dinfo->resources);
2815 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2816 pci_cfg_restore(dinfo->cfg.dev, dinfo);
2817 pci_print_verbose(dinfo);
2818 pci_add_resources(pcib, bus, dinfo->cfg.dev, 0, 0);
2822 pci_probe(device_t dev)
2824 device_set_desc(dev, "PCI bus");
2826 /* Allow other subclasses to override this driver. */
2831 pci_attach(device_t dev)
2836 * Since there can be multiple independantly numbered PCI
2837 * busses on systems with multiple PCI domains, we can't use
2838 * the unit number to decide which bus we are probing. We ask
2839 * the parent pcib what our domain and bus numbers are.
2841 domain = pcib_get_domain(dev);
2842 busno = pcib_get_bus(dev);
2844 device_printf(dev, "domain=%d, physical bus=%d\n",
2847 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
2849 return (bus_generic_attach(dev));
2853 pci_suspend(device_t dev)
2855 int dstate, error, i, numdevs;
2856 device_t acpi_dev, child, *devlist;
2857 struct pci_devinfo *dinfo;
2860 * Save the PCI configuration space for each child and set the
2861 * device in the appropriate power state for this sleep state.
2864 if (pci_do_power_resume)
2865 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2866 device_get_children(dev, &devlist, &numdevs);
2867 for (i = 0; i < numdevs; i++) {
2869 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2870 pci_cfg_save(child, dinfo, 0);
2873 /* Suspend devices before potentially powering them down. */
2874 error = bus_generic_suspend(dev);
2876 kfree(devlist, M_TEMP);
2881 * Always set the device to D3. If ACPI suggests a different
2882 * power state, use it instead. If ACPI is not present, the
2883 * firmware is responsible for managing device power. Skip
2884 * children who aren't attached since they are powered down
2885 * separately. Only manage type 0 devices for now.
2887 for (i = 0; acpi_dev && i < numdevs; i++) {
2889 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2890 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
2891 dstate = PCI_POWERSTATE_D3;
2892 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
2893 pci_set_powerstate(child, dstate);
2896 kfree(devlist, M_TEMP);
2901 pci_resume(device_t dev)
2904 device_t acpi_dev, child, *devlist;
2905 struct pci_devinfo *dinfo;
2908 * Set each child to D0 and restore its PCI configuration space.
2911 if (pci_do_power_resume)
2912 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2913 device_get_children(dev, &devlist, &numdevs);
2914 for (i = 0; i < numdevs; i++) {
2916 * Notify ACPI we're going to D0 but ignore the result. If
2917 * ACPI is not present, the firmware is responsible for
2918 * managing device power. Only manage type 0 devices for now.
2921 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2922 if (acpi_dev && device_is_attached(child) &&
2923 dinfo->cfg.hdrtype == 0) {
2924 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
2925 pci_set_powerstate(child, PCI_POWERSTATE_D0);
2928 /* Now the device is powered up, restore its config space. */
2929 pci_cfg_restore(child, dinfo);
2931 kfree(devlist, M_TEMP);
2932 return (bus_generic_resume(dev));
2936 pci_load_vendor_data(void)
2938 caddr_t vendordata, info;
2940 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
2941 info = preload_search_info(vendordata, MODINFO_ADDR);
2942 pci_vendordata = *(char **)info;
2943 info = preload_search_info(vendordata, MODINFO_SIZE);
2944 pci_vendordata_size = *(size_t *)info;
2945 /* terminate the database */
2946 pci_vendordata[pci_vendordata_size] = '\n';
2951 pci_driver_added(device_t dev, driver_t *driver)
2956 struct pci_devinfo *dinfo;
2960 device_printf(dev, "driver added\n");
2961 DEVICE_IDENTIFY(driver, dev);
2962 device_get_children(dev, &devlist, &numdevs);
2963 for (i = 0; i < numdevs; i++) {
2965 if (device_get_state(child) != DS_NOTPRESENT)
2967 dinfo = device_get_ivars(child);
2968 pci_print_verbose(dinfo);
2970 kprintf("pci%d:%d:%d:%d: reprobing on driver added\n",
2971 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2973 pci_cfg_restore(child, dinfo);
2974 if (device_probe_and_attach(child) != 0)
2975 pci_cfg_save(child, dinfo, 1);
2977 kfree(devlist, M_TEMP);
2981 pci_child_detached(device_t parent __unused, device_t child)
2983 /* Turn child's power off */
2984 pci_cfg_save(child, device_get_ivars(child), 1);
2988 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
2989 driver_intr_t *intr, void *arg, void **cookiep, lwkt_serialize_t serializer)
2992 struct pci_devinfo *dinfo;
2993 struct msix_table_entry *mte;
2994 struct msix_vector *mv;
3000 error = bus_generic_setup_intr(dev, child, irq, flags, intr,
3001 arg, &cookie, serializer);
3005 /* If this is not a direct child, just bail out. */
3006 if (device_get_parent(child) != dev) {
3011 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3013 rid = rman_get_rid(irq);
3015 /* Make sure that INTx is enabled */
3016 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3019 * Check to see if the interrupt is MSI or MSI-X.
3020 * Ask our parent to map the MSI and give
3021 * us the address and data register values.
3022 * If we fail for some reason, teardown the
3023 * interrupt handler.
3025 dinfo = device_get_ivars(child);
3026 if (dinfo->cfg.msi.msi_alloc > 0) {
3027 if (dinfo->cfg.msi.msi_addr == 0) {
3028 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
3029 ("MSI has handlers, but vectors not mapped"));
3030 error = PCIB_MAP_MSI(device_get_parent(dev),
3031 child, rman_get_start(irq), &addr, &data);
3034 dinfo->cfg.msi.msi_addr = addr;
3035 dinfo->cfg.msi.msi_data = data;
3036 pci_enable_msi(child, addr, data);
3038 dinfo->cfg.msi.msi_handlers++;
3040 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3041 ("No MSI or MSI-X interrupts allocated"));
3042 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3043 ("MSI-X index too high"));
3044 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3045 KASSERT(mte->mte_vector != 0, ("no message vector"));
3046 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
3047 KASSERT(mv->mv_irq == rman_get_start(irq),
3049 if (mv->mv_address == 0) {
3050 KASSERT(mte->mte_handlers == 0,
3051 ("MSI-X table entry has handlers, but vector not mapped"));
3052 error = PCIB_MAP_MSI(device_get_parent(dev),
3053 child, rman_get_start(irq), &addr, &data);
3056 mv->mv_address = addr;
3059 if (mte->mte_handlers == 0) {
3060 pci_enable_msix(child, rid - 1, mv->mv_address,
3062 pci_unmask_msix(child, rid - 1);
3064 mte->mte_handlers++;
3067 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3068 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3071 (void)bus_generic_teardown_intr(dev, child, irq,
3082 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3086 struct msix_table_entry *mte;
3087 struct resource_list_entry *rle;
3088 struct pci_devinfo *dinfo;
3092 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3095 /* If this isn't a direct child, just bail out */
3096 if (device_get_parent(child) != dev)
3097 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3099 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3101 rid = rman_get_rid(irq);
3104 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3107 * Check to see if the interrupt is MSI or MSI-X. If so,
3108 * decrement the appropriate handlers count and mask the
3109 * MSI-X message, or disable MSI messages if the count
3112 dinfo = device_get_ivars(child);
3113 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
3114 if (rle->res != irq)
3116 if (dinfo->cfg.msi.msi_alloc > 0) {
3117 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
3118 ("MSI-X index too high"));
3119 if (dinfo->cfg.msi.msi_handlers == 0)
3121 dinfo->cfg.msi.msi_handlers--;
3122 if (dinfo->cfg.msi.msi_handlers == 0)
3123 pci_disable_msi(child);
3125 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3126 ("No MSI or MSI-X interrupts allocated"));
3127 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3128 ("MSI-X index too high"));
3129 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3130 if (mte->mte_handlers == 0)
3132 mte->mte_handlers--;
3133 if (mte->mte_handlers == 0)
3134 pci_mask_msix(child, rid - 1);
3137 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3140 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3142 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3147 pci_print_child(device_t dev, device_t child)
3149 struct pci_devinfo *dinfo;
3150 struct resource_list *rl;
3153 dinfo = device_get_ivars(child);
3154 rl = &dinfo->resources;
3156 retval += bus_print_child_header(dev, child);
3158 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3159 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3160 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3161 if (device_get_flags(dev))
3162 retval += kprintf(" flags %#x", device_get_flags(dev));
3164 retval += kprintf(" at device %d.%d", pci_get_slot(child),
3165 pci_get_function(child));
3167 retval += bus_print_child_footer(dev, child);
3177 } pci_nomatch_tab[] = {
3178 {PCIC_OLD, -1, "old"},
3179 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3180 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3181 {PCIC_STORAGE, -1, "mass storage"},
3182 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3183 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3184 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3185 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3186 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3187 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3188 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3189 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3190 {PCIC_NETWORK, -1, "network"},
3191 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3192 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3193 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3194 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3195 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3196 {PCIC_DISPLAY, -1, "display"},
3197 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3198 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3199 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3200 {PCIC_MULTIMEDIA, -1, "multimedia"},
3201 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3202 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3203 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3204 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3205 {PCIC_MEMORY, -1, "memory"},
3206 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3207 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3208 {PCIC_BRIDGE, -1, "bridge"},
3209 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3210 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3211 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3212 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3213 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3214 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3215 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3216 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3217 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3218 {PCIC_SIMPLECOMM, -1, "simple comms"},
3219 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3220 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3221 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3222 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3223 {PCIC_BASEPERIPH, -1, "base peripheral"},
3224 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3225 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3226 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3227 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3228 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3229 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3230 {PCIC_INPUTDEV, -1, "input device"},
3231 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3232 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3233 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3234 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3235 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3236 {PCIC_DOCKING, -1, "docking station"},
3237 {PCIC_PROCESSOR, -1, "processor"},
3238 {PCIC_SERIALBUS, -1, "serial bus"},
3239 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3240 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3241 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3242 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3243 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3244 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3245 {PCIC_WIRELESS, -1, "wireless controller"},
3246 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3247 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3248 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3249 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3250 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3251 {PCIC_SATCOM, -1, "satellite communication"},
3252 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3253 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3254 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3255 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3256 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3257 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3258 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3259 {PCIC_DASP, -1, "dasp"},
3260 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3265 pci_probe_nomatch(device_t dev, device_t child)
3268 char *cp, *scp, *device;
3271 * Look for a listing for this device in a loaded device database.
3273 if ((device = pci_describe_device(child)) != NULL) {
3274 device_printf(dev, "<%s>", device);
3275 kfree(device, M_DEVBUF);
3278 * Scan the class/subclass descriptions for a general
3283 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3284 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3285 if (pci_nomatch_tab[i].subclass == -1) {
3286 cp = pci_nomatch_tab[i].desc;
3287 } else if (pci_nomatch_tab[i].subclass ==
3288 pci_get_subclass(child)) {
3289 scp = pci_nomatch_tab[i].desc;
3293 device_printf(dev, "<%s%s%s>",
3295 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3298 kprintf(" at device %d.%d (no driver attached)\n",
3299 pci_get_slot(child), pci_get_function(child));
3300 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
3305 * Parse the PCI device database, if loaded, and return a pointer to a
3306 * description of the device.
3308 * The database is flat text formatted as follows:
3310 * Any line not in a valid format is ignored.
3311 * Lines are terminated with newline '\n' characters.
3313 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3316 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3317 * - devices cannot be listed without a corresponding VENDOR line.
3318 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3319 * another TAB, then the device name.
3323 * Assuming (ptr) points to the beginning of a line in the database,
3324 * return the vendor or device and description of the next entry.
3325 * The value of (vendor) or (device) inappropriate for the entry type
3326 * is set to -1. Returns nonzero at the end of the database.
3328 * Note that this is slightly unrobust in the face of corrupt data;
3329 * we attempt to safeguard against this by spamming the end of the
3330 * database with a newline when we initialise.
3333 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3342 left = pci_vendordata_size - (cp - pci_vendordata);
3350 ksscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3354 ksscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3357 /* skip to next line */
3358 while (*cp != '\n' && left > 0) {
3367 /* skip to next line */
3368 while (*cp != '\n' && left > 0) {
3372 if (*cp == '\n' && left > 0)
3379 pci_describe_device(device_t dev)
3382 char *desc, *vp, *dp, *line;
3384 desc = vp = dp = NULL;
3387 * If we have no vendor data, we can't do anything.
3389 if (pci_vendordata == NULL)
3393 * Scan the vendor data looking for this device
3395 line = pci_vendordata;
3396 if ((vp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3399 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3401 if (vendor == pci_get_vendor(dev))
3404 if ((dp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3407 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3415 if (device == pci_get_device(dev))
3419 ksnprintf(dp, 80, "0x%x", pci_get_device(dev));
3420 if ((desc = kmalloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3422 ksprintf(desc, "%s, %s", vp, dp);
3425 kfree(vp, M_DEVBUF);
3427 kfree(dp, M_DEVBUF);
3432 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3434 struct pci_devinfo *dinfo;
3437 dinfo = device_get_ivars(child);
3441 case PCI_IVAR_ETHADDR:
3443 * The generic accessor doesn't deal with failure, so
3444 * we set the return value, then return an error.
3446 *((uint8_t **) result) = NULL;
3448 case PCI_IVAR_SUBVENDOR:
3449 *result = cfg->subvendor;
3451 case PCI_IVAR_SUBDEVICE:
3452 *result = cfg->subdevice;
3454 case PCI_IVAR_VENDOR:
3455 *result = cfg->vendor;
3457 case PCI_IVAR_DEVICE:
3458 *result = cfg->device;
3460 case PCI_IVAR_DEVID:
3461 *result = (cfg->device << 16) | cfg->vendor;
3463 case PCI_IVAR_CLASS:
3464 *result = cfg->baseclass;
3466 case PCI_IVAR_SUBCLASS:
3467 *result = cfg->subclass;
3469 case PCI_IVAR_PROGIF:
3470 *result = cfg->progif;
3472 case PCI_IVAR_REVID:
3473 *result = cfg->revid;
3475 case PCI_IVAR_INTPIN:
3476 *result = cfg->intpin;
3479 *result = cfg->intline;
3481 case PCI_IVAR_DOMAIN:
3482 *result = cfg->domain;
3488 *result = cfg->slot;
3490 case PCI_IVAR_FUNCTION:
3491 *result = cfg->func;
3493 case PCI_IVAR_CMDREG:
3494 *result = cfg->cmdreg;
3496 case PCI_IVAR_CACHELNSZ:
3497 *result = cfg->cachelnsz;
3499 case PCI_IVAR_MINGNT:
3500 *result = cfg->mingnt;
3502 case PCI_IVAR_MAXLAT:
3503 *result = cfg->maxlat;
3505 case PCI_IVAR_LATTIMER:
3506 *result = cfg->lattimer;
3515 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3517 struct pci_devinfo *dinfo;
3519 dinfo = device_get_ivars(child);
3522 case PCI_IVAR_INTPIN:
3523 dinfo->cfg.intpin = value;
3525 case PCI_IVAR_ETHADDR:
3526 case PCI_IVAR_SUBVENDOR:
3527 case PCI_IVAR_SUBDEVICE:
3528 case PCI_IVAR_VENDOR:
3529 case PCI_IVAR_DEVICE:
3530 case PCI_IVAR_DEVID:
3531 case PCI_IVAR_CLASS:
3532 case PCI_IVAR_SUBCLASS:
3533 case PCI_IVAR_PROGIF:
3534 case PCI_IVAR_REVID:
3536 case PCI_IVAR_DOMAIN:
3539 case PCI_IVAR_FUNCTION:
3540 return (EINVAL); /* disallow for now */
3547 #include "opt_ddb.h"
3549 #include <ddb/ddb.h>
3550 #include <sys/cons.h>
3553 * List resources based on pci map registers, used for within ddb
3556 DB_SHOW_COMMAND(pciregs, db_pci_dump)
3558 struct pci_devinfo *dinfo;
3559 struct devlist *devlist_head;
3562 int i, error, none_count;
3565 /* get the head of the device queue */
3566 devlist_head = &pci_devq;
3569 * Go through the list of devices and print out devices
3571 for (error = 0, i = 0,
3572 dinfo = STAILQ_FIRST(devlist_head);
3573 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3574 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3576 /* Populate pd_name and pd_unit */
3579 name = device_get_name(dinfo->cfg.dev);
3582 db_kprintf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3583 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3584 (name && *name) ? name : "none",
3585 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3587 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3588 p->pc_sel.pc_func, (p->pc_class << 16) |
3589 (p->pc_subclass << 8) | p->pc_progif,
3590 (p->pc_subdevice << 16) | p->pc_subvendor,
3591 (p->pc_device << 16) | p->pc_vendor,
3592 p->pc_revid, p->pc_hdr);
3598 static struct resource *
3599 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3600 u_long start, u_long end, u_long count, u_int flags)
3602 struct pci_devinfo *dinfo = device_get_ivars(child);
3603 struct resource_list *rl = &dinfo->resources;
3604 struct resource_list_entry *rle;
3605 struct resource *res;
3606 pci_addr_t map, testval;
3610 * Weed out the bogons, and figure out how large the BAR/map
3611 * is. Bars that read back 0 here are bogus and unimplemented.
3612 * Note: atapci in legacy mode are special and handled elsewhere
3613 * in the code. If you have a atapci device in legacy mode and
3614 * it fails here, that other code is broken.
3617 map = pci_read_config(child, *rid, 4);
3618 pci_write_config(child, *rid, 0xffffffff, 4);
3619 testval = pci_read_config(child, *rid, 4);
3620 if (pci_maprange(testval) == 64)
3621 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
3622 if (pci_mapbase(testval) == 0)
3626 * Restore the original value of the BAR. We may have reprogrammed
3627 * the BAR of the low-level console device and when booting verbose,
3628 * we need the console device addressable.
3630 pci_write_config(child, *rid, map, 4);
3632 if (PCI_BAR_MEM(testval)) {
3633 if (type != SYS_RES_MEMORY) {
3636 "child %s requested type %d for rid %#x,"
3637 " but the BAR says it is an memio\n",
3638 device_get_nameunit(child), type, *rid);
3642 if (type != SYS_RES_IOPORT) {
3645 "child %s requested type %d for rid %#x,"
3646 " but the BAR says it is an ioport\n",
3647 device_get_nameunit(child), type, *rid);
3652 * For real BARs, we need to override the size that
3653 * the driver requests, because that's what the BAR
3654 * actually uses and we would otherwise have a
3655 * situation where we might allocate the excess to
3656 * another driver, which won't work.
3658 mapsize = pci_mapsize(testval);
3659 count = 1UL << mapsize;
3660 if (RF_ALIGNMENT(flags) < mapsize)
3661 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3662 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3663 flags |= RF_PREFETCHABLE;
3666 * Allocate enough resource, and then write back the
3667 * appropriate bar for that resource.
3669 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
3670 start, end, count, flags);
3672 device_printf(child,
3673 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3674 count, *rid, type, start, end);
3677 resource_list_add(rl, type, *rid, start, end, count);
3678 rle = resource_list_find(rl, type, *rid);
3680 panic("pci_alloc_map: unexpectedly can't find resource.");
3682 rle->start = rman_get_start(res);
3683 rle->end = rman_get_end(res);
3686 device_printf(child,
3687 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3688 count, *rid, type, rman_get_start(res));
3689 map = rman_get_start(res);
3691 pci_write_config(child, *rid, map, 4);
3692 if (pci_maprange(testval) == 64)
3693 pci_write_config(child, *rid + 4, map >> 32, 4);
3699 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
3700 u_long start, u_long end, u_long count, u_int flags)
3702 struct pci_devinfo *dinfo = device_get_ivars(child);
3703 struct resource_list *rl = &dinfo->resources;
3704 struct resource_list_entry *rle;
3705 pcicfgregs *cfg = &dinfo->cfg;
3706 //kprintf("%s on %s: requesting resource\n", device_get_desc(child), device_get_desc(dev));
3708 * Perform lazy resource allocation
3710 if (device_get_parent(child) == dev) {
3714 * Can't alloc legacy interrupt once MSI messages
3715 * have been allocated.
3718 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3719 cfg->msix.msix_alloc > 0))
3723 * If the child device doesn't have an
3724 * interrupt routed and is deserving of an
3725 * interrupt, try to assign it one.
3727 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3729 pci_assign_interrupt(dev, child, 0);
3731 case SYS_RES_IOPORT:
3732 case SYS_RES_MEMORY:
3733 if (*rid < PCIR_BAR(cfg->nummaps)) {
3735 * Enable the I/O mode. We should
3736 * also be assigning resources too
3737 * when none are present. The
3738 * resource_list_alloc kind of sorta does
3741 if (PCI_ENABLE_IO(dev, child, type))
3744 rle = resource_list_find(rl, type, *rid);
3746 return (pci_alloc_map(dev, child, type, rid,
3747 start, end, count, flags));
3751 * If we've already allocated the resource, then
3752 * return it now. But first we may need to activate
3753 * it, since we don't allocate the resource as active
3754 * above. Normally this would be done down in the
3755 * nexus, but since we short-circuit that path we have
3756 * to do its job here. Not sure if we should kfree the
3757 * resource if it fails to activate.
3759 rle = resource_list_find(rl, type, *rid);
3760 if (rle != NULL && rle->res != NULL) {
3762 device_printf(child,
3763 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
3764 rman_get_size(rle->res), *rid, type,
3765 rman_get_start(rle->res));
3766 if ((flags & RF_ACTIVE) &&
3767 bus_generic_activate_resource(dev, child, type,
3768 *rid, rle->res) != 0)
3773 return (resource_list_alloc(rl, dev, child, type, rid,
3774 start, end, count, flags));
3778 pci_delete_resource(device_t dev, device_t child, int type, int rid)
3780 struct pci_devinfo *dinfo;
3781 struct resource_list *rl;
3782 struct resource_list_entry *rle;
3784 if (device_get_parent(child) != dev)
3787 dinfo = device_get_ivars(child);
3788 rl = &dinfo->resources;
3789 rle = resource_list_find(rl, type, rid);
3792 if (rman_get_device(rle->res) != dev ||
3793 rman_get_flags(rle->res) & RF_ACTIVE) {
3794 device_printf(dev, "delete_resource: "
3795 "Resource still owned by child, oops. "
3796 "(type=%d, rid=%d, addr=%lx)\n",
3797 rle->type, rle->rid,
3798 rman_get_start(rle->res));
3801 bus_release_resource(dev, type, rid, rle->res);
3803 resource_list_delete(rl, type, rid);
3806 * Why do we turn off the PCI configuration BAR when we delete a
3809 pci_write_config(child, rid, 0, 4);
3810 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
3813 struct resource_list *
3814 pci_get_resource_list (device_t dev, device_t child)
3816 struct pci_devinfo *dinfo = device_get_ivars(child);
3821 return (&dinfo->resources);
3825 pci_read_config_method(device_t dev, device_t child, int reg, int width)
3827 struct pci_devinfo *dinfo = device_get_ivars(child);
3828 pcicfgregs *cfg = &dinfo->cfg;
3830 return (PCIB_READ_CONFIG(device_get_parent(dev),
3831 cfg->bus, cfg->slot, cfg->func, reg, width));
3835 pci_write_config_method(device_t dev, device_t child, int reg,
3836 uint32_t val, int width)
3838 struct pci_devinfo *dinfo = device_get_ivars(child);
3839 pcicfgregs *cfg = &dinfo->cfg;
3841 PCIB_WRITE_CONFIG(device_get_parent(dev),
3842 cfg->bus, cfg->slot, cfg->func, reg, val, width);
3846 pci_child_location_str_method(device_t dev, device_t child, char *buf,
3850 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
3851 pci_get_function(child));
3856 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
3859 struct pci_devinfo *dinfo;
3862 dinfo = device_get_ivars(child);
3864 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
3865 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
3866 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
3872 pci_assign_interrupt_method(device_t dev, device_t child)
3874 struct pci_devinfo *dinfo = device_get_ivars(child);
3875 pcicfgregs *cfg = &dinfo->cfg;
3877 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
3882 pci_modevent(module_t mod, int what, void *arg)
3884 static struct cdev *pci_cdev;
3885 extern struct dev_ops pcic_ops;
3889 STAILQ_INIT(&pci_devq);
3891 dev_ops_add(&pcic_ops, -1, 0);
3892 pci_cdev = make_dev(&pcic_ops, 0, UID_ROOT, GID_WHEEL, 0644,
3894 pci_load_vendor_data();
3898 destroy_dev(pci_cdev);
3906 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
3911 * Only do header type 0 devices. Type 1 devices are bridges,
3912 * which we know need special treatment. Type 2 devices are
3913 * cardbus bridges which also require special treatment.
3914 * Other types are unknown, and we err on the side of safety
3917 if (dinfo->cfg.hdrtype != 0)
3921 * Restore the device to full power mode. We must do this
3922 * before we restore the registers because moving from D3 to
3923 * D0 will cause the chip's BARs and some other registers to
3924 * be reset to some unknown power on reset values. Cut down
3925 * the noise on boot by doing nothing if we are already in
3928 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
3929 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
3931 for (i = 0; i < dinfo->cfg.nummaps; i++)
3932 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
3933 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
3934 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
3935 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
3936 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
3937 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
3938 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
3939 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
3940 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
3941 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
3942 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
3944 /* Restore MSI and MSI-X configurations if they are present. */
3945 if (dinfo->cfg.msi.msi_location != 0)
3946 pci_resume_msi(dev);
3947 if (dinfo->cfg.msix.msix_location != 0)
3948 pci_resume_msix(dev);
3952 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
3959 * Only do header type 0 devices. Type 1 devices are bridges, which
3960 * we know need special treatment. Type 2 devices are cardbus bridges
3961 * which also require special treatment. Other types are unknown, and
3962 * we err on the side of safety by ignoring them. Powering down
3963 * bridges should not be undertaken lightly.
3965 if (dinfo->cfg.hdrtype != 0)
3967 for (i = 0; i < dinfo->cfg.nummaps; i++)
3968 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
3969 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
3972 * Some drivers apparently write to these registers w/o updating our
3973 * cached copy. No harm happens if we update the copy, so do so here
3974 * so we can restore them. The COMMAND register is modified by the
3975 * bus w/o updating the cache. This should represent the normally
3976 * writable portion of the 'defined' part of type 0 headers. In
3977 * theory we also need to save/restore the PCI capability structures
3978 * we know about, but apart from power we don't know any that are
3981 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
3982 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
3983 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
3984 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
3985 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
3986 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
3987 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
3988 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
3989 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
3990 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3991 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3992 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
3993 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
3994 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
3995 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
3998 * don't set the state for display devices, base peripherals and
3999 * memory devices since bad things happen when they are powered down.
4000 * We should (a) have drivers that can easily detach and (b) use
4001 * generic drivers for these devices so that some device actually
4002 * attaches. We need to make sure that when we implement (a) we don't
4003 * power the device down on a reattach.
4005 cls = pci_get_class(dev);
4008 switch (pci_do_power_nodriver)
4010 case 0: /* NO powerdown at all */
4012 case 1: /* Conservative about what to power down */
4013 if (cls == PCIC_STORAGE)
4016 case 2: /* Agressive about what to power down */
4017 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
4018 cls == PCIC_BASEPERIPH)
4021 case 3: /* Power down everything */
4025 * PCI spec says we can only go into D3 state from D0 state.
4026 * Transition from D[12] into D0 before going to D3 state.
4028 ps = pci_get_powerstate(dev);
4029 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
4030 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4031 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
4032 pci_set_powerstate(dev, PCI_POWERSTATE_D3);