2 * Copyright (c) 2003,2004 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Matthew Dillon <dillon@backplane.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * Copyright (c) 1996, by Peter Wemm and Steve Passe, All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. The name of the developer may NOT be used to endorse or promote products
42 * derived from this software without specific prior written permission.
44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
45 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
47 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
56 * $FreeBSD: src/sys/i386/include/apic.h,v 1.14.2.2 2003/03/21 21:46:15 jhb Exp $
57 * $DragonFly: src/sys/platform/pc32/apic/apicreg.h,v 1.3 2004/07/16 05:48:46 dillon Exp $
60 #ifndef _MACHINE_APICREG_H_
61 #define _MACHINE_APICREG_H_
64 * Local && I/O APIC definitions for Pentium P54C+ Built-in APIC.
66 * A per-cpu APIC resides in memory location 0xFEE00000.
68 * 31 ... 24 23 ... 16 15 ... 8 7 ... 0
69 * +-----------+-----------+-----------+-----------+
72 * +-----------+-----------+-----------+-----------+
74 * +-----------+-----------+-----------+-----------+
75 * 0020 ID | | ID | | | | RW
76 * +-----------+-----------+-----------+-----------+
78 * The physical APIC ID is used with physical interrupt
81 * +-----------+-----------+-----------+-----------+
83 * +-----------+-----------+-----------+-----------+
88 * +-----------+-----------+-----------+-----------+
89 * 0080 TPR | | | | PRIO SUBC |
92 * +-----------+-----------+-----------+-----------+
94 * The Task Priority Register provides a priority threshold
95 * mechanism for interrupting the processor. Only interrupts
96 * with a higher priority then that specified in the TPR will
97 * be served. Other interrupts are recorded and serviced
98 * as soon as the TPR value decreases enough to allow that
99 * (unless EOId by another APIC).
101 * PRIO (7:4). Main priority. If 15 the APIC will not
102 * accept any interrupts.
103 * SUBC (3:0) Sub priority. See APR/PPR.
106 * The Processor Priority Register determines whether a
107 * pending interrupt can be dispensed to the processor. ISRV
108 * Is the vector of the highest priority ISR bit set or
109 * zero if no ISR bit is set.
111 * IF TPR[7:4] >= ISRV[7:4]
112 * PPR[7:0] = TPR[7:0]
114 * PPR[7:0] = ISRV[7:4].000
116 * The Arbitration Priority Register holds the current
117 * lowest priority of the procsesor, a value used during
118 * lowest-priority arbitration.
120 * IF (TPR[7:4] >= IRRV[7:4] AND TPR[7:4] > ISRV[7:4])
121 * APR[7:0] = TPR[7:0]
123 * APR[7:4] = max((TPR[7:4]&ISRV[7:4]),IRRV[7:4]).000
125 * +-----------+-----------+-----------+-----------+
127 * +-----------+-----------+-----------+-----------+
129 * +-----------+-----------+-----------+-----------+
130 * 00D0 LDR |LOG APICID | | | |
131 * +-----------+-----------+-----------+-----------+
132 * 00E0 DFR |MODEL| | | | |
133 * +-----------+-----------+-----------+-----------+
135 * The logical APIC ID is used with logical interrupt
136 * delivery modes. Interpretation of logical destination
137 * information depends on the MODEL bits in the Destination
140 * MODEL=1111 FLAT MODEL - The MDA is interpreted as
141 * a decoded address. By setting
142 * one bit in the LDR for each
143 * local apic 8 APICs can coexist.
145 * MODEL=0000 CLUSTER MODEL -
147 * 31 ... 24 23 ... 16 15 ... 8 7 ... 0
148 * +-----------+-----------+-----------+-----------+
150 * +-----------+-----------+-----------+-----------+
151 * 0100-0170 ISR| | | | |
152 * 0180-01F0 TMR| | | | |
153 * 0200-0270 IRR| | | | |
154 * +-----------+-----------+-----------+-----------+
156 * These registers represent 256 bits, one bit for each
157 * possible interrupt. Interrupts 0-15 are reserved so
158 * bits 0-15 are also reserved.
160 * TMR - Trigger mode register. Upon acceptance of an int
161 * the corresponding bit is cleared for edge-trig and
162 * set for level-trig. If the TMR bit is set (level),
163 * the local APIC sends an EOI to all I/O APICs as
164 * a result of software issuing an EOI command.
166 * IRR - Interrupt Request Register. Contains active
167 * interrupt requests that have been accepted but not
168 * yet dispensed by the current local APIC. The bit is
169 * cleared and the corresponding ISR bit is set when
170 * the INTA cycle is issued.
172 * ISR - Interrupt In-Service register. Interrupt has been
173 * delivered but not yet fully serviced. Cleared when
174 * an EOI is issued from the processor. An EOI will
175 * also send an EOI to all I/O APICs if TMR was set.
177 * +-----------+-----------+-----------+-----------+
179 * 0290-02F0 | | | | |
180 * +--FEDCBA98-+--76543210-+--FEDCBA98-+-----------+
181 * 0300 ICR_LO | | XX | TL SDMMM | vector |
182 * 0310 ICR_HI | DEST FIELD| | | |
183 * +-----------+-----------+-----------+-----------+
185 * The interrupt command register. Generally speaking
186 * writing to ICR_LO initiates a command. All fields
187 * are R/W except the 'S' (delivery status) field, which
191 * XX: Destination Shorthand field:
193 * 00 Use Destination field
194 * 01 Self only. Dest field ignored.
195 * 10 All including self (uses a
196 * destination field of 0x0F)
197 * 11 All excluding self (uses a
198 * destination field of 0x0F)
200 * T: 1 = Level 0 = Edge Trigger modde, used for
201 * the INIT level de-assert delivery mode only
202 * to de-assert a request.
204 * L: 0 = De-Assert, 1 = Assert. Always write as
205 * 1 when initiating a new command. Can only
206 * write as 0 for INIT mode de-assertion of
209 * S: 1 = Send Pending. Interrupt has been injected
210 * but APIC has not yet accepted it.
212 * D: 0=physical 1=logical. In physical mode
213 * only 24-27 of DEST FIELD is used from ICR_HI.
215 * MMM: 000 Fixed. Deliver to all processors according
216 * to the ICR. Always treated as edge trig.
218 * 001 Lowest Priority. Deliver to just the
219 * processor running at the lowest priority.
221 * 010 SMI. The vector must be 00B. Only edge
222 * triggered is allowed. The vector field
223 * must be programmed to zero (huh?).
227 * 100 NMI. Deliver as an NMI to all processors
228 * listed in the destination field. The
229 * vector is ignored. Alawys treated as
232 * 101 INIT. Deliver as an INIT signal to all
233 * processors (like FIXED). Vector is ignored
234 * and it is always edge-triggered.
236 * 110 Start Up. Sends a special message between
237 * cpus. the vector contains a start-up
238 * address for MP boot protocol.
239 * Always edge triggered. Note: a startup
240 * int is not automatically tried in case of
245 * +-----------+--------10-+--FEDCBA98-+-----------+
246 * 0320 LTIMER | | TM | ---S---- | vector |
248 * +-----------+--------10-+--FEDCBA98-+-----------+
249 * 0340 LVPCINT | | -M | ---S-MMM | vector |
250 * 0350 LVINT0 | | -M | LRPS-MMM | vector |
251 * 0360 LVINT1 | | -M | LRPS-MMM | vector |
252 * 0370 LVERROR | | -M | -------- | vector |
253 * +-----------+-----------+-----------+-----------+
255 * T: 1 = periodic, 0 = one-shot
259 * L: 1 = level, 0 = edge
261 * R: For level triggered only, set to 1 when a
262 * level int is accepted, cleared by EOI.
264 * P: Pin Polarity 0 = Active High, 1 = Active Low
266 * S: 1 = Send Pending. Interrupt has been injected
267 * but APIC has not yet accepted it.
269 * MMM 000 = Fixed deliver to cpu according to LVT
271 * MMM 100 = NMI deliver as an NMI. Always edge
273 * MMM 111 = ExtInt deliver from 8259, routes INTA
274 * bus cycle to external
275 * controller. Controller is
276 * expected to supply vector.
279 * +-----------+-----------+-----------+-----------+
280 * 0380 TMR_ICR | | | | |
281 * 0390 TMR_CCR | | | | |
286 * 03E0 TMR_DCR | | | | |
287 * +-----------+-----------+-----------+-----------+
289 * Timer control and access registers.
292 * NOTE ON EOI: Upon receiving an EOI the APIC clears the highest priority
293 * interrupt in the ISR and selects the next highest priority interrupt
294 * for posting to the CPU. If the interrupt being EOId was level
295 * triggered the APIC will send an EOI to all I/O APICs. For the moment
296 * you can write garbage to the EOI register but for future compatibility
297 * 0 should be written.
301 #include <sys/types.h>
303 #define PAD3 int : 32; int : 32; int : 32
304 #define PAD4 int : 32; int : 32; int : 32; int : 32
309 u_int32_t id; PAD3; /* 0020 R/W */
310 u_int32_t version; PAD3; /* 0030 RO */
323 u_int32_t isr0; PAD3;
324 u_int32_t isr1; PAD3;
325 u_int32_t isr2; PAD3;
326 u_int32_t isr3; PAD3;
327 u_int32_t isr4; PAD3;
328 u_int32_t isr5; PAD3;
329 u_int32_t isr6; PAD3;
330 u_int32_t isr7; PAD3;
331 u_int32_t tmr0; PAD3;
332 u_int32_t tmr1; PAD3;
333 u_int32_t tmr2; PAD3;
334 u_int32_t tmr3; PAD3;
335 u_int32_t tmr4; PAD3;
336 u_int32_t tmr5; PAD3;
337 u_int32_t tmr6; PAD3;
338 u_int32_t tmr7; PAD3;
339 u_int32_t irr0; PAD3;
340 u_int32_t irr1; PAD3;
341 u_int32_t irr2; PAD3;
342 u_int32_t irr3; PAD3;
343 u_int32_t irr4; PAD3;
344 u_int32_t irr5; PAD3;
345 u_int32_t irr6; PAD3;
346 u_int32_t irr7; PAD3;
355 u_int32_t icr_lo; PAD3;
356 u_int32_t icr_hi; PAD3;
357 u_int32_t lvt_timer; PAD3;
359 u_int32_t lvt_pcint; PAD3;
360 u_int32_t lvt_lint0; PAD3;
361 u_int32_t lvt_lint1; PAD3;
362 u_int32_t lvt_error; PAD3;
363 u_int32_t icr_timer; PAD3;
364 u_int32_t ccr_timer; PAD3;
369 u_int32_t dcr_timer; PAD3;
373 typedef struct LAPIC lapic_t;
375 /******************************************************************************
380 u_int32_t ioregsel; PAD3;
381 u_int32_t iowin; PAD3;
384 typedef struct IOAPIC ioapic_t;
392 /******************************************************************************
393 * various code 'logical' values
397 #define LOPRIO_LEVEL 0x00000010 /* TPR of CPU accepting INTs */
398 #define ALLHWI_LEVEL 0x00000000 /* TPR of CPU grabbing INTs */
399 #endif /** GRAB_LOPRIO */
402 * XXX This code assummes that the reserved field of the
403 * local APIC TPR can be written with all 0s.
404 * This saves quite a few memory accesses.
405 * If the silicon ever changes then things will break!
406 * It affects mplock.s, swtch.s, and possibly other files.
411 /******************************************************************************
415 /* default physical locations of LOCAL (CPU) APICs */
416 #define DEFAULT_APIC_BASE 0xfee00000
419 #define APIC_VER_VERSION 0x000000ff
420 #define APIC_VER_MAXLVT 0x00ff0000
421 #define MAXLVTSHIFT 16
424 #define APIC_SVR_VECTOR 0x000000ff
425 #define APIC_SVR_VEC_PROG 0x000000f0
426 #define APIC_SVR_VEC_FIX 0x0000000f
427 #define APIC_SVR_ENABLE 0x00000100
428 # define APIC_SVR_SWDIS 0x00000000
429 # define APIC_SVR_SWEN 0x00000100
430 #define APIC_SVR_FOCUS 0x00000200
431 # define APIC_SVR_FEN 0x00000000
432 # define APIC_SVR_FDIS 0x00000200
435 #define APIC_TPR_PRIO 0x000000ff
436 # define APIC_TPR_INT 0x000000f0
437 # define APIC_TPR_SUB 0x0000000f
440 /* fields in ICR_LOW */
441 #define APIC_VECTOR_MASK 0x000000ff
443 #define APIC_DELMODE_MASK 0x00000700
444 # define APIC_DELMODE_FIXED 0x00000000
445 # define APIC_DELMODE_LOWPRIO 0x00000100
446 # define APIC_DELMODE_SMI 0x00000200
447 # define APIC_DELMODE_RR 0x00000300
448 # define APIC_DELMODE_NMI 0x00000400
449 # define APIC_DELMODE_INIT 0x00000500
450 # define APIC_DELMODE_STARTUP 0x00000600
451 # define APIC_DELMODE_RESV 0x00000700
453 #define APIC_DESTMODE_MASK 0x00000800
454 # define APIC_DESTMODE_PHY 0x00000000
455 # define APIC_DESTMODE_LOG 0x00000800
457 #define APIC_DELSTAT_MASK 0x00001000
458 # define APIC_DELSTAT_IDLE 0x00000000
459 # define APIC_DELSTAT_PEND 0x00001000
461 #define APIC_RESV1_MASK 0x00002000
463 #define APIC_LEVEL_MASK 0x00004000
464 # define APIC_LEVEL_DEASSERT 0x00000000
465 # define APIC_LEVEL_ASSERT 0x00004000
467 #define APIC_TRIGMOD_MASK 0x00008000
468 # define APIC_TRIGMOD_EDGE 0x00000000
469 # define APIC_TRIGMOD_LEVEL 0x00008000
471 #define APIC_RRSTAT_MASK 0x00030000
472 # define APIC_RRSTAT_INVALID 0x00000000
473 # define APIC_RRSTAT_INPROG 0x00010000
474 # define APIC_RRSTAT_VALID 0x00020000
475 # define APIC_RRSTAT_RESV 0x00030000
477 #define APIC_DEST_MASK 0x000c0000
478 # define APIC_DEST_DESTFLD 0x00000000
479 # define APIC_DEST_SELF 0x00040000
480 # define APIC_DEST_ALLISELF 0x00080000
481 # define APIC_DEST_ALLESELF 0x000c0000
483 #define APIC_RESV2_MASK 0xfff00000
486 /* fields in ICR_HIGH */
487 #define APIC_ID_MASK 0xff000000
490 /* fields in LVT1/2 */
491 #define APIC_LVT_VECTOR 0x000000ff
492 #define APIC_LVT_DM 0x00000700
493 # define APIC_LVT_DM_FIXED 0x00000000
494 # define APIC_LVT_DM_NMI 0x00000400
495 # define APIC_LVT_DM_EXTINT 0x00000700
496 #define APIC_LVT_DS 0x00001000
497 #define APIC_LVT_IIPP 0x00002000
498 #define APIC_LVT_IIPP_INTALO 0x00002000
499 #define APIC_LVT_IIPP_INTAHI 0x00000000
500 #define APIC_LVT_RIRR 0x00004000
501 #define APIC_LVT_TM 0x00008000
502 #define APIC_LVT_M 0x00010000
505 /* fields in LVT Timer */
506 #define APIC_LVTT_VECTOR 0x000000ff
507 #define APIC_LVTT_DS 0x00001000
508 #define APIC_LVTT_M 0x00010000
509 #define APIC_LVTT_TM 0x00020000
513 #define APIC_TDCR_2 0x00
514 #define APIC_TDCR_4 0x01
515 #define APIC_TDCR_8 0x02
516 #define APIC_TDCR_16 0x03
517 #define APIC_TDCR_32 0x08
518 #define APIC_TDCR_64 0x09
519 #define APIC_TDCR_128 0x0a
520 #define APIC_TDCR_1 0x0b
525 * ISA INTerrupts are in bits 16-31 of the 1st IRR register.
526 * these masks DON'T EQUAL the isa IRQs of the same name.
528 #define APIC_IRQ0 0x00000001
529 #define APIC_IRQ1 0x00000002
530 #define APIC_IRQ2 0x00000004
531 #define APIC_IRQ3 0x00000008
532 #define APIC_IRQ4 0x00000010
533 #define APIC_IRQ5 0x00000020
534 #define APIC_IRQ6 0x00000040
535 #define APIC_IRQ7 0x00000080
536 #define APIC_IRQ8 0x00000100
537 #define APIC_IRQ9 0x00000200
538 #define APIC_IRQ10 0x00000400
539 #define APIC_IRQ11 0x00000800
540 #define APIC_IRQ12 0x00001000
541 #define APIC_IRQ13 0x00002000
542 #define APIC_IRQ14 0x00004000
543 #define APIC_IRQ15 0x00008000
544 #define APIC_IRQ16 0x00010000
545 #define APIC_IRQ17 0x00020000
546 #define APIC_IRQ18 0x00040000
547 #define APIC_IRQ19 0x00080000
548 #define APIC_IRQ20 0x00100000
549 #define APIC_IRQ21 0x00200000
550 #define APIC_IRQ22 0x00400000
551 #define APIC_IRQ23 0x00800000
554 /******************************************************************************
558 /* default physical locations of an IO APIC */
559 #define DEFAULT_IO_APIC_BASE 0xfec00000
561 /* window register offset */
562 #define IOAPIC_WINDOW 0x10
564 /* indexes into IO APIC */
565 #define IOAPIC_ID 0x00
566 #define IOAPIC_VER 0x01
567 #define IOAPIC_ARB 0x02
568 #define IOAPIC_REDTBL 0x10
569 #define IOAPIC_REDTBL0 IOAPIC_REDTBL
570 #define IOAPIC_REDTBL1 (IOAPIC_REDTBL+0x02)
571 #define IOAPIC_REDTBL2 (IOAPIC_REDTBL+0x04)
572 #define IOAPIC_REDTBL3 (IOAPIC_REDTBL+0x06)
573 #define IOAPIC_REDTBL4 (IOAPIC_REDTBL+0x08)
574 #define IOAPIC_REDTBL5 (IOAPIC_REDTBL+0x0a)
575 #define IOAPIC_REDTBL6 (IOAPIC_REDTBL+0x0c)
576 #define IOAPIC_REDTBL7 (IOAPIC_REDTBL+0x0e)
577 #define IOAPIC_REDTBL8 (IOAPIC_REDTBL+0x10)
578 #define IOAPIC_REDTBL9 (IOAPIC_REDTBL+0x12)
579 #define IOAPIC_REDTBL10 (IOAPIC_REDTBL+0x14)
580 #define IOAPIC_REDTBL11 (IOAPIC_REDTBL+0x16)
581 #define IOAPIC_REDTBL12 (IOAPIC_REDTBL+0x18)
582 #define IOAPIC_REDTBL13 (IOAPIC_REDTBL+0x1a)
583 #define IOAPIC_REDTBL14 (IOAPIC_REDTBL+0x1c)
584 #define IOAPIC_REDTBL15 (IOAPIC_REDTBL+0x1e)
585 #define IOAPIC_REDTBL16 (IOAPIC_REDTBL+0x20)
586 #define IOAPIC_REDTBL17 (IOAPIC_REDTBL+0x22)
587 #define IOAPIC_REDTBL18 (IOAPIC_REDTBL+0x24)
588 #define IOAPIC_REDTBL19 (IOAPIC_REDTBL+0x26)
589 #define IOAPIC_REDTBL20 (IOAPIC_REDTBL+0x28)
590 #define IOAPIC_REDTBL21 (IOAPIC_REDTBL+0x2a)
591 #define IOAPIC_REDTBL22 (IOAPIC_REDTBL+0x2c)
592 #define IOAPIC_REDTBL23 (IOAPIC_REDTBL+0x2e)
595 #define IOART_VER_VERSION 0x000000ff
596 #define IOART_VER_MAXREDIR 0x00ff0000
597 #define MAXREDIRSHIFT 16
600 * fields in the IO APIC's redirection table entries
602 #define IOART_DEST APIC_ID_MASK /* broadcast addr: all APICs */
604 #define IOART_RESV 0x00fe0000 /* reserved */
606 #define IOART_INTMASK 0x00010000 /* R/W: INTerrupt mask */
607 # define IOART_INTMCLR 0x00000000 /* clear, allow INTs */
608 # define IOART_INTMSET 0x00010000 /* set, inhibit INTs */
610 #define IOART_TRGRMOD 0x00008000 /* R/W: trigger mode */
611 # define IOART_TRGREDG 0x00000000 /* edge */
612 # define IOART_TRGRLVL 0x00008000 /* level */
614 #define IOART_REM_IRR 0x00004000 /* RO: remote IRR */
616 #define IOART_INTPOL 0x00002000 /* R/W: INT input pin polarity */
617 # define IOART_INTAHI 0x00000000 /* active high */
618 # define IOART_INTALO 0x00002000 /* active low */
620 #define IOART_DELIVS 0x00001000 /* RO: delivery status */
622 #define IOART_DESTMOD 0x00000800 /* R/W: destination mode */
623 # define IOART_DESTPHY 0x00000000 /* physical */
624 # define IOART_DESTLOG 0x00000800 /* logical */
626 #define IOART_DELMOD 0x00000700 /* R/W: delivery mode */
627 # define IOART_DELFIXED 0x00000000 /* fixed */
628 # define IOART_DELLOPRI 0x00000100 /* lowest priority */
629 # define IOART_DELSMI 0x00000200 /* System Management INT */
630 # define IOART_DELRSV1 0x00000300 /* reserved */
631 # define IOART_DELNMI 0x00000400 /* NMI signal */
632 # define IOART_DELINIT 0x00000500 /* INIT signal */
633 # define IOART_DELRSV2 0x00000600 /* reserved */
634 # define IOART_DELEXINT 0x00000700 /* External INTerrupt */
636 #define IOART_INTVEC 0x000000ff /* R/W: INTerrupt vector field */
638 #endif /* _MACHINE_APIC_H_ */