sys/dev/netif/sk/if_sk.c

   1 /*      $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */
   2
   3 /*
   4  * Copyright (c) 1997, 1998, 1999, 2000
   5  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by Bill Paul.
  18  * 4. Neither the name of the author nor the names of any co-contributors
  19  *    may be used to endorse or promote products derived from this software
  20  *    without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  32  * THE POSSIBILITY OF SUCH DAMAGE.
  33  *
  34  * $FreeBSD: src/sys/pci/if_sk.c,v 1.19.2.9 2003/03/05 18:42:34 njl Exp $
  35  * $DragonFly: src/sys/dev/netif/sk/if_sk.c,v 1.25 2005/02/20 01:49:21 joerg Exp $
  36  *
  37  * $FreeBSD: src/sys/pci/if_sk.c,v 1.19.2.9 2003/03/05 18:42:34 njl Exp $
  38  */
  39
  40 /*
  41  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
  42  *
  43  * Permission to use, copy, modify, and distribute this software for any
  44  * purpose with or without fee is hereby granted, provided that the above
  45  * copyright notice and this permission notice appear in all copies.
  46  *
  47  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  48  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  49  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  50  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  51  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  52  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  53  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  54  */
  55
  56 /*
  57  * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
  58  * the SK-984x series adapters, both single port and dual port.
  59  * References:
  60  *      The XaQti XMAC II datasheet,
  61  *  http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  62  *      The SysKonnect GEnesis manual, http://www.syskonnect.com
  63  *
  64  * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the
  65  * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
  66  * convenience to others until Vitesse corrects this problem:
  67  *
  68  * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  69  *
  70  * Written by Bill Paul <wpaul@ee.columbia.edu>
  71  * Department of Electrical Engineering
  72  * Columbia University, New York City
  73  */
  74
  75 /*
  76  * The SysKonnect gigabit ethernet adapters consist of two main
  77  * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
  78  * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
  79  * components and a PHY while the GEnesis controller provides a PCI
  80  * interface with DMA support. Each card may have between 512K and
  81  * 2MB of SRAM on board depending on the configuration.
  82  *
  83  * The SysKonnect GEnesis controller can have either one or two XMAC
  84  * chips connected to it, allowing single or dual port NIC configurations.
  85  * SysKonnect has the distinction of being the only vendor on the market
  86  * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
  87  * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
  88  * XMAC registers. This driver takes advantage of these features to allow
  89  * both XMACs to operate as independent interfaces.
  90  */
  91
  92 #include <sys/param.h>
  93 #include <sys/systm.h>
  94 #include <sys/sockio.h>
  95 #include <sys/mbuf.h>
  96 #include <sys/malloc.h>
  97 #include <sys/kernel.h>
  98 #include <sys/socket.h>
  99 #include <sys/queue.h>
 100
 101 #include <net/if.h>
 102 #include <net/ifq_var.h>
 103 #include <net/if_arp.h>
 104 #include <net/ethernet.h>
 105 #include <net/if_dl.h>
 106 #include <net/if_media.h>
 107
 108 #include <net/bpf.h>
 109
 110 #include <vm/vm.h>              /* for vtophys */
 111 #include <vm/pmap.h>            /* for vtophys */
 112 #include <machine/clock.h>      /* for DELAY */
 113 #include <machine/bus_pio.h>
 114 #include <machine/bus_memio.h>
 115 #include <machine/bus.h>
 116 #include <machine/resource.h>
 117 #include <sys/bus.h>
 118 #include <sys/rman.h>
 119
 120 #include "../mii_layer/mii.h"
 121 #include "../mii_layer/miivar.h"
 122 #include "../mii_layer/brgphyreg.h"
 123
 124 #include <bus/pci/pcireg.h>
 125 #include <bus/pci/pcivar.h>
 126
 127 #if 0
 128 #define SK_USEIOSPACE
 129 #endif
 130
 131 #include "if_skreg.h"
 132 #include "xmaciireg.h"
 133 #include "yukonreg.h"
 134
 135 /* "controller miibus0" required.  See GENERIC if you get errors here. */
 136 #include "miibus_if.h"
 137
 138 static struct sk_type sk_devs[] = {
 139         {
 140                 VENDORID_SK,
 141                 DEVICEID_SK_V1,
 142                 "SysKonnect Gigabit Ethernet (V1.0)"
 143         },
 144         {
 145                 VENDORID_SK,
 146                 DEVICEID_SK_V2,
 147                 "SysKonnect Gigabit Ethernet (V2.0)"
 148         },
 149         {
 150                 VENDORID_MARVELL,
 151                 DEVICEID_SK_V2,
 152                 "Marvell Gigabit Ethernet"
 153         },
 154         {
 155                 VENDORID_3COM,
 156                 DEVICEID_3COM_3C940,
 157                 "3Com 3C940 Gigabit Ethernet"
 158         },
 159         {
 160                 VENDORID_LINKSYS,
 161                 DEVICEID_LINKSYS_EG1032,
 162                 "Linksys EG1032 Gigabit Ethernet"
 163         },
 164         {
 165                 VENDORID_DLINK,
 166                 DEVICEID_DLINK_DGE530T,
 167                 "D-Link DGE-530T Gigabit Ethernet"
 168         },
 169         { 0, 0, NULL }
 170 };
 171
 172 static int skc_probe            (device_t);
 173 static int skc_attach           (device_t);
 174 static int skc_detach           (device_t);
 175 static void skc_shutdown        (device_t);
 176 static int sk_probe             (device_t);
 177 static int sk_attach            (device_t);
 178 static int sk_detach            (device_t);
 179 static void sk_tick             (void *);
 180 static void sk_intr             (void *);
 181 static void sk_intr_bcom        (struct sk_if_softc *);
 182 static void sk_intr_xmac        (struct sk_if_softc *);
 183 static void sk_intr_yukon       (struct sk_if_softc *);
 184 static void sk_rxeof            (struct sk_if_softc *);
 185 static void sk_txeof            (struct sk_if_softc *);
 186 static int sk_encap             (struct sk_if_softc *, struct mbuf *,
 187                                         u_int32_t *);
 188 static void sk_start            (struct ifnet *);
 189 static int sk_ioctl             (struct ifnet *, u_long, caddr_t,
 190                                         struct ucred *);
 191 static void sk_init             (void *);
 192 static void sk_init_xmac        (struct sk_if_softc *);
 193 static void sk_init_yukon       (struct sk_if_softc *);
 194 static void sk_stop             (struct sk_if_softc *);
 195 static void sk_watchdog         (struct ifnet *);
 196 static int sk_ifmedia_upd       (struct ifnet *);
 197 static void sk_ifmedia_sts      (struct ifnet *, struct ifmediareq *);
 198 static void sk_reset            (struct sk_softc *);
 199 static int sk_newbuf            (struct sk_if_softc *,
 200                                         struct sk_chain *, struct mbuf *);
 201 static int sk_alloc_jumbo_mem   (struct sk_if_softc *);
 202 static void *sk_jalloc          (struct sk_if_softc *);
 203 static void sk_jfree            (caddr_t, u_int);
 204 static void sk_jref             (caddr_t, u_int);
 205 static int sk_init_rx_ring      (struct sk_if_softc *);
 206 static void sk_init_tx_ring     (struct sk_if_softc *);
 207 static u_int32_t sk_win_read_4  (struct sk_softc *, int);
 208 static u_int16_t sk_win_read_2  (struct sk_softc *, int);
 209 static u_int8_t sk_win_read_1   (struct sk_softc *, int);
 210 static void sk_win_write_4      (struct sk_softc *, int, u_int32_t);
 211 static void sk_win_write_2      (struct sk_softc *, int, u_int32_t);
 212 static void sk_win_write_1      (struct sk_softc *, int, u_int32_t);
 213 static u_int8_t sk_vpd_readbyte (struct sk_softc *, int);
 214 static void sk_vpd_read_res     (struct sk_softc *,
 215                                         struct vpd_res *, int);
 216 static void sk_vpd_read         (struct sk_softc *);
 217
 218 static int sk_miibus_readreg    (device_t, int, int);
 219 static int sk_miibus_writereg   (device_t, int, int, int);
 220 static void sk_miibus_statchg   (device_t);
 221
 222 static int sk_xmac_miibus_readreg     (struct sk_if_softc *, int, int);
 223 static int sk_xmac_miibus_writereg    (struct sk_if_softc *, int, int, int);
 224 static void sk_xmac_miibus_statchg    (struct sk_if_softc *);
 225
 226 static int sk_marv_miibus_readreg     (struct sk_if_softc *, int, int);
 227 static int sk_marv_miibus_writereg    (struct sk_if_softc *, int, int, int);
 228 static void sk_marv_miibus_statchg    (struct sk_if_softc *);
 229
 230 static u_int32_t xmac_calchash  (caddr_t);
 231 static u_int32_t gmac_calchash  (caddr_t);
 232 static void sk_setfilt          (struct sk_if_softc *, caddr_t, int);
 233 static void sk_setmulti         (struct sk_if_softc *);
 234 static void sk_setpromisc       (struct sk_if_softc *);
 235
 236 #ifdef SK_USEIOSPACE
 237 #define SK_RES          SYS_RES_IOPORT
 238 #define SK_RID          SK_PCI_LOIO
 239 #else
 240 #define SK_RES          SYS_RES_MEMORY
 241 #define SK_RID          SK_PCI_LOMEM
 242 #endif
 243
 244 /*
 245  * Note that we have newbus methods for both the GEnesis controller
 246  * itself and the XMAC(s). The XMACs are children of the GEnesis, and
 247  * the miibus code is a child of the XMACs. We need to do it this way
 248  * so that the miibus drivers can access the PHY registers on the
 249  * right PHY. It's not quite what I had in mind, but it's the only
 250  * design that achieves the desired effect.
 251  */
 252 static device_method_t skc_methods[] = {
 253         /* Device interface */
 254         DEVMETHOD(device_probe,         skc_probe),
 255         DEVMETHOD(device_attach,        skc_attach),
 256         DEVMETHOD(device_detach,        skc_detach),
 257         DEVMETHOD(device_shutdown,      skc_shutdown),
 258
 259         /* bus interface */
 260         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 261         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 262
 263         { 0, 0 }
 264 };
 265
 266 static driver_t skc_driver = {
 267         "skc",
 268         skc_methods,
 269         sizeof(struct sk_softc)
 270 };
 271
 272 static devclass_t skc_devclass;
 273
 274 static device_method_t sk_methods[] = {
 275         /* Device interface */
 276         DEVMETHOD(device_probe,         sk_probe),
 277         DEVMETHOD(device_attach,        sk_attach),
 278         DEVMETHOD(device_detach,        sk_detach),
 279         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 280
 281         /* bus interface */
 282         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 283         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 284
 285         /* MII interface */
 286         DEVMETHOD(miibus_readreg,       sk_miibus_readreg),
 287         DEVMETHOD(miibus_writereg,      sk_miibus_writereg),
 288         DEVMETHOD(miibus_statchg,       sk_miibus_statchg),
 289
 290         { 0, 0 }
 291 };
 292
 293 static driver_t sk_driver = {
 294         "sk",
 295         sk_methods,
 296         sizeof(struct sk_if_softc)
 297 };
 298
 299 static devclass_t sk_devclass;
 300
 301 DECLARE_DUMMY_MODULE(if_sk);
 302 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0);
 303 DRIVER_MODULE(if_sk, skc, sk_driver, sk_devclass, 0, 0);
 304 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0);
 305
 306 #define SK_SETBIT(sc, reg, x)           \
 307         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
 308
 309 #define SK_CLRBIT(sc, reg, x)           \
 310         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
 311
 312 #define SK_WIN_SETBIT_4(sc, reg, x)     \
 313         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
 314
 315 #define SK_WIN_CLRBIT_4(sc, reg, x)     \
 316         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
 317
 318 #define SK_WIN_SETBIT_2(sc, reg, x)     \
 319         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
 320
 321 #define SK_WIN_CLRBIT_2(sc, reg, x)     \
 322         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
 323
 324 static u_int32_t sk_win_read_4(sc, reg)
 325         struct sk_softc         *sc;
 326         int                     reg;
 327 {
 328 #ifdef SK_USEIOSPACE
 329         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 330         return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
 331 #else
 332         return(CSR_READ_4(sc, reg));
 333 #endif
 334 }
 335
 336 static u_int16_t sk_win_read_2(sc, reg)
 337         struct sk_softc         *sc;
 338         int                     reg;
 339 {
 340 #ifdef SK_USEIOSPACE
 341         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 342         return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
 343 #else
 344         return(CSR_READ_2(sc, reg));
 345 #endif
 346 }
 347
 348 static u_int8_t sk_win_read_1(sc, reg)
 349         struct sk_softc         *sc;
 350         int                     reg;
 351 {
 352 #ifdef SK_USEIOSPACE
 353         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 354         return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
 355 #else
 356         return(CSR_READ_1(sc, reg));
 357 #endif
 358 }
 359
 360 static void sk_win_write_4(sc, reg, val)
 361         struct sk_softc         *sc;
 362         int                     reg;
 363         u_int32_t               val;
 364 {
 365 #ifdef SK_USEIOSPACE
 366         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 367         CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
 368 #else
 369         CSR_WRITE_4(sc, reg, val);
 370 #endif
 371         return;
 372 }
 373
 374 static void sk_win_write_2(sc, reg, val)
 375         struct sk_softc         *sc;
 376         int                     reg;
 377         u_int32_t               val;
 378 {
 379 #ifdef SK_USEIOSPACE
 380         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 381         CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
 382 #else
 383         CSR_WRITE_2(sc, reg, val);
 384 #endif
 385         return;
 386 }
 387
 388 static void sk_win_write_1(sc, reg, val)
 389         struct sk_softc         *sc;
 390         int                     reg;
 391         u_int32_t               val;
 392 {
 393 #ifdef SK_USEIOSPACE
 394         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 395         CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
 396 #else
 397         CSR_WRITE_1(sc, reg, val);
 398 #endif
 399         return;
 400 }
 401
 402 /*
 403  * The VPD EEPROM contains Vital Product Data, as suggested in
 404  * the PCI 2.1 specification. The VPD data is separared into areas
 405  * denoted by resource IDs. The SysKonnect VPD contains an ID string
 406  * resource (the name of the adapter), a read-only area resource
 407  * containing various key/data fields and a read/write area which
 408  * can be used to store asset management information or log messages.
 409  * We read the ID string and read-only into buffers attached to
 410  * the controller softc structure for later use. At the moment,
 411  * we only use the ID string during sk_attach().
 412  */
 413 static u_int8_t sk_vpd_readbyte(sc, addr)
 414         struct sk_softc         *sc;
 415         int                     addr;
 416 {
 417         int                     i;
 418
 419         sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr);
 420         for (i = 0; i < SK_TIMEOUT; i++) {
 421                 DELAY(1);
 422                 if (sk_win_read_2(sc,
 423                     SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG)
 424                         break;
 425         }
 426
 427         if (i == SK_TIMEOUT)
 428                 return(0);
 429
 430         return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)));
 431 }
 432
 433 static void sk_vpd_read_res(sc, res, addr)
 434         struct sk_softc         *sc;
 435         struct vpd_res          *res;
 436         int                     addr;
 437 {
 438         int                     i;
 439         u_int8_t                *ptr;
 440
 441         ptr = (u_int8_t *)res;
 442         for (i = 0; i < sizeof(struct vpd_res); i++)
 443                 ptr[i] = sk_vpd_readbyte(sc, i + addr);
 444
 445         return;
 446 }
 447
 448 static void sk_vpd_read(sc)
 449         struct sk_softc         *sc;
 450 {
 451         int                     pos = 0, i;
 452         struct vpd_res          res;
 453
 454         if (sc->sk_vpd_prodname != NULL)
 455                 free(sc->sk_vpd_prodname, M_DEVBUF);
 456         if (sc->sk_vpd_readonly != NULL)
 457                 free(sc->sk_vpd_readonly, M_DEVBUF);
 458         sc->sk_vpd_prodname = NULL;
 459         sc->sk_vpd_readonly = NULL;
 460
 461         sk_vpd_read_res(sc, &res, pos);
 462
 463         if (res.vr_id != VPD_RES_ID) {
 464                 printf("skc%d: bad VPD resource id: expected %x got %x\n",
 465                     sc->sk_unit, VPD_RES_ID, res.vr_id);
 466                 return;
 467         }
 468
 469         pos += sizeof(res);
 470         sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT);
 471         for (i = 0; i < res.vr_len; i++)
 472                 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos);
 473         sc->sk_vpd_prodname[i] = '\0';
 474         pos += i;
 475
 476         sk_vpd_read_res(sc, &res, pos);
 477
 478         if (res.vr_id != VPD_RES_READ) {
 479                 printf("skc%d: bad VPD resource id: expected %x got %x\n",
 480                     sc->sk_unit, VPD_RES_READ, res.vr_id);
 481                 return;
 482         }
 483
 484         pos += sizeof(res);
 485         sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_INTWAIT);
 486         for (i = 0; i < res.vr_len + 1; i++)
 487                 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos);
 488
 489         return;
 490 }
 491
 492 static int sk_miibus_readreg(dev, phy, reg)
 493         device_t                dev;
 494         int                     phy, reg;
 495 {
 496         struct sk_if_softc      *sc_if;
 497
 498         sc_if = device_get_softc(dev);
 499
 500         switch(sc_if->sk_softc->sk_type) {
 501         case SK_GENESIS:
 502                 return(sk_xmac_miibus_readreg(sc_if, phy, reg));
 503         case SK_YUKON:
 504                 return(sk_marv_miibus_readreg(sc_if, phy, reg));
 505         }
 506
 507         return(0);
 508 }
 509
 510 static int sk_miibus_writereg(dev, phy, reg, val)
 511         device_t                dev;
 512         int                     phy, reg, val;
 513 {
 514         struct sk_if_softc      *sc_if;
 515
 516         sc_if = device_get_softc(dev);
 517
 518         switch(sc_if->sk_softc->sk_type) {
 519         case SK_GENESIS:
 520                 return(sk_xmac_miibus_writereg(sc_if, phy, reg, val));
 521         case SK_YUKON:
 522                 return(sk_marv_miibus_writereg(sc_if, phy, reg, val));
 523         }
 524
 525         return(0);
 526 }
 527
 528 static void sk_miibus_statchg(dev)
 529         device_t                dev;
 530 {
 531         struct sk_if_softc      *sc_if;
 532
 533         sc_if = device_get_softc(dev);
 534
 535         switch(sc_if->sk_softc->sk_type) {
 536         case SK_GENESIS:
 537                 sk_xmac_miibus_statchg(sc_if);
 538                 break;
 539         case SK_YUKON:
 540                 sk_marv_miibus_statchg(sc_if);
 541                 break;
 542         }
 543
 544         return;
 545 }
 546
 547 static int sk_xmac_miibus_readreg(sc_if, phy, reg)
 548         struct sk_if_softc      *sc_if;
 549         int                     phy, reg;
 550 {
 551         int                     i;
 552
 553         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
 554                 return(0);
 555
 556         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 557         SK_XM_READ_2(sc_if, XM_PHY_DATA);
 558         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 559                 for (i = 0; i < SK_TIMEOUT; i++) {
 560                         DELAY(1);
 561                         if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
 562                             XM_MMUCMD_PHYDATARDY)
 563                                 break;
 564                 }
 565
 566                 if (i == SK_TIMEOUT) {
 567                         printf("sk%d: phy failed to come ready\n",
 568                             sc_if->sk_unit);
 569                         return(0);
 570                 }
 571         }
 572         DELAY(1);
 573         return(SK_XM_READ_2(sc_if, XM_PHY_DATA));
 574 }
 575
 576 static int sk_xmac_miibus_writereg(sc_if, phy, reg, val)
 577         struct sk_if_softc      *sc_if;
 578         int                     phy, reg, val;
 579 {
 580         int                     i;
 581
 582         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 583         for (i = 0; i < SK_TIMEOUT; i++) {
 584                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
 585                         break;
 586         }
 587
 588         if (i == SK_TIMEOUT) {
 589                 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit);
 590                 return(ETIMEDOUT);
 591         }
 592
 593         SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
 594         for (i = 0; i < SK_TIMEOUT; i++) {
 595                 DELAY(1);
 596                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
 597                         break;
 598         }
 599
 600         if (i == SK_TIMEOUT)
 601                 printf("sk%d: phy write timed out\n", sc_if->sk_unit);
 602
 603         return(0);
 604 }
 605
 606 static void sk_xmac_miibus_statchg(sc_if)
 607         struct sk_if_softc      *sc_if;
 608 {
 609         struct mii_data         *mii;
 610
 611         mii = device_get_softc(sc_if->sk_miibus);
 612
 613         /*
 614          * If this is a GMII PHY, manually set the XMAC's
 615          * duplex mode accordingly.
 616          */
 617         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 618                 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 619                         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 620                 } else {
 621                         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 622                 }
 623         }
 624
 625         return;
 626 }
 627
 628 static int sk_marv_miibus_readreg(sc_if, phy, reg)
 629         struct sk_if_softc      *sc_if;
 630         int                     phy, reg;
 631 {
 632         u_int16_t               val;
 633         int                     i;
 634
 635         if (phy != 0 ||
 636             (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
 637              sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
 638                 return(0);
 639         }
 640
 641         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 642                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
 643
 644         for (i = 0; i < SK_TIMEOUT; i++) {
 645                 DELAY(1);
 646                 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
 647                 if (val & YU_SMICR_READ_VALID)
 648                         break;
 649         }
 650
 651         if (i == SK_TIMEOUT) {
 652                 printf("sk%d: phy failed to come ready\n",
 653                     sc_if->sk_unit);
 654                 return(0);
 655         }
 656
 657         val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
 658
 659         return(val);
 660 }
 661
 662 static int sk_marv_miibus_writereg(sc_if, phy, reg, val)
 663         struct sk_if_softc      *sc_if;
 664         int                     phy, reg, val;
 665 {
 666         int                     i;
 667
 668         SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
 669         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 670                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
 671
 672         for (i = 0; i < SK_TIMEOUT; i++) {
 673                 DELAY(1);
 674                 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)
 675                         break;
 676         }
 677
 678         return(0);
 679 }
 680
 681 static void sk_marv_miibus_statchg(sc_if)
 682         struct sk_if_softc      *sc_if;
 683 {
 684         return;
 685 }
 686
 687 #define XMAC_POLY               0xEDB88320
 688 #define GMAC_POLY               0x04C11DB7L
 689 #define HASH_BITS               6
 690
 691 static u_int32_t xmac_calchash(addr)
 692         caddr_t                 addr;
 693 {
 694         u_int32_t               idx, bit, data, crc;
 695
 696         /* Compute CRC for the address value. */
 697         crc = 0xFFFFFFFF; /* initial value */
 698
 699         for (idx = 0; idx < 6; idx++) {
 700                 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
 701                         crc = (crc >> 1) ^ (((crc ^ data) & 1) ? XMAC_POLY : 0);
 702         }
 703
 704         return (~crc & ((1 << HASH_BITS) - 1));
 705 }
 706
 707 static u_int32_t gmac_calchash(addr)
 708     caddr_t                     addr;
 709 {
 710     u_int32_t               idx, bit, crc, tmpData, data;
 711
 712     /* Compute CRC for the address value. */
 713     crc = 0xFFFFFFFF; /* initial value */
 714
 715     for (idx = 0; idx < 6; idx++) {
 716         data = *addr++;
 717
 718         /* Change bit order in byte. */
 719         tmpData = data;
 720         for (bit = 0; bit < 8; bit++) {
 721             if (tmpData & 1) {
 722                 data |=  1 << (7 - bit);
 723             }
 724             else {
 725                 data &= ~(1 << (7 - bit));
 726             }
 727
 728             tmpData >>= 1;
 729         }
 730
 731         crc ^= (data << 24);
 732         for (bit = 0; bit < 8; bit++) {
 733             if (crc & 0x80000000) {
 734                 crc = (crc << 1) ^ GMAC_POLY;
 735             } else {
 736                 crc <<= 1;
 737             }
 738         }
 739     }
 740
 741     return (crc & ((1 << HASH_BITS) - 1));
 742 }
 743
 744 static void sk_setfilt(sc_if, addr, slot)
 745         struct sk_if_softc      *sc_if;
 746         caddr_t                 addr;
 747         int                     slot;
 748 {
 749         int                     base;
 750
 751         base = XM_RXFILT_ENTRY(slot);
 752
 753         SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0]));
 754         SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2]));
 755         SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4]));
 756
 757         return;
 758 }
 759
 760 static void sk_setmulti(sc_if)
 761         struct sk_if_softc      *sc_if;
 762 {
 763         struct sk_softc         *sc = sc_if->sk_softc;
 764         struct ifnet            *ifp = &sc_if->arpcom.ac_if;
 765         u_int32_t               hashes[2] = { 0, 0 };
 766         int                     h, i;
 767         struct ifmultiaddr      *ifma;
 768         u_int8_t                dummy[] = { 0, 0, 0, 0, 0 ,0 };
 769
 770
 771         /* First, zot all the existing filters. */
 772         switch(sc->sk_type) {
 773         case SK_GENESIS:
 774                 for (i = 1; i < XM_RXFILT_MAX; i++)
 775                         sk_setfilt(sc_if, (caddr_t)&dummy, i);
 776
 777                 SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
 778                 SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
 779                 break;
 780         case SK_YUKON:
 781                 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
 782                 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
 783                 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
 784                 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
 785                 break;
 786         }
 787
 788         /* Now program new ones. */
 789         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 790                 hashes[0] = 0xFFFFFFFF;
 791                 hashes[1] = 0xFFFFFFFF;
 792         } else {
 793                 i = 1;
 794                 /* First find the tail of the list. */
 795                 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
 796                                         ifma = ifma->ifma_link.le_next) {
 797                         if (ifma->ifma_link.le_next == NULL)
 798                                 break;
 799                 }
 800                 /* Now traverse the list backwards. */
 801                 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
 802                         ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
 803                         if (ifma->ifma_addr->sa_family != AF_LINK)
 804                                 continue;
 805                         /*
 806                          * Program the first XM_RXFILT_MAX multicast groups
 807                          * into the perfect filter. For all others,
 808                          * use the hash table.
 809                          */
 810                         if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) {
 811                                 sk_setfilt(sc_if,
 812                         LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
 813                                 i++;
 814                                 continue;
 815                         }
 816
 817                         switch(sc->sk_type) {
 818                         case SK_GENESIS:
 819                             h = xmac_calchash(
 820                                 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
 821                             if (h < 32)
 822                                 hashes[0] |= (1 << h);
 823                             else
 824                                 hashes[1] |= (1 << (h - 32));
 825                             break;
 826
 827                         case SK_YUKON:
 828                             h = gmac_calchash(
 829                                 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
 830                             if (h < 32)
 831                                 hashes[0] |= (1 << h);
 832                             else
 833                                 hashes[1] |= (1 << (h - 32));
 834                             break;
 835                         }
 836                 }
 837         }
 838
 839         switch(sc->sk_type) {
 840         case SK_GENESIS:
 841                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH|
 842                                XM_MODE_RX_USE_PERFECT);
 843                 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
 844                 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
 845                 break;
 846         case SK_YUKON:
 847                 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
 848                 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
 849                 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
 850                 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
 851                 break;
 852         }
 853
 854         return;
 855 }
 856
 857 static void sk_setpromisc(sc_if)
 858         struct sk_if_softc      *sc_if;
 859 {
 860         struct sk_softc         *sc = sc_if->sk_softc;
 861         struct ifnet            *ifp = &sc_if->arpcom.ac_if;
 862
 863         switch(sc->sk_type) {
 864         case SK_GENESIS:
 865                 if (ifp->if_flags & IFF_PROMISC) {
 866                         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
 867                 } else {
 868                         SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
 869                 }
 870                 break;
 871         case SK_YUKON:
 872                 if (ifp->if_flags & IFF_PROMISC) {
 873                         SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
 874                             YU_RCR_UFLEN | YU_RCR_MUFLEN);
 875                 } else {
 876                         SK_YU_SETBIT_2(sc_if, YUKON_RCR,
 877                             YU_RCR_UFLEN | YU_RCR_MUFLEN);
 878                 }
 879                 break;
 880         }
 881
 882         return;
 883 }
 884
 885 static int sk_init_rx_ring(sc_if)
 886         struct sk_if_softc      *sc_if;
 887 {
 888         struct sk_chain_data    *cd = &sc_if->sk_cdata;
 889         struct sk_ring_data     *rd = sc_if->sk_rdata;
 890         int                     i;
 891
 892         bzero((char *)rd->sk_rx_ring,
 893             sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
 894
 895         for (i = 0; i < SK_RX_RING_CNT; i++) {
 896                 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i];
 897                 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS)
 898                         return(ENOBUFS);
 899                 if (i == (SK_RX_RING_CNT - 1)) {
 900                         cd->sk_rx_chain[i].sk_next =
 901                             &cd->sk_rx_chain[0];
 902                         rd->sk_rx_ring[i].sk_next =
 903                             vtophys(&rd->sk_rx_ring[0]);
 904                 } else {
 905                         cd->sk_rx_chain[i].sk_next =
 906                             &cd->sk_rx_chain[i + 1];
 907                         rd->sk_rx_ring[i].sk_next =
 908                             vtophys(&rd->sk_rx_ring[i + 1]);
 909                 }
 910         }
 911
 912         sc_if->sk_cdata.sk_rx_prod = 0;
 913         sc_if->sk_cdata.sk_rx_cons = 0;
 914
 915         return(0);
 916 }
 917
 918 static void sk_init_tx_ring(sc_if)
 919         struct sk_if_softc      *sc_if;
 920 {
 921         struct sk_chain_data    *cd = &sc_if->sk_cdata;
 922         struct sk_ring_data     *rd = sc_if->sk_rdata;
 923         int                     i;
 924
 925         bzero((char *)sc_if->sk_rdata->sk_tx_ring,
 926             sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
 927
 928         for (i = 0; i < SK_TX_RING_CNT; i++) {
 929                 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i];
 930                 if (i == (SK_TX_RING_CNT - 1)) {
 931                         cd->sk_tx_chain[i].sk_next =
 932                             &cd->sk_tx_chain[0];
 933                         rd->sk_tx_ring[i].sk_next =
 934                             vtophys(&rd->sk_tx_ring[0]);
 935                 } else {
 936                         cd->sk_tx_chain[i].sk_next =
 937                             &cd->sk_tx_chain[i + 1];
 938                         rd->sk_tx_ring[i].sk_next =
 939                             vtophys(&rd->sk_tx_ring[i + 1]);
 940                 }
 941         }
 942
 943         sc_if->sk_cdata.sk_tx_prod = 0;
 944         sc_if->sk_cdata.sk_tx_cons = 0;
 945         sc_if->sk_cdata.sk_tx_cnt = 0;
 946
 947         return;
 948 }
 949
 950 static int sk_newbuf(sc_if, c, m)
 951         struct sk_if_softc      *sc_if;
 952         struct sk_chain         *c;
 953         struct mbuf             *m;
 954 {
 955         struct mbuf             *m_new = NULL;
 956         struct sk_rx_desc       *r;
 957
 958         if (m == NULL) {
 959                 caddr_t                 *buf = NULL;
 960
 961                 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
 962                 if (m_new == NULL)
 963                         return(ENOBUFS);
 964
 965                 /* Allocate the jumbo buffer */
 966                 buf = sk_jalloc(sc_if);
 967                 if (buf == NULL) {
 968                         m_freem(m_new);
 969 #ifdef SK_VERBOSE
 970                         printf("sk%d: jumbo allocation failed "
 971                             "-- packet dropped!\n", sc_if->sk_unit);
 972 #endif
 973                         return(ENOBUFS);
 974                 }
 975
 976                 /* Attach the buffer to the mbuf */
 977                 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
 978                 m_new->m_flags |= M_EXT | M_EXT_OLD;
 979                 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
 980                     m_new->m_len = SK_MCLBYTES;
 981                 m_new->m_ext.ext_nfree.old = sk_jfree;
 982                 m_new->m_ext.ext_nref.old = sk_jref;
 983         } else {
 984                 /*
 985                  * We're re-using a previously allocated mbuf;
 986                  * be sure to re-init pointers and lengths to
 987                  * default values.
 988                  */
 989                 m_new = m;
 990                 m_new->m_len = m_new->m_pkthdr.len = SK_MCLBYTES;
 991                 m_new->m_data = m_new->m_ext.ext_buf;
 992         }
 993
 994         /*
 995          * Adjust alignment so packet payload begins on a
 996          * longword boundary. Mandatory for Alpha, useful on
 997          * x86 too.
 998          */
 999         m_adj(m_new, ETHER_ALIGN);
1000
1001         r = c->sk_desc;
1002         c->sk_mbuf = m_new;
1003         r->sk_data_lo = vtophys(mtod(m_new, caddr_t));
1004         r->sk_ctl = m_new->m_len | SK_RXSTAT;
1005
1006         return(0);
1007 }
1008
1009 /*
1010  * Allocate jumbo buffer storage. The SysKonnect adapters support
1011  * "jumbograms" (9K frames), although SysKonnect doesn't currently
1012  * use them in their drivers. In order for us to use them, we need
1013  * large 9K receive buffers, however standard mbuf clusters are only
1014  * 2048 bytes in size. Consequently, we need to allocate and manage
1015  * our own jumbo buffer pool. Fortunately, this does not require an
1016  * excessive amount of additional code.
1017  */
1018 static int sk_alloc_jumbo_mem(sc_if)
1019         struct sk_if_softc      *sc_if;
1020 {
1021         caddr_t                 ptr;
1022         int             i;
1023         struct sk_jpool_entry   *entry;
1024
1025         /* Grab a big chunk o' storage. */
1026         sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF,
1027             M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1028
1029         if (sc_if->sk_cdata.sk_jumbo_buf == NULL) {
1030                 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit);
1031                 return(ENOBUFS);
1032         }
1033
1034         SLIST_INIT(&sc_if->sk_jfree_listhead);
1035         SLIST_INIT(&sc_if->sk_jinuse_listhead);
1036
1037         /*
1038          * Now divide it up into 9K pieces and save the addresses
1039          * in an array. Note that we play an evil trick here by using
1040          * the first few bytes in the buffer to hold the the address
1041          * of the softc structure for this interface. This is because
1042          * sk_jfree() needs it, but it is called by the mbuf management
1043          * code which will not pass it to us explicitly.
1044          */
1045         ptr = sc_if->sk_cdata.sk_jumbo_buf;
1046         for (i = 0; i < SK_JSLOTS; i++) {
1047                 u_int64_t               **aptr;
1048                 aptr = (u_int64_t **)ptr;
1049                 aptr[0] = (u_int64_t *)sc_if;
1050                 ptr += sizeof(u_int64_t);
1051                 sc_if->sk_cdata.sk_jslots[i].sk_buf = ptr;
1052                 sc_if->sk_cdata.sk_jslots[i].sk_inuse = 0;
1053                 ptr += SK_MCLBYTES;
1054                 entry = malloc(sizeof(struct sk_jpool_entry),
1055                     M_DEVBUF, M_WAITOK);
1056                 if (entry == NULL) {
1057                         free(sc_if->sk_cdata.sk_jumbo_buf, M_DEVBUF);
1058                         sc_if->sk_cdata.sk_jumbo_buf = NULL;
1059                         printf("sk%d: no memory for jumbo "
1060                             "buffer queue!\n", sc_if->sk_unit);
1061                         return(ENOBUFS);
1062                 }
1063                 entry->slot = i;
1064                 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
1065                     entry, jpool_entries);
1066         }
1067
1068         return(0);
1069 }
1070
1071 /*
1072  * Allocate a jumbo buffer.
1073  */
1074 static void *sk_jalloc(sc_if)
1075         struct sk_if_softc      *sc_if;
1076 {
1077         struct sk_jpool_entry   *entry;
1078
1079         entry = SLIST_FIRST(&sc_if->sk_jfree_listhead);
1080
1081         if (entry == NULL) {
1082 #ifdef SK_VERBOSE
1083                 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit);
1084 #endif
1085                 return(NULL);
1086         }
1087
1088         SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries);
1089         SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries);
1090         sc_if->sk_cdata.sk_jslots[entry->slot].sk_inuse = 1;
1091         return(sc_if->sk_cdata.sk_jslots[entry->slot].sk_buf);
1092 }
1093
1094 /*
1095  * Adjust usage count on a jumbo buffer. In general this doesn't
1096  * get used much because our jumbo buffers don't get passed around
1097  * a lot, but it's implemented for correctness.
1098  */
1099 static void sk_jref(buf, size)
1100         caddr_t                 buf;
1101         u_int                   size;
1102 {
1103         struct sk_if_softc      *sc_if;
1104         u_int64_t               **aptr;
1105         int             i;
1106
1107         /* Extract the softc struct pointer. */
1108         aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
1109         sc_if = (struct sk_if_softc *)(aptr[0]);
1110
1111         if (sc_if == NULL)
1112                 panic("sk_jref: can't find softc pointer!");
1113
1114         if (size != SK_MCLBYTES)
1115                 panic("sk_jref: adjusting refcount of buf of wrong size!");
1116
1117         /* calculate the slot this buffer belongs to */
1118
1119         i = ((vm_offset_t)aptr
1120              - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN;
1121
1122         if ((i < 0) || (i >= SK_JSLOTS))
1123                 panic("sk_jref: asked to reference buffer "
1124                     "that we don't manage!");
1125         else if (sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0)
1126                 panic("sk_jref: buffer already free!");
1127         else
1128                 sc_if->sk_cdata.sk_jslots[i].sk_inuse++;
1129
1130         return;
1131 }
1132
1133 /*
1134  * Release a jumbo buffer.
1135  */
1136 static void sk_jfree(buf, size)
1137         caddr_t                 buf;
1138         u_int                   size;
1139 {
1140         struct sk_if_softc      *sc_if;
1141         u_int64_t               **aptr;
1142         int                     i;
1143         struct sk_jpool_entry   *entry;
1144
1145         /* Extract the softc struct pointer. */
1146         aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
1147         sc_if = (struct sk_if_softc *)(aptr[0]);
1148
1149         if (sc_if == NULL)
1150                 panic("sk_jfree: can't find softc pointer!");
1151
1152         if (size != SK_MCLBYTES)
1153                 panic("sk_jfree: freeing buffer of wrong size!");
1154
1155         /* calculate the slot this buffer belongs to */
1156
1157         i = ((vm_offset_t)aptr
1158              - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN;
1159
1160         if ((i < 0) || (i >= SK_JSLOTS))
1161                 panic("sk_jfree: asked to free buffer that we don't manage!");
1162         else if (sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0)
1163                 panic("sk_jfree: buffer already free!");
1164         else {
1165                 sc_if->sk_cdata.sk_jslots[i].sk_inuse--;
1166                 if(sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0) {
1167                         entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead);
1168                         if (entry == NULL)
1169                                 panic("sk_jfree: buffer not in use!");
1170                         entry->slot = i;
1171                         SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead,
1172                                           jpool_entries);
1173                         SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
1174                                           entry, jpool_entries);
1175                 }
1176         }
1177
1178         return;
1179 }
1180
1181 /*
1182  * Set media options.
1183  */
1184 static int sk_ifmedia_upd(ifp)
1185         struct ifnet            *ifp;
1186 {
1187         struct sk_if_softc      *sc_if = ifp->if_softc;
1188         struct mii_data         *mii;
1189
1190         mii = device_get_softc(sc_if->sk_miibus);
1191         sk_init(sc_if);
1192         mii_mediachg(mii);
1193
1194         return(0);
1195 }
1196
1197 /*
1198  * Report current media status.
1199  */
1200 static void sk_ifmedia_sts(ifp, ifmr)
1201         struct ifnet            *ifp;
1202         struct ifmediareq       *ifmr;
1203 {
1204         struct sk_if_softc      *sc_if;
1205         struct mii_data         *mii;
1206
1207         sc_if = ifp->if_softc;
1208         mii = device_get_softc(sc_if->sk_miibus);
1209
1210         mii_pollstat(mii);
1211         ifmr->ifm_active = mii->mii_media_active;
1212         ifmr->ifm_status = mii->mii_media_status;
1213
1214         return;
1215 }
1216
1217 static int sk_ioctl(ifp, command, data, cr)
1218         struct ifnet            *ifp;
1219         u_long                  command;
1220         caddr_t                 data;
1221         struct ucred            *cr;
1222 {
1223         struct sk_if_softc      *sc_if = ifp->if_softc;
1224         struct ifreq            *ifr = (struct ifreq *) data;
1225         int                     s, error = 0;
1226         struct mii_data         *mii;
1227
1228         s = splimp();
1229
1230         switch(command) {
1231         case SIOCSIFADDR:
1232         case SIOCGIFADDR:
1233                 error = ether_ioctl(ifp, command, data);
1234                 break;
1235         case SIOCSIFMTU:
1236                 if (ifr->ifr_mtu > SK_JUMBO_MTU)
1237                         error = EINVAL;
1238                 else {
1239                         ifp->if_mtu = ifr->ifr_mtu;
1240                         sk_init(sc_if);
1241                 }
1242                 break;
1243         case SIOCSIFFLAGS:
1244                 if (ifp->if_flags & IFF_UP) {
1245                         if (ifp->if_flags & IFF_RUNNING) {
1246                                 if ((ifp->if_flags ^ sc_if->sk_if_flags)
1247                                     & IFF_PROMISC) {
1248                                         sk_setpromisc(sc_if);
1249                                         sk_setmulti(sc_if);
1250                                 }
1251                         } else
1252                                 sk_init(sc_if);
1253                 } else {
1254                         if (ifp->if_flags & IFF_RUNNING)
1255                                 sk_stop(sc_if);
1256                 }
1257                 sc_if->sk_if_flags = ifp->if_flags;
1258                 error = 0;
1259                 break;
1260         case SIOCADDMULTI:
1261         case SIOCDELMULTI:
1262                 sk_setmulti(sc_if);
1263                 error = 0;
1264                 break;
1265         case SIOCGIFMEDIA:
1266         case SIOCSIFMEDIA:
1267                 mii = device_get_softc(sc_if->sk_miibus);
1268                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1269                 break;
1270         default:
1271                 error = EINVAL;
1272                 break;
1273         }
1274
1275         (void)splx(s);
1276
1277         return(error);
1278 }
1279
1280 /*
1281  * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1282  * IDs against our list and return a device name if we find a match.
1283  */
1284 static int skc_probe(dev)
1285         device_t                dev;
1286 {
1287         struct sk_softc         *sc;
1288         struct sk_type          *t = sk_devs;
1289
1290         sc = device_get_softc(dev);
1291
1292         while(t->sk_name != NULL) {
1293                 if ((pci_get_vendor(dev) == t->sk_vid) &&
1294                     (pci_get_device(dev) == t->sk_did)) {
1295                         device_set_desc(dev, t->sk_name);
1296                         return(0);
1297                 }
1298                 t++;
1299         }
1300
1301         return(ENXIO);
1302 }
1303
1304 /*
1305  * Force the GEnesis into reset, then bring it out of reset.
1306  */
1307 static void sk_reset(sc)
1308         struct sk_softc         *sc;
1309 {
1310         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1311         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1312         if (sc->sk_type == SK_YUKON)
1313                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1314
1315         DELAY(1000);
1316         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1317         DELAY(2);
1318         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1319         if (sc->sk_type == SK_YUKON)
1320                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1321
1322         if (sc->sk_type == SK_GENESIS) {
1323                 /* Configure packet arbiter */
1324                 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1325                 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1326                 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1327                 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1328                 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1329         }
1330
1331         /* Enable RAM interface */
1332         sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1333
1334         /*
1335          * Configure interrupt moderation. The moderation timer
1336          * defers interrupts specified in the interrupt moderation
1337          * timer mask based on the timeout specified in the interrupt
1338          * moderation timer init register. Each bit in the timer
1339          * register represents 18.825ns, so to specify a timeout in
1340          * microseconds, we have to multiply by 54.
1341          */
1342         sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200));
1343         sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1344             SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1345         sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1346
1347         return;
1348 }
1349
1350 static int sk_probe(dev)
1351         device_t                dev;
1352 {
1353         struct sk_softc         *sc;
1354
1355         sc = device_get_softc(device_get_parent(dev));
1356
1357         /*
1358          * Not much to do here. We always know there will be
1359          * at least one XMAC present, and if there are two,
1360          * skc_attach() will create a second device instance
1361          * for us.
1362          */
1363         switch (sc->sk_type) {
1364         case SK_GENESIS:
1365                 device_set_desc(dev, "XaQti Corp. XMAC II");
1366                 break;
1367         case SK_YUKON:
1368                 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
1369                 break;
1370         }
1371
1372         return(0);
1373 }
1374
1375 /*
1376  * Each XMAC chip is attached as a separate logical IP interface.
1377  * Single port cards will have only one logical interface of course.
1378  */
1379 static int sk_attach(dev)
1380         device_t                dev;
1381 {
1382         struct sk_softc         *sc;
1383         struct sk_if_softc      *sc_if;
1384         struct ifnet            *ifp;
1385         int                     i, port;
1386
1387         if (dev == NULL)
1388                 return(EINVAL);
1389
1390         sc_if = device_get_softc(dev);
1391         sc = device_get_softc(device_get_parent(dev));
1392         port = *(int *)device_get_ivars(dev);
1393         free(device_get_ivars(dev), M_DEVBUF);
1394         device_set_ivars(dev, NULL);
1395         sc_if->sk_dev = dev;
1396         callout_init(&sc_if->sk_tick_timer);
1397
1398         bzero((char *)sc_if, sizeof(struct sk_if_softc));
1399
1400         sc_if->sk_dev = dev;
1401         sc_if->sk_unit = device_get_unit(dev);
1402         sc_if->sk_port = port;
1403         sc_if->sk_softc = sc;
1404         sc->sk_if[port] = sc_if;
1405         if (port == SK_PORT_A)
1406                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1407         if (port == SK_PORT_B)
1408                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1409
1410         /*
1411          * Get station address for this interface. Note that
1412          * dual port cards actually come with three station
1413          * addresses: one for each port, plus an extra. The
1414          * extra one is used by the SysKonnect driver software
1415          * as a 'virtual' station address for when both ports
1416          * are operating in failover mode. Currently we don't
1417          * use this extra address.
1418          */
1419         for (i = 0; i < ETHER_ADDR_LEN; i++)
1420                 sc_if->arpcom.ac_enaddr[i] =
1421                     sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1422
1423         /*
1424          * Set up RAM buffer addresses. The NIC will have a certain
1425          * amount of SRAM on it, somewhere between 512K and 2MB. We
1426          * need to divide this up a) between the transmitter and
1427          * receiver and b) between the two XMACs, if this is a
1428          * dual port NIC. Our algotithm is to divide up the memory
1429          * evenly so that everyone gets a fair share.
1430          */
1431         if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1432                 u_int32_t               chunk, val;
1433
1434                 chunk = sc->sk_ramsize / 2;
1435                 val = sc->sk_rboff / sizeof(u_int64_t);
1436                 sc_if->sk_rx_ramstart = val;
1437                 val += (chunk / sizeof(u_int64_t));
1438                 sc_if->sk_rx_ramend = val - 1;
1439                 sc_if->sk_tx_ramstart = val;
1440                 val += (chunk / sizeof(u_int64_t));
1441                 sc_if->sk_tx_ramend = val - 1;
1442         } else {
1443                 u_int32_t               chunk, val;
1444
1445                 chunk = sc->sk_ramsize / 4;
1446                 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1447                     sizeof(u_int64_t);
1448                 sc_if->sk_rx_ramstart = val;
1449                 val += (chunk / sizeof(u_int64_t));
1450                 sc_if->sk_rx_ramend = val - 1;
1451                 sc_if->sk_tx_ramstart = val;
1452                 val += (chunk / sizeof(u_int64_t));
1453                 sc_if->sk_tx_ramend = val - 1;
1454         }
1455
1456         /* Read and save PHY type and set PHY address */
1457         sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1458         switch(sc_if->sk_phytype) {
1459         case SK_PHYTYPE_XMAC:
1460                 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1461                 break;
1462         case SK_PHYTYPE_BCOM:
1463                 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1464                 break;
1465         case SK_PHYTYPE_MARV_COPPER:
1466                 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1467                 break;
1468         default:
1469                 printf("skc%d: unsupported PHY type: %d\n",
1470                     sc->sk_unit, sc_if->sk_phytype);
1471                 return(ENODEV);
1472         }
1473
1474         /* Allocate the descriptor queues. */
1475         sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF,
1476             M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1477
1478         if (sc_if->sk_rdata == NULL) {
1479                 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit);
1480                 sc->sk_if[port] = NULL;
1481                 return(ENOMEM);
1482         }
1483
1484         bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data));
1485
1486         /* Try to allocate memory for jumbo buffers. */
1487         if (sk_alloc_jumbo_mem(sc_if)) {
1488                 printf("sk%d: jumbo buffer allocation failed\n",
1489                     sc_if->sk_unit);
1490                 contigfree(sc_if->sk_rdata,
1491                     sizeof(struct sk_ring_data), M_DEVBUF);
1492                 sc->sk_if[port] = NULL;
1493                 return(ENOMEM);
1494         }
1495
1496         ifp = &sc_if->arpcom.ac_if;
1497         ifp->if_softc = sc_if;
1498         if_initname(ifp, "sk", sc_if->sk_unit);
1499         ifp->if_mtu = ETHERMTU;
1500         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1501         ifp->if_ioctl = sk_ioctl;
1502         ifp->if_start = sk_start;
1503         ifp->if_watchdog = sk_watchdog;
1504         ifp->if_init = sk_init;
1505         ifp->if_baudrate = 1000000000;
1506         ifq_set_maxlen(&ifp->if_snd, SK_TX_RING_CNT - 1);
1507         ifq_set_ready(&ifp->if_snd);
1508
1509         /*
1510          * Do miibus setup.
1511          */
1512         switch (sc->sk_type) {
1513         case SK_GENESIS:
1514                 sk_init_xmac(sc_if);
1515                 break;
1516         case SK_YUKON:
1517                 sk_init_yukon(sc_if);
1518                 break;
1519         }
1520
1521         if (mii_phy_probe(dev, &sc_if->sk_miibus,
1522             sk_ifmedia_upd, sk_ifmedia_sts)) {
1523                 printf("skc%d: no PHY found!\n", sc_if->sk_unit);
1524                 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM,
1525                     M_DEVBUF);
1526                 contigfree(sc_if->sk_rdata,
1527                     sizeof(struct sk_ring_data), M_DEVBUF);
1528                 return(ENXIO);
1529         }
1530
1531         /*
1532          * Call MI attach routine.
1533          */
1534         ether_ifattach(ifp, sc_if->arpcom.ac_enaddr);
1535         callout_init(&sc_if->sk_tick_timer);
1536
1537         return(0);
1538 }
1539
1540 /*
1541  * Attach the interface. Allocate softc structures, do ifmedia
1542  * setup and ethernet/BPF attach.
1543  */
1544 static int skc_attach(dev)
1545         device_t                dev;
1546 {
1547         int                     s;
1548         u_int32_t               command;
1549         struct sk_softc         *sc;
1550         int                     unit, error = 0, rid, *port;
1551         uint8_t                 skrs;
1552
1553         s = splimp();
1554
1555         sc = device_get_softc(dev);
1556         unit = device_get_unit(dev);
1557         bzero(sc, sizeof(struct sk_softc));
1558         switch (pci_get_device(dev)) {
1559         case DEVICEID_SK_V1:
1560                 sc->sk_type = SK_GENESIS;
1561                 break;
1562         case DEVICEID_SK_V2:
1563         case DEVICEID_3COM_3C940:
1564         case DEVICEID_LINKSYS_EG1032:
1565         case DEVICEID_DLINK_DGE530T:
1566                 sc->sk_type = SK_YUKON;
1567                 break;
1568         }
1569
1570         /*
1571          * Handle power management nonsense.
1572          */
1573         command = pci_read_config(dev, SK_PCI_CAPID, 4) & 0x000000FF;
1574         if (command == 0x01) {
1575                 command = pci_read_config(dev, SK_PCI_PWRMGMTCTRL, 4);
1576                 if (command & SK_PSTATE_MASK) {
1577                         u_int32_t               iobase, membase, irq;
1578
1579                         /* Save important PCI config data. */
1580                         iobase = pci_read_config(dev, SK_PCI_LOIO, 4);
1581                         membase = pci_read_config(dev, SK_PCI_LOMEM, 4);
1582                         irq = pci_read_config(dev, SK_PCI_INTLINE, 4);
1583
1584                         /* Reset the power state. */
1585                         printf("skc%d: chip is in D%d power mode "
1586                         "-- setting to D0\n", unit, command & SK_PSTATE_MASK);
1587                         command &= 0xFFFFFFFC;
1588                         pci_write_config(dev, SK_PCI_PWRMGMTCTRL, command, 4);
1589
1590                         /* Restore PCI config data. */
1591                         pci_write_config(dev, SK_PCI_LOIO, iobase, 4);
1592                         pci_write_config(dev, SK_PCI_LOMEM, membase, 4);
1593                         pci_write_config(dev, SK_PCI_INTLINE, irq, 4);
1594                 }
1595         }
1596
1597         /*
1598          * Map control/status registers.
1599          */
1600         command = pci_read_config(dev, PCIR_COMMAND, 4);
1601         command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1602         pci_write_config(dev, PCIR_COMMAND, command, 4);
1603         command = pci_read_config(dev, PCIR_COMMAND, 4);
1604
1605 #ifdef SK_USEIOSPACE
1606         if (!(command & PCIM_CMD_PORTEN)) {
1607                 printf("skc%d: failed to enable I/O ports!\n", unit);
1608                 error = ENXIO;
1609                 goto fail;
1610         }
1611 #else
1612         if (!(command & PCIM_CMD_MEMEN)) {
1613                 printf("skc%d: failed to enable memory mapping!\n", unit);
1614                 error = ENXIO;
1615                 goto fail;
1616         }
1617 #endif
1618
1619         rid = SK_RID;
1620         sc->sk_res = bus_alloc_resource(dev, SK_RES, &rid,
1621             0, ~0, 1, RF_ACTIVE);
1622
1623         if (sc->sk_res == NULL) {
1624                 printf("sk%d: couldn't map ports/memory\n", unit);
1625                 error = ENXIO;
1626                 goto fail;
1627         }
1628
1629         sc->sk_btag = rman_get_bustag(sc->sk_res);
1630         sc->sk_bhandle = rman_get_bushandle(sc->sk_res);
1631
1632         /* Allocate interrupt */
1633         rid = 0;
1634         sc->sk_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1635             RF_SHAREABLE | RF_ACTIVE);
1636
1637         if (sc->sk_irq == NULL) {
1638                 printf("skc%d: couldn't map interrupt\n", unit);
1639                 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1640                 error = ENXIO;
1641                 goto fail;
1642         }
1643
1644         error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET,
1645             sk_intr, sc, &sc->sk_intrhand);
1646
1647         if (error) {
1648                 printf("skc%d: couldn't set up irq\n", unit);
1649                 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1650                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1651                 goto fail;
1652         }
1653
1654         /* Reset the adapter. */
1655         sk_reset(sc);
1656
1657         sc->sk_unit = unit;
1658
1659         /* Read and save vital product data from EEPROM. */
1660         sk_vpd_read(sc);
1661
1662         skrs = sk_win_read_1(sc, SK_EPROM0);
1663         if (sc->sk_type == SK_GENESIS) {
1664                 /* Read and save RAM size and RAMbuffer offset */
1665                 switch(skrs) {
1666                 case SK_RAMSIZE_512K_64:
1667                         sc->sk_ramsize = 0x80000;
1668                         sc->sk_rboff = SK_RBOFF_0;
1669                         break;
1670                 case SK_RAMSIZE_1024K_64:
1671                         sc->sk_ramsize = 0x100000;
1672                         sc->sk_rboff = SK_RBOFF_80000;
1673                         break;
1674                 case SK_RAMSIZE_1024K_128:
1675                         sc->sk_ramsize = 0x100000;
1676                         sc->sk_rboff = SK_RBOFF_0;
1677                         break;
1678                 case SK_RAMSIZE_2048K_128:
1679                         sc->sk_ramsize = 0x200000;
1680                         sc->sk_rboff = SK_RBOFF_0;
1681                         break;
1682                 default:
1683                         printf("skc%d: unknown ram size: %d\n",
1684                             sc->sk_unit, sk_win_read_1(sc, SK_EPROM0));
1685                         bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1686                         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1687                         bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1688                         error = ENXIO;
1689                         goto fail;
1690                         break;
1691                 }
1692         } else { /* SK_YUKON */
1693                 if (skrs == 0x00) {
1694                         sc->sk_ramsize = 0x20000;
1695                 } else {
1696                         sc->sk_ramsize = skrs * (1<<12);
1697                 }
1698                 sc->sk_rboff = SK_RBOFF_0;
1699         }
1700
1701         /* Read and save physical media type */
1702         switch(sk_win_read_1(sc, SK_PMDTYPE)) {
1703         case SK_PMD_1000BASESX:
1704                 sc->sk_pmd = IFM_1000_SX;
1705                 break;
1706         case SK_PMD_1000BASELX:
1707                 sc->sk_pmd = IFM_1000_LX;
1708                 break;
1709         case SK_PMD_1000BASECX:
1710                 sc->sk_pmd = IFM_1000_CX;
1711                 break;
1712         case SK_PMD_1000BASETX:
1713                 sc->sk_pmd = IFM_1000_T;
1714                 break;
1715         default:
1716                 printf("skc%d: unknown media type: 0x%x\n",
1717                     sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE));
1718                 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1719                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1720                 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1721                 error = ENXIO;
1722                 goto fail;
1723         }
1724
1725         /* Announce the product name. */
1726         printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname);
1727         sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1728         port = malloc(sizeof(int), M_DEVBUF, M_WAITOK);
1729         *port = SK_PORT_A;
1730         device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1731
1732         if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1733                 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1734                 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK);
1735                 *port = SK_PORT_B;
1736                 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1737         }
1738
1739         /* Turn on the 'driver is loaded' LED. */
1740         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1741
1742         bus_generic_attach(dev);
1743
1744 fail:
1745         splx(s);
1746         return(error);
1747 }
1748
1749 static int sk_detach(dev)
1750         device_t                dev;
1751 {
1752         struct sk_softc         *sc;
1753         struct sk_if_softc      *sc_if;
1754         struct ifnet            *ifp;
1755         int                     s;
1756
1757         s = splimp();
1758
1759         sc = device_get_softc(device_get_parent(dev));
1760         sc_if = device_get_softc(dev);
1761         ifp = &sc_if->arpcom.ac_if;
1762         sk_stop(sc_if);
1763         ether_ifdetach(ifp);
1764         bus_generic_detach(dev);
1765         if (sc_if->sk_miibus != NULL)
1766                 device_delete_child(dev, sc_if->sk_miibus);
1767         contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF);
1768         contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), M_DEVBUF);
1769
1770         return(0);
1771 }
1772
1773 static int skc_detach(dev)
1774         device_t                dev;
1775 {
1776         struct sk_softc         *sc;
1777         int                     s;
1778
1779         s = splimp();
1780
1781         sc = device_get_softc(dev);
1782
1783         bus_generic_detach(dev);
1784         if (sc->sk_devs[SK_PORT_A] != NULL)
1785                 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1786         if (sc->sk_devs[SK_PORT_B] != NULL)
1787                 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1788
1789         bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1790         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1791         bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1792
1793         splx(s);
1794
1795         return(0);
1796 }
1797
1798 static int sk_encap(sc_if, m_head, txidx)
1799         struct sk_if_softc      *sc_if;
1800         struct mbuf             *m_head;
1801         u_int32_t               *txidx;
1802 {
1803         struct sk_tx_desc       *f = NULL;
1804         struct mbuf             *m;
1805         u_int32_t               frag, cur, cnt = 0;
1806
1807         m = m_head;
1808         cur = frag = *txidx;
1809
1810         /*
1811          * Start packing the mbufs in this chain into
1812          * the fragment pointers. Stop when we run out
1813          * of fragments or hit the end of the mbuf chain.
1814          */
1815         for (m = m_head; m != NULL; m = m->m_next) {
1816                 if (m->m_len != 0) {
1817                         if ((SK_TX_RING_CNT -
1818                             (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2)
1819                                 return(ENOBUFS);
1820                         f = &sc_if->sk_rdata->sk_tx_ring[frag];
1821                         f->sk_data_lo = vtophys(mtod(m, vm_offset_t));
1822                         f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT;
1823                         if (cnt == 0)
1824                                 f->sk_ctl |= SK_TXCTL_FIRSTFRAG;
1825                         else
1826                                 f->sk_ctl |= SK_TXCTL_OWN;
1827                         cur = frag;
1828                         SK_INC(frag, SK_TX_RING_CNT);
1829                         cnt++;
1830                 }
1831         }
1832
1833         if (m != NULL)
1834                 return(ENOBUFS);
1835
1836         sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |=
1837                 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR;
1838         sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head;
1839         sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN;
1840         sc_if->sk_cdata.sk_tx_cnt += cnt;
1841
1842         *txidx = frag;
1843
1844         return(0);
1845 }
1846
1847 static void sk_start(ifp)
1848         struct ifnet            *ifp;
1849 {
1850         struct sk_softc         *sc;
1851         struct sk_if_softc      *sc_if;
1852         struct mbuf             *m_head = NULL;
1853         u_int32_t               idx;
1854
1855         sc_if = ifp->if_softc;
1856         sc = sc_if->sk_softc;
1857
1858         idx = sc_if->sk_cdata.sk_tx_prod;
1859
1860         while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) {
1861                 m_head = ifq_poll(&ifp->if_snd);
1862                 if (m_head == NULL)
1863                         break;
1864
1865                 /*
1866                  * Pack the data into the transmit ring. If we
1867                  * don't have room, set the OACTIVE flag and wait
1868                  * for the NIC to drain the ring.
1869                  */
1870                 if (sk_encap(sc_if, m_head, &idx)) {
1871                         ifp->if_flags |= IFF_OACTIVE;
1872                         break;
1873                 }
1874                 m_head = ifq_dequeue(&ifp->if_snd);
1875
1876                 BPF_MTAP(ifp, m_head);
1877         }
1878
1879         /* Transmit */
1880         sc_if->sk_cdata.sk_tx_prod = idx;
1881         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
1882
1883         /* Set a timeout in case the chip goes out to lunch. */
1884         ifp->if_timer = 5;
1885
1886         return;
1887 }
1888
1889
1890 static void sk_watchdog(ifp)
1891         struct ifnet            *ifp;
1892 {
1893         struct sk_if_softc      *sc_if;
1894
1895         sc_if = ifp->if_softc;
1896
1897         printf("sk%d: watchdog timeout\n", sc_if->sk_unit);
1898         sk_init(sc_if);
1899
1900         return;
1901 }
1902
1903 static void skc_shutdown(dev)
1904         device_t                dev;
1905 {
1906         struct sk_softc         *sc;
1907
1908         sc = device_get_softc(dev);
1909
1910         /* Turn off the 'driver is loaded' LED. */
1911         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
1912
1913         /*
1914          * Reset the GEnesis controller. Doing this should also
1915          * assert the resets on the attached XMAC(s).
1916          */
1917         sk_reset(sc);
1918
1919         return;
1920 }
1921
1922 static void sk_rxeof(sc_if)
1923         struct sk_if_softc      *sc_if;
1924 {
1925         struct mbuf             *m;
1926         struct ifnet            *ifp;
1927         struct sk_chain         *cur_rx;
1928         int                     total_len = 0;
1929         int                     i;
1930         u_int32_t               rxstat;
1931
1932         ifp = &sc_if->arpcom.ac_if;
1933         i = sc_if->sk_cdata.sk_rx_prod;
1934         cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
1935
1936         while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) {
1937
1938                 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
1939                 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat;
1940                 m = cur_rx->sk_mbuf;
1941                 cur_rx->sk_mbuf = NULL;
1942                 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl);
1943                 SK_INC(i, SK_RX_RING_CNT);
1944
1945                 if (rxstat & XM_RXSTAT_ERRFRAME) {
1946                         ifp->if_ierrors++;
1947                         sk_newbuf(sc_if, cur_rx, m);
1948                         continue;
1949                 }
1950
1951                 /*
1952                  * Try to allocate a new jumbo buffer. If that
1953                  * fails, copy the packet to mbufs and put the
1954                  * jumbo buffer back in the ring so it can be
1955                  * re-used. If allocating mbufs fails, then we
1956                  * have to drop the packet.
1957                  */
1958                 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) {
1959                         struct mbuf             *m0;
1960                         m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1961                             total_len + ETHER_ALIGN, 0, ifp, NULL);
1962                         sk_newbuf(sc_if, cur_rx, m);
1963                         if (m0 == NULL) {
1964                                 printf("sk%d: no receive buffers "
1965                                     "available -- packet dropped!\n",
1966                                     sc_if->sk_unit);
1967                                 ifp->if_ierrors++;
1968                                 continue;
1969                         }
1970                         m_adj(m0, ETHER_ALIGN);
1971                         m = m0;
1972                 } else {
1973                         m->m_pkthdr.rcvif = ifp;
1974                         m->m_pkthdr.len = m->m_len = total_len;
1975                 }
1976
1977                 ifp->if_ipackets++;
1978                 (*ifp->if_input)(ifp, m);
1979         }
1980
1981         sc_if->sk_cdata.sk_rx_prod = i;
1982
1983         return;
1984 }
1985
1986 static void sk_txeof(sc_if)
1987         struct sk_if_softc      *sc_if;
1988 {
1989         struct sk_tx_desc       *cur_tx = NULL;
1990         struct ifnet            *ifp;
1991         u_int32_t               idx;
1992
1993         ifp = &sc_if->arpcom.ac_if;
1994
1995         /*
1996          * Go through our tx ring and free mbufs for those
1997          * frames that have been sent.
1998          */
1999         idx = sc_if->sk_cdata.sk_tx_cons;
2000         while(idx != sc_if->sk_cdata.sk_tx_prod) {
2001                 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx];
2002                 if (cur_tx->sk_ctl & SK_TXCTL_OWN)
2003                         break;
2004                 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG)
2005                         ifp->if_opackets++;
2006                 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) {
2007                         m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf);
2008                         sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL;
2009                 }
2010                 sc_if->sk_cdata.sk_tx_cnt--;
2011                 SK_INC(idx, SK_TX_RING_CNT);
2012                 ifp->if_timer = 0;
2013         }
2014
2015         sc_if->sk_cdata.sk_tx_cons = idx;
2016
2017         if (cur_tx != NULL)
2018                 ifp->if_flags &= ~IFF_OACTIVE;
2019
2020         return;
2021 }
2022
2023 static void sk_tick(xsc_if)
2024         void                    *xsc_if;
2025 {
2026         struct sk_if_softc      *sc_if;
2027         struct mii_data         *mii;
2028         struct ifnet            *ifp;
2029         int                     i;
2030
2031         sc_if = xsc_if;
2032         ifp = &sc_if->arpcom.ac_if;
2033         mii = device_get_softc(sc_if->sk_miibus);
2034
2035         if (!(ifp->if_flags & IFF_UP))
2036                 return;
2037
2038         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2039                 sk_intr_bcom(sc_if);
2040                 return;
2041         }
2042
2043         /*
2044          * According to SysKonnect, the correct way to verify that
2045          * the link has come back up is to poll bit 0 of the GPIO
2046          * register three times. This pin has the signal from the
2047          * link_sync pin connected to it; if we read the same link
2048          * state 3 times in a row, we know the link is up.
2049          */
2050         for (i = 0; i < 3; i++) {
2051                 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2052                         break;
2053         }
2054
2055         if (i != 3) {
2056                 callout_reset(&sc_if->sk_tick_timer, hz, sk_tick, sc_if);
2057                 return;
2058         }
2059
2060         /* Turn the GP0 interrupt back on. */
2061         SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2062         SK_XM_READ_2(sc_if, XM_ISR);
2063         mii_tick(mii);
2064         mii_pollstat(mii);
2065         callout_stop(&sc_if->sk_tick_timer);
2066
2067         return;
2068 }
2069
2070 static void sk_intr_bcom(sc_if)
2071         struct sk_if_softc      *sc_if;
2072 {
2073         struct sk_softc         *sc;
2074         struct mii_data         *mii;
2075         struct ifnet            *ifp;
2076         int                     status;
2077
2078         sc = sc_if->sk_softc;
2079         mii = device_get_softc(sc_if->sk_miibus);
2080         ifp = &sc_if->arpcom.ac_if;
2081
2082         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2083
2084         /*
2085          * Read the PHY interrupt register to make sure
2086          * we clear any pending interrupts.
2087          */
2088         status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
2089
2090         if (!(ifp->if_flags & IFF_RUNNING)) {
2091                 sk_init_xmac(sc_if);
2092                 return;
2093         }
2094
2095         if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
2096                 int                     lstat;
2097                 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
2098                     BRGPHY_MII_AUXSTS);
2099
2100                 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
2101                         mii_mediachg(mii);
2102                         /* Turn off the link LED. */
2103                         SK_IF_WRITE_1(sc_if, 0,
2104                             SK_LINKLED1_CTL, SK_LINKLED_OFF);
2105                         sc_if->sk_link = 0;
2106                 } else if (status & BRGPHY_ISR_LNK_CHG) {
2107                         sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2108                             BRGPHY_MII_IMR, 0xFF00);
2109                         mii_tick(mii);
2110                         sc_if->sk_link = 1;
2111                         /* Turn on the link LED. */
2112                         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2113                             SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
2114                             SK_LINKLED_BLINK_OFF);
2115                         mii_pollstat(mii);
2116                 } else {
2117                         mii_tick(mii);
2118                         callout_reset(&sc_if->sk_tick_timer, hz,
2119                                       sk_tick, sc_if);
2120                 }
2121         }
2122
2123         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2124
2125         return;
2126 }
2127
2128 static void sk_intr_xmac(sc_if)
2129         struct sk_if_softc      *sc_if;
2130 {
2131         struct sk_softc         *sc;
2132         u_int16_t               status;
2133         struct mii_data         *mii;
2134
2135         sc = sc_if->sk_softc;
2136         mii = device_get_softc(sc_if->sk_miibus);
2137         status = SK_XM_READ_2(sc_if, XM_ISR);
2138
2139         /*
2140          * Link has gone down. Start MII tick timeout to
2141          * watch for link resync.
2142          */
2143         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
2144                 if (status & XM_ISR_GP0_SET) {
2145                         SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2146                         callout_reset(&sc_if->sk_tick_timer, hz,
2147                                       sk_tick, sc_if);
2148                 }
2149
2150                 if (status & XM_ISR_AUTONEG_DONE) {
2151                         callout_reset(&sc_if->sk_tick_timer, hz,
2152                                       sk_tick, sc_if);
2153                 }
2154         }
2155
2156         if (status & XM_IMR_TX_UNDERRUN)
2157                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
2158
2159         if (status & XM_IMR_RX_OVERRUN)
2160                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
2161
2162         status = SK_XM_READ_2(sc_if, XM_ISR);
2163
2164         return;
2165 }
2166
2167 static void sk_intr_yukon(sc_if)
2168         struct sk_if_softc      *sc_if;
2169 {
2170         int status;
2171
2172         status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2173
2174         return;
2175 }
2176
2177 static void sk_intr(xsc)
2178         void                    *xsc;
2179 {
2180         struct sk_softc         *sc = xsc;
2181         struct sk_if_softc      *sc_if0 = NULL, *sc_if1 = NULL;
2182         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
2183         u_int32_t               status;
2184
2185         sc_if0 = sc->sk_if[SK_PORT_A];
2186         sc_if1 = sc->sk_if[SK_PORT_B];
2187
2188         if (sc_if0 != NULL)
2189                 ifp0 = &sc_if0->arpcom.ac_if;
2190         if (sc_if1 != NULL)
2191                 ifp1 = &sc_if1->arpcom.ac_if;
2192
2193         for (;;) {
2194                 status = CSR_READ_4(sc, SK_ISSR);
2195                 if (!(status & sc->sk_intrmask))
2196                         break;
2197
2198                 /* Handle receive interrupts first. */
2199                 if (status & SK_ISR_RX1_EOF) {
2200                         sk_rxeof(sc_if0);
2201                         CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
2202                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2203                 }
2204                 if (status & SK_ISR_RX2_EOF) {
2205                         sk_rxeof(sc_if1);
2206                         CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
2207                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2208                 }
2209
2210                 /* Then transmit interrupts. */
2211                 if (status & SK_ISR_TX1_S_EOF) {
2212                         sk_txeof(sc_if0);
2213                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR0,
2214                             SK_TXBMU_CLR_IRQ_EOF);
2215                 }
2216                 if (status & SK_ISR_TX2_S_EOF) {
2217                         sk_txeof(sc_if1);
2218                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR1,
2219                             SK_TXBMU_CLR_IRQ_EOF);
2220                 }
2221
2222                 /* Then MAC interrupts. */
2223                 if (status & SK_ISR_MAC1 && ifp0->if_flags & IFF_RUNNING) {
2224                         if (sc->sk_type == SK_GENESIS)
2225                                 sk_intr_xmac(sc_if0);
2226                         else
2227                                 sk_intr_yukon(sc_if0);
2228                 }
2229
2230                 if (status & SK_ISR_MAC2 && ifp1->if_flags & IFF_RUNNING) {
2231                         if (sc->sk_type == SK_GENESIS)
2232                                 sk_intr_xmac(sc_if1);
2233                         else
2234                                 sk_intr_yukon(sc_if0);
2235                 }
2236
2237                 if (status & SK_ISR_EXTERNAL_REG) {
2238                         if (ifp0 != NULL &&
2239                             sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
2240                                 sk_intr_bcom(sc_if0);
2241                         if (ifp1 != NULL &&
2242                             sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
2243                                 sk_intr_bcom(sc_if1);
2244                 }
2245         }
2246
2247         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2248
2249         if (ifp0 != NULL && !ifq_is_empty(&ifp0->if_snd))
2250                 sk_start(ifp0);
2251         if (ifp1 != NULL && !ifq_is_empty(&ifp0->if_snd))
2252                 sk_start(ifp1);
2253
2254         return;
2255 }
2256
2257 static void sk_init_xmac(sc_if)
2258         struct sk_if_softc      *sc_if;
2259 {
2260         struct sk_softc         *sc;
2261         struct ifnet            *ifp;
2262         struct sk_bcom_hack     bhack[] = {
2263         { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
2264         { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
2265         { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
2266         { 0, 0 } };
2267
2268         sc = sc_if->sk_softc;
2269         ifp = &sc_if->arpcom.ac_if;
2270
2271         /* Unreset the XMAC. */
2272         SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
2273         DELAY(1000);
2274
2275         /* Reset the XMAC's internal state. */
2276         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2277
2278         /* Save the XMAC II revision */
2279         sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
2280
2281         /*
2282          * Perform additional initialization for external PHYs,
2283          * namely for the 1000baseTX cards that use the XMAC's
2284          * GMII mode.
2285          */
2286         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2287                 int                     i = 0;
2288                 u_int32_t               val;
2289
2290                 /* Take PHY out of reset. */
2291                 val = sk_win_read_4(sc, SK_GPIO);
2292                 if (sc_if->sk_port == SK_PORT_A)
2293                         val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
2294                 else
2295                         val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
2296                 sk_win_write_4(sc, SK_GPIO, val);
2297
2298                 /* Enable GMII mode on the XMAC. */
2299                 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
2300
2301                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2302                     BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
2303                 DELAY(10000);
2304                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2305                     BRGPHY_MII_IMR, 0xFFF0);
2306
2307                 /*
2308                  * Early versions of the BCM5400 apparently have
2309                  * a bug that requires them to have their reserved
2310                  * registers initialized to some magic values. I don't
2311                  * know what the numbers do, I'm just the messenger.
2312                  */
2313                 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
2314                     == 0x6041) {
2315                         while(bhack[i].reg) {
2316                                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2317                                     bhack[i].reg, bhack[i].val);
2318                                 i++;
2319                         }
2320                 }
2321         }
2322
2323         /* Set station address */
2324         SK_XM_WRITE_2(sc_if, XM_PAR0,
2325             *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0]));
2326         SK_XM_WRITE_2(sc_if, XM_PAR1,
2327             *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2]));
2328         SK_XM_WRITE_2(sc_if, XM_PAR2,
2329             *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4]));
2330         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
2331
2332         if (ifp->if_flags & IFF_BROADCAST) {
2333                 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2334         } else {
2335                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2336         }
2337
2338         /* We don't need the FCS appended to the packet. */
2339         SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
2340
2341         /* We want short frames padded to 60 bytes. */
2342         SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
2343
2344         /*
2345          * Enable the reception of all error frames. This is is
2346          * a necessary evil due to the design of the XMAC. The
2347          * XMAC's receive FIFO is only 8K in size, however jumbo
2348          * frames can be up to 9000 bytes in length. When bad
2349          * frame filtering is enabled, the XMAC's RX FIFO operates
2350          * in 'store and forward' mode. For this to work, the
2351          * entire frame has to fit into the FIFO, but that means
2352          * that jumbo frames larger than 8192 bytes will be
2353          * truncated. Disabling all bad frame filtering causes
2354          * the RX FIFO to operate in streaming mode, in which
2355          * case the XMAC will start transfering frames out of the
2356          * RX FIFO as soon as the FIFO threshold is reached.
2357          */
2358         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
2359             XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
2360             XM_MODE_RX_INRANGELEN);
2361
2362         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2363                 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2364         else
2365                 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2366
2367         /*
2368          * Bump up the transmit threshold. This helps hold off transmit
2369          * underruns when we're blasting traffic from both ports at once.
2370          */
2371         SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
2372
2373         /* Set promiscuous mode */
2374         sk_setpromisc(sc_if);
2375
2376         /* Set multicast filter */
2377         sk_setmulti(sc_if);
2378
2379         /* Clear and enable interrupts */
2380         SK_XM_READ_2(sc_if, XM_ISR);
2381         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
2382                 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
2383         else
2384                 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2385
2386         /* Configure MAC arbiter */
2387         switch(sc_if->sk_xmac_rev) {
2388         case XM_XMAC_REV_B2:
2389                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
2390                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
2391                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
2392                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
2393                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
2394                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
2395                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
2396                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
2397                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2398                 break;
2399         case XM_XMAC_REV_C1:
2400                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
2401                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
2402                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
2403                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
2404                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
2405                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
2406                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
2407                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
2408                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2409                 break;
2410         default:
2411                 break;
2412         }
2413         sk_win_write_2(sc, SK_MACARB_CTL,
2414             SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
2415
2416         sc_if->sk_link = 1;
2417
2418         return;
2419 }
2420
2421 static void sk_init_yukon(sc_if)
2422         struct sk_if_softc      *sc_if;
2423 {
2424         u_int32_t               phy;
2425         u_int16_t               reg;
2426         struct sk_softc         *sc;
2427         struct ifnet            *ifp;
2428         int                     i;
2429
2430         sc = sc_if->sk_softc;
2431         ifp = &sc_if->arpcom.ac_if;
2432
2433         /* GMAC and GPHY Reset */
2434         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
2435         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2436         DELAY(1000);
2437         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR);
2438         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2439         DELAY(1000);
2440
2441         phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
2442                 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
2443
2444         switch(sc_if->sk_softc->sk_pmd) {
2445         case IFM_1000_SX:
2446         case IFM_1000_LX:
2447                 phy |= SK_GPHY_FIBER;
2448                 break;
2449
2450         case IFM_1000_CX:
2451         case IFM_1000_T:
2452                 phy |= SK_GPHY_COPPER;
2453                 break;
2454         }
2455
2456         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
2457         DELAY(1000);
2458         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
2459         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
2460                       SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
2461
2462         /* unused read of the interrupt source register */
2463         SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2464
2465         reg = SK_YU_READ_2(sc_if, YUKON_PAR);
2466
2467         /* MIB Counter Clear Mode set */
2468         reg |= YU_PAR_MIB_CLR;
2469         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2470
2471         /* MIB Counter Clear Mode clear */
2472         reg &= ~YU_PAR_MIB_CLR;
2473         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2474
2475         /* receive control reg */
2476         SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
2477
2478         /* transmit parameter register */
2479         SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
2480                       YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
2481
2482         /* serial mode register */
2483         reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
2484         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2485                 reg |= YU_SMR_MFL_JUMBO;
2486         SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
2487
2488         /* Setup Yukon's address */
2489         for (i = 0; i < 3; i++) {
2490                 /* Write Source Address 1 (unicast filter) */
2491                 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
2492                               sc_if->arpcom.ac_enaddr[i * 2] |
2493                               sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8);
2494         }
2495
2496         for (i = 0; i < 3; i++) {
2497                 reg = sk_win_read_2(sc_if->sk_softc,
2498                                     SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
2499                 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
2500         }
2501
2502         /* Set promiscuous mode */
2503         sk_setpromisc(sc_if);
2504
2505         /* Set multicast filter */
2506         sk_setmulti(sc_if);
2507
2508         /* enable interrupt mask for counter overflows */
2509         SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
2510         SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
2511         SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
2512
2513         /* Configure RX MAC FIFO */
2514         SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
2515         SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON);
2516
2517         /* Configure TX MAC FIFO */
2518         SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
2519         SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
2520 }
2521
2522 /*
2523  * Note that to properly initialize any part of the GEnesis chip,
2524  * you first have to take it out of reset mode.
2525  */
2526 static void sk_init(xsc)
2527         void                    *xsc;
2528 {
2529         struct sk_if_softc      *sc_if = xsc;
2530         struct sk_softc         *sc;
2531         struct ifnet            *ifp;
2532         struct mii_data         *mii;
2533         int                     s;
2534         u_int16_t               reg;
2535
2536         s = splimp();
2537
2538         ifp = &sc_if->arpcom.ac_if;
2539         sc = sc_if->sk_softc;
2540         mii = device_get_softc(sc_if->sk_miibus);
2541
2542         /* Cancel pending I/O and free all RX/TX buffers. */
2543         sk_stop(sc_if);
2544
2545         if (sc->sk_type == SK_GENESIS) {
2546                 /* Configure LINK_SYNC LED */
2547                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
2548                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2549                         SK_LINKLED_LINKSYNC_ON);
2550
2551                 /* Configure RX LED */
2552                 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
2553                         SK_RXLEDCTL_COUNTER_START);
2554
2555                 /* Configure TX LED */
2556                 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
2557                         SK_TXLEDCTL_COUNTER_START);
2558         }
2559
2560         /* Configure I2C registers */
2561
2562         /* Configure XMAC(s) */
2563         switch (sc->sk_type) {
2564         case SK_GENESIS:
2565                 sk_init_xmac(sc_if);
2566                 break;
2567         case SK_YUKON:
2568                 sk_init_yukon(sc_if);
2569                 break;
2570         }
2571         mii_mediachg(mii);
2572
2573         if (sc->sk_type == SK_GENESIS) {
2574                 /* Configure MAC FIFOs */
2575                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
2576                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
2577                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
2578
2579                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
2580                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
2581                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
2582         }
2583
2584         /* Configure transmit arbiter(s) */
2585         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
2586             SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
2587
2588         /* Configure RAMbuffers */
2589         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2590         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2591         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2592         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2593         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2594         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2595
2596         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
2597         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
2598         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
2599         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
2600         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
2601         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
2602         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
2603
2604         /* Configure BMUs */
2605         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
2606         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
2607             vtophys(&sc_if->sk_rdata->sk_rx_ring[0]));
2608         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0);
2609
2610         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
2611         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
2612             vtophys(&sc_if->sk_rdata->sk_tx_ring[0]));
2613         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0);
2614
2615         /* Init descriptors */
2616         if (sk_init_rx_ring(sc_if) == ENOBUFS) {
2617                 printf("sk%d: initialization failed: no "
2618                     "memory for rx buffers\n", sc_if->sk_unit);
2619                 sk_stop(sc_if);
2620                 (void)splx(s);
2621                 return;
2622         }
2623         sk_init_tx_ring(sc_if);
2624
2625         /* Configure interrupt handling */
2626         CSR_READ_4(sc, SK_ISSR);
2627         if (sc_if->sk_port == SK_PORT_A)
2628                 sc->sk_intrmask |= SK_INTRS1;
2629         else
2630                 sc->sk_intrmask |= SK_INTRS2;
2631
2632         sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
2633
2634         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2635
2636         /* Start BMUs. */
2637         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
2638
2639         switch(sc->sk_type) {
2640         case SK_GENESIS:
2641                 /* Enable XMACs TX and RX state machines */
2642                 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
2643                 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2644                 break;
2645         case SK_YUKON:
2646                 reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
2647                 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
2648                 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN);
2649                 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
2650         }
2651
2652         ifp->if_flags |= IFF_RUNNING;
2653         ifp->if_flags &= ~IFF_OACTIVE;
2654
2655         splx(s);
2656
2657         return;
2658 }
2659
2660 static void sk_stop(sc_if)
2661         struct sk_if_softc      *sc_if;
2662 {
2663         int                     i;
2664         struct sk_softc         *sc;
2665         struct ifnet            *ifp;
2666
2667         sc = sc_if->sk_softc;
2668         ifp = &sc_if->arpcom.ac_if;
2669
2670         callout_stop(&sc_if->sk_tick_timer);
2671
2672         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2673                 u_int32_t               val;
2674
2675                 /* Put PHY back into reset. */
2676                 val = sk_win_read_4(sc, SK_GPIO);
2677                 if (sc_if->sk_port == SK_PORT_A) {
2678                         val |= SK_GPIO_DIR0;
2679                         val &= ~SK_GPIO_DAT0;
2680                 } else {
2681                         val |= SK_GPIO_DIR2;
2682                         val &= ~SK_GPIO_DAT2;
2683                 }
2684                 sk_win_write_4(sc, SK_GPIO, val);
2685         }
2686
2687         /* Turn off various components of this interface. */
2688         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2689         switch (sc->sk_type) {
2690         case SK_GENESIS:
2691                 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
2692                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
2693                 break;
2694         case SK_YUKON:
2695                 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
2696                 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
2697                 break;
2698         }
2699         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2700         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2701         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
2702         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2703         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2704         SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2705         SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2706         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2707         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2708
2709         /* Disable interrupts */
2710         if (sc_if->sk_port == SK_PORT_A)
2711                 sc->sk_intrmask &= ~SK_INTRS1;
2712         else
2713                 sc->sk_intrmask &= ~SK_INTRS2;
2714         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2715
2716         SK_XM_READ_2(sc_if, XM_ISR);
2717         SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2718
2719         /* Free RX and TX mbufs still in the queues. */
2720         for (i = 0; i < SK_RX_RING_CNT; i++) {
2721                 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) {
2722                         m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf);
2723                         sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL;
2724                 }
2725         }
2726
2727         for (i = 0; i < SK_TX_RING_CNT; i++) {
2728                 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) {
2729                         m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf);
2730                         sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL;
2731                 }
2732         }
2733
2734         ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
2735
2736         return;
2737 }