2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 1997 KATO Takenori.
5 * Copyright (c) 2001 Tamotsu Hattori.
6 * Copyright (c) 2001 Mitsuru IWASAKI.
9 * This code is derived from software contributed to Berkeley by
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the University of
23 * California, Berkeley and its contributors.
24 * 4. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
41 * $FreeBSD: src/sys/i386/i386/identcpu.c,v 1.80.2.15 2003/04/11 17:06:41 jhb Exp $
42 * $DragonFly: src/sys/platform/pc32/i386/identcpu.c,v 1.24 2008/11/24 13:14:21 swildner Exp $
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/sysctl.h>
53 #include <machine/asmacros.h>
54 #include <machine/clock.h>
55 #include <machine/cputypes.h>
56 #include <machine/segments.h>
57 #include <machine/specialreg.h>
58 #include <machine/md_var.h>
60 #include <machine_base/isa/intr_machdep.h>
62 #define IDENTBLUE_CYRIX486 0
63 #define IDENTBLUE_IBMCPU 1
64 #define IDENTBLUE_CYRIXM2 2
66 /* XXX - should be in header file: */
67 void printcpuinfo(void);
68 void finishidentcpu(void);
69 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
70 void enable_K5_wt_alloc(void);
71 void enable_K6_wt_alloc(void);
72 void enable_K6_2_wt_alloc(void);
74 void panicifcpuunsupported(void);
76 static void identifycyrix(void);
77 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
78 static void print_AMD_features(void);
80 static void print_AMD_info(void);
81 static void print_AMD_assoc(int i);
82 static void print_transmeta_info(void);
83 static void setup_tmx86_longrun(void);
84 static void print_via_padlock_info(void);
86 int cpu_class = CPUCLASS_386;
87 u_int cpu_exthigh; /* Highest arg to extended CPUID */
88 u_int cyrix_did; /* Device ID of Cyrix CPU */
89 char machine[] = MACHINE;
90 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
91 machine, 0, "Machine class");
93 static char cpu_model[128];
94 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
95 cpu_model, 0, "Machine model");
97 static char cpu_brand[48];
99 #define MAX_ADDITIONAL_INFO 16
101 static const char *additional_cpu_info_ary[MAX_ADDITIONAL_INFO];
102 static u_int additional_cpu_info_count;
104 #define MAX_BRAND_INDEX 23
107 * Brand ID's according to Intel document AP-485, number 241618-31, published
108 * September 2006, page 42.
110 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
114 "Intel Pentium III Xeon",
116 NULL, /* Unspecified */
117 "Mobile Intel Pentium III-M",
118 "Mobile Intel Celeron",
124 NULL, /* Unspecified */
125 "Mobile Intel Pentium 4-M",
126 "Mobile Intel Celeron",
127 NULL, /* Unspecified */
128 "Mobile Genuine Intel",
130 "Mobile Intel Celeron",
132 "Mobile Genuine Intel",
134 "Mobile Intel Celeron"
137 static struct cpu_nameclass i386_cpus[] = {
138 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
139 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
140 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
141 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
142 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
143 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
144 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
145 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
146 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
147 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
148 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
149 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
150 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
151 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
152 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
153 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
154 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
157 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
158 int has_f00f_bug = 0; /* Initialized so that it can be patched. */
164 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
169 cpu_class = i386_cpus[cpu].cpu_class;
171 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
173 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
174 /* Check for extended CPUID information and a processor name. */
176 (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
177 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
178 strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
179 strcmp(cpu_vendor, "TransmetaCPU") == 0)) {
180 do_cpuid(0x80000000, regs);
181 if (regs[0] >= 0x80000000) {
182 cpu_exthigh = regs[0];
183 if (cpu_exthigh >= 0x80000004) {
185 for (i = 0x80000002; i < 0x80000005; i++) {
187 memcpy(brand, regs, sizeof(regs));
188 brand += sizeof(regs);
194 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
195 if ((cpu_id & 0xf00) > 0x300) {
200 switch (cpu_id & 0x3000) {
202 strcpy(cpu_model, "Overdrive ");
205 strcpy(cpu_model, "Dual ");
209 switch (cpu_id & 0xf00) {
211 strcat(cpu_model, "i486 ");
212 /* Check the particular flavor of 486 */
213 switch (cpu_id & 0xf0) {
216 strcat(cpu_model, "DX");
219 strcat(cpu_model, "SX");
222 strcat(cpu_model, "DX2");
225 strcat(cpu_model, "SL");
228 strcat(cpu_model, "SX2");
232 "DX2 Write-Back Enhanced");
235 strcat(cpu_model, "DX4");
240 /* Check the particular flavor of 586 */
241 strcat(cpu_model, "Pentium");
242 switch (cpu_id & 0xf0) {
244 strcat(cpu_model, " A-step");
247 strcat(cpu_model, "/P5");
250 strcat(cpu_model, "/P54C");
253 strcat(cpu_model, "/P54T Overdrive");
256 strcat(cpu_model, "/P55C");
259 strcat(cpu_model, "/P54C");
262 strcat(cpu_model, "/P55C (quarter-micron)");
268 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
270 * XXX - If/when Intel fixes the bug, this
271 * should also check the version of the
272 * CPU, not just that it's a Pentium.
278 /* Check the particular flavor of 686 */
279 switch (cpu_id & 0xf0) {
281 strcat(cpu_model, "Pentium Pro A-step");
284 strcat(cpu_model, "Pentium Pro");
290 "Pentium II/Pentium II Xeon/Celeron");
298 "Pentium III/Pentium III Xeon/Celeron");
302 strcat(cpu_model, "Unknown 80686");
307 strcat(cpu_model, "Pentium 4");
311 strcat(cpu_model, "unknown");
316 * If we didn't get a brand name from the extended
317 * CPUID, try to look it up in the brand table.
319 if (cpu_high > 0 && *cpu_brand == '\0') {
320 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
321 if (brand_index <= MAX_BRAND_INDEX &&
322 cpu_brandtable[brand_index] != NULL)
324 cpu_brandtable[brand_index]);
327 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
329 * Values taken from AMD Processor Recognition
330 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
331 * (also describes ``Features'' encodings.
333 strcpy(cpu_model, "AMD ");
334 switch (cpu_id & 0xFF0) {
336 strcat(cpu_model, "Standard Am486DX");
339 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
342 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
345 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
348 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
351 strcat(cpu_model, "Am5x86 Write-Through");
354 strcat(cpu_model, "Am5x86 Write-Back");
357 strcat(cpu_model, "K5 model 0");
361 strcat(cpu_model, "K5 model 1");
364 strcat(cpu_model, "K5 PR166 (model 2)");
367 strcat(cpu_model, "K5 PR200 (model 3)");
370 strcat(cpu_model, "K6");
373 strcat(cpu_model, "K6 266 (model 1)");
376 strcat(cpu_model, "K6-2");
379 strcat(cpu_model, "K6-III");
382 strcat(cpu_model, "Geode LX");
384 * Make sure the TSC runs through suspension,
385 * otherwise we can't use it as timecounter.
387 wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
390 strcat(cpu_model, "Unknown");
393 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
394 if ((cpu_id & 0xf00) == 0x500) {
395 if (((cpu_id & 0x0f0) > 0)
396 && ((cpu_id & 0x0f0) < 0x60)
397 && ((cpu_id & 0x00f) > 3))
398 enable_K5_wt_alloc();
399 else if (((cpu_id & 0x0f0) > 0x80)
400 || (((cpu_id & 0x0f0) == 0x80)
401 && (cpu_id & 0x00f) > 0x07))
402 enable_K6_2_wt_alloc();
403 else if ((cpu_id & 0x0f0) > 0x50)
404 enable_K6_wt_alloc();
407 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
408 strcpy(cpu_model, "Cyrix ");
409 switch (cpu_id & 0xff0) {
411 strcat(cpu_model, "MediaGX");
414 strcat(cpu_model, "6x86");
417 cpu_class = CPUCLASS_586;
418 strcat(cpu_model, "GXm");
421 strcat(cpu_model, "6x86MX");
425 * Even though CPU supports the cpuid
426 * instruction, it can be disabled.
427 * Therefore, this routine supports all Cyrix
430 switch (cyrix_did & 0xf0) {
432 switch (cyrix_did & 0x0f) {
434 strcat(cpu_model, "486SLC");
437 strcat(cpu_model, "486DLC");
440 strcat(cpu_model, "486SLC2");
443 strcat(cpu_model, "486DLC2");
446 strcat(cpu_model, "486SRx");
449 strcat(cpu_model, "486DRx");
452 strcat(cpu_model, "486SRx2");
455 strcat(cpu_model, "486DRx2");
458 strcat(cpu_model, "486SRu");
461 strcat(cpu_model, "486DRu");
464 strcat(cpu_model, "486SRu2");
467 strcat(cpu_model, "486DRu2");
470 strcat(cpu_model, "Unknown");
475 switch (cyrix_did & 0x0f) {
477 strcat(cpu_model, "486S");
480 strcat(cpu_model, "486S2");
483 strcat(cpu_model, "486Se");
486 strcat(cpu_model, "486S2e");
489 strcat(cpu_model, "486DX");
492 strcat(cpu_model, "486DX2");
495 strcat(cpu_model, "486DX4");
498 strcat(cpu_model, "Unknown");
503 if ((cyrix_did & 0x0f) < 8)
504 strcat(cpu_model, "6x86"); /* Where did you get it? */
506 strcat(cpu_model, "5x86");
509 strcat(cpu_model, "6x86");
512 if ((cyrix_did & 0xf000) == 0x3000) {
513 cpu_class = CPUCLASS_586;
514 strcat(cpu_model, "GXm");
516 strcat(cpu_model, "MediaGX");
519 strcat(cpu_model, "6x86MX");
522 switch (cyrix_did & 0x0f) {
524 strcat(cpu_model, "Overdrive CPU");
527 strcpy(cpu_model, "Texas Instruments 486SXL");
530 strcat(cpu_model, "486SLC/DLC");
533 strcat(cpu_model, "Unknown");
538 strcat(cpu_model, "Unknown");
543 } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
544 strcpy(cpu_model, "Rise ");
545 switch (cpu_id & 0xff0) {
547 strcat(cpu_model, "mP6");
550 strcat(cpu_model, "Unknown");
552 } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
553 switch (cpu_id & 0xff0) {
555 strcpy(cpu_model, "IDT WinChip C6");
559 strcpy(cpu_model, "IDT WinChip 2");
562 strcpy(cpu_model, "VIA C3 Samuel");
566 strcpy(cpu_model, "VIA C3 Ezra");
568 strcpy(cpu_model, "VIA C3 Samuel 2");
571 strcpy(cpu_model, "VIA C3 Ezra-T");
574 strcpy(cpu_model, "VIA C3 Nehemiah");
578 strcpy(cpu_model, "VIA C7 Esther");
581 strcpy(cpu_model, "VIA Nano");
584 strcpy(cpu_model, "VIA/IDT Unknown");
586 } else if (strcmp(cpu_vendor, "IBM") == 0) {
587 strcpy(cpu_model, "Blue Lightning CPU");
591 * Replace cpu_model with cpu_brand minus leading spaces if
595 while (*brand == ' ')
598 strcpy(cpu_model, brand);
602 kprintf("%s (", cpu_model);
610 #if defined(I486_CPU)
613 /* bzero = i486_bzero; */
616 #if defined(I586_CPU)
618 kprintf("%lld.%02lld-MHz ",
619 (tsc_frequency + 4999LL) / 1000000LL,
620 ((tsc_frequency + 4999LL) / 10000LL) % 100LL);
624 #if defined(I686_CPU)
626 kprintf("%lld.%02lld-MHz ",
627 (tsc_frequency + 4999LL) / 1000000LL,
628 ((tsc_frequency + 4999LL) / 10000LL) % 100LL);
633 kprintf("Unknown"); /* will panic below... */
635 kprintf("-class CPU)\n");
636 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
638 kprintf(" Origin = \"%s\"",cpu_vendor);
640 kprintf(" Id = 0x%x", cpu_id);
642 if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
643 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
644 strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
645 strcmp(cpu_vendor, "CentaurHauls") == 0 ||
646 ((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
647 ((cpu_id & 0xf00) > 0x500))) {
648 kprintf(" Stepping = %u", cpu_id & 0xf);
649 if (strcmp(cpu_vendor, "CyrixInstead") == 0)
650 kprintf(" DIR=0x%04x", cyrix_did);
653 * Here we should probably set up flags indicating
654 * whether or not various features are available.
655 * The interesting ones are probably VME, PSE, PAE,
656 * and PGE. The code already assumes without bothering
657 * to check that all CPUs >= Pentium have a TSC and
660 kprintf("\n Features=0x%b", cpu_feature,
662 "\001FPU" /* Integral FPU */
663 "\002VME" /* Extended VM86 mode support */
664 "\003DE" /* Debugging Extensions (CR4.DE) */
665 "\004PSE" /* 4MByte page tables */
666 "\005TSC" /* Timestamp counter */
667 "\006MSR" /* Machine specific registers */
668 "\007PAE" /* Physical address extension */
669 "\010MCE" /* Machine Check support */
670 "\011CX8" /* CMPEXCH8 instruction */
671 "\012APIC" /* SMP local APIC */
672 "\013oldMTRR" /* Previous implementation of MTRR */
673 "\014SEP" /* Fast System Call */
674 "\015MTRR" /* Memory Type Range Registers */
675 "\016PGE" /* PG_G (global bit) support */
676 "\017MCA" /* Machine Check Architecture */
677 "\020CMOV" /* CMOV instruction */
678 "\021PAT" /* Page attributes table */
679 "\022PSE36" /* 36 bit address space support */
680 "\023PN" /* Processor Serial number */
681 "\024CLFLUSH" /* Has the CLFLUSH instruction */
683 "\026DTS" /* Debug Trace Store */
684 "\027ACPI" /* ACPI support */
685 "\030MMX" /* MMX instructions */
686 "\031FXSR" /* FXSAVE/FXRSTOR */
687 "\032SSE" /* Streaming SIMD Extensions */
688 "\033SSE2" /* Streaming SIMD Extensions #2 */
689 "\034SS" /* Self snoop */
690 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
691 "\036TM" /* Thermal Monitor clock slowdown */
692 "\037IA64" /* CPU can execute IA64 instructions */
693 "\040PBE" /* Pending Break Enable */
696 if (cpu_feature2 != 0) {
697 kprintf("\n Features2=0x%b", cpu_feature2,
699 "\001SSE3" /* SSE3 */
701 "\003DTES64" /* 64-bit Debug Trace */
702 "\004MON" /* MONITOR/MWAIT Instructions */
703 "\005DS_CPL" /* CPL Qualified Debug Store */
704 "\006VMX" /* Virtual Machine Extensions */
705 "\007SMX" /* Safer Mode Extensions */
706 "\010EST" /* Enhanced SpeedStep */
707 "\011TM2" /* Thermal Monitor 2 */
708 "\012SSSE3" /* SSSE3 */
709 "\013CNXT-ID" /* L1 context ID available */
712 "\016CX16" /* CMPXCHG16B Instruction */
713 "\017xTPR" /* Send Task Priority Messages*/
714 "\020PDCM" /* Perf/Debug Capability MSR */
717 "\023DCA" /* Direct Cache Access */
720 "\026x2APIC" /* xAPIC Extensions */
721 "\027MOVBE" /* MOVBE instruction */
734 if (strcmp(cpu_vendor, "CentaurHauls") == 0)
735 print_via_padlock_info();
738 * If this CPU supports hyperthreading then mention
739 * the number of logical CPU's it contains.
741 if (cpu_feature & CPUID_HTT &&
742 (cpu_procinfo & CPUID_HTT_CORES) >> 16 > 1)
743 kprintf("\n Hyperthreading: %d logical CPUs",
744 (cpu_procinfo & CPUID_HTT_CORES) >> 16);
746 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
747 cpu_exthigh >= 0x80000001)
748 print_AMD_features();
749 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
750 kprintf(" DIR=0x%04x", cyrix_did);
751 kprintf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
752 kprintf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
753 #ifndef CYRIX_CACHE_REALLY_WORKS
754 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
755 kprintf("\n CPU cache: write-through mode");
758 /* Avoid ugly blank lines: only print newline when we have to. */
759 if (*cpu_vendor || cpu_id)
763 if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
764 strcmp(cpu_vendor, "TransmetaCPU") == 0) {
765 setup_tmx86_longrun();
768 for (i = 0; i < additional_cpu_info_count; ++i) {
769 kprintf(" %s\n", additional_cpu_info_ary[i]);
775 if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
777 else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
778 strcmp(cpu_vendor, "TransmetaCPU") == 0)
779 print_transmeta_info();
783 * XXX - Do PPro CPUID level=2 stuff here?
785 * No, but maybe in a print_Intel_info() function called from here.
791 panicifcpuunsupported(void)
794 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
795 #error This kernel is not configured for one of the supported CPUs
798 * Now that we have told the user what they have,
799 * let them know if that machine type isn't configured.
803 * A 286 and 386 should not make it this far, anyway.
807 #if !defined(I486_CPU)
810 #if !defined(I586_CPU)
813 #if !defined(I686_CPU)
816 panic("CPU class not configured");
823 static volatile u_int trap_by_rdmsr;
826 * Special exception 6 handler.
827 * The rdmsr instruction generates invalid opcodes fault on 486-class
828 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
829 * function identblue() when this handler is called. Stacked eip should
836 " .p2align 2,0x90 \n"
837 " .type " __XSTRING(CNAME(bluetrap6)) ",@function \n"
838 __XSTRING(CNAME(bluetrap6)) ": \n"
840 " movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n"
841 " addl $2, (%esp) # I know rdmsr is a 2-bytes instruction. \n"
846 * Special exception 13 handler.
847 * Accessing non-existent MSR generates general protection fault.
849 inthand_t bluetrap13;
853 " .p2align 2,0x90 \n"
854 " .type " __XSTRING(CNAME(bluetrap13)) ",@function \n"
855 __XSTRING(CNAME(bluetrap13)) ": \n"
857 " movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n"
858 " popl %eax # discard errorcode. \n"
859 " addl $2, (%esp) # I know rdmsr is a 2-bytes instruction. \n"
864 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
865 * support cpuid instruction. This function should be called after
866 * loading interrupt descriptor table register.
868 * I don't like this method that handles fault, but I couldn't get
869 * information for any other methods. Does blue giant know?
878 * Cyrix 486-class CPU does not support rdmsr instruction.
879 * The rdmsr instruction generates invalid opcode fault, and exception
880 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
881 * bluetrap6() set the magic number to trap_by_rdmsr.
883 setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
886 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
887 * In this case, rdmsr generates general protection fault, and
888 * exception will be trapped by bluetrap13().
890 setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
892 rdmsr(0x1002); /* Cyrix CPU generates fault. */
894 if (trap_by_rdmsr == 0xa8c1d)
895 return IDENTBLUE_CYRIX486;
896 else if (trap_by_rdmsr == 0xa89c4)
897 return IDENTBLUE_CYRIXM2;
898 return IDENTBLUE_IBMCPU;
903 * identifycyrix() set lower 16 bits of cyrix_did as follows:
905 * F E D C B A 9 8 7 6 5 4 3 2 1 0
906 * +-------+-------+---------------+
907 * | SID | RID | Device ID |
908 * | (DIR 1) | (DIR 0) |
909 * +-------+-------+---------------+
914 int ccr2_test = 0, dir_test = 0;
919 ccr2 = read_cyrix_reg(CCR2);
920 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
921 read_cyrix_reg(CCR2);
922 if (read_cyrix_reg(CCR2) != ccr2)
924 write_cyrix_reg(CCR2, ccr2);
926 ccr3 = read_cyrix_reg(CCR3);
927 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
928 read_cyrix_reg(CCR3);
929 if (read_cyrix_reg(CCR3) != ccr3)
930 dir_test = 1; /* CPU supports DIRs. */
931 write_cyrix_reg(CCR3, ccr3);
934 /* Device ID registers are available. */
935 cyrix_did = read_cyrix_reg(DIR1) << 8;
936 cyrix_did += read_cyrix_reg(DIR0);
937 } else if (ccr2_test)
938 cyrix_did = 0x0010; /* 486S A-step */
940 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
946 * Final stage of CPU identification. -- Should I check TI?
955 if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
956 if (cpu == CPU_486) {
958 * These conditions are equivalent to:
959 * - CPU does not support cpuid instruction.
960 * - Cyrix/IBM CPU is detected.
962 isblue = identblue();
963 if (isblue == IDENTBLUE_IBMCPU) {
964 strcpy(cpu_vendor, "IBM");
969 switch (cpu_id & 0xf00) {
972 * Cyrix's datasheet does not describe DIRs.
973 * Therefor, I assume it does not have them
974 * and use the result of the cpuid instruction.
975 * XXX they seem to have it for now at least. -Peter
983 * This routine contains a trick.
984 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
986 switch (cyrix_did & 0x00f0) {
995 if ((cyrix_did & 0x000f) < 8)
1008 /* M2 and later CPUs are treated as M2. */
1012 * enable cpuid instruction.
1014 ccr3 = read_cyrix_reg(CCR3);
1015 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1016 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1017 write_cyrix_reg(CCR3, ccr3);
1020 cpu_high = regs[0]; /* eax */
1022 cpu_id = regs[0]; /* eax */
1023 cpu_feature = regs[3]; /* edx */
1027 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1029 * There are BlueLightning CPUs that do not change
1030 * undefined flags by dividing 5 by 2. In this case,
1031 * the CPU identification routine in locore.s leaves
1032 * cpu_vendor null string and puts CPU_486 into the
1035 isblue = identblue();
1036 if (isblue == IDENTBLUE_IBMCPU) {
1037 strcpy(cpu_vendor, "IBM");
1045 print_AMD_assoc(int i)
1048 kprintf(", fully associative\n");
1050 kprintf(", %d-way associative\n", i);
1054 * #31116 Rev 3.06 section 3.9
1055 * CPUID Fn8000_0006 L2/L3 Cache and L2 TLB Identifiers
1058 print_AMD_L2L3_assoc(int i)
1060 static const char *assoc_str[] = {
1062 [0x1] = "direct mapped",
1063 [0x2] = "2-way associative",
1064 [0x4] = "4-way associative",
1065 [0x6] = "8-way associative",
1066 [0x8] = "16-way associative",
1067 [0xa] = "32-way associative",
1068 [0xb] = "48-way associative",
1069 [0xc] = "64-way associative",
1070 [0xd] = "96-way associative",
1071 [0xe] = "128-way associative",
1072 [0xf] = "fully associative"
1076 if (assoc_str[i] == NULL)
1077 kprintf(", unknown associative\n");
1079 kprintf(", %s\n", assoc_str[i]);
1083 print_AMD_info(void)
1087 if (cpu_exthigh >= 0x80000005) {
1090 do_cpuid(0x80000005, regs);
1091 kprintf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
1092 print_AMD_assoc(regs[1] >> 24);
1093 kprintf("Instruction TLB: %d entries", regs[1] & 0xff);
1094 print_AMD_assoc((regs[1] >> 8) & 0xff);
1095 kprintf("L1 data cache: %d kbytes", regs[2] >> 24);
1096 kprintf(", %d bytes/line", regs[2] & 0xff);
1097 kprintf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1098 print_AMD_assoc((regs[2] >> 16) & 0xff);
1099 kprintf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1100 kprintf(", %d bytes/line", regs[3] & 0xff);
1101 kprintf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1102 print_AMD_assoc((regs[3] >> 16) & 0xff);
1103 if (cpu_exthigh >= 0x80000006) { /* K6-III, or later */
1104 do_cpuid(0x80000006, regs);
1106 * Report right L2 cache size on Duron rev. A0.
1108 if ((cpu_id & 0xFF0) == 0x630)
1109 kprintf("L2 internal cache: 64 kbytes");
1111 kprintf("L2 internal cache: %d kbytes",
1114 kprintf(", %d bytes/line", regs[2] & 0xff);
1115 kprintf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1116 print_AMD_L2L3_assoc((regs[2] >> 12) & 0x0f);
1119 * #31116 Rev 3.06 section 2.16.2:
1120 * ... If EDX[31:16] is not zero then the processor
1121 * includes an L3. ...
1123 if ((regs[3] & 0xffff0000) != 0) {
1124 kprintf("L3 shared cache: %d kbytes",
1125 (regs[3] >> 18) * 512);
1126 kprintf(", %d bytes/line", regs[3] & 0xff);
1127 kprintf(", %d lines/tag", (regs[3] >> 8) & 0x0f);
1128 print_AMD_L2L3_assoc((regs[3] >> 12) & 0x0f);
1132 if (((cpu_id & 0xf00) == 0x500)
1133 && (((cpu_id & 0x0f0) > 0x80)
1134 || (((cpu_id & 0x0f0) == 0x80)
1135 && (cpu_id & 0x00f) > 0x07))) {
1136 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1137 amd_whcr = rdmsr(0xc0000082);
1138 if (!(amd_whcr & (0x3ff << 22))) {
1139 kprintf("Write Allocate Disable\n");
1141 kprintf("Write Allocate Enable Limit: %dM bytes\n",
1142 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1143 kprintf("Write Allocate 15-16M bytes: %s\n",
1144 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1146 } else if (((cpu_id & 0xf00) == 0x500)
1147 && ((cpu_id & 0x0f0) > 0x50)) {
1148 /* K6, K6-2(old core) */
1149 amd_whcr = rdmsr(0xc0000082);
1150 if (!(amd_whcr & (0x7f << 1))) {
1151 kprintf("Write Allocate Disable\n");
1153 kprintf("Write Allocate Enable Limit: %dM bytes\n",
1154 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1155 kprintf("Write Allocate 15-16M bytes: %s\n",
1156 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1157 kprintf("Hardware Write Allocate Control: %s\n",
1158 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1163 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
1165 print_AMD_features(void)
1170 * Values taken from AMD Processor Recognition
1171 * http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf
1173 do_cpuid(0x80000001, regs);
1174 kprintf("\n AMD Features=0x%b", regs[3] &~ cpu_feature,
1176 "\001FPU" /* Integral FPU */
1177 "\002VME" /* Extended VM86 mode support */
1178 "\003DE" /* Debug extensions */
1179 "\004PSE" /* 4MByte page tables */
1180 "\005TSC" /* Timestamp counter */
1181 "\006MSR" /* Machine specific registers */
1182 "\007PAE" /* Physical address extension */
1183 "\010MCE" /* Machine Check support */
1184 "\011CX8" /* CMPEXCH8 instruction */
1185 "\012APIC" /* SMP local APIC */
1187 "\014SYSCALL" /* SYSENTER/SYSEXIT instructions */
1188 "\015MTRR" /* Memory Type Range Registers */
1189 "\016PGE" /* PG_G (global bit) support */
1190 "\017MCA" /* Machine Check Architecture */
1191 "\020ICMOV" /* CMOV instruction */
1192 "\021PAT" /* Page attributes table */
1193 "\022PGE36" /* 36 bit address space support */
1194 "\023RSVD" /* Reserved, unknown */
1195 "\024MP" /* Multiprocessor Capable */
1196 "\025NX" /* No-execute page protection */
1198 "\027AMIE" /* AMD MMX Instruction Extensions */
1200 "\031FXSAVE" /* FXSAVE/FXRSTOR */
1203 "\034RDTSCP" /* RDTSCP instruction */
1205 "\036LM" /* Long mode */
1206 "\037DSP" /* AMD 3DNow! Instruction Extensions */
1213 * Transmeta Crusoe LongRun Support by Tamotsu Hattori.
1216 #define MSR_TMx86_LONGRUN 0x80868010
1217 #define MSR_TMx86_LONGRUN_FLAGS 0x80868011
1219 #define LONGRUN_MODE_MASK(x) ((x) & 0x000000007f)
1220 #define LONGRUN_MODE_RESERVED(x) ((x) & 0xffffff80)
1221 #define LONGRUN_MODE_WRITE(x, y) (LONGRUN_MODE_RESERVED(x) | LONGRUN_MODE_MASK(y))
1223 #define LONGRUN_MODE_MINFREQUENCY 0x00
1224 #define LONGRUN_MODE_ECONOMY 0x01
1225 #define LONGRUN_MODE_PERFORMANCE 0x02
1226 #define LONGRUN_MODE_MAXFREQUENCY 0x03
1227 #define LONGRUN_MODE_UNKNOWN 0x04
1228 #define LONGRUN_MODE_MAX 0x04
1235 u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
1236 /* MSR low, MSR high, flags bit0 */
1237 { 0, 0, 0}, /* LONGRUN_MODE_MINFREQUENCY */
1238 { 0, 100, 0}, /* LONGRUN_MODE_ECONOMY */
1239 { 0, 100, 1}, /* LONGRUN_MODE_PERFORMANCE */
1240 { 100, 100, 1}, /* LONGRUN_MODE_MAXFREQUENCY */
1244 tmx86_get_longrun_mode(void)
1246 union msrinfo msrinfo;
1247 u_int low, high, flags, mode;
1251 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1252 low = LONGRUN_MODE_MASK(msrinfo.regs[0]);
1253 high = LONGRUN_MODE_MASK(msrinfo.regs[1]);
1254 flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01;
1256 for (mode = 0; mode < LONGRUN_MODE_MAX; mode++) {
1257 if (low == longrun_modes[mode][0] &&
1258 high == longrun_modes[mode][1] &&
1259 flags == longrun_modes[mode][2]) {
1263 mode = LONGRUN_MODE_UNKNOWN;
1270 tmx86_get_longrun_status(u_int * frequency, u_int * voltage, u_int * percentage)
1276 do_cpuid(0x80860007, regs);
1277 *frequency = regs[0];
1279 *percentage = regs[2];
1286 tmx86_set_longrun_mode(u_int mode)
1288 union msrinfo msrinfo;
1290 if (mode >= LONGRUN_MODE_UNKNOWN) {
1296 /* Write LongRun mode values to Model Specific Register. */
1297 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1298 msrinfo.regs[0] = LONGRUN_MODE_WRITE(msrinfo.regs[0],
1299 longrun_modes[mode][0]);
1300 msrinfo.regs[1] = LONGRUN_MODE_WRITE(msrinfo.regs[1],
1301 longrun_modes[mode][1]);
1302 wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr);
1304 /* Write LongRun mode flags to Model Specific Register. */
1305 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS);
1306 msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2];
1307 wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
1313 static u_int crusoe_longrun;
1314 static u_int crusoe_frequency;
1315 static u_int crusoe_voltage;
1316 static u_int crusoe_percentage;
1317 static struct sysctl_ctx_list crusoe_sysctl_ctx;
1318 static struct sysctl_oid *crusoe_sysctl_tree;
1321 tmx86_longrun_sysctl(SYSCTL_HANDLER_ARGS)
1326 crusoe_longrun = tmx86_get_longrun_mode();
1327 mode = crusoe_longrun;
1328 error = sysctl_handle_int(oidp, &mode, 0, req);
1329 if (error || !req->newptr) {
1332 if (mode >= LONGRUN_MODE_UNKNOWN) {
1336 if (crusoe_longrun != mode) {
1337 crusoe_longrun = mode;
1338 tmx86_set_longrun_mode(crusoe_longrun);
1345 tmx86_status_sysctl(SYSCTL_HANDLER_ARGS)
1350 tmx86_get_longrun_status(&crusoe_frequency,
1351 &crusoe_voltage, &crusoe_percentage);
1352 val = *(u_int *)oidp->oid_arg1;
1353 error = sysctl_handle_int(oidp, &val, 0, req);
1358 setup_tmx86_longrun(void)
1360 static int done = 0;
1366 sysctl_ctx_init(&crusoe_sysctl_ctx);
1367 crusoe_sysctl_tree = SYSCTL_ADD_NODE(&crusoe_sysctl_ctx,
1368 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1369 "crusoe", CTLFLAG_RD, 0,
1370 "Transmeta Crusoe LongRun support");
1371 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1372 OID_AUTO, "longrun", CTLTYPE_INT | CTLFLAG_RW,
1373 &crusoe_longrun, 0, tmx86_longrun_sysctl, "I",
1374 "LongRun mode [0-3]");
1375 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1376 OID_AUTO, "frequency", CTLTYPE_INT | CTLFLAG_RD,
1377 &crusoe_frequency, 0, tmx86_status_sysctl, "I",
1378 "Current frequency (MHz)");
1379 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1380 OID_AUTO, "voltage", CTLTYPE_INT | CTLFLAG_RD,
1381 &crusoe_voltage, 0, tmx86_status_sysctl, "I",
1382 "Current voltage (mV)");
1383 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1384 OID_AUTO, "percentage", CTLTYPE_INT | CTLFLAG_RD,
1385 &crusoe_percentage, 0, tmx86_status_sysctl, "I",
1386 "Processing performance (%)");
1390 print_transmeta_info(void)
1392 u_int regs[4], nreg = 0;
1394 do_cpuid(0x80860000, regs);
1396 if (nreg >= 0x80860001) {
1397 do_cpuid(0x80860001, regs);
1398 kprintf(" Processor revision %u.%u.%u.%u\n",
1399 (regs[1] >> 24) & 0xff,
1400 (regs[1] >> 16) & 0xff,
1401 (regs[1] >> 8) & 0xff,
1404 if (nreg >= 0x80860002) {
1405 do_cpuid(0x80860002, regs);
1406 kprintf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
1407 (regs[1] >> 24) & 0xff,
1408 (regs[1] >> 16) & 0xff,
1409 (regs[1] >> 8) & 0xff,
1413 if (nreg >= 0x80860006) {
1415 do_cpuid(0x80860003, (u_int*) &info[0]);
1416 do_cpuid(0x80860004, (u_int*) &info[16]);
1417 do_cpuid(0x80860005, (u_int*) &info[32]);
1418 do_cpuid(0x80860006, (u_int*) &info[48]);
1420 kprintf(" %s\n", info);
1423 crusoe_longrun = tmx86_get_longrun_mode();
1424 tmx86_get_longrun_status(&crusoe_frequency,
1425 &crusoe_voltage, &crusoe_percentage);
1426 kprintf(" LongRun mode: %d <%dMHz %dmV %d%%>\n", crusoe_longrun,
1427 crusoe_frequency, crusoe_voltage, crusoe_percentage);
1431 print_via_padlock_info(void)
1435 /* Check for supported models. */
1436 switch (cpu_id & 0xff0) {
1438 if ((cpu_id & 0xf) < 3)
1448 do_cpuid(0xc0000000, regs);
1449 if (regs[0] >= 0xc0000001)
1450 do_cpuid(0xc0000001, regs);
1454 kprintf("\n VIA Padlock Features=0x%b", regs[3],
1458 "\011AES-CTR" /* ACE2 */
1459 "\013SHA1,SHA256" /* PHE */
1465 additional_cpu_info(const char *line)
1469 if ((i = additional_cpu_info_count) < MAX_ADDITIONAL_INFO) {
1470 additional_cpu_info_ary[i] = line;
1471 ++additional_cpu_info_count;