2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 #include "opt_ifpoll.h"
70 #include <sys/param.h>
72 #include <sys/endian.h>
73 #include <sys/interrupt.h>
74 #include <sys/kernel.h>
76 #include <sys/malloc.h>
80 #include <sys/serialize.h>
81 #include <sys/serialize2.h>
82 #include <sys/socket.h>
83 #include <sys/sockio.h>
84 #include <sys/sysctl.h>
85 #include <sys/systm.h>
88 #include <net/ethernet.h>
90 #include <net/if_arp.h>
91 #include <net/if_dl.h>
92 #include <net/if_media.h>
93 #include <net/ifq_var.h>
94 #include <net/toeplitz.h>
95 #include <net/toeplitz2.h>
96 #include <net/vlan/if_vlan_var.h>
97 #include <net/vlan/if_vlan_ether.h>
98 #include <net/if_poll.h>
100 #include <netinet/in_systm.h>
101 #include <netinet/in.h>
102 #include <netinet/ip.h>
103 #include <netinet/tcp.h>
104 #include <netinet/udp.h>
106 #include <bus/pci/pcivar.h>
107 #include <bus/pci/pcireg.h>
109 #include <dev/netif/ig_hal/e1000_api.h>
110 #include <dev/netif/ig_hal/e1000_82571.h>
111 #include <dev/netif/emx/if_emx.h>
116 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
118 if (sc->rss_debug >= lvl) \
119 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
121 #else /* !EMX_RSS_DEBUG */
122 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
123 #endif /* EMX_RSS_DEBUG */
125 #define EMX_NAME "Intel(R) PRO/1000 "
127 #define EMX_DEVICE(id) \
128 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
129 #define EMX_DEVICE_NULL { 0, 0, NULL }
131 static const struct emx_device {
136 EMX_DEVICE(82571EB_COPPER),
137 EMX_DEVICE(82571EB_FIBER),
138 EMX_DEVICE(82571EB_SERDES),
139 EMX_DEVICE(82571EB_SERDES_DUAL),
140 EMX_DEVICE(82571EB_SERDES_QUAD),
141 EMX_DEVICE(82571EB_QUAD_COPPER),
142 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
143 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
144 EMX_DEVICE(82571EB_QUAD_FIBER),
145 EMX_DEVICE(82571PT_QUAD_COPPER),
147 EMX_DEVICE(82572EI_COPPER),
148 EMX_DEVICE(82572EI_FIBER),
149 EMX_DEVICE(82572EI_SERDES),
153 EMX_DEVICE(82573E_IAMT),
156 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
157 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
158 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
159 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
164 EMX_DEVICE(PCH_LPT_I217_LM),
165 EMX_DEVICE(PCH_LPT_I217_V),
166 EMX_DEVICE(PCH_LPTLP_I218_LM),
167 EMX_DEVICE(PCH_LPTLP_I218_V),
168 EMX_DEVICE(PCH_I218_LM2),
169 EMX_DEVICE(PCH_I218_V2),
170 EMX_DEVICE(PCH_I218_LM3),
171 EMX_DEVICE(PCH_I218_V3),
173 /* required last entry */
177 static int emx_probe(device_t);
178 static int emx_attach(device_t);
179 static int emx_detach(device_t);
180 static int emx_shutdown(device_t);
181 static int emx_suspend(device_t);
182 static int emx_resume(device_t);
184 static void emx_init(void *);
185 static void emx_stop(struct emx_softc *);
186 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
187 static void emx_start(struct ifnet *, struct ifaltq_subque *);
189 static void emx_npoll(struct ifnet *, struct ifpoll_info *);
190 static void emx_npoll_status(struct ifnet *);
191 static void emx_npoll_tx(struct ifnet *, void *, int);
192 static void emx_npoll_rx(struct ifnet *, void *, int);
194 static void emx_watchdog(struct ifaltq_subque *);
195 static void emx_media_status(struct ifnet *, struct ifmediareq *);
196 static int emx_media_change(struct ifnet *);
197 static void emx_timer(void *);
198 static void emx_serialize(struct ifnet *, enum ifnet_serialize);
199 static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
200 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
202 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
206 static void emx_intr(void *);
207 static void emx_intr_mask(void *);
208 static void emx_intr_body(struct emx_softc *, boolean_t);
209 static void emx_rxeof(struct emx_rxdata *, int);
210 static void emx_txeof(struct emx_txdata *);
211 static void emx_tx_collect(struct emx_txdata *);
212 static void emx_tx_purge(struct emx_softc *);
213 static void emx_enable_intr(struct emx_softc *);
214 static void emx_disable_intr(struct emx_softc *);
216 static int emx_dma_alloc(struct emx_softc *);
217 static void emx_dma_free(struct emx_softc *);
218 static void emx_init_tx_ring(struct emx_txdata *);
219 static int emx_init_rx_ring(struct emx_rxdata *);
220 static void emx_free_tx_ring(struct emx_txdata *);
221 static void emx_free_rx_ring(struct emx_rxdata *);
222 static int emx_create_tx_ring(struct emx_txdata *);
223 static int emx_create_rx_ring(struct emx_rxdata *);
224 static void emx_destroy_tx_ring(struct emx_txdata *, int);
225 static void emx_destroy_rx_ring(struct emx_rxdata *, int);
226 static int emx_newbuf(struct emx_rxdata *, int, int);
227 static int emx_encap(struct emx_txdata *, struct mbuf **, int *, int *);
228 static int emx_txcsum(struct emx_txdata *, struct mbuf *,
229 uint32_t *, uint32_t *);
230 static int emx_tso_pullup(struct emx_txdata *, struct mbuf **);
231 static int emx_tso_setup(struct emx_txdata *, struct mbuf *,
232 uint32_t *, uint32_t *);
233 static int emx_get_txring_inuse(const struct emx_softc *, boolean_t);
235 static int emx_is_valid_eaddr(const uint8_t *);
236 static int emx_reset(struct emx_softc *);
237 static void emx_setup_ifp(struct emx_softc *);
238 static void emx_init_tx_unit(struct emx_softc *);
239 static void emx_init_rx_unit(struct emx_softc *);
240 static void emx_update_stats(struct emx_softc *);
241 static void emx_set_promisc(struct emx_softc *);
242 static void emx_disable_promisc(struct emx_softc *);
243 static void emx_set_multi(struct emx_softc *);
244 static void emx_update_link_status(struct emx_softc *);
245 static void emx_smartspeed(struct emx_softc *);
246 static void emx_set_itr(struct emx_softc *, uint32_t);
247 static void emx_disable_aspm(struct emx_softc *);
249 static void emx_print_debug_info(struct emx_softc *);
250 static void emx_print_nvm_info(struct emx_softc *);
251 static void emx_print_hw_stats(struct emx_softc *);
253 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
254 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
255 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
256 static int emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
257 static int emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
259 static int emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
260 static int emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
262 static void emx_add_sysctl(struct emx_softc *);
264 static void emx_serialize_skipmain(struct emx_softc *);
265 static void emx_deserialize_skipmain(struct emx_softc *);
267 /* Management and WOL Support */
268 static void emx_get_mgmt(struct emx_softc *);
269 static void emx_rel_mgmt(struct emx_softc *);
270 static void emx_get_hw_control(struct emx_softc *);
271 static void emx_rel_hw_control(struct emx_softc *);
272 static void emx_enable_wol(device_t);
274 static device_method_t emx_methods[] = {
275 /* Device interface */
276 DEVMETHOD(device_probe, emx_probe),
277 DEVMETHOD(device_attach, emx_attach),
278 DEVMETHOD(device_detach, emx_detach),
279 DEVMETHOD(device_shutdown, emx_shutdown),
280 DEVMETHOD(device_suspend, emx_suspend),
281 DEVMETHOD(device_resume, emx_resume),
285 static driver_t emx_driver = {
288 sizeof(struct emx_softc),
291 static devclass_t emx_devclass;
293 DECLARE_DUMMY_MODULE(if_emx);
294 MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
295 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
300 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
301 static int emx_rxd = EMX_DEFAULT_RXD;
302 static int emx_txd = EMX_DEFAULT_TXD;
303 static int emx_smart_pwr_down = 0;
304 static int emx_rxr = 0;
305 static int emx_txr = 1;
307 /* Controls whether promiscuous also shows bad packets */
308 static int emx_debug_sbp = 0;
310 static int emx_82573_workaround = 1;
311 static int emx_msi_enable = 1;
313 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
314 TUNABLE_INT("hw.emx.rxd", &emx_rxd);
315 TUNABLE_INT("hw.emx.rxr", &emx_rxr);
316 TUNABLE_INT("hw.emx.txd", &emx_txd);
317 TUNABLE_INT("hw.emx.txr", &emx_txr);
318 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
319 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
320 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
321 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
323 /* Global used in WOL setup with multiport cards */
324 static int emx_global_quad_port_a = 0;
326 /* Set this to one to display debug statistics */
327 static int emx_display_debug_stats = 0;
329 #if !defined(KTR_IF_EMX)
330 #define KTR_IF_EMX KTR_ALL
332 KTR_INFO_MASTER(if_emx);
333 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
334 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
335 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
336 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
337 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
338 #define logif(name) KTR_LOG(if_emx_ ## name)
341 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
343 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
344 /* DD bit must be cleared */
345 rxd->rxd_staterr = 0;
349 emx_rxcsum(uint32_t staterr, struct mbuf *mp)
351 /* Ignore Checksum bit is set */
352 if (staterr & E1000_RXD_STAT_IXSM)
355 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
357 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
359 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
360 E1000_RXD_STAT_TCPCS) {
361 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
363 CSUM_FRAG_NOT_CHECKED;
364 mp->m_pkthdr.csum_data = htons(0xffff);
368 static __inline struct pktinfo *
369 emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
370 uint32_t mrq, uint32_t hash, uint32_t staterr)
372 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
373 case EMX_RXDMRQ_IPV4_TCP:
374 pi->pi_netisr = NETISR_IP;
376 pi->pi_l3proto = IPPROTO_TCP;
379 case EMX_RXDMRQ_IPV6_TCP:
380 pi->pi_netisr = NETISR_IPV6;
382 pi->pi_l3proto = IPPROTO_TCP;
385 case EMX_RXDMRQ_IPV4:
386 if (staterr & E1000_RXD_STAT_IXSM)
390 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
391 E1000_RXD_STAT_TCPCS) {
392 pi->pi_netisr = NETISR_IP;
394 pi->pi_l3proto = IPPROTO_UDP;
402 m->m_flags |= M_HASH;
403 m->m_pkthdr.hash = toeplitz_hash(hash);
408 emx_probe(device_t dev)
410 const struct emx_device *d;
413 vid = pci_get_vendor(dev);
414 did = pci_get_device(dev);
416 for (d = emx_devices; d->desc != NULL; ++d) {
417 if (vid == d->vid && did == d->did) {
418 device_set_desc(dev, d->desc);
419 device_set_async_attach(dev, TRUE);
427 emx_attach(device_t dev)
429 struct emx_softc *sc = device_get_softc(dev);
430 int error = 0, i, throttle, msi_enable, tx_ring_max;
432 uint16_t eeprom_data, device_id, apme_mask;
433 driver_intr_t *intr_func;
435 int offset, offset_def;
441 for (i = 0; i < EMX_NRX_RING; ++i) {
442 sc->rx_data[i].sc = sc;
443 sc->rx_data[i].idx = i;
449 for (i = 0; i < EMX_NTX_RING; ++i) {
450 sc->tx_data[i].sc = sc;
451 sc->tx_data[i].idx = i;
455 * Initialize serializers
457 lwkt_serialize_init(&sc->main_serialize);
458 for (i = 0; i < EMX_NTX_RING; ++i)
459 lwkt_serialize_init(&sc->tx_data[i].tx_serialize);
460 for (i = 0; i < EMX_NRX_RING; ++i)
461 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
464 * Initialize serializer array
468 KKASSERT(i < EMX_NSERIALIZE);
469 sc->serializes[i++] = &sc->main_serialize;
471 KKASSERT(i < EMX_NSERIALIZE);
472 sc->serializes[i++] = &sc->tx_data[0].tx_serialize;
473 KKASSERT(i < EMX_NSERIALIZE);
474 sc->serializes[i++] = &sc->tx_data[1].tx_serialize;
476 KKASSERT(i < EMX_NSERIALIZE);
477 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
478 KKASSERT(i < EMX_NSERIALIZE);
479 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
481 KKASSERT(i == EMX_NSERIALIZE);
483 ifmedia_init(&sc->media, IFM_IMASK, emx_media_change, emx_media_status);
484 callout_init_mp(&sc->timer);
486 sc->dev = sc->osdep.dev = dev;
489 * Determine hardware and mac type
491 sc->hw.vendor_id = pci_get_vendor(dev);
492 sc->hw.device_id = pci_get_device(dev);
493 sc->hw.revision_id = pci_get_revid(dev);
494 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
495 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
497 if (e1000_set_mac_type(&sc->hw))
500 /* Enable bus mastering */
501 pci_enable_busmaster(dev);
506 sc->memory_rid = EMX_BAR_MEM;
507 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
508 &sc->memory_rid, RF_ACTIVE);
509 if (sc->memory == NULL) {
510 device_printf(dev, "Unable to allocate bus resource: memory\n");
514 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
515 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
517 /* XXX This is quite goofy, it is not actually used */
518 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
521 * Don't enable MSI-X on 82574, see:
522 * 82574 specification update errata #15
524 * Don't enable MSI on 82571/82572, see:
525 * 82571/82572 specification update errata #63
527 msi_enable = emx_msi_enable;
529 (sc->hw.mac.type == e1000_82571 ||
530 sc->hw.mac.type == e1000_82572))
536 sc->intr_type = pci_alloc_1intr(dev, msi_enable,
537 &sc->intr_rid, &intr_flags);
539 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
542 unshared = device_getenv_int(dev, "irq.unshared", 0);
544 sc->flags |= EMX_FLAG_SHARED_INTR;
546 device_printf(dev, "IRQ shared\n");
548 intr_flags &= ~RF_SHAREABLE;
550 device_printf(dev, "IRQ unshared\n");
554 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
556 if (sc->intr_res == NULL) {
557 device_printf(dev, "Unable to allocate bus resource: "
563 /* Save PCI command register for Shared Code */
564 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
565 sc->hw.back = &sc->osdep;
568 * For I217/I218, we need to map the flash memory and this
569 * must happen after the MAC is identified.
571 if (sc->hw.mac.type == e1000_pch_lpt) {
572 sc->flash_rid = EMX_BAR_FLASH;
574 sc->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
575 &sc->flash_rid, RF_ACTIVE);
576 if (sc->flash == NULL) {
577 device_printf(dev, "Mapping of Flash failed\n");
581 sc->osdep.flash_bus_space_tag = rman_get_bustag(sc->flash);
582 sc->osdep.flash_bus_space_handle =
583 rman_get_bushandle(sc->flash);
586 * This is used in the shared code
587 * XXX this goof is actually not used.
589 sc->hw.flash_address = (uint8_t *)sc->flash;
592 /* Do Shared Code initialization */
593 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
594 device_printf(dev, "Setup of Shared code failed\n");
598 e1000_get_bus_info(&sc->hw);
600 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
601 sc->hw.phy.autoneg_wait_to_complete = FALSE;
602 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
605 * Interrupt throttle rate
607 throttle = device_getenv_int(dev, "int_throttle_ceil",
608 emx_int_throttle_ceil);
610 sc->int_throttle_ceil = 0;
613 throttle = EMX_DEFAULT_ITR;
615 /* Recalculate the tunable value to get the exact frequency. */
616 throttle = 1000000000 / 256 / throttle;
618 /* Upper 16bits of ITR is reserved and should be zero */
619 if (throttle & 0xffff0000)
620 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
622 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
625 e1000_init_script_state_82541(&sc->hw, TRUE);
626 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
629 if (sc->hw.phy.media_type == e1000_media_type_copper) {
630 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
631 sc->hw.phy.disable_polarity_correction = FALSE;
632 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
635 /* Set the frame limits assuming standard ethernet sized frames. */
636 sc->hw.mac.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
638 /* This controls when hardware reports transmit completion status. */
639 sc->hw.mac.report_tx_early = 1;
641 /* Calculate # of RX rings */
642 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr);
643 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING);
646 * Calculate # of TX rings
649 * I217/I218 claims to have 2 TX queues
652 * Don't enable multiple TX queues on 82574; it always gives
653 * watchdog timeout on TX queue0, when multiple TCP streams are
654 * received. It was originally suspected that the hardware TX
655 * checksum offloading caused this watchdog timeout, since only
656 * TCP ACKs are sent during TCP receiving tests. However, even
657 * if the hardware TX checksum offloading is disable, TX queue0
658 * still will give watchdog.
661 if (sc->hw.mac.type == e1000_82571 ||
662 sc->hw.mac.type == e1000_82572 ||
663 sc->hw.mac.type == e1000_80003es2lan ||
664 sc->hw.mac.type == e1000_pch_lpt ||
665 sc->hw.mac.type == e1000_82574)
666 tx_ring_max = EMX_NTX_RING;
667 sc->tx_ring_cnt = device_getenv_int(dev, "txr", emx_txr);
668 sc->tx_ring_cnt = if_ring_count2(sc->tx_ring_cnt, tx_ring_max);
670 /* Allocate RX/TX rings' busdma(9) stuffs */
671 error = emx_dma_alloc(sc);
675 /* Allocate multicast array memory. */
676 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
679 /* Indicate SOL/IDER usage */
680 if (e1000_check_reset_block(&sc->hw)) {
682 "PHY reset is blocked due to SOL/IDER session.\n");
685 /* Disable EEE on I217/I218 */
686 sc->hw.dev_spec.ich8lan.eee_disable = 1;
689 * Start from a known state, this is important in reading the
690 * nvm and mac from that.
692 e1000_reset_hw(&sc->hw);
694 /* Make sure we have a good EEPROM before we read from it */
695 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
697 * Some PCI-E parts fail the first check due to
698 * the link being in sleep state, call it again,
699 * if it fails a second time its a real issue.
701 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
703 "The EEPROM Checksum Is Not Valid\n");
709 /* Copy the permanent MAC address out of the EEPROM */
710 if (e1000_read_mac_addr(&sc->hw) < 0) {
711 device_printf(dev, "EEPROM read error while reading MAC"
716 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
717 device_printf(dev, "Invalid MAC address\n");
722 /* Disable ULP support */
723 e1000_disable_ulp_lpt_lp(&sc->hw, TRUE);
725 /* Determine if we have to control management hardware */
726 if (e1000_enable_mng_pass_thru(&sc->hw))
727 sc->flags |= EMX_FLAG_HAS_MGMT;
732 apme_mask = EMX_EEPROM_APME;
734 switch (sc->hw.mac.type) {
736 sc->flags |= EMX_FLAG_HAS_AMT;
741 case e1000_80003es2lan:
742 if (sc->hw.bus.func == 1) {
743 e1000_read_nvm(&sc->hw,
744 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
746 e1000_read_nvm(&sc->hw,
747 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
752 e1000_read_nvm(&sc->hw,
753 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
756 if (eeprom_data & apme_mask)
757 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
760 * We have the eeprom settings, now apply the special cases
761 * where the eeprom may be wrong or the board won't support
762 * wake on lan on a particular port
764 device_id = pci_get_device(dev);
766 case E1000_DEV_ID_82571EB_FIBER:
768 * Wake events only supported on port A for dual fiber
769 * regardless of eeprom setting
771 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
776 case E1000_DEV_ID_82571EB_QUAD_COPPER:
777 case E1000_DEV_ID_82571EB_QUAD_FIBER:
778 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
779 /* if quad port sc, disable WoL on all but port A */
780 if (emx_global_quad_port_a != 0)
782 /* Reset for multiple quad port adapters */
783 if (++emx_global_quad_port_a == 4)
784 emx_global_quad_port_a = 0;
788 /* XXX disable wol */
793 * NPOLLING RX CPU offset
795 if (sc->rx_ring_cnt == ncpus2) {
798 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
799 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
800 if (offset >= ncpus2 ||
801 offset % sc->rx_ring_cnt != 0) {
802 device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
807 sc->rx_npoll_off = offset;
810 * NPOLLING TX CPU offset
812 if (sc->tx_ring_cnt == ncpus2) {
815 offset_def = (sc->tx_ring_cnt * device_get_unit(dev)) % ncpus2;
816 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
817 if (offset >= ncpus2 ||
818 offset % sc->tx_ring_cnt != 0) {
819 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
824 sc->tx_npoll_off = offset;
826 sc->tx_ring_inuse = emx_get_txring_inuse(sc, FALSE);
828 /* Setup OS specific network interface */
831 /* Add sysctl tree, must after em_setup_ifp() */
834 /* Reset the hardware */
835 error = emx_reset(sc);
838 * Some 82573 parts fail the first reset, call it again,
839 * if it fails a second time its a real issue.
841 error = emx_reset(sc);
843 device_printf(dev, "Unable to reset the hardware\n");
844 ether_ifdetach(&sc->arpcom.ac_if);
849 /* Initialize statistics */
850 emx_update_stats(sc);
852 sc->hw.mac.get_link_status = 1;
853 emx_update_link_status(sc);
855 /* Non-AMT based hardware can now take control from firmware */
856 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
858 emx_get_hw_control(sc);
861 * Missing Interrupt Following ICR read:
863 * 82571/82572 specification update errata #76
864 * 82573 specification update errata #31
865 * 82574 specification update errata #12
867 intr_func = emx_intr;
868 if ((sc->flags & EMX_FLAG_SHARED_INTR) &&
869 (sc->hw.mac.type == e1000_82571 ||
870 sc->hw.mac.type == e1000_82572 ||
871 sc->hw.mac.type == e1000_82573 ||
872 sc->hw.mac.type == e1000_82574))
873 intr_func = emx_intr_mask;
875 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc,
876 &sc->intr_tag, &sc->main_serialize);
878 device_printf(dev, "Failed to register interrupt handler");
879 ether_ifdetach(&sc->arpcom.ac_if);
889 emx_detach(device_t dev)
891 struct emx_softc *sc = device_get_softc(dev);
893 if (device_is_attached(dev)) {
894 struct ifnet *ifp = &sc->arpcom.ac_if;
896 ifnet_serialize_all(ifp);
900 e1000_phy_hw_reset(&sc->hw);
903 emx_rel_hw_control(sc);
906 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
907 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
911 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
913 ifnet_deserialize_all(ifp);
916 } else if (sc->memory != NULL) {
917 emx_rel_hw_control(sc);
920 ifmedia_removeall(&sc->media);
921 bus_generic_detach(dev);
923 if (sc->intr_res != NULL) {
924 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
928 if (sc->intr_type == PCI_INTR_TYPE_MSI)
929 pci_release_msi(dev);
931 if (sc->memory != NULL) {
932 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
936 if (sc->flash != NULL) {
937 bus_release_resource(dev, SYS_RES_MEMORY, sc->flash_rid,
944 kfree(sc->mta, M_DEVBUF);
950 emx_shutdown(device_t dev)
952 return emx_suspend(dev);
956 emx_suspend(device_t dev)
958 struct emx_softc *sc = device_get_softc(dev);
959 struct ifnet *ifp = &sc->arpcom.ac_if;
961 ifnet_serialize_all(ifp);
966 emx_rel_hw_control(sc);
969 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
970 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
974 ifnet_deserialize_all(ifp);
976 return bus_generic_suspend(dev);
980 emx_resume(device_t dev)
982 struct emx_softc *sc = device_get_softc(dev);
983 struct ifnet *ifp = &sc->arpcom.ac_if;
986 ifnet_serialize_all(ifp);
990 for (i = 0; i < sc->tx_ring_inuse; ++i)
991 ifsq_devstart_sched(sc->tx_data[i].ifsq);
993 ifnet_deserialize_all(ifp);
995 return bus_generic_resume(dev);
999 emx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1001 struct emx_softc *sc = ifp->if_softc;
1002 struct emx_txdata *tdata = ifsq_get_priv(ifsq);
1003 struct mbuf *m_head;
1004 int idx = -1, nsegs = 0;
1006 KKASSERT(tdata->ifsq == ifsq);
1007 ASSERT_SERIALIZED(&tdata->tx_serialize);
1009 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
1012 if (!sc->link_active || (tdata->tx_flags & EMX_TXFLAG_ENABLED) == 0) {
1017 while (!ifsq_is_empty(ifsq)) {
1018 /* Now do we at least have a minimal? */
1019 if (EMX_IS_OACTIVE(tdata)) {
1020 emx_tx_collect(tdata);
1021 if (EMX_IS_OACTIVE(tdata)) {
1022 ifsq_set_oactive(ifsq);
1028 m_head = ifsq_dequeue(ifsq);
1032 if (emx_encap(tdata, &m_head, &nsegs, &idx)) {
1033 IFNET_STAT_INC(ifp, oerrors, 1);
1034 emx_tx_collect(tdata);
1039 * TX interrupt are aggressively aggregated, so increasing
1040 * opackets at TX interrupt time will make the opackets
1041 * statistics vastly inaccurate; we do the opackets increment
1044 IFNET_STAT_INC(ifp, opackets, 1);
1046 if (nsegs >= tdata->tx_wreg_nsegs) {
1047 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx);
1052 /* Send a copy of the frame to the BPF listener */
1053 ETHER_BPF_MTAP(ifp, m_head);
1055 /* Set timeout in case hardware has problems transmitting. */
1056 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT;
1059 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx);
1063 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1065 struct emx_softc *sc = ifp->if_softc;
1066 struct ifreq *ifr = (struct ifreq *)data;
1067 uint16_t eeprom_data = 0;
1068 int max_frame_size, mask, reinit;
1071 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1075 switch (sc->hw.mac.type) {
1078 * 82573 only supports jumbo frames
1079 * if ASPM is disabled.
1081 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
1083 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
1084 max_frame_size = ETHER_MAX_LEN;
1089 /* Limit Jumbo Frame size */
1094 case e1000_80003es2lan:
1095 max_frame_size = 9234;
1099 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1102 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1108 ifp->if_mtu = ifr->ifr_mtu;
1109 sc->hw.mac.max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
1112 if (ifp->if_flags & IFF_RUNNING)
1117 if (ifp->if_flags & IFF_UP) {
1118 if ((ifp->if_flags & IFF_RUNNING)) {
1119 if ((ifp->if_flags ^ sc->if_flags) &
1120 (IFF_PROMISC | IFF_ALLMULTI)) {
1121 emx_disable_promisc(sc);
1122 emx_set_promisc(sc);
1127 } else if (ifp->if_flags & IFF_RUNNING) {
1130 sc->if_flags = ifp->if_flags;
1135 if (ifp->if_flags & IFF_RUNNING) {
1136 emx_disable_intr(sc);
1138 #ifdef IFPOLL_ENABLE
1139 if (!(ifp->if_flags & IFF_NPOLLING))
1141 emx_enable_intr(sc);
1146 /* Check SOL/IDER usage */
1147 if (e1000_check_reset_block(&sc->hw)) {
1148 device_printf(sc->dev, "Media change is"
1149 " blocked due to SOL/IDER session.\n");
1155 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
1160 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1161 if (mask & IFCAP_RXCSUM) {
1162 ifp->if_capenable ^= IFCAP_RXCSUM;
1165 if (mask & IFCAP_VLAN_HWTAGGING) {
1166 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1169 if (mask & IFCAP_TXCSUM) {
1170 ifp->if_capenable ^= IFCAP_TXCSUM;
1171 if (ifp->if_capenable & IFCAP_TXCSUM)
1172 ifp->if_hwassist |= EMX_CSUM_FEATURES;
1174 ifp->if_hwassist &= ~EMX_CSUM_FEATURES;
1176 if (mask & IFCAP_TSO) {
1177 ifp->if_capenable ^= IFCAP_TSO;
1178 if (ifp->if_capenable & IFCAP_TSO)
1179 ifp->if_hwassist |= CSUM_TSO;
1181 ifp->if_hwassist &= ~CSUM_TSO;
1183 if (mask & IFCAP_RSS)
1184 ifp->if_capenable ^= IFCAP_RSS;
1185 if (reinit && (ifp->if_flags & IFF_RUNNING))
1190 error = ether_ioctl(ifp, command, data);
1197 emx_watchdog(struct ifaltq_subque *ifsq)
1199 struct emx_txdata *tdata = ifsq_get_priv(ifsq);
1200 struct ifnet *ifp = ifsq_get_ifp(ifsq);
1201 struct emx_softc *sc = ifp->if_softc;
1204 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1207 * The timer is set to 5 every time start queues a packet.
1208 * Then txeof keeps resetting it as long as it cleans at
1209 * least one descriptor.
1210 * Finally, anytime all descriptors are clean the timer is
1214 if (E1000_READ_REG(&sc->hw, E1000_TDT(tdata->idx)) ==
1215 E1000_READ_REG(&sc->hw, E1000_TDH(tdata->idx))) {
1217 * If we reach here, all TX jobs are completed and
1218 * the TX engine should have been idled for some time.
1219 * We don't need to call ifsq_devstart_sched() here.
1221 ifsq_clr_oactive(ifsq);
1222 tdata->tx_watchdog.wd_timer = 0;
1227 * If we are in this routine because of pause frames, then
1228 * don't reset the hardware.
1230 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1231 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT;
1235 if_printf(ifp, "TX %d watchdog timeout -- resetting\n", tdata->idx);
1237 IFNET_STAT_INC(ifp, oerrors, 1);
1240 for (i = 0; i < sc->tx_ring_inuse; ++i)
1241 ifsq_devstart_sched(sc->tx_data[i].ifsq);
1247 struct emx_softc *sc = xsc;
1248 struct ifnet *ifp = &sc->arpcom.ac_if;
1249 device_t dev = sc->dev;
1253 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1257 /* Get the latest mac address, User can use a LAA */
1258 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1260 /* Put the address into the Receive Address Array */
1261 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1264 * With the 82571 sc, RAR[0] may be overwritten
1265 * when the other port is reset, we make a duplicate
1266 * in RAR[14] for that eventuality, this assures
1267 * the interface continues to function.
1269 if (sc->hw.mac.type == e1000_82571) {
1270 e1000_set_laa_state_82571(&sc->hw, TRUE);
1271 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1272 E1000_RAR_ENTRIES - 1);
1275 /* Initialize the hardware */
1276 if (emx_reset(sc)) {
1277 device_printf(dev, "Unable to reset the hardware\n");
1278 /* XXX emx_stop()? */
1281 emx_update_link_status(sc);
1283 /* Setup VLAN support, basic and offload if available */
1284 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1286 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1289 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1290 ctrl |= E1000_CTRL_VME;
1291 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1294 /* Configure for OS presence */
1298 #ifdef IFPOLL_ENABLE
1299 if (ifp->if_flags & IFF_NPOLLING)
1302 sc->tx_ring_inuse = emx_get_txring_inuse(sc, polling);
1303 ifq_set_subq_mask(&ifp->if_snd, sc->tx_ring_inuse - 1);
1305 /* Prepare transmit descriptors and buffers */
1306 for (i = 0; i < sc->tx_ring_inuse; ++i)
1307 emx_init_tx_ring(&sc->tx_data[i]);
1308 emx_init_tx_unit(sc);
1310 /* Setup Multicast table */
1313 /* Prepare receive descriptors and buffers */
1314 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1315 if (emx_init_rx_ring(&sc->rx_data[i])) {
1317 "Could not setup receive structures\n");
1322 emx_init_rx_unit(sc);
1324 /* Don't lose promiscuous settings */
1325 emx_set_promisc(sc);
1327 ifp->if_flags |= IFF_RUNNING;
1328 for (i = 0; i < sc->tx_ring_inuse; ++i) {
1329 ifsq_clr_oactive(sc->tx_data[i].ifsq);
1330 ifsq_watchdog_start(&sc->tx_data[i].tx_watchdog);
1333 callout_reset(&sc->timer, hz, emx_timer, sc);
1334 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1336 /* MSI/X configuration for 82574 */
1337 if (sc->hw.mac.type == e1000_82574) {
1340 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1341 tmp |= E1000_CTRL_EXT_PBA_CLR;
1342 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1345 * Set the IVAR - interrupt vector routing.
1346 * Each nibble represents a vector, high bit
1347 * is enable, other 3 bits are the MSIX table
1348 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1349 * Link (other) to 2, hence the magic number.
1351 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1355 * Only enable interrupts if we are not polling, make sure
1356 * they are off otherwise.
1359 emx_disable_intr(sc);
1361 emx_enable_intr(sc);
1363 /* AMT based hardware can now take control from firmware */
1364 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
1365 (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT))
1366 emx_get_hw_control(sc);
1372 emx_intr_body(xsc, TRUE);
1376 emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted)
1378 struct ifnet *ifp = &sc->arpcom.ac_if;
1382 ASSERT_SERIALIZED(&sc->main_serialize);
1384 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1386 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1392 * XXX: some laptops trigger several spurious interrupts
1393 * on emx(4) when in the resume cycle. The ICR register
1394 * reports all-ones value in this case. Processing such
1395 * interrupts would lead to a freeze. I don't know why.
1397 if (reg_icr == 0xffffffff) {
1402 if (ifp->if_flags & IFF_RUNNING) {
1404 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1407 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1408 lwkt_serialize_enter(
1409 &sc->rx_data[i].rx_serialize);
1410 emx_rxeof(&sc->rx_data[i], -1);
1411 lwkt_serialize_exit(
1412 &sc->rx_data[i].rx_serialize);
1415 if (reg_icr & E1000_ICR_TXDW) {
1416 struct emx_txdata *tdata = &sc->tx_data[0];
1418 lwkt_serialize_enter(&tdata->tx_serialize);
1420 if (!ifsq_is_empty(tdata->ifsq))
1421 ifsq_devstart(tdata->ifsq);
1422 lwkt_serialize_exit(&tdata->tx_serialize);
1426 /* Link status change */
1427 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1428 emx_serialize_skipmain(sc);
1430 callout_stop(&sc->timer);
1431 sc->hw.mac.get_link_status = 1;
1432 emx_update_link_status(sc);
1434 /* Deal with TX cruft when link lost */
1437 callout_reset(&sc->timer, hz, emx_timer, sc);
1439 emx_deserialize_skipmain(sc);
1442 if (reg_icr & E1000_ICR_RXO)
1449 emx_intr_mask(void *xsc)
1451 struct emx_softc *sc = xsc;
1453 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
1456 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1457 * so don't check it.
1459 emx_intr_body(sc, FALSE);
1460 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
1464 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1466 struct emx_softc *sc = ifp->if_softc;
1468 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1470 emx_update_link_status(sc);
1472 ifmr->ifm_status = IFM_AVALID;
1473 ifmr->ifm_active = IFM_ETHER;
1475 if (!sc->link_active)
1478 ifmr->ifm_status |= IFM_ACTIVE;
1480 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1481 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1482 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1484 switch (sc->link_speed) {
1486 ifmr->ifm_active |= IFM_10_T;
1489 ifmr->ifm_active |= IFM_100_TX;
1493 ifmr->ifm_active |= IFM_1000_T;
1496 if (sc->link_duplex == FULL_DUPLEX)
1497 ifmr->ifm_active |= IFM_FDX;
1499 ifmr->ifm_active |= IFM_HDX;
1504 emx_media_change(struct ifnet *ifp)
1506 struct emx_softc *sc = ifp->if_softc;
1507 struct ifmedia *ifm = &sc->media;
1509 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1511 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1514 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1516 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1517 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1523 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1524 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1528 sc->hw.mac.autoneg = FALSE;
1529 sc->hw.phy.autoneg_advertised = 0;
1530 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1531 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1533 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1537 sc->hw.mac.autoneg = FALSE;
1538 sc->hw.phy.autoneg_advertised = 0;
1539 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1540 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1542 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1546 if_printf(ifp, "Unsupported media type\n");
1556 emx_encap(struct emx_txdata *tdata, struct mbuf **m_headp,
1557 int *segs_used, int *idx)
1559 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1561 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
1562 struct e1000_tx_desc *ctxd = NULL;
1563 struct mbuf *m_head = *m_headp;
1564 uint32_t txd_upper, txd_lower, cmd = 0;
1565 int maxsegs, nsegs, i, j, first, last = 0, error;
1567 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1568 error = emx_tso_pullup(tdata, m_headp);
1574 txd_upper = txd_lower = 0;
1577 * Capture the first descriptor index, this descriptor
1578 * will have the index of the EOP which is the only one
1579 * that now gets a DONE bit writeback.
1581 first = tdata->next_avail_tx_desc;
1582 tx_buffer = &tdata->tx_buf[first];
1583 tx_buffer_mapped = tx_buffer;
1584 map = tx_buffer->map;
1586 maxsegs = tdata->num_tx_desc_avail - EMX_TX_RESERVED;
1587 KASSERT(maxsegs >= tdata->spare_tx_desc, ("not enough spare TX desc"));
1588 if (maxsegs > EMX_MAX_SCATTER)
1589 maxsegs = EMX_MAX_SCATTER;
1591 error = bus_dmamap_load_mbuf_defrag(tdata->txtag, map, m_headp,
1592 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1598 bus_dmamap_sync(tdata->txtag, map, BUS_DMASYNC_PREWRITE);
1601 tdata->tx_nsegs += nsegs;
1602 *segs_used += nsegs;
1604 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1605 /* TSO will consume one TX desc */
1606 i = emx_tso_setup(tdata, m_head, &txd_upper, &txd_lower);
1607 tdata->tx_nsegs += i;
1609 } else if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1610 /* TX csum offloading will consume one TX desc */
1611 i = emx_txcsum(tdata, m_head, &txd_upper, &txd_lower);
1612 tdata->tx_nsegs += i;
1616 /* Handle VLAN tag */
1617 if (m_head->m_flags & M_VLANTAG) {
1618 /* Set the vlan id. */
1619 txd_upper |= (htole16(m_head->m_pkthdr.ether_vlantag) << 16);
1620 /* Tell hardware to add tag */
1621 txd_lower |= htole32(E1000_TXD_CMD_VLE);
1624 i = tdata->next_avail_tx_desc;
1626 /* Set up our transmit descriptors */
1627 for (j = 0; j < nsegs; j++) {
1628 tx_buffer = &tdata->tx_buf[i];
1629 ctxd = &tdata->tx_desc_base[i];
1631 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1632 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1633 txd_lower | segs[j].ds_len);
1634 ctxd->upper.data = htole32(txd_upper);
1637 if (++i == tdata->num_tx_desc)
1641 tdata->next_avail_tx_desc = i;
1643 KKASSERT(tdata->num_tx_desc_avail > nsegs);
1644 tdata->num_tx_desc_avail -= nsegs;
1646 tx_buffer->m_head = m_head;
1647 tx_buffer_mapped->map = tx_buffer->map;
1648 tx_buffer->map = map;
1650 if (tdata->tx_nsegs >= tdata->tx_intr_nsegs) {
1651 tdata->tx_nsegs = 0;
1654 * Report Status (RS) is turned on
1655 * every tx_intr_nsegs descriptors.
1657 cmd = E1000_TXD_CMD_RS;
1660 * Keep track of the descriptor, which will
1661 * be written back by hardware.
1663 tdata->tx_dd[tdata->tx_dd_tail] = last;
1664 EMX_INC_TXDD_IDX(tdata->tx_dd_tail);
1665 KKASSERT(tdata->tx_dd_tail != tdata->tx_dd_head);
1669 * Last Descriptor of Packet needs End Of Packet (EOP)
1671 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1674 * Defer TDT updating, until enough descriptors are setup
1678 #ifdef EMX_TSS_DEBUG
1686 emx_set_promisc(struct emx_softc *sc)
1688 struct ifnet *ifp = &sc->arpcom.ac_if;
1691 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1693 if (ifp->if_flags & IFF_PROMISC) {
1694 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1695 /* Turn this on if you want to see bad packets */
1697 reg_rctl |= E1000_RCTL_SBP;
1698 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1699 } else if (ifp->if_flags & IFF_ALLMULTI) {
1700 reg_rctl |= E1000_RCTL_MPE;
1701 reg_rctl &= ~E1000_RCTL_UPE;
1702 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1707 emx_disable_promisc(struct emx_softc *sc)
1711 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1713 reg_rctl &= ~E1000_RCTL_UPE;
1714 reg_rctl &= ~E1000_RCTL_MPE;
1715 reg_rctl &= ~E1000_RCTL_SBP;
1716 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1720 emx_set_multi(struct emx_softc *sc)
1722 struct ifnet *ifp = &sc->arpcom.ac_if;
1723 struct ifmultiaddr *ifma;
1724 uint32_t reg_rctl = 0;
1729 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1731 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1732 if (ifma->ifma_addr->sa_family != AF_LINK)
1735 if (mcnt == EMX_MCAST_ADDR_MAX)
1738 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1739 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1743 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1744 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1745 reg_rctl |= E1000_RCTL_MPE;
1746 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1748 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1753 * This routine checks for link status and updates statistics.
1756 emx_timer(void *xsc)
1758 struct emx_softc *sc = xsc;
1759 struct ifnet *ifp = &sc->arpcom.ac_if;
1761 lwkt_serialize_enter(&sc->main_serialize);
1763 emx_update_link_status(sc);
1764 emx_update_stats(sc);
1766 /* Reset LAA into RAR[0] on 82571 */
1767 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1768 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1770 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1771 emx_print_hw_stats(sc);
1775 callout_reset(&sc->timer, hz, emx_timer, sc);
1777 lwkt_serialize_exit(&sc->main_serialize);
1781 emx_update_link_status(struct emx_softc *sc)
1783 struct e1000_hw *hw = &sc->hw;
1784 struct ifnet *ifp = &sc->arpcom.ac_if;
1785 device_t dev = sc->dev;
1786 uint32_t link_check = 0;
1788 /* Get the cached link value or read phy for real */
1789 switch (hw->phy.media_type) {
1790 case e1000_media_type_copper:
1791 if (hw->mac.get_link_status) {
1792 /* Do the work to read phy */
1793 e1000_check_for_link(hw);
1794 link_check = !hw->mac.get_link_status;
1795 if (link_check) /* ESB2 fix */
1796 e1000_cfg_on_link_up(hw);
1802 case e1000_media_type_fiber:
1803 e1000_check_for_link(hw);
1804 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1807 case e1000_media_type_internal_serdes:
1808 e1000_check_for_link(hw);
1809 link_check = sc->hw.mac.serdes_has_link;
1812 case e1000_media_type_unknown:
1817 /* Now check for a transition */
1818 if (link_check && sc->link_active == 0) {
1819 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1823 * Check if we should enable/disable SPEED_MODE bit on
1826 if (sc->link_speed != SPEED_1000 &&
1827 (hw->mac.type == e1000_82571 ||
1828 hw->mac.type == e1000_82572)) {
1831 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1832 tarc0 &= ~EMX_TARC_SPEED_MODE;
1833 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1836 device_printf(dev, "Link is up %d Mbps %s\n",
1838 ((sc->link_duplex == FULL_DUPLEX) ?
1839 "Full Duplex" : "Half Duplex"));
1841 sc->link_active = 1;
1843 ifp->if_baudrate = sc->link_speed * 1000000;
1844 ifp->if_link_state = LINK_STATE_UP;
1845 if_link_state_change(ifp);
1846 } else if (!link_check && sc->link_active == 1) {
1847 ifp->if_baudrate = sc->link_speed = 0;
1848 sc->link_duplex = 0;
1850 device_printf(dev, "Link is Down\n");
1851 sc->link_active = 0;
1852 ifp->if_link_state = LINK_STATE_DOWN;
1853 if_link_state_change(ifp);
1858 emx_stop(struct emx_softc *sc)
1860 struct ifnet *ifp = &sc->arpcom.ac_if;
1863 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1865 emx_disable_intr(sc);
1867 callout_stop(&sc->timer);
1869 ifp->if_flags &= ~IFF_RUNNING;
1870 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1871 struct emx_txdata *tdata = &sc->tx_data[i];
1873 ifsq_clr_oactive(tdata->ifsq);
1874 ifsq_watchdog_stop(&tdata->tx_watchdog);
1875 tdata->tx_flags &= ~EMX_TXFLAG_ENABLED;
1879 * Disable multiple receive queues.
1882 * We should disable multiple receive queues before
1883 * resetting the hardware.
1885 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1887 e1000_reset_hw(&sc->hw);
1888 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1890 for (i = 0; i < sc->tx_ring_cnt; ++i)
1891 emx_free_tx_ring(&sc->tx_data[i]);
1892 for (i = 0; i < sc->rx_ring_cnt; ++i)
1893 emx_free_rx_ring(&sc->rx_data[i]);
1897 emx_reset(struct emx_softc *sc)
1899 device_t dev = sc->dev;
1900 uint16_t rx_buffer_size;
1903 /* Set up smart power down as default off on newer adapters. */
1904 if (!emx_smart_pwr_down &&
1905 (sc->hw.mac.type == e1000_82571 ||
1906 sc->hw.mac.type == e1000_82572)) {
1907 uint16_t phy_tmp = 0;
1909 /* Speed up time to link by disabling smart power down. */
1910 e1000_read_phy_reg(&sc->hw,
1911 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1912 phy_tmp &= ~IGP02E1000_PM_SPD;
1913 e1000_write_phy_reg(&sc->hw,
1914 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1918 * Packet Buffer Allocation (PBA)
1919 * Writing PBA sets the receive portion of the buffer
1920 * the remainder is used for the transmit buffer.
1922 switch (sc->hw.mac.type) {
1923 /* Total Packet Buffer on these is 48K */
1926 case e1000_80003es2lan:
1927 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1930 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1931 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1935 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1939 pba = E1000_PBA_26K;
1943 /* Devices before 82547 had a Packet Buffer of 64K. */
1944 if (sc->hw.mac.max_frame_size > 8192)
1945 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1947 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1949 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1952 * These parameters control the automatic generation (Tx) and
1953 * response (Rx) to Ethernet PAUSE frames.
1954 * - High water mark should allow for at least two frames to be
1955 * received after sending an XOFF.
1956 * - Low water mark works best when it is very near the high water mark.
1957 * This allows the receiver to restart by sending XON when it has
1958 * drained a bit. Here we use an arbitary value of 1500 which will
1959 * restart after one full frame is pulled from the buffer. There
1960 * could be several smaller frames in the buffer and if so they will
1961 * not trigger the XON until their total number reduces the buffer
1963 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1965 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1967 sc->hw.fc.high_water = rx_buffer_size -
1968 roundup2(sc->hw.mac.max_frame_size, 1024);
1969 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1971 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1972 sc->hw.fc.send_xon = TRUE;
1973 sc->hw.fc.requested_mode = e1000_fc_full;
1976 * Device specific overrides/settings
1978 if (sc->hw.mac.type == e1000_pch_lpt) {
1979 sc->hw.fc.high_water = 0x5C20;
1980 sc->hw.fc.low_water = 0x5048;
1981 sc->hw.fc.pause_time = 0x0650;
1982 sc->hw.fc.refresh_time = 0x0400;
1983 /* Jumbos need adjusted PBA */
1984 if (sc->arpcom.ac_if.if_mtu > ETHERMTU)
1985 E1000_WRITE_REG(&sc->hw, E1000_PBA, 12);
1987 E1000_WRITE_REG(&sc->hw, E1000_PBA, 26);
1988 } else if (sc->hw.mac.type == e1000_80003es2lan) {
1989 sc->hw.fc.pause_time = 0xFFFF;
1992 /* Issue a global reset */
1993 e1000_reset_hw(&sc->hw);
1994 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1995 emx_disable_aspm(sc);
1997 if (e1000_init_hw(&sc->hw) < 0) {
1998 device_printf(dev, "Hardware Initialization Failed\n");
2002 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
2003 e1000_get_phy_info(&sc->hw);
2004 e1000_check_for_link(&sc->hw);
2010 emx_setup_ifp(struct emx_softc *sc)
2012 struct ifnet *ifp = &sc->arpcom.ac_if;
2015 if_initname(ifp, device_get_name(sc->dev),
2016 device_get_unit(sc->dev));
2018 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2019 ifp->if_init = emx_init;
2020 ifp->if_ioctl = emx_ioctl;
2021 ifp->if_start = emx_start;
2022 #ifdef IFPOLL_ENABLE
2023 ifp->if_npoll = emx_npoll;
2025 ifp->if_serialize = emx_serialize;
2026 ifp->if_deserialize = emx_deserialize;
2027 ifp->if_tryserialize = emx_tryserialize;
2029 ifp->if_serialize_assert = emx_serialize_assert;
2032 ifp->if_nmbclusters = sc->rx_ring_cnt * sc->rx_data[0].num_rx_desc;
2034 ifq_set_maxlen(&ifp->if_snd, sc->tx_data[0].num_tx_desc - 1);
2035 ifq_set_ready(&ifp->if_snd);
2036 ifq_set_subq_cnt(&ifp->if_snd, sc->tx_ring_cnt);
2038 ifp->if_mapsubq = ifq_mapsubq_mask;
2039 ifq_set_subq_mask(&ifp->if_snd, 0);
2041 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
2043 ifp->if_capabilities = IFCAP_HWCSUM |
2044 IFCAP_VLAN_HWTAGGING |
2047 if (sc->rx_ring_cnt > 1)
2048 ifp->if_capabilities |= IFCAP_RSS;
2049 ifp->if_capenable = ifp->if_capabilities;
2050 ifp->if_hwassist = EMX_CSUM_FEATURES | CSUM_TSO;
2053 * Tell the upper layer(s) we support long frames.
2055 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2057 for (i = 0; i < sc->tx_ring_cnt; ++i) {
2058 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i);
2059 struct emx_txdata *tdata = &sc->tx_data[i];
2061 ifsq_set_cpuid(ifsq, rman_get_cpuid(sc->intr_res));
2062 ifsq_set_priv(ifsq, tdata);
2063 ifsq_set_hw_serialize(ifsq, &tdata->tx_serialize);
2066 ifsq_watchdog_init(&tdata->tx_watchdog, ifsq, emx_watchdog);
2070 * Specify the media types supported by this sc and register
2071 * callbacks to update media and link information
2073 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2074 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
2075 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2077 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
2079 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
2080 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
2082 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2083 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
2085 if (sc->hw.phy.type != e1000_phy_ife) {
2086 ifmedia_add(&sc->media,
2087 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2088 ifmedia_add(&sc->media,
2089 IFM_ETHER | IFM_1000_T, 0, NULL);
2092 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2093 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
2097 * Workaround for SmartSpeed on 82541 and 82547 controllers
2100 emx_smartspeed(struct emx_softc *sc)
2104 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
2105 sc->hw.mac.autoneg == 0 ||
2106 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2109 if (sc->smartspeed == 0) {
2111 * If Master/Slave config fault is asserted twice,
2112 * we assume back-to-back
2114 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2115 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2117 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2118 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2119 e1000_read_phy_reg(&sc->hw,
2120 PHY_1000T_CTRL, &phy_tmp);
2121 if (phy_tmp & CR_1000T_MS_ENABLE) {
2122 phy_tmp &= ~CR_1000T_MS_ENABLE;
2123 e1000_write_phy_reg(&sc->hw,
2124 PHY_1000T_CTRL, phy_tmp);
2126 if (sc->hw.mac.autoneg &&
2127 !e1000_phy_setup_autoneg(&sc->hw) &&
2128 !e1000_read_phy_reg(&sc->hw,
2129 PHY_CONTROL, &phy_tmp)) {
2130 phy_tmp |= MII_CR_AUTO_NEG_EN |
2131 MII_CR_RESTART_AUTO_NEG;
2132 e1000_write_phy_reg(&sc->hw,
2133 PHY_CONTROL, phy_tmp);
2138 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
2139 /* If still no link, perhaps using 2/3 pair cable */
2140 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
2141 phy_tmp |= CR_1000T_MS_ENABLE;
2142 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
2143 if (sc->hw.mac.autoneg &&
2144 !e1000_phy_setup_autoneg(&sc->hw) &&
2145 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
2146 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2147 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
2151 /* Restart process after EMX_SMARTSPEED_MAX iterations */
2152 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
2157 emx_create_tx_ring(struct emx_txdata *tdata)
2159 device_t dev = tdata->sc->dev;
2160 struct emx_txbuf *tx_buffer;
2161 int error, i, tsize, ntxd;
2164 * Validate number of transmit descriptors. It must not exceed
2165 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2167 ntxd = device_getenv_int(dev, "txd", emx_txd);
2168 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
2169 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) {
2170 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
2171 EMX_DEFAULT_TXD, ntxd);
2172 tdata->num_tx_desc = EMX_DEFAULT_TXD;
2174 tdata->num_tx_desc = ntxd;
2178 * Allocate Transmit Descriptor ring
2180 tsize = roundup2(tdata->num_tx_desc * sizeof(struct e1000_tx_desc),
2182 tdata->tx_desc_base = bus_dmamem_coherent_any(tdata->sc->parent_dtag,
2183 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
2184 &tdata->tx_desc_dtag, &tdata->tx_desc_dmap,
2185 &tdata->tx_desc_paddr);
2186 if (tdata->tx_desc_base == NULL) {
2187 device_printf(dev, "Unable to allocate tx_desc memory\n");
2191 tsize = __VM_CACHELINE_ALIGN(
2192 sizeof(struct emx_txbuf) * tdata->num_tx_desc);
2193 tdata->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
2196 * Create DMA tags for tx buffers
2198 error = bus_dma_tag_create(tdata->sc->parent_dtag, /* parent */
2199 1, 0, /* alignment, bounds */
2200 BUS_SPACE_MAXADDR, /* lowaddr */
2201 BUS_SPACE_MAXADDR, /* highaddr */
2202 NULL, NULL, /* filter, filterarg */
2203 EMX_TSO_SIZE, /* maxsize */
2204 EMX_MAX_SCATTER, /* nsegments */
2205 EMX_MAX_SEGSIZE, /* maxsegsize */
2206 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2207 BUS_DMA_ONEBPAGE, /* flags */
2210 device_printf(dev, "Unable to allocate TX DMA tag\n");
2211 kfree(tdata->tx_buf, M_DEVBUF);
2212 tdata->tx_buf = NULL;
2217 * Create DMA maps for tx buffers
2219 for (i = 0; i < tdata->num_tx_desc; i++) {
2220 tx_buffer = &tdata->tx_buf[i];
2222 error = bus_dmamap_create(tdata->txtag,
2223 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2226 device_printf(dev, "Unable to create TX DMA map\n");
2227 emx_destroy_tx_ring(tdata, i);
2233 * Setup TX parameters
2235 tdata->spare_tx_desc = EMX_TX_SPARE;
2236 tdata->tx_wreg_nsegs = EMX_DEFAULT_TXWREG;
2239 * Keep following relationship between spare_tx_desc, oact_tx_desc
2240 * and tx_intr_nsegs:
2241 * (spare_tx_desc + EMX_TX_RESERVED) <=
2242 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_intr_nsegs
2244 tdata->oact_tx_desc = tdata->num_tx_desc / 8;
2245 if (tdata->oact_tx_desc > EMX_TX_OACTIVE_MAX)
2246 tdata->oact_tx_desc = EMX_TX_OACTIVE_MAX;
2247 if (tdata->oact_tx_desc < tdata->spare_tx_desc + EMX_TX_RESERVED)
2248 tdata->oact_tx_desc = tdata->spare_tx_desc + EMX_TX_RESERVED;
2250 tdata->tx_intr_nsegs = tdata->num_tx_desc / 16;
2251 if (tdata->tx_intr_nsegs < tdata->oact_tx_desc)
2252 tdata->tx_intr_nsegs = tdata->oact_tx_desc;
2255 * Pullup extra 4bytes into the first data segment for TSO, see:
2256 * 82571/82572 specification update errata #7
2258 * Same applies to I217 (and maybe I218).
2261 * 4bytes instead of 2bytes, which are mentioned in the errata,
2262 * are pulled; mainly to keep rest of the data properly aligned.
2264 if (tdata->sc->hw.mac.type == e1000_82571 ||
2265 tdata->sc->hw.mac.type == e1000_82572 ||
2266 tdata->sc->hw.mac.type == e1000_pch_lpt)
2267 tdata->tx_flags |= EMX_TXFLAG_TSO_PULLEX;
2273 emx_init_tx_ring(struct emx_txdata *tdata)
2275 /* Clear the old ring contents */
2276 bzero(tdata->tx_desc_base,
2277 sizeof(struct e1000_tx_desc) * tdata->num_tx_desc);
2280 tdata->next_avail_tx_desc = 0;
2281 tdata->next_tx_to_clean = 0;
2282 tdata->num_tx_desc_avail = tdata->num_tx_desc;
2284 tdata->tx_flags |= EMX_TXFLAG_ENABLED;
2285 if (tdata->sc->tx_ring_inuse > 1) {
2286 tdata->tx_flags |= EMX_TXFLAG_FORCECTX;
2288 if_printf(&tdata->sc->arpcom.ac_if,
2289 "TX %d force ctx setup\n", tdata->idx);
2295 emx_init_tx_unit(struct emx_softc *sc)
2297 uint32_t tctl, tarc, tipg = 0, txdctl;
2300 for (i = 0; i < sc->tx_ring_inuse; ++i) {
2301 struct emx_txdata *tdata = &sc->tx_data[i];
2304 /* Setup the Base and Length of the Tx Descriptor Ring */
2305 bus_addr = tdata->tx_desc_paddr;
2306 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(i),
2307 tdata->num_tx_desc * sizeof(struct e1000_tx_desc));
2308 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(i),
2309 (uint32_t)(bus_addr >> 32));
2310 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(i),
2311 (uint32_t)bus_addr);
2312 /* Setup the HW Tx Head and Tail descriptor pointers */
2313 E1000_WRITE_REG(&sc->hw, E1000_TDT(i), 0);
2314 E1000_WRITE_REG(&sc->hw, E1000_TDH(i), 0);
2317 /* Set the default values for the Tx Inter Packet Gap timer */
2318 switch (sc->hw.mac.type) {
2319 case e1000_80003es2lan:
2320 tipg = DEFAULT_82543_TIPG_IPGR1;
2321 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2322 E1000_TIPG_IPGR2_SHIFT;
2326 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2327 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2328 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2330 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2331 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2332 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2336 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2338 /* NOTE: 0 is not allowed for TIDV */
2339 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2340 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2343 * Errata workaround (obtained from Linux). This is necessary
2344 * to make multiple TX queues work on 82574.
2345 * XXX can't find it in any published errata though.
2347 txdctl = E1000_READ_REG(&sc->hw, E1000_TXDCTL(0));
2348 E1000_WRITE_REG(&sc->hw, E1000_TXDCTL(1), txdctl);
2350 if (sc->hw.mac.type == e1000_82571 ||
2351 sc->hw.mac.type == e1000_82572) {
2352 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2353 tarc |= EMX_TARC_SPEED_MODE;
2354 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2355 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2356 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2358 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2359 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2361 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2364 /* Program the Transmit Control Register */
2365 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2366 tctl &= ~E1000_TCTL_CT;
2367 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2368 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2369 tctl |= E1000_TCTL_MULR;
2371 /* This write will effectively turn on the transmit unit. */
2372 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2374 if (sc->hw.mac.type == e1000_82571 ||
2375 sc->hw.mac.type == e1000_82572 ||
2376 sc->hw.mac.type == e1000_80003es2lan) {
2377 /* Bit 28 of TARC1 must be cleared when MULR is enabled */
2378 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2380 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2383 if (sc->tx_ring_inuse > 1) {
2384 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2385 tarc &= ~EMX_TARC_COUNT_MASK;
2387 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2389 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2390 tarc &= ~EMX_TARC_COUNT_MASK;
2392 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2397 emx_destroy_tx_ring(struct emx_txdata *tdata, int ndesc)
2399 struct emx_txbuf *tx_buffer;
2402 /* Free Transmit Descriptor ring */
2403 if (tdata->tx_desc_base) {
2404 bus_dmamap_unload(tdata->tx_desc_dtag, tdata->tx_desc_dmap);
2405 bus_dmamem_free(tdata->tx_desc_dtag, tdata->tx_desc_base,
2406 tdata->tx_desc_dmap);
2407 bus_dma_tag_destroy(tdata->tx_desc_dtag);
2409 tdata->tx_desc_base = NULL;
2412 if (tdata->tx_buf == NULL)
2415 for (i = 0; i < ndesc; i++) {
2416 tx_buffer = &tdata->tx_buf[i];
2418 KKASSERT(tx_buffer->m_head == NULL);
2419 bus_dmamap_destroy(tdata->txtag, tx_buffer->map);
2421 bus_dma_tag_destroy(tdata->txtag);
2423 kfree(tdata->tx_buf, M_DEVBUF);
2424 tdata->tx_buf = NULL;
2428 * The offload context needs to be set when we transfer the first
2429 * packet of a particular protocol (TCP/UDP). This routine has been
2430 * enhanced to deal with inserted VLAN headers.
2432 * If the new packet's ether header length, ip header length and
2433 * csum offloading type are same as the previous packet, we should
2434 * avoid allocating a new csum context descriptor; mainly to take
2435 * advantage of the pipeline effect of the TX data read request.
2437 * This function returns number of TX descrptors allocated for
2441 emx_txcsum(struct emx_txdata *tdata, struct mbuf *mp,
2442 uint32_t *txd_upper, uint32_t *txd_lower)
2444 struct e1000_context_desc *TXD;
2445 int curr_txd, ehdrlen, csum_flags;
2446 uint32_t cmd, hdr_len, ip_hlen;
2448 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2449 ip_hlen = mp->m_pkthdr.csum_iphlen;
2450 ehdrlen = mp->m_pkthdr.csum_lhlen;
2452 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 &&
2453 tdata->csum_lhlen == ehdrlen && tdata->csum_iphlen == ip_hlen &&
2454 tdata->csum_flags == csum_flags) {
2456 * Same csum offload context as the previous packets;
2459 *txd_upper = tdata->csum_txd_upper;
2460 *txd_lower = tdata->csum_txd_lower;
2465 * Setup a new csum offload context.
2468 curr_txd = tdata->next_avail_tx_desc;
2469 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd];
2473 /* Setup of IP header checksum. */
2474 if (csum_flags & CSUM_IP) {
2476 * Start offset for header checksum calculation.
2477 * End offset for header checksum calculation.
2478 * Offset of place to put the checksum.
2480 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2481 TXD->lower_setup.ip_fields.ipcse =
2482 htole16(ehdrlen + ip_hlen - 1);
2483 TXD->lower_setup.ip_fields.ipcso =
2484 ehdrlen + offsetof(struct ip, ip_sum);
2485 cmd |= E1000_TXD_CMD_IP;
2486 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2488 hdr_len = ehdrlen + ip_hlen;
2490 if (csum_flags & CSUM_TCP) {
2492 * Start offset for payload checksum calculation.
2493 * End offset for payload checksum calculation.
2494 * Offset of place to put the checksum.
2496 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2497 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2498 TXD->upper_setup.tcp_fields.tucso =
2499 hdr_len + offsetof(struct tcphdr, th_sum);
2500 cmd |= E1000_TXD_CMD_TCP;
2501 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2502 } else if (csum_flags & CSUM_UDP) {
2504 * Start offset for header checksum calculation.
2505 * End offset for header checksum calculation.
2506 * Offset of place to put the checksum.
2508 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2509 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2510 TXD->upper_setup.tcp_fields.tucso =
2511 hdr_len + offsetof(struct udphdr, uh_sum);
2512 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2515 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2516 E1000_TXD_DTYP_D; /* Data descr */
2518 /* Save the information for this csum offloading context */
2519 tdata->csum_lhlen = ehdrlen;
2520 tdata->csum_iphlen = ip_hlen;
2521 tdata->csum_flags = csum_flags;
2522 tdata->csum_txd_upper = *txd_upper;
2523 tdata->csum_txd_lower = *txd_lower;
2525 TXD->tcp_seg_setup.data = htole32(0);
2526 TXD->cmd_and_length =
2527 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2529 if (++curr_txd == tdata->num_tx_desc)
2532 KKASSERT(tdata->num_tx_desc_avail > 0);
2533 tdata->num_tx_desc_avail--;
2535 tdata->next_avail_tx_desc = curr_txd;
2540 emx_txeof(struct emx_txdata *tdata)
2542 struct emx_txbuf *tx_buffer;
2543 int first, num_avail;
2545 if (tdata->tx_dd_head == tdata->tx_dd_tail)
2548 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2551 num_avail = tdata->num_tx_desc_avail;
2552 first = tdata->next_tx_to_clean;
2554 while (tdata->tx_dd_head != tdata->tx_dd_tail) {
2555 int dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2556 struct e1000_tx_desc *tx_desc;
2558 tx_desc = &tdata->tx_desc_base[dd_idx];
2559 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2560 EMX_INC_TXDD_IDX(tdata->tx_dd_head);
2562 if (++dd_idx == tdata->num_tx_desc)
2565 while (first != dd_idx) {
2570 tx_buffer = &tdata->tx_buf[first];
2571 if (tx_buffer->m_head) {
2572 bus_dmamap_unload(tdata->txtag,
2574 m_freem(tx_buffer->m_head);
2575 tx_buffer->m_head = NULL;
2578 if (++first == tdata->num_tx_desc)
2585 tdata->next_tx_to_clean = first;
2586 tdata->num_tx_desc_avail = num_avail;
2588 if (tdata->tx_dd_head == tdata->tx_dd_tail) {
2589 tdata->tx_dd_head = 0;
2590 tdata->tx_dd_tail = 0;
2593 if (!EMX_IS_OACTIVE(tdata)) {
2594 ifsq_clr_oactive(tdata->ifsq);
2596 /* All clean, turn off the timer */
2597 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2598 tdata->tx_watchdog.wd_timer = 0;
2603 emx_tx_collect(struct emx_txdata *tdata)
2605 struct emx_txbuf *tx_buffer;
2606 int tdh, first, num_avail, dd_idx = -1;
2608 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2611 tdh = E1000_READ_REG(&tdata->sc->hw, E1000_TDH(tdata->idx));
2612 if (tdh == tdata->next_tx_to_clean)
2615 if (tdata->tx_dd_head != tdata->tx_dd_tail)
2616 dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2618 num_avail = tdata->num_tx_desc_avail;
2619 first = tdata->next_tx_to_clean;
2621 while (first != tdh) {
2626 tx_buffer = &tdata->tx_buf[first];
2627 if (tx_buffer->m_head) {
2628 bus_dmamap_unload(tdata->txtag,
2630 m_freem(tx_buffer->m_head);
2631 tx_buffer->m_head = NULL;
2634 if (first == dd_idx) {
2635 EMX_INC_TXDD_IDX(tdata->tx_dd_head);
2636 if (tdata->tx_dd_head == tdata->tx_dd_tail) {
2637 tdata->tx_dd_head = 0;
2638 tdata->tx_dd_tail = 0;
2641 dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2645 if (++first == tdata->num_tx_desc)
2648 tdata->next_tx_to_clean = first;
2649 tdata->num_tx_desc_avail = num_avail;
2651 if (!EMX_IS_OACTIVE(tdata)) {
2652 ifsq_clr_oactive(tdata->ifsq);
2654 /* All clean, turn off the timer */
2655 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2656 tdata->tx_watchdog.wd_timer = 0;
2661 * When Link is lost sometimes there is work still in the TX ring
2662 * which will result in a watchdog, rather than allow that do an
2663 * attempted cleanup and then reinit here. Note that this has been
2664 * seens mostly with fiber adapters.
2667 emx_tx_purge(struct emx_softc *sc)
2671 if (sc->link_active)
2674 for (i = 0; i < sc->tx_ring_inuse; ++i) {
2675 struct emx_txdata *tdata = &sc->tx_data[i];
2677 if (tdata->tx_watchdog.wd_timer) {
2678 emx_tx_collect(tdata);
2679 if (tdata->tx_watchdog.wd_timer) {
2680 if_printf(&sc->arpcom.ac_if,
2681 "Link lost, TX pending, reinit\n");
2690 emx_newbuf(struct emx_rxdata *rdata, int i, int init)
2693 bus_dma_segment_t seg;
2695 struct emx_rxbuf *rx_buffer;
2698 m = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR);
2701 if_printf(&rdata->sc->arpcom.ac_if,
2702 "Unable to allocate RX mbuf\n");
2706 m->m_len = m->m_pkthdr.len = MCLBYTES;
2708 if (rdata->sc->hw.mac.max_frame_size <= MCLBYTES - ETHER_ALIGN)
2709 m_adj(m, ETHER_ALIGN);
2711 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2712 rdata->rx_sparemap, m,
2713 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2717 if_printf(&rdata->sc->arpcom.ac_if,
2718 "Unable to load RX mbuf\n");
2723 rx_buffer = &rdata->rx_buf[i];
2724 if (rx_buffer->m_head != NULL)
2725 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2727 map = rx_buffer->map;
2728 rx_buffer->map = rdata->rx_sparemap;
2729 rdata->rx_sparemap = map;
2731 rx_buffer->m_head = m;
2732 rx_buffer->paddr = seg.ds_addr;
2734 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
2739 emx_create_rx_ring(struct emx_rxdata *rdata)
2741 device_t dev = rdata->sc->dev;
2742 struct emx_rxbuf *rx_buffer;
2743 int i, error, rsize, nrxd;
2746 * Validate number of receive descriptors. It must not exceed
2747 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2749 nrxd = device_getenv_int(dev, "rxd", emx_rxd);
2750 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2751 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) {
2752 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2753 EMX_DEFAULT_RXD, nrxd);
2754 rdata->num_rx_desc = EMX_DEFAULT_RXD;
2756 rdata->num_rx_desc = nrxd;
2760 * Allocate Receive Descriptor ring
2762 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
2764 rdata->rx_desc = bus_dmamem_coherent_any(rdata->sc->parent_dtag,
2765 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2766 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2767 &rdata->rx_desc_paddr);
2768 if (rdata->rx_desc == NULL) {
2769 device_printf(dev, "Unable to allocate rx_desc memory\n");
2773 rsize = __VM_CACHELINE_ALIGN(
2774 sizeof(struct emx_rxbuf) * rdata->num_rx_desc);
2775 rdata->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2778 * Create DMA tag for rx buffers
2780 error = bus_dma_tag_create(rdata->sc->parent_dtag, /* parent */
2781 1, 0, /* alignment, bounds */
2782 BUS_SPACE_MAXADDR, /* lowaddr */
2783 BUS_SPACE_MAXADDR, /* highaddr */
2784 NULL, NULL, /* filter, filterarg */
2785 MCLBYTES, /* maxsize */
2787 MCLBYTES, /* maxsegsize */
2788 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2791 device_printf(dev, "Unable to allocate RX DMA tag\n");
2792 kfree(rdata->rx_buf, M_DEVBUF);
2793 rdata->rx_buf = NULL;
2798 * Create spare DMA map for rx buffers
2800 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2801 &rdata->rx_sparemap);
2803 device_printf(dev, "Unable to create spare RX DMA map\n");
2804 bus_dma_tag_destroy(rdata->rxtag);
2805 kfree(rdata->rx_buf, M_DEVBUF);
2806 rdata->rx_buf = NULL;
2811 * Create DMA maps for rx buffers
2813 for (i = 0; i < rdata->num_rx_desc; i++) {
2814 rx_buffer = &rdata->rx_buf[i];
2816 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2819 device_printf(dev, "Unable to create RX DMA map\n");
2820 emx_destroy_rx_ring(rdata, i);
2828 emx_free_rx_ring(struct emx_rxdata *rdata)
2832 for (i = 0; i < rdata->num_rx_desc; i++) {
2833 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
2835 if (rx_buffer->m_head != NULL) {
2836 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2837 m_freem(rx_buffer->m_head);
2838 rx_buffer->m_head = NULL;
2842 if (rdata->fmp != NULL)
2843 m_freem(rdata->fmp);
2849 emx_free_tx_ring(struct emx_txdata *tdata)
2853 for (i = 0; i < tdata->num_tx_desc; i++) {
2854 struct emx_txbuf *tx_buffer = &tdata->tx_buf[i];
2856 if (tx_buffer->m_head != NULL) {
2857 bus_dmamap_unload(tdata->txtag, tx_buffer->map);
2858 m_freem(tx_buffer->m_head);
2859 tx_buffer->m_head = NULL;
2863 tdata->tx_flags &= ~EMX_TXFLAG_FORCECTX;
2865 tdata->csum_flags = 0;
2866 tdata->csum_lhlen = 0;
2867 tdata->csum_iphlen = 0;
2868 tdata->csum_thlen = 0;
2869 tdata->csum_mss = 0;
2870 tdata->csum_pktlen = 0;
2872 tdata->tx_dd_head = 0;
2873 tdata->tx_dd_tail = 0;
2874 tdata->tx_nsegs = 0;
2878 emx_init_rx_ring(struct emx_rxdata *rdata)
2882 /* Reset descriptor ring */
2883 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
2885 /* Allocate new ones. */
2886 for (i = 0; i < rdata->num_rx_desc; i++) {
2887 error = emx_newbuf(rdata, i, 1);
2892 /* Setup our descriptor pointers */
2893 rdata->next_rx_desc_to_check = 0;
2899 emx_init_rx_unit(struct emx_softc *sc)
2901 struct ifnet *ifp = &sc->arpcom.ac_if;
2903 uint32_t rctl, itr, rfctl;
2907 * Make sure receives are disabled while setting
2908 * up the descriptor ring
2910 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2911 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2914 * Set the interrupt throttling rate. Value is calculated
2915 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2917 if (sc->int_throttle_ceil)
2918 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2921 emx_set_itr(sc, itr);
2923 /* Use extended RX descriptor */
2924 rfctl = E1000_RFCTL_EXTEN;
2926 /* Disable accelerated ackknowledge */
2927 if (sc->hw.mac.type == e1000_82574)
2928 rfctl |= E1000_RFCTL_ACK_DIS;
2930 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
2933 * Receive Checksum Offload for TCP and UDP
2935 * Checksum offloading is also enabled if multiple receive
2936 * queue is to be supported, since we need it to figure out
2939 if ((ifp->if_capenable & IFCAP_RXCSUM) ||
2940 sc->rx_ring_cnt > 1) {
2943 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2947 * PCSD must be enabled to enable multiple
2950 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2952 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2956 * Configure multiple receive queue (RSS)
2958 if (sc->rx_ring_cnt > 1) {
2959 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2962 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING,
2963 ("invalid number of RX ring (%d)", sc->rx_ring_cnt));
2967 * When we reach here, RSS has already been disabled
2968 * in emx_stop(), so we could safely configure RSS key
2969 * and redirect table.
2975 toeplitz_get_key(key, sizeof(key));
2976 for (i = 0; i < EMX_NRSSRK; ++i) {
2979 rssrk = EMX_RSSRK_VAL(key, i);
2980 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2982 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2986 * Configure RSS redirect table in following fashion:
2987 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2990 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2993 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT;
2994 reta |= q << (8 * i);
2996 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2998 for (i = 0; i < EMX_NRETA; ++i)
2999 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
3002 * Enable multiple receive queues.
3003 * Enable IPv4 RSS standard hash functions.
3004 * Disable RSS interrupt.
3006 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
3007 E1000_MRQC_ENABLE_RSS_2Q |
3008 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3009 E1000_MRQC_RSS_FIELD_IPV4);
3013 * XXX TEMPORARY WORKAROUND: on some systems with 82573
3014 * long latencies are observed, like Lenovo X60. This
3015 * change eliminates the problem, but since having positive
3016 * values in RDTR is a known source of problems on other
3017 * platforms another solution is being sought.
3019 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
3020 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
3021 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
3024 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3025 struct emx_rxdata *rdata = &sc->rx_data[i];
3028 * Setup the Base and Length of the Rx Descriptor Ring
3030 bus_addr = rdata->rx_desc_paddr;
3031 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
3032 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
3033 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
3034 (uint32_t)(bus_addr >> 32));
3035 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
3036 (uint32_t)bus_addr);
3039 * Setup the HW Rx Head and Tail Descriptor Pointers
3041 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
3042 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
3043 sc->rx_data[i].num_rx_desc - 1);
3046 if (sc->hw.mac.type >= e1000_pch2lan) {
3047 if (ifp->if_mtu > ETHERMTU)
3048 e1000_lv_jumbo_workaround_ich8lan(&sc->hw, TRUE);
3050 e1000_lv_jumbo_workaround_ich8lan(&sc->hw, FALSE);
3053 /* Setup the Receive Control Register */
3054 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3055 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
3056 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
3057 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3059 /* Make sure VLAN Filters are off */
3060 rctl &= ~E1000_RCTL_VFE;
3062 /* Don't store bad paket */
3063 rctl &= ~E1000_RCTL_SBP;
3066 rctl |= E1000_RCTL_SZ_2048;
3068 if (ifp->if_mtu > ETHERMTU)
3069 rctl |= E1000_RCTL_LPE;
3071 rctl &= ~E1000_RCTL_LPE;
3073 /* Enable Receives */
3074 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
3078 emx_destroy_rx_ring(struct emx_rxdata *rdata, int ndesc)
3080 struct emx_rxbuf *rx_buffer;
3083 /* Free Receive Descriptor ring */
3084 if (rdata->rx_desc) {
3085 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
3086 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
3087 rdata->rx_desc_dmap);
3088 bus_dma_tag_destroy(rdata->rx_desc_dtag);
3090 rdata->rx_desc = NULL;
3093 if (rdata->rx_buf == NULL)
3096 for (i = 0; i < ndesc; i++) {
3097 rx_buffer = &rdata->rx_buf[i];
3099 KKASSERT(rx_buffer->m_head == NULL);
3100 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
3102 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
3103 bus_dma_tag_destroy(rdata->rxtag);
3105 kfree(rdata->rx_buf, M_DEVBUF);
3106 rdata->rx_buf = NULL;
3110 emx_rxeof(struct emx_rxdata *rdata, int count)
3112 struct ifnet *ifp = &rdata->sc->arpcom.ac_if;
3114 emx_rxdesc_t *current_desc;
3116 int i, cpuid = mycpuid;
3118 i = rdata->next_rx_desc_to_check;
3119 current_desc = &rdata->rx_desc[i];
3120 staterr = le32toh(current_desc->rxd_staterr);
3122 if (!(staterr & E1000_RXD_STAT_DD))
3125 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
3126 struct pktinfo *pi = NULL, pi0;
3127 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
3128 struct mbuf *m = NULL;
3133 mp = rx_buf->m_head;
3136 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
3137 * needs to access the last received byte in the mbuf.
3139 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
3140 BUS_DMASYNC_POSTREAD);
3142 len = le16toh(current_desc->rxd_length);
3143 if (staterr & E1000_RXD_STAT_EOP) {
3150 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
3152 uint32_t mrq, rss_hash;
3155 * Save several necessary information,
3156 * before emx_newbuf() destroy it.
3158 if ((staterr & E1000_RXD_STAT_VP) && eop)
3159 vlan = le16toh(current_desc->rxd_vlan);
3161 mrq = le32toh(current_desc->rxd_mrq);
3162 rss_hash = le32toh(current_desc->rxd_rss);
3164 EMX_RSS_DPRINTF(rdata->sc, 10,
3165 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
3166 rdata->idx, mrq, rss_hash);
3168 if (emx_newbuf(rdata, i, 0) != 0) {
3169 IFNET_STAT_INC(ifp, iqdrops, 1);
3173 /* Assign correct length to the current fragment */
3176 if (rdata->fmp == NULL) {
3177 mp->m_pkthdr.len = len;
3178 rdata->fmp = mp; /* Store the first mbuf */
3182 * Chain mbuf's together
3184 rdata->lmp->m_next = mp;
3185 rdata->lmp = rdata->lmp->m_next;
3186 rdata->fmp->m_pkthdr.len += len;
3190 rdata->fmp->m_pkthdr.rcvif = ifp;
3191 IFNET_STAT_INC(ifp, ipackets, 1);
3193 if (ifp->if_capenable & IFCAP_RXCSUM)
3194 emx_rxcsum(staterr, rdata->fmp);
3196 if (staterr & E1000_RXD_STAT_VP) {
3197 rdata->fmp->m_pkthdr.ether_vlantag =
3199 rdata->fmp->m_flags |= M_VLANTAG;
3205 if (ifp->if_capenable & IFCAP_RSS) {
3206 pi = emx_rssinfo(m, &pi0, mrq,
3209 #ifdef EMX_RSS_DEBUG
3214 IFNET_STAT_INC(ifp, ierrors, 1);
3216 emx_setup_rxdesc(current_desc, rx_buf);
3217 if (rdata->fmp != NULL) {
3218 m_freem(rdata->fmp);
3226 ifp->if_input(ifp, m, pi, cpuid);
3228 /* Advance our pointers to the next descriptor. */
3229 if (++i == rdata->num_rx_desc)
3232 current_desc = &rdata->rx_desc[i];
3233 staterr = le32toh(current_desc->rxd_staterr);
3235 rdata->next_rx_desc_to_check = i;
3237 /* Advance the E1000's Receive Queue "Tail Pointer". */
3239 i = rdata->num_rx_desc - 1;
3240 E1000_WRITE_REG(&rdata->sc->hw, E1000_RDT(rdata->idx), i);
3244 emx_enable_intr(struct emx_softc *sc)
3246 uint32_t ims_mask = IMS_ENABLE_MASK;
3248 lwkt_serialize_handler_enable(&sc->main_serialize);
3251 if (sc->hw.mac.type == e1000_82574) {
3252 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
3253 ims_mask |= EM_MSIX_MASK;
3256 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
3260 emx_disable_intr(struct emx_softc *sc)
3262 if (sc->hw.mac.type == e1000_82574)
3263 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
3264 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
3266 lwkt_serialize_handler_disable(&sc->main_serialize);
3270 * Bit of a misnomer, what this really means is
3271 * to enable OS management of the system... aka
3272 * to disable special hardware management features
3275 emx_get_mgmt(struct emx_softc *sc)
3277 /* A shared code workaround */
3278 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3279 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3280 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3282 /* disable hardware interception of ARP */
3283 manc &= ~(E1000_MANC_ARP_EN);
3285 /* enable receiving management packets to the host */
3286 manc |= E1000_MANC_EN_MNG2HOST;
3287 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3288 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3289 manc2h |= E1000_MNG2HOST_PORT_623;
3290 manc2h |= E1000_MNG2HOST_PORT_664;
3291 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3293 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3298 * Give control back to hardware management
3299 * controller if there is one.
3302 emx_rel_mgmt(struct emx_softc *sc)
3304 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3305 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3307 /* re-enable hardware interception of ARP */
3308 manc |= E1000_MANC_ARP_EN;
3309 manc &= ~E1000_MANC_EN_MNG2HOST;
3311 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3316 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3317 * For ASF and Pass Through versions of f/w this means that
3318 * the driver is loaded. For AMT version (only with 82573)
3319 * of the f/w this means that the network i/f is open.
3322 emx_get_hw_control(struct emx_softc *sc)
3324 /* Let firmware know the driver has taken over */
3325 if (sc->hw.mac.type == e1000_82573) {
3328 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3329 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3330 swsm | E1000_SWSM_DRV_LOAD);
3334 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3335 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3336 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3338 sc->flags |= EMX_FLAG_HW_CTRL;
3342 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3343 * For ASF and Pass Through versions of f/w this means that the
3344 * driver is no longer loaded. For AMT version (only with 82573)
3345 * of the f/w this means that the network i/f is closed.
3348 emx_rel_hw_control(struct emx_softc *sc)
3350 if ((sc->flags & EMX_FLAG_HW_CTRL) == 0)
3352 sc->flags &= ~EMX_FLAG_HW_CTRL;
3354 /* Let firmware taken over control of h/w */
3355 if (sc->hw.mac.type == e1000_82573) {
3358 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3359 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3360 swsm & ~E1000_SWSM_DRV_LOAD);
3364 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3365 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3366 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3371 emx_is_valid_eaddr(const uint8_t *addr)
3373 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3375 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3382 * Enable PCI Wake On Lan capability
3385 emx_enable_wol(device_t dev)
3387 uint16_t cap, status;
3390 /* First find the capabilities pointer*/
3391 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3393 /* Read the PM Capabilities */
3394 id = pci_read_config(dev, cap, 1);
3395 if (id != PCIY_PMG) /* Something wrong */
3399 * OK, we have the power capabilities,
3400 * so now get the status register
3402 cap += PCIR_POWER_STATUS;
3403 status = pci_read_config(dev, cap, 2);
3404 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3405 pci_write_config(dev, cap, status, 2);
3409 emx_update_stats(struct emx_softc *sc)
3411 struct ifnet *ifp = &sc->arpcom.ac_if;
3413 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3414 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3415 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3416 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3418 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3419 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3420 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3421 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3423 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3424 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3425 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3426 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3427 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3428 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3429 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3430 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3431 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3432 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3433 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3434 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3435 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3436 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3437 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3438 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3439 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3440 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3441 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3442 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3444 /* For the 64-bit byte counters the low dword must be read first. */
3445 /* Both registers clear on the read of the high dword */
3447 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3448 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3450 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3451 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3452 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3453 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3454 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3456 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3457 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3459 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3460 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3461 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3462 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3463 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3464 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3465 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3466 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3467 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3468 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3470 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3471 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3472 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3473 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3474 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3475 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3477 IFNET_STAT_SET(ifp, collisions, sc->stats.colc);
3480 IFNET_STAT_SET(ifp, ierrors,
3481 sc->stats.rxerrc + sc->stats.crcerrs + sc->stats.algnerrc +
3482 sc->stats.ruc + sc->stats.roc + sc->stats.mpc + sc->stats.cexterr);
3485 IFNET_STAT_SET(ifp, oerrors, sc->stats.ecol + sc->stats.latecol);
3489 emx_print_debug_info(struct emx_softc *sc)
3491 device_t dev = sc->dev;
3492 uint8_t *hw_addr = sc->hw.hw_addr;
3495 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3496 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3497 E1000_READ_REG(&sc->hw, E1000_CTRL),
3498 E1000_READ_REG(&sc->hw, E1000_RCTL));
3499 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3500 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3501 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3502 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3503 sc->hw.fc.high_water, sc->hw.fc.low_water);
3504 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3505 E1000_READ_REG(&sc->hw, E1000_TIDV),
3506 E1000_READ_REG(&sc->hw, E1000_TADV));
3507 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3508 E1000_READ_REG(&sc->hw, E1000_RDTR),
3509 E1000_READ_REG(&sc->hw, E1000_RADV));
3511 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3512 device_printf(dev, "hw %d tdh = %d, hw tdt = %d\n", i,
3513 E1000_READ_REG(&sc->hw, E1000_TDH(i)),
3514 E1000_READ_REG(&sc->hw, E1000_TDT(i)));
3516 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3517 device_printf(dev, "hw %d rdh = %d, hw rdt = %d\n", i,
3518 E1000_READ_REG(&sc->hw, E1000_RDH(i)),
3519 E1000_READ_REG(&sc->hw, E1000_RDT(i)));
3522 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3523 device_printf(dev, "TX %d Tx descriptors avail = %d\n", i,
3524 sc->tx_data[i].num_tx_desc_avail);
3525 device_printf(dev, "TX %d TSO segments = %lu\n", i,
3526 sc->tx_data[i].tso_segments);
3527 device_printf(dev, "TX %d TSO ctx reused = %lu\n", i,
3528 sc->tx_data[i].tso_ctx_reused);
3533 emx_print_hw_stats(struct emx_softc *sc)
3535 device_t dev = sc->dev;
3537 device_printf(dev, "Excessive collisions = %lld\n",
3538 (long long)sc->stats.ecol);
3539 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3540 device_printf(dev, "Symbol errors = %lld\n",
3541 (long long)sc->stats.symerrs);
3543 device_printf(dev, "Sequence errors = %lld\n",
3544 (long long)sc->stats.sec);
3545 device_printf(dev, "Defer count = %lld\n",
3546 (long long)sc->stats.dc);
3547 device_printf(dev, "Missed Packets = %lld\n",
3548 (long long)sc->stats.mpc);
3549 device_printf(dev, "Receive No Buffers = %lld\n",
3550 (long long)sc->stats.rnbc);
3551 /* RLEC is inaccurate on some hardware, calculate our own. */
3552 device_printf(dev, "Receive Length Errors = %lld\n",
3553 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3554 device_printf(dev, "Receive errors = %lld\n",
3555 (long long)sc->stats.rxerrc);
3556 device_printf(dev, "Crc errors = %lld\n",
3557 (long long)sc->stats.crcerrs);
3558 device_printf(dev, "Alignment errors = %lld\n",
3559 (long long)sc->stats.algnerrc);
3560 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3561 (long long)sc->stats.cexterr);
3562 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3563 device_printf(dev, "XON Rcvd = %lld\n",
3564 (long long)sc->stats.xonrxc);
3565 device_printf(dev, "XON Xmtd = %lld\n",
3566 (long long)sc->stats.xontxc);
3567 device_printf(dev, "XOFF Rcvd = %lld\n",
3568 (long long)sc->stats.xoffrxc);
3569 device_printf(dev, "XOFF Xmtd = %lld\n",
3570 (long long)sc->stats.xofftxc);
3571 device_printf(dev, "Good Packets Rcvd = %lld\n",
3572 (long long)sc->stats.gprc);
3573 device_printf(dev, "Good Packets Xmtd = %lld\n",
3574 (long long)sc->stats.gptc);
3578 emx_print_nvm_info(struct emx_softc *sc)
3580 uint16_t eeprom_data;
3583 /* Its a bit crude, but it gets the job done */
3584 kprintf("\nInterface EEPROM Dump:\n");
3585 kprintf("Offset\n0x0000 ");
3586 for (i = 0, j = 0; i < 32; i++, j++) {
3587 if (j == 8) { /* Make the offset block */
3589 kprintf("\n0x00%x0 ",row);
3591 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3592 kprintf("%04x ", eeprom_data);
3598 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3600 struct emx_softc *sc;
3605 error = sysctl_handle_int(oidp, &result, 0, req);
3606 if (error || !req->newptr)
3609 sc = (struct emx_softc *)arg1;
3610 ifp = &sc->arpcom.ac_if;
3612 ifnet_serialize_all(ifp);
3615 emx_print_debug_info(sc);
3618 * This value will cause a hex dump of the
3619 * first 32 16-bit words of the EEPROM to
3623 emx_print_nvm_info(sc);
3625 ifnet_deserialize_all(ifp);
3631 emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3636 error = sysctl_handle_int(oidp, &result, 0, req);
3637 if (error || !req->newptr)
3641 struct emx_softc *sc = (struct emx_softc *)arg1;
3642 struct ifnet *ifp = &sc->arpcom.ac_if;
3644 ifnet_serialize_all(ifp);
3645 emx_print_hw_stats(sc);
3646 ifnet_deserialize_all(ifp);
3652 emx_add_sysctl(struct emx_softc *sc)
3654 struct sysctl_ctx_list *ctx;
3655 struct sysctl_oid *tree;
3656 #if defined(EMX_RSS_DEBUG) || defined(EMX_TSS_DEBUG)
3661 ctx = device_get_sysctl_ctx(sc->dev);
3662 tree = device_get_sysctl_tree(sc->dev);
3663 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3664 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3665 emx_sysctl_debug_info, "I", "Debug Information");
3667 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3668 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3669 emx_sysctl_stats, "I", "Statistics");
3671 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3672 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_data[0].num_rx_desc, 0,
3674 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3675 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_data[0].num_tx_desc, 0,
3678 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3679 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3680 emx_sysctl_int_throttle, "I", "interrupt throttling rate");
3681 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3682 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3683 emx_sysctl_tx_intr_nsegs, "I", "# segments per TX interrupt");
3684 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3685 OID_AUTO, "tx_wreg_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3686 emx_sysctl_tx_wreg_nsegs, "I",
3687 "# segments sent before write to hardware register");
3689 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3690 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD, &sc->rx_ring_cnt, 0,
3692 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3693 OID_AUTO, "tx_ring_cnt", CTLFLAG_RD, &sc->tx_ring_cnt, 0,
3695 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3696 OID_AUTO, "tx_ring_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0,
3697 "# of TX rings used");
3699 #ifdef IFPOLL_ENABLE
3700 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3701 OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
3702 sc, 0, emx_sysctl_npoll_rxoff, "I",
3703 "NPOLLING RX cpu offset");
3704 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3705 OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
3706 sc, 0, emx_sysctl_npoll_txoff, "I",
3707 "NPOLLING TX cpu offset");
3710 #ifdef EMX_RSS_DEBUG
3711 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3712 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3713 0, "RSS debug level");
3714 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3715 ksnprintf(pkt_desc, sizeof(pkt_desc), "rx%d_pkt", i);
3716 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
3717 pkt_desc, CTLFLAG_RW, &sc->rx_data[i].rx_pkts,
3721 #ifdef EMX_TSS_DEBUG
3722 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3723 ksnprintf(pkt_desc, sizeof(pkt_desc), "tx%d_pkt", i);
3724 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
3725 pkt_desc, CTLFLAG_RW, &sc->tx_data[i].tx_pkts,
3732 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3734 struct emx_softc *sc = (void *)arg1;
3735 struct ifnet *ifp = &sc->arpcom.ac_if;
3736 int error, throttle;
3738 throttle = sc->int_throttle_ceil;
3739 error = sysctl_handle_int(oidp, &throttle, 0, req);
3740 if (error || req->newptr == NULL)
3742 if (throttle < 0 || throttle > 1000000000 / 256)
3747 * Set the interrupt throttling rate in 256ns increments,
3748 * recalculate sysctl value assignment to get exact frequency.
3750 throttle = 1000000000 / 256 / throttle;
3752 /* Upper 16bits of ITR is reserved and should be zero */
3753 if (throttle & 0xffff0000)
3757 ifnet_serialize_all(ifp);
3760 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3762 sc->int_throttle_ceil = 0;
3764 if (ifp->if_flags & IFF_RUNNING)
3765 emx_set_itr(sc, throttle);
3767 ifnet_deserialize_all(ifp);
3770 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3771 sc->int_throttle_ceil);
3777 emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3779 struct emx_softc *sc = (void *)arg1;
3780 struct ifnet *ifp = &sc->arpcom.ac_if;
3781 struct emx_txdata *tdata = &sc->tx_data[0];
3784 segs = tdata->tx_intr_nsegs;
3785 error = sysctl_handle_int(oidp, &segs, 0, req);
3786 if (error || req->newptr == NULL)
3791 ifnet_serialize_all(ifp);
3794 * Don't allow tx_intr_nsegs to become:
3795 * o Less the oact_tx_desc
3796 * o Too large that no TX desc will cause TX interrupt to
3797 * be generated (OACTIVE will never recover)
3798 * o Too small that will cause tx_dd[] overflow
3800 if (segs < tdata->oact_tx_desc ||
3801 segs >= tdata->num_tx_desc - tdata->oact_tx_desc ||
3802 segs < tdata->num_tx_desc / EMX_TXDD_SAFE) {
3808 for (i = 0; i < sc->tx_ring_cnt; ++i)
3809 sc->tx_data[i].tx_intr_nsegs = segs;
3812 ifnet_deserialize_all(ifp);
3818 emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3820 struct emx_softc *sc = (void *)arg1;
3821 struct ifnet *ifp = &sc->arpcom.ac_if;
3822 int error, nsegs, i;
3824 nsegs = sc->tx_data[0].tx_wreg_nsegs;
3825 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3826 if (error || req->newptr == NULL)
3829 ifnet_serialize_all(ifp);
3830 for (i = 0; i < sc->tx_ring_cnt; ++i)
3831 sc->tx_data[i].tx_wreg_nsegs =nsegs;
3832 ifnet_deserialize_all(ifp);
3837 #ifdef IFPOLL_ENABLE
3840 emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3842 struct emx_softc *sc = (void *)arg1;
3843 struct ifnet *ifp = &sc->arpcom.ac_if;
3846 off = sc->rx_npoll_off;
3847 error = sysctl_handle_int(oidp, &off, 0, req);
3848 if (error || req->newptr == NULL)
3853 ifnet_serialize_all(ifp);
3854 if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3858 sc->rx_npoll_off = off;
3860 ifnet_deserialize_all(ifp);
3866 emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3868 struct emx_softc *sc = (void *)arg1;
3869 struct ifnet *ifp = &sc->arpcom.ac_if;
3872 off = sc->tx_npoll_off;
3873 error = sysctl_handle_int(oidp, &off, 0, req);
3874 if (error || req->newptr == NULL)
3879 ifnet_serialize_all(ifp);
3880 if (off >= ncpus2 || off % sc->tx_ring_cnt != 0) {
3884 sc->tx_npoll_off = off;
3886 ifnet_deserialize_all(ifp);
3891 #endif /* IFPOLL_ENABLE */
3894 emx_dma_alloc(struct emx_softc *sc)
3899 * Create top level busdma tag
3901 error = bus_dma_tag_create(NULL, 1, 0,
3902 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3904 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3905 0, &sc->parent_dtag);
3907 device_printf(sc->dev, "could not create top level DMA tag\n");
3912 * Allocate transmit descriptors ring and buffers
3914 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3915 error = emx_create_tx_ring(&sc->tx_data[i]);
3917 device_printf(sc->dev,
3918 "Could not setup transmit structures\n");
3924 * Allocate receive descriptors ring and buffers
3926 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3927 error = emx_create_rx_ring(&sc->rx_data[i]);
3929 device_printf(sc->dev,
3930 "Could not setup receive structures\n");
3938 emx_dma_free(struct emx_softc *sc)
3942 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3943 emx_destroy_tx_ring(&sc->tx_data[i],
3944 sc->tx_data[i].num_tx_desc);
3947 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3948 emx_destroy_rx_ring(&sc->rx_data[i],
3949 sc->rx_data[i].num_rx_desc);
3952 /* Free top level busdma tag */
3953 if (sc->parent_dtag != NULL)
3954 bus_dma_tag_destroy(sc->parent_dtag);
3958 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3960 struct emx_softc *sc = ifp->if_softc;
3962 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, slz);
3966 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3968 struct emx_softc *sc = ifp->if_softc;
3970 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, slz);
3974 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3976 struct emx_softc *sc = ifp->if_softc;
3978 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE, slz);
3982 emx_serialize_skipmain(struct emx_softc *sc)
3984 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3988 emx_deserialize_skipmain(struct emx_softc *sc)
3990 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3996 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3997 boolean_t serialized)
3999 struct emx_softc *sc = ifp->if_softc;
4001 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE,
4005 #endif /* INVARIANTS */
4007 #ifdef IFPOLL_ENABLE
4010 emx_npoll_status(struct ifnet *ifp)
4012 struct emx_softc *sc = ifp->if_softc;
4015 ASSERT_SERIALIZED(&sc->main_serialize);
4017 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
4018 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4019 callout_stop(&sc->timer);
4020 sc->hw.mac.get_link_status = 1;
4021 emx_update_link_status(sc);
4022 callout_reset(&sc->timer, hz, emx_timer, sc);
4027 emx_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
4029 struct emx_txdata *tdata = arg;
4031 ASSERT_SERIALIZED(&tdata->tx_serialize);
4034 if (!ifsq_is_empty(tdata->ifsq))
4035 ifsq_devstart(tdata->ifsq);
4039 emx_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
4041 struct emx_rxdata *rdata = arg;
4043 ASSERT_SERIALIZED(&rdata->rx_serialize);
4045 emx_rxeof(rdata, cycle);
4049 emx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
4051 struct emx_softc *sc = ifp->if_softc;
4054 ASSERT_IFNET_SERIALIZED_ALL(ifp);
4059 info->ifpi_status.status_func = emx_npoll_status;
4060 info->ifpi_status.serializer = &sc->main_serialize;
4062 txr_cnt = emx_get_txring_inuse(sc, TRUE);
4063 off = sc->tx_npoll_off;
4064 for (i = 0; i < txr_cnt; ++i) {
4065 struct emx_txdata *tdata = &sc->tx_data[i];
4068 KKASSERT(idx < ncpus2);
4069 info->ifpi_tx[idx].poll_func = emx_npoll_tx;
4070 info->ifpi_tx[idx].arg = tdata;
4071 info->ifpi_tx[idx].serializer = &tdata->tx_serialize;
4072 ifsq_set_cpuid(tdata->ifsq, idx);
4075 off = sc->rx_npoll_off;
4076 for (i = 0; i < sc->rx_ring_cnt; ++i) {
4077 struct emx_rxdata *rdata = &sc->rx_data[i];
4080 KKASSERT(idx < ncpus2);
4081 info->ifpi_rx[idx].poll_func = emx_npoll_rx;
4082 info->ifpi_rx[idx].arg = rdata;
4083 info->ifpi_rx[idx].serializer = &rdata->rx_serialize;
4086 if (ifp->if_flags & IFF_RUNNING) {
4087 if (txr_cnt == sc->tx_ring_inuse)
4088 emx_disable_intr(sc);
4093 for (i = 0; i < sc->tx_ring_cnt; ++i) {
4094 struct emx_txdata *tdata = &sc->tx_data[i];
4096 ifsq_set_cpuid(tdata->ifsq,
4097 rman_get_cpuid(sc->intr_res));
4100 if (ifp->if_flags & IFF_RUNNING) {
4101 txr_cnt = emx_get_txring_inuse(sc, FALSE);
4102 if (txr_cnt == sc->tx_ring_inuse)
4103 emx_enable_intr(sc);
4110 #endif /* IFPOLL_ENABLE */
4113 emx_set_itr(struct emx_softc *sc, uint32_t itr)
4115 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr);
4116 if (sc->hw.mac.type == e1000_82574) {
4120 * When using MSIX interrupts we need to
4121 * throttle using the EITR register
4123 for (i = 0; i < 4; ++i)
4124 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr);
4129 * Disable the L0s, 82574L Errata #20
4132 emx_disable_aspm(struct emx_softc *sc)
4134 uint16_t link_cap, link_ctrl, disable;
4135 uint8_t pcie_ptr, reg;
4136 device_t dev = sc->dev;
4138 switch (sc->hw.mac.type) {
4143 * 82573 specification update
4144 * errata #8 disable L0s
4145 * errata #41 disable L1
4147 * 82571/82572 specification update
4148 # errata #13 disable L1
4149 * errata #68 disable L0s
4151 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1;
4156 * 82574 specification update errata #20
4158 * There is no need to disable L1
4160 disable = PCIEM_LNKCTL_ASPM_L0S;
4167 pcie_ptr = pci_get_pciecap_ptr(dev);
4171 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2);
4172 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0)
4176 if_printf(&sc->arpcom.ac_if, "disable ASPM %#02x\n", disable);
4178 reg = pcie_ptr + PCIER_LINKCTRL;
4179 link_ctrl = pci_read_config(dev, reg, 2);
4180 link_ctrl &= ~disable;
4181 pci_write_config(dev, reg, link_ctrl, 2);
4185 emx_tso_pullup(struct emx_txdata *tdata, struct mbuf **mp)
4187 int iphlen, hoff, thoff, ex = 0;
4192 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4194 iphlen = m->m_pkthdr.csum_iphlen;
4195 thoff = m->m_pkthdr.csum_thlen;
4196 hoff = m->m_pkthdr.csum_lhlen;
4198 KASSERT(iphlen > 0, ("invalid ip hlen"));
4199 KASSERT(thoff > 0, ("invalid tcp hlen"));
4200 KASSERT(hoff > 0, ("invalid ether hlen"));
4202 if (tdata->tx_flags & EMX_TXFLAG_TSO_PULLEX)
4205 if (m->m_len < hoff + iphlen + thoff + ex) {
4206 m = m_pullup(m, hoff + iphlen + thoff + ex);
4213 ip = mtodoff(m, struct ip *, hoff);
4220 emx_tso_setup(struct emx_txdata *tdata, struct mbuf *mp,
4221 uint32_t *txd_upper, uint32_t *txd_lower)
4223 struct e1000_context_desc *TXD;
4224 int hoff, iphlen, thoff, hlen;
4225 int mss, pktlen, curr_txd;
4227 #ifdef EMX_TSO_DEBUG
4228 tdata->tso_segments++;
4231 iphlen = mp->m_pkthdr.csum_iphlen;
4232 thoff = mp->m_pkthdr.csum_thlen;
4233 hoff = mp->m_pkthdr.csum_lhlen;
4234 mss = mp->m_pkthdr.tso_segsz;
4235 pktlen = mp->m_pkthdr.len;
4237 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 &&
4238 tdata->csum_flags == CSUM_TSO &&
4239 tdata->csum_iphlen == iphlen &&
4240 tdata->csum_lhlen == hoff &&
4241 tdata->csum_thlen == thoff &&
4242 tdata->csum_mss == mss &&
4243 tdata->csum_pktlen == pktlen) {
4244 *txd_upper = tdata->csum_txd_upper;
4245 *txd_lower = tdata->csum_txd_lower;
4246 #ifdef EMX_TSO_DEBUG
4247 tdata->tso_ctx_reused++;
4251 hlen = hoff + iphlen + thoff;
4254 * Setup a new TSO context.
4257 curr_txd = tdata->next_avail_tx_desc;
4258 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd];
4260 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
4261 E1000_TXD_DTYP_D | /* Data descr type */
4262 E1000_TXD_CMD_TSE; /* Do TSE on this packet */
4264 /* IP and/or TCP header checksum calculation and insertion. */
4265 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8;
4268 * Start offset for header checksum calculation.
4269 * End offset for header checksum calculation.
4270 * Offset of place put the checksum.
4272 TXD->lower_setup.ip_fields.ipcss = hoff;
4273 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1);
4274 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum);
4277 * Start offset for payload checksum calculation.
4278 * End offset for payload checksum calculation.
4279 * Offset of place to put the checksum.
4281 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen;
4282 TXD->upper_setup.tcp_fields.tucse = 0;
4283 TXD->upper_setup.tcp_fields.tucso =
4284 hoff + iphlen + offsetof(struct tcphdr, th_sum);
4287 * Payload size per packet w/o any headers.
4288 * Length of all headers up to payload.
4290 TXD->tcp_seg_setup.fields.mss = htole16(mss);
4291 TXD->tcp_seg_setup.fields.hdr_len = hlen;
4292 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS |
4293 E1000_TXD_CMD_DEXT | /* Extended descr */
4294 E1000_TXD_CMD_TSE | /* TSE context */
4295 E1000_TXD_CMD_IP | /* Do IP csum */
4296 E1000_TXD_CMD_TCP | /* Do TCP checksum */
4297 (pktlen - hlen)); /* Total len */
4299 /* Save the information for this TSO context */
4300 tdata->csum_flags = CSUM_TSO;
4301 tdata->csum_lhlen = hoff;
4302 tdata->csum_iphlen = iphlen;
4303 tdata->csum_thlen = thoff;
4304 tdata->csum_mss = mss;
4305 tdata->csum_pktlen = pktlen;
4306 tdata->csum_txd_upper = *txd_upper;
4307 tdata->csum_txd_lower = *txd_lower;
4309 if (++curr_txd == tdata->num_tx_desc)
4312 KKASSERT(tdata->num_tx_desc_avail > 0);
4313 tdata->num_tx_desc_avail--;
4315 tdata->next_avail_tx_desc = curr_txd;
4320 emx_get_txring_inuse(const struct emx_softc *sc, boolean_t polling)
4323 return sc->tx_ring_cnt;