2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/i386/i386/Attic/mp_machdep.c,v 1.18 2003/11/03 22:50:11 dillon Exp $
31 #include "opt_user_ldt.h"
34 #include <machine/smptests.h>
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/kernel.h>
42 #include <sys/sysctl.h>
43 #include <sys/malloc.h>
44 #include <sys/memrange.h>
46 #include <sys/dkstat.h>
48 #include <sys/cons.h> /* cngetc() */
51 #include <vm/vm_param.h>
53 #include <vm/vm_kern.h>
54 #include <vm/vm_extern.h>
56 #include <vm/vm_map.h>
62 #include <machine/smp.h>
63 #include <machine/apic.h>
64 #include <machine/atomic.h>
65 #include <machine/cpufunc.h>
66 #include <machine/mpapic.h>
67 #include <machine/psl.h>
68 #include <machine/segments.h>
69 #include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */
70 #include <machine/tss.h>
71 #include <machine/specialreg.h>
72 #include <machine/globaldata.h>
75 #include <machine/md_var.h> /* setidt() */
76 #include <i386/isa/icu.h> /* IPIs */
77 #include <i386/isa/intr_machdep.h> /* IPIs */
80 #if defined(TEST_DEFAULT_CONFIG)
81 #define MPFPS_MPFB1 TEST_DEFAULT_CONFIG
83 #define MPFPS_MPFB1 mpfps->mpfb1
84 #endif /* TEST_DEFAULT_CONFIG */
86 #define WARMBOOT_TARGET 0
87 #define WARMBOOT_OFF (KERNBASE + 0x0467)
88 #define WARMBOOT_SEG (KERNBASE + 0x0469)
91 #define BIOS_BASE (0xe8000)
92 #define BIOS_SIZE (0x18000)
94 #define BIOS_BASE (0xf0000)
95 #define BIOS_SIZE (0x10000)
97 #define BIOS_COUNT (BIOS_SIZE/4)
99 #define CMOS_REG (0x70)
100 #define CMOS_DATA (0x71)
101 #define BIOS_RESET (0x0f)
102 #define BIOS_WARM (0x0a)
104 #define PROCENTRY_FLAG_EN 0x01
105 #define PROCENTRY_FLAG_BP 0x02
106 #define IOAPICENTRY_FLAG_EN 0x01
109 /* MP Floating Pointer Structure */
110 typedef struct MPFPS {
123 /* MP Configuration Table Header */
124 typedef struct MPCTH {
126 u_short base_table_length;
130 u_char product_id[12];
131 void *oem_table_pointer;
132 u_short oem_table_size;
135 u_short extended_table_length;
136 u_char extended_table_checksum;
141 typedef struct PROCENTRY {
146 u_long cpu_signature;
147 u_long feature_flags;
152 typedef struct BUSENTRY {
158 typedef struct IOAPICENTRY {
164 } *io_apic_entry_ptr;
166 typedef struct INTENTRY {
176 /* descriptions of MP basetable entries */
177 typedef struct BASETABLE_ENTRY {
184 * this code MUST be enabled here and in mpboot.s.
185 * it follows the very early stages of AP boot by placing values in CMOS ram.
186 * it NORMALLY will never be needed and thus the primitive method for enabling.
189 #if defined(CHECK_POINTS) && !defined(PC98)
190 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
191 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
193 #define CHECK_INIT(D); \
194 CHECK_WRITE(0x34, (D)); \
195 CHECK_WRITE(0x35, (D)); \
196 CHECK_WRITE(0x36, (D)); \
197 CHECK_WRITE(0x37, (D)); \
198 CHECK_WRITE(0x38, (D)); \
199 CHECK_WRITE(0x39, (D));
201 #define CHECK_PRINT(S); \
202 printf("%s: %d, %d, %d, %d, %d, %d\n", \
211 #else /* CHECK_POINTS */
213 #define CHECK_INIT(D)
214 #define CHECK_PRINT(S)
216 #endif /* CHECK_POINTS */
219 * Values to send to the POST hardware.
221 #define MP_BOOTADDRESS_POST 0x10
222 #define MP_PROBE_POST 0x11
223 #define MPTABLE_PASS1_POST 0x12
225 #define MP_START_POST 0x13
226 #define MP_ENABLE_POST 0x14
227 #define MPTABLE_PASS2_POST 0x15
229 #define START_ALL_APS_POST 0x16
230 #define INSTALL_AP_TRAMP_POST 0x17
231 #define START_AP_POST 0x18
233 #define MP_ANNOUNCE_POST 0x19
236 static int need_hyperthreading_fixup;
237 static u_int logical_cpus;
240 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
241 int current_postcode;
243 /** XXX FIXME: what system files declare these??? */
244 extern struct region_descriptor r_gdt, r_idt;
246 int bsp_apic_ready = 0; /* flags useability of BSP apic */
247 int mp_naps; /* # of Applications processors */
248 int mp_nbusses; /* # of busses */
249 int mp_napics; /* # of IO APICs */
250 int boot_cpu_id; /* designated BSP */
251 vm_offset_t cpu_apic_address;
252 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
255 u_int32_t cpu_apic_versions[MAXCPU];
256 u_int32_t *io_apic_versions;
258 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
260 #ifdef APIC_INTR_REORDER
262 volatile int *location;
264 } apic_isrbit_location[32];
269 * APIC ID logical/physical mapping structures.
270 * We oversize these to simplify boot-time config.
272 int cpu_num_to_apic_id[NAPICID];
273 int io_num_to_apic_id[NAPICID];
274 int apic_id_to_logical[NAPICID];
277 /* Bitmap of all available CPUs */
280 /* AP uses this during bootstrap. Do not staticize. */
284 /* Hotwire a 0->4MB V==P mapping */
285 extern pt_entry_t *KPTphys;
287 /* SMP page table page */
288 extern pt_entry_t *SMPpt;
290 struct pcb stoppcbs[MAXCPU];
292 int smp_started; /* has the system started? */
295 * Local data and functions.
298 static int mp_capable;
299 static u_int boot_address;
300 static u_int base_memory;
302 static int picmode; /* 0: virtual wire mode, 1: PIC mode */
303 static mpfps_t mpfps;
304 static int search_for_sig(u_int32_t target, int count);
305 static void mp_enable(u_int boot_addr);
308 static void mptable_hyperthread_fixup(u_int id_mask);
310 static void mptable_pass1(void);
311 static int mptable_pass2(void);
312 static void default_mp_table(int type);
313 static void fix_mp_table(void);
314 static void setup_apic_irq_mapping(void);
315 static int start_all_aps(u_int boot_addr);
316 static void install_ap_tramp(u_int boot_addr);
317 static int start_ap(int logicalCpu, u_int boot_addr);
318 static int apic_int_is_bus_type(int intr, int bus_type);
321 * Calculate usable address in base memory for AP trampoline code.
324 mp_bootaddress(u_int basemem)
326 POSTCODE(MP_BOOTADDRESS_POST);
328 base_memory = basemem * 1024; /* convert to bytes */
330 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
331 if ((base_memory - boot_address) < bootMP_size)
332 boot_address -= 4096; /* not enough, lower by 4k */
339 * Look for an Intel MP spec table (ie, SMP capable hardware).
348 POSTCODE(MP_PROBE_POST);
350 /* see if EBDA exists */
351 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
352 /* search first 1K of EBDA */
353 target = (u_int32_t) (segment << 4);
354 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
357 /* last 1K of base memory, effective 'top of base' passed in */
358 target = (u_int32_t) (base_memory - 0x400);
359 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
363 /* search the BIOS */
364 target = (u_int32_t) BIOS_BASE;
365 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
374 /* calculate needed resources */
378 /* flag fact that we are running multiple processors */
385 * Startup the SMP processors.
390 POSTCODE(MP_START_POST);
392 /* look for MP capable motherboard */
394 mp_enable(boot_address);
396 panic("MP hardware not found!");
401 * Print various information about the SMP system hardware and setup.
408 POSTCODE(MP_ANNOUNCE_POST);
410 printf("FreeBSD/SMP: Multiprocessor motherboard\n");
411 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
412 printf(", version: 0x%08x", cpu_apic_versions[0]);
413 printf(", at 0x%08x\n", cpu_apic_address);
414 for (x = 1; x <= mp_naps; ++x) {
415 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
416 printf(", version: 0x%08x", cpu_apic_versions[x]);
417 printf(", at 0x%08x\n", cpu_apic_address);
421 for (x = 0; x < mp_napics; ++x) {
422 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
423 printf(", version: 0x%08x", io_apic_versions[x]);
424 printf(", at 0x%08x\n", io_apic_address[x]);
427 printf(" Warning: APIC I/O disabled\n");
432 * AP cpu's call this to sync up protected mode.
438 int x, myid = bootAP;
440 struct mdglobaldata *md;
442 gdt_segs[GPRIV_SEL].ssd_base = (int) &CPU_prvspace[myid];
443 gdt_segs[GPROC0_SEL].ssd_base =
444 (int) &CPU_prvspace[myid].mdglobaldata.gd_common_tss;
445 CPU_prvspace[myid].mdglobaldata.mi.gd_prvspace = &CPU_prvspace[myid];
447 for (x = 0; x < NGDT; x++) {
448 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
451 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
452 r_gdt.rd_base = (int) &gdt[myid * NGDT];
453 lgdt(&r_gdt); /* does magic intra-segment return */
459 mdcpu->gd_currentldt = _default_ldt;
462 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
463 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
467 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
468 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
469 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
470 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
471 md->gd_common_tssd = *md->gd_tss_gdt;
475 * Set to a known state:
476 * Set by mpboot.s: CR0_PG, CR0_PE
477 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
480 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
489 * Final configuration of the BSP's local APIC:
490 * - disable 'pic mode'.
491 * - disable 'virtual wire mode'.
495 bsp_apic_configure(void)
500 /* leave 'pic mode' if necessary */
502 outb(0x22, 0x70); /* select IMCR */
503 byte = inb(0x23); /* current contents */
504 byte |= 0x01; /* mask external INTR */
505 outb(0x23, byte); /* disconnect 8259s/NMI */
508 /* mask lint0 (the 8259 'virtual wire' connection) */
509 temp = lapic.lvt_lint0;
510 temp |= APIC_LVT_M; /* set the mask */
511 lapic.lvt_lint0 = temp;
513 /* setup lint1 to handle NMI */
514 temp = lapic.lvt_lint1;
515 temp &= ~APIC_LVT_M; /* clear the mask */
516 lapic.lvt_lint1 = temp;
519 apic_dump("bsp_apic_configure()");
524 /*******************************************************************
525 * local functions and data
529 * start the SMP system
532 mp_enable(u_int boot_addr)
540 POSTCODE(MP_ENABLE_POST);
542 /* turn on 4MB of V == P addressing so we can get to MP table */
543 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
546 /* examine the MP table for needed info, uses physical addresses */
552 /* can't process default configs till the CPU APIC is pmapped */
556 /* post scan cleanup */
558 setup_apic_irq_mapping();
562 /* fill the LOGICAL io_apic_versions table */
563 for (apic = 0; apic < mp_napics; ++apic) {
564 ux = io_apic_read(apic, IOAPIC_VER);
565 io_apic_versions[apic] = ux;
566 io_apic_set_id(apic, IO_TO_ID(apic));
569 /* program each IO APIC in the system */
570 for (apic = 0; apic < mp_napics; ++apic)
571 if (io_apic_setup(apic) < 0)
572 panic("IO APIC setup failure");
574 /* install a 'Spurious INTerrupt' vector */
575 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
576 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
578 /* install an inter-CPU IPI for TLB invalidation */
579 setidt(XINVLTLB_OFFSET, Xinvltlb,
580 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
584 /* install an inter-CPU IPI for reading processor state */
585 setidt(XCPUCHECKSTATE_OFFSET, Xcpucheckstate,
586 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
590 /* install an inter-CPU IPI for IPIQ messaging */
591 setidt(XIPIQ_OFFSET, Xipiq,
592 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
594 /* install an inter-CPU IPI for all-CPU rendezvous */
595 setidt(XRENDEZVOUS_OFFSET, Xrendezvous,
596 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
599 /* install an inter-CPU IPI for forcing an additional software trap */
600 setidt(XCPUAST_OFFSET, Xcpuast,
601 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
603 /* install an inter-CPU IPI for interrupt forwarding */
604 setidt(XFORWARD_IRQ_OFFSET, Xforward_irq,
605 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
608 /* install an inter-CPU IPI for CPU stop/restart */
609 setidt(XCPUSTOP_OFFSET, Xcpustop,
610 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
612 #if defined(TEST_TEST1)
613 /* install a "fake hardware INTerrupt" vector */
614 setidt(XTEST1_OFFSET, Xtest1,
615 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
616 #endif /** TEST_TEST1 */
620 /* start each Application Processor */
621 start_all_aps(boot_addr);
626 * look for the MP spec signature
629 /* string defined by the Intel MP Spec as identifying the MP table */
630 #define MP_SIG 0x5f504d5f /* _MP_ */
631 #define NEXT(X) ((X) += 4)
633 search_for_sig(u_int32_t target, int count)
636 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
638 for (x = 0; x < count; NEXT(x))
639 if (addr[x] == MP_SIG)
640 /* make array index a byte index */
641 return (target + (x * sizeof(u_int32_t)));
647 static basetable_entry basetable_entry_types[] =
649 {0, 20, "Processor"},
656 typedef struct BUSDATA {
658 enum busTypes bus_type;
661 typedef struct INTDATA {
671 typedef struct BUSTYPENAME {
676 static bus_type_name bus_type_table[] =
682 {UNKNOWN_BUSTYPE, "---"},
685 {UNKNOWN_BUSTYPE, "---"},
686 {UNKNOWN_BUSTYPE, "---"},
687 {UNKNOWN_BUSTYPE, "---"},
688 {UNKNOWN_BUSTYPE, "---"},
689 {UNKNOWN_BUSTYPE, "---"},
691 {UNKNOWN_BUSTYPE, "---"},
692 {UNKNOWN_BUSTYPE, "---"},
693 {UNKNOWN_BUSTYPE, "---"},
694 {UNKNOWN_BUSTYPE, "---"},
696 {UNKNOWN_BUSTYPE, "---"}
698 /* from MP spec v1.4, table 5-1 */
699 static int default_data[7][5] =
701 /* nbus, id0, type0, id1, type1 */
702 {1, 0, ISA, 255, 255},
703 {1, 0, EISA, 255, 255},
704 {1, 0, EISA, 255, 255},
705 {1, 0, MCA, 255, 255},
707 {2, 0, EISA, 1, PCI},
713 static bus_datum *bus_data;
715 /* the IO INT data, one entry per possible APIC INTerrupt */
716 static io_int *io_apic_ints;
720 static int processor_entry (proc_entry_ptr entry, int cpu);
721 static int bus_entry (bus_entry_ptr entry, int bus);
722 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
723 static int int_entry (int_entry_ptr entry, int intr);
724 static int lookup_bus_type (char *name);
728 * 1st pass on motherboard's Intel MP specification table.
734 * cpu_apic_address (common to all CPUs)
754 POSTCODE(MPTABLE_PASS1_POST);
756 /* clear various tables */
757 for (x = 0; x < NAPICID; ++x) {
758 io_apic_address[x] = ~0; /* IO APIC address table */
761 /* init everything to empty */
770 /* check for use of 'default' configuration */
771 if (MPFPS_MPFB1 != 0) {
772 /* use default addresses */
773 cpu_apic_address = DEFAULT_APIC_BASE;
774 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
776 /* fill in with defaults */
777 mp_naps = 2; /* includes BSP */
778 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0];
785 if ((cth = mpfps->pap) == 0)
786 panic("MP Configuration Table Header MISSING!");
788 cpu_apic_address = (vm_offset_t) cth->apic_address;
790 /* walk the table, recording info of interest */
791 totalSize = cth->base_table_length - sizeof(struct MPCTH);
792 position = (u_char *) cth + sizeof(struct MPCTH);
793 count = cth->entry_count;
796 switch (type = *(u_char *) position) {
797 case 0: /* processor_entry */
798 if (((proc_entry_ptr)position)->cpu_flags
799 & PROCENTRY_FLAG_EN) {
803 ((proc_entry_ptr)position)->apic_id;
807 case 1: /* bus_entry */
810 case 2: /* io_apic_entry */
811 if (((io_apic_entry_ptr)position)->apic_flags
812 & IOAPICENTRY_FLAG_EN)
813 io_apic_address[mp_napics++] =
814 (vm_offset_t)((io_apic_entry_ptr)
815 position)->apic_address;
817 case 3: /* int_entry */
820 case 4: /* int_entry */
823 panic("mpfps Base Table HOSED!");
827 totalSize -= basetable_entry_types[type].length;
828 (u_char*)position += basetable_entry_types[type].length;
832 /* qualify the numbers */
833 if (mp_naps > MAXCPU) {
834 printf("Warning: only using %d of %d available CPUs!\n",
840 /* See if we need to fixup HT logical CPUs. */
841 mptable_hyperthread_fixup(id_mask);
846 * This is also used as a counter while starting the APs.
850 --mp_naps; /* subtract the BSP */
855 * 2nd pass on motherboard's Intel MP specification table.
859 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
860 * CPU_TO_ID(N), logical CPU to APIC ID table
861 * IO_TO_ID(N), logical IO to APIC ID table
869 struct PROCENTRY proc;
877 int apic, bus, cpu, intr;
881 POSTCODE(MPTABLE_PASS2_POST);
884 /* Initialize fake proc entry for use with HT fixup. */
885 bzero(&proc, sizeof(proc));
887 proc.cpu_flags = PROCENTRY_FLAG_EN;
890 pgeflag = 0; /* XXX - Not used under SMP yet. */
892 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
894 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
896 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + 1),
898 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
901 bzero(ioapic, sizeof(ioapic_t *) * mp_napics);
903 for (i = 0; i < mp_napics; i++) {
904 for (j = 0; j < mp_napics; j++) {
905 /* same page frame as a previous IO apic? */
906 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) ==
907 (io_apic_address[i] & PG_FRAME)) {
908 ioapic[i] = (ioapic_t *)((u_int)CPU_prvspace
909 + (NPTEPG-2-j) * PAGE_SIZE
910 + (io_apic_address[i] & PAGE_MASK));
913 /* use this slot if available */
914 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 0) {
915 SMPpt[NPTEPG-2-j] = (pt_entry_t)(PG_V | PG_RW |
916 pgeflag | (io_apic_address[i] & PG_FRAME));
917 ioapic[i] = (ioapic_t *)((u_int)CPU_prvspace
918 + (NPTEPG-2-j) * PAGE_SIZE
919 + (io_apic_address[i] & PAGE_MASK));
925 /* clear various tables */
926 for (x = 0; x < NAPICID; ++x) {
927 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
928 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
929 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
932 /* clear bus data table */
933 for (x = 0; x < mp_nbusses; ++x)
934 bus_data[x].bus_id = 0xff;
936 /* clear IO APIC INT table */
937 for (x = 0; x < (nintrs + 1); ++x) {
938 io_apic_ints[x].int_type = 0xff;
939 io_apic_ints[x].int_vector = 0xff;
942 /* setup the cpu/apic mapping arrays */
945 /* record whether PIC or virtual-wire mode */
946 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0;
948 /* check for use of 'default' configuration */
949 if (MPFPS_MPFB1 != 0)
950 return MPFPS_MPFB1; /* return default configuration type */
952 if ((cth = mpfps->pap) == 0)
953 panic("MP Configuration Table Header MISSING!");
955 /* walk the table, recording info of interest */
956 totalSize = cth->base_table_length - sizeof(struct MPCTH);
957 position = (u_char *) cth + sizeof(struct MPCTH);
958 count = cth->entry_count;
959 apic = bus = intr = 0;
960 cpu = 1; /* pre-count the BSP */
963 switch (type = *(u_char *) position) {
965 if (processor_entry(position, cpu))
969 if (need_hyperthreading_fixup) {
971 * Create fake mptable processor entries
972 * and feed them to processor_entry() to
973 * enumerate the logical CPUs.
975 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
976 for (i = 1; i < logical_cpus; i++) {
978 (void)processor_entry(&proc, cpu);
985 if (bus_entry(position, bus))
989 if (io_apic_entry(position, apic))
993 if (int_entry(position, intr))
997 /* int_entry(position); */
1000 panic("mpfps Base Table HOSED!");
1004 totalSize -= basetable_entry_types[type].length;
1005 (u_char *) position += basetable_entry_types[type].length;
1008 if (boot_cpu_id == -1)
1009 panic("NO BSP found!");
1011 /* report fact that its NOT a default configuration */
1017 * Check if we should perform a hyperthreading "fix-up" to
1018 * enumerate any logical CPU's that aren't already listed
1021 * XXX: We assume that all of the physical CPUs in the
1022 * system have the same number of logical CPUs.
1024 * XXX: We assume that APIC ID's are allocated such that
1025 * the APIC ID's for a physical processor are aligned
1026 * with the number of logical CPU's in the processor.
1029 mptable_hyperthread_fixup(u_int id_mask)
1033 /* Nothing to do if there is no HTT support. */
1034 if ((cpu_feature & CPUID_HTT) == 0)
1036 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1037 if (logical_cpus <= 1)
1041 * For each APIC ID of a CPU that is set in the mask,
1042 * scan the other candidate APIC ID's for this
1043 * physical processor. If any of those ID's are
1044 * already in the table, then kill the fixup.
1046 for (id = 0; id <= MAXCPU; id++) {
1047 if ((id_mask & 1 << id) == 0)
1049 /* First, make sure we are on a logical_cpus boundary. */
1050 if (id % logical_cpus != 0)
1052 for (i = id + 1; i < id + logical_cpus; i++)
1053 if ((id_mask & 1 << i) != 0)
1058 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1059 * mp_naps right now.
1061 need_hyperthreading_fixup = 1;
1062 mp_naps *= logical_cpus;
1067 assign_apic_irq(int apic, int intpin, int irq)
1071 if (int_to_apicintpin[irq].ioapic != -1)
1072 panic("assign_apic_irq: inconsistent table");
1074 int_to_apicintpin[irq].ioapic = apic;
1075 int_to_apicintpin[irq].int_pin = intpin;
1076 int_to_apicintpin[irq].apic_address = ioapic[apic];
1077 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1079 for (x = 0; x < nintrs; x++) {
1080 if ((io_apic_ints[x].int_type == 0 ||
1081 io_apic_ints[x].int_type == 3) &&
1082 io_apic_ints[x].int_vector == 0xff &&
1083 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1084 io_apic_ints[x].dst_apic_int == intpin)
1085 io_apic_ints[x].int_vector = irq;
1090 revoke_apic_irq(int irq)
1096 if (int_to_apicintpin[irq].ioapic == -1)
1097 panic("revoke_apic_irq: inconsistent table");
1099 oldapic = int_to_apicintpin[irq].ioapic;
1100 oldintpin = int_to_apicintpin[irq].int_pin;
1102 int_to_apicintpin[irq].ioapic = -1;
1103 int_to_apicintpin[irq].int_pin = 0;
1104 int_to_apicintpin[irq].apic_address = NULL;
1105 int_to_apicintpin[irq].redirindex = 0;
1107 for (x = 0; x < nintrs; x++) {
1108 if ((io_apic_ints[x].int_type == 0 ||
1109 io_apic_ints[x].int_type == 3) &&
1110 io_apic_ints[x].int_vector != 0xff &&
1111 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1112 io_apic_ints[x].dst_apic_int == oldintpin)
1113 io_apic_ints[x].int_vector = 0xff;
1119 allocate_apic_irq(int intr)
1125 if (io_apic_ints[intr].int_vector != 0xff)
1126 return; /* Interrupt handler already assigned */
1128 if (io_apic_ints[intr].int_type != 0 &&
1129 (io_apic_ints[intr].int_type != 3 ||
1130 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1131 io_apic_ints[intr].dst_apic_int == 0)))
1132 return; /* Not INT or ExtInt on != (0, 0) */
1135 while (irq < APIC_INTMAPSIZE &&
1136 int_to_apicintpin[irq].ioapic != -1)
1139 if (irq >= APIC_INTMAPSIZE)
1140 return; /* No free interrupt handlers */
1142 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1143 intpin = io_apic_ints[intr].dst_apic_int;
1145 assign_apic_irq(apic, intpin, irq);
1146 io_apic_setup_intpin(apic, intpin);
1151 swap_apic_id(int apic, int oldid, int newid)
1158 return; /* Nothing to do */
1160 printf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1161 apic, oldid, newid);
1163 /* Swap physical APIC IDs in interrupt entries */
1164 for (x = 0; x < nintrs; x++) {
1165 if (io_apic_ints[x].dst_apic_id == oldid)
1166 io_apic_ints[x].dst_apic_id = newid;
1167 else if (io_apic_ints[x].dst_apic_id == newid)
1168 io_apic_ints[x].dst_apic_id = oldid;
1171 /* Swap physical APIC IDs in IO_TO_ID mappings */
1172 for (oapic = 0; oapic < mp_napics; oapic++)
1173 if (IO_TO_ID(oapic) == newid)
1176 if (oapic < mp_napics) {
1177 printf("Changing APIC ID for IO APIC #%d from "
1178 "%d to %d in MP table\n",
1179 oapic, newid, oldid);
1180 IO_TO_ID(oapic) = oldid;
1182 IO_TO_ID(apic) = newid;
1187 fix_id_to_io_mapping(void)
1191 for (x = 0; x < NAPICID; x++)
1194 for (x = 0; x <= mp_naps; x++)
1195 if (CPU_TO_ID(x) < NAPICID)
1196 ID_TO_IO(CPU_TO_ID(x)) = x;
1198 for (x = 0; x < mp_napics; x++)
1199 if (IO_TO_ID(x) < NAPICID)
1200 ID_TO_IO(IO_TO_ID(x)) = x;
1205 first_free_apic_id(void)
1209 for (freeid = 0; freeid < NAPICID; freeid++) {
1210 for (x = 0; x <= mp_naps; x++)
1211 if (CPU_TO_ID(x) == freeid)
1215 for (x = 0; x < mp_napics; x++)
1216 if (IO_TO_ID(x) == freeid)
1227 io_apic_id_acceptable(int apic, int id)
1229 int cpu; /* Logical CPU number */
1230 int oapic; /* Logical IO APIC number for other IO APIC */
1233 return 0; /* Out of range */
1235 for (cpu = 0; cpu <= mp_naps; cpu++)
1236 if (CPU_TO_ID(cpu) == id)
1237 return 0; /* Conflict with CPU */
1239 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1240 if (IO_TO_ID(oapic) == id)
1241 return 0; /* Conflict with other APIC */
1243 return 1; /* ID is acceptable for IO APIC */
1248 * parse an Intel MP specification table
1255 int bus_0 = 0; /* Stop GCC warning */
1256 int bus_pci = 0; /* Stop GCC warning */
1258 int apic; /* IO APIC unit number */
1259 int freeid; /* Free physical APIC ID */
1260 int physid; /* Current physical IO APIC ID */
1263 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1264 * did it wrong. The MP spec says that when more than 1 PCI bus
1265 * exists the BIOS must begin with bus entries for the PCI bus and use
1266 * actual PCI bus numbering. This implies that when only 1 PCI bus
1267 * exists the BIOS can choose to ignore this ordering, and indeed many
1268 * MP motherboards do ignore it. This causes a problem when the PCI
1269 * sub-system makes requests of the MP sub-system based on PCI bus
1270 * numbers. So here we look for the situation and renumber the
1271 * busses and associated INTs in an effort to "make it right".
1274 /* find bus 0, PCI bus, count the number of PCI busses */
1275 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1276 if (bus_data[x].bus_id == 0) {
1279 if (bus_data[x].bus_type == PCI) {
1285 * bus_0 == slot of bus with ID of 0
1286 * bus_pci == slot of last PCI bus encountered
1289 /* check the 1 PCI bus case for sanity */
1290 /* if it is number 0 all is well */
1291 if (num_pci_bus == 1 &&
1292 bus_data[bus_pci].bus_id != 0) {
1294 /* mis-numbered, swap with whichever bus uses slot 0 */
1296 /* swap the bus entry types */
1297 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1298 bus_data[bus_0].bus_type = PCI;
1300 /* swap each relavant INTerrupt entry */
1301 id = bus_data[bus_pci].bus_id;
1302 for (x = 0; x < nintrs; ++x) {
1303 if (io_apic_ints[x].src_bus_id == id) {
1304 io_apic_ints[x].src_bus_id = 0;
1306 else if (io_apic_ints[x].src_bus_id == 0) {
1307 io_apic_ints[x].src_bus_id = id;
1312 /* Assign IO APIC IDs.
1314 * First try the existing ID. If a conflict is detected, try
1315 * the ID in the MP table. If a conflict is still detected, find
1318 * We cannot use the ID_TO_IO table before all conflicts has been
1319 * resolved and the table has been corrected.
1321 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1323 /* First try to use the value set by the BIOS */
1324 physid = io_apic_get_id(apic);
1325 if (io_apic_id_acceptable(apic, physid)) {
1326 if (IO_TO_ID(apic) != physid)
1327 swap_apic_id(apic, IO_TO_ID(apic), physid);
1331 /* Then check if the value in the MP table is acceptable */
1332 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1335 /* Last resort, find a free APIC ID and use it */
1336 freeid = first_free_apic_id();
1337 if (freeid >= NAPICID)
1338 panic("No free physical APIC IDs found");
1340 if (io_apic_id_acceptable(apic, freeid)) {
1341 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1344 panic("Free physical APIC ID not usable");
1346 fix_id_to_io_mapping();
1348 /* detect and fix broken Compaq MP table */
1349 if (apic_int_type(0, 0) == -1) {
1350 printf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1351 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1352 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1353 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1354 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1355 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1361 /* Assign low level interrupt handlers */
1363 setup_apic_irq_mapping(void)
1369 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1370 int_to_apicintpin[x].ioapic = -1;
1371 int_to_apicintpin[x].int_pin = 0;
1372 int_to_apicintpin[x].apic_address = NULL;
1373 int_to_apicintpin[x].redirindex = 0;
1376 /* First assign ISA/EISA interrupts */
1377 for (x = 0; x < nintrs; x++) {
1378 int_vector = io_apic_ints[x].src_bus_irq;
1379 if (int_vector < APIC_INTMAPSIZE &&
1380 io_apic_ints[x].int_vector == 0xff &&
1381 int_to_apicintpin[int_vector].ioapic == -1 &&
1382 (apic_int_is_bus_type(x, ISA) ||
1383 apic_int_is_bus_type(x, EISA)) &&
1384 io_apic_ints[x].int_type == 0) {
1385 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1386 io_apic_ints[x].dst_apic_int,
1391 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1392 for (x = 0; x < nintrs; x++) {
1393 if (io_apic_ints[x].dst_apic_int == 0 &&
1394 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1395 io_apic_ints[x].int_vector == 0xff &&
1396 int_to_apicintpin[0].ioapic == -1 &&
1397 io_apic_ints[x].int_type == 3) {
1398 assign_apic_irq(0, 0, 0);
1402 /* PCI interrupt assignment is deferred */
1407 processor_entry(proc_entry_ptr entry, int cpu)
1409 /* check for usability */
1410 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1413 if(entry->apic_id >= NAPICID)
1414 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1415 /* check for BSP flag */
1416 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1417 boot_cpu_id = entry->apic_id;
1418 CPU_TO_ID(0) = entry->apic_id;
1419 ID_TO_CPU(entry->apic_id) = 0;
1420 return 0; /* its already been counted */
1423 /* add another AP to list, if less than max number of CPUs */
1424 else if (cpu < MAXCPU) {
1425 CPU_TO_ID(cpu) = entry->apic_id;
1426 ID_TO_CPU(entry->apic_id) = cpu;
1435 bus_entry(bus_entry_ptr entry, int bus)
1440 /* encode the name into an index */
1441 for (x = 0; x < 6; ++x) {
1442 if ((c = entry->bus_type[x]) == ' ')
1448 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1449 panic("unknown bus type: '%s'", name);
1451 bus_data[bus].bus_id = entry->bus_id;
1452 bus_data[bus].bus_type = x;
1459 io_apic_entry(io_apic_entry_ptr entry, int apic)
1461 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1464 IO_TO_ID(apic) = entry->apic_id;
1465 if (entry->apic_id < NAPICID)
1466 ID_TO_IO(entry->apic_id) = apic;
1473 lookup_bus_type(char *name)
1477 for (x = 0; x < MAX_BUSTYPE; ++x)
1478 if (strcmp(bus_type_table[x].name, name) == 0)
1479 return bus_type_table[x].type;
1481 return UNKNOWN_BUSTYPE;
1486 int_entry(int_entry_ptr entry, int intr)
1490 io_apic_ints[intr].int_type = entry->int_type;
1491 io_apic_ints[intr].int_flags = entry->int_flags;
1492 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1493 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1494 if (entry->dst_apic_id == 255) {
1495 /* This signal goes to all IO APICS. Select an IO APIC
1496 with sufficient number of interrupt pins */
1497 for (apic = 0; apic < mp_napics; apic++)
1498 if (((io_apic_read(apic, IOAPIC_VER) &
1499 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1500 entry->dst_apic_int)
1502 if (apic < mp_napics)
1503 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1505 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1507 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1508 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1515 apic_int_is_bus_type(int intr, int bus_type)
1519 for (bus = 0; bus < mp_nbusses; ++bus)
1520 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1521 && ((int) bus_data[bus].bus_type == bus_type))
1529 * Given a traditional ISA INT mask, return an APIC mask.
1532 isa_apic_mask(u_int isa_mask)
1537 #if defined(SKIP_IRQ15_REDIRECT)
1538 if (isa_mask == (1 << 15)) {
1539 printf("skipping ISA IRQ15 redirect\n");
1542 #endif /* SKIP_IRQ15_REDIRECT */
1544 isa_irq = ffs(isa_mask); /* find its bit position */
1545 if (isa_irq == 0) /* doesn't exist */
1547 --isa_irq; /* make it zero based */
1549 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1553 return (1 << apic_pin); /* convert pin# to a mask */
1558 * Determine which APIC pin an ISA/EISA INT is attached to.
1560 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1561 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1562 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1563 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1565 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1567 isa_apic_irq(int isa_irq)
1571 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1572 if (INTTYPE(intr) == 0) { /* standard INT */
1573 if (SRCBUSIRQ(intr) == isa_irq) {
1574 if (apic_int_is_bus_type(intr, ISA) ||
1575 apic_int_is_bus_type(intr, EISA)) {
1576 if (INTIRQ(intr) == 0xff)
1577 return -1; /* unassigned */
1578 return INTIRQ(intr); /* found */
1583 return -1; /* NOT found */
1588 * Determine which APIC pin a PCI INT is attached to.
1590 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1591 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1592 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1594 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1598 --pciInt; /* zero based */
1600 for (intr = 0; intr < nintrs; ++intr) /* check each record */
1601 if ((INTTYPE(intr) == 0) /* standard INT */
1602 && (SRCBUSID(intr) == pciBus)
1603 && (SRCBUSDEVICE(intr) == pciDevice)
1604 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */
1605 if (apic_int_is_bus_type(intr, PCI)) {
1606 if (INTIRQ(intr) == 0xff)
1607 allocate_apic_irq(intr);
1608 if (INTIRQ(intr) == 0xff)
1609 return -1; /* unassigned */
1610 return INTIRQ(intr); /* exact match */
1613 return -1; /* NOT found */
1617 next_apic_irq(int irq)
1624 for (intr = 0; intr < nintrs; intr++) {
1625 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1627 bus = SRCBUSID(intr);
1628 bustype = apic_bus_type(bus);
1629 if (bustype != ISA &&
1635 if (intr >= nintrs) {
1638 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1639 if (INTTYPE(ointr) != 0)
1641 if (bus != SRCBUSID(ointr))
1643 if (bustype == PCI) {
1644 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1646 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1649 if (bustype == ISA || bustype == EISA) {
1650 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1653 if (INTPIN(intr) == INTPIN(ointr))
1657 if (ointr >= nintrs) {
1660 return INTIRQ(ointr);
1674 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1677 * Exactly what this means is unclear at this point. It is a solution
1678 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1679 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1680 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1684 undirect_isa_irq(int rirq)
1688 printf("Freeing redirected ISA irq %d.\n", rirq);
1689 /** FIXME: tickle the MB redirector chip */
1693 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1700 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1703 undirect_pci_irq(int rirq)
1707 printf("Freeing redirected PCI irq %d.\n", rirq);
1709 /** FIXME: tickle the MB redirector chip */
1713 printf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1721 * given a bus ID, return:
1722 * the bus type if found
1726 apic_bus_type(int id)
1730 for (x = 0; x < mp_nbusses; ++x)
1731 if (bus_data[x].bus_id == id)
1732 return bus_data[x].bus_type;
1739 * given a LOGICAL APIC# and pin#, return:
1740 * the associated src bus ID if found
1744 apic_src_bus_id(int apic, int pin)
1748 /* search each of the possible INTerrupt sources */
1749 for (x = 0; x < nintrs; ++x)
1750 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1751 (pin == io_apic_ints[x].dst_apic_int))
1752 return (io_apic_ints[x].src_bus_id);
1754 return -1; /* NOT found */
1759 * given a LOGICAL APIC# and pin#, return:
1760 * the associated src bus IRQ if found
1764 apic_src_bus_irq(int apic, int pin)
1768 for (x = 0; x < nintrs; x++)
1769 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1770 (pin == io_apic_ints[x].dst_apic_int))
1771 return (io_apic_ints[x].src_bus_irq);
1773 return -1; /* NOT found */
1778 * given a LOGICAL APIC# and pin#, return:
1779 * the associated INTerrupt type if found
1783 apic_int_type(int apic, int pin)
1787 /* search each of the possible INTerrupt sources */
1788 for (x = 0; x < nintrs; ++x)
1789 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1790 (pin == io_apic_ints[x].dst_apic_int))
1791 return (io_apic_ints[x].int_type);
1793 return -1; /* NOT found */
1797 apic_irq(int apic, int pin)
1802 for (x = 0; x < nintrs; ++x)
1803 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1804 (pin == io_apic_ints[x].dst_apic_int)) {
1805 res = io_apic_ints[x].int_vector;
1808 if (apic != int_to_apicintpin[res].ioapic)
1809 panic("apic_irq: inconsistent table");
1810 if (pin != int_to_apicintpin[res].int_pin)
1811 panic("apic_irq inconsistent table (2)");
1819 * given a LOGICAL APIC# and pin#, return:
1820 * the associated trigger mode if found
1824 apic_trigger(int apic, int pin)
1828 /* search each of the possible INTerrupt sources */
1829 for (x = 0; x < nintrs; ++x)
1830 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1831 (pin == io_apic_ints[x].dst_apic_int))
1832 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1834 return -1; /* NOT found */
1839 * given a LOGICAL APIC# and pin#, return:
1840 * the associated 'active' level if found
1844 apic_polarity(int apic, int pin)
1848 /* search each of the possible INTerrupt sources */
1849 for (x = 0; x < nintrs; ++x)
1850 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1851 (pin == io_apic_ints[x].dst_apic_int))
1852 return (io_apic_ints[x].int_flags & 0x03);
1854 return -1; /* NOT found */
1859 * set data according to MP defaults
1860 * FIXME: probably not complete yet...
1863 default_mp_table(int type)
1866 #if defined(APIC_IO)
1869 #endif /* APIC_IO */
1872 printf(" MP default config type: %d\n", type);
1875 printf(" bus: ISA, APIC: 82489DX\n");
1878 printf(" bus: EISA, APIC: 82489DX\n");
1881 printf(" bus: EISA, APIC: 82489DX\n");
1884 printf(" bus: MCA, APIC: 82489DX\n");
1887 printf(" bus: ISA+PCI, APIC: Integrated\n");
1890 printf(" bus: EISA+PCI, APIC: Integrated\n");
1893 printf(" bus: MCA+PCI, APIC: Integrated\n");
1896 printf(" future type\n");
1902 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1903 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1906 CPU_TO_ID(0) = boot_cpu_id;
1907 ID_TO_CPU(boot_cpu_id) = 0;
1909 /* one and only AP */
1910 CPU_TO_ID(1) = ap_cpu_id;
1911 ID_TO_CPU(ap_cpu_id) = 1;
1913 #if defined(APIC_IO)
1914 /* one and only IO APIC */
1915 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1918 * sanity check, refer to MP spec section 3.6.6, last paragraph
1919 * necessary as some hardware isn't properly setting up the IO APIC
1921 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1922 if (io_apic_id != 2) {
1924 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1925 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1926 io_apic_set_id(0, 2);
1929 IO_TO_ID(0) = io_apic_id;
1930 ID_TO_IO(io_apic_id) = 0;
1931 #endif /* APIC_IO */
1933 /* fill out bus entries */
1942 bus_data[0].bus_id = default_data[type - 1][1];
1943 bus_data[0].bus_type = default_data[type - 1][2];
1944 bus_data[1].bus_id = default_data[type - 1][3];
1945 bus_data[1].bus_type = default_data[type - 1][4];
1948 /* case 4: case 7: MCA NOT supported */
1949 default: /* illegal/reserved */
1950 panic("BAD default MP config: %d", type);
1954 #if defined(APIC_IO)
1955 /* general cases from MP v1.4, table 5-2 */
1956 for (pin = 0; pin < 16; ++pin) {
1957 io_apic_ints[pin].int_type = 0;
1958 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1959 io_apic_ints[pin].src_bus_id = 0;
1960 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1961 io_apic_ints[pin].dst_apic_id = io_apic_id;
1962 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
1965 /* special cases from MP v1.4, table 5-2 */
1967 io_apic_ints[2].int_type = 0xff; /* N/C */
1968 io_apic_ints[13].int_type = 0xff; /* N/C */
1969 #if !defined(APIC_MIXED_MODE)
1971 panic("sorry, can't support type 2 default yet");
1972 #endif /* APIC_MIXED_MODE */
1975 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
1978 io_apic_ints[0].int_type = 0xff; /* N/C */
1980 io_apic_ints[0].int_type = 3; /* vectored 8259 */
1981 #endif /* APIC_IO */
1985 * start each AP in our list
1988 start_all_aps(u_int boot_addr)
1991 u_char mpbiosreason;
1992 u_long mpbioswarmvec;
1993 struct mdglobaldata *gd;
1997 POSTCODE(START_ALL_APS_POST);
1999 /* initialize BSP's local APIC */
2003 /* install the AP 1st level boot code */
2004 install_ap_tramp(boot_addr);
2007 /* save the current value of the warm-start vector */
2008 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2010 outb(CMOS_REG, BIOS_RESET);
2011 mpbiosreason = inb(CMOS_DATA);
2014 /* record BSP in CPU map */
2017 /* set up temporary P==V mapping for AP boot */
2018 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2019 kptbase = (uintptr_t)(void *)KPTphys;
2020 for (x = 0; x < NKPT; x++)
2021 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2022 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2026 for (x = 1; x <= mp_naps; ++x) {
2028 /* This is a bit verbose, it will go away soon. */
2030 /* first page of AP's private space */
2031 pg = x * i386_btop(sizeof(struct privatespace));
2033 /* allocate a new private data page */
2034 gd = (struct mdglobaldata *)kmem_alloc(kernel_map, PAGE_SIZE);
2036 /* wire it into the private page table page */
2037 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys_pte(gd));
2039 /* allocate and set up an idle stack data page */
2040 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE);
2041 for (i = 0; i < UPAGES; i++) {
2042 SMPpt[pg + 5 + i] = (pt_entry_t)
2043 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2046 SMPpt[pg + 1] = 0; /* *gd_CMAP1 */
2047 SMPpt[pg + 2] = 0; /* *gd_CMAP2 */
2048 SMPpt[pg + 3] = 0; /* *gd_CMAP3 */
2049 SMPpt[pg + 4] = 0; /* *gd_PMAP1 */
2051 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2052 bzero(gd, sizeof(*gd));
2053 gd->mi.gd_prvspace = &CPU_prvspace[x];
2055 /* prime data page for it to use */
2056 mi_gdinit(&gd->mi, x);
2058 gd->gd_cpu_lockid = x << 24;
2059 gd->gd_CMAP1 = &SMPpt[pg + 1];
2060 gd->gd_CMAP2 = &SMPpt[pg + 2];
2061 gd->gd_CMAP3 = &SMPpt[pg + 3];
2062 gd->gd_PMAP1 = &SMPpt[pg + 4];
2063 gd->gd_CADDR1 = CPU_prvspace[x].CPAGE1;
2064 gd->gd_CADDR2 = CPU_prvspace[x].CPAGE2;
2065 gd->gd_CADDR3 = CPU_prvspace[x].CPAGE3;
2066 gd->gd_PADDR1 = (unsigned *)CPU_prvspace[x].PPAGE1;
2067 gd->mi.gd_ipiq = (void *)kmem_alloc(kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2068 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2070 /* setup a vector to our boot code */
2071 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2072 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2074 outb(CMOS_REG, BIOS_RESET);
2075 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2079 * Setup the AP boot stack
2081 bootSTK = &CPU_prvspace[x].idlestack[UPAGES*PAGE_SIZE/2];
2084 /* attempt to start the Application Processor */
2085 CHECK_INIT(99); /* setup checkpoints */
2086 if (!start_ap(x, boot_addr)) {
2087 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2088 CHECK_PRINT("trace"); /* show checkpoints */
2089 /* better panic as the AP may be running loose */
2090 printf("panic y/n? [y] ");
2091 if (cngetc() != 'n')
2094 CHECK_PRINT("trace"); /* show checkpoints */
2096 /* record its version info */
2097 cpu_apic_versions[x] = cpu_apic_versions[0];
2099 all_cpus |= (1 << x); /* record AP in CPU map */
2102 /* build our map of 'other' CPUs */
2103 mycpu->gd_other_cpus = all_cpus & ~(1 << mycpu->gd_cpuid);
2104 mycpu->gd_ipiq = (void *)kmem_alloc(kernel_map, sizeof(lwkt_ipiq) * ncpus);
2105 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2107 /* fill in our (BSP) APIC version */
2108 cpu_apic_versions[0] = lapic.version;
2110 /* restore the warmstart vector */
2111 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2113 outb(CMOS_REG, BIOS_RESET);
2114 outb(CMOS_DATA, mpbiosreason);
2118 * NOTE! The idlestack for the BSP was setup by locore. Finish
2119 * up, clean out the P==V mapping we did earlier.
2121 for (x = 0; x < NKPT; x++)
2125 /* number of APs actually started */
2131 * load the 1st level AP boot code into base memory.
2134 /* targets for relocation */
2135 extern void bigJump(void);
2136 extern void bootCodeSeg(void);
2137 extern void bootDataSeg(void);
2138 extern void MPentry(void);
2139 extern u_int MP_GDT;
2140 extern u_int mp_gdtbase;
2143 install_ap_tramp(u_int boot_addr)
2146 int size = *(int *) ((u_long) & bootMP_size);
2147 u_char *src = (u_char *) ((u_long) bootMP);
2148 u_char *dst = (u_char *) boot_addr + KERNBASE;
2149 u_int boot_base = (u_int) bootMP;
2154 POSTCODE(INSTALL_AP_TRAMP_POST);
2156 for (x = 0; x < size; ++x)
2160 * modify addresses in code we just moved to basemem. unfortunately we
2161 * need fairly detailed info about mpboot.s for this to work. changes
2162 * to mpboot.s might require changes here.
2165 /* boot code is located in KERNEL space */
2166 dst = (u_char *) boot_addr + KERNBASE;
2168 /* modify the lgdt arg */
2169 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2170 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2172 /* modify the ljmp target for MPentry() */
2173 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2174 *dst32 = ((u_int) MPentry - KERNBASE);
2176 /* modify the target for boot code segment */
2177 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2178 dst8 = (u_int8_t *) (dst16 + 1);
2179 *dst16 = (u_int) boot_addr & 0xffff;
2180 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2182 /* modify the target for boot data segment */
2183 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2184 dst8 = (u_int8_t *) (dst16 + 1);
2185 *dst16 = (u_int) boot_addr & 0xffff;
2186 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2191 * this function starts the AP (application processor) identified
2192 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2193 * to accomplish this. This is necessary because of the nuances
2194 * of the different hardware we might encounter. It ain't pretty,
2195 * but it seems to work.
2197 * NOTE: eventually an AP gets to ap_init(), which is called just
2198 * before the AP goes into the LWKT scheduler's idle loop.
2201 start_ap(int logical_cpu, u_int boot_addr)
2206 u_long icr_lo, icr_hi;
2208 POSTCODE(START_AP_POST);
2210 /* get the PHYSICAL APIC ID# */
2211 physical_cpu = CPU_TO_ID(logical_cpu);
2213 /* calculate the vector */
2214 vector = (boot_addr >> 12) & 0xff;
2216 /* used as a watchpoint to signal AP startup */
2219 /* Make sure the target cpu sees everything */
2223 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2224 * and running the target CPU. OR this INIT IPI might be latched (P5
2225 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2229 /* setup the address for the target AP */
2230 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2231 icr_hi |= (physical_cpu << 24);
2232 lapic.icr_hi = icr_hi;
2234 /* do an INIT IPI: assert RESET */
2235 icr_lo = lapic.icr_lo & 0xfff00000;
2236 lapic.icr_lo = icr_lo | 0x0000c500;
2238 /* wait for pending status end */
2239 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2242 /* do an INIT IPI: deassert RESET */
2243 lapic.icr_lo = icr_lo | 0x00008500;
2245 /* wait for pending status end */
2246 u_sleep(10000); /* wait ~10mS */
2247 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2251 * next we do a STARTUP IPI: the previous INIT IPI might still be
2252 * latched, (P5 bug) this 1st STARTUP would then terminate
2253 * immediately, and the previously started INIT IPI would continue. OR
2254 * the previous INIT IPI has already run. and this STARTUP IPI will
2255 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2259 /* do a STARTUP IPI */
2260 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2261 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2263 u_sleep(200); /* wait ~200uS */
2266 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2267 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2268 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2269 * recognized after hardware RESET or INIT IPI.
2272 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2273 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2275 u_sleep(200); /* wait ~200uS */
2277 /* wait for it to start, see ap_init() */
2278 set_apic_timer(5000000);/* == 5 seconds */
2279 while (read_apic_timer()) {
2281 return 1; /* return SUCCESS */
2283 return 0; /* return FAILURE */
2288 * Flush the TLB on all other CPU's
2290 * XXX: Needs to handshake and wait for completion before proceding.
2295 #if defined(APIC_IO)
2296 if (smp_started && invltlb_ok)
2297 all_but_self_ipi(XINVLTLB_OFFSET);
2298 #endif /* APIC_IO */
2302 * When called the executing CPU will send an IPI to all other CPUs
2303 * requesting that they halt execution.
2305 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2307 * - Signals all CPUs in map to stop.
2308 * - Waits for each to stop.
2315 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2316 * from executing at same time.
2319 stop_cpus(u_int map)
2324 /* send the Xcpustop IPI to all CPUs in map */
2325 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2327 while ((stopped_cpus & map) != map)
2335 * Called by a CPU to restart stopped CPUs.
2337 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2339 * - Signals all CPUs in map to restart.
2340 * - Waits for each to restart.
2348 restart_cpus(u_int map)
2353 started_cpus = map; /* signal other cpus to restart */
2355 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2361 int smp_active = 0; /* are the APs allowed to run? */
2362 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, "");
2364 /* XXX maybe should be hw.ncpu */
2365 static int smp_cpus = 1; /* how many cpu's running */
2366 SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, "");
2368 int invltlb_ok = 0; /* throttle smp_invltlb() till safe */
2369 SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, "");
2371 /* Warning: Do not staticize. Used from swtch.s */
2372 int do_page_zero_idle = 1; /* bzero pages for fun and profit in idleloop */
2373 SYSCTL_INT(_machdep, OID_AUTO, do_page_zero_idle, CTLFLAG_RW,
2374 &do_page_zero_idle, 0, "");
2376 /* Is forwarding of a interrupt to the CPU holding the ISR lock enabled ? */
2377 int forward_irq_enabled = 1;
2378 SYSCTL_INT(_machdep, OID_AUTO, forward_irq_enabled, CTLFLAG_RW,
2379 &forward_irq_enabled, 0, "");
2381 /* Enable forwarding of a signal to a process running on a different CPU */
2382 static int forward_signal_enabled = 1;
2383 SYSCTL_INT(_machdep, OID_AUTO, forward_signal_enabled, CTLFLAG_RW,
2384 &forward_signal_enabled, 0, "");
2386 /* Enable forwarding of roundrobin to all other cpus */
2387 static int forward_roundrobin_enabled = 1;
2388 SYSCTL_INT(_machdep, OID_AUTO, forward_roundrobin_enabled, CTLFLAG_RW,
2389 &forward_roundrobin_enabled, 0, "");
2392 * This is called once the mpboot code has gotten us properly relocated
2393 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2394 * and when it returns the scheduler will call the real cpu_idle() main
2395 * loop for the idlethread. Interrupts are disabled on entry and should
2396 * remain disabled at return.
2405 * Signal the BSP that we have started up successfully by incrementing
2406 * ncpus. Note that we do not hold the BGL yet. The BSP is waiting
2412 * Get the MP lock so we can finish initializing. Note: we are
2413 * in a critical section. td_mpcount must always be bumped prior
2414 * to obtaining the actual lock.
2416 ++curthread->td_mpcount;
2417 while (cpu_try_mplock() == 0)
2420 /* BSP may have changed PTD while we're waiting for the lock */
2423 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2427 /* Build our map of 'other' CPUs. */
2428 mycpu->gd_other_cpus = all_cpus & ~(1 << mycpu->gd_cpuid);
2430 printf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2432 /* set up CPU registers and state */
2435 /* set up FPU state on the AP */
2436 npxinit(__INITIAL_NPXCW__);
2438 /* set up SSE registers */
2441 /* A quick check from sanity claus */
2442 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2443 if (mycpu->gd_cpuid != apic_id) {
2444 printf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2445 printf("SMP: apic_id = %d\n", apic_id);
2446 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2447 panic("cpuid mismatch! boom!!");
2450 /* Init local apic for irq's */
2453 /* Set memory range attributes for this CPU to match the BSP */
2454 mem_range_AP_init();
2457 * Since we have the BGL if smp_cpus matches ncpus then we are
2458 * the last AP to get to this point and we can enable IPI's,
2459 * tlb shootdowns, freezes, and so forth.
2462 if (smp_cpus == ncpus) {
2464 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */
2465 smp_active = 1; /* historic */
2469 * AP helper function for kernel memory support. This will create
2470 * a memory reserve for the AP that is necessary to avoid certain
2471 * memory deadlock situations, such as when the kernel_map needs
2472 * a vm_map_entry and zalloc has no free entries and tries to allocate
2473 * a new one from the ... kernel_map :-)
2478 * Startup helper thread(s) one per cpu.
2480 sched_thread_init();
2483 * The idle loop doesn't expect the BGL to be held and while
2484 * lwkt_switch() normally cleans things up this is a special case
2485 * because we returning almost directly into the idle loop.
2487 KKASSERT(curthread->td_mpcount == 1);
2493 #define CHECKSTATE_USER 0
2494 #define CHECKSTATE_SYS 1
2495 #define CHECKSTATE_INTR 2
2497 /* Do not staticize. Used from apic_vector.s */
2498 struct thread *checkstate_curtd[MAXCPU];
2499 int checkstate_cpustate[MAXCPU];
2500 u_long checkstate_pc[MAXCPU];
2502 #define PC_TO_INDEX(pc, prof) \
2503 ((int)(((u_quad_t)((pc) - (prof)->pr_off) * \
2504 (u_quad_t)((prof)->pr_scale)) >> 16) & ~1)
2508 addupc_intr_forwarded(struct proc *p, int id, int *astmap)
2514 pc = checkstate_pc[id];
2515 prof = &p->p_stats->p_prof;
2516 if (pc >= prof->pr_off &&
2517 (i = PC_TO_INDEX(pc, prof)) < prof->pr_size) {
2518 if ((p->p_flag & P_OWEUPC) == 0) {
2521 p->p_flag |= P_OWEUPC;
2523 *astmap |= (1 << id);
2529 forwarded_statclock(int id, int pscnt, int *astmap)
2532 struct pstats *pstats;
2539 register struct gmonparam *g;
2543 t = checkstate_curtd[id];
2544 cpustate = checkstate_cpustate[id];
2547 case CHECKSTATE_USER:
2548 if (td->td_proc && td->td_proc->p_flag & P_PROFIL)
2549 addupc_intr_forwarded(td->td_proc, id, astmap);
2553 if (p->p_nice > NZERO)
2558 case CHECKSTATE_SYS:
2561 * Kernel statistics are just like addupc_intr, only easier.
2564 if (g->state == GMON_PROF_ON) {
2565 i = checkstate_pc[id] - g->lowpc;
2566 if (i < g->textsize) {
2567 i /= HISTFRACTION * sizeof(*g->kcount);
2582 case CHECKSTATE_INTR:
2586 * Kernel statistics are just like addupc_intr, only easier.
2589 if (g->state == GMON_PROF_ON) {
2590 i = checkstate_pc[id] - g->lowpc;
2591 if (i < g->textsize) {
2592 i /= HISTFRACTION * sizeof(*g->kcount);
2606 /* Update resource usage integrals and maximums. */
2607 if ((pstats = p->p_stats) != NULL &&
2608 (ru = &pstats->p_ru) != NULL &&
2609 (vm = p->p_vmspace) != NULL) {
2610 ru->ru_ixrss += pgtok(vm->vm_tsize);
2611 ru->ru_idrss += pgtok(vm->vm_dsize);
2612 ru->ru_isrss += pgtok(vm->vm_ssize);
2613 rss = pgtok(vmspace_resident_count(vm));
2614 if (ru->ru_maxrss < rss)
2615 ru->ru_maxrss = rss;
2622 forward_statclock(int pscnt)
2628 /* Kludge. We don't yet have separate locks for the interrupts
2629 * and the kernel. This means that we cannot let the other processors
2630 * handle complex interrupts while inhibiting them from entering
2631 * the kernel in a non-interrupt context.
2633 * What we can do, without changing the locking mechanisms yet,
2634 * is letting the other processors handle a very simple interrupt
2635 * (wich determines the processor states), and do the main
2639 if (!smp_started || !invltlb_ok || cold || panicstr)
2642 printf("forward_statclock\n");
2643 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle ) */
2645 map = mycpu->gd_other_cpus & ~stopped_cpus ;
2646 checkstate_probed_cpus = 0;
2648 selected_apic_ipi(map,
2649 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2652 while (checkstate_probed_cpus != map) {
2656 #ifdef BETTER_CLOCK_DIAGNOSTIC
2657 printf("forward_statclock: checkstate %x\n",
2658 checkstate_probed_cpus);
2665 * Step 2: walk through other processors processes, update ticks and
2670 for (id = 0; id < ncpus; id++) {
2671 if (id == mycpu->gd_cpuid)
2673 if (((1 << id) & checkstate_probed_cpus) == 0)
2675 forwarded_statclock(id, pscnt, &map);
2682 forward_hardclock(int pscnt)
2688 struct pstats *pstats;
2692 /* Kludge. We don't yet have separate locks for the interrupts
2693 * and the kernel. This means that we cannot let the other processors
2694 * handle complex interrupts while inhibiting them from entering
2695 * the kernel in a non-interrupt context.
2697 * What we can do, without changing the locking mechanisms yet,
2698 * is letting the other processors handle a very simple interrupt
2699 * (wich determines the processor states), and do the main
2703 if (!smp_started || !invltlb_ok || cold || panicstr)
2706 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle) */
2708 map = mycpu->gd_other_cpus & ~stopped_cpus ;
2709 checkstate_probed_cpus = 0;
2711 selected_apic_ipi(map,
2712 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2715 while (checkstate_probed_cpus != map) {
2719 #ifdef BETTER_CLOCK_DIAGNOSTIC
2720 printf("forward_hardclock: checkstate %x\n",
2721 checkstate_probed_cpus);
2728 * Step 2: walk through other processors processes, update virtual
2729 * timer and profiling timer. If stathz == 0, also update ticks and
2734 for (id = 0; id < ncpus; id++) {
2735 if (id == mycpu->gd_cpuid)
2737 if (((1 << id) & checkstate_probed_cpus) == 0)
2739 printf("forward_hardclock\n");
2741 p = checkstate_curproc[id];
2743 pstats = p->p_stats;
2744 if (checkstate_cpustate[id] == CHECKSTATE_USER &&
2745 timevalisset(&pstats->p_timer[ITIMER_VIRTUAL].it_value) &&
2746 itimerdecr(&pstats->p_timer[ITIMER_VIRTUAL], tick) == 0) {
2747 psignal(p, SIGVTALRM);
2750 if (timevalisset(&pstats->p_timer[ITIMER_PROF].it_value) &&
2751 itimerdecr(&pstats->p_timer[ITIMER_PROF], tick) == 0) {
2752 psignal(p, SIGPROF);
2757 forwarded_statclock( id, pscnt, &map);
2765 #endif /* BETTER_CLOCK */
2767 #ifdef APIC_INTR_REORDER
2769 * Maintain mapping from softintr vector to isr bit in local apic.
2772 set_lapic_isrloc(int intr, int vector)
2774 if (intr < 0 || intr > 32)
2775 panic("set_apic_isrloc: bad intr argument: %d",intr);
2776 if (vector < ICU_OFFSET || vector > 255)
2777 panic("set_apic_isrloc: bad vector argument: %d",vector);
2778 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2);
2779 apic_isrbit_location[intr].bit = (1<<(vector & 31));
2784 * All-CPU rendezvous. CPUs are signalled, all execute the setup function
2785 * (if specified), rendezvous, execute the action function (if specified),
2786 * rendezvous again, execute the teardown function (if specified), and then
2789 * Note that the supplied external functions _must_ be reentrant and aware
2790 * that they are running in parallel and in an unknown lock context.
2792 static void (*smp_rv_setup_func)(void *arg);
2793 static void (*smp_rv_action_func)(void *arg);
2794 static void (*smp_rv_teardown_func)(void *arg);
2795 static void *smp_rv_func_arg;
2796 static volatile int smp_rv_waiters[2];
2799 smp_rendezvous_action(void)
2801 /* setup function */
2802 if (smp_rv_setup_func != NULL)
2803 smp_rv_setup_func(smp_rv_func_arg);
2804 /* spin on entry rendezvous */
2805 atomic_add_int(&smp_rv_waiters[0], 1);
2806 while (smp_rv_waiters[0] < ncpus)
2808 /* action function */
2809 if (smp_rv_action_func != NULL)
2810 smp_rv_action_func(smp_rv_func_arg);
2811 /* spin on exit rendezvous */
2812 atomic_add_int(&smp_rv_waiters[1], 1);
2813 while (smp_rv_waiters[1] < ncpus)
2815 /* teardown function */
2816 if (smp_rv_teardown_func != NULL)
2817 smp_rv_teardown_func(smp_rv_func_arg);
2821 smp_rendezvous(void (* setup_func)(void *),
2822 void (* action_func)(void *),
2823 void (* teardown_func)(void *),
2826 /* obtain rendezvous lock. This disables interrupts */
2827 spin_lock(&smp_rv_spinlock); /* XXX sleep here? NOWAIT flag? */
2829 /* set static function pointers */
2830 smp_rv_setup_func = setup_func;
2831 smp_rv_action_func = action_func;
2832 smp_rv_teardown_func = teardown_func;
2833 smp_rv_func_arg = arg;
2834 smp_rv_waiters[0] = 0;
2835 smp_rv_waiters[1] = 0;
2837 /* signal other processors, which will enter the IPI with interrupts off */
2838 all_but_self_ipi(XRENDEZVOUS_OFFSET);
2840 /* call executor function */
2841 smp_rendezvous_action();
2844 spin_unlock(&smp_rv_spinlock);
2848 cpu_send_ipiq(int dcpu)
2850 selected_apic_ipi(1 << dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);