2 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
3 * Copyright (c) 1990 William Jolitz.
4 * Copyright (c) 1991 The Regents of the University of California.
7 * This code is derived from software contributed to The DragonFly Project
8 * by Matthew Dillon <dillon@backplane.com>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in
18 * the documentation and/or other materials provided with the
20 * 3. Neither the name of The DragonFly Project nor the names of its
21 * contributors may be used to endorse or promote products derived
22 * from this software without specific, prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
28 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
29 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
30 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
31 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
32 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
34 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
38 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $
41 #include <sys/param.h>
42 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/malloc.h>
46 #include <sys/module.h>
47 #include <sys/sysctl.h>
50 #include <sys/signalvar.h>
52 #include <sys/thread2.h>
53 #include <sys/mplock2.h>
55 #include <machine/cputypes.h>
56 #include <machine/frame.h>
57 #include <machine/md_var.h>
58 #include <machine/pcb.h>
59 #include <machine/psl.h>
60 #include <machine/specialreg.h>
61 #include <machine/segments.h>
62 #include <machine/globaldata.h>
64 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr)))
65 #define fnclex() __asm("fnclex")
66 #define fninit() __asm("fninit")
67 #define fnop() __asm("fnop")
68 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr)))
69 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
70 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr)))
71 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr)))
72 #ifndef CPU_DISABLE_SSE
73 #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr)))
74 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
77 typedef u_char bool_t;
78 #ifndef CPU_DISABLE_SSE
79 static void fpu_clean_state(void);
84 static struct krate badfprate = { 1 };
86 /*static int npx_attach (device_t dev);*/
87 static void fpusave (union savefpu *);
88 static void fpurstor (union savefpu *);
90 #if (defined(I586_CPU) || defined(I686_CPU)) && !defined(CPU_DISABLE_SSE)
92 SYSCTL_INT(_kern, OID_AUTO, mmxopt, CTLFLAG_RD, &mmxopt, 0,
93 "MMX/XMM optimized bcopy/copyin/copyout support");
96 static int hw_instruction_sse;
97 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
98 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
102 * Attach routine - announce which it is, and wire into system
105 npx_attach(device_t dev)
107 npxinit(__INITIAL_NPXCW__);
113 init_fpu(int supports_sse)
115 cpu_fxsr = hw_instruction_sse = supports_sse;
119 * Initialize the floating point unit.
122 npxinit(u_short control)
124 static union savefpu dummy __aligned(16);
127 * fninit has the same h/w bugs as fnsave. Use the detoxified
128 * fnsave to throw away any junk in the fpu. npxsave() initializes
129 * the fpu and sets npxthread = NULL as important side effects.
133 /*stop_emulating();*/
135 fpusave(curthread->td_savefpu);
136 mdcpu->gd_npxthread = NULL;
137 /*start_emulating();*/
142 * Free coprocessor (if we have it).
147 if (curthread == mdcpu->gd_npxthread)
148 npxsave(curthread->td_savefpu);
153 * The following mechanism is used to ensure that the FPE_... value
154 * that is passed as a trapcode to the signal handler of the user
155 * process does not have more than one bit set.
157 * Multiple bits may be set if the user process modifies the control
158 * word while a status word bit is already set. While this is a sign
159 * of bad coding, we have no choise than to narrow them down to one
160 * bit, since we must not send a trapcode that is not exactly one of
163 * The mechanism has a static table with 127 entries. Each combination
164 * of the 7 FPU status word exception bits directly translates to a
165 * position in this table, where a single FPE_... value is stored.
166 * This FPE_... value stored there is considered the "most important"
167 * of the exception bits and will be sent as the signal code. The
168 * precedence of the bits is based upon Intel Document "Numerical
169 * Applications", Chapter "Special Computational Situations".
171 * The macro to choose one of these values does these steps: 1) Throw
172 * away status word bits that cannot be masked. 2) Throw away the bits
173 * currently masked in the control word, assuming the user isn't
174 * interested in them anymore. 3) Reinsert status word bit 7 (stack
175 * fault) if it is set, which cannot be masked but must be presered.
176 * 4) Use the remaining bits to point into the trapcode table.
178 * The 6 maskable bits in order of their preference, as stated in the
179 * above referenced Intel manual:
180 * 1 Invalid operation (FP_X_INV)
183 * 1c Operand of unsupported format
185 * 2 QNaN operand (not an exception, irrelavant here)
186 * 3 Any other invalid-operation not mentioned above or zero divide
187 * (FP_X_INV, FP_X_DZ)
188 * 4 Denormal operand (FP_X_DNML)
189 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
190 * 6 Inexact result (FP_X_IMP)
192 static char fpetable[128] = {
194 FPE_FLTINV, /* 1 - INV */
195 FPE_FLTUND, /* 2 - DNML */
196 FPE_FLTINV, /* 3 - INV | DNML */
197 FPE_FLTDIV, /* 4 - DZ */
198 FPE_FLTINV, /* 5 - INV | DZ */
199 FPE_FLTDIV, /* 6 - DNML | DZ */
200 FPE_FLTINV, /* 7 - INV | DNML | DZ */
201 FPE_FLTOVF, /* 8 - OFL */
202 FPE_FLTINV, /* 9 - INV | OFL */
203 FPE_FLTUND, /* A - DNML | OFL */
204 FPE_FLTINV, /* B - INV | DNML | OFL */
205 FPE_FLTDIV, /* C - DZ | OFL */
206 FPE_FLTINV, /* D - INV | DZ | OFL */
207 FPE_FLTDIV, /* E - DNML | DZ | OFL */
208 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
209 FPE_FLTUND, /* 10 - UFL */
210 FPE_FLTINV, /* 11 - INV | UFL */
211 FPE_FLTUND, /* 12 - DNML | UFL */
212 FPE_FLTINV, /* 13 - INV | DNML | UFL */
213 FPE_FLTDIV, /* 14 - DZ | UFL */
214 FPE_FLTINV, /* 15 - INV | DZ | UFL */
215 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
216 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
217 FPE_FLTOVF, /* 18 - OFL | UFL */
218 FPE_FLTINV, /* 19 - INV | OFL | UFL */
219 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
220 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
221 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
222 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
223 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
224 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
225 FPE_FLTRES, /* 20 - IMP */
226 FPE_FLTINV, /* 21 - INV | IMP */
227 FPE_FLTUND, /* 22 - DNML | IMP */
228 FPE_FLTINV, /* 23 - INV | DNML | IMP */
229 FPE_FLTDIV, /* 24 - DZ | IMP */
230 FPE_FLTINV, /* 25 - INV | DZ | IMP */
231 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
232 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
233 FPE_FLTOVF, /* 28 - OFL | IMP */
234 FPE_FLTINV, /* 29 - INV | OFL | IMP */
235 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
236 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
237 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
238 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
239 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
240 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
241 FPE_FLTUND, /* 30 - UFL | IMP */
242 FPE_FLTINV, /* 31 - INV | UFL | IMP */
243 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
244 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
245 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
246 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
247 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
248 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
249 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
250 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
251 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
252 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
253 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
254 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
255 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
256 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
257 FPE_FLTSUB, /* 40 - STK */
258 FPE_FLTSUB, /* 41 - INV | STK */
259 FPE_FLTUND, /* 42 - DNML | STK */
260 FPE_FLTSUB, /* 43 - INV | DNML | STK */
261 FPE_FLTDIV, /* 44 - DZ | STK */
262 FPE_FLTSUB, /* 45 - INV | DZ | STK */
263 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
264 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
265 FPE_FLTOVF, /* 48 - OFL | STK */
266 FPE_FLTSUB, /* 49 - INV | OFL | STK */
267 FPE_FLTUND, /* 4A - DNML | OFL | STK */
268 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
269 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
270 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
271 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
272 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
273 FPE_FLTUND, /* 50 - UFL | STK */
274 FPE_FLTSUB, /* 51 - INV | UFL | STK */
275 FPE_FLTUND, /* 52 - DNML | UFL | STK */
276 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
277 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
278 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
279 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
280 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
281 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
282 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
283 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
284 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
285 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
286 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
287 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
288 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
289 FPE_FLTRES, /* 60 - IMP | STK */
290 FPE_FLTSUB, /* 61 - INV | IMP | STK */
291 FPE_FLTUND, /* 62 - DNML | IMP | STK */
292 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
293 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
294 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
295 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
296 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
297 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
298 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
299 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
300 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
301 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
302 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
303 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
304 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
305 FPE_FLTUND, /* 70 - UFL | IMP | STK */
306 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
307 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
308 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
309 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
310 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
311 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
312 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
313 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
314 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
315 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
316 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
317 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
318 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
319 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
320 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
327 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
329 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now
330 * depend on longjmp() restoring a usable state. Restoring the state
331 * or examining it might fail if we didn't clear exceptions.
333 * The error code chosen will be one of the FPE_... macros. It will be
334 * sent as the second argument to old BSD-style signal handlers and as
335 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
337 * XXX the FP state is not preserved across signal handlers. So signal
338 * handlers cannot afford to do FP unless they preserve the state or
339 * longjmp() out. Both preserving the state and longjmp()ing may be
340 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable
341 * solution for signals other than SIGFPE.
343 * The MP lock is not held on entry (see i386/i386/exception.s) and
344 * should not be held on exit. Interrupts are enabled. We must enter
345 * a critical section to stabilize the FP system and prevent an interrupt
346 * or preemption from changing the FP state out from under us.
349 npx_intr(void *dummy)
354 struct intrframe *frame;
359 * This exception can only occur with CR0_TS clear, otherwise we
360 * would get a DNA exception. However, since interrupts were
361 * enabled a preemption could have sneaked in and used the FP system
362 * before we entered our critical section. If that occured, the
363 * TS bit will be set and npxthread will be NULL.
365 panic("npx_intr: not coded");
366 /* XXX FP STATE FLAG MUST BE PART OF CONTEXT SUPPLIED BY REAL KERNEL */
368 if (rcr0() & CR0_TS) {
369 KASSERT(mdcpu->gd_npxthread == NULL, ("gd_npxthread was %p with TS set!", mdcpu->gd_npxthread));
375 if (mdcpu->gd_npxthread == NULL) {
377 kprintf("npxintr: npxthread = %p, curthread = %p\n",
378 mdcpu->gd_npxthread, curthread);
379 panic("npxintr from nowhere");
381 if (mdcpu->gd_npxthread != curthread) {
383 kprintf("npxintr: npxthread = %p, curthread = %p\n",
384 mdcpu->gd_npxthread, curthread);
385 panic("npxintr from non-current process");
396 * Pass exception to process.
398 frame = (struct intrframe *)&dummy; /* XXX */
399 if ((ISPL(frame->if_cs) == SEL_UPL) /*||(frame->if_eflags&PSL_VM)*/) {
401 * Interrupt is essentially a trap, so we can afford to call
402 * the SIGFPE handler (if any) as soon as the interrupt
405 * XXX little or nothing is gained from this, and plenty is
406 * lost - the interrupt frame has to contain the trap frame
407 * (this is otherwise only necessary for the rescheduling trap
408 * in doreti, and the frame for that could easily be set up
409 * just before it is used).
411 curthread->td_lwp->lwp_md.md_regs = INTR_TO_TRAPFRAME(frame);
413 * Encode the appropriate code for detailed information on
417 fpetable[(status & ~control & 0x3f) | (status & 0x40)];
418 trapsignal(curthread->td_lwp, SIGFPE, code);
421 * Nested interrupt. These losers occur when:
422 * o an IRQ13 is bogusly generated at a bogus time, e.g.:
423 * o immediately after an fnsave or frstor of an
425 * o a couple of 386 instructions after
426 * "fstpl _memvar" causes a stack overflow.
427 * These are especially nasty when combined with a
429 * o an IRQ13 occurs at the same time as another higher-
430 * priority interrupt.
432 * Treat them like a true async interrupt.
434 lwpsignal(curproc, curthread->td_lwp, SIGFPE);
443 * Implement the device not available (DNA) exception. gd_npxthread had
444 * better be NULL. Restore the current thread's FP state and set gd_npxthread
447 * Interrupts are enabled and preemption can occur. Enter a critical
448 * section to stabilize the FP state.
451 npxdna(struct trapframe *frame)
453 thread_t td = curthread;
456 if (mdcpu->gd_npxthread != NULL) {
457 kprintf("npxdna: npxthread = %p, curthread = %p\n",
458 mdcpu->gd_npxthread, td);
463 * Setup the initial saved state if the thread has never before
464 * used the FP unit. This also occurs when a thread pushes a
465 * signal handler and uses FP in the handler.
467 if ((curthread->td_flags & TDF_USINGFP) == 0) {
468 curthread->td_flags |= TDF_USINGFP;
469 npxinit(__INITIAL_NPXCW__);
474 * The setting of gd_npxthread and the call to fpurstor() must not
475 * be preempted by an interrupt thread or we will take an npxdna
476 * trap and potentially save our current fpstate (which is garbage)
477 * and then restore the garbage rather then the originally saved
481 /*stop_emulating();*/
483 * Record new context early in case frstor causes an IRQ13.
485 mdcpu->gd_npxthread = td;
487 * The following frstor may cause an IRQ13 when the state being
488 * restored has a pending error. The error will appear to have been
489 * triggered by the current (npx) user instruction even when that
490 * instruction is a no-wait instruction that should not trigger an
491 * error (e.g., fnclex). On at least one 486 system all of the
492 * no-wait instructions are broken the same as frstor, so our
493 * treatment does not amplify the breakage. On at least one
494 * 386/Cyrix 387 system, fnclex works correctly while frstor and
495 * fnsave are broken, so our treatment breaks fnclex if it is the
496 * first FPU instruction after a context switch.
498 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF) && cpu_fxsr) {
499 krateprintf(&badfprate,
500 "FXRSTR: illegal FP MXCSR %08x didinit = %d\n",
501 td->td_savefpu->sv_xmm.sv_env.en_mxcsr, didinit);
502 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF;
503 lwpsignal(curproc, curthread->td_lwp, SIGFPE);
505 fpurstor(curthread->td_savefpu);
512 * Wrapper for the fnsave instruction to handle h/w bugs. If there is an error
513 * pending, then fnsave generates a bogus IRQ13 on some systems. Force
514 * any IRQ13 to be handled immediately, and then ignore it. This routine is
515 * often called at splhigh so it must not use many system services. In
516 * particular, it's much easier to install a special handler than to
517 * guarantee that it's safe to use npxintr() and its supporting code.
519 * WARNING! This call is made during a switch and the MP lock will be
520 * setup for the new target thread rather then the current thread, so we
521 * cannot do anything here that depends on the *_mplock() functions as
522 * we may trip over their assertions.
524 * WARNING! When using fxsave we MUST fninit after saving the FP state. The
525 * kernel will always assume that the FP state is 'safe' (will not cause
526 * exceptions) for mmx/xmm use if npxthread is NULL. The kernel must still
527 * setup a custom save area before actually using the FP unit, but it will
528 * not bother calling fninit. This greatly improves kernel performance when
529 * it wishes to use the FP unit.
532 npxsave(union savefpu *addr)
535 /*stop_emulating();*/
537 mdcpu->gd_npxthread = NULL;
539 /*start_emulating();*/
544 fpusave(union savefpu *addr)
553 * Save the FP state to the mcontext structure.
555 * WARNING: If you want to try to npxsave() directly to mctx->mc_fpregs,
556 * then it MUST be 16-byte aligned. Currently this is not guarenteed.
559 npxpush(mcontext_t *mctx)
561 thread_t td = curthread;
563 if (td->td_flags & TDF_USINGFP) {
564 if (mdcpu->gd_npxthread == td) {
566 * XXX Note: This is a bit inefficient if the signal
567 * handler uses floating point, extra faults will
570 mctx->mc_ownedfp = _MC_FPOWNED_FPU;
571 npxsave(td->td_savefpu);
573 mctx->mc_ownedfp = _MC_FPOWNED_PCB;
575 bcopy(td->td_savefpu, mctx->mc_fpregs, sizeof(mctx->mc_fpregs));
576 td->td_flags &= ~TDF_USINGFP;
578 #ifndef CPU_DISABLE_SSE
579 (cpu_fxsr) ? _MC_FPFMT_XMM :
583 mctx->mc_ownedfp = _MC_FPOWNED_NONE;
584 mctx->mc_fpformat = _MC_FPFMT_NODEV;
589 * Restore the FP state from the mcontext structure.
592 npxpop(mcontext_t *mctx)
594 thread_t td = curthread;
596 switch(mctx->mc_ownedfp) {
597 case _MC_FPOWNED_NONE:
599 * If the signal handler used the FP unit but the interrupted
600 * code did not, release the FP unit. Clear TDF_USINGFP will
601 * force the FP unit to reinit so the interrupted code sees
604 if (td->td_flags & TDF_USINGFP) {
605 if (td == mdcpu->gd_npxthread)
606 npxsave(td->td_savefpu);
607 td->td_flags &= ~TDF_USINGFP;
610 case _MC_FPOWNED_FPU:
611 case _MC_FPOWNED_PCB:
613 * Clear ownership of the FP unit and restore our saved state.
615 * NOTE: The signal handler may have set-up some FP state and
616 * enabled the FP unit, so we have to restore no matter what.
618 * XXX: This is bit inefficient, if the code being returned
619 * to is actively using the FP this results in multiple
622 * WARNING: The saved state was exposed to userland and may
623 * have to be sanitized to avoid a GP fault in the kernel.
625 if (td == mdcpu->gd_npxthread)
626 npxsave(td->td_savefpu);
627 bcopy(mctx->mc_fpregs, td->td_savefpu, sizeof(*td->td_savefpu));
628 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF) &&
630 krateprintf(&badfprate,
631 "pid %d (%s) signal return from user: "
632 "illegal FP MXCSR %08x\n",
635 td->td_savefpu->sv_xmm.sv_env.en_mxcsr);
636 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF;
638 td->td_flags |= TDF_USINGFP;
644 #ifndef CPU_DISABLE_SSE
646 * On AuthenticAMD processors, the fxrstor instruction does not restore
647 * the x87's stored last instruction pointer, last data pointer, and last
648 * opcode values, except in the rare case in which the exception summary
649 * (ES) bit in the x87 status word is set to 1.
651 * In order to avoid leaking this information across processes, we clean
652 * these values by performing a dummy load before executing fxrstor().
654 static double dummy_variable = 0.0;
656 fpu_clean_state(void)
661 * Clear the ES bit in the x87 status word if it is currently
662 * set, in order to avoid causing a fault in the upcoming load.
669 * Load the dummy variable into the x87 stack. This mangles
670 * the x87 stack, but we don't care since we're about to call
673 __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable));
675 #endif /* CPU_DISABLE_SSE */
678 fpurstor(union savefpu *addr)
680 #ifndef CPU_DISABLE_SSE