1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
45 #include "basic-block.h"
48 #include "target-def.h"
49 #include "langhooks.h"
54 #include "tm-constrs.h"
58 static int x86_builtin_vectorization_cost (bool);
59 static rtx legitimize_dllimport_symbol (rtx, bool);
61 #ifndef CHECK_STACK_LIMIT
62 #define CHECK_STACK_LIMIT (-1)
65 /* Return index of given mode in mult and division cost tables. */
66 #define MODE_INDEX(mode) \
67 ((mode) == QImode ? 0 \
68 : (mode) == HImode ? 1 \
69 : (mode) == SImode ? 2 \
70 : (mode) == DImode ? 3 \
73 /* Processor costs (relative to an add) */
74 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
75 #define COSTS_N_BYTES(N) ((N) * 2)
77 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
80 struct processor_costs ix86_size_cost = {/* costs for tuning for size */
81 COSTS_N_BYTES (2), /* cost of an add instruction */
82 COSTS_N_BYTES (3), /* cost of a lea instruction */
83 COSTS_N_BYTES (2), /* variable shift costs */
84 COSTS_N_BYTES (3), /* constant shift costs */
85 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
86 COSTS_N_BYTES (3), /* HI */
87 COSTS_N_BYTES (3), /* SI */
88 COSTS_N_BYTES (3), /* DI */
89 COSTS_N_BYTES (5)}, /* other */
90 0, /* cost of multiply per each bit set */
91 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
92 COSTS_N_BYTES (3), /* HI */
93 COSTS_N_BYTES (3), /* SI */
94 COSTS_N_BYTES (3), /* DI */
95 COSTS_N_BYTES (5)}, /* other */
96 COSTS_N_BYTES (3), /* cost of movsx */
97 COSTS_N_BYTES (3), /* cost of movzx */
100 2, /* cost for loading QImode using movzbl */
101 {2, 2, 2}, /* cost of loading integer registers
102 in QImode, HImode and SImode.
103 Relative to reg-reg move (2). */
104 {2, 2, 2}, /* cost of storing integer registers */
105 2, /* cost of reg,reg fld/fst */
106 {2, 2, 2}, /* cost of loading fp registers
107 in SFmode, DFmode and XFmode */
108 {2, 2, 2}, /* cost of storing fp registers
109 in SFmode, DFmode and XFmode */
110 3, /* cost of moving MMX register */
111 {3, 3}, /* cost of loading MMX registers
112 in SImode and DImode */
113 {3, 3}, /* cost of storing MMX registers
114 in SImode and DImode */
115 3, /* cost of moving SSE register */
116 {3, 3, 3}, /* cost of loading SSE registers
117 in SImode, DImode and TImode */
118 {3, 3, 3}, /* cost of storing SSE registers
119 in SImode, DImode and TImode */
120 3, /* MMX or SSE register to integer */
121 0, /* size of l1 cache */
122 0, /* size of l2 cache */
123 0, /* size of prefetch block */
124 0, /* number of parallel prefetches */
126 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
127 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
128 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
129 COSTS_N_BYTES (2), /* cost of FABS instruction. */
130 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
131 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
132 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
133 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
134 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
135 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
136 1, /* scalar_stmt_cost. */
137 1, /* scalar load_cost. */
138 1, /* scalar_store_cost. */
139 1, /* vec_stmt_cost. */
140 1, /* vec_to_scalar_cost. */
141 1, /* scalar_to_vec_cost. */
142 1, /* vec_align_load_cost. */
143 1, /* vec_unalign_load_cost. */
144 1, /* vec_store_cost. */
145 1, /* cond_taken_branch_cost. */
146 1, /* cond_not_taken_branch_cost. */
149 /* Processor costs (relative to an add) */
151 struct processor_costs i386_cost = { /* 386 specific costs */
152 COSTS_N_INSNS (1), /* cost of an add instruction */
153 COSTS_N_INSNS (1), /* cost of a lea instruction */
154 COSTS_N_INSNS (3), /* variable shift costs */
155 COSTS_N_INSNS (2), /* constant shift costs */
156 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
157 COSTS_N_INSNS (6), /* HI */
158 COSTS_N_INSNS (6), /* SI */
159 COSTS_N_INSNS (6), /* DI */
160 COSTS_N_INSNS (6)}, /* other */
161 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
162 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
163 COSTS_N_INSNS (23), /* HI */
164 COSTS_N_INSNS (23), /* SI */
165 COSTS_N_INSNS (23), /* DI */
166 COSTS_N_INSNS (23)}, /* other */
167 COSTS_N_INSNS (3), /* cost of movsx */
168 COSTS_N_INSNS (2), /* cost of movzx */
169 15, /* "large" insn */
171 4, /* cost for loading QImode using movzbl */
172 {2, 4, 2}, /* cost of loading integer registers
173 in QImode, HImode and SImode.
174 Relative to reg-reg move (2). */
175 {2, 4, 2}, /* cost of storing integer registers */
176 2, /* cost of reg,reg fld/fst */
177 {8, 8, 8}, /* cost of loading fp registers
178 in SFmode, DFmode and XFmode */
179 {8, 8, 8}, /* cost of storing fp registers
180 in SFmode, DFmode and XFmode */
181 2, /* cost of moving MMX register */
182 {4, 8}, /* cost of loading MMX registers
183 in SImode and DImode */
184 {4, 8}, /* cost of storing MMX registers
185 in SImode and DImode */
186 2, /* cost of moving SSE register */
187 {4, 8, 16}, /* cost of loading SSE registers
188 in SImode, DImode and TImode */
189 {4, 8, 16}, /* cost of storing SSE registers
190 in SImode, DImode and TImode */
191 3, /* MMX or SSE register to integer */
192 0, /* size of l1 cache */
193 0, /* size of l2 cache */
194 0, /* size of prefetch block */
195 0, /* number of parallel prefetches */
197 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
198 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
199 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
200 COSTS_N_INSNS (22), /* cost of FABS instruction. */
201 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
202 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
203 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
204 DUMMY_STRINGOP_ALGS},
205 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
206 DUMMY_STRINGOP_ALGS},
207 1, /* scalar_stmt_cost. */
208 1, /* scalar load_cost. */
209 1, /* scalar_store_cost. */
210 1, /* vec_stmt_cost. */
211 1, /* vec_to_scalar_cost. */
212 1, /* scalar_to_vec_cost. */
213 1, /* vec_align_load_cost. */
214 2, /* vec_unalign_load_cost. */
215 1, /* vec_store_cost. */
216 3, /* cond_taken_branch_cost. */
217 1, /* cond_not_taken_branch_cost. */
221 struct processor_costs i486_cost = { /* 486 specific costs */
222 COSTS_N_INSNS (1), /* cost of an add instruction */
223 COSTS_N_INSNS (1), /* cost of a lea instruction */
224 COSTS_N_INSNS (3), /* variable shift costs */
225 COSTS_N_INSNS (2), /* constant shift costs */
226 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
227 COSTS_N_INSNS (12), /* HI */
228 COSTS_N_INSNS (12), /* SI */
229 COSTS_N_INSNS (12), /* DI */
230 COSTS_N_INSNS (12)}, /* other */
231 1, /* cost of multiply per each bit set */
232 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
233 COSTS_N_INSNS (40), /* HI */
234 COSTS_N_INSNS (40), /* SI */
235 COSTS_N_INSNS (40), /* DI */
236 COSTS_N_INSNS (40)}, /* other */
237 COSTS_N_INSNS (3), /* cost of movsx */
238 COSTS_N_INSNS (2), /* cost of movzx */
239 15, /* "large" insn */
241 4, /* cost for loading QImode using movzbl */
242 {2, 4, 2}, /* cost of loading integer registers
243 in QImode, HImode and SImode.
244 Relative to reg-reg move (2). */
245 {2, 4, 2}, /* cost of storing integer registers */
246 2, /* cost of reg,reg fld/fst */
247 {8, 8, 8}, /* cost of loading fp registers
248 in SFmode, DFmode and XFmode */
249 {8, 8, 8}, /* cost of storing fp registers
250 in SFmode, DFmode and XFmode */
251 2, /* cost of moving MMX register */
252 {4, 8}, /* cost of loading MMX registers
253 in SImode and DImode */
254 {4, 8}, /* cost of storing MMX registers
255 in SImode and DImode */
256 2, /* cost of moving SSE register */
257 {4, 8, 16}, /* cost of loading SSE registers
258 in SImode, DImode and TImode */
259 {4, 8, 16}, /* cost of storing SSE registers
260 in SImode, DImode and TImode */
261 3, /* MMX or SSE register to integer */
262 4, /* size of l1 cache. 486 has 8kB cache
263 shared for code and data, so 4kB is
264 not really precise. */
265 4, /* size of l2 cache */
266 0, /* size of prefetch block */
267 0, /* number of parallel prefetches */
269 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
270 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
271 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
272 COSTS_N_INSNS (3), /* cost of FABS instruction. */
273 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
274 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
275 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
276 DUMMY_STRINGOP_ALGS},
277 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
278 DUMMY_STRINGOP_ALGS},
279 1, /* scalar_stmt_cost. */
280 1, /* scalar load_cost. */
281 1, /* scalar_store_cost. */
282 1, /* vec_stmt_cost. */
283 1, /* vec_to_scalar_cost. */
284 1, /* scalar_to_vec_cost. */
285 1, /* vec_align_load_cost. */
286 2, /* vec_unalign_load_cost. */
287 1, /* vec_store_cost. */
288 3, /* cond_taken_branch_cost. */
289 1, /* cond_not_taken_branch_cost. */
293 struct processor_costs pentium_cost = {
294 COSTS_N_INSNS (1), /* cost of an add instruction */
295 COSTS_N_INSNS (1), /* cost of a lea instruction */
296 COSTS_N_INSNS (4), /* variable shift costs */
297 COSTS_N_INSNS (1), /* constant shift costs */
298 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
299 COSTS_N_INSNS (11), /* HI */
300 COSTS_N_INSNS (11), /* SI */
301 COSTS_N_INSNS (11), /* DI */
302 COSTS_N_INSNS (11)}, /* other */
303 0, /* cost of multiply per each bit set */
304 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
305 COSTS_N_INSNS (25), /* HI */
306 COSTS_N_INSNS (25), /* SI */
307 COSTS_N_INSNS (25), /* DI */
308 COSTS_N_INSNS (25)}, /* other */
309 COSTS_N_INSNS (3), /* cost of movsx */
310 COSTS_N_INSNS (2), /* cost of movzx */
311 8, /* "large" insn */
313 6, /* cost for loading QImode using movzbl */
314 {2, 4, 2}, /* cost of loading integer registers
315 in QImode, HImode and SImode.
316 Relative to reg-reg move (2). */
317 {2, 4, 2}, /* cost of storing integer registers */
318 2, /* cost of reg,reg fld/fst */
319 {2, 2, 6}, /* cost of loading fp registers
320 in SFmode, DFmode and XFmode */
321 {4, 4, 6}, /* cost of storing fp registers
322 in SFmode, DFmode and XFmode */
323 8, /* cost of moving MMX register */
324 {8, 8}, /* cost of loading MMX registers
325 in SImode and DImode */
326 {8, 8}, /* cost of storing MMX registers
327 in SImode and DImode */
328 2, /* cost of moving SSE register */
329 {4, 8, 16}, /* cost of loading SSE registers
330 in SImode, DImode and TImode */
331 {4, 8, 16}, /* cost of storing SSE registers
332 in SImode, DImode and TImode */
333 3, /* MMX or SSE register to integer */
334 8, /* size of l1 cache. */
335 8, /* size of l2 cache */
336 0, /* size of prefetch block */
337 0, /* number of parallel prefetches */
339 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
340 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
341 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
342 COSTS_N_INSNS (1), /* cost of FABS instruction. */
343 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
344 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
345 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
346 DUMMY_STRINGOP_ALGS},
347 {{libcall, {{-1, rep_prefix_4_byte}}},
348 DUMMY_STRINGOP_ALGS},
349 1, /* scalar_stmt_cost. */
350 1, /* scalar load_cost. */
351 1, /* scalar_store_cost. */
352 1, /* vec_stmt_cost. */
353 1, /* vec_to_scalar_cost. */
354 1, /* scalar_to_vec_cost. */
355 1, /* vec_align_load_cost. */
356 2, /* vec_unalign_load_cost. */
357 1, /* vec_store_cost. */
358 3, /* cond_taken_branch_cost. */
359 1, /* cond_not_taken_branch_cost. */
363 struct processor_costs pentiumpro_cost = {
364 COSTS_N_INSNS (1), /* cost of an add instruction */
365 COSTS_N_INSNS (1), /* cost of a lea instruction */
366 COSTS_N_INSNS (1), /* variable shift costs */
367 COSTS_N_INSNS (1), /* constant shift costs */
368 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
369 COSTS_N_INSNS (4), /* HI */
370 COSTS_N_INSNS (4), /* SI */
371 COSTS_N_INSNS (4), /* DI */
372 COSTS_N_INSNS (4)}, /* other */
373 0, /* cost of multiply per each bit set */
374 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
375 COSTS_N_INSNS (17), /* HI */
376 COSTS_N_INSNS (17), /* SI */
377 COSTS_N_INSNS (17), /* DI */
378 COSTS_N_INSNS (17)}, /* other */
379 COSTS_N_INSNS (1), /* cost of movsx */
380 COSTS_N_INSNS (1), /* cost of movzx */
381 8, /* "large" insn */
383 2, /* cost for loading QImode using movzbl */
384 {4, 4, 4}, /* cost of loading integer registers
385 in QImode, HImode and SImode.
386 Relative to reg-reg move (2). */
387 {2, 2, 2}, /* cost of storing integer registers */
388 2, /* cost of reg,reg fld/fst */
389 {2, 2, 6}, /* cost of loading fp registers
390 in SFmode, DFmode and XFmode */
391 {4, 4, 6}, /* cost of storing fp registers
392 in SFmode, DFmode and XFmode */
393 2, /* cost of moving MMX register */
394 {2, 2}, /* cost of loading MMX registers
395 in SImode and DImode */
396 {2, 2}, /* cost of storing MMX registers
397 in SImode and DImode */
398 2, /* cost of moving SSE register */
399 {2, 2, 8}, /* cost of loading SSE registers
400 in SImode, DImode and TImode */
401 {2, 2, 8}, /* cost of storing SSE registers
402 in SImode, DImode and TImode */
403 3, /* MMX or SSE register to integer */
404 8, /* size of l1 cache. */
405 256, /* size of l2 cache */
406 32, /* size of prefetch block */
407 6, /* number of parallel prefetches */
409 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
410 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
411 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
412 COSTS_N_INSNS (2), /* cost of FABS instruction. */
413 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
414 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
415 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
416 the alignment). For small blocks inline loop is still a noticeable win, for bigger
417 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
418 more expensive startup time in CPU, but after 4K the difference is down in the noise.
420 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
421 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
422 DUMMY_STRINGOP_ALGS},
423 {{rep_prefix_4_byte, {{1024, unrolled_loop},
424 {8192, rep_prefix_4_byte}, {-1, libcall}}},
425 DUMMY_STRINGOP_ALGS},
426 1, /* scalar_stmt_cost. */
427 1, /* scalar load_cost. */
428 1, /* scalar_store_cost. */
429 1, /* vec_stmt_cost. */
430 1, /* vec_to_scalar_cost. */
431 1, /* scalar_to_vec_cost. */
432 1, /* vec_align_load_cost. */
433 2, /* vec_unalign_load_cost. */
434 1, /* vec_store_cost. */
435 3, /* cond_taken_branch_cost. */
436 1, /* cond_not_taken_branch_cost. */
440 struct processor_costs geode_cost = {
441 COSTS_N_INSNS (1), /* cost of an add instruction */
442 COSTS_N_INSNS (1), /* cost of a lea instruction */
443 COSTS_N_INSNS (2), /* variable shift costs */
444 COSTS_N_INSNS (1), /* constant shift costs */
445 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
446 COSTS_N_INSNS (4), /* HI */
447 COSTS_N_INSNS (7), /* SI */
448 COSTS_N_INSNS (7), /* DI */
449 COSTS_N_INSNS (7)}, /* other */
450 0, /* cost of multiply per each bit set */
451 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
452 COSTS_N_INSNS (23), /* HI */
453 COSTS_N_INSNS (39), /* SI */
454 COSTS_N_INSNS (39), /* DI */
455 COSTS_N_INSNS (39)}, /* other */
456 COSTS_N_INSNS (1), /* cost of movsx */
457 COSTS_N_INSNS (1), /* cost of movzx */
458 8, /* "large" insn */
460 1, /* cost for loading QImode using movzbl */
461 {1, 1, 1}, /* cost of loading integer registers
462 in QImode, HImode and SImode.
463 Relative to reg-reg move (2). */
464 {1, 1, 1}, /* cost of storing integer registers */
465 1, /* cost of reg,reg fld/fst */
466 {1, 1, 1}, /* cost of loading fp registers
467 in SFmode, DFmode and XFmode */
468 {4, 6, 6}, /* cost of storing fp registers
469 in SFmode, DFmode and XFmode */
471 1, /* cost of moving MMX register */
472 {1, 1}, /* cost of loading MMX registers
473 in SImode and DImode */
474 {1, 1}, /* cost of storing MMX registers
475 in SImode and DImode */
476 1, /* cost of moving SSE register */
477 {1, 1, 1}, /* cost of loading SSE registers
478 in SImode, DImode and TImode */
479 {1, 1, 1}, /* cost of storing SSE registers
480 in SImode, DImode and TImode */
481 1, /* MMX or SSE register to integer */
482 64, /* size of l1 cache. */
483 128, /* size of l2 cache. */
484 32, /* size of prefetch block */
485 1, /* number of parallel prefetches */
487 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
488 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
489 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
490 COSTS_N_INSNS (1), /* cost of FABS instruction. */
491 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
492 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
493 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
494 DUMMY_STRINGOP_ALGS},
495 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
496 DUMMY_STRINGOP_ALGS},
497 1, /* scalar_stmt_cost. */
498 1, /* scalar load_cost. */
499 1, /* scalar_store_cost. */
500 1, /* vec_stmt_cost. */
501 1, /* vec_to_scalar_cost. */
502 1, /* scalar_to_vec_cost. */
503 1, /* vec_align_load_cost. */
504 2, /* vec_unalign_load_cost. */
505 1, /* vec_store_cost. */
506 3, /* cond_taken_branch_cost. */
507 1, /* cond_not_taken_branch_cost. */
511 struct processor_costs k6_cost = {
512 COSTS_N_INSNS (1), /* cost of an add instruction */
513 COSTS_N_INSNS (2), /* cost of a lea instruction */
514 COSTS_N_INSNS (1), /* variable shift costs */
515 COSTS_N_INSNS (1), /* constant shift costs */
516 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
517 COSTS_N_INSNS (3), /* HI */
518 COSTS_N_INSNS (3), /* SI */
519 COSTS_N_INSNS (3), /* DI */
520 COSTS_N_INSNS (3)}, /* other */
521 0, /* cost of multiply per each bit set */
522 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
523 COSTS_N_INSNS (18), /* HI */
524 COSTS_N_INSNS (18), /* SI */
525 COSTS_N_INSNS (18), /* DI */
526 COSTS_N_INSNS (18)}, /* other */
527 COSTS_N_INSNS (2), /* cost of movsx */
528 COSTS_N_INSNS (2), /* cost of movzx */
529 8, /* "large" insn */
531 3, /* cost for loading QImode using movzbl */
532 {4, 5, 4}, /* cost of loading integer registers
533 in QImode, HImode and SImode.
534 Relative to reg-reg move (2). */
535 {2, 3, 2}, /* cost of storing integer registers */
536 4, /* cost of reg,reg fld/fst */
537 {6, 6, 6}, /* cost of loading fp registers
538 in SFmode, DFmode and XFmode */
539 {4, 4, 4}, /* cost of storing fp registers
540 in SFmode, DFmode and XFmode */
541 2, /* cost of moving MMX register */
542 {2, 2}, /* cost of loading MMX registers
543 in SImode and DImode */
544 {2, 2}, /* cost of storing MMX registers
545 in SImode and DImode */
546 2, /* cost of moving SSE register */
547 {2, 2, 8}, /* cost of loading SSE registers
548 in SImode, DImode and TImode */
549 {2, 2, 8}, /* cost of storing SSE registers
550 in SImode, DImode and TImode */
551 6, /* MMX or SSE register to integer */
552 32, /* size of l1 cache. */
553 32, /* size of l2 cache. Some models
554 have integrated l2 cache, but
555 optimizing for k6 is not important
556 enough to worry about that. */
557 32, /* size of prefetch block */
558 1, /* number of parallel prefetches */
560 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
561 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
562 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
563 COSTS_N_INSNS (2), /* cost of FABS instruction. */
564 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
565 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
566 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
567 DUMMY_STRINGOP_ALGS},
568 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
569 DUMMY_STRINGOP_ALGS},
570 1, /* scalar_stmt_cost. */
571 1, /* scalar load_cost. */
572 1, /* scalar_store_cost. */
573 1, /* vec_stmt_cost. */
574 1, /* vec_to_scalar_cost. */
575 1, /* scalar_to_vec_cost. */
576 1, /* vec_align_load_cost. */
577 2, /* vec_unalign_load_cost. */
578 1, /* vec_store_cost. */
579 3, /* cond_taken_branch_cost. */
580 1, /* cond_not_taken_branch_cost. */
584 struct processor_costs athlon_cost = {
585 COSTS_N_INSNS (1), /* cost of an add instruction */
586 COSTS_N_INSNS (2), /* cost of a lea instruction */
587 COSTS_N_INSNS (1), /* variable shift costs */
588 COSTS_N_INSNS (1), /* constant shift costs */
589 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
590 COSTS_N_INSNS (5), /* HI */
591 COSTS_N_INSNS (5), /* SI */
592 COSTS_N_INSNS (5), /* DI */
593 COSTS_N_INSNS (5)}, /* other */
594 0, /* cost of multiply per each bit set */
595 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
596 COSTS_N_INSNS (26), /* HI */
597 COSTS_N_INSNS (42), /* SI */
598 COSTS_N_INSNS (74), /* DI */
599 COSTS_N_INSNS (74)}, /* other */
600 COSTS_N_INSNS (1), /* cost of movsx */
601 COSTS_N_INSNS (1), /* cost of movzx */
602 8, /* "large" insn */
604 4, /* cost for loading QImode using movzbl */
605 {3, 4, 3}, /* cost of loading integer registers
606 in QImode, HImode and SImode.
607 Relative to reg-reg move (2). */
608 {3, 4, 3}, /* cost of storing integer registers */
609 4, /* cost of reg,reg fld/fst */
610 {4, 4, 12}, /* cost of loading fp registers
611 in SFmode, DFmode and XFmode */
612 {6, 6, 8}, /* cost of storing fp registers
613 in SFmode, DFmode and XFmode */
614 2, /* cost of moving MMX register */
615 {4, 4}, /* cost of loading MMX registers
616 in SImode and DImode */
617 {4, 4}, /* cost of storing MMX registers
618 in SImode and DImode */
619 2, /* cost of moving SSE register */
620 {4, 4, 6}, /* cost of loading SSE registers
621 in SImode, DImode and TImode */
622 {4, 4, 5}, /* cost of storing SSE registers
623 in SImode, DImode and TImode */
624 5, /* MMX or SSE register to integer */
625 64, /* size of l1 cache. */
626 256, /* size of l2 cache. */
627 64, /* size of prefetch block */
628 6, /* number of parallel prefetches */
630 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
631 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
632 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
633 COSTS_N_INSNS (2), /* cost of FABS instruction. */
634 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
635 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
636 /* For some reason, Athlon deals better with REP prefix (relative to loops)
637 compared to K8. Alignment becomes important after 8 bytes for memcpy and
638 128 bytes for memset. */
639 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
640 DUMMY_STRINGOP_ALGS},
641 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
642 DUMMY_STRINGOP_ALGS},
643 1, /* scalar_stmt_cost. */
644 1, /* scalar load_cost. */
645 1, /* scalar_store_cost. */
646 1, /* vec_stmt_cost. */
647 1, /* vec_to_scalar_cost. */
648 1, /* scalar_to_vec_cost. */
649 1, /* vec_align_load_cost. */
650 2, /* vec_unalign_load_cost. */
651 1, /* vec_store_cost. */
652 3, /* cond_taken_branch_cost. */
653 1, /* cond_not_taken_branch_cost. */
657 struct processor_costs k8_cost = {
658 COSTS_N_INSNS (1), /* cost of an add instruction */
659 COSTS_N_INSNS (2), /* cost of a lea instruction */
660 COSTS_N_INSNS (1), /* variable shift costs */
661 COSTS_N_INSNS (1), /* constant shift costs */
662 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
663 COSTS_N_INSNS (4), /* HI */
664 COSTS_N_INSNS (3), /* SI */
665 COSTS_N_INSNS (4), /* DI */
666 COSTS_N_INSNS (5)}, /* other */
667 0, /* cost of multiply per each bit set */
668 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
669 COSTS_N_INSNS (26), /* HI */
670 COSTS_N_INSNS (42), /* SI */
671 COSTS_N_INSNS (74), /* DI */
672 COSTS_N_INSNS (74)}, /* other */
673 COSTS_N_INSNS (1), /* cost of movsx */
674 COSTS_N_INSNS (1), /* cost of movzx */
675 8, /* "large" insn */
677 4, /* cost for loading QImode using movzbl */
678 {3, 4, 3}, /* cost of loading integer registers
679 in QImode, HImode and SImode.
680 Relative to reg-reg move (2). */
681 {3, 4, 3}, /* cost of storing integer registers */
682 4, /* cost of reg,reg fld/fst */
683 {4, 4, 12}, /* cost of loading fp registers
684 in SFmode, DFmode and XFmode */
685 {6, 6, 8}, /* cost of storing fp registers
686 in SFmode, DFmode and XFmode */
687 2, /* cost of moving MMX register */
688 {3, 3}, /* cost of loading MMX registers
689 in SImode and DImode */
690 {4, 4}, /* cost of storing MMX registers
691 in SImode and DImode */
692 2, /* cost of moving SSE register */
693 {4, 3, 6}, /* cost of loading SSE registers
694 in SImode, DImode and TImode */
695 {4, 4, 5}, /* cost of storing SSE registers
696 in SImode, DImode and TImode */
697 5, /* MMX or SSE register to integer */
698 64, /* size of l1 cache. */
699 512, /* size of l2 cache. */
700 64, /* size of prefetch block */
701 /* New AMD processors never drop prefetches; if they cannot be performed
702 immediately, they are queued. We set number of simultaneous prefetches
703 to a large constant to reflect this (it probably is not a good idea not
704 to limit number of prefetches at all, as their execution also takes some
706 100, /* number of parallel prefetches */
708 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
709 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
710 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
711 COSTS_N_INSNS (2), /* cost of FABS instruction. */
712 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
713 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
714 /* K8 has optimized REP instruction for medium sized blocks, but for very small
715 blocks it is better to use loop. For large blocks, libcall can do
716 nontemporary accesses and beat inline considerably. */
717 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
718 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
719 {{libcall, {{8, loop}, {24, unrolled_loop},
720 {2048, rep_prefix_4_byte}, {-1, libcall}}},
721 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
722 4, /* scalar_stmt_cost. */
723 2, /* scalar load_cost. */
724 2, /* scalar_store_cost. */
725 5, /* vec_stmt_cost. */
726 0, /* vec_to_scalar_cost. */
727 2, /* scalar_to_vec_cost. */
728 2, /* vec_align_load_cost. */
729 3, /* vec_unalign_load_cost. */
730 3, /* vec_store_cost. */
731 3, /* cond_taken_branch_cost. */
732 2, /* cond_not_taken_branch_cost. */
735 struct processor_costs amdfam10_cost = {
736 COSTS_N_INSNS (1), /* cost of an add instruction */
737 COSTS_N_INSNS (2), /* cost of a lea instruction */
738 COSTS_N_INSNS (1), /* variable shift costs */
739 COSTS_N_INSNS (1), /* constant shift costs */
740 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
741 COSTS_N_INSNS (4), /* HI */
742 COSTS_N_INSNS (3), /* SI */
743 COSTS_N_INSNS (4), /* DI */
744 COSTS_N_INSNS (5)}, /* other */
745 0, /* cost of multiply per each bit set */
746 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
747 COSTS_N_INSNS (35), /* HI */
748 COSTS_N_INSNS (51), /* SI */
749 COSTS_N_INSNS (83), /* DI */
750 COSTS_N_INSNS (83)}, /* other */
751 COSTS_N_INSNS (1), /* cost of movsx */
752 COSTS_N_INSNS (1), /* cost of movzx */
753 8, /* "large" insn */
755 4, /* cost for loading QImode using movzbl */
756 {3, 4, 3}, /* cost of loading integer registers
757 in QImode, HImode and SImode.
758 Relative to reg-reg move (2). */
759 {3, 4, 3}, /* cost of storing integer registers */
760 4, /* cost of reg,reg fld/fst */
761 {4, 4, 12}, /* cost of loading fp registers
762 in SFmode, DFmode and XFmode */
763 {6, 6, 8}, /* cost of storing fp registers
764 in SFmode, DFmode and XFmode */
765 2, /* cost of moving MMX register */
766 {3, 3}, /* cost of loading MMX registers
767 in SImode and DImode */
768 {4, 4}, /* cost of storing MMX registers
769 in SImode and DImode */
770 2, /* cost of moving SSE register */
771 {4, 4, 3}, /* cost of loading SSE registers
772 in SImode, DImode and TImode */
773 {4, 4, 5}, /* cost of storing SSE registers
774 in SImode, DImode and TImode */
775 3, /* MMX or SSE register to integer */
777 MOVD reg64, xmmreg Double FSTORE 4
778 MOVD reg32, xmmreg Double FSTORE 4
780 MOVD reg64, xmmreg Double FADD 3
782 MOVD reg32, xmmreg Double FADD 3
784 64, /* size of l1 cache. */
785 512, /* size of l2 cache. */
786 64, /* size of prefetch block */
787 /* New AMD processors never drop prefetches; if they cannot be performed
788 immediately, they are queued. We set number of simultaneous prefetches
789 to a large constant to reflect this (it probably is not a good idea not
790 to limit number of prefetches at all, as their execution also takes some
792 100, /* number of parallel prefetches */
794 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
795 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
796 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
797 COSTS_N_INSNS (2), /* cost of FABS instruction. */
798 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
799 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
801 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
802 very small blocks it is better to use loop. For large blocks, libcall can
803 do nontemporary accesses and beat inline considerably. */
804 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
805 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
806 {{libcall, {{8, loop}, {24, unrolled_loop},
807 {2048, rep_prefix_4_byte}, {-1, libcall}}},
808 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
809 4, /* scalar_stmt_cost. */
810 2, /* scalar load_cost. */
811 2, /* scalar_store_cost. */
812 6, /* vec_stmt_cost. */
813 0, /* vec_to_scalar_cost. */
814 2, /* scalar_to_vec_cost. */
815 2, /* vec_align_load_cost. */
816 2, /* vec_unalign_load_cost. */
817 2, /* vec_store_cost. */
818 2, /* cond_taken_branch_cost. */
819 1, /* cond_not_taken_branch_cost. */
823 struct processor_costs pentium4_cost = {
824 COSTS_N_INSNS (1), /* cost of an add instruction */
825 COSTS_N_INSNS (3), /* cost of a lea instruction */
826 COSTS_N_INSNS (4), /* variable shift costs */
827 COSTS_N_INSNS (4), /* constant shift costs */
828 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
829 COSTS_N_INSNS (15), /* HI */
830 COSTS_N_INSNS (15), /* SI */
831 COSTS_N_INSNS (15), /* DI */
832 COSTS_N_INSNS (15)}, /* other */
833 0, /* cost of multiply per each bit set */
834 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
835 COSTS_N_INSNS (56), /* HI */
836 COSTS_N_INSNS (56), /* SI */
837 COSTS_N_INSNS (56), /* DI */
838 COSTS_N_INSNS (56)}, /* other */
839 COSTS_N_INSNS (1), /* cost of movsx */
840 COSTS_N_INSNS (1), /* cost of movzx */
841 16, /* "large" insn */
843 2, /* cost for loading QImode using movzbl */
844 {4, 5, 4}, /* cost of loading integer registers
845 in QImode, HImode and SImode.
846 Relative to reg-reg move (2). */
847 {2, 3, 2}, /* cost of storing integer registers */
848 2, /* cost of reg,reg fld/fst */
849 {2, 2, 6}, /* cost of loading fp registers
850 in SFmode, DFmode and XFmode */
851 {4, 4, 6}, /* cost of storing fp registers
852 in SFmode, DFmode and XFmode */
853 2, /* cost of moving MMX register */
854 {2, 2}, /* cost of loading MMX registers
855 in SImode and DImode */
856 {2, 2}, /* cost of storing MMX registers
857 in SImode and DImode */
858 12, /* cost of moving SSE register */
859 {12, 12, 12}, /* cost of loading SSE registers
860 in SImode, DImode and TImode */
861 {2, 2, 8}, /* cost of storing SSE registers
862 in SImode, DImode and TImode */
863 10, /* MMX or SSE register to integer */
864 8, /* size of l1 cache. */
865 256, /* size of l2 cache. */
866 64, /* size of prefetch block */
867 6, /* number of parallel prefetches */
869 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
870 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
871 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
872 COSTS_N_INSNS (2), /* cost of FABS instruction. */
873 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
874 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
875 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
876 DUMMY_STRINGOP_ALGS},
877 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
879 DUMMY_STRINGOP_ALGS},
880 1, /* scalar_stmt_cost. */
881 1, /* scalar load_cost. */
882 1, /* scalar_store_cost. */
883 1, /* vec_stmt_cost. */
884 1, /* vec_to_scalar_cost. */
885 1, /* scalar_to_vec_cost. */
886 1, /* vec_align_load_cost. */
887 2, /* vec_unalign_load_cost. */
888 1, /* vec_store_cost. */
889 3, /* cond_taken_branch_cost. */
890 1, /* cond_not_taken_branch_cost. */
894 struct processor_costs nocona_cost = {
895 COSTS_N_INSNS (1), /* cost of an add instruction */
896 COSTS_N_INSNS (1), /* cost of a lea instruction */
897 COSTS_N_INSNS (1), /* variable shift costs */
898 COSTS_N_INSNS (1), /* constant shift costs */
899 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
900 COSTS_N_INSNS (10), /* HI */
901 COSTS_N_INSNS (10), /* SI */
902 COSTS_N_INSNS (10), /* DI */
903 COSTS_N_INSNS (10)}, /* other */
904 0, /* cost of multiply per each bit set */
905 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
906 COSTS_N_INSNS (66), /* HI */
907 COSTS_N_INSNS (66), /* SI */
908 COSTS_N_INSNS (66), /* DI */
909 COSTS_N_INSNS (66)}, /* other */
910 COSTS_N_INSNS (1), /* cost of movsx */
911 COSTS_N_INSNS (1), /* cost of movzx */
912 16, /* "large" insn */
914 4, /* cost for loading QImode using movzbl */
915 {4, 4, 4}, /* cost of loading integer registers
916 in QImode, HImode and SImode.
917 Relative to reg-reg move (2). */
918 {4, 4, 4}, /* cost of storing integer registers */
919 3, /* cost of reg,reg fld/fst */
920 {12, 12, 12}, /* cost of loading fp registers
921 in SFmode, DFmode and XFmode */
922 {4, 4, 4}, /* cost of storing fp registers
923 in SFmode, DFmode and XFmode */
924 6, /* cost of moving MMX register */
925 {12, 12}, /* cost of loading MMX registers
926 in SImode and DImode */
927 {12, 12}, /* cost of storing MMX registers
928 in SImode and DImode */
929 6, /* cost of moving SSE register */
930 {12, 12, 12}, /* cost of loading SSE registers
931 in SImode, DImode and TImode */
932 {12, 12, 12}, /* cost of storing SSE registers
933 in SImode, DImode and TImode */
934 8, /* MMX or SSE register to integer */
935 8, /* size of l1 cache. */
936 1024, /* size of l2 cache. */
937 128, /* size of prefetch block */
938 8, /* number of parallel prefetches */
940 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
941 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
942 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
943 COSTS_N_INSNS (3), /* cost of FABS instruction. */
944 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
945 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
946 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
947 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
948 {100000, unrolled_loop}, {-1, libcall}}}},
949 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
951 {libcall, {{24, loop}, {64, unrolled_loop},
952 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
953 1, /* scalar_stmt_cost. */
954 1, /* scalar load_cost. */
955 1, /* scalar_store_cost. */
956 1, /* vec_stmt_cost. */
957 1, /* vec_to_scalar_cost. */
958 1, /* scalar_to_vec_cost. */
959 1, /* vec_align_load_cost. */
960 2, /* vec_unalign_load_cost. */
961 1, /* vec_store_cost. */
962 3, /* cond_taken_branch_cost. */
963 1, /* cond_not_taken_branch_cost. */
967 struct processor_costs core2_cost = {
968 COSTS_N_INSNS (1), /* cost of an add instruction */
969 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
970 COSTS_N_INSNS (1), /* variable shift costs */
971 COSTS_N_INSNS (1), /* constant shift costs */
972 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
973 COSTS_N_INSNS (3), /* HI */
974 COSTS_N_INSNS (3), /* SI */
975 COSTS_N_INSNS (3), /* DI */
976 COSTS_N_INSNS (3)}, /* other */
977 0, /* cost of multiply per each bit set */
978 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
979 COSTS_N_INSNS (22), /* HI */
980 COSTS_N_INSNS (22), /* SI */
981 COSTS_N_INSNS (22), /* DI */
982 COSTS_N_INSNS (22)}, /* other */
983 COSTS_N_INSNS (1), /* cost of movsx */
984 COSTS_N_INSNS (1), /* cost of movzx */
985 8, /* "large" insn */
987 2, /* cost for loading QImode using movzbl */
988 {6, 6, 6}, /* cost of loading integer registers
989 in QImode, HImode and SImode.
990 Relative to reg-reg move (2). */
991 {4, 4, 4}, /* cost of storing integer registers */
992 2, /* cost of reg,reg fld/fst */
993 {6, 6, 6}, /* cost of loading fp registers
994 in SFmode, DFmode and XFmode */
995 {4, 4, 4}, /* cost of storing fp registers
996 in SFmode, DFmode and XFmode */
997 2, /* cost of moving MMX register */
998 {6, 6}, /* cost of loading MMX registers
999 in SImode and DImode */
1000 {4, 4}, /* cost of storing MMX registers
1001 in SImode and DImode */
1002 2, /* cost of moving SSE register */
1003 {6, 6, 6}, /* cost of loading SSE registers
1004 in SImode, DImode and TImode */
1005 {4, 4, 4}, /* cost of storing SSE registers
1006 in SImode, DImode and TImode */
1007 2, /* MMX or SSE register to integer */
1008 32, /* size of l1 cache. */
1009 2048, /* size of l2 cache. */
1010 128, /* size of prefetch block */
1011 8, /* number of parallel prefetches */
1012 3, /* Branch cost */
1013 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1014 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1015 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1016 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1017 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1018 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1019 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1020 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1021 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1022 {{libcall, {{8, loop}, {15, unrolled_loop},
1023 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1024 {libcall, {{24, loop}, {32, unrolled_loop},
1025 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1026 1, /* scalar_stmt_cost. */
1027 1, /* scalar load_cost. */
1028 1, /* scalar_store_cost. */
1029 1, /* vec_stmt_cost. */
1030 1, /* vec_to_scalar_cost. */
1031 1, /* scalar_to_vec_cost. */
1032 1, /* vec_align_load_cost. */
1033 2, /* vec_unalign_load_cost. */
1034 1, /* vec_store_cost. */
1035 3, /* cond_taken_branch_cost. */
1036 1, /* cond_not_taken_branch_cost. */
1039 /* Generic64 should produce code tuned for Nocona and K8. */
1041 struct processor_costs generic64_cost = {
1042 COSTS_N_INSNS (1), /* cost of an add instruction */
1043 /* On all chips taken into consideration lea is 2 cycles and more. With
1044 this cost however our current implementation of synth_mult results in
1045 use of unnecessary temporary registers causing regression on several
1046 SPECfp benchmarks. */
1047 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1048 COSTS_N_INSNS (1), /* variable shift costs */
1049 COSTS_N_INSNS (1), /* constant shift costs */
1050 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1051 COSTS_N_INSNS (4), /* HI */
1052 COSTS_N_INSNS (3), /* SI */
1053 COSTS_N_INSNS (4), /* DI */
1054 COSTS_N_INSNS (2)}, /* other */
1055 0, /* cost of multiply per each bit set */
1056 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1057 COSTS_N_INSNS (26), /* HI */
1058 COSTS_N_INSNS (42), /* SI */
1059 COSTS_N_INSNS (74), /* DI */
1060 COSTS_N_INSNS (74)}, /* other */
1061 COSTS_N_INSNS (1), /* cost of movsx */
1062 COSTS_N_INSNS (1), /* cost of movzx */
1063 8, /* "large" insn */
1064 17, /* MOVE_RATIO */
1065 4, /* cost for loading QImode using movzbl */
1066 {4, 4, 4}, /* cost of loading integer registers
1067 in QImode, HImode and SImode.
1068 Relative to reg-reg move (2). */
1069 {4, 4, 4}, /* cost of storing integer registers */
1070 4, /* cost of reg,reg fld/fst */
1071 {12, 12, 12}, /* cost of loading fp registers
1072 in SFmode, DFmode and XFmode */
1073 {6, 6, 8}, /* cost of storing fp registers
1074 in SFmode, DFmode and XFmode */
1075 2, /* cost of moving MMX register */
1076 {8, 8}, /* cost of loading MMX registers
1077 in SImode and DImode */
1078 {8, 8}, /* cost of storing MMX registers
1079 in SImode and DImode */
1080 2, /* cost of moving SSE register */
1081 {8, 8, 8}, /* cost of loading SSE registers
1082 in SImode, DImode and TImode */
1083 {8, 8, 8}, /* cost of storing SSE registers
1084 in SImode, DImode and TImode */
1085 5, /* MMX or SSE register to integer */
1086 32, /* size of l1 cache. */
1087 512, /* size of l2 cache. */
1088 64, /* size of prefetch block */
1089 6, /* number of parallel prefetches */
1090 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1091 is increased to perhaps more appropriate value of 5. */
1092 3, /* Branch cost */
1093 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1094 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1095 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1096 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1097 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1098 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1099 {DUMMY_STRINGOP_ALGS,
1100 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1101 {DUMMY_STRINGOP_ALGS,
1102 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1103 1, /* scalar_stmt_cost. */
1104 1, /* scalar load_cost. */
1105 1, /* scalar_store_cost. */
1106 1, /* vec_stmt_cost. */
1107 1, /* vec_to_scalar_cost. */
1108 1, /* scalar_to_vec_cost. */
1109 1, /* vec_align_load_cost. */
1110 2, /* vec_unalign_load_cost. */
1111 1, /* vec_store_cost. */
1112 3, /* cond_taken_branch_cost. */
1113 1, /* cond_not_taken_branch_cost. */
1116 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1118 struct processor_costs generic32_cost = {
1119 COSTS_N_INSNS (1), /* cost of an add instruction */
1120 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1121 COSTS_N_INSNS (1), /* variable shift costs */
1122 COSTS_N_INSNS (1), /* constant shift costs */
1123 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1124 COSTS_N_INSNS (4), /* HI */
1125 COSTS_N_INSNS (3), /* SI */
1126 COSTS_N_INSNS (4), /* DI */
1127 COSTS_N_INSNS (2)}, /* other */
1128 0, /* cost of multiply per each bit set */
1129 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1130 COSTS_N_INSNS (26), /* HI */
1131 COSTS_N_INSNS (42), /* SI */
1132 COSTS_N_INSNS (74), /* DI */
1133 COSTS_N_INSNS (74)}, /* other */
1134 COSTS_N_INSNS (1), /* cost of movsx */
1135 COSTS_N_INSNS (1), /* cost of movzx */
1136 8, /* "large" insn */
1137 17, /* MOVE_RATIO */
1138 4, /* cost for loading QImode using movzbl */
1139 {4, 4, 4}, /* cost of loading integer registers
1140 in QImode, HImode and SImode.
1141 Relative to reg-reg move (2). */
1142 {4, 4, 4}, /* cost of storing integer registers */
1143 4, /* cost of reg,reg fld/fst */
1144 {12, 12, 12}, /* cost of loading fp registers
1145 in SFmode, DFmode and XFmode */
1146 {6, 6, 8}, /* cost of storing fp registers
1147 in SFmode, DFmode and XFmode */
1148 2, /* cost of moving MMX register */
1149 {8, 8}, /* cost of loading MMX registers
1150 in SImode and DImode */
1151 {8, 8}, /* cost of storing MMX registers
1152 in SImode and DImode */
1153 2, /* cost of moving SSE register */
1154 {8, 8, 8}, /* cost of loading SSE registers
1155 in SImode, DImode and TImode */
1156 {8, 8, 8}, /* cost of storing SSE registers
1157 in SImode, DImode and TImode */
1158 5, /* MMX or SSE register to integer */
1159 32, /* size of l1 cache. */
1160 256, /* size of l2 cache. */
1161 64, /* size of prefetch block */
1162 6, /* number of parallel prefetches */
1163 3, /* Branch cost */
1164 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1165 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1166 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1167 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1168 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1169 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1170 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1171 DUMMY_STRINGOP_ALGS},
1172 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1173 DUMMY_STRINGOP_ALGS},
1174 1, /* scalar_stmt_cost. */
1175 1, /* scalar load_cost. */
1176 1, /* scalar_store_cost. */
1177 1, /* vec_stmt_cost. */
1178 1, /* vec_to_scalar_cost. */
1179 1, /* scalar_to_vec_cost. */
1180 1, /* vec_align_load_cost. */
1181 2, /* vec_unalign_load_cost. */
1182 1, /* vec_store_cost. */
1183 3, /* cond_taken_branch_cost. */
1184 1, /* cond_not_taken_branch_cost. */
1187 const struct processor_costs *ix86_cost = &pentium_cost;
1189 /* Processor feature/optimization bitmasks. */
1190 #define m_386 (1<<PROCESSOR_I386)
1191 #define m_486 (1<<PROCESSOR_I486)
1192 #define m_PENT (1<<PROCESSOR_PENTIUM)
1193 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1194 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1195 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1196 #define m_CORE2 (1<<PROCESSOR_CORE2)
1198 #define m_GEODE (1<<PROCESSOR_GEODE)
1199 #define m_K6 (1<<PROCESSOR_K6)
1200 #define m_K6_GEODE (m_K6 | m_GEODE)
1201 #define m_K8 (1<<PROCESSOR_K8)
1202 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1203 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1204 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1205 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1207 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1208 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1210 /* Generic instruction choice should be common subset of supported CPUs
1211 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1212 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1214 /* Feature tests against the various tunings. */
1215 unsigned char ix86_tune_features[X86_TUNE_LAST];
1217 /* Feature tests against the various tunings used to create ix86_tune_features
1218 based on the processor mask. */
1219 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
1220 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1221 negatively, so enabling for Generic64 seems like good code size
1222 tradeoff. We can't enable it for 32bit generic because it does not
1223 work well with PPro base chips. */
1224 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1226 /* X86_TUNE_PUSH_MEMORY */
1227 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1228 | m_NOCONA | m_CORE2 | m_GENERIC,
1230 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1233 /* X86_TUNE_UNROLL_STRLEN */
1234 m_486 | m_PENT | m_PPRO | m_AMD_MULTIPLE | m_K6 | m_CORE2 | m_GENERIC,
1236 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1237 m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1239 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1240 on simulation result. But after P4 was made, no performance benefit
1241 was observed with branch hints. It also increases the code size.
1242 As a result, icc never generates branch hints. */
1245 /* X86_TUNE_DOUBLE_WITH_ADD */
1248 /* X86_TUNE_USE_SAHF */
1249 m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1250 | m_NOCONA | m_CORE2 | m_GENERIC,
1252 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1253 partial dependencies. */
1254 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA
1255 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1257 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1258 register stalls on Generic32 compilation setting as well. However
1259 in current implementation the partial register stalls are not eliminated
1260 very well - they can be introduced via subregs synthesized by combine
1261 and can happen in caller/callee saving sequences. Because this option
1262 pays back little on PPro based chips and is in conflict with partial reg
1263 dependencies used by Athlon/P4 based chips, it is better to leave it off
1264 for generic32 for now. */
1267 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1268 m_CORE2 | m_GENERIC,
1270 /* X86_TUNE_USE_HIMODE_FIOP */
1271 m_386 | m_486 | m_K6_GEODE,
1273 /* X86_TUNE_USE_SIMODE_FIOP */
1274 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_CORE2 | m_GENERIC),
1276 /* X86_TUNE_USE_MOV0 */
1279 /* X86_TUNE_USE_CLTD */
1280 ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC),
1282 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1285 /* X86_TUNE_SPLIT_LONG_MOVES */
1288 /* X86_TUNE_READ_MODIFY_WRITE */
1291 /* X86_TUNE_READ_MODIFY */
1294 /* X86_TUNE_PROMOTE_QIMODE */
1295 m_K6_GEODE | m_PENT | m_386 | m_486 | m_AMD_MULTIPLE | m_CORE2
1296 | m_GENERIC /* | m_PENT4 ? */,
1298 /* X86_TUNE_FAST_PREFIX */
1299 ~(m_PENT | m_486 | m_386),
1301 /* X86_TUNE_SINGLE_STRINGOP */
1302 m_386 | m_PENT4 | m_NOCONA,
1304 /* X86_TUNE_QIMODE_MATH */
1307 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1308 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1309 might be considered for Generic32 if our scheme for avoiding partial
1310 stalls was more effective. */
1313 /* X86_TUNE_PROMOTE_QI_REGS */
1316 /* X86_TUNE_PROMOTE_HI_REGS */
1319 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1320 m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1322 /* X86_TUNE_ADD_ESP_8 */
1323 m_AMD_MULTIPLE | m_PPRO | m_K6_GEODE | m_386
1324 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1326 /* X86_TUNE_SUB_ESP_4 */
1327 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1329 /* X86_TUNE_SUB_ESP_8 */
1330 m_AMD_MULTIPLE | m_PPRO | m_386 | m_486
1331 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1333 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1334 for DFmode copies */
1335 ~(m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1336 | m_GENERIC | m_GEODE),
1338 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1339 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1341 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1342 conflict here in between PPro/Pentium4 based chips that thread 128bit
1343 SSE registers as single units versus K8 based chips that divide SSE
1344 registers to two 64bit halves. This knob promotes all store destinations
1345 to be 128bit to allow register renaming on 128bit SSE units, but usually
1346 results in one extra microop on 64bit SSE units. Experimental results
1347 shows that disabling this option on P4 brings over 20% SPECfp regression,
1348 while enabling it on K8 brings roughly 2.4% regression that can be partly
1349 masked by careful scheduling of moves. */
1350 m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_AMDFAM10,
1352 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1355 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1356 are resolved on SSE register parts instead of whole registers, so we may
1357 maintain just lower part of scalar values in proper format leaving the
1358 upper part undefined. */
1361 /* X86_TUNE_SSE_TYPELESS_STORES */
1364 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1365 m_PPRO | m_PENT4 | m_NOCONA,
1367 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1368 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1370 /* X86_TUNE_PROLOGUE_USING_MOVE */
1371 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1373 /* X86_TUNE_EPILOGUE_USING_MOVE */
1374 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1376 /* X86_TUNE_SHIFT1 */
1379 /* X86_TUNE_USE_FFREEP */
1382 /* X86_TUNE_INTER_UNIT_MOVES */
1383 ~(m_AMD_MULTIPLE | m_GENERIC),
1385 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1388 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1389 than 4 branch instructions in the 16 byte window. */
1390 m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1392 /* X86_TUNE_SCHEDULE */
1393 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC,
1395 /* X86_TUNE_USE_BT */
1396 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1398 /* X86_TUNE_USE_INCDEC */
1399 ~(m_PENT4 | m_NOCONA | m_GENERIC),
1401 /* X86_TUNE_PAD_RETURNS */
1402 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1404 /* X86_TUNE_EXT_80387_CONSTANTS */
1405 m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC,
1407 /* X86_TUNE_SHORTEN_X87_SSE */
1410 /* X86_TUNE_AVOID_VECTOR_DECODE */
1413 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1414 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1417 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1418 vector path on AMD machines. */
1419 m_K8 | m_GENERIC64 | m_AMDFAM10,
1421 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1423 m_K8 | m_GENERIC64 | m_AMDFAM10,
1425 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1429 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1430 but one byte longer. */
1433 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1434 operand that cannot be represented using a modRM byte. The XOR
1435 replacement is long decoded, so this split helps here as well. */
1438 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1440 m_AMDFAM10 | m_GENERIC,
1442 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1443 from integer to FP. */
1446 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1447 with a subsequent conditional jump instruction into a single
1448 compare-and-branch uop. */
1452 /* Feature tests against the various architecture variations. */
1453 unsigned char ix86_arch_features[X86_ARCH_LAST];
1455 /* Feature tests against the various architecture variations, used to create
1456 ix86_arch_features based on the processor mask. */
1457 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
1458 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1459 ~(m_386 | m_486 | m_PENT | m_K6),
1461 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1464 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1467 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1470 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1474 static const unsigned int x86_accumulate_outgoing_args
1475 = m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
1477 static const unsigned int x86_arch_always_fancy_math_387
1478 = m_PENT | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1479 | m_NOCONA | m_CORE2 | m_GENERIC;
1481 static enum stringop_alg stringop_alg = no_stringop;
1483 /* In case the average insn count for single function invocation is
1484 lower than this constant, emit fast (but longer) prologue and
1486 #define FAST_PROLOGUE_INSN_COUNT 20
1488 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1489 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1490 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1491 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1493 /* Array of the smallest class containing reg number REGNO, indexed by
1494 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1496 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1498 /* ax, dx, cx, bx */
1499 AREG, DREG, CREG, BREG,
1500 /* si, di, bp, sp */
1501 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1503 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1504 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1507 /* flags, fpsr, fpcr, frame */
1508 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1510 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1513 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1516 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1517 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1518 /* SSE REX registers */
1519 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1523 /* The "default" register map used in 32bit mode. */
1525 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1527 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1528 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1529 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1530 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1531 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1532 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1533 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1536 /* The "default" register map used in 64bit mode. */
1538 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1540 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1541 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1542 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1543 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1544 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1545 8,9,10,11,12,13,14,15, /* extended integer registers */
1546 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1549 /* Define the register numbers to be used in Dwarf debugging information.
1550 The SVR4 reference port C compiler uses the following register numbers
1551 in its Dwarf output code:
1552 0 for %eax (gcc regno = 0)
1553 1 for %ecx (gcc regno = 2)
1554 2 for %edx (gcc regno = 1)
1555 3 for %ebx (gcc regno = 3)
1556 4 for %esp (gcc regno = 7)
1557 5 for %ebp (gcc regno = 6)
1558 6 for %esi (gcc regno = 4)
1559 7 for %edi (gcc regno = 5)
1560 The following three DWARF register numbers are never generated by
1561 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1562 believes these numbers have these meanings.
1563 8 for %eip (no gcc equivalent)
1564 9 for %eflags (gcc regno = 17)
1565 10 for %trapno (no gcc equivalent)
1566 It is not at all clear how we should number the FP stack registers
1567 for the x86 architecture. If the version of SDB on x86/svr4 were
1568 a bit less brain dead with respect to floating-point then we would
1569 have a precedent to follow with respect to DWARF register numbers
1570 for x86 FP registers, but the SDB on x86/svr4 is so completely
1571 broken with respect to FP registers that it is hardly worth thinking
1572 of it as something to strive for compatibility with.
1573 The version of x86/svr4 SDB I have at the moment does (partially)
1574 seem to believe that DWARF register number 11 is associated with
1575 the x86 register %st(0), but that's about all. Higher DWARF
1576 register numbers don't seem to be associated with anything in
1577 particular, and even for DWARF regno 11, SDB only seems to under-
1578 stand that it should say that a variable lives in %st(0) (when
1579 asked via an `=' command) if we said it was in DWARF regno 11,
1580 but SDB still prints garbage when asked for the value of the
1581 variable in question (via a `/' command).
1582 (Also note that the labels SDB prints for various FP stack regs
1583 when doing an `x' command are all wrong.)
1584 Note that these problems generally don't affect the native SVR4
1585 C compiler because it doesn't allow the use of -O with -g and
1586 because when it is *not* optimizing, it allocates a memory
1587 location for each floating-point variable, and the memory
1588 location is what gets described in the DWARF AT_location
1589 attribute for the variable in question.
1590 Regardless of the severe mental illness of the x86/svr4 SDB, we
1591 do something sensible here and we use the following DWARF
1592 register numbers. Note that these are all stack-top-relative
1594 11 for %st(0) (gcc regno = 8)
1595 12 for %st(1) (gcc regno = 9)
1596 13 for %st(2) (gcc regno = 10)
1597 14 for %st(3) (gcc regno = 11)
1598 15 for %st(4) (gcc regno = 12)
1599 16 for %st(5) (gcc regno = 13)
1600 17 for %st(6) (gcc regno = 14)
1601 18 for %st(7) (gcc regno = 15)
1603 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1605 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1606 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1607 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1608 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1609 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1610 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1611 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1614 /* Test and compare insns in i386.md store the information needed to
1615 generate branch and scc insns here. */
1617 rtx ix86_compare_op0 = NULL_RTX;
1618 rtx ix86_compare_op1 = NULL_RTX;
1619 rtx ix86_compare_emitted = NULL_RTX;
1621 /* Define parameter passing and return registers. */
1623 static int const x86_64_int_parameter_registers[6] =
1625 DI_REG, SI_REG, DX_REG, CX_REG, R8_REG, R9_REG
1628 static int const x86_64_ms_abi_int_parameter_registers[4] =
1630 CX_REG, DX_REG, R8_REG, R9_REG
1633 static int const x86_64_int_return_registers[4] =
1635 AX_REG, DX_REG, DI_REG, SI_REG
1638 /* Define the structure for the machine field in struct function. */
1640 struct stack_local_entry GTY(())
1642 unsigned short mode;
1645 struct stack_local_entry *next;
1648 /* Structure describing stack frame layout.
1649 Stack grows downward:
1655 saved frame pointer if frame_pointer_needed
1656 <- HARD_FRAME_POINTER
1665 [va_arg registers] (
1666 > to_allocate <- FRAME_POINTER
1678 HOST_WIDE_INT frame;
1680 int outgoing_arguments_size;
1683 HOST_WIDE_INT to_allocate;
1684 /* The offsets relative to ARG_POINTER. */
1685 HOST_WIDE_INT frame_pointer_offset;
1686 HOST_WIDE_INT hard_frame_pointer_offset;
1687 HOST_WIDE_INT stack_pointer_offset;
1689 /* When save_regs_using_mov is set, emit prologue using
1690 move instead of push instructions. */
1691 bool save_regs_using_mov;
1694 /* Code model option. */
1695 enum cmodel ix86_cmodel;
1697 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1699 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1701 /* Which unit we are generating floating point math for. */
1702 enum fpmath_unit ix86_fpmath;
1704 /* Which cpu are we scheduling for. */
1705 enum attr_cpu ix86_schedule;
1707 /* Which cpu are we optimizing for. */
1708 enum processor_type ix86_tune;
1710 /* Which instruction set architecture to use. */
1711 enum processor_type ix86_arch;
1713 /* true if sse prefetch instruction is not NOOP. */
1714 int x86_prefetch_sse;
1716 /* ix86_regparm_string as a number */
1717 static int ix86_regparm;
1719 /* -mstackrealign option */
1720 extern int ix86_force_align_arg_pointer;
1721 static const char ix86_force_align_arg_pointer_string[]
1722 = "force_align_arg_pointer";
1724 static rtx (*ix86_gen_leave) (void);
1725 static rtx (*ix86_gen_pop1) (rtx);
1726 static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
1727 static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
1728 static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx);
1729 static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
1730 static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
1731 static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
1733 /* Preferred alignment for stack boundary in bits. */
1734 unsigned int ix86_preferred_stack_boundary;
1736 /* Alignment for incoming stack boundary in bits specified at
1738 static unsigned int ix86_user_incoming_stack_boundary;
1740 /* Default alignment for incoming stack boundary in bits. */
1741 static unsigned int ix86_default_incoming_stack_boundary;
1743 /* Alignment for incoming stack boundary in bits. */
1744 unsigned int ix86_incoming_stack_boundary;
1746 /* Values 1-5: see jump.c */
1747 int ix86_branch_cost;
1749 /* Calling abi specific va_list type nodes. */
1750 static GTY(()) tree sysv_va_list_type_node;
1751 static GTY(()) tree ms_va_list_type_node;
1753 /* Variables which are this size or smaller are put in the data/bss
1754 or ldata/lbss sections. */
1756 int ix86_section_threshold = 65536;
1758 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1759 char internal_label_prefix[16];
1760 int internal_label_prefix_len;
1762 /* Fence to use after loop using movnt. */
1765 /* Register class used for passing given 64bit part of the argument.
1766 These represent classes as documented by the PS ABI, with the exception
1767 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1768 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1770 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1771 whenever possible (upper half does contain padding). */
1772 enum x86_64_reg_class
1775 X86_64_INTEGER_CLASS,
1776 X86_64_INTEGERSI_CLASS,
1783 X86_64_COMPLEX_X87_CLASS,
1787 #define MAX_CLASSES 4
1789 /* Table of constants used by fldpi, fldln2, etc.... */
1790 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1791 static bool ext_80387_constants_init = 0;
1794 static struct machine_function * ix86_init_machine_status (void);
1795 static rtx ix86_function_value (const_tree, const_tree, bool);
1796 static int ix86_function_regparm (const_tree, const_tree);
1797 static void ix86_compute_frame_layout (struct ix86_frame *);
1798 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1800 static void ix86_add_new_builtins (int);
1802 enum ix86_function_specific_strings
1804 IX86_FUNCTION_SPECIFIC_ARCH,
1805 IX86_FUNCTION_SPECIFIC_TUNE,
1806 IX86_FUNCTION_SPECIFIC_FPMATH,
1807 IX86_FUNCTION_SPECIFIC_MAX
1810 static char *ix86_target_string (int, int, const char *, const char *,
1811 const char *, bool);
1812 static void ix86_debug_options (void) ATTRIBUTE_UNUSED;
1813 static void ix86_function_specific_save (struct cl_target_option *);
1814 static void ix86_function_specific_restore (struct cl_target_option *);
1815 static void ix86_function_specific_print (FILE *, int,
1816 struct cl_target_option *);
1817 static bool ix86_valid_target_attribute_p (tree, tree, tree, int);
1818 static bool ix86_valid_target_attribute_inner_p (tree, char *[]);
1819 static bool ix86_can_inline_p (tree, tree);
1820 static void ix86_set_current_function (tree);
1823 /* The svr4 ABI for the i386 says that records and unions are returned
1825 #ifndef DEFAULT_PCC_STRUCT_RETURN
1826 #define DEFAULT_PCC_STRUCT_RETURN 1
1829 /* Whether -mtune= or -march= were specified */
1830 static int ix86_tune_defaulted;
1831 static int ix86_arch_specified;
1833 /* Bit flags that specify the ISA we are compiling for. */
1834 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1836 /* A mask of ix86_isa_flags that includes bit X if X
1837 was set or cleared on the command line. */
1838 static int ix86_isa_flags_explicit;
1840 /* Define a set of ISAs which are available when a given ISA is
1841 enabled. MMX and SSE ISAs are handled separately. */
1843 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1844 #define OPTION_MASK_ISA_3DNOW_SET \
1845 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1847 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1848 #define OPTION_MASK_ISA_SSE2_SET \
1849 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1850 #define OPTION_MASK_ISA_SSE3_SET \
1851 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1852 #define OPTION_MASK_ISA_SSSE3_SET \
1853 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1854 #define OPTION_MASK_ISA_SSE4_1_SET \
1855 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1856 #define OPTION_MASK_ISA_SSE4_2_SET \
1857 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1858 #define OPTION_MASK_ISA_AVX_SET \
1859 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
1860 #define OPTION_MASK_ISA_FMA_SET \
1861 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
1863 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1865 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1867 #define OPTION_MASK_ISA_SSE4A_SET \
1868 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1869 #define OPTION_MASK_ISA_SSE5_SET \
1870 (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
1872 /* AES and PCLMUL need SSE2 because they use xmm registers */
1873 #define OPTION_MASK_ISA_AES_SET \
1874 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1875 #define OPTION_MASK_ISA_PCLMUL_SET \
1876 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1878 #define OPTION_MASK_ISA_ABM_SET \
1879 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1880 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1881 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1882 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1884 /* Define a set of ISAs which aren't available when a given ISA is
1885 disabled. MMX and SSE ISAs are handled separately. */
1887 #define OPTION_MASK_ISA_MMX_UNSET \
1888 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1889 #define OPTION_MASK_ISA_3DNOW_UNSET \
1890 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1891 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1893 #define OPTION_MASK_ISA_SSE_UNSET \
1894 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1895 #define OPTION_MASK_ISA_SSE2_UNSET \
1896 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1897 #define OPTION_MASK_ISA_SSE3_UNSET \
1898 (OPTION_MASK_ISA_SSE3 \
1899 | OPTION_MASK_ISA_SSSE3_UNSET \
1900 | OPTION_MASK_ISA_SSE4A_UNSET )
1901 #define OPTION_MASK_ISA_SSSE3_UNSET \
1902 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1903 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1904 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1905 #define OPTION_MASK_ISA_SSE4_2_UNSET \
1906 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
1907 #define OPTION_MASK_ISA_AVX_UNSET \
1908 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET)
1909 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
1911 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
1913 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
1915 #define OPTION_MASK_ISA_SSE4A_UNSET \
1916 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
1917 #define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
1918 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
1919 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
1920 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
1921 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
1922 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
1923 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
1925 /* Vectorization library interface and handlers. */
1926 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
1927 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
1928 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
1930 /* Processor target table, indexed by processor number */
1933 const struct processor_costs *cost; /* Processor costs */
1934 const int align_loop; /* Default alignments. */
1935 const int align_loop_max_skip;
1936 const int align_jump;
1937 const int align_jump_max_skip;
1938 const int align_func;
1941 static const struct ptt processor_target_table[PROCESSOR_max] =
1943 {&i386_cost, 4, 3, 4, 3, 4},
1944 {&i486_cost, 16, 15, 16, 15, 16},
1945 {&pentium_cost, 16, 7, 16, 7, 16},
1946 {&pentiumpro_cost, 16, 15, 16, 10, 16},
1947 {&geode_cost, 0, 0, 0, 0, 0},
1948 {&k6_cost, 32, 7, 32, 7, 32},
1949 {&athlon_cost, 16, 7, 16, 7, 16},
1950 {&pentium4_cost, 0, 0, 0, 0, 0},
1951 {&k8_cost, 16, 7, 16, 7, 16},
1952 {&nocona_cost, 0, 0, 0, 0, 0},
1953 {&core2_cost, 16, 10, 16, 10, 16},
1954 {&generic32_cost, 16, 7, 16, 7, 16},
1955 {&generic64_cost, 16, 10, 16, 10, 16},
1956 {&amdfam10_cost, 32, 24, 32, 7, 32}
1959 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
1984 /* Implement TARGET_HANDLE_OPTION. */
1987 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1994 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
1995 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
1999 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
2000 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
2007 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
2008 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
2012 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
2013 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
2023 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
2024 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
2028 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
2029 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
2036 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2037 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2041 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
2042 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
2049 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
2050 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
2054 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
2055 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
2062 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
2063 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
2067 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
2068 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
2075 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
2076 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
2080 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
2081 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
2088 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
2089 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
2093 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
2094 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
2101 ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
2102 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
2106 ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
2107 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
2114 ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
2115 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
2119 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
2120 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
2125 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
2126 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
2130 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
2131 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
2137 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
2138 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
2142 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
2143 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
2150 ix86_isa_flags |= OPTION_MASK_ISA_SSE5_SET;
2151 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_SET;
2155 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE5_UNSET;
2156 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_UNSET;
2163 ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
2164 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
2168 ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
2169 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
2176 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
2177 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
2181 ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
2182 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
2189 ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
2190 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
2194 ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
2195 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
2202 ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
2203 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
2207 ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
2208 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
2215 ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
2216 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
2220 ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
2221 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
2228 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
2229 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
2233 ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
2234 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
2243 /* Return a string the documents the current -m options. The caller is
2244 responsible for freeing the string. */
2247 ix86_target_string (int isa, int flags, const char *arch, const char *tune,
2248 const char *fpmath, bool add_nl_p)
2250 struct ix86_target_opts
2252 const char *option; /* option string */
2253 int mask; /* isa mask options */
2256 /* This table is ordered so that options like -msse5 or -msse4.2 that imply
2257 preceding options while match those first. */
2258 static struct ix86_target_opts isa_opts[] =
2260 { "-m64", OPTION_MASK_ISA_64BIT },
2261 { "-msse5", OPTION_MASK_ISA_SSE5 },
2262 { "-msse4a", OPTION_MASK_ISA_SSE4A },
2263 { "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
2264 { "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
2265 { "-mssse3", OPTION_MASK_ISA_SSSE3 },
2266 { "-msse3", OPTION_MASK_ISA_SSE3 },
2267 { "-msse2", OPTION_MASK_ISA_SSE2 },
2268 { "-msse", OPTION_MASK_ISA_SSE },
2269 { "-m3dnow", OPTION_MASK_ISA_3DNOW },
2270 { "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
2271 { "-mmmx", OPTION_MASK_ISA_MMX },
2272 { "-mabm", OPTION_MASK_ISA_ABM },
2273 { "-mpopcnt", OPTION_MASK_ISA_POPCNT },
2274 { "-maes", OPTION_MASK_ISA_AES },
2275 { "-mpclmul", OPTION_MASK_ISA_PCLMUL },
2279 static struct ix86_target_opts flag_opts[] =
2281 { "-m128bit-long-double", MASK_128BIT_LONG_DOUBLE },
2282 { "-m80387", MASK_80387 },
2283 { "-maccumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS },
2284 { "-malign-double", MASK_ALIGN_DOUBLE },
2285 { "-mcld", MASK_CLD },
2286 { "-mfp-ret-in-387", MASK_FLOAT_RETURNS },
2287 { "-mieee-fp", MASK_IEEE_FP },
2288 { "-minline-all-stringops", MASK_INLINE_ALL_STRINGOPS },
2289 { "-minline-stringops-dynamically", MASK_INLINE_STRINGOPS_DYNAMICALLY },
2290 { "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT },
2291 { "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS },
2292 { "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 },
2293 { "-mno-fused-madd", MASK_NO_FUSED_MADD },
2294 { "-mno-push-args", MASK_NO_PUSH_ARGS },
2295 { "-mno-red-zone", MASK_NO_RED_ZONE },
2296 { "-momit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER },
2297 { "-mrecip", MASK_RECIP },
2298 { "-mrtd", MASK_RTD },
2299 { "-msseregparm", MASK_SSEREGPARM },
2300 { "-mstack-arg-probe", MASK_STACK_PROBE },
2301 { "-mtls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS },
2304 const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (flag_opts) + 6][2];
2307 char target_other[40];
2316 memset (opts, '\0', sizeof (opts));
2318 /* Add -march= option. */
2321 opts[num][0] = "-march=";
2322 opts[num++][1] = arch;
2325 /* Add -mtune= option. */
2328 opts[num][0] = "-mtune=";
2329 opts[num++][1] = tune;
2332 /* Pick out the options in isa options. */
2333 for (i = 0; i < ARRAY_SIZE (isa_opts); i++)
2335 if ((isa & isa_opts[i].mask) != 0)
2337 opts[num++][0] = isa_opts[i].option;
2338 isa &= ~ isa_opts[i].mask;
2342 if (isa && add_nl_p)
2344 opts[num++][0] = isa_other;
2345 sprintf (isa_other, "(other isa: 0x%x)", isa);
2348 /* Add flag options. */
2349 for (i = 0; i < ARRAY_SIZE (flag_opts); i++)
2351 if ((flags & flag_opts[i].mask) != 0)
2353 opts[num++][0] = flag_opts[i].option;
2354 flags &= ~ flag_opts[i].mask;
2358 if (flags && add_nl_p)
2360 opts[num++][0] = target_other;
2361 sprintf (target_other, "(other flags: 0x%x)", isa);
2364 /* Add -fpmath= option. */
2367 opts[num][0] = "-mfpmath=";
2368 opts[num++][1] = fpmath;
2375 gcc_assert (num < ARRAY_SIZE (opts));
2377 /* Size the string. */
2379 sep_len = (add_nl_p) ? 3 : 1;
2380 for (i = 0; i < num; i++)
2383 for (j = 0; j < 2; j++)
2385 len += strlen (opts[i][j]);
2388 /* Build the string. */
2389 ret = ptr = (char *) xmalloc (len);
2392 for (i = 0; i < num; i++)
2396 for (j = 0; j < 2; j++)
2397 len2[j] = (opts[i][j]) ? strlen (opts[i][j]) : 0;
2404 if (add_nl_p && line_len + len2[0] + len2[1] > 70)
2412 for (j = 0; j < 2; j++)
2415 memcpy (ptr, opts[i][j], len2[j]);
2417 line_len += len2[j];
2422 gcc_assert (ret + len >= ptr);
2427 /* Function that is callable from the debugger to print the current
2430 ix86_debug_options (void)
2432 char *opts = ix86_target_string (ix86_isa_flags, target_flags,
2433 ix86_arch_string, ix86_tune_string,
2434 ix86_fpmath_string, true);
2438 fprintf (stderr, "%s\n\n", opts);
2442 fprintf (stderr, "<no options>\n\n");
2447 /* Sometimes certain combinations of command options do not make
2448 sense on a particular target machine. You can define a macro
2449 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2450 defined, is executed once just after all the command options have
2453 Don't use this macro to turn on various extra optimizations for
2454 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2457 override_options (bool main_args_p)
2460 unsigned int ix86_arch_mask, ix86_tune_mask;
2465 /* Comes from final.c -- no real reason to change it. */
2466 #define MAX_CODE_ALIGN 16
2474 PTA_PREFETCH_SSE = 1 << 4,
2476 PTA_3DNOW_A = 1 << 6,
2480 PTA_POPCNT = 1 << 10,
2482 PTA_SSE4A = 1 << 12,
2483 PTA_NO_SAHF = 1 << 13,
2484 PTA_SSE4_1 = 1 << 14,
2485 PTA_SSE4_2 = 1 << 15,
2488 PTA_PCLMUL = 1 << 18,
2495 const char *const name; /* processor name or nickname. */
2496 const enum processor_type processor;
2497 const enum attr_cpu schedule;
2498 const unsigned /*enum pta_flags*/ flags;
2500 const processor_alias_table[] =
2502 {"i386", PROCESSOR_I386, CPU_NONE, 0},
2503 {"i486", PROCESSOR_I486, CPU_NONE, 0},
2504 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2505 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2506 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
2507 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
2508 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2509 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2510 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE},
2511 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2512 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2513 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX},
2514 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2516 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2518 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2519 PTA_MMX | PTA_SSE | PTA_SSE2},
2520 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2521 PTA_MMX |PTA_SSE | PTA_SSE2},
2522 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2523 PTA_MMX | PTA_SSE | PTA_SSE2},
2524 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2525 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2526 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2527 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2528 | PTA_CX16 | PTA_NO_SAHF},
2529 {"core2", PROCESSOR_CORE2, CPU_CORE2,
2530 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2531 | PTA_SSSE3 | PTA_CX16},
2532 {"geode", PROCESSOR_GEODE, CPU_GEODE,
2533 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A |PTA_PREFETCH_SSE},
2534 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
2535 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2536 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2537 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2538 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2539 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2540 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2541 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2542 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2543 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2544 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2545 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2546 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2547 {"x86-64", PROCESSOR_K8, CPU_K8,
2548 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF},
2549 {"k8", PROCESSOR_K8, CPU_K8,
2550 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2551 | PTA_SSE2 | PTA_NO_SAHF},
2552 {"k8-sse3", PROCESSOR_K8, CPU_K8,
2553 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2554 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2555 {"opteron", PROCESSOR_K8, CPU_K8,
2556 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2557 | PTA_SSE2 | PTA_NO_SAHF},
2558 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2559 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2560 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2561 {"athlon64", PROCESSOR_K8, CPU_K8,
2562 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2563 | PTA_SSE2 | PTA_NO_SAHF},
2564 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2565 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2566 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2567 {"athlon-fx", PROCESSOR_K8, CPU_K8,
2568 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2569 | PTA_SSE2 | PTA_NO_SAHF},
2570 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2571 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2572 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2573 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2574 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2575 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2576 {"generic32", PROCESSOR_GENERIC32, CPU_PENTIUMPRO,
2577 0 /* flags are only used for -march switch. */ },
2578 {"generic64", PROCESSOR_GENERIC64, CPU_GENERIC64,
2579 PTA_64BIT /* flags are only used for -march switch. */ },
2582 int const pta_size = ARRAY_SIZE (processor_alias_table);
2584 /* Set up prefix/suffix so the error messages refer to either the command
2585 line argument, or the attribute(target). */
2594 prefix = "option(\"";
2599 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2600 SUBTARGET_OVERRIDE_OPTIONS;
2603 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2604 SUBSUBTARGET_OVERRIDE_OPTIONS;
2607 /* -fPIC is the default for x86_64. */
2608 if (TARGET_MACHO && TARGET_64BIT)
2611 /* Set the default values for switches whose default depends on TARGET_64BIT
2612 in case they weren't overwritten by command line options. */
2615 /* Mach-O doesn't support omitting the frame pointer for now. */
2616 if (flag_omit_frame_pointer == 2)
2617 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2618 if (flag_asynchronous_unwind_tables == 2)
2619 flag_asynchronous_unwind_tables = 1;
2620 if (flag_pcc_struct_return == 2)
2621 flag_pcc_struct_return = 0;
2625 if (flag_omit_frame_pointer == 2)
2626 flag_omit_frame_pointer = 0;
2627 if (flag_asynchronous_unwind_tables == 2)
2628 flag_asynchronous_unwind_tables = 0;
2629 if (flag_pcc_struct_return == 2)
2630 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2633 /* Need to check -mtune=generic first. */
2634 if (ix86_tune_string)
2636 if (!strcmp (ix86_tune_string, "generic")
2637 || !strcmp (ix86_tune_string, "i686")
2638 /* As special support for cross compilers we read -mtune=native
2639 as -mtune=generic. With native compilers we won't see the
2640 -mtune=native, as it was changed by the driver. */
2641 || !strcmp (ix86_tune_string, "native"))
2644 ix86_tune_string = "generic64";
2646 ix86_tune_string = "generic32";
2648 /* If this call is for setting the option attribute, allow the
2649 generic32/generic64 that was previously set. */
2650 else if (!main_args_p
2651 && (!strcmp (ix86_tune_string, "generic32")
2652 || !strcmp (ix86_tune_string, "generic64")))
2654 else if (!strncmp (ix86_tune_string, "generic", 7))
2655 error ("bad value (%s) for %stune=%s %s",
2656 ix86_tune_string, prefix, suffix, sw);
2660 if (ix86_arch_string)
2661 ix86_tune_string = ix86_arch_string;
2662 if (!ix86_tune_string)
2664 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2665 ix86_tune_defaulted = 1;
2668 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2669 need to use a sensible tune option. */
2670 if (!strcmp (ix86_tune_string, "generic")
2671 || !strcmp (ix86_tune_string, "x86-64")
2672 || !strcmp (ix86_tune_string, "i686"))
2675 ix86_tune_string = "generic64";
2677 ix86_tune_string = "generic32";
2680 if (ix86_stringop_string)
2682 if (!strcmp (ix86_stringop_string, "rep_byte"))
2683 stringop_alg = rep_prefix_1_byte;
2684 else if (!strcmp (ix86_stringop_string, "libcall"))
2685 stringop_alg = libcall;
2686 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2687 stringop_alg = rep_prefix_4_byte;
2688 else if (!strcmp (ix86_stringop_string, "rep_8byte")
2690 /* rep; movq isn't available in 32-bit code. */
2691 stringop_alg = rep_prefix_8_byte;
2692 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2693 stringop_alg = loop_1_byte;
2694 else if (!strcmp (ix86_stringop_string, "loop"))
2695 stringop_alg = loop;
2696 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2697 stringop_alg = unrolled_loop;
2699 error ("bad value (%s) for %sstringop-strategy=%s %s",
2700 ix86_stringop_string, prefix, suffix, sw);
2702 if (!strcmp (ix86_tune_string, "x86-64"))
2703 warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated. Use "
2704 "%stune=k8%s or %stune=generic%s instead as appropriate.",
2705 prefix, suffix, prefix, suffix, prefix, suffix);
2707 if (!ix86_arch_string)
2708 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2710 ix86_arch_specified = 1;
2712 if (!strcmp (ix86_arch_string, "generic"))
2713 error ("generic CPU can be used only for %stune=%s %s",
2714 prefix, suffix, sw);
2715 if (!strncmp (ix86_arch_string, "generic", 7))
2716 error ("bad value (%s) for %sarch=%s %s",
2717 ix86_arch_string, prefix, suffix, sw);
2719 if (ix86_cmodel_string != 0)
2721 if (!strcmp (ix86_cmodel_string, "small"))
2722 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2723 else if (!strcmp (ix86_cmodel_string, "medium"))
2724 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2725 else if (!strcmp (ix86_cmodel_string, "large"))
2726 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2728 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2729 else if (!strcmp (ix86_cmodel_string, "32"))
2730 ix86_cmodel = CM_32;
2731 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2732 ix86_cmodel = CM_KERNEL;
2734 error ("bad value (%s) for %scmodel=%s %s",
2735 ix86_cmodel_string, prefix, suffix, sw);
2739 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2740 use of rip-relative addressing. This eliminates fixups that
2741 would otherwise be needed if this object is to be placed in a
2742 DLL, and is essentially just as efficient as direct addressing. */
2743 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
2744 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2745 else if (TARGET_64BIT)
2746 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2748 ix86_cmodel = CM_32;
2750 if (ix86_asm_string != 0)
2753 && !strcmp (ix86_asm_string, "intel"))
2754 ix86_asm_dialect = ASM_INTEL;
2755 else if (!strcmp (ix86_asm_string, "att"))
2756 ix86_asm_dialect = ASM_ATT;
2758 error ("bad value (%s) for %sasm=%s %s",
2759 ix86_asm_string, prefix, suffix, sw);
2761 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2762 error ("code model %qs not supported in the %s bit mode",
2763 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2764 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2765 sorry ("%i-bit mode not compiled in",
2766 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2768 for (i = 0; i < pta_size; i++)
2769 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2771 ix86_schedule = processor_alias_table[i].schedule;
2772 ix86_arch = processor_alias_table[i].processor;
2773 /* Default cpu tuning to the architecture. */
2774 ix86_tune = ix86_arch;
2776 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2777 error ("CPU you selected does not support x86-64 "
2780 if (processor_alias_table[i].flags & PTA_MMX
2781 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2782 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2783 if (processor_alias_table[i].flags & PTA_3DNOW
2784 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2785 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2786 if (processor_alias_table[i].flags & PTA_3DNOW_A
2787 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2788 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2789 if (processor_alias_table[i].flags & PTA_SSE
2790 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2791 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2792 if (processor_alias_table[i].flags & PTA_SSE2
2793 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2794 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2795 if (processor_alias_table[i].flags & PTA_SSE3
2796 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2797 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2798 if (processor_alias_table[i].flags & PTA_SSSE3
2799 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2800 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2801 if (processor_alias_table[i].flags & PTA_SSE4_1
2802 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2803 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2804 if (processor_alias_table[i].flags & PTA_SSE4_2
2805 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2806 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2807 if (processor_alias_table[i].flags & PTA_AVX
2808 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
2809 ix86_isa_flags |= OPTION_MASK_ISA_AVX;
2810 if (processor_alias_table[i].flags & PTA_FMA
2811 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
2812 ix86_isa_flags |= OPTION_MASK_ISA_FMA;
2813 if (processor_alias_table[i].flags & PTA_SSE4A
2814 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2815 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2816 if (processor_alias_table[i].flags & PTA_SSE5
2817 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE5))
2818 ix86_isa_flags |= OPTION_MASK_ISA_SSE5;
2819 if (processor_alias_table[i].flags & PTA_ABM
2820 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
2821 ix86_isa_flags |= OPTION_MASK_ISA_ABM;
2822 if (processor_alias_table[i].flags & PTA_CX16
2823 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
2824 ix86_isa_flags |= OPTION_MASK_ISA_CX16;
2825 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
2826 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
2827 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
2828 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF))
2829 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
2830 ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
2831 if (processor_alias_table[i].flags & PTA_AES
2832 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
2833 ix86_isa_flags |= OPTION_MASK_ISA_AES;
2834 if (processor_alias_table[i].flags & PTA_PCLMUL
2835 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
2836 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
2837 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2838 x86_prefetch_sse = true;
2844 error ("bad value (%s) for %sarch=%s %s",
2845 ix86_arch_string, prefix, suffix, sw);
2847 ix86_arch_mask = 1u << ix86_arch;
2848 for (i = 0; i < X86_ARCH_LAST; ++i)
2849 ix86_arch_features[i] = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
2851 for (i = 0; i < pta_size; i++)
2852 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2854 ix86_schedule = processor_alias_table[i].schedule;
2855 ix86_tune = processor_alias_table[i].processor;
2856 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2858 if (ix86_tune_defaulted)
2860 ix86_tune_string = "x86-64";
2861 for (i = 0; i < pta_size; i++)
2862 if (! strcmp (ix86_tune_string,
2863 processor_alias_table[i].name))
2865 ix86_schedule = processor_alias_table[i].schedule;
2866 ix86_tune = processor_alias_table[i].processor;
2869 error ("CPU you selected does not support x86-64 "
2872 /* Intel CPUs have always interpreted SSE prefetch instructions as
2873 NOPs; so, we can enable SSE prefetch instructions even when
2874 -mtune (rather than -march) points us to a processor that has them.
2875 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2876 higher processors. */
2878 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
2879 x86_prefetch_sse = true;
2883 error ("bad value (%s) for %stune=%s %s",
2884 ix86_tune_string, prefix, suffix, sw);
2886 ix86_tune_mask = 1u << ix86_tune;
2887 for (i = 0; i < X86_TUNE_LAST; ++i)
2888 ix86_tune_features[i] = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
2891 ix86_cost = &ix86_size_cost;
2893 ix86_cost = processor_target_table[ix86_tune].cost;
2895 /* Arrange to set up i386_stack_locals for all functions. */
2896 init_machine_status = ix86_init_machine_status;
2898 /* Validate -mregparm= value. */
2899 if (ix86_regparm_string)
2902 warning (0, "%sregparm%s is ignored in 64-bit mode", prefix, suffix);
2903 i = atoi (ix86_regparm_string);
2904 if (i < 0 || i > REGPARM_MAX)
2905 error ("%sregparm=%d%s is not between 0 and %d",
2906 prefix, i, suffix, REGPARM_MAX);
2911 ix86_regparm = REGPARM_MAX;
2913 /* If the user has provided any of the -malign-* options,
2914 warn and use that value only if -falign-* is not set.
2915 Remove this code in GCC 3.2 or later. */
2916 if (ix86_align_loops_string)
2918 warning (0, "%salign-loops%s is obsolete, use -falign-loops%s",
2919 prefix, suffix, suffix);
2920 if (align_loops == 0)
2922 i = atoi (ix86_align_loops_string);
2923 if (i < 0 || i > MAX_CODE_ALIGN)
2924 error ("%salign-loops=%d%s is not between 0 and %d",
2925 prefix, i, suffix, MAX_CODE_ALIGN);
2927 align_loops = 1 << i;
2931 if (ix86_align_jumps_string)
2933 warning (0, "%salign-jumps%s is obsolete, use -falign-jumps%s",
2934 prefix, suffix, suffix);
2935 if (align_jumps == 0)
2937 i = atoi (ix86_align_jumps_string);
2938 if (i < 0 || i > MAX_CODE_ALIGN)
2939 error ("%salign-loops=%d%s is not between 0 and %d",
2940 prefix, i, suffix, MAX_CODE_ALIGN);
2942 align_jumps = 1 << i;
2946 if (ix86_align_funcs_string)
2948 warning (0, "%salign-functions%s is obsolete, use -falign-functions%s",
2949 prefix, suffix, suffix);
2950 if (align_functions == 0)
2952 i = atoi (ix86_align_funcs_string);
2953 if (i < 0 || i > MAX_CODE_ALIGN)
2954 error ("%salign-loops=%d%s is not between 0 and %d",
2955 prefix, i, suffix, MAX_CODE_ALIGN);
2957 align_functions = 1 << i;
2961 /* Default align_* from the processor table. */
2962 if (align_loops == 0)
2964 align_loops = processor_target_table[ix86_tune].align_loop;
2965 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
2967 if (align_jumps == 0)
2969 align_jumps = processor_target_table[ix86_tune].align_jump;
2970 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
2972 if (align_functions == 0)
2974 align_functions = processor_target_table[ix86_tune].align_func;
2977 /* Validate -mbranch-cost= value, or provide default. */
2978 ix86_branch_cost = ix86_cost->branch_cost;
2979 if (ix86_branch_cost_string)
2981 i = atoi (ix86_branch_cost_string);
2983 error ("%sbranch-cost=%d%s is not between 0 and 5", prefix, i, suffix);
2985 ix86_branch_cost = i;
2987 if (ix86_section_threshold_string)
2989 i = atoi (ix86_section_threshold_string);
2991 error ("%slarge-data-threshold=%d%s is negative", prefix, i, suffix);
2993 ix86_section_threshold = i;
2996 if (ix86_tls_dialect_string)
2998 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
2999 ix86_tls_dialect = TLS_DIALECT_GNU;
3000 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
3001 ix86_tls_dialect = TLS_DIALECT_GNU2;
3002 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
3003 ix86_tls_dialect = TLS_DIALECT_SUN;
3005 error ("bad value (%s) for %stls-dialect=%s %s",
3006 ix86_tls_dialect_string, prefix, suffix, sw);
3009 if (ix87_precision_string)
3011 i = atoi (ix87_precision_string);
3012 if (i != 32 && i != 64 && i != 80)
3013 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
3018 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
3020 /* Enable by default the SSE and MMX builtins. Do allow the user to
3021 explicitly disable any of these. In particular, disabling SSE and
3022 MMX for kernel code is extremely useful. */
3023 if (!ix86_arch_specified)
3025 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
3026 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
3029 warning (0, "%srtd%s is ignored in 64bit mode", prefix, suffix);
3033 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
3035 if (!ix86_arch_specified)
3037 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
3039 /* i386 ABI does not specify red zone. It still makes sense to use it
3040 when programmer takes care to stack from being destroyed. */
3041 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
3042 target_flags |= MASK_NO_RED_ZONE;
3045 /* Keep nonleaf frame pointers. */
3046 if (flag_omit_frame_pointer)
3047 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
3048 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
3049 flag_omit_frame_pointer = 1;
3051 /* If we're doing fast math, we don't care about comparison order
3052 wrt NaNs. This lets us use a shorter comparison sequence. */
3053 if (flag_finite_math_only)
3054 target_flags &= ~MASK_IEEE_FP;
3056 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3057 since the insns won't need emulation. */
3058 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
3059 target_flags &= ~MASK_NO_FANCY_MATH_387;
3061 /* Likewise, if the target doesn't have a 387, or we've specified
3062 software floating point, don't use 387 inline intrinsics. */
3064 target_flags |= MASK_NO_FANCY_MATH_387;
3066 /* Turn on MMX builtins for -msse. */
3069 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
3070 x86_prefetch_sse = true;
3073 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3074 if (TARGET_SSE4_2 || TARGET_ABM)
3075 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
3077 /* Validate -mpreferred-stack-boundary= value or default it to
3078 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3079 ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
3080 if (ix86_preferred_stack_boundary_string)
3082 i = atoi (ix86_preferred_stack_boundary_string);
3083 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3084 error ("%spreferred-stack-boundary=%d%s is not between %d and 12",
3085 prefix, i, suffix, TARGET_64BIT ? 4 : 2);
3087 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
3090 /* Set the default value for -mstackrealign. */
3091 if (ix86_force_align_arg_pointer == -1)
3092 ix86_force_align_arg_pointer = STACK_REALIGN_DEFAULT;
3094 /* Validate -mincoming-stack-boundary= value or default it to
3095 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3096 if (ix86_force_align_arg_pointer)
3097 ix86_default_incoming_stack_boundary = MIN_STACK_BOUNDARY;
3099 ix86_default_incoming_stack_boundary = PREFERRED_STACK_BOUNDARY;
3100 ix86_incoming_stack_boundary = ix86_default_incoming_stack_boundary;
3101 if (ix86_incoming_stack_boundary_string)
3103 i = atoi (ix86_incoming_stack_boundary_string);
3104 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3105 error ("-mincoming-stack-boundary=%d is not between %d and 12",
3106 i, TARGET_64BIT ? 4 : 2);
3109 ix86_user_incoming_stack_boundary = (1 << i) * BITS_PER_UNIT;
3110 ix86_incoming_stack_boundary
3111 = ix86_user_incoming_stack_boundary;
3115 /* Accept -msseregparm only if at least SSE support is enabled. */
3116 if (TARGET_SSEREGPARM
3118 error ("%ssseregparm%s used without SSE enabled", prefix, suffix);
3120 ix86_fpmath = TARGET_FPMATH_DEFAULT;
3121 if (ix86_fpmath_string != 0)
3123 if (! strcmp (ix86_fpmath_string, "387"))
3124 ix86_fpmath = FPMATH_387;
3125 else if (! strcmp (ix86_fpmath_string, "sse"))
3129 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3130 ix86_fpmath = FPMATH_387;
3133 ix86_fpmath = FPMATH_SSE;
3135 else if (! strcmp (ix86_fpmath_string, "387,sse")
3136 || ! strcmp (ix86_fpmath_string, "387+sse")
3137 || ! strcmp (ix86_fpmath_string, "sse,387")
3138 || ! strcmp (ix86_fpmath_string, "sse+387")
3139 || ! strcmp (ix86_fpmath_string, "both"))
3143 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3144 ix86_fpmath = FPMATH_387;
3146 else if (!TARGET_80387)
3148 warning (0, "387 instruction set disabled, using SSE arithmetics");
3149 ix86_fpmath = FPMATH_SSE;
3152 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
3155 error ("bad value (%s) for %sfpmath=%s %s",
3156 ix86_fpmath_string, prefix, suffix, sw);
3159 /* If the i387 is disabled, then do not return values in it. */
3161 target_flags &= ~MASK_FLOAT_RETURNS;
3163 /* Use external vectorized library in vectorizing intrinsics. */
3164 if (ix86_veclibabi_string)
3166 if (strcmp (ix86_veclibabi_string, "svml") == 0)
3167 ix86_veclib_handler = ix86_veclibabi_svml;
3168 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
3169 ix86_veclib_handler = ix86_veclibabi_acml;
3171 error ("unknown vectorization library ABI type (%s) for "
3172 "%sveclibabi=%s %s", ix86_veclibabi_string,
3173 prefix, suffix, sw);
3176 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
3177 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3179 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3181 /* ??? Unwind info is not correct around the CFG unless either a frame
3182 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3183 unwind info generation to be aware of the CFG and propagating states
3185 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
3186 || flag_exceptions || flag_non_call_exceptions)
3187 && flag_omit_frame_pointer
3188 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3190 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3191 warning (0, "unwind tables currently require either a frame pointer "
3192 "or %saccumulate-outgoing-args%s for correctness",
3194 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3197 /* If stack probes are required, the space used for large function
3198 arguments on the stack must also be probed, so enable
3199 -maccumulate-outgoing-args so this happens in the prologue. */
3200 if (TARGET_STACK_PROBE
3201 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3203 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3204 warning (0, "stack probing requires %saccumulate-outgoing-args%s "
3205 "for correctness", prefix, suffix);
3206 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3209 /* For sane SSE instruction set generation we need fcomi instruction.
3210 It is safe to enable all CMOVE instructions. */
3214 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3217 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
3218 p = strchr (internal_label_prefix, 'X');
3219 internal_label_prefix_len = p - internal_label_prefix;
3223 /* When scheduling description is not available, disable scheduler pass
3224 so it won't slow down the compilation and make x87 code slower. */
3225 if (!TARGET_SCHEDULE)
3226 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
3228 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
3229 set_param_value ("simultaneous-prefetches",
3230 ix86_cost->simultaneous_prefetches);
3231 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
3232 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
3233 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
3234 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
3235 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
3236 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
3238 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3239 can be optimized to ap = __builtin_next_arg (0). */
3241 targetm.expand_builtin_va_start = NULL;
3245 ix86_gen_leave = gen_leave_rex64;
3246 ix86_gen_pop1 = gen_popdi1;
3247 ix86_gen_add3 = gen_adddi3;
3248 ix86_gen_sub3 = gen_subdi3;
3249 ix86_gen_sub3_carry = gen_subdi3_carry_rex64;
3250 ix86_gen_one_cmpl2 = gen_one_cmpldi2;
3251 ix86_gen_monitor = gen_sse3_monitor64;
3252 ix86_gen_andsp = gen_anddi3;
3256 ix86_gen_leave = gen_leave;
3257 ix86_gen_pop1 = gen_popsi1;
3258 ix86_gen_add3 = gen_addsi3;
3259 ix86_gen_sub3 = gen_subsi3;
3260 ix86_gen_sub3_carry = gen_subsi3_carry;
3261 ix86_gen_one_cmpl2 = gen_one_cmplsi2;
3262 ix86_gen_monitor = gen_sse3_monitor;
3263 ix86_gen_andsp = gen_andsi3;
3267 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3269 target_flags |= MASK_CLD & ~target_flags_explicit;
3272 /* Save the initial options in case the user does function specific options */
3274 target_option_default_node = target_option_current_node
3275 = build_target_option_node ();
3278 /* Update register usage after having seen the compiler flags. */
3281 ix86_conditional_register_usage (void)
3286 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3288 if (fixed_regs[i] > 1)
3289 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2));
3290 if (call_used_regs[i] > 1)
3291 call_used_regs[i] = (call_used_regs[i] == (TARGET_64BIT ? 3 : 2));
3294 /* The PIC register, if it exists, is fixed. */
3295 j = PIC_OFFSET_TABLE_REGNUM;
3296 if (j != INVALID_REGNUM)
3297 fixed_regs[j] = call_used_regs[j] = 1;
3299 /* The MS_ABI changes the set of call-used registers. */
3300 if (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
3302 call_used_regs[SI_REG] = 0;
3303 call_used_regs[DI_REG] = 0;
3304 call_used_regs[XMM6_REG] = 0;
3305 call_used_regs[XMM7_REG] = 0;
3306 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
3307 call_used_regs[i] = 0;
3310 /* The default setting of CLOBBERED_REGS is for 32-bit; add in the
3311 other call-clobbered regs for 64-bit. */
3314 CLEAR_HARD_REG_SET (reg_class_contents[(int)CLOBBERED_REGS]);
3316 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3317 if (TEST_HARD_REG_BIT (reg_class_contents[(int)GENERAL_REGS], i)
3318 && call_used_regs[i])
3319 SET_HARD_REG_BIT (reg_class_contents[(int)CLOBBERED_REGS], i);
3322 /* If MMX is disabled, squash the registers. */
3324 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3325 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i))
3326 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3328 /* If SSE is disabled, squash the registers. */
3330 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3331 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i))
3332 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3334 /* If the FPU is disabled, squash the registers. */
3335 if (! (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387))
3336 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3337 if (TEST_HARD_REG_BIT (reg_class_contents[(int)FLOAT_REGS], i))
3338 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3340 /* If 32-bit, squash the 64-bit registers. */
3343 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++)
3345 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
3351 /* Save the current options */
3354 ix86_function_specific_save (struct cl_target_option *ptr)
3356 gcc_assert (IN_RANGE (ix86_arch, 0, 255));
3357 gcc_assert (IN_RANGE (ix86_schedule, 0, 255));
3358 gcc_assert (IN_RANGE (ix86_tune, 0, 255));
3359 gcc_assert (IN_RANGE (ix86_fpmath, 0, 255));
3360 gcc_assert (IN_RANGE (ix86_branch_cost, 0, 255));
3362 ptr->arch = ix86_arch;
3363 ptr->schedule = ix86_schedule;
3364 ptr->tune = ix86_tune;
3365 ptr->fpmath = ix86_fpmath;
3366 ptr->branch_cost = ix86_branch_cost;
3367 ptr->tune_defaulted = ix86_tune_defaulted;
3368 ptr->arch_specified = ix86_arch_specified;
3369 ptr->ix86_isa_flags_explicit = ix86_isa_flags_explicit;
3370 ptr->target_flags_explicit = target_flags_explicit;
3373 /* Restore the current options */
3376 ix86_function_specific_restore (struct cl_target_option *ptr)
3378 enum processor_type old_tune = ix86_tune;
3379 enum processor_type old_arch = ix86_arch;
3380 unsigned int ix86_arch_mask, ix86_tune_mask;
3383 ix86_arch = ptr->arch;
3384 ix86_schedule = ptr->schedule;
3385 ix86_tune = ptr->tune;
3386 ix86_fpmath = ptr->fpmath;
3387 ix86_branch_cost = ptr->branch_cost;
3388 ix86_tune_defaulted = ptr->tune_defaulted;
3389 ix86_arch_specified = ptr->arch_specified;
3390 ix86_isa_flags_explicit = ptr->ix86_isa_flags_explicit;
3391 target_flags_explicit = ptr->target_flags_explicit;
3393 /* Recreate the arch feature tests if the arch changed */
3394 if (old_arch != ix86_arch)
3396 ix86_arch_mask = 1u << ix86_arch;
3397 for (i = 0; i < X86_ARCH_LAST; ++i)
3398 ix86_arch_features[i]
3399 = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3402 /* Recreate the tune optimization tests */
3403 if (old_tune != ix86_tune)
3405 ix86_tune_mask = 1u << ix86_tune;
3406 for (i = 0; i < X86_TUNE_LAST; ++i)
3407 ix86_tune_features[i]
3408 = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3412 /* Print the current options */
3415 ix86_function_specific_print (FILE *file, int indent,
3416 struct cl_target_option *ptr)
3419 = ix86_target_string (ptr->ix86_isa_flags, ptr->target_flags,
3420 NULL, NULL, NULL, false);
3422 fprintf (file, "%*sarch = %d (%s)\n",
3425 ((ptr->arch < TARGET_CPU_DEFAULT_max)
3426 ? cpu_names[ptr->arch]
3429 fprintf (file, "%*stune = %d (%s)\n",
3432 ((ptr->tune < TARGET_CPU_DEFAULT_max)
3433 ? cpu_names[ptr->tune]
3436 fprintf (file, "%*sfpmath = %d%s%s\n", indent, "", ptr->fpmath,
3437 (ptr->fpmath & FPMATH_387) ? ", 387" : "",
3438 (ptr->fpmath & FPMATH_SSE) ? ", sse" : "");
3439 fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);
3443 fprintf (file, "%*s%s\n", indent, "", target_string);
3444 free (target_string);
3449 /* Inner function to process the attribute((target(...))), take an argument and
3450 set the current options from the argument. If we have a list, recursively go
3454 ix86_valid_target_attribute_inner_p (tree args, char *p_strings[])
3459 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3460 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3461 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3462 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3477 enum ix86_opt_type type;
3482 IX86_ATTR_ISA ("3dnow", OPT_m3dnow),
3483 IX86_ATTR_ISA ("abm", OPT_mabm),
3484 IX86_ATTR_ISA ("aes", OPT_maes),
3485 IX86_ATTR_ISA ("avx", OPT_mavx),
3486 IX86_ATTR_ISA ("mmx", OPT_mmmx),
3487 IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
3488 IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
3489 IX86_ATTR_ISA ("sse", OPT_msse),
3490 IX86_ATTR_ISA ("sse2", OPT_msse2),
3491 IX86_ATTR_ISA ("sse3", OPT_msse3),
3492 IX86_ATTR_ISA ("sse4", OPT_msse4),
3493 IX86_ATTR_ISA ("sse4.1", OPT_msse4_1),
3494 IX86_ATTR_ISA ("sse4.2", OPT_msse4_2),
3495 IX86_ATTR_ISA ("sse4a", OPT_msse4a),
3496 IX86_ATTR_ISA ("sse5", OPT_msse5),
3497 IX86_ATTR_ISA ("ssse3", OPT_mssse3),
3499 /* string options */
3500 IX86_ATTR_STR ("arch=", IX86_FUNCTION_SPECIFIC_ARCH),
3501 IX86_ATTR_STR ("fpmath=", IX86_FUNCTION_SPECIFIC_FPMATH),
3502 IX86_ATTR_STR ("tune=", IX86_FUNCTION_SPECIFIC_TUNE),
3505 IX86_ATTR_YES ("cld",
3509 IX86_ATTR_NO ("fancy-math-387",
3510 OPT_mfancy_math_387,
3511 MASK_NO_FANCY_MATH_387),
3513 IX86_ATTR_NO ("fused-madd",
3515 MASK_NO_FUSED_MADD),
3517 IX86_ATTR_YES ("ieee-fp",
3521 IX86_ATTR_YES ("inline-all-stringops",
3522 OPT_minline_all_stringops,
3523 MASK_INLINE_ALL_STRINGOPS),
3525 IX86_ATTR_YES ("inline-stringops-dynamically",
3526 OPT_minline_stringops_dynamically,
3527 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3529 IX86_ATTR_NO ("align-stringops",
3530 OPT_mno_align_stringops,
3531 MASK_NO_ALIGN_STRINGOPS),
3533 IX86_ATTR_YES ("recip",
3539 /* If this is a list, recurse to get the options. */
3540 if (TREE_CODE (args) == TREE_LIST)
3544 for (; args; args = TREE_CHAIN (args))
3545 if (TREE_VALUE (args)
3546 && !ix86_valid_target_attribute_inner_p (TREE_VALUE (args), p_strings))
3552 else if (TREE_CODE (args) != STRING_CST)
3555 /* Handle multiple arguments separated by commas. */
3556 next_optstr = ASTRDUP (TREE_STRING_POINTER (args));
3558 while (next_optstr && *next_optstr != '\0')
3560 char *p = next_optstr;
3562 char *comma = strchr (next_optstr, ',');
3563 const char *opt_string;
3564 size_t len, opt_len;
3569 enum ix86_opt_type type = ix86_opt_unknown;
3575 len = comma - next_optstr;
3576 next_optstr = comma + 1;
3584 /* Recognize no-xxx. */
3585 if (len > 3 && p[0] == 'n' && p[1] == 'o' && p[2] == '-')
3594 /* Find the option. */
3597 for (i = 0; i < ARRAY_SIZE (attrs); i++)
3599 type = attrs[i].type;
3600 opt_len = attrs[i].len;
3601 if (ch == attrs[i].string[0]
3602 && ((type != ix86_opt_str) ? len == opt_len : len > opt_len)
3603 && memcmp (p, attrs[i].string, opt_len) == 0)
3606 mask = attrs[i].mask;
3607 opt_string = attrs[i].string;
3612 /* Process the option. */
3615 error ("attribute(target(\"%s\")) is unknown", orig_p);
3619 else if (type == ix86_opt_isa)
3620 ix86_handle_option (opt, p, opt_set_p);
3622 else if (type == ix86_opt_yes || type == ix86_opt_no)
3624 if (type == ix86_opt_no)
3625 opt_set_p = !opt_set_p;
3628 target_flags |= mask;
3630 target_flags &= ~mask;
3633 else if (type == ix86_opt_str)
3637 error ("option(\"%s\") was already specified", opt_string);
3641 p_strings[opt] = xstrdup (p + opt_len);
3651 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3654 ix86_valid_target_attribute_tree (tree args)
3656 const char *orig_arch_string = ix86_arch_string;
3657 const char *orig_tune_string = ix86_tune_string;
3658 const char *orig_fpmath_string = ix86_fpmath_string;
3659 int orig_tune_defaulted = ix86_tune_defaulted;
3660 int orig_arch_specified = ix86_arch_specified;
3661 char *option_strings[IX86_FUNCTION_SPECIFIC_MAX] = { NULL, NULL, NULL };
3664 struct cl_target_option *def
3665 = TREE_TARGET_OPTION (target_option_default_node);
3667 /* Process each of the options on the chain. */
3668 if (! ix86_valid_target_attribute_inner_p (args, option_strings))
3671 /* If the changed options are different from the default, rerun override_options,
3672 and then save the options away. The string options are are attribute options,
3673 and will be undone when we copy the save structure. */
3674 if (ix86_isa_flags != def->ix86_isa_flags
3675 || target_flags != def->target_flags
3676 || option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
3677 || option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
3678 || option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3680 /* If we are using the default tune= or arch=, undo the string assigned,
3681 and use the default. */
3682 if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
3683 ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
3684 else if (!orig_arch_specified)
3685 ix86_arch_string = NULL;
3687 if (option_strings[IX86_FUNCTION_SPECIFIC_TUNE])
3688 ix86_tune_string = option_strings[IX86_FUNCTION_SPECIFIC_TUNE];
3689 else if (orig_tune_defaulted)
3690 ix86_tune_string = NULL;
3692 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3693 if (option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3694 ix86_fpmath_string = option_strings[IX86_FUNCTION_SPECIFIC_FPMATH];
3695 else if (!TARGET_64BIT && TARGET_SSE)
3696 ix86_fpmath_string = "sse,387";
3698 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3699 override_options (false);
3701 /* Add any builtin functions with the new isa if any. */
3702 ix86_add_new_builtins (ix86_isa_flags);
3704 /* Save the current options unless we are validating options for
3706 t = build_target_option_node ();
3708 ix86_arch_string = orig_arch_string;
3709 ix86_tune_string = orig_tune_string;
3710 ix86_fpmath_string = orig_fpmath_string;
3712 /* Free up memory allocated to hold the strings */
3713 for (i = 0; i < IX86_FUNCTION_SPECIFIC_MAX; i++)
3714 if (option_strings[i])
3715 free (option_strings[i]);
3721 /* Hook to validate attribute((target("string"))). */
3724 ix86_valid_target_attribute_p (tree fndecl,
3725 tree ARG_UNUSED (name),
3727 int ARG_UNUSED (flags))
3729 struct cl_target_option cur_target;
3731 tree old_optimize = build_optimization_node ();
3732 tree new_target, new_optimize;
3733 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
3735 /* If the function changed the optimization levels as well as setting target
3736 options, start with the optimizations specified. */
3737 if (func_optimize && func_optimize != old_optimize)
3738 cl_optimization_restore (TREE_OPTIMIZATION (func_optimize));
3740 /* The target attributes may also change some optimization flags, so update
3741 the optimization options if necessary. */
3742 cl_target_option_save (&cur_target);
3743 new_target = ix86_valid_target_attribute_tree (args);
3744 new_optimize = build_optimization_node ();
3751 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
3753 if (old_optimize != new_optimize)
3754 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
3757 cl_target_option_restore (&cur_target);
3759 if (old_optimize != new_optimize)
3760 cl_optimization_restore (TREE_OPTIMIZATION (old_optimize));
3766 /* Hook to determine if one function can safely inline another. */
3769 ix86_can_inline_p (tree caller, tree callee)
3772 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
3773 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
3775 /* If callee has no option attributes, then it is ok to inline. */
3779 /* If caller has no option attributes, but callee does then it is not ok to
3781 else if (!caller_tree)
3786 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
3787 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
3789 /* Callee's isa options should a subset of the caller's, i.e. a SSE5 function
3790 can inline a SSE2 function but a SSE2 function can't inline a SSE5
3792 if ((caller_opts->ix86_isa_flags & callee_opts->ix86_isa_flags)
3793 != callee_opts->ix86_isa_flags)
3796 /* See if we have the same non-isa options. */
3797 else if (caller_opts->target_flags != callee_opts->target_flags)
3800 /* See if arch, tune, etc. are the same. */
3801 else if (caller_opts->arch != callee_opts->arch)
3804 else if (caller_opts->tune != callee_opts->tune)
3807 else if (caller_opts->fpmath != callee_opts->fpmath)
3810 else if (caller_opts->branch_cost != callee_opts->branch_cost)
3821 /* Remember the last target of ix86_set_current_function. */
3822 static GTY(()) tree ix86_previous_fndecl;
3824 /* Establish appropriate back-end context for processing the function
3825 FNDECL. The argument might be NULL to indicate processing at top
3826 level, outside of any function scope. */
3828 ix86_set_current_function (tree fndecl)
3830 /* Only change the context if the function changes. This hook is called
3831 several times in the course of compiling a function, and we don't want to
3832 slow things down too much or call target_reinit when it isn't safe. */
3833 if (fndecl && fndecl != ix86_previous_fndecl)
3835 tree old_tree = (ix86_previous_fndecl
3836 ? DECL_FUNCTION_SPECIFIC_TARGET (ix86_previous_fndecl)
3839 tree new_tree = (fndecl
3840 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
3843 ix86_previous_fndecl = fndecl;
3844 if (old_tree == new_tree)
3849 cl_target_option_restore (TREE_TARGET_OPTION (new_tree));
3855 struct cl_target_option *def
3856 = TREE_TARGET_OPTION (target_option_current_node);
3858 cl_target_option_restore (def);
3865 /* Return true if this goes in large data/bss. */
3868 ix86_in_large_data_p (tree exp)
3870 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
3873 /* Functions are never large data. */
3874 if (TREE_CODE (exp) == FUNCTION_DECL)
3877 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
3879 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
3880 if (strcmp (section, ".ldata") == 0
3881 || strcmp (section, ".lbss") == 0)
3887 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
3889 /* If this is an incomplete type with size 0, then we can't put it
3890 in data because it might be too big when completed. */
3891 if (!size || size > ix86_section_threshold)
3898 /* Switch to the appropriate section for output of DECL.
3899 DECL is either a `VAR_DECL' node or a constant of some sort.
3900 RELOC indicates whether forming the initial value of DECL requires
3901 link-time relocations. */
3903 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
3907 x86_64_elf_select_section (tree decl, int reloc,
3908 unsigned HOST_WIDE_INT align)
3910 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3911 && ix86_in_large_data_p (decl))
3913 const char *sname = NULL;
3914 unsigned int flags = SECTION_WRITE;
3915 switch (categorize_decl_for_section (decl, reloc))
3920 case SECCAT_DATA_REL:
3921 sname = ".ldata.rel";
3923 case SECCAT_DATA_REL_LOCAL:
3924 sname = ".ldata.rel.local";
3926 case SECCAT_DATA_REL_RO:
3927 sname = ".ldata.rel.ro";
3929 case SECCAT_DATA_REL_RO_LOCAL:
3930 sname = ".ldata.rel.ro.local";
3934 flags |= SECTION_BSS;
3937 case SECCAT_RODATA_MERGE_STR:
3938 case SECCAT_RODATA_MERGE_STR_INIT:
3939 case SECCAT_RODATA_MERGE_CONST:
3943 case SECCAT_SRODATA:
3950 /* We don't split these for medium model. Place them into
3951 default sections and hope for best. */
3953 case SECCAT_EMUTLS_VAR:
3954 case SECCAT_EMUTLS_TMPL:
3959 /* We might get called with string constants, but get_named_section
3960 doesn't like them as they are not DECLs. Also, we need to set
3961 flags in that case. */
3963 return get_section (sname, flags, NULL);
3964 return get_named_section (decl, sname, reloc);
3967 return default_elf_select_section (decl, reloc, align);
3970 /* Build up a unique section name, expressed as a
3971 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
3972 RELOC indicates whether the initial value of EXP requires
3973 link-time relocations. */
3975 static void ATTRIBUTE_UNUSED
3976 x86_64_elf_unique_section (tree decl, int reloc)
3978 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3979 && ix86_in_large_data_p (decl))
3981 const char *prefix = NULL;
3982 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
3983 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
3985 switch (categorize_decl_for_section (decl, reloc))
3988 case SECCAT_DATA_REL:
3989 case SECCAT_DATA_REL_LOCAL:
3990 case SECCAT_DATA_REL_RO:
3991 case SECCAT_DATA_REL_RO_LOCAL:
3992 prefix = one_only ? ".ld" : ".ldata";
3995 prefix = one_only ? ".lb" : ".lbss";
3998 case SECCAT_RODATA_MERGE_STR:
3999 case SECCAT_RODATA_MERGE_STR_INIT:
4000 case SECCAT_RODATA_MERGE_CONST:
4001 prefix = one_only ? ".lr" : ".lrodata";
4003 case SECCAT_SRODATA:
4010 /* We don't split these for medium model. Place them into
4011 default sections and hope for best. */
4013 case SECCAT_EMUTLS_VAR:
4014 prefix = targetm.emutls.var_section;
4016 case SECCAT_EMUTLS_TMPL:
4017 prefix = targetm.emutls.tmpl_section;
4022 const char *name, *linkonce;
4025 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
4026 name = targetm.strip_name_encoding (name);
4028 /* If we're using one_only, then there needs to be a .gnu.linkonce
4029 prefix to the section name. */
4030 linkonce = one_only ? ".gnu.linkonce" : "";
4032 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
4034 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
4038 default_unique_section (decl, reloc);
4041 #ifdef COMMON_ASM_OP
4042 /* This says how to output assembler code to declare an
4043 uninitialized external linkage data object.
4045 For medium model x86-64 we need to use .largecomm opcode for
4048 x86_elf_aligned_common (FILE *file,
4049 const char *name, unsigned HOST_WIDE_INT size,
4052 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4053 && size > (unsigned int)ix86_section_threshold)
4054 fprintf (file, ".largecomm\t");
4056 fprintf (file, "%s", COMMON_ASM_OP);
4057 assemble_name (file, name);
4058 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
4059 size, align / BITS_PER_UNIT);
4063 /* Utility function for targets to use in implementing
4064 ASM_OUTPUT_ALIGNED_BSS. */
4067 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
4068 const char *name, unsigned HOST_WIDE_INT size,
4071 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4072 && size > (unsigned int)ix86_section_threshold)
4073 switch_to_section (get_named_section (decl, ".lbss", 0));
4075 switch_to_section (bss_section);
4076 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
4077 #ifdef ASM_DECLARE_OBJECT_NAME
4078 last_assemble_variable_decl = decl;
4079 ASM_DECLARE_OBJECT_NAME (file, name, decl);
4081 /* Standard thing is just output label for the object. */
4082 ASM_OUTPUT_LABEL (file, name);
4083 #endif /* ASM_DECLARE_OBJECT_NAME */
4084 ASM_OUTPUT_SKIP (file, size ? size : 1);
4088 optimization_options (int level, int size ATTRIBUTE_UNUSED)
4090 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4091 make the problem with not enough registers even worse. */
4092 #ifdef INSN_SCHEDULING
4094 flag_schedule_insns = 0;
4098 /* The Darwin libraries never set errno, so we might as well
4099 avoid calling them when that's the only reason we would. */
4100 flag_errno_math = 0;
4102 /* The default values of these switches depend on the TARGET_64BIT
4103 that is not known at this moment. Mark these values with 2 and
4104 let user the to override these. In case there is no command line option
4105 specifying them, we will set the defaults in override_options. */
4107 flag_omit_frame_pointer = 2;
4108 flag_pcc_struct_return = 2;
4109 flag_asynchronous_unwind_tables = 2;
4110 flag_vect_cost_model = 1;
4111 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4112 SUBTARGET_OPTIMIZATION_OPTIONS;
4116 /* Decide whether we can make a sibling call to a function. DECL is the
4117 declaration of the function being targeted by the call and EXP is the
4118 CALL_EXPR representing the call. */
4121 ix86_function_ok_for_sibcall (tree decl, tree exp)
4123 tree type, decl_or_type;
4126 /* If we are generating position-independent code, we cannot sibcall
4127 optimize any indirect call, or a direct call to a global function,
4128 as the PLT requires %ebx be live. */
4129 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
4132 /* If we need to align the outgoing stack, then sibcalling would
4133 unalign the stack, which may break the called function. */
4134 if (ix86_incoming_stack_boundary < PREFERRED_STACK_BOUNDARY)
4139 decl_or_type = decl;
4140 type = TREE_TYPE (decl);
4144 /* We're looking at the CALL_EXPR, we need the type of the function. */
4145 type = CALL_EXPR_FN (exp); /* pointer expression */
4146 type = TREE_TYPE (type); /* pointer type */
4147 type = TREE_TYPE (type); /* function type */
4148 decl_or_type = type;
4151 /* Check that the return value locations are the same. Like
4152 if we are returning floats on the 80387 register stack, we cannot
4153 make a sibcall from a function that doesn't return a float to a
4154 function that does or, conversely, from a function that does return
4155 a float to a function that doesn't; the necessary stack adjustment
4156 would not be executed. This is also the place we notice
4157 differences in the return value ABI. Note that it is ok for one
4158 of the functions to have void return type as long as the return
4159 value of the other is passed in a register. */
4160 a = ix86_function_value (TREE_TYPE (exp), decl_or_type, false);
4161 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
4163 if (STACK_REG_P (a) || STACK_REG_P (b))
4165 if (!rtx_equal_p (a, b))
4168 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
4170 else if (!rtx_equal_p (a, b))
4175 /* The SYSV ABI has more call-clobbered registers;
4176 disallow sibcalls from MS to SYSV. */
4177 if (cfun->machine->call_abi == MS_ABI
4178 && ix86_function_type_abi (type) == SYSV_ABI)
4183 /* If this call is indirect, we'll need to be able to use a
4184 call-clobbered register for the address of the target function.
4185 Make sure that all such registers are not used for passing
4186 parameters. Note that DLLIMPORT functions are indirect. */
4188 || (TARGET_DLLIMPORT_DECL_ATTRIBUTES && DECL_DLLIMPORT_P (decl)))
4190 if (ix86_function_regparm (type, NULL) >= 3)
4192 /* ??? Need to count the actual number of registers to be used,
4193 not the possible number of registers. Fix later. */
4199 /* Otherwise okay. That also includes certain types of indirect calls. */
4203 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4204 calling convention attributes;
4205 arguments as in struct attribute_spec.handler. */
4208 ix86_handle_cconv_attribute (tree *node, tree name,
4210 int flags ATTRIBUTE_UNUSED,
4213 if (TREE_CODE (*node) != FUNCTION_TYPE
4214 && TREE_CODE (*node) != METHOD_TYPE
4215 && TREE_CODE (*node) != FIELD_DECL
4216 && TREE_CODE (*node) != TYPE_DECL)
4218 warning (OPT_Wattributes, "%qs attribute only applies to functions",
4219 IDENTIFIER_POINTER (name));
4220 *no_add_attrs = true;
4224 /* Can combine regparm with all attributes but fastcall. */
4225 if (is_attribute_p ("regparm", name))
4229 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4231 error ("fastcall and regparm attributes are not compatible");
4234 cst = TREE_VALUE (args);
4235 if (TREE_CODE (cst) != INTEGER_CST)
4237 warning (OPT_Wattributes,
4238 "%qs attribute requires an integer constant argument",
4239 IDENTIFIER_POINTER (name));
4240 *no_add_attrs = true;
4242 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
4244 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
4245 IDENTIFIER_POINTER (name), REGPARM_MAX);
4246 *no_add_attrs = true;
4254 /* Do not warn when emulating the MS ABI. */
4255 if (TREE_CODE (*node) != FUNCTION_TYPE || ix86_function_type_abi (*node)!=MS_ABI)
4256 warning (OPT_Wattributes, "%qs attribute ignored",
4257 IDENTIFIER_POINTER (name));
4258 *no_add_attrs = true;
4262 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4263 if (is_attribute_p ("fastcall", name))
4265 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4267 error ("fastcall and cdecl attributes are not compatible");
4269 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4271 error ("fastcall and stdcall attributes are not compatible");
4273 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
4275 error ("fastcall and regparm attributes are not compatible");
4279 /* Can combine stdcall with fastcall (redundant), regparm and
4281 else if (is_attribute_p ("stdcall", name))
4283 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4285 error ("stdcall and cdecl attributes are not compatible");
4287 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4289 error ("stdcall and fastcall attributes are not compatible");
4293 /* Can combine cdecl with regparm and sseregparm. */
4294 else if (is_attribute_p ("cdecl", name))
4296 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4298 error ("stdcall and cdecl attributes are not compatible");
4300 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4302 error ("fastcall and cdecl attributes are not compatible");
4306 /* Can combine sseregparm with all attributes. */
4311 /* Return 0 if the attributes for two types are incompatible, 1 if they
4312 are compatible, and 2 if they are nearly compatible (which causes a
4313 warning to be generated). */
4316 ix86_comp_type_attributes (const_tree type1, const_tree type2)
4318 /* Check for mismatch of non-default calling convention. */
4319 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
4321 if (TREE_CODE (type1) != FUNCTION_TYPE
4322 && TREE_CODE (type1) != METHOD_TYPE)
4325 /* Check for mismatched fastcall/regparm types. */
4326 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
4327 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
4328 || (ix86_function_regparm (type1, NULL)
4329 != ix86_function_regparm (type2, NULL)))
4332 /* Check for mismatched sseregparm types. */
4333 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
4334 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
4337 /* Check for mismatched return types (cdecl vs stdcall). */
4338 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
4339 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
4345 /* Return the regparm value for a function with the indicated TYPE and DECL.
4346 DECL may be NULL when calling function indirectly
4347 or considering a libcall. */
4350 ix86_function_regparm (const_tree type, const_tree decl)
4355 static bool error_issued;
4358 return (ix86_function_type_abi (type) == SYSV_ABI
4359 ? X86_64_REGPARM_MAX : X64_REGPARM_MAX);
4361 regparm = ix86_regparm;
4362 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
4366 = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
4368 if (decl && TREE_CODE (decl) == FUNCTION_DECL)
4370 /* We can't use regparm(3) for nested functions because
4371 these pass static chain pointer in %ecx register. */
4372 if (!error_issued && regparm == 3
4373 && decl_function_context (decl)
4374 && !DECL_NO_STATIC_CHAIN (decl))
4376 error ("nested functions are limited to 2 register parameters");
4377 error_issued = true;
4385 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
4388 /* Use register calling convention for local functions when possible. */
4390 && TREE_CODE (decl) == FUNCTION_DECL
4394 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4395 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4398 int local_regparm, globals = 0, regno;
4401 /* Make sure no regparm register is taken by a
4402 fixed register variable. */
4403 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
4404 if (fixed_regs[local_regparm])
4407 /* We can't use regparm(3) for nested functions as these use
4408 static chain pointer in third argument. */
4409 if (local_regparm == 3
4410 && decl_function_context (decl)
4411 && !DECL_NO_STATIC_CHAIN (decl))
4414 /* If the function realigns its stackpointer, the prologue will
4415 clobber %ecx. If we've already generated code for the callee,
4416 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
4417 scanning the attributes for the self-realigning property. */
4418 f = DECL_STRUCT_FUNCTION (decl);
4419 /* Since current internal arg pointer won't conflict with
4420 parameter passing regs, so no need to change stack
4421 realignment and adjust regparm number.
4423 Each fixed register usage increases register pressure,
4424 so less registers should be used for argument passing.
4425 This functionality can be overriden by an explicit
4427 for (regno = 0; regno <= DI_REG; regno++)
4428 if (fixed_regs[regno])
4432 = globals < local_regparm ? local_regparm - globals : 0;
4434 if (local_regparm > regparm)
4435 regparm = local_regparm;
4442 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4443 DFmode (2) arguments in SSE registers for a function with the
4444 indicated TYPE and DECL. DECL may be NULL when calling function
4445 indirectly or considering a libcall. Otherwise return 0. */
4448 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
4450 gcc_assert (!TARGET_64BIT);
4452 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4453 by the sseregparm attribute. */
4454 if (TARGET_SSEREGPARM
4455 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
4462 error ("Calling %qD with attribute sseregparm without "
4463 "SSE/SSE2 enabled", decl);
4465 error ("Calling %qT with attribute sseregparm without "
4466 "SSE/SSE2 enabled", type);
4474 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4475 (and DFmode for SSE2) arguments in SSE registers. */
4476 if (decl && TARGET_SSE_MATH && optimize && !profile_flag)
4478 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4479 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4481 return TARGET_SSE2 ? 2 : 1;
4487 /* Return true if EAX is live at the start of the function. Used by
4488 ix86_expand_prologue to determine if we need special help before
4489 calling allocate_stack_worker. */
4492 ix86_eax_live_at_start_p (void)
4494 /* Cheat. Don't bother working forward from ix86_function_regparm
4495 to the function type to whether an actual argument is located in
4496 eax. Instead just look at cfg info, which is still close enough
4497 to correct at this point. This gives false positives for broken
4498 functions that might use uninitialized data that happens to be
4499 allocated in eax, but who cares? */
4500 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
4503 /* Value is the number of bytes of arguments automatically
4504 popped when returning from a subroutine call.
4505 FUNDECL is the declaration node of the function (as a tree),
4506 FUNTYPE is the data type of the function (as a tree),
4507 or for a library call it is an identifier node for the subroutine name.
4508 SIZE is the number of bytes of arguments passed on the stack.
4510 On the 80386, the RTD insn may be used to pop them if the number
4511 of args is fixed, but if the number is variable then the caller
4512 must pop them all. RTD can't be used for library calls now
4513 because the library is compiled with the Unix compiler.
4514 Use of RTD is a selectable option, since it is incompatible with
4515 standard Unix calling sequences. If the option is not selected,
4516 the caller must always pop the args.
4518 The attribute stdcall is equivalent to RTD on a per module basis. */
4521 ix86_return_pops_args (tree fundecl, tree funtype, int size)
4525 /* None of the 64-bit ABIs pop arguments. */
4529 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
4531 /* Cdecl functions override -mrtd, and never pop the stack. */
4532 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
4534 /* Stdcall and fastcall functions will pop the stack if not
4536 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
4537 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
4540 if (rtd && ! stdarg_p (funtype))
4544 /* Lose any fake structure return argument if it is passed on the stack. */
4545 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
4546 && !KEEP_AGGREGATE_RETURN_POINTER)
4548 int nregs = ix86_function_regparm (funtype, fundecl);
4550 return GET_MODE_SIZE (Pmode);
4556 /* Argument support functions. */
4558 /* Return true when register may be used to pass function parameters. */
4560 ix86_function_arg_regno_p (int regno)
4563 const int *parm_regs;
4568 return (regno < REGPARM_MAX
4569 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
4571 return (regno < REGPARM_MAX
4572 || (TARGET_MMX && MMX_REGNO_P (regno)
4573 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
4574 || (TARGET_SSE && SSE_REGNO_P (regno)
4575 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
4580 if (SSE_REGNO_P (regno) && TARGET_SSE)
4585 if (TARGET_SSE && SSE_REGNO_P (regno)
4586 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
4590 /* TODO: The function should depend on current function ABI but
4591 builtins.c would need updating then. Therefore we use the
4594 /* RAX is used as hidden argument to va_arg functions. */
4595 if (DEFAULT_ABI == SYSV_ABI && regno == AX_REG)
4598 if (DEFAULT_ABI == MS_ABI)
4599 parm_regs = x86_64_ms_abi_int_parameter_registers;
4601 parm_regs = x86_64_int_parameter_registers;
4602 for (i = 0; i < (DEFAULT_ABI == MS_ABI ? X64_REGPARM_MAX
4603 : X86_64_REGPARM_MAX); i++)
4604 if (regno == parm_regs[i])
4609 /* Return if we do not know how to pass TYPE solely in registers. */
4612 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
4614 if (must_pass_in_stack_var_size_or_pad (mode, type))
4617 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4618 The layout_type routine is crafty and tries to trick us into passing
4619 currently unsupported vector types on the stack by using TImode. */
4620 return (!TARGET_64BIT && mode == TImode
4621 && type && TREE_CODE (type) != VECTOR_TYPE);
4624 /* It returns the size, in bytes, of the area reserved for arguments passed
4625 in registers for the function represented by fndecl dependent to the used
4628 ix86_reg_parm_stack_space (const_tree fndecl)
4630 int call_abi = SYSV_ABI;
4631 if (fndecl != NULL_TREE && TREE_CODE (fndecl) == FUNCTION_DECL)
4632 call_abi = ix86_function_abi (fndecl);
4634 call_abi = ix86_function_type_abi (fndecl);
4635 if (call_abi == MS_ABI)
4640 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4643 ix86_function_type_abi (const_tree fntype)
4645 if (TARGET_64BIT && fntype != NULL)
4648 if (DEFAULT_ABI == SYSV_ABI)
4649 abi = lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)) ? MS_ABI : SYSV_ABI;
4651 abi = lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)) ? SYSV_ABI : MS_ABI;
4659 ix86_function_abi (const_tree fndecl)
4663 return ix86_function_type_abi (TREE_TYPE (fndecl));
4666 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4669 ix86_cfun_abi (void)
4671 if (! cfun || ! TARGET_64BIT)
4673 return cfun->machine->call_abi;
4677 extern void init_regs (void);
4679 /* Implementation of call abi switching target hook. Specific to FNDECL
4680 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4681 for more details. */
4683 ix86_call_abi_override (const_tree fndecl)
4685 if (fndecl == NULL_TREE)
4686 cfun->machine->call_abi = DEFAULT_ABI;
4688 cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl));
4691 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
4692 re-initialization of init_regs each time we switch function context since
4693 this is needed only during RTL expansion. */
4695 ix86_maybe_switch_abi (void)
4698 call_used_regs[SI_REG] == (cfun->machine->call_abi == MS_ABI))
4702 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4703 for a call to a function whose data type is FNTYPE.
4704 For a library call, FNTYPE is 0. */
4707 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
4708 tree fntype, /* tree ptr for function decl */
4709 rtx libname, /* SYMBOL_REF of library name or 0 */
4712 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
4713 memset (cum, 0, sizeof (*cum));
4716 cum->call_abi = ix86_function_abi (fndecl);
4718 cum->call_abi = ix86_function_type_abi (fntype);
4719 /* Set up the number of registers to use for passing arguments. */
4721 if (cum->call_abi == MS_ABI && !ACCUMULATE_OUTGOING_ARGS)
4722 sorry ("ms_abi attribute requires -maccumulate-outgoing-args "
4723 "or subtarget optimization implying it");
4724 cum->nregs = ix86_regparm;
4727 if (cum->call_abi != DEFAULT_ABI)
4728 cum->nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX
4733 cum->sse_nregs = SSE_REGPARM_MAX;
4736 if (cum->call_abi != DEFAULT_ABI)
4737 cum->sse_nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
4738 : X64_SSE_REGPARM_MAX;
4742 cum->mmx_nregs = MMX_REGPARM_MAX;
4743 cum->warn_avx = true;
4744 cum->warn_sse = true;
4745 cum->warn_mmx = true;
4747 /* Because type might mismatch in between caller and callee, we need to
4748 use actual type of function for local calls.
4749 FIXME: cgraph_analyze can be told to actually record if function uses
4750 va_start so for local functions maybe_vaarg can be made aggressive
4752 FIXME: once typesytem is fixed, we won't need this code anymore. */
4754 fntype = TREE_TYPE (fndecl);
4755 cum->maybe_vaarg = (fntype
4756 ? (!prototype_p (fntype) || stdarg_p (fntype))
4761 /* If there are variable arguments, then we won't pass anything
4762 in registers in 32-bit mode. */
4763 if (stdarg_p (fntype))
4774 /* Use ecx and edx registers if function has fastcall attribute,
4775 else look for regparm information. */
4778 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
4784 cum->nregs = ix86_function_regparm (fntype, fndecl);
4787 /* Set up the number of SSE registers used for passing SFmode
4788 and DFmode arguments. Warn for mismatching ABI. */
4789 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
4793 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4794 But in the case of vector types, it is some vector mode.
4796 When we have only some of our vector isa extensions enabled, then there
4797 are some modes for which vector_mode_supported_p is false. For these
4798 modes, the generic vector support in gcc will choose some non-vector mode
4799 in order to implement the type. By computing the natural mode, we'll
4800 select the proper ABI location for the operand and not depend on whatever
4801 the middle-end decides to do with these vector types.
4803 The midde-end can't deal with the vector types > 16 bytes. In this
4804 case, we return the original mode and warn ABI change if CUM isn't
4807 static enum machine_mode
4808 type_natural_mode (const_tree type, CUMULATIVE_ARGS *cum)
4810 enum machine_mode mode = TYPE_MODE (type);
4812 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
4814 HOST_WIDE_INT size = int_size_in_bytes (type);
4815 if ((size == 8 || size == 16 || size == 32)
4816 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
4817 && TYPE_VECTOR_SUBPARTS (type) > 1)
4819 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
4821 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
4822 mode = MIN_MODE_VECTOR_FLOAT;
4824 mode = MIN_MODE_VECTOR_INT;
4826 /* Get the mode which has this inner mode and number of units. */
4827 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
4828 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
4829 && GET_MODE_INNER (mode) == innermode)
4831 if (size == 32 && !TARGET_AVX)
4833 static bool warnedavx;
4840 warning (0, "AVX vector argument without AVX "
4841 "enabled changes the ABI");
4843 return TYPE_MODE (type);
4856 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
4857 this may not agree with the mode that the type system has chosen for the
4858 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
4859 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
4862 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
4867 if (orig_mode != BLKmode)
4868 tmp = gen_rtx_REG (orig_mode, regno);
4871 tmp = gen_rtx_REG (mode, regno);
4872 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
4873 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
4879 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
4880 of this code is to classify each 8bytes of incoming argument by the register
4881 class and assign registers accordingly. */
4883 /* Return the union class of CLASS1 and CLASS2.
4884 See the x86-64 PS ABI for details. */
4886 static enum x86_64_reg_class
4887 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
4889 /* Rule #1: If both classes are equal, this is the resulting class. */
4890 if (class1 == class2)
4893 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
4895 if (class1 == X86_64_NO_CLASS)
4897 if (class2 == X86_64_NO_CLASS)
4900 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
4901 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
4902 return X86_64_MEMORY_CLASS;
4904 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
4905 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
4906 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
4907 return X86_64_INTEGERSI_CLASS;
4908 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
4909 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
4910 return X86_64_INTEGER_CLASS;
4912 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
4914 if (class1 == X86_64_X87_CLASS
4915 || class1 == X86_64_X87UP_CLASS
4916 || class1 == X86_64_COMPLEX_X87_CLASS
4917 || class2 == X86_64_X87_CLASS
4918 || class2 == X86_64_X87UP_CLASS
4919 || class2 == X86_64_COMPLEX_X87_CLASS)
4920 return X86_64_MEMORY_CLASS;
4922 /* Rule #6: Otherwise class SSE is used. */
4923 return X86_64_SSE_CLASS;
4926 /* Classify the argument of type TYPE and mode MODE.
4927 CLASSES will be filled by the register class used to pass each word
4928 of the operand. The number of words is returned. In case the parameter
4929 should be passed in memory, 0 is returned. As a special case for zero
4930 sized containers, classes[0] will be NO_CLASS and 1 is returned.
4932 BIT_OFFSET is used internally for handling records and specifies offset
4933 of the offset in bits modulo 256 to avoid overflow cases.
4935 See the x86-64 PS ABI for details.
4939 classify_argument (enum machine_mode mode, const_tree type,
4940 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
4942 HOST_WIDE_INT bytes =
4943 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
4944 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4946 /* Variable sized entities are always passed/returned in memory. */
4950 if (mode != VOIDmode
4951 && targetm.calls.must_pass_in_stack (mode, type))
4954 if (type && AGGREGATE_TYPE_P (type))
4958 enum x86_64_reg_class subclasses[MAX_CLASSES];
4960 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
4964 for (i = 0; i < words; i++)
4965 classes[i] = X86_64_NO_CLASS;
4967 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
4968 signalize memory class, so handle it as special case. */
4971 classes[0] = X86_64_NO_CLASS;
4975 /* Classify each field of record and merge classes. */
4976 switch (TREE_CODE (type))
4979 /* And now merge the fields of structure. */
4980 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4982 if (TREE_CODE (field) == FIELD_DECL)
4986 if (TREE_TYPE (field) == error_mark_node)
4989 /* Bitfields are always classified as integer. Handle them
4990 early, since later code would consider them to be
4991 misaligned integers. */
4992 if (DECL_BIT_FIELD (field))
4994 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
4995 i < ((int_bit_position (field) + (bit_offset % 64))
4996 + tree_low_cst (DECL_SIZE (field), 0)
4999 merge_classes (X86_64_INTEGER_CLASS,
5004 type = TREE_TYPE (field);
5006 /* Flexible array member is ignored. */
5007 if (TYPE_MODE (type) == BLKmode
5008 && TREE_CODE (type) == ARRAY_TYPE
5009 && TYPE_SIZE (type) == NULL_TREE
5010 && TYPE_DOMAIN (type) != NULL_TREE
5011 && (TYPE_MAX_VALUE (TYPE_DOMAIN (type))
5016 if (!warned && warn_psabi)
5019 inform (input_location,
5020 "The ABI of passing struct with"
5021 " a flexible array member has"
5022 " changed in GCC 4.4");
5026 num = classify_argument (TYPE_MODE (type), type,
5028 (int_bit_position (field)
5029 + bit_offset) % 256);
5032 for (i = 0; i < num; i++)
5035 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5037 merge_classes (subclasses[i], classes[i + pos]);
5045 /* Arrays are handled as small records. */
5048 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
5049 TREE_TYPE (type), subclasses, bit_offset);
5053 /* The partial classes are now full classes. */
5054 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
5055 subclasses[0] = X86_64_SSE_CLASS;
5056 if (subclasses[0] == X86_64_INTEGERSI_CLASS
5057 && !((bit_offset % 64) == 0 && bytes == 4))
5058 subclasses[0] = X86_64_INTEGER_CLASS;
5060 for (i = 0; i < words; i++)
5061 classes[i] = subclasses[i % num];
5066 case QUAL_UNION_TYPE:
5067 /* Unions are similar to RECORD_TYPE but offset is always 0.
5069 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5071 if (TREE_CODE (field) == FIELD_DECL)
5075 if (TREE_TYPE (field) == error_mark_node)
5078 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
5079 TREE_TYPE (field), subclasses,
5083 for (i = 0; i < num; i++)
5084 classes[i] = merge_classes (subclasses[i], classes[i]);
5095 /* When size > 16 bytes, if the first one isn't
5096 X86_64_SSE_CLASS or any other ones aren't
5097 X86_64_SSEUP_CLASS, everything should be passed in
5099 if (classes[0] != X86_64_SSE_CLASS)
5102 for (i = 1; i < words; i++)
5103 if (classes[i] != X86_64_SSEUP_CLASS)
5107 /* Final merger cleanup. */
5108 for (i = 0; i < words; i++)
5110 /* If one class is MEMORY, everything should be passed in
5112 if (classes[i] == X86_64_MEMORY_CLASS)
5115 /* The X86_64_SSEUP_CLASS should be always preceded by
5116 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5117 if (classes[i] == X86_64_SSEUP_CLASS
5118 && classes[i - 1] != X86_64_SSE_CLASS
5119 && classes[i - 1] != X86_64_SSEUP_CLASS)
5121 /* The first one should never be X86_64_SSEUP_CLASS. */
5122 gcc_assert (i != 0);
5123 classes[i] = X86_64_SSE_CLASS;
5126 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
5127 everything should be passed in memory. */
5128 if (classes[i] == X86_64_X87UP_CLASS
5129 && (classes[i - 1] != X86_64_X87_CLASS))
5133 /* The first one should never be X86_64_X87UP_CLASS. */
5134 gcc_assert (i != 0);
5135 if (!warned && warn_psabi)
5138 inform (input_location,
5139 "The ABI of passing union with long double"
5140 " has changed in GCC 4.4");
5148 /* Compute alignment needed. We align all types to natural boundaries with
5149 exception of XFmode that is aligned to 64bits. */
5150 if (mode != VOIDmode && mode != BLKmode)
5152 int mode_alignment = GET_MODE_BITSIZE (mode);
5155 mode_alignment = 128;
5156 else if (mode == XCmode)
5157 mode_alignment = 256;
5158 if (COMPLEX_MODE_P (mode))
5159 mode_alignment /= 2;
5160 /* Misaligned fields are always returned in memory. */
5161 if (bit_offset % mode_alignment)
5165 /* for V1xx modes, just use the base mode */
5166 if (VECTOR_MODE_P (mode) && mode != V1DImode
5167 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
5168 mode = GET_MODE_INNER (mode);
5170 /* Classification of atomic types. */
5175 classes[0] = X86_64_SSE_CLASS;
5178 classes[0] = X86_64_SSE_CLASS;
5179 classes[1] = X86_64_SSEUP_CLASS;
5189 int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode);
5193 classes[0] = X86_64_INTEGERSI_CLASS;
5196 else if (size <= 64)
5198 classes[0] = X86_64_INTEGER_CLASS;
5201 else if (size <= 64+32)
5203 classes[0] = X86_64_INTEGER_CLASS;
5204 classes[1] = X86_64_INTEGERSI_CLASS;
5207 else if (size <= 64+64)
5209 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5217 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5221 /* OImode shouldn't be used directly. */
5226 if (!(bit_offset % 64))
5227 classes[0] = X86_64_SSESF_CLASS;
5229 classes[0] = X86_64_SSE_CLASS;
5232 classes[0] = X86_64_SSEDF_CLASS;
5235 classes[0] = X86_64_X87_CLASS;
5236 classes[1] = X86_64_X87UP_CLASS;
5239 classes[0] = X86_64_SSE_CLASS;
5240 classes[1] = X86_64_SSEUP_CLASS;
5243 classes[0] = X86_64_SSE_CLASS;
5244 if (!(bit_offset % 64))
5250 if (!warned && warn_psabi)
5253 inform (input_location,
5254 "The ABI of passing structure with complex float"
5255 " member has changed in GCC 4.4");
5257 classes[1] = X86_64_SSESF_CLASS;
5261 classes[0] = X86_64_SSEDF_CLASS;
5262 classes[1] = X86_64_SSEDF_CLASS;
5265 classes[0] = X86_64_COMPLEX_X87_CLASS;
5268 /* This modes is larger than 16 bytes. */
5276 classes[0] = X86_64_SSE_CLASS;
5277 classes[1] = X86_64_SSEUP_CLASS;
5278 classes[2] = X86_64_SSEUP_CLASS;
5279 classes[3] = X86_64_SSEUP_CLASS;
5287 classes[0] = X86_64_SSE_CLASS;
5288 classes[1] = X86_64_SSEUP_CLASS;
5295 classes[0] = X86_64_SSE_CLASS;
5301 gcc_assert (VECTOR_MODE_P (mode));
5306 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
5308 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
5309 classes[0] = X86_64_INTEGERSI_CLASS;
5311 classes[0] = X86_64_INTEGER_CLASS;
5312 classes[1] = X86_64_INTEGER_CLASS;
5313 return 1 + (bytes > 8);
5317 /* Examine the argument and return set number of register required in each
5318 class. Return 0 iff parameter should be passed in memory. */
5320 examine_argument (enum machine_mode mode, const_tree type, int in_return,
5321 int *int_nregs, int *sse_nregs)
5323 enum x86_64_reg_class regclass[MAX_CLASSES];
5324 int n = classify_argument (mode, type, regclass, 0);
5330 for (n--; n >= 0; n--)
5331 switch (regclass[n])
5333 case X86_64_INTEGER_CLASS:
5334 case X86_64_INTEGERSI_CLASS:
5337 case X86_64_SSE_CLASS:
5338 case X86_64_SSESF_CLASS:
5339 case X86_64_SSEDF_CLASS:
5342 case X86_64_NO_CLASS:
5343 case X86_64_SSEUP_CLASS:
5345 case X86_64_X87_CLASS:
5346 case X86_64_X87UP_CLASS:
5350 case X86_64_COMPLEX_X87_CLASS:
5351 return in_return ? 2 : 0;
5352 case X86_64_MEMORY_CLASS:
5358 /* Construct container for the argument used by GCC interface. See
5359 FUNCTION_ARG for the detailed description. */
5362 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
5363 const_tree type, int in_return, int nintregs, int nsseregs,
5364 const int *intreg, int sse_regno)
5366 /* The following variables hold the static issued_error state. */
5367 static bool issued_sse_arg_error;
5368 static bool issued_sse_ret_error;
5369 static bool issued_x87_ret_error;
5371 enum machine_mode tmpmode;
5373 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5374 enum x86_64_reg_class regclass[MAX_CLASSES];
5378 int needed_sseregs, needed_intregs;
5379 rtx exp[MAX_CLASSES];
5382 n = classify_argument (mode, type, regclass, 0);
5385 if (!examine_argument (mode, type, in_return, &needed_intregs,
5388 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
5391 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5392 some less clueful developer tries to use floating-point anyway. */
5393 if (needed_sseregs && !TARGET_SSE)
5397 if (!issued_sse_ret_error)
5399 error ("SSE register return with SSE disabled");
5400 issued_sse_ret_error = true;
5403 else if (!issued_sse_arg_error)
5405 error ("SSE register argument with SSE disabled");
5406 issued_sse_arg_error = true;
5411 /* Likewise, error if the ABI requires us to return values in the
5412 x87 registers and the user specified -mno-80387. */
5413 if (!TARGET_80387 && in_return)
5414 for (i = 0; i < n; i++)
5415 if (regclass[i] == X86_64_X87_CLASS
5416 || regclass[i] == X86_64_X87UP_CLASS
5417 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
5419 if (!issued_x87_ret_error)
5421 error ("x87 register return with x87 disabled");
5422 issued_x87_ret_error = true;
5427 /* First construct simple cases. Avoid SCmode, since we want to use
5428 single register to pass this type. */
5429 if (n == 1 && mode != SCmode)
5430 switch (regclass[0])
5432 case X86_64_INTEGER_CLASS:
5433 case X86_64_INTEGERSI_CLASS:
5434 return gen_rtx_REG (mode, intreg[0]);
5435 case X86_64_SSE_CLASS:
5436 case X86_64_SSESF_CLASS:
5437 case X86_64_SSEDF_CLASS:
5438 if (mode != BLKmode)
5439 return gen_reg_or_parallel (mode, orig_mode,
5440 SSE_REGNO (sse_regno));
5442 case X86_64_X87_CLASS:
5443 case X86_64_COMPLEX_X87_CLASS:
5444 return gen_rtx_REG (mode, FIRST_STACK_REG);
5445 case X86_64_NO_CLASS:
5446 /* Zero sized array, struct or class. */
5451 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
5452 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
5453 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5455 && regclass[0] == X86_64_SSE_CLASS
5456 && regclass[1] == X86_64_SSEUP_CLASS
5457 && regclass[2] == X86_64_SSEUP_CLASS
5458 && regclass[3] == X86_64_SSEUP_CLASS
5460 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5463 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
5464 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
5465 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
5466 && regclass[1] == X86_64_INTEGER_CLASS
5467 && (mode == CDImode || mode == TImode || mode == TFmode)
5468 && intreg[0] + 1 == intreg[1])
5469 return gen_rtx_REG (mode, intreg[0]);
5471 /* Otherwise figure out the entries of the PARALLEL. */
5472 for (i = 0; i < n; i++)
5476 switch (regclass[i])
5478 case X86_64_NO_CLASS:
5480 case X86_64_INTEGER_CLASS:
5481 case X86_64_INTEGERSI_CLASS:
5482 /* Merge TImodes on aligned occasions here too. */
5483 if (i * 8 + 8 > bytes)
5484 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
5485 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
5489 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5490 if (tmpmode == BLKmode)
5492 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5493 gen_rtx_REG (tmpmode, *intreg),
5497 case X86_64_SSESF_CLASS:
5498 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5499 gen_rtx_REG (SFmode,
5500 SSE_REGNO (sse_regno)),
5504 case X86_64_SSEDF_CLASS:
5505 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5506 gen_rtx_REG (DFmode,
5507 SSE_REGNO (sse_regno)),
5511 case X86_64_SSE_CLASS:
5519 if (i == 0 && regclass[1] == X86_64_SSEUP_CLASS)
5529 && regclass[1] == X86_64_SSEUP_CLASS
5530 && regclass[2] == X86_64_SSEUP_CLASS
5531 && regclass[3] == X86_64_SSEUP_CLASS);
5538 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5539 gen_rtx_REG (tmpmode,
5540 SSE_REGNO (sse_regno)),
5549 /* Empty aligned struct, union or class. */
5553 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
5554 for (i = 0; i < nexps; i++)
5555 XVECEXP (ret, 0, i) = exp [i];
5559 /* Update the data in CUM to advance over an argument of mode MODE
5560 and data type TYPE. (TYPE is null for libcalls where that information
5561 may not be available.) */
5564 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5565 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5581 cum->words += words;
5582 cum->nregs -= words;
5583 cum->regno += words;
5585 if (cum->nregs <= 0)
5593 /* OImode shouldn't be used directly. */
5597 if (cum->float_in_sse < 2)
5600 if (cum->float_in_sse < 1)
5617 if (!type || !AGGREGATE_TYPE_P (type))
5619 cum->sse_words += words;
5620 cum->sse_nregs -= 1;
5621 cum->sse_regno += 1;
5622 if (cum->sse_nregs <= 0)
5635 if (!type || !AGGREGATE_TYPE_P (type))
5637 cum->mmx_words += words;
5638 cum->mmx_nregs -= 1;
5639 cum->mmx_regno += 1;
5640 if (cum->mmx_nregs <= 0)
5651 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5652 tree type, HOST_WIDE_INT words, int named)
5654 int int_nregs, sse_nregs;
5656 /* Unnamed 256bit vector mode parameters are passed on stack. */
5657 if (!named && VALID_AVX256_REG_MODE (mode))
5660 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
5661 cum->words += words;
5662 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
5664 cum->nregs -= int_nregs;
5665 cum->sse_nregs -= sse_nregs;
5666 cum->regno += int_nregs;
5667 cum->sse_regno += sse_nregs;
5670 cum->words += words;
5674 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
5675 HOST_WIDE_INT words)
5677 /* Otherwise, this should be passed indirect. */
5678 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
5680 cum->words += words;
5689 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5690 tree type, int named)
5692 HOST_WIDE_INT bytes, words;
5694 if (mode == BLKmode)
5695 bytes = int_size_in_bytes (type);
5697 bytes = GET_MODE_SIZE (mode);
5698 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5701 mode = type_natural_mode (type, NULL);
5703 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5704 function_arg_advance_ms_64 (cum, bytes, words);
5705 else if (TARGET_64BIT)
5706 function_arg_advance_64 (cum, mode, type, words, named);
5708 function_arg_advance_32 (cum, mode, type, bytes, words);
5711 /* Define where to put the arguments to a function.
5712 Value is zero to push the argument on the stack,
5713 or a hard register in which to store the argument.
5715 MODE is the argument's machine mode.
5716 TYPE is the data type of the argument (as a tree).
5717 This is null for libcalls where that information may
5719 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5720 the preceding args and about the function being called.
5721 NAMED is nonzero if this argument is a named parameter
5722 (otherwise it is an extra parameter matching an ellipsis). */
5725 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5726 enum machine_mode orig_mode, tree type,
5727 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5729 static bool warnedsse, warnedmmx;
5731 /* Avoid the AL settings for the Unix64 ABI. */
5732 if (mode == VOIDmode)
5748 if (words <= cum->nregs)
5750 int regno = cum->regno;
5752 /* Fastcall allocates the first two DWORD (SImode) or
5753 smaller arguments to ECX and EDX if it isn't an
5759 || (type && AGGREGATE_TYPE_P (type)))
5762 /* ECX not EAX is the first allocated register. */
5763 if (regno == AX_REG)
5766 return gen_rtx_REG (mode, regno);
5771 if (cum->float_in_sse < 2)
5774 if (cum->float_in_sse < 1)
5778 /* In 32bit, we pass TImode in xmm registers. */
5785 if (!type || !AGGREGATE_TYPE_P (type))
5787 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
5790 warning (0, "SSE vector argument without SSE enabled "
5794 return gen_reg_or_parallel (mode, orig_mode,
5795 cum->sse_regno + FIRST_SSE_REG);
5800 /* OImode shouldn't be used directly. */
5809 if (!type || !AGGREGATE_TYPE_P (type))
5812 return gen_reg_or_parallel (mode, orig_mode,
5813 cum->sse_regno + FIRST_SSE_REG);
5822 if (!type || !AGGREGATE_TYPE_P (type))
5824 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
5827 warning (0, "MMX vector argument without MMX enabled "
5831 return gen_reg_or_parallel (mode, orig_mode,
5832 cum->mmx_regno + FIRST_MMX_REG);
5841 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5842 enum machine_mode orig_mode, tree type, int named)
5844 /* Handle a hidden AL argument containing number of registers
5845 for varargs x86-64 functions. */
5846 if (mode == VOIDmode)
5847 return GEN_INT (cum->maybe_vaarg
5848 ? (cum->sse_nregs < 0
5849 ? (cum->call_abi == DEFAULT_ABI
5851 : (DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
5852 : X64_SSE_REGPARM_MAX))
5867 /* Unnamed 256bit vector mode parameters are passed on stack. */
5873 return construct_container (mode, orig_mode, type, 0, cum->nregs,
5875 &x86_64_int_parameter_registers [cum->regno],
5880 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5881 enum machine_mode orig_mode, int named,
5882 HOST_WIDE_INT bytes)
5886 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
5887 We use value of -2 to specify that current function call is MSABI. */
5888 if (mode == VOIDmode)
5889 return GEN_INT (-2);
5891 /* If we've run out of registers, it goes on the stack. */
5892 if (cum->nregs == 0)
5895 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
5897 /* Only floating point modes are passed in anything but integer regs. */
5898 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
5901 regno = cum->regno + FIRST_SSE_REG;
5906 /* Unnamed floating parameters are passed in both the
5907 SSE and integer registers. */
5908 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
5909 t2 = gen_rtx_REG (mode, regno);
5910 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
5911 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
5912 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
5915 /* Handle aggregated types passed in register. */
5916 if (orig_mode == BLKmode)
5918 if (bytes > 0 && bytes <= 8)
5919 mode = (bytes > 4 ? DImode : SImode);
5920 if (mode == BLKmode)
5924 return gen_reg_or_parallel (mode, orig_mode, regno);
5928 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
5929 tree type, int named)
5931 enum machine_mode mode = omode;
5932 HOST_WIDE_INT bytes, words;
5934 if (mode == BLKmode)
5935 bytes = int_size_in_bytes (type);
5937 bytes = GET_MODE_SIZE (mode);
5938 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5940 /* To simplify the code below, represent vector types with a vector mode
5941 even if MMX/SSE are not active. */
5942 if (type && TREE_CODE (type) == VECTOR_TYPE)
5943 mode = type_natural_mode (type, cum);
5945 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5946 return function_arg_ms_64 (cum, mode, omode, named, bytes);
5947 else if (TARGET_64BIT)
5948 return function_arg_64 (cum, mode, omode, type, named);
5950 return function_arg_32 (cum, mode, omode, type, bytes, words);
5953 /* A C expression that indicates when an argument must be passed by
5954 reference. If nonzero for an argument, a copy of that argument is
5955 made in memory and a pointer to the argument is passed instead of
5956 the argument itself. The pointer is passed in whatever way is
5957 appropriate for passing a pointer to that type. */
5960 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5961 enum machine_mode mode ATTRIBUTE_UNUSED,
5962 const_tree type, bool named ATTRIBUTE_UNUSED)
5964 /* See Windows x64 Software Convention. */
5965 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5967 int msize = (int) GET_MODE_SIZE (mode);
5970 /* Arrays are passed by reference. */
5971 if (TREE_CODE (type) == ARRAY_TYPE)
5974 if (AGGREGATE_TYPE_P (type))
5976 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
5977 are passed by reference. */
5978 msize = int_size_in_bytes (type);
5982 /* __m128 is passed by reference. */
5984 case 1: case 2: case 4: case 8:
5990 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
5996 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
5999 contains_aligned_value_p (tree type)
6001 enum machine_mode mode = TYPE_MODE (type);
6002 if (((TARGET_SSE && SSE_REG_MODE_P (mode))
6006 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
6008 if (TYPE_ALIGN (type) < 128)
6011 if (AGGREGATE_TYPE_P (type))
6013 /* Walk the aggregates recursively. */
6014 switch (TREE_CODE (type))
6018 case QUAL_UNION_TYPE:
6022 /* Walk all the structure fields. */
6023 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
6025 if (TREE_CODE (field) == FIELD_DECL
6026 && contains_aligned_value_p (TREE_TYPE (field)))
6033 /* Just for use if some languages passes arrays by value. */
6034 if (contains_aligned_value_p (TREE_TYPE (type)))
6045 /* Gives the alignment boundary, in bits, of an argument with the
6046 specified mode and type. */
6049 ix86_function_arg_boundary (enum machine_mode mode, tree type)
6054 /* Since canonical type is used for call, we convert it to
6055 canonical type if needed. */
6056 if (!TYPE_STRUCTURAL_EQUALITY_P (type))
6057 type = TYPE_CANONICAL (type);
6058 align = TYPE_ALIGN (type);
6061 align = GET_MODE_ALIGNMENT (mode);
6062 if (align < PARM_BOUNDARY)
6063 align = PARM_BOUNDARY;
6064 /* In 32bit, only _Decimal128 and __float128 are aligned to their
6065 natural boundaries. */
6066 if (!TARGET_64BIT && mode != TDmode && mode != TFmode)
6068 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
6069 make an exception for SSE modes since these require 128bit
6072 The handling here differs from field_alignment. ICC aligns MMX
6073 arguments to 4 byte boundaries, while structure fields are aligned
6074 to 8 byte boundaries. */
6077 if (!(TARGET_SSE && SSE_REG_MODE_P (mode)))
6078 align = PARM_BOUNDARY;
6082 if (!contains_aligned_value_p (type))
6083 align = PARM_BOUNDARY;
6086 if (align > BIGGEST_ALIGNMENT)
6087 align = BIGGEST_ALIGNMENT;
6091 /* Return true if N is a possible register number of function value. */
6094 ix86_function_value_regno_p (int regno)
6101 case FIRST_FLOAT_REG:
6102 /* TODO: The function should depend on current function ABI but
6103 builtins.c would need updating then. Therefore we use the
6105 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
6107 return TARGET_FLOAT_RETURNS_IN_80387;
6113 if (TARGET_MACHO || TARGET_64BIT)
6121 /* Define how to find the value returned by a function.
6122 VALTYPE is the data type of the value (as a tree).
6123 If the precise function being called is known, FUNC is its FUNCTION_DECL;
6124 otherwise, FUNC is 0. */
6127 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
6128 const_tree fntype, const_tree fn)
6132 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
6133 we normally prevent this case when mmx is not available. However
6134 some ABIs may require the result to be returned like DImode. */
6135 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6136 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
6138 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
6139 we prevent this case when sse is not available. However some ABIs
6140 may require the result to be returned like integer TImode. */
6141 else if (mode == TImode
6142 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6143 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
6145 /* 32-byte vector modes in %ymm0. */
6146 else if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 32)
6147 regno = TARGET_AVX ? FIRST_SSE_REG : 0;
6149 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
6150 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
6151 regno = FIRST_FLOAT_REG;
6153 /* Most things go in %eax. */
6156 /* Override FP return register with %xmm0 for local functions when
6157 SSE math is enabled or for functions with sseregparm attribute. */
6158 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
6160 int sse_level = ix86_function_sseregparm (fntype, fn, false);
6161 if ((sse_level >= 1 && mode == SFmode)
6162 || (sse_level == 2 && mode == DFmode))
6163 regno = FIRST_SSE_REG;
6166 /* OImode shouldn't be used directly. */
6167 gcc_assert (mode != OImode);
6169 return gen_rtx_REG (orig_mode, regno);
6173 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
6178 /* Handle libcalls, which don't provide a type node. */
6179 if (valtype == NULL)
6191 return gen_rtx_REG (mode, FIRST_SSE_REG);
6194 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
6198 return gen_rtx_REG (mode, AX_REG);
6202 ret = construct_container (mode, orig_mode, valtype, 1,
6203 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
6204 x86_64_int_return_registers, 0);
6206 /* For zero sized structures, construct_container returns NULL, but we
6207 need to keep rest of compiler happy by returning meaningful value. */
6209 ret = gen_rtx_REG (orig_mode, AX_REG);
6215 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
6217 unsigned int regno = AX_REG;
6221 switch (GET_MODE_SIZE (mode))
6224 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6225 && !COMPLEX_MODE_P (mode))
6226 regno = FIRST_SSE_REG;
6230 if (mode == SFmode || mode == DFmode)
6231 regno = FIRST_SSE_REG;
6237 return gen_rtx_REG (orig_mode, regno);
6241 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
6242 enum machine_mode orig_mode, enum machine_mode mode)
6244 const_tree fn, fntype;
6247 if (fntype_or_decl && DECL_P (fntype_or_decl))
6248 fn = fntype_or_decl;
6249 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
6251 if (TARGET_64BIT && ix86_function_type_abi (fntype) == MS_ABI)
6252 return function_value_ms_64 (orig_mode, mode);
6253 else if (TARGET_64BIT)
6254 return function_value_64 (orig_mode, mode, valtype);
6256 return function_value_32 (orig_mode, mode, fntype, fn);
6260 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
6261 bool outgoing ATTRIBUTE_UNUSED)
6263 enum machine_mode mode, orig_mode;
6265 orig_mode = TYPE_MODE (valtype);
6266 mode = type_natural_mode (valtype, NULL);
6267 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
6271 ix86_libcall_value (enum machine_mode mode)
6273 return ix86_function_value_1 (NULL, NULL, mode, mode);
6276 /* Return true iff type is returned in memory. */
6278 static int ATTRIBUTE_UNUSED
6279 return_in_memory_32 (const_tree type, enum machine_mode mode)
6283 if (mode == BLKmode)
6286 size = int_size_in_bytes (type);
6288 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
6291 if (VECTOR_MODE_P (mode) || mode == TImode)
6293 /* User-created vectors small enough to fit in EAX. */
6297 /* MMX/3dNow values are returned in MM0,
6298 except when it doesn't exits. */
6300 return (TARGET_MMX ? 0 : 1);
6302 /* SSE values are returned in XMM0, except when it doesn't exist. */
6304 return (TARGET_SSE ? 0 : 1);
6306 /* AVX values are returned in YMM0, except when it doesn't exist. */
6308 return TARGET_AVX ? 0 : 1;
6317 /* OImode shouldn't be used directly. */
6318 gcc_assert (mode != OImode);
6323 static int ATTRIBUTE_UNUSED
6324 return_in_memory_64 (const_tree type, enum machine_mode mode)
6326 int needed_intregs, needed_sseregs;
6327 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
6330 static int ATTRIBUTE_UNUSED
6331 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
6333 HOST_WIDE_INT size = int_size_in_bytes (type);
6335 /* __m128 is returned in xmm0. */
6336 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6337 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
6340 /* Otherwise, the size must be exactly in [1248]. */
6341 return (size != 1 && size != 2 && size != 4 && size != 8);
6345 ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6347 #ifdef SUBTARGET_RETURN_IN_MEMORY
6348 return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
6350 const enum machine_mode mode = type_natural_mode (type, NULL);
6354 if (ix86_function_type_abi (fntype) == MS_ABI)
6355 return return_in_memory_ms_64 (type, mode);
6357 return return_in_memory_64 (type, mode);
6360 return return_in_memory_32 (type, mode);
6364 /* Return false iff TYPE is returned in memory. This version is used
6365 on Solaris 10. It is similar to the generic ix86_return_in_memory,
6366 but differs notably in that when MMX is available, 8-byte vectors
6367 are returned in memory, rather than in MMX registers. */
6370 ix86_sol10_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6373 enum machine_mode mode = type_natural_mode (type, NULL);
6376 return return_in_memory_64 (type, mode);
6378 if (mode == BLKmode)
6381 size = int_size_in_bytes (type);
6383 if (VECTOR_MODE_P (mode))
6385 /* Return in memory only if MMX registers *are* available. This
6386 seems backwards, but it is consistent with the existing
6393 else if (mode == TImode)
6395 else if (mode == XFmode)
6401 /* When returning SSE vector types, we have a choice of either
6402 (1) being abi incompatible with a -march switch, or
6403 (2) generating an error.
6404 Given no good solution, I think the safest thing is one warning.
6405 The user won't be able to use -Werror, but....
6407 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6408 called in response to actually generating a caller or callee that
6409 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6410 via aggregate_value_p for general type probing from tree-ssa. */
6413 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
6415 static bool warnedsse, warnedmmx;
6417 if (!TARGET_64BIT && type)
6419 /* Look at the return type of the function, not the function type. */
6420 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
6422 if (!TARGET_SSE && !warnedsse)
6425 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6428 warning (0, "SSE vector return without SSE enabled "
6433 if (!TARGET_MMX && !warnedmmx)
6435 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6438 warning (0, "MMX vector return without MMX enabled "
6448 /* Create the va_list data type. */
6450 /* Returns the calling convention specific va_list date type.
6451 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6454 ix86_build_builtin_va_list_abi (enum calling_abi abi)
6456 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
6458 /* For i386 we use plain pointer to argument area. */
6459 if (!TARGET_64BIT || abi == MS_ABI)
6460 return build_pointer_type (char_type_node);
6462 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6463 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6465 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
6466 unsigned_type_node);
6467 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
6468 unsigned_type_node);
6469 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6471 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6474 va_list_gpr_counter_field = f_gpr;
6475 va_list_fpr_counter_field = f_fpr;
6477 DECL_FIELD_CONTEXT (f_gpr) = record;
6478 DECL_FIELD_CONTEXT (f_fpr) = record;
6479 DECL_FIELD_CONTEXT (f_ovf) = record;
6480 DECL_FIELD_CONTEXT (f_sav) = record;
6482 TREE_CHAIN (record) = type_decl;
6483 TYPE_NAME (record) = type_decl;
6484 TYPE_FIELDS (record) = f_gpr;
6485 TREE_CHAIN (f_gpr) = f_fpr;
6486 TREE_CHAIN (f_fpr) = f_ovf;
6487 TREE_CHAIN (f_ovf) = f_sav;
6489 layout_type (record);
6491 /* The correct type is an array type of one element. */
6492 return build_array_type (record, build_index_type (size_zero_node));
6495 /* Setup the builtin va_list data type and for 64-bit the additional
6496 calling convention specific va_list data types. */
6499 ix86_build_builtin_va_list (void)
6501 tree ret = ix86_build_builtin_va_list_abi (DEFAULT_ABI);
6503 /* Initialize abi specific va_list builtin types. */
6507 if (DEFAULT_ABI == MS_ABI)
6509 t = ix86_build_builtin_va_list_abi (SYSV_ABI);
6510 if (TREE_CODE (t) != RECORD_TYPE)
6511 t = build_variant_type_copy (t);
6512 sysv_va_list_type_node = t;
6517 if (TREE_CODE (t) != RECORD_TYPE)
6518 t = build_variant_type_copy (t);
6519 sysv_va_list_type_node = t;
6521 if (DEFAULT_ABI != MS_ABI)
6523 t = ix86_build_builtin_va_list_abi (MS_ABI);
6524 if (TREE_CODE (t) != RECORD_TYPE)
6525 t = build_variant_type_copy (t);
6526 ms_va_list_type_node = t;
6531 if (TREE_CODE (t) != RECORD_TYPE)
6532 t = build_variant_type_copy (t);
6533 ms_va_list_type_node = t;
6540 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6543 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
6552 int regparm = ix86_regparm;
6554 if (cum->call_abi != DEFAULT_ABI)
6555 regparm = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX;
6557 /* GPR size of varargs save area. */
6558 if (cfun->va_list_gpr_size)
6559 ix86_varargs_gpr_size = X86_64_REGPARM_MAX * UNITS_PER_WORD;
6561 ix86_varargs_gpr_size = 0;
6563 /* FPR size of varargs save area. We don't need it if we don't pass
6564 anything in SSE registers. */
6565 if (cum->sse_nregs && cfun->va_list_fpr_size)
6566 ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16;
6568 ix86_varargs_fpr_size = 0;
6570 if (! ix86_varargs_gpr_size && ! ix86_varargs_fpr_size)
6573 save_area = frame_pointer_rtx;
6574 set = get_varargs_alias_set ();
6576 for (i = cum->regno;
6578 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
6581 mem = gen_rtx_MEM (Pmode,
6582 plus_constant (save_area, i * UNITS_PER_WORD));
6583 MEM_NOTRAP_P (mem) = 1;
6584 set_mem_alias_set (mem, set);
6585 emit_move_insn (mem, gen_rtx_REG (Pmode,
6586 x86_64_int_parameter_registers[i]));
6589 if (ix86_varargs_fpr_size)
6591 /* Now emit code to save SSE registers. The AX parameter contains number
6592 of SSE parameter registers used to call this function. We use
6593 sse_prologue_save insn template that produces computed jump across
6594 SSE saves. We need some preparation work to get this working. */
6596 label = gen_label_rtx ();
6597 label_ref = gen_rtx_LABEL_REF (Pmode, label);
6599 /* Compute address to jump to :
6600 label - eax*4 + nnamed_sse_arguments*4 Or
6601 label - eax*5 + nnamed_sse_arguments*5 for AVX. */
6602 tmp_reg = gen_reg_rtx (Pmode);
6603 nsse_reg = gen_reg_rtx (Pmode);
6604 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
6605 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6606 gen_rtx_MULT (Pmode, nsse_reg,
6609 /* vmovaps is one byte longer than movaps. */
6611 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6612 gen_rtx_PLUS (Pmode, tmp_reg,
6618 gen_rtx_CONST (DImode,
6619 gen_rtx_PLUS (DImode,
6621 GEN_INT (cum->sse_regno
6622 * (TARGET_AVX ? 5 : 4)))));
6624 emit_move_insn (nsse_reg, label_ref);
6625 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
6627 /* Compute address of memory block we save into. We always use pointer
6628 pointing 127 bytes after first byte to store - this is needed to keep
6629 instruction size limited by 4 bytes (5 bytes for AVX) with one
6630 byte displacement. */
6631 tmp_reg = gen_reg_rtx (Pmode);
6632 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6633 plus_constant (save_area,
6634 ix86_varargs_gpr_size + 127)));
6635 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
6636 MEM_NOTRAP_P (mem) = 1;
6637 set_mem_alias_set (mem, set);
6638 set_mem_align (mem, BITS_PER_WORD);
6640 /* And finally do the dirty job! */
6641 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
6642 GEN_INT (cum->sse_regno), label));
6647 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
6649 alias_set_type set = get_varargs_alias_set ();
6652 for (i = cum->regno; i < X64_REGPARM_MAX; i++)
6656 mem = gen_rtx_MEM (Pmode,
6657 plus_constant (virtual_incoming_args_rtx,
6658 i * UNITS_PER_WORD));
6659 MEM_NOTRAP_P (mem) = 1;
6660 set_mem_alias_set (mem, set);
6662 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
6663 emit_move_insn (mem, reg);
6668 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6669 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6672 CUMULATIVE_ARGS next_cum;
6675 /* This argument doesn't appear to be used anymore. Which is good,
6676 because the old code here didn't suppress rtl generation. */
6677 gcc_assert (!no_rtl);
6682 fntype = TREE_TYPE (current_function_decl);
6684 /* For varargs, we do not want to skip the dummy va_dcl argument.
6685 For stdargs, we do want to skip the last named argument. */
6687 if (stdarg_p (fntype))
6688 function_arg_advance (&next_cum, mode, type, 1);
6690 if (cum->call_abi == MS_ABI)
6691 setup_incoming_varargs_ms_64 (&next_cum);
6693 setup_incoming_varargs_64 (&next_cum);
6696 /* Checks if TYPE is of kind va_list char *. */
6699 is_va_list_char_pointer (tree type)
6703 /* For 32-bit it is always true. */
6706 canonic = ix86_canonical_va_list_type (type);
6707 return (canonic == ms_va_list_type_node
6708 || (DEFAULT_ABI == MS_ABI && canonic == va_list_type_node));
6711 /* Implement va_start. */
6714 ix86_va_start (tree valist, rtx nextarg)
6716 HOST_WIDE_INT words, n_gpr, n_fpr;
6717 tree f_gpr, f_fpr, f_ovf, f_sav;
6718 tree gpr, fpr, ovf, sav, t;
6721 /* Only 64bit target needs something special. */
6722 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6724 std_expand_builtin_va_start (valist, nextarg);
6728 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6729 f_fpr = TREE_CHAIN (f_gpr);
6730 f_ovf = TREE_CHAIN (f_fpr);
6731 f_sav = TREE_CHAIN (f_ovf);
6733 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
6734 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6735 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6736 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6737 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6739 /* Count number of gp and fp argument registers used. */
6740 words = crtl->args.info.words;
6741 n_gpr = crtl->args.info.regno;
6742 n_fpr = crtl->args.info.sse_regno;
6744 if (cfun->va_list_gpr_size)
6746 type = TREE_TYPE (gpr);
6747 t = build2 (MODIFY_EXPR, type,
6748 gpr, build_int_cst (type, n_gpr * 8));
6749 TREE_SIDE_EFFECTS (t) = 1;
6750 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6753 if (TARGET_SSE && cfun->va_list_fpr_size)
6755 type = TREE_TYPE (fpr);
6756 t = build2 (MODIFY_EXPR, type, fpr,
6757 build_int_cst (type, n_fpr * 16 + 8*X86_64_REGPARM_MAX));
6758 TREE_SIDE_EFFECTS (t) = 1;
6759 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6762 /* Find the overflow area. */
6763 type = TREE_TYPE (ovf);
6764 t = make_tree (type, crtl->args.internal_arg_pointer);
6766 t = build2 (POINTER_PLUS_EXPR, type, t,
6767 size_int (words * UNITS_PER_WORD));
6768 t = build2 (MODIFY_EXPR, type, ovf, t);
6769 TREE_SIDE_EFFECTS (t) = 1;
6770 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6772 if (ix86_varargs_gpr_size || ix86_varargs_fpr_size)
6774 /* Find the register save area.
6775 Prologue of the function save it right above stack frame. */
6776 type = TREE_TYPE (sav);
6777 t = make_tree (type, frame_pointer_rtx);
6778 if (!ix86_varargs_gpr_size)
6779 t = build2 (POINTER_PLUS_EXPR, type, t,
6780 size_int (-8 * X86_64_REGPARM_MAX));
6781 t = build2 (MODIFY_EXPR, type, sav, t);
6782 TREE_SIDE_EFFECTS (t) = 1;
6783 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6787 /* Implement va_arg. */
6790 ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6793 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
6794 tree f_gpr, f_fpr, f_ovf, f_sav;
6795 tree gpr, fpr, ovf, sav, t;
6797 tree lab_false, lab_over = NULL_TREE;
6802 enum machine_mode nat_mode;
6805 /* Only 64bit target needs something special. */
6806 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6807 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6809 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6810 f_fpr = TREE_CHAIN (f_gpr);
6811 f_ovf = TREE_CHAIN (f_fpr);
6812 f_sav = TREE_CHAIN (f_ovf);
6814 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr),
6815 build_va_arg_indirect_ref (valist), f_gpr, NULL_TREE);
6816 valist = build_va_arg_indirect_ref (valist);
6817 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6818 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6819 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6821 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6823 type = build_pointer_type (type);
6824 size = int_size_in_bytes (type);
6825 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6827 nat_mode = type_natural_mode (type, NULL);
6836 /* Unnamed 256bit vector mode parameters are passed on stack. */
6837 if (ix86_cfun_abi () == SYSV_ABI)
6844 container = construct_container (nat_mode, TYPE_MODE (type),
6845 type, 0, X86_64_REGPARM_MAX,
6846 X86_64_SSE_REGPARM_MAX, intreg,
6851 /* Pull the value out of the saved registers. */
6853 addr = create_tmp_var (ptr_type_node, "addr");
6854 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6858 int needed_intregs, needed_sseregs;
6860 tree int_addr, sse_addr;
6862 lab_false = create_artificial_label ();
6863 lab_over = create_artificial_label ();
6865 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
6867 need_temp = (!REG_P (container)
6868 && ((needed_intregs && TYPE_ALIGN (type) > 64)
6869 || TYPE_ALIGN (type) > 128));
6871 /* In case we are passing structure, verify that it is consecutive block
6872 on the register save area. If not we need to do moves. */
6873 if (!need_temp && !REG_P (container))
6875 /* Verify that all registers are strictly consecutive */
6876 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
6880 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6882 rtx slot = XVECEXP (container, 0, i);
6883 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
6884 || INTVAL (XEXP (slot, 1)) != i * 16)
6892 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6894 rtx slot = XVECEXP (container, 0, i);
6895 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
6896 || INTVAL (XEXP (slot, 1)) != i * 8)
6908 int_addr = create_tmp_var (ptr_type_node, "int_addr");
6909 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
6910 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
6911 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
6914 /* First ensure that we fit completely in registers. */
6917 t = build_int_cst (TREE_TYPE (gpr),
6918 (X86_64_REGPARM_MAX - needed_intregs + 1) * 8);
6919 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
6920 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6921 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6922 gimplify_and_add (t, pre_p);
6926 t = build_int_cst (TREE_TYPE (fpr),
6927 (X86_64_SSE_REGPARM_MAX - needed_sseregs + 1) * 16
6928 + X86_64_REGPARM_MAX * 8);
6929 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
6930 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6931 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6932 gimplify_and_add (t, pre_p);
6935 /* Compute index to start of area used for integer regs. */
6938 /* int_addr = gpr + sav; */
6939 t = fold_convert (sizetype, gpr);
6940 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
6941 gimplify_assign (int_addr, t, pre_p);
6945 /* sse_addr = fpr + sav; */
6946 t = fold_convert (sizetype, fpr);
6947 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
6948 gimplify_assign (sse_addr, t, pre_p);
6953 tree temp = create_tmp_var (type, "va_arg_tmp");
6956 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
6957 gimplify_assign (addr, t, pre_p);
6959 for (i = 0; i < XVECLEN (container, 0); i++)
6961 rtx slot = XVECEXP (container, 0, i);
6962 rtx reg = XEXP (slot, 0);
6963 enum machine_mode mode = GET_MODE (reg);
6964 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
6965 tree addr_type = build_pointer_type (piece_type);
6966 tree daddr_type = build_pointer_type_for_mode (piece_type,
6970 tree dest_addr, dest;
6972 if (SSE_REGNO_P (REGNO (reg)))
6974 src_addr = sse_addr;
6975 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
6979 src_addr = int_addr;
6980 src_offset = REGNO (reg) * 8;
6982 src_addr = fold_convert (addr_type, src_addr);
6983 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
6984 size_int (src_offset));
6985 src = build_va_arg_indirect_ref (src_addr);
6987 dest_addr = fold_convert (daddr_type, addr);
6988 dest_addr = fold_build2 (POINTER_PLUS_EXPR, daddr_type, dest_addr,
6989 size_int (INTVAL (XEXP (slot, 1))));
6990 dest = build_va_arg_indirect_ref (dest_addr);
6992 gimplify_assign (dest, src, pre_p);
6998 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
6999 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
7000 gimplify_assign (gpr, t, pre_p);
7005 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
7006 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
7007 gimplify_assign (fpr, t, pre_p);
7010 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
7012 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
7015 /* ... otherwise out of the overflow area. */
7017 /* When we align parameter on stack for caller, if the parameter
7018 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
7019 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
7020 here with caller. */
7021 arg_boundary = FUNCTION_ARG_BOUNDARY (VOIDmode, type);
7022 if ((unsigned int) arg_boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
7023 arg_boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
7025 /* Care for on-stack alignment if needed. */
7026 if (arg_boundary <= 64
7027 || integer_zerop (TYPE_SIZE (type)))
7031 HOST_WIDE_INT align = arg_boundary / 8;
7032 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
7033 size_int (align - 1));
7034 t = fold_convert (sizetype, t);
7035 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
7037 t = fold_convert (TREE_TYPE (ovf), t);
7039 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
7040 gimplify_assign (addr, t, pre_p);
7042 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
7043 size_int (rsize * UNITS_PER_WORD));
7044 gimplify_assign (unshare_expr (ovf), t, pre_p);
7047 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
7049 ptrtype = build_pointer_type (type);
7050 addr = fold_convert (ptrtype, addr);
7053 addr = build_va_arg_indirect_ref (addr);
7054 return build_va_arg_indirect_ref (addr);
7057 /* Return nonzero if OPNUM's MEM should be matched
7058 in movabs* patterns. */
7061 ix86_check_movabs (rtx insn, int opnum)
7065 set = PATTERN (insn);
7066 if (GET_CODE (set) == PARALLEL)
7067 set = XVECEXP (set, 0, 0);
7068 gcc_assert (GET_CODE (set) == SET);
7069 mem = XEXP (set, opnum);
7070 while (GET_CODE (mem) == SUBREG)
7071 mem = SUBREG_REG (mem);
7072 gcc_assert (MEM_P (mem));
7073 return (volatile_ok || !MEM_VOLATILE_P (mem));
7076 /* Initialize the table of extra 80387 mathematical constants. */
7079 init_ext_80387_constants (void)
7081 static const char * cst[5] =
7083 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
7084 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
7085 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
7086 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
7087 "3.1415926535897932385128089594061862044", /* 4: fldpi */
7091 for (i = 0; i < 5; i++)
7093 real_from_string (&ext_80387_constants_table[i], cst[i]);
7094 /* Ensure each constant is rounded to XFmode precision. */
7095 real_convert (&ext_80387_constants_table[i],
7096 XFmode, &ext_80387_constants_table[i]);
7099 ext_80387_constants_init = 1;
7102 /* Return true if the constant is something that can be loaded with
7103 a special instruction. */
7106 standard_80387_constant_p (rtx x)
7108 enum machine_mode mode = GET_MODE (x);
7112 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
7115 if (x == CONST0_RTX (mode))
7117 if (x == CONST1_RTX (mode))
7120 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7122 /* For XFmode constants, try to find a special 80387 instruction when
7123 optimizing for size or on those CPUs that benefit from them. */
7125 && (optimize_function_for_size_p (cfun) || TARGET_EXT_80387_CONSTANTS))
7129 if (! ext_80387_constants_init)
7130 init_ext_80387_constants ();
7132 for (i = 0; i < 5; i++)
7133 if (real_identical (&r, &ext_80387_constants_table[i]))
7137 /* Load of the constant -0.0 or -1.0 will be split as
7138 fldz;fchs or fld1;fchs sequence. */
7139 if (real_isnegzero (&r))
7141 if (real_identical (&r, &dconstm1))
7147 /* Return the opcode of the special instruction to be used to load
7151 standard_80387_constant_opcode (rtx x)
7153 switch (standard_80387_constant_p (x))
7177 /* Return the CONST_DOUBLE representing the 80387 constant that is
7178 loaded by the specified special instruction. The argument IDX
7179 matches the return value from standard_80387_constant_p. */
7182 standard_80387_constant_rtx (int idx)
7186 if (! ext_80387_constants_init)
7187 init_ext_80387_constants ();
7203 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
7207 /* Return 1 if mode is a valid mode for sse. */
7209 standard_sse_mode_p (enum machine_mode mode)
7226 /* Return 1 if X is all 0s. For all 1s, return 2 if X is in 128bit
7227 SSE modes and SSE2 is enabled, return 3 if X is in 256bit AVX
7228 modes and AVX is enabled. */
7231 standard_sse_constant_p (rtx x)
7233 enum machine_mode mode = GET_MODE (x);
7235 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
7237 if (vector_all_ones_operand (x, mode))
7239 if (standard_sse_mode_p (mode))
7240 return TARGET_SSE2 ? 2 : -2;
7241 else if (VALID_AVX256_REG_MODE (mode))
7242 return TARGET_AVX ? 3 : -3;
7248 /* Return the opcode of the special instruction to be used to load
7252 standard_sse_constant_opcode (rtx insn, rtx x)
7254 switch (standard_sse_constant_p (x))
7257 switch (get_attr_mode (insn))
7260 return TARGET_AVX ? "vxorps\t%0, %0, %0" : "xorps\t%0, %0";
7262 return TARGET_AVX ? "vxorpd\t%0, %0, %0" : "xorpd\t%0, %0";
7264 return TARGET_AVX ? "vpxor\t%0, %0, %0" : "pxor\t%0, %0";
7266 return "vxorps\t%x0, %x0, %x0";
7268 return "vxorpd\t%x0, %x0, %x0";
7270 return "vpxor\t%x0, %x0, %x0";
7276 switch (get_attr_mode (insn))
7281 return "vpcmpeqd\t%0, %0, %0";
7287 return "pcmpeqd\t%0, %0";
7292 /* Returns 1 if OP contains a symbol reference */
7295 symbolic_reference_mentioned_p (rtx op)
7300 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
7303 fmt = GET_RTX_FORMAT (GET_CODE (op));
7304 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
7310 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
7311 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
7315 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
7322 /* Return 1 if it is appropriate to emit `ret' instructions in the
7323 body of a function. Do this only if the epilogue is simple, needing a
7324 couple of insns. Prior to reloading, we can't tell how many registers
7325 must be saved, so return 0 then. Return 0 if there is no frame
7326 marker to de-allocate. */
7329 ix86_can_use_return_insn_p (void)
7331 struct ix86_frame frame;
7333 if (! reload_completed || frame_pointer_needed)
7336 /* Don't allow more than 32 pop, since that's all we can do
7337 with one instruction. */
7338 if (crtl->args.pops_args
7339 && crtl->args.size >= 32768)
7342 ix86_compute_frame_layout (&frame);
7343 return frame.to_allocate == 0 && frame.padding0 == 0
7344 && (frame.nregs + frame.nsseregs) == 0;
7347 /* Value should be nonzero if functions must have frame pointers.
7348 Zero means the frame pointer need not be set up (and parms may
7349 be accessed via the stack pointer) in functions that seem suitable. */
7352 ix86_frame_pointer_required (void)
7354 /* If we accessed previous frames, then the generated code expects
7355 to be able to access the saved ebp value in our frame. */
7356 if (cfun->machine->accesses_prev_frame)
7359 /* Several x86 os'es need a frame pointer for other reasons,
7360 usually pertaining to setjmp. */
7361 if (SUBTARGET_FRAME_POINTER_REQUIRED)
7364 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7365 the frame pointer by default. Turn it back on now if we've not
7366 got a leaf function. */
7367 if (TARGET_OMIT_LEAF_FRAME_POINTER
7368 && (!current_function_is_leaf
7369 || ix86_current_function_calls_tls_descriptor))
7378 /* Record that the current function accesses previous call frames. */
7381 ix86_setup_frame_addresses (void)
7383 cfun->machine->accesses_prev_frame = 1;
7386 #ifndef USE_HIDDEN_LINKONCE
7387 # if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7388 # define USE_HIDDEN_LINKONCE 1
7390 # define USE_HIDDEN_LINKONCE 0
7394 static int pic_labels_used;
7396 /* Fills in the label name that should be used for a pc thunk for
7397 the given register. */
7400 get_pc_thunk_name (char name[32], unsigned int regno)
7402 gcc_assert (!TARGET_64BIT);
7404 if (USE_HIDDEN_LINKONCE)
7405 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
7407 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
7411 /* This function generates code for -fpic that loads %ebx with
7412 the return address of the caller and then returns. */
7415 ix86_file_end (void)
7420 for (regno = 0; regno < 8; ++regno)
7424 if (! ((pic_labels_used >> regno) & 1))
7427 get_pc_thunk_name (name, regno);
7432 switch_to_section (darwin_sections[text_coal_section]);
7433 fputs ("\t.weak_definition\t", asm_out_file);
7434 assemble_name (asm_out_file, name);
7435 fputs ("\n\t.private_extern\t", asm_out_file);
7436 assemble_name (asm_out_file, name);
7437 fputs ("\n", asm_out_file);
7438 ASM_OUTPUT_LABEL (asm_out_file, name);
7442 if (USE_HIDDEN_LINKONCE)
7446 decl = build_decl (FUNCTION_DECL, get_identifier (name),
7448 TREE_PUBLIC (decl) = 1;
7449 TREE_STATIC (decl) = 1;
7450 DECL_ONE_ONLY (decl) = 1;
7452 (*targetm.asm_out.unique_section) (decl, 0);
7453 switch_to_section (get_named_section (decl, NULL, 0));
7455 (*targetm.asm_out.globalize_label) (asm_out_file, name);
7456 fputs ("\t.hidden\t", asm_out_file);
7457 assemble_name (asm_out_file, name);
7458 fputc ('\n', asm_out_file);
7459 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
7463 switch_to_section (text_section);
7464 ASM_OUTPUT_LABEL (asm_out_file, name);
7467 xops[0] = gen_rtx_REG (Pmode, regno);
7468 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7469 output_asm_insn ("mov%z0\t{%1, %0|%0, %1}", xops);
7470 output_asm_insn ("ret", xops);
7473 if (NEED_INDICATE_EXEC_STACK)
7474 file_end_indicate_exec_stack ();
7477 /* Emit code for the SET_GOT patterns. */
7480 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
7486 if (TARGET_VXWORKS_RTP && flag_pic)
7488 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7489 xops[2] = gen_rtx_MEM (Pmode,
7490 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
7491 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
7493 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7494 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7495 an unadorned address. */
7496 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7497 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
7498 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
7502 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
7504 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
7506 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
7509 output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
7511 output_asm_insn ("call\t%a2", xops);
7514 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7515 is what will be referenced by the Mach-O PIC subsystem. */
7517 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7520 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7521 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
7524 output_asm_insn ("pop%z0\t%0", xops);
7529 get_pc_thunk_name (name, REGNO (dest));
7530 pic_labels_used |= 1 << REGNO (dest);
7532 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
7533 xops[2] = gen_rtx_MEM (QImode, xops[2]);
7534 output_asm_insn ("call\t%X2", xops);
7535 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7536 is what will be referenced by the Mach-O PIC subsystem. */
7539 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7541 targetm.asm_out.internal_label (asm_out_file, "L",
7542 CODE_LABEL_NUMBER (label));
7549 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
7550 output_asm_insn ("add%z0\t{%1, %0|%0, %1}", xops);
7552 output_asm_insn ("add%z0\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
7557 /* Generate an "push" pattern for input ARG. */
7562 return gen_rtx_SET (VOIDmode,
7564 gen_rtx_PRE_DEC (Pmode,
7565 stack_pointer_rtx)),
7569 /* Return >= 0 if there is an unused call-clobbered register available
7570 for the entire function. */
7573 ix86_select_alt_pic_regnum (void)
7575 if (current_function_is_leaf && !crtl->profile
7576 && !ix86_current_function_calls_tls_descriptor)
7579 /* Can't use the same register for both PIC and DRAP. */
7581 drap = REGNO (crtl->drap_reg);
7584 for (i = 2; i >= 0; --i)
7585 if (i != drap && !df_regs_ever_live_p (i))
7589 return INVALID_REGNUM;
7592 /* Return 1 if we need to save REGNO. */
7594 ix86_save_reg (unsigned int regno, int maybe_eh_return)
7596 if (pic_offset_table_rtx
7597 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
7598 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
7600 || crtl->calls_eh_return
7601 || crtl->uses_const_pool))
7603 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
7608 if (crtl->calls_eh_return && maybe_eh_return)
7613 unsigned test = EH_RETURN_DATA_REGNO (i);
7614 if (test == INVALID_REGNUM)
7622 && regno == REGNO (crtl->drap_reg))
7625 return (df_regs_ever_live_p (regno)
7626 && !call_used_regs[regno]
7627 && !fixed_regs[regno]
7628 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
7631 /* Return number of saved general prupose registers. */
7634 ix86_nsaved_regs (void)
7639 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7640 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7645 /* Return number of saved SSE registrers. */
7648 ix86_nsaved_sseregs (void)
7653 if (ix86_cfun_abi () != MS_ABI)
7655 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7656 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7661 /* Given FROM and TO register numbers, say whether this elimination is
7662 allowed. If stack alignment is needed, we can only replace argument
7663 pointer with hard frame pointer, or replace frame pointer with stack
7664 pointer. Otherwise, frame pointer elimination is automatically
7665 handled and all other eliminations are valid. */
7668 ix86_can_eliminate (int from, int to)
7670 if (stack_realign_fp)
7671 return ((from == ARG_POINTER_REGNUM
7672 && to == HARD_FRAME_POINTER_REGNUM)
7673 || (from == FRAME_POINTER_REGNUM
7674 && to == STACK_POINTER_REGNUM));
7676 return to == STACK_POINTER_REGNUM ? !frame_pointer_needed : 1;
7679 /* Return the offset between two registers, one to be eliminated, and the other
7680 its replacement, at the start of a routine. */
7683 ix86_initial_elimination_offset (int from, int to)
7685 struct ix86_frame frame;
7686 ix86_compute_frame_layout (&frame);
7688 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7689 return frame.hard_frame_pointer_offset;
7690 else if (from == FRAME_POINTER_REGNUM
7691 && to == HARD_FRAME_POINTER_REGNUM)
7692 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
7695 gcc_assert (to == STACK_POINTER_REGNUM);
7697 if (from == ARG_POINTER_REGNUM)
7698 return frame.stack_pointer_offset;
7700 gcc_assert (from == FRAME_POINTER_REGNUM);
7701 return frame.stack_pointer_offset - frame.frame_pointer_offset;
7705 /* In a dynamically-aligned function, we can't know the offset from
7706 stack pointer to frame pointer, so we must ensure that setjmp
7707 eliminates fp against the hard fp (%ebp) rather than trying to
7708 index from %esp up to the top of the frame across a gap that is
7709 of unknown (at compile-time) size. */
7711 ix86_builtin_setjmp_frame_value (void)
7713 return stack_realign_fp ? hard_frame_pointer_rtx : virtual_stack_vars_rtx;
7716 /* Fill structure ix86_frame about frame of currently computed function. */
7719 ix86_compute_frame_layout (struct ix86_frame *frame)
7721 HOST_WIDE_INT total_size;
7722 unsigned int stack_alignment_needed;
7723 HOST_WIDE_INT offset;
7724 unsigned int preferred_alignment;
7725 HOST_WIDE_INT size = get_frame_size ();
7727 frame->nregs = ix86_nsaved_regs ();
7728 frame->nsseregs = ix86_nsaved_sseregs ();
7731 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
7732 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
7734 /* MS ABI seem to require stack alignment to be always 16 except for function
7736 if (ix86_cfun_abi () == MS_ABI && preferred_alignment < 16)
7738 preferred_alignment = 16;
7739 stack_alignment_needed = 16;
7740 crtl->preferred_stack_boundary = 128;
7741 crtl->stack_alignment_needed = 128;
7744 gcc_assert (!size || stack_alignment_needed);
7745 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
7746 gcc_assert (preferred_alignment <= stack_alignment_needed);
7748 /* During reload iteration the amount of registers saved can change.
7749 Recompute the value as needed. Do not recompute when amount of registers
7750 didn't change as reload does multiple calls to the function and does not
7751 expect the decision to change within single iteration. */
7752 if (!optimize_function_for_size_p (cfun)
7753 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
7755 int count = frame->nregs;
7757 cfun->machine->use_fast_prologue_epilogue_nregs = count;
7758 /* The fast prologue uses move instead of push to save registers. This
7759 is significantly longer, but also executes faster as modern hardware
7760 can execute the moves in parallel, but can't do that for push/pop.
7762 Be careful about choosing what prologue to emit: When function takes
7763 many instructions to execute we may use slow version as well as in
7764 case function is known to be outside hot spot (this is known with
7765 feedback only). Weight the size of function by number of registers
7766 to save as it is cheap to use one or two push instructions but very
7767 slow to use many of them. */
7769 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
7770 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
7771 || (flag_branch_probabilities
7772 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
7773 cfun->machine->use_fast_prologue_epilogue = false;
7775 cfun->machine->use_fast_prologue_epilogue
7776 = !expensive_function_p (count);
7778 if (TARGET_PROLOGUE_USING_MOVE
7779 && cfun->machine->use_fast_prologue_epilogue)
7780 frame->save_regs_using_mov = true;
7782 frame->save_regs_using_mov = false;
7785 /* Skip return address and saved base pointer. */
7786 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
7788 frame->hard_frame_pointer_offset = offset;
7790 /* Set offset to aligned because the realigned frame starts from
7792 if (stack_realign_fp)
7793 offset = (offset + stack_alignment_needed -1) & -stack_alignment_needed;
7795 /* Register save area */
7796 offset += frame->nregs * UNITS_PER_WORD;
7798 /* Align SSE reg save area. */
7799 if (frame->nsseregs)
7800 frame->padding0 = ((offset + 16 - 1) & -16) - offset;
7802 frame->padding0 = 0;
7804 /* SSE register save area. */
7805 offset += frame->padding0 + frame->nsseregs * 16;
7808 frame->va_arg_size = ix86_varargs_gpr_size + ix86_varargs_fpr_size;
7809 offset += frame->va_arg_size;
7811 /* Align start of frame for local function. */
7812 frame->padding1 = ((offset + stack_alignment_needed - 1)
7813 & -stack_alignment_needed) - offset;
7815 offset += frame->padding1;
7817 /* Frame pointer points here. */
7818 frame->frame_pointer_offset = offset;
7822 /* Add outgoing arguments area. Can be skipped if we eliminated
7823 all the function calls as dead code.
7824 Skipping is however impossible when function calls alloca. Alloca
7825 expander assumes that last crtl->outgoing_args_size
7826 of stack frame are unused. */
7827 if (ACCUMULATE_OUTGOING_ARGS
7828 && (!current_function_is_leaf || cfun->calls_alloca
7829 || ix86_current_function_calls_tls_descriptor))
7831 offset += crtl->outgoing_args_size;
7832 frame->outgoing_arguments_size = crtl->outgoing_args_size;
7835 frame->outgoing_arguments_size = 0;
7837 /* Align stack boundary. Only needed if we're calling another function
7839 if (!current_function_is_leaf || cfun->calls_alloca
7840 || ix86_current_function_calls_tls_descriptor)
7841 frame->padding2 = ((offset + preferred_alignment - 1)
7842 & -preferred_alignment) - offset;
7844 frame->padding2 = 0;
7846 offset += frame->padding2;
7848 /* We've reached end of stack frame. */
7849 frame->stack_pointer_offset = offset;
7851 /* Size prologue needs to allocate. */
7852 frame->to_allocate =
7853 (size + frame->padding1 + frame->padding2
7854 + frame->outgoing_arguments_size + frame->va_arg_size);
7856 if ((!frame->to_allocate && frame->nregs <= 1)
7857 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
7858 frame->save_regs_using_mov = false;
7860 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
7861 && current_function_sp_is_unchanging
7862 && current_function_is_leaf
7863 && !ix86_current_function_calls_tls_descriptor)
7865 frame->red_zone_size = frame->to_allocate;
7866 if (frame->save_regs_using_mov)
7867 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
7868 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
7869 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
7872 frame->red_zone_size = 0;
7873 frame->to_allocate -= frame->red_zone_size;
7874 frame->stack_pointer_offset -= frame->red_zone_size;
7876 fprintf (stderr, "\n");
7877 fprintf (stderr, "size: %ld\n", (long)size);
7878 fprintf (stderr, "nregs: %ld\n", (long)frame->nregs);
7879 fprintf (stderr, "nsseregs: %ld\n", (long)frame->nsseregs);
7880 fprintf (stderr, "padding0: %ld\n", (long)frame->padding0);
7881 fprintf (stderr, "alignment1: %ld\n", (long)stack_alignment_needed);
7882 fprintf (stderr, "padding1: %ld\n", (long)frame->padding1);
7883 fprintf (stderr, "va_arg: %ld\n", (long)frame->va_arg_size);
7884 fprintf (stderr, "padding2: %ld\n", (long)frame->padding2);
7885 fprintf (stderr, "to_allocate: %ld\n", (long)frame->to_allocate);
7886 fprintf (stderr, "red_zone_size: %ld\n", (long)frame->red_zone_size);
7887 fprintf (stderr, "frame_pointer_offset: %ld\n", (long)frame->frame_pointer_offset);
7888 fprintf (stderr, "hard_frame_pointer_offset: %ld\n",
7889 (long)frame->hard_frame_pointer_offset);
7890 fprintf (stderr, "stack_pointer_offset: %ld\n", (long)frame->stack_pointer_offset);
7891 fprintf (stderr, "current_function_is_leaf: %ld\n", (long)current_function_is_leaf);
7892 fprintf (stderr, "cfun->calls_alloca: %ld\n", (long)cfun->calls_alloca);
7893 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
7897 /* Emit code to save registers in the prologue. */
7900 ix86_emit_save_regs (void)
7905 for (regno = FIRST_PSEUDO_REGISTER - 1; regno-- > 0; )
7906 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7908 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
7909 RTX_FRAME_RELATED_P (insn) = 1;
7913 /* Emit code to save registers using MOV insns. First register
7914 is restored from POINTER + OFFSET. */
7916 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
7921 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7922 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7924 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
7926 gen_rtx_REG (Pmode, regno));
7927 RTX_FRAME_RELATED_P (insn) = 1;
7928 offset += UNITS_PER_WORD;
7932 /* Emit code to save registers using MOV insns. First register
7933 is restored from POINTER + OFFSET. */
7935 ix86_emit_save_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
7941 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7942 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7944 mem = adjust_address (gen_rtx_MEM (TImode, pointer), TImode, offset);
7945 set_mem_align (mem, 128);
7946 insn = emit_move_insn (mem, gen_rtx_REG (TImode, regno));
7947 RTX_FRAME_RELATED_P (insn) = 1;
7952 /* Expand prologue or epilogue stack adjustment.
7953 The pattern exist to put a dependency on all ebp-based memory accesses.
7954 STYLE should be negative if instructions should be marked as frame related,
7955 zero if %r11 register is live and cannot be freely used and positive
7959 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
7964 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
7965 else if (x86_64_immediate_operand (offset, DImode))
7966 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
7970 /* r11 is used by indirect sibcall return as well, set before the
7971 epilogue and used after the epilogue. ATM indirect sibcall
7972 shouldn't be used together with huge frame sizes in one
7973 function because of the frame_size check in sibcall.c. */
7975 r11 = gen_rtx_REG (DImode, R11_REG);
7976 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
7978 RTX_FRAME_RELATED_P (insn) = 1;
7979 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
7983 RTX_FRAME_RELATED_P (insn) = 1;
7986 /* Find an available register to be used as dynamic realign argument
7987 pointer regsiter. Such a register will be written in prologue and
7988 used in begin of body, so it must not be
7989 1. parameter passing register.
7991 We reuse static-chain register if it is available. Otherwise, we
7992 use DI for i386 and R13 for x86-64. We chose R13 since it has
7995 Return: the regno of chosen register. */
7998 find_drap_reg (void)
8000 tree decl = cfun->decl;
8004 /* Use R13 for nested function or function need static chain.
8005 Since function with tail call may use any caller-saved
8006 registers in epilogue, DRAP must not use caller-saved
8007 register in such case. */
8008 if ((decl_function_context (decl)
8009 && !DECL_NO_STATIC_CHAIN (decl))
8010 || crtl->tail_call_emit)
8017 /* Use DI for nested function or function need static chain.
8018 Since function with tail call may use any caller-saved
8019 registers in epilogue, DRAP must not use caller-saved
8020 register in such case. */
8021 if ((decl_function_context (decl)
8022 && !DECL_NO_STATIC_CHAIN (decl))
8023 || crtl->tail_call_emit)
8026 /* Reuse static chain register if it isn't used for parameter
8028 if (ix86_function_regparm (TREE_TYPE (decl), decl) <= 2
8029 && !lookup_attribute ("fastcall",
8030 TYPE_ATTRIBUTES (TREE_TYPE (decl))))
8037 /* Update incoming stack boundary and estimated stack alignment. */
8040 ix86_update_stack_boundary (void)
8042 /* Prefer the one specified at command line. */
8043 ix86_incoming_stack_boundary
8044 = (ix86_user_incoming_stack_boundary
8045 ? ix86_user_incoming_stack_boundary
8046 : ix86_default_incoming_stack_boundary);
8048 /* Incoming stack alignment can be changed on individual functions
8049 via force_align_arg_pointer attribute. We use the smallest
8050 incoming stack boundary. */
8051 if (ix86_incoming_stack_boundary > MIN_STACK_BOUNDARY
8052 && lookup_attribute (ix86_force_align_arg_pointer_string,
8053 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
8054 ix86_incoming_stack_boundary = MIN_STACK_BOUNDARY;
8056 /* The incoming stack frame has to be aligned at least at
8057 parm_stack_boundary. */
8058 if (ix86_incoming_stack_boundary < crtl->parm_stack_boundary)
8059 ix86_incoming_stack_boundary = crtl->parm_stack_boundary;
8061 /* Stack at entrance of main is aligned by runtime. We use the
8062 smallest incoming stack boundary. */
8063 if (ix86_incoming_stack_boundary > MAIN_STACK_BOUNDARY
8064 && DECL_NAME (current_function_decl)
8065 && MAIN_NAME_P (DECL_NAME (current_function_decl))
8066 && DECL_FILE_SCOPE_P (current_function_decl))
8067 ix86_incoming_stack_boundary = MAIN_STACK_BOUNDARY;
8069 /* x86_64 vararg needs 16byte stack alignment for register save
8073 && crtl->stack_alignment_estimated < 128)
8074 crtl->stack_alignment_estimated = 128;
8077 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
8078 needed or an rtx for DRAP otherwise. */
8081 ix86_get_drap_rtx (void)
8083 if (ix86_force_drap || !ACCUMULATE_OUTGOING_ARGS)
8084 crtl->need_drap = true;
8086 if (stack_realign_drap)
8088 /* Assign DRAP to vDRAP and returns vDRAP */
8089 unsigned int regno = find_drap_reg ();
8094 arg_ptr = gen_rtx_REG (Pmode, regno);
8095 crtl->drap_reg = arg_ptr;
8098 drap_vreg = copy_to_reg (arg_ptr);
8102 insn = emit_insn_before (seq, NEXT_INSN (entry_of_function ()));
8103 RTX_FRAME_RELATED_P (insn) = 1;
8110 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
8113 ix86_internal_arg_pointer (void)
8115 return virtual_incoming_args_rtx;
8118 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
8119 This is called from dwarf2out.c to emit call frame instructions
8120 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
8122 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
8124 rtx unspec = SET_SRC (pattern);
8125 gcc_assert (GET_CODE (unspec) == UNSPEC);
8129 case UNSPEC_REG_SAVE:
8130 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
8131 SET_DEST (pattern));
8133 case UNSPEC_DEF_CFA:
8134 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
8135 INTVAL (XVECEXP (unspec, 0, 0)));
8142 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
8143 to be generated in correct form. */
8145 ix86_finalize_stack_realign_flags (void)
8147 /* Check if stack realign is really needed after reload, and
8148 stores result in cfun */
8149 unsigned int incoming_stack_boundary
8150 = (crtl->parm_stack_boundary > ix86_incoming_stack_boundary
8151 ? crtl->parm_stack_boundary : ix86_incoming_stack_boundary);
8152 unsigned int stack_realign = (incoming_stack_boundary
8153 < (current_function_is_leaf
8154 ? crtl->max_used_stack_slot_alignment
8155 : crtl->stack_alignment_needed));
8157 if (crtl->stack_realign_finalized)
8159 /* After stack_realign_needed is finalized, we can't no longer
8161 gcc_assert (crtl->stack_realign_needed == stack_realign);
8165 crtl->stack_realign_needed = stack_realign;
8166 crtl->stack_realign_finalized = true;
8170 /* Expand the prologue into a bunch of separate insns. */
8173 ix86_expand_prologue (void)
8177 struct ix86_frame frame;
8178 HOST_WIDE_INT allocate;
8180 ix86_finalize_stack_realign_flags ();
8182 /* DRAP should not coexist with stack_realign_fp */
8183 gcc_assert (!(crtl->drap_reg && stack_realign_fp));
8185 ix86_compute_frame_layout (&frame);
8187 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
8188 of DRAP is needed and stack realignment is really needed after reload */
8189 if (crtl->drap_reg && crtl->stack_realign_needed)
8192 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8193 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8194 ? 0 : UNITS_PER_WORD);
8196 gcc_assert (stack_realign_drap);
8198 /* Grab the argument pointer. */
8199 x = plus_constant (stack_pointer_rtx,
8200 (UNITS_PER_WORD + param_ptr_offset));
8203 /* Only need to push parameter pointer reg if it is caller
8205 if (!call_used_regs[REGNO (crtl->drap_reg)])
8207 /* Push arg pointer reg */
8208 insn = emit_insn (gen_push (y));
8209 RTX_FRAME_RELATED_P (insn) = 1;
8212 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
8213 RTX_FRAME_RELATED_P (insn) = 1;
8215 /* Align the stack. */
8216 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8218 GEN_INT (-align_bytes)));
8219 RTX_FRAME_RELATED_P (insn) = 1;
8221 /* Replicate the return address on the stack so that return
8222 address can be reached via (argp - 1) slot. This is needed
8223 to implement macro RETURN_ADDR_RTX and intrinsic function
8224 expand_builtin_return_addr etc. */
8226 x = gen_frame_mem (Pmode,
8227 plus_constant (x, -UNITS_PER_WORD));
8228 insn = emit_insn (gen_push (x));
8229 RTX_FRAME_RELATED_P (insn) = 1;
8232 /* Note: AT&T enter does NOT have reversed args. Enter is probably
8233 slower on all targets. Also sdb doesn't like it. */
8235 if (frame_pointer_needed)
8237 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
8238 RTX_FRAME_RELATED_P (insn) = 1;
8240 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8241 RTX_FRAME_RELATED_P (insn) = 1;
8244 if (stack_realign_fp)
8246 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8247 gcc_assert (align_bytes > MIN_STACK_BOUNDARY / BITS_PER_UNIT);
8249 /* Align the stack. */
8250 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8252 GEN_INT (-align_bytes)));
8253 RTX_FRAME_RELATED_P (insn) = 1;
8256 allocate = frame.to_allocate + frame.nsseregs * 16 + frame.padding0;
8258 if (!frame.save_regs_using_mov)
8259 ix86_emit_save_regs ();
8261 allocate += frame.nregs * UNITS_PER_WORD;
8263 /* When using red zone we may start register saving before allocating
8264 the stack frame saving one cycle of the prologue. However I will
8265 avoid doing this if I am going to have to probe the stack since
8266 at least on x86_64 the stack probe can turn into a call that clobbers
8267 a red zone location */
8268 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && frame.save_regs_using_mov
8269 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
8270 ix86_emit_save_regs_using_mov ((frame_pointer_needed
8271 && !crtl->stack_realign_needed)
8272 ? hard_frame_pointer_rtx
8273 : stack_pointer_rtx,
8274 -frame.nregs * UNITS_PER_WORD);
8278 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
8279 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8280 GEN_INT (-allocate), -1);
8283 /* Only valid for Win32. */
8284 rtx eax = gen_rtx_REG (Pmode, AX_REG);
8288 gcc_assert (!TARGET_64BIT || cfun->machine->call_abi == MS_ABI);
8290 if (cfun->machine->call_abi == MS_ABI)
8293 eax_live = ix86_eax_live_at_start_p ();
8297 emit_insn (gen_push (eax));
8298 allocate -= UNITS_PER_WORD;
8301 emit_move_insn (eax, GEN_INT (allocate));
8304 insn = gen_allocate_stack_worker_64 (eax, eax);
8306 insn = gen_allocate_stack_worker_32 (eax, eax);
8307 insn = emit_insn (insn);
8308 RTX_FRAME_RELATED_P (insn) = 1;
8309 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
8310 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8311 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8312 t, REG_NOTES (insn));
8316 if (frame_pointer_needed)
8317 t = plus_constant (hard_frame_pointer_rtx,
8320 - frame.nregs * UNITS_PER_WORD);
8322 t = plus_constant (stack_pointer_rtx, allocate);
8323 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
8327 if (frame.save_regs_using_mov
8328 && !(!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
8329 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
8331 if (!frame_pointer_needed
8332 || !(frame.to_allocate + frame.padding0)
8333 || crtl->stack_realign_needed)
8334 ix86_emit_save_regs_using_mov (stack_pointer_rtx,
8336 + frame.nsseregs * 16 + frame.padding0);
8338 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
8339 -frame.nregs * UNITS_PER_WORD);
8341 if (!frame_pointer_needed
8342 || !(frame.to_allocate + frame.padding0)
8343 || crtl->stack_realign_needed)
8344 ix86_emit_save_sse_regs_using_mov (stack_pointer_rtx,
8347 ix86_emit_save_sse_regs_using_mov (hard_frame_pointer_rtx,
8348 - frame.nregs * UNITS_PER_WORD
8349 - frame.nsseregs * 16
8352 pic_reg_used = false;
8353 if (pic_offset_table_rtx
8354 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
8357 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
8359 if (alt_pic_reg_used != INVALID_REGNUM)
8360 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
8362 pic_reg_used = true;
8369 if (ix86_cmodel == CM_LARGE_PIC)
8371 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
8372 rtx label = gen_label_rtx ();
8374 LABEL_PRESERVE_P (label) = 1;
8375 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
8376 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
8377 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
8378 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
8379 pic_offset_table_rtx, tmp_reg));
8382 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
8385 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
8388 /* In the pic_reg_used case, make sure that the got load isn't deleted
8389 when mcount needs it. Blockage to avoid call movement across mcount
8390 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
8392 if (crtl->profile && pic_reg_used)
8393 emit_insn (gen_prologue_use (pic_offset_table_rtx));
8395 if (crtl->drap_reg && !crtl->stack_realign_needed)
8397 /* vDRAP is setup but after reload it turns out stack realign
8398 isn't necessary, here we will emit prologue to setup DRAP
8399 without stack realign adjustment */
8400 int drap_bp_offset = UNITS_PER_WORD * 2;
8401 rtx x = plus_constant (hard_frame_pointer_rtx, drap_bp_offset);
8402 insn = emit_insn (gen_rtx_SET (VOIDmode, crtl->drap_reg, x));
8405 /* Prevent instructions from being scheduled into register save push
8406 sequence when access to the redzone area is done through frame pointer.
8407 The offset betweeh the frame pointer and the stack pointer is calculated
8408 relative to the value of the stack pointer at the end of the function
8409 prologue, and moving instructions that access redzone area via frame
8410 pointer inside push sequence violates this assumption. */
8411 if (frame_pointer_needed && frame.red_zone_size)
8412 emit_insn (gen_memory_blockage ());
8414 /* Emit cld instruction if stringops are used in the function. */
8415 if (TARGET_CLD && ix86_current_function_needs_cld)
8416 emit_insn (gen_cld ());
8419 /* Emit code to restore saved registers using MOV insns. First register
8420 is restored from POINTER + OFFSET. */
8422 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8423 int maybe_eh_return)
8426 rtx base_address = gen_rtx_MEM (Pmode, pointer);
8428 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8429 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8431 /* Ensure that adjust_address won't be forced to produce pointer
8432 out of range allowed by x86-64 instruction set. */
8433 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8437 r11 = gen_rtx_REG (DImode, R11_REG);
8438 emit_move_insn (r11, GEN_INT (offset));
8439 emit_insn (gen_adddi3 (r11, r11, pointer));
8440 base_address = gen_rtx_MEM (Pmode, r11);
8443 emit_move_insn (gen_rtx_REG (Pmode, regno),
8444 adjust_address (base_address, Pmode, offset));
8445 offset += UNITS_PER_WORD;
8449 /* Emit code to restore saved registers using MOV insns. First register
8450 is restored from POINTER + OFFSET. */
8452 ix86_emit_restore_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8453 int maybe_eh_return)
8456 rtx base_address = gen_rtx_MEM (TImode, pointer);
8459 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8460 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8462 /* Ensure that adjust_address won't be forced to produce pointer
8463 out of range allowed by x86-64 instruction set. */
8464 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8468 r11 = gen_rtx_REG (DImode, R11_REG);
8469 emit_move_insn (r11, GEN_INT (offset));
8470 emit_insn (gen_adddi3 (r11, r11, pointer));
8471 base_address = gen_rtx_MEM (TImode, r11);
8474 mem = adjust_address (base_address, TImode, offset);
8475 set_mem_align (mem, 128);
8476 emit_move_insn (gen_rtx_REG (TImode, regno), mem);
8481 /* Restore function stack, frame, and registers. */
8484 ix86_expand_epilogue (int style)
8488 struct ix86_frame frame;
8489 HOST_WIDE_INT offset;
8491 ix86_finalize_stack_realign_flags ();
8493 /* When stack is realigned, SP must be valid. */
8494 sp_valid = (!frame_pointer_needed
8495 || current_function_sp_is_unchanging
8496 || stack_realign_fp);
8498 ix86_compute_frame_layout (&frame);
8500 /* See the comment about red zone and frame
8501 pointer usage in ix86_expand_prologue. */
8502 if (frame_pointer_needed && frame.red_zone_size)
8503 emit_insn (gen_memory_blockage ());
8505 /* Calculate start of saved registers relative to ebp. Special care
8506 must be taken for the normal return case of a function using
8507 eh_return: the eax and edx registers are marked as saved, but not
8508 restored along this path. */
8509 offset = frame.nregs;
8510 if (crtl->calls_eh_return && style != 2)
8512 offset *= -UNITS_PER_WORD;
8513 offset -= frame.nsseregs * 16 + frame.padding0;
8515 /* If we're only restoring one register and sp is not valid then
8516 using a move instruction to restore the register since it's
8517 less work than reloading sp and popping the register.
8519 The default code result in stack adjustment using add/lea instruction,
8520 while this code results in LEAVE instruction (or discrete equivalent),
8521 so it is profitable in some other cases as well. Especially when there
8522 are no registers to restore. We also use this code when TARGET_USE_LEAVE
8523 and there is exactly one register to pop. This heuristic may need some
8524 tuning in future. */
8525 if ((!sp_valid && (frame.nregs + frame.nsseregs) <= 1)
8526 || (TARGET_EPILOGUE_USING_MOVE
8527 && cfun->machine->use_fast_prologue_epilogue
8528 && ((frame.nregs + frame.nsseregs) > 1
8529 || (frame.to_allocate + frame.padding0) != 0))
8530 || (frame_pointer_needed && !(frame.nregs + frame.nsseregs)
8531 && (frame.to_allocate + frame.padding0) != 0)
8532 || (frame_pointer_needed && TARGET_USE_LEAVE
8533 && cfun->machine->use_fast_prologue_epilogue
8534 && (frame.nregs + frame.nsseregs) == 1)
8535 || crtl->calls_eh_return)
8537 /* Restore registers. We can use ebp or esp to address the memory
8538 locations. If both are available, default to ebp, since offsets
8539 are known to be small. Only exception is esp pointing directly
8540 to the end of block of saved registers, where we may simplify
8543 If we are realigning stack with bp and sp, regs restore can't
8544 be addressed by bp. sp must be used instead. */
8546 if (!frame_pointer_needed
8547 || (sp_valid && !(frame.to_allocate + frame.padding0))
8548 || stack_realign_fp)
8550 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8551 frame.to_allocate, style == 2);
8552 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
8554 + frame.nsseregs * 16
8555 + frame.padding0, style == 2);
8559 ix86_emit_restore_sse_regs_using_mov (hard_frame_pointer_rtx,
8560 offset, style == 2);
8561 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
8563 + frame.nsseregs * 16
8564 + frame.padding0, style == 2);
8567 /* eh_return epilogues need %ecx added to the stack pointer. */
8570 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
8572 /* Stack align doesn't work with eh_return. */
8573 gcc_assert (!crtl->stack_realign_needed);
8575 if (frame_pointer_needed)
8577 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
8578 tmp = plus_constant (tmp, UNITS_PER_WORD);
8579 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
8581 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
8582 emit_move_insn (hard_frame_pointer_rtx, tmp);
8584 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
8589 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
8590 tmp = plus_constant (tmp, (frame.to_allocate
8591 + frame.nregs * UNITS_PER_WORD
8592 + frame.nsseregs * 16
8594 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
8597 else if (!frame_pointer_needed)
8598 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8599 GEN_INT (frame.to_allocate
8600 + frame.nregs * UNITS_PER_WORD
8601 + frame.nsseregs * 16
8604 /* If not an i386, mov & pop is faster than "leave". */
8605 else if (TARGET_USE_LEAVE || optimize_function_for_size_p (cfun)
8606 || !cfun->machine->use_fast_prologue_epilogue)
8607 emit_insn ((*ix86_gen_leave) ());
8610 pro_epilogue_adjust_stack (stack_pointer_rtx,
8611 hard_frame_pointer_rtx,
8614 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8619 /* First step is to deallocate the stack frame so that we can
8622 If we realign stack with frame pointer, then stack pointer
8623 won't be able to recover via lea $offset(%bp), %sp, because
8624 there is a padding area between bp and sp for realign.
8625 "add $to_allocate, %sp" must be used instead. */
8628 gcc_assert (frame_pointer_needed);
8629 gcc_assert (!stack_realign_fp);
8630 pro_epilogue_adjust_stack (stack_pointer_rtx,
8631 hard_frame_pointer_rtx,
8632 GEN_INT (offset), style);
8633 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8635 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8636 GEN_INT (frame.nsseregs * 16 +
8637 frame.padding0), style);
8639 else if (frame.to_allocate || frame.padding0 || frame.nsseregs)
8641 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8644 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8645 GEN_INT (frame.to_allocate
8646 + frame.nsseregs * 16
8647 + frame.padding0), style);
8650 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8651 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, false))
8652 emit_insn ((*ix86_gen_pop1) (gen_rtx_REG (Pmode, regno)));
8653 if (frame_pointer_needed)
8655 /* Leave results in shorter dependency chains on CPUs that are
8656 able to grok it fast. */
8657 if (TARGET_USE_LEAVE)
8658 emit_insn ((*ix86_gen_leave) ());
8661 /* For stack realigned really happens, recover stack
8662 pointer to hard frame pointer is a must, if not using
8664 if (stack_realign_fp)
8665 pro_epilogue_adjust_stack (stack_pointer_rtx,
8666 hard_frame_pointer_rtx,
8668 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8673 if (crtl->drap_reg && crtl->stack_realign_needed)
8675 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8676 ? 0 : UNITS_PER_WORD);
8677 gcc_assert (stack_realign_drap);
8678 emit_insn ((*ix86_gen_add3) (stack_pointer_rtx,
8680 GEN_INT (-(UNITS_PER_WORD
8681 + param_ptr_offset))));
8682 if (!call_used_regs[REGNO (crtl->drap_reg)])
8683 emit_insn ((*ix86_gen_pop1) (crtl->drap_reg));
8687 /* Sibcall epilogues don't want a return instruction. */
8691 if (crtl->args.pops_args && crtl->args.size)
8693 rtx popc = GEN_INT (crtl->args.pops_args);
8695 /* i386 can only pop 64K bytes. If asked to pop more, pop
8696 return address, do explicit add, and jump indirectly to the
8699 if (crtl->args.pops_args >= 65536)
8701 rtx ecx = gen_rtx_REG (SImode, CX_REG);
8703 /* There is no "pascal" calling convention in any 64bit ABI. */
8704 gcc_assert (!TARGET_64BIT);
8706 emit_insn (gen_popsi1 (ecx));
8707 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
8708 emit_jump_insn (gen_return_indirect_internal (ecx));
8711 emit_jump_insn (gen_return_pop_internal (popc));
8714 emit_jump_insn (gen_return_internal ());
8717 /* Reset from the function's potential modifications. */
8720 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
8721 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8723 if (pic_offset_table_rtx)
8724 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
8726 /* Mach-O doesn't support labels at the end of objects, so if
8727 it looks like we might want one, insert a NOP. */
8729 rtx insn = get_last_insn ();
8732 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
8733 insn = PREV_INSN (insn);
8737 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
8738 fputs ("\tnop\n", file);
8744 /* Extract the parts of an RTL expression that is a valid memory address
8745 for an instruction. Return 0 if the structure of the address is
8746 grossly off. Return -1 if the address contains ASHIFT, so it is not
8747 strictly valid, but still used for computing length of lea instruction. */
8750 ix86_decompose_address (rtx addr, struct ix86_address *out)
8752 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
8753 rtx base_reg, index_reg;
8754 HOST_WIDE_INT scale = 1;
8755 rtx scale_rtx = NULL_RTX;
8757 enum ix86_address_seg seg = SEG_DEFAULT;
8759 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
8761 else if (GET_CODE (addr) == PLUS)
8771 addends[n++] = XEXP (op, 1);
8774 while (GET_CODE (op) == PLUS);
8779 for (i = n; i >= 0; --i)
8782 switch (GET_CODE (op))
8787 index = XEXP (op, 0);
8788 scale_rtx = XEXP (op, 1);
8792 if (XINT (op, 1) == UNSPEC_TP
8793 && TARGET_TLS_DIRECT_SEG_REFS
8794 && seg == SEG_DEFAULT)
8795 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
8824 else if (GET_CODE (addr) == MULT)
8826 index = XEXP (addr, 0); /* index*scale */
8827 scale_rtx = XEXP (addr, 1);
8829 else if (GET_CODE (addr) == ASHIFT)
8833 /* We're called for lea too, which implements ashift on occasion. */
8834 index = XEXP (addr, 0);
8835 tmp = XEXP (addr, 1);
8836 if (!CONST_INT_P (tmp))
8838 scale = INTVAL (tmp);
8839 if ((unsigned HOST_WIDE_INT) scale > 3)
8845 disp = addr; /* displacement */
8847 /* Extract the integral value of scale. */
8850 if (!CONST_INT_P (scale_rtx))
8852 scale = INTVAL (scale_rtx);
8855 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
8856 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
8858 /* Allow arg pointer and stack pointer as index if there is not scaling. */
8859 if (base_reg && index_reg && scale == 1
8860 && (index_reg == arg_pointer_rtx
8861 || index_reg == frame_pointer_rtx
8862 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
8865 tmp = base, base = index, index = tmp;
8866 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
8869 /* Special case: %ebp cannot be encoded as a base without a displacement. */
8870 if ((base_reg == hard_frame_pointer_rtx
8871 || base_reg == frame_pointer_rtx
8872 || base_reg == arg_pointer_rtx) && !disp)
8875 /* Special case: on K6, [%esi] makes the instruction vector decoded.
8876 Avoid this by transforming to [%esi+0].
8877 Reload calls address legitimization without cfun defined, so we need
8878 to test cfun for being non-NULL. */
8879 if (TARGET_K6 && cfun && optimize_function_for_speed_p (cfun)
8880 && base_reg && !index_reg && !disp
8882 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
8885 /* Special case: encode reg+reg instead of reg*2. */
8886 if (!base && index && scale && scale == 2)
8887 base = index, base_reg = index_reg, scale = 1;
8889 /* Special case: scaling cannot be encoded without base or displacement. */
8890 if (!base && !disp && index && scale != 1)
8902 /* Return cost of the memory address x.
8903 For i386, it is better to use a complex address than let gcc copy
8904 the address into a reg and make a new pseudo. But not if the address
8905 requires to two regs - that would mean more pseudos with longer
8908 ix86_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
8910 struct ix86_address parts;
8912 int ok = ix86_decompose_address (x, &parts);
8916 if (parts.base && GET_CODE (parts.base) == SUBREG)
8917 parts.base = SUBREG_REG (parts.base);
8918 if (parts.index && GET_CODE (parts.index) == SUBREG)
8919 parts.index = SUBREG_REG (parts.index);
8921 /* Attempt to minimize number of registers in the address. */
8923 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
8925 && (!REG_P (parts.index)
8926 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
8930 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
8932 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
8933 && parts.base != parts.index)
8936 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
8937 since it's predecode logic can't detect the length of instructions
8938 and it degenerates to vector decoded. Increase cost of such
8939 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
8940 to split such addresses or even refuse such addresses at all.
8942 Following addressing modes are affected:
8947 The first and last case may be avoidable by explicitly coding the zero in
8948 memory address, but I don't have AMD-K6 machine handy to check this
8952 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
8953 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
8954 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
8960 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
8961 this is used for to form addresses to local data when -fPIC is in
8965 darwin_local_data_pic (rtx disp)
8967 return (GET_CODE (disp) == UNSPEC
8968 && XINT (disp, 1) == UNSPEC_MACHOPIC_OFFSET);
8971 /* Determine if a given RTX is a valid constant. We already know this
8972 satisfies CONSTANT_P. */
8975 legitimate_constant_p (rtx x)
8977 switch (GET_CODE (x))
8982 if (GET_CODE (x) == PLUS)
8984 if (!CONST_INT_P (XEXP (x, 1)))
8989 if (TARGET_MACHO && darwin_local_data_pic (x))
8992 /* Only some unspecs are valid as "constants". */
8993 if (GET_CODE (x) == UNSPEC)
8994 switch (XINT (x, 1))
8999 return TARGET_64BIT;
9002 x = XVECEXP (x, 0, 0);
9003 return (GET_CODE (x) == SYMBOL_REF
9004 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9006 x = XVECEXP (x, 0, 0);
9007 return (GET_CODE (x) == SYMBOL_REF
9008 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
9013 /* We must have drilled down to a symbol. */
9014 if (GET_CODE (x) == LABEL_REF)
9016 if (GET_CODE (x) != SYMBOL_REF)
9021 /* TLS symbols are never valid. */
9022 if (SYMBOL_REF_TLS_MODEL (x))
9025 /* DLLIMPORT symbols are never valid. */
9026 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
9027 && SYMBOL_REF_DLLIMPORT_P (x))
9032 if (GET_MODE (x) == TImode
9033 && x != CONST0_RTX (TImode)
9039 if (x == CONST0_RTX (GET_MODE (x)))
9047 /* Otherwise we handle everything else in the move patterns. */
9051 /* Determine if it's legal to put X into the constant pool. This
9052 is not possible for the address of thread-local symbols, which
9053 is checked above. */
9056 ix86_cannot_force_const_mem (rtx x)
9058 /* We can always put integral constants and vectors in memory. */
9059 switch (GET_CODE (x))
9069 return !legitimate_constant_p (x);
9072 /* Determine if a given RTX is a valid constant address. */
9075 constant_address_p (rtx x)
9077 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
9080 /* Nonzero if the constant value X is a legitimate general operand
9081 when generating PIC code. It is given that flag_pic is on and
9082 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
9085 legitimate_pic_operand_p (rtx x)
9089 switch (GET_CODE (x))
9092 inner = XEXP (x, 0);
9093 if (GET_CODE (inner) == PLUS
9094 && CONST_INT_P (XEXP (inner, 1)))
9095 inner = XEXP (inner, 0);
9097 /* Only some unspecs are valid as "constants". */
9098 if (GET_CODE (inner) == UNSPEC)
9099 switch (XINT (inner, 1))
9104 return TARGET_64BIT;
9106 x = XVECEXP (inner, 0, 0);
9107 return (GET_CODE (x) == SYMBOL_REF
9108 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9109 case UNSPEC_MACHOPIC_OFFSET:
9110 return legitimate_pic_address_disp_p (x);
9118 return legitimate_pic_address_disp_p (x);
9125 /* Determine if a given CONST RTX is a valid memory displacement
9129 legitimate_pic_address_disp_p (rtx disp)
9133 /* In 64bit mode we can allow direct addresses of symbols and labels
9134 when they are not dynamic symbols. */
9137 rtx op0 = disp, op1;
9139 switch (GET_CODE (disp))
9145 if (GET_CODE (XEXP (disp, 0)) != PLUS)
9147 op0 = XEXP (XEXP (disp, 0), 0);
9148 op1 = XEXP (XEXP (disp, 0), 1);
9149 if (!CONST_INT_P (op1)
9150 || INTVAL (op1) >= 16*1024*1024
9151 || INTVAL (op1) < -16*1024*1024)
9153 if (GET_CODE (op0) == LABEL_REF)
9155 if (GET_CODE (op0) != SYMBOL_REF)
9160 /* TLS references should always be enclosed in UNSPEC. */
9161 if (SYMBOL_REF_TLS_MODEL (op0))
9163 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
9164 && ix86_cmodel != CM_LARGE_PIC)
9172 if (GET_CODE (disp) != CONST)
9174 disp = XEXP (disp, 0);
9178 /* We are unsafe to allow PLUS expressions. This limit allowed distance
9179 of GOT tables. We should not need these anyway. */
9180 if (GET_CODE (disp) != UNSPEC
9181 || (XINT (disp, 1) != UNSPEC_GOTPCREL
9182 && XINT (disp, 1) != UNSPEC_GOTOFF
9183 && XINT (disp, 1) != UNSPEC_PLTOFF))
9186 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
9187 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
9193 if (GET_CODE (disp) == PLUS)
9195 if (!CONST_INT_P (XEXP (disp, 1)))
9197 disp = XEXP (disp, 0);
9201 if (TARGET_MACHO && darwin_local_data_pic (disp))
9204 if (GET_CODE (disp) != UNSPEC)
9207 switch (XINT (disp, 1))
9212 /* We need to check for both symbols and labels because VxWorks loads
9213 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
9215 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9216 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
9218 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
9219 While ABI specify also 32bit relocation but we don't produce it in
9220 small PIC model at all. */
9221 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9222 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
9224 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
9226 case UNSPEC_GOTTPOFF:
9227 case UNSPEC_GOTNTPOFF:
9228 case UNSPEC_INDNTPOFF:
9231 disp = XVECEXP (disp, 0, 0);
9232 return (GET_CODE (disp) == SYMBOL_REF
9233 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
9235 disp = XVECEXP (disp, 0, 0);
9236 return (GET_CODE (disp) == SYMBOL_REF
9237 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
9239 disp = XVECEXP (disp, 0, 0);
9240 return (GET_CODE (disp) == SYMBOL_REF
9241 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
9247 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
9248 memory address for an instruction. The MODE argument is the machine mode
9249 for the MEM expression that wants to use this address.
9251 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
9252 convert common non-canonical forms to canonical form so that they will
9256 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
9257 rtx addr, int strict)
9259 struct ix86_address parts;
9260 rtx base, index, disp;
9261 HOST_WIDE_INT scale;
9262 const char *reason = NULL;
9263 rtx reason_rtx = NULL_RTX;
9265 if (ix86_decompose_address (addr, &parts) <= 0)
9267 reason = "decomposition failed";
9272 index = parts.index;
9274 scale = parts.scale;
9276 /* Validate base register.
9278 Don't allow SUBREG's that span more than a word here. It can lead to spill
9279 failures when the base is one word out of a two word structure, which is
9280 represented internally as a DImode int. */
9289 else if (GET_CODE (base) == SUBREG
9290 && REG_P (SUBREG_REG (base))
9291 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
9293 reg = SUBREG_REG (base);
9296 reason = "base is not a register";
9300 if (GET_MODE (base) != Pmode)
9302 reason = "base is not in Pmode";
9306 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
9307 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
9309 reason = "base is not valid";
9314 /* Validate index register.
9316 Don't allow SUBREG's that span more than a word here -- same as above. */
9325 else if (GET_CODE (index) == SUBREG
9326 && REG_P (SUBREG_REG (index))
9327 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
9329 reg = SUBREG_REG (index);
9332 reason = "index is not a register";
9336 if (GET_MODE (index) != Pmode)
9338 reason = "index is not in Pmode";
9342 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
9343 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
9345 reason = "index is not valid";
9350 /* Validate scale factor. */
9353 reason_rtx = GEN_INT (scale);
9356 reason = "scale without index";
9360 if (scale != 2 && scale != 4 && scale != 8)
9362 reason = "scale is not a valid multiplier";
9367 /* Validate displacement. */
9372 if (GET_CODE (disp) == CONST
9373 && GET_CODE (XEXP (disp, 0)) == UNSPEC
9374 && XINT (XEXP (disp, 0), 1) != UNSPEC_MACHOPIC_OFFSET)
9375 switch (XINT (XEXP (disp, 0), 1))
9377 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
9378 used. While ABI specify also 32bit relocations, we don't produce
9379 them at all and use IP relative instead. */
9382 gcc_assert (flag_pic);
9384 goto is_legitimate_pic;
9385 reason = "64bit address unspec";
9388 case UNSPEC_GOTPCREL:
9389 gcc_assert (flag_pic);
9390 goto is_legitimate_pic;
9392 case UNSPEC_GOTTPOFF:
9393 case UNSPEC_GOTNTPOFF:
9394 case UNSPEC_INDNTPOFF:
9400 reason = "invalid address unspec";
9404 else if (SYMBOLIC_CONST (disp)
9408 && MACHOPIC_INDIRECT
9409 && !machopic_operand_p (disp)
9415 if (TARGET_64BIT && (index || base))
9417 /* foo@dtpoff(%rX) is ok. */
9418 if (GET_CODE (disp) != CONST
9419 || GET_CODE (XEXP (disp, 0)) != PLUS
9420 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
9421 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
9422 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
9423 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
9425 reason = "non-constant pic memory reference";
9429 else if (! legitimate_pic_address_disp_p (disp))
9431 reason = "displacement is an invalid pic construct";
9435 /* This code used to verify that a symbolic pic displacement
9436 includes the pic_offset_table_rtx register.
9438 While this is good idea, unfortunately these constructs may
9439 be created by "adds using lea" optimization for incorrect
9448 This code is nonsensical, but results in addressing
9449 GOT table with pic_offset_table_rtx base. We can't
9450 just refuse it easily, since it gets matched by
9451 "addsi3" pattern, that later gets split to lea in the
9452 case output register differs from input. While this
9453 can be handled by separate addsi pattern for this case
9454 that never results in lea, this seems to be easier and
9455 correct fix for crash to disable this test. */
9457 else if (GET_CODE (disp) != LABEL_REF
9458 && !CONST_INT_P (disp)
9459 && (GET_CODE (disp) != CONST
9460 || !legitimate_constant_p (disp))
9461 && (GET_CODE (disp) != SYMBOL_REF
9462 || !legitimate_constant_p (disp)))
9464 reason = "displacement is not constant";
9467 else if (TARGET_64BIT
9468 && !x86_64_immediate_operand (disp, VOIDmode))
9470 reason = "displacement is out of range";
9475 /* Everything looks valid. */
9482 /* Return a unique alias set for the GOT. */
9484 static alias_set_type
9485 ix86_GOT_alias_set (void)
9487 static alias_set_type set = -1;
9489 set = new_alias_set ();
9493 /* Return a legitimate reference for ORIG (an address) using the
9494 register REG. If REG is 0, a new pseudo is generated.
9496 There are two types of references that must be handled:
9498 1. Global data references must load the address from the GOT, via
9499 the PIC reg. An insn is emitted to do this load, and the reg is
9502 2. Static data references, constant pool addresses, and code labels
9503 compute the address as an offset from the GOT, whose base is in
9504 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9505 differentiate them from global data objects. The returned
9506 address is the PIC reg + an unspec constant.
9508 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
9509 reg also appears in the address. */
9512 legitimize_pic_address (rtx orig, rtx reg)
9519 if (TARGET_MACHO && !TARGET_64BIT)
9522 reg = gen_reg_rtx (Pmode);
9523 /* Use the generic Mach-O PIC machinery. */
9524 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
9528 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
9530 else if (TARGET_64BIT
9531 && ix86_cmodel != CM_SMALL_PIC
9532 && gotoff_operand (addr, Pmode))
9535 /* This symbol may be referenced via a displacement from the PIC
9536 base address (@GOTOFF). */
9538 if (reload_in_progress)
9539 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9540 if (GET_CODE (addr) == CONST)
9541 addr = XEXP (addr, 0);
9542 if (GET_CODE (addr) == PLUS)
9544 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9546 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9549 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9550 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9552 tmpreg = gen_reg_rtx (Pmode);
9555 emit_move_insn (tmpreg, new_rtx);
9559 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
9560 tmpreg, 1, OPTAB_DIRECT);
9563 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
9565 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
9567 /* This symbol may be referenced via a displacement from the PIC
9568 base address (@GOTOFF). */
9570 if (reload_in_progress)
9571 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9572 if (GET_CODE (addr) == CONST)
9573 addr = XEXP (addr, 0);
9574 if (GET_CODE (addr) == PLUS)
9576 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9578 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9581 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9582 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9583 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9587 emit_move_insn (reg, new_rtx);
9591 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
9592 /* We can't use @GOTOFF for text labels on VxWorks;
9593 see gotoff_operand. */
9594 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
9596 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
9598 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
9599 return legitimize_dllimport_symbol (addr, true);
9600 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
9601 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
9602 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
9604 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
9605 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
9609 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
9611 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
9612 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9613 new_rtx = gen_const_mem (Pmode, new_rtx);
9614 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9617 reg = gen_reg_rtx (Pmode);
9618 /* Use directly gen_movsi, otherwise the address is loaded
9619 into register for CSE. We don't want to CSE this addresses,
9620 instead we CSE addresses from the GOT table, so skip this. */
9621 emit_insn (gen_movsi (reg, new_rtx));
9626 /* This symbol must be referenced via a load from the
9627 Global Offset Table (@GOT). */
9629 if (reload_in_progress)
9630 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9631 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
9632 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9634 new_rtx = force_reg (Pmode, new_rtx);
9635 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9636 new_rtx = gen_const_mem (Pmode, new_rtx);
9637 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9640 reg = gen_reg_rtx (Pmode);
9641 emit_move_insn (reg, new_rtx);
9647 if (CONST_INT_P (addr)
9648 && !x86_64_immediate_operand (addr, VOIDmode))
9652 emit_move_insn (reg, addr);
9656 new_rtx = force_reg (Pmode, addr);
9658 else if (GET_CODE (addr) == CONST)
9660 addr = XEXP (addr, 0);
9662 /* We must match stuff we generate before. Assume the only
9663 unspecs that can get here are ours. Not that we could do
9664 anything with them anyway.... */
9665 if (GET_CODE (addr) == UNSPEC
9666 || (GET_CODE (addr) == PLUS
9667 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
9669 gcc_assert (GET_CODE (addr) == PLUS);
9671 if (GET_CODE (addr) == PLUS)
9673 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
9675 /* Check first to see if this is a constant offset from a @GOTOFF
9676 symbol reference. */
9677 if (gotoff_operand (op0, Pmode)
9678 && CONST_INT_P (op1))
9682 if (reload_in_progress)
9683 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9684 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
9686 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
9687 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9688 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9692 emit_move_insn (reg, new_rtx);
9698 if (INTVAL (op1) < -16*1024*1024
9699 || INTVAL (op1) >= 16*1024*1024)
9701 if (!x86_64_immediate_operand (op1, Pmode))
9702 op1 = force_reg (Pmode, op1);
9703 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
9709 base = legitimize_pic_address (XEXP (addr, 0), reg);
9710 new_rtx = legitimize_pic_address (XEXP (addr, 1),
9711 base == reg ? NULL_RTX : reg);
9713 if (CONST_INT_P (new_rtx))
9714 new_rtx = plus_constant (base, INTVAL (new_rtx));
9717 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
9719 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
9720 new_rtx = XEXP (new_rtx, 1);
9722 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
9730 /* Load the thread pointer. If TO_REG is true, force it into a register. */
9733 get_thread_pointer (int to_reg)
9737 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
9741 reg = gen_reg_rtx (Pmode);
9742 insn = gen_rtx_SET (VOIDmode, reg, tp);
9743 insn = emit_insn (insn);
9748 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
9749 false if we expect this to be used for a memory address and true if
9750 we expect to load the address into a register. */
9753 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
9755 rtx dest, base, off, pic, tp;
9760 case TLS_MODEL_GLOBAL_DYNAMIC:
9761 dest = gen_reg_rtx (Pmode);
9762 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
9764 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
9766 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
9769 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
9770 insns = get_insns ();
9773 RTL_CONST_CALL_P (insns) = 1;
9774 emit_libcall_block (insns, dest, rax, x);
9776 else if (TARGET_64BIT && TARGET_GNU2_TLS)
9777 emit_insn (gen_tls_global_dynamic_64 (dest, x));
9779 emit_insn (gen_tls_global_dynamic_32 (dest, x));
9781 if (TARGET_GNU2_TLS)
9783 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
9785 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
9789 case TLS_MODEL_LOCAL_DYNAMIC:
9790 base = gen_reg_rtx (Pmode);
9791 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
9793 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
9795 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
9798 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
9799 insns = get_insns ();
9802 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
9803 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
9804 RTL_CONST_CALL_P (insns) = 1;
9805 emit_libcall_block (insns, base, rax, note);
9807 else if (TARGET_64BIT && TARGET_GNU2_TLS)
9808 emit_insn (gen_tls_local_dynamic_base_64 (base));
9810 emit_insn (gen_tls_local_dynamic_base_32 (base));
9812 if (TARGET_GNU2_TLS)
9814 rtx x = ix86_tls_module_base ();
9816 set_unique_reg_note (get_last_insn (), REG_EQUIV,
9817 gen_rtx_MINUS (Pmode, x, tp));
9820 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
9821 off = gen_rtx_CONST (Pmode, off);
9823 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
9825 if (TARGET_GNU2_TLS)
9827 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
9829 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
9834 case TLS_MODEL_INITIAL_EXEC:
9838 type = UNSPEC_GOTNTPOFF;
9842 if (reload_in_progress)
9843 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9844 pic = pic_offset_table_rtx;
9845 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
9847 else if (!TARGET_ANY_GNU_TLS)
9849 pic = gen_reg_rtx (Pmode);
9850 emit_insn (gen_set_got (pic));
9851 type = UNSPEC_GOTTPOFF;
9856 type = UNSPEC_INDNTPOFF;
9859 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
9860 off = gen_rtx_CONST (Pmode, off);
9862 off = gen_rtx_PLUS (Pmode, pic, off);
9863 off = gen_const_mem (Pmode, off);
9864 set_mem_alias_set (off, ix86_GOT_alias_set ());
9866 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9868 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
9869 off = force_reg (Pmode, off);
9870 return gen_rtx_PLUS (Pmode, base, off);
9874 base = get_thread_pointer (true);
9875 dest = gen_reg_rtx (Pmode);
9876 emit_insn (gen_subsi3 (dest, base, off));
9880 case TLS_MODEL_LOCAL_EXEC:
9881 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
9882 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9883 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
9884 off = gen_rtx_CONST (Pmode, off);
9886 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9888 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
9889 return gen_rtx_PLUS (Pmode, base, off);
9893 base = get_thread_pointer (true);
9894 dest = gen_reg_rtx (Pmode);
9895 emit_insn (gen_subsi3 (dest, base, off));
9906 /* Create or return the unique __imp_DECL dllimport symbol corresponding
9909 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
9910 htab_t dllimport_map;
9913 get_dllimport_decl (tree decl)
9915 struct tree_map *h, in;
9919 size_t namelen, prefixlen;
9925 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
9927 in.hash = htab_hash_pointer (decl);
9928 in.base.from = decl;
9929 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
9930 h = (struct tree_map *) *loc;
9934 *loc = h = GGC_NEW (struct tree_map);
9936 h->base.from = decl;
9937 h->to = to = build_decl (VAR_DECL, NULL, ptr_type_node);
9938 DECL_ARTIFICIAL (to) = 1;
9939 DECL_IGNORED_P (to) = 1;
9940 DECL_EXTERNAL (to) = 1;
9941 TREE_READONLY (to) = 1;
9943 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
9944 name = targetm.strip_name_encoding (name);
9945 prefix = name[0] == FASTCALL_PREFIX || user_label_prefix[0] == 0
9946 ? "*__imp_" : "*__imp__";
9947 namelen = strlen (name);
9948 prefixlen = strlen (prefix);
9949 imp_name = (char *) alloca (namelen + prefixlen + 1);
9950 memcpy (imp_name, prefix, prefixlen);
9951 memcpy (imp_name + prefixlen, name, namelen + 1);
9953 name = ggc_alloc_string (imp_name, namelen + prefixlen);
9954 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
9955 SET_SYMBOL_REF_DECL (rtl, to);
9956 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
9958 rtl = gen_const_mem (Pmode, rtl);
9959 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
9961 SET_DECL_RTL (to, rtl);
9962 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
9967 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
9968 true if we require the result be a register. */
9971 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
9976 gcc_assert (SYMBOL_REF_DECL (symbol));
9977 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
9979 x = DECL_RTL (imp_decl);
9981 x = force_reg (Pmode, x);
9985 /* Try machine-dependent ways of modifying an illegitimate address
9986 to be legitimate. If we find one, return the new, valid address.
9987 This macro is used in only one place: `memory_address' in explow.c.
9989 OLDX is the address as it was before break_out_memory_refs was called.
9990 In some cases it is useful to look at this to decide what needs to be done.
9992 MODE and WIN are passed so that this macro can use
9993 GO_IF_LEGITIMATE_ADDRESS.
9995 It is always safe for this macro to do nothing. It exists to recognize
9996 opportunities to optimize the output.
9998 For the 80386, we handle X+REG by loading X into a register R and
9999 using R+REG. R will go in a general reg and indexing will be used.
10000 However, if REG is a broken-out memory address or multiplication,
10001 nothing needs to be done because REG can certainly go in a general reg.
10003 When -fpic is used, special handling is needed for symbolic references.
10004 See comments by legitimize_pic_address in i386.c for details. */
10007 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
10012 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
10014 return legitimize_tls_address (x, (enum tls_model) log, false);
10015 if (GET_CODE (x) == CONST
10016 && GET_CODE (XEXP (x, 0)) == PLUS
10017 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10018 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
10020 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
10021 (enum tls_model) log, false);
10022 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10025 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
10027 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
10028 return legitimize_dllimport_symbol (x, true);
10029 if (GET_CODE (x) == CONST
10030 && GET_CODE (XEXP (x, 0)) == PLUS
10031 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10032 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
10034 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
10035 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10039 if (flag_pic && SYMBOLIC_CONST (x))
10040 return legitimize_pic_address (x, 0);
10042 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
10043 if (GET_CODE (x) == ASHIFT
10044 && CONST_INT_P (XEXP (x, 1))
10045 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
10048 log = INTVAL (XEXP (x, 1));
10049 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
10050 GEN_INT (1 << log));
10053 if (GET_CODE (x) == PLUS)
10055 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
10057 if (GET_CODE (XEXP (x, 0)) == ASHIFT
10058 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
10059 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
10062 log = INTVAL (XEXP (XEXP (x, 0), 1));
10063 XEXP (x, 0) = gen_rtx_MULT (Pmode,
10064 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
10065 GEN_INT (1 << log));
10068 if (GET_CODE (XEXP (x, 1)) == ASHIFT
10069 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
10070 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
10073 log = INTVAL (XEXP (XEXP (x, 1), 1));
10074 XEXP (x, 1) = gen_rtx_MULT (Pmode,
10075 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
10076 GEN_INT (1 << log));
10079 /* Put multiply first if it isn't already. */
10080 if (GET_CODE (XEXP (x, 1)) == MULT)
10082 rtx tmp = XEXP (x, 0);
10083 XEXP (x, 0) = XEXP (x, 1);
10088 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
10089 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
10090 created by virtual register instantiation, register elimination, and
10091 similar optimizations. */
10092 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
10095 x = gen_rtx_PLUS (Pmode,
10096 gen_rtx_PLUS (Pmode, XEXP (x, 0),
10097 XEXP (XEXP (x, 1), 0)),
10098 XEXP (XEXP (x, 1), 1));
10102 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
10103 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
10104 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
10105 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
10106 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
10107 && CONSTANT_P (XEXP (x, 1)))
10110 rtx other = NULL_RTX;
10112 if (CONST_INT_P (XEXP (x, 1)))
10114 constant = XEXP (x, 1);
10115 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
10117 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
10119 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
10120 other = XEXP (x, 1);
10128 x = gen_rtx_PLUS (Pmode,
10129 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
10130 XEXP (XEXP (XEXP (x, 0), 1), 0)),
10131 plus_constant (other, INTVAL (constant)));
10135 if (changed && legitimate_address_p (mode, x, FALSE))
10138 if (GET_CODE (XEXP (x, 0)) == MULT)
10141 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
10144 if (GET_CODE (XEXP (x, 1)) == MULT)
10147 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
10151 && REG_P (XEXP (x, 1))
10152 && REG_P (XEXP (x, 0)))
10155 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
10158 x = legitimize_pic_address (x, 0);
10161 if (changed && legitimate_address_p (mode, x, FALSE))
10164 if (REG_P (XEXP (x, 0)))
10166 rtx temp = gen_reg_rtx (Pmode);
10167 rtx val = force_operand (XEXP (x, 1), temp);
10169 emit_move_insn (temp, val);
10171 XEXP (x, 1) = temp;
10175 else if (REG_P (XEXP (x, 1)))
10177 rtx temp = gen_reg_rtx (Pmode);
10178 rtx val = force_operand (XEXP (x, 0), temp);
10180 emit_move_insn (temp, val);
10182 XEXP (x, 0) = temp;
10190 /* Print an integer constant expression in assembler syntax. Addition
10191 and subtraction are the only arithmetic that may appear in these
10192 expressions. FILE is the stdio stream to write to, X is the rtx, and
10193 CODE is the operand print code from the output string. */
10196 output_pic_addr_const (FILE *file, rtx x, int code)
10200 switch (GET_CODE (x))
10203 gcc_assert (flag_pic);
10208 if (! TARGET_MACHO || TARGET_64BIT)
10209 output_addr_const (file, x);
10212 const char *name = XSTR (x, 0);
10214 /* Mark the decl as referenced so that cgraph will
10215 output the function. */
10216 if (SYMBOL_REF_DECL (x))
10217 mark_decl_referenced (SYMBOL_REF_DECL (x));
10220 if (MACHOPIC_INDIRECT
10221 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10222 name = machopic_indirection_name (x, /*stub_p=*/true);
10224 assemble_name (file, name);
10226 if (!TARGET_MACHO && !(TARGET_64BIT && DEFAULT_ABI == MS_ABI)
10227 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
10228 fputs ("@PLT", file);
10235 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
10236 assemble_name (asm_out_file, buf);
10240 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
10244 /* This used to output parentheses around the expression,
10245 but that does not work on the 386 (either ATT or BSD assembler). */
10246 output_pic_addr_const (file, XEXP (x, 0), code);
10250 if (GET_MODE (x) == VOIDmode)
10252 /* We can use %d if the number is <32 bits and positive. */
10253 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
10254 fprintf (file, "0x%lx%08lx",
10255 (unsigned long) CONST_DOUBLE_HIGH (x),
10256 (unsigned long) CONST_DOUBLE_LOW (x));
10258 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
10261 /* We can't handle floating point constants;
10262 PRINT_OPERAND must handle them. */
10263 output_operand_lossage ("floating constant misused");
10267 /* Some assemblers need integer constants to appear first. */
10268 if (CONST_INT_P (XEXP (x, 0)))
10270 output_pic_addr_const (file, XEXP (x, 0), code);
10272 output_pic_addr_const (file, XEXP (x, 1), code);
10276 gcc_assert (CONST_INT_P (XEXP (x, 1)));
10277 output_pic_addr_const (file, XEXP (x, 1), code);
10279 output_pic_addr_const (file, XEXP (x, 0), code);
10285 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
10286 output_pic_addr_const (file, XEXP (x, 0), code);
10288 output_pic_addr_const (file, XEXP (x, 1), code);
10290 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
10294 gcc_assert (XVECLEN (x, 0) == 1);
10295 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
10296 switch (XINT (x, 1))
10299 fputs ("@GOT", file);
10301 case UNSPEC_GOTOFF:
10302 fputs ("@GOTOFF", file);
10304 case UNSPEC_PLTOFF:
10305 fputs ("@PLTOFF", file);
10307 case UNSPEC_GOTPCREL:
10308 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10309 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
10311 case UNSPEC_GOTTPOFF:
10312 /* FIXME: This might be @TPOFF in Sun ld too. */
10313 fputs ("@GOTTPOFF", file);
10316 fputs ("@TPOFF", file);
10318 case UNSPEC_NTPOFF:
10320 fputs ("@TPOFF", file);
10322 fputs ("@NTPOFF", file);
10324 case UNSPEC_DTPOFF:
10325 fputs ("@DTPOFF", file);
10327 case UNSPEC_GOTNTPOFF:
10329 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10330 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
10332 fputs ("@GOTNTPOFF", file);
10334 case UNSPEC_INDNTPOFF:
10335 fputs ("@INDNTPOFF", file);
10338 case UNSPEC_MACHOPIC_OFFSET:
10340 machopic_output_function_base_name (file);
10344 output_operand_lossage ("invalid UNSPEC as operand");
10350 output_operand_lossage ("invalid expression as operand");
10354 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10355 We need to emit DTP-relative relocations. */
10357 static void ATTRIBUTE_UNUSED
10358 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
10360 fputs (ASM_LONG, file);
10361 output_addr_const (file, x);
10362 fputs ("@DTPOFF", file);
10368 fputs (", 0", file);
10371 gcc_unreachable ();
10375 /* Return true if X is a representation of the PIC register. This copes
10376 with calls from ix86_find_base_term, where the register might have
10377 been replaced by a cselib value. */
10380 ix86_pic_register_p (rtx x)
10382 if (GET_CODE (x) == VALUE)
10383 return (pic_offset_table_rtx
10384 && rtx_equal_for_cselib_p (x, pic_offset_table_rtx));
10386 return REG_P (x) && REGNO (x) == PIC_OFFSET_TABLE_REGNUM;
10389 /* In the name of slightly smaller debug output, and to cater to
10390 general assembler lossage, recognize PIC+GOTOFF and turn it back
10391 into a direct symbol reference.
10393 On Darwin, this is necessary to avoid a crash, because Darwin
10394 has a different PIC label for each routine but the DWARF debugging
10395 information is not associated with any particular routine, so it's
10396 necessary to remove references to the PIC label from RTL stored by
10397 the DWARF output code. */
10400 ix86_delegitimize_address (rtx orig_x)
10403 /* reg_addend is NULL or a multiple of some register. */
10404 rtx reg_addend = NULL_RTX;
10405 /* const_addend is NULL or a const_int. */
10406 rtx const_addend = NULL_RTX;
10407 /* This is the result, or NULL. */
10408 rtx result = NULL_RTX;
10415 if (GET_CODE (x) != CONST
10416 || GET_CODE (XEXP (x, 0)) != UNSPEC
10417 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
10418 || !MEM_P (orig_x))
10420 return XVECEXP (XEXP (x, 0), 0, 0);
10423 if (GET_CODE (x) != PLUS
10424 || GET_CODE (XEXP (x, 1)) != CONST)
10427 if (ix86_pic_register_p (XEXP (x, 0)))
10428 /* %ebx + GOT/GOTOFF */
10430 else if (GET_CODE (XEXP (x, 0)) == PLUS)
10432 /* %ebx + %reg * scale + GOT/GOTOFF */
10433 reg_addend = XEXP (x, 0);
10434 if (ix86_pic_register_p (XEXP (reg_addend, 0)))
10435 reg_addend = XEXP (reg_addend, 1);
10436 else if (ix86_pic_register_p (XEXP (reg_addend, 1)))
10437 reg_addend = XEXP (reg_addend, 0);
10440 if (!REG_P (reg_addend)
10441 && GET_CODE (reg_addend) != MULT
10442 && GET_CODE (reg_addend) != ASHIFT)
10448 x = XEXP (XEXP (x, 1), 0);
10449 if (GET_CODE (x) == PLUS
10450 && CONST_INT_P (XEXP (x, 1)))
10452 const_addend = XEXP (x, 1);
10456 if (GET_CODE (x) == UNSPEC
10457 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
10458 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
10459 result = XVECEXP (x, 0, 0);
10461 if (TARGET_MACHO && darwin_local_data_pic (x)
10462 && !MEM_P (orig_x))
10463 result = XVECEXP (x, 0, 0);
10469 result = gen_rtx_CONST (Pmode, gen_rtx_PLUS (Pmode, result, const_addend));
10471 result = gen_rtx_PLUS (Pmode, reg_addend, result);
10475 /* If X is a machine specific address (i.e. a symbol or label being
10476 referenced as a displacement from the GOT implemented using an
10477 UNSPEC), then return the base term. Otherwise return X. */
10480 ix86_find_base_term (rtx x)
10486 if (GET_CODE (x) != CONST)
10488 term = XEXP (x, 0);
10489 if (GET_CODE (term) == PLUS
10490 && (CONST_INT_P (XEXP (term, 1))
10491 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
10492 term = XEXP (term, 0);
10493 if (GET_CODE (term) != UNSPEC
10494 || XINT (term, 1) != UNSPEC_GOTPCREL)
10497 return XVECEXP (term, 0, 0);
10500 return ix86_delegitimize_address (x);
10504 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
10505 int fp, FILE *file)
10507 const char *suffix;
10509 if (mode == CCFPmode || mode == CCFPUmode)
10511 enum rtx_code second_code, bypass_code;
10512 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
10513 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
10514 code = ix86_fp_compare_code_to_integer (code);
10518 code = reverse_condition (code);
10569 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
10573 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
10574 Those same assemblers have the same but opposite lossage on cmov. */
10575 if (mode == CCmode)
10576 suffix = fp ? "nbe" : "a";
10577 else if (mode == CCCmode)
10580 gcc_unreachable ();
10596 gcc_unreachable ();
10600 gcc_assert (mode == CCmode || mode == CCCmode);
10617 gcc_unreachable ();
10621 /* ??? As above. */
10622 gcc_assert (mode == CCmode || mode == CCCmode);
10623 suffix = fp ? "nb" : "ae";
10626 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
10630 /* ??? As above. */
10631 if (mode == CCmode)
10633 else if (mode == CCCmode)
10634 suffix = fp ? "nb" : "ae";
10636 gcc_unreachable ();
10639 suffix = fp ? "u" : "p";
10642 suffix = fp ? "nu" : "np";
10645 gcc_unreachable ();
10647 fputs (suffix, file);
10650 /* Print the name of register X to FILE based on its machine mode and number.
10651 If CODE is 'w', pretend the mode is HImode.
10652 If CODE is 'b', pretend the mode is QImode.
10653 If CODE is 'k', pretend the mode is SImode.
10654 If CODE is 'q', pretend the mode is DImode.
10655 If CODE is 'x', pretend the mode is V4SFmode.
10656 If CODE is 't', pretend the mode is V8SFmode.
10657 If CODE is 'h', pretend the reg is the 'high' byte register.
10658 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
10659 If CODE is 'd', duplicate the operand for AVX instruction.
10663 print_reg (rtx x, int code, FILE *file)
10666 bool duplicated = code == 'd' && TARGET_AVX;
10668 gcc_assert (x == pc_rtx
10669 || (REGNO (x) != ARG_POINTER_REGNUM
10670 && REGNO (x) != FRAME_POINTER_REGNUM
10671 && REGNO (x) != FLAGS_REG
10672 && REGNO (x) != FPSR_REG
10673 && REGNO (x) != FPCR_REG));
10675 if (ASSEMBLER_DIALECT == ASM_ATT)
10680 gcc_assert (TARGET_64BIT);
10681 fputs ("rip", file);
10685 if (code == 'w' || MMX_REG_P (x))
10687 else if (code == 'b')
10689 else if (code == 'k')
10691 else if (code == 'q')
10693 else if (code == 'y')
10695 else if (code == 'h')
10697 else if (code == 'x')
10699 else if (code == 't')
10702 code = GET_MODE_SIZE (GET_MODE (x));
10704 /* Irritatingly, AMD extended registers use different naming convention
10705 from the normal registers. */
10706 if (REX_INT_REG_P (x))
10708 gcc_assert (TARGET_64BIT);
10712 error ("extended registers have no high halves");
10715 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
10718 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
10721 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
10724 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
10727 error ("unsupported operand size for extended register");
10737 if (STACK_TOP_P (x))
10746 if (! ANY_FP_REG_P (x))
10747 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
10752 reg = hi_reg_name[REGNO (x)];
10755 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
10757 reg = qi_reg_name[REGNO (x)];
10760 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
10762 reg = qi_high_reg_name[REGNO (x)];
10767 gcc_assert (!duplicated);
10769 fputs (hi_reg_name[REGNO (x)] + 1, file);
10774 gcc_unreachable ();
10780 if (ASSEMBLER_DIALECT == ASM_ATT)
10781 fprintf (file, ", %%%s", reg);
10783 fprintf (file, ", %s", reg);
10787 /* Locate some local-dynamic symbol still in use by this function
10788 so that we can print its name in some tls_local_dynamic_base
10792 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10796 if (GET_CODE (x) == SYMBOL_REF
10797 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10799 cfun->machine->some_ld_name = XSTR (x, 0);
10806 static const char *
10807 get_some_local_dynamic_name (void)
10811 if (cfun->machine->some_ld_name)
10812 return cfun->machine->some_ld_name;
10814 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10816 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
10817 return cfun->machine->some_ld_name;
10819 gcc_unreachable ();
10822 /* Meaning of CODE:
10823 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
10824 C -- print opcode suffix for set/cmov insn.
10825 c -- like C, but print reversed condition
10826 E,e -- likewise, but for compare-and-branch fused insn.
10827 F,f -- likewise, but for floating-point.
10828 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
10830 R -- print the prefix for register names.
10831 z -- print the opcode suffix for the size of the current operand.
10832 * -- print a star (in certain assembler syntax)
10833 A -- print an absolute memory reference.
10834 w -- print the operand as if it's a "word" (HImode) even if it isn't.
10835 s -- print a shift double count, followed by the assemblers argument
10837 b -- print the QImode name of the register for the indicated operand.
10838 %b0 would print %al if operands[0] is reg 0.
10839 w -- likewise, print the HImode name of the register.
10840 k -- likewise, print the SImode name of the register.
10841 q -- likewise, print the DImode name of the register.
10842 x -- likewise, print the V4SFmode name of the register.
10843 t -- likewise, print the V8SFmode name of the register.
10844 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
10845 y -- print "st(0)" instead of "st" as a register.
10846 d -- print duplicated register operand for AVX instruction.
10847 D -- print condition for SSE cmp instruction.
10848 P -- if PIC, print an @PLT suffix.
10849 X -- don't print any sort of PIC '@' suffix for a symbol.
10850 & -- print some in-use local-dynamic symbol name.
10851 H -- print a memory address offset by 8; used for sse high-parts
10852 Y -- print condition for SSE5 com* instruction.
10853 + -- print a branch hint as 'cs' or 'ds' prefix
10854 ; -- print a semicolon (after prefixes due to bug in older gas).
10858 print_operand (FILE *file, rtx x, int code)
10865 if (ASSEMBLER_DIALECT == ASM_ATT)
10870 assemble_name (file, get_some_local_dynamic_name ());
10874 switch (ASSEMBLER_DIALECT)
10881 /* Intel syntax. For absolute addresses, registers should not
10882 be surrounded by braces. */
10886 PRINT_OPERAND (file, x, 0);
10893 gcc_unreachable ();
10896 PRINT_OPERAND (file, x, 0);
10901 if (ASSEMBLER_DIALECT == ASM_ATT)
10906 if (ASSEMBLER_DIALECT == ASM_ATT)
10911 if (ASSEMBLER_DIALECT == ASM_ATT)
10916 if (ASSEMBLER_DIALECT == ASM_ATT)
10921 if (ASSEMBLER_DIALECT == ASM_ATT)
10926 if (ASSEMBLER_DIALECT == ASM_ATT)
10931 /* 387 opcodes don't get size suffixes if the operands are
10933 if (STACK_REG_P (x))
10936 /* Likewise if using Intel opcodes. */
10937 if (ASSEMBLER_DIALECT == ASM_INTEL)
10940 /* This is the size of op from size of operand. */
10941 switch (GET_MODE_SIZE (GET_MODE (x)))
10950 #ifdef HAVE_GAS_FILDS_FISTS
10960 if (GET_MODE (x) == SFmode)
10975 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
10979 #ifdef GAS_MNEMONICS
10994 gcc_unreachable ();
11011 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
11013 PRINT_OPERAND (file, x, 0);
11014 fputs (", ", file);
11019 /* Little bit of braindamage here. The SSE compare instructions
11020 does use completely different names for the comparisons that the
11021 fp conditional moves. */
11024 switch (GET_CODE (x))
11027 fputs ("eq", file);
11030 fputs ("eq_us", file);
11033 fputs ("lt", file);
11036 fputs ("nge", file);
11039 fputs ("le", file);
11042 fputs ("ngt", file);
11045 fputs ("unord", file);
11048 fputs ("neq", file);
11051 fputs ("neq_oq", file);
11054 fputs ("ge", file);
11057 fputs ("nlt", file);
11060 fputs ("gt", file);
11063 fputs ("nle", file);
11066 fputs ("ord", file);
11069 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11075 switch (GET_CODE (x))
11079 fputs ("eq", file);
11083 fputs ("lt", file);
11087 fputs ("le", file);
11090 fputs ("unord", file);
11094 fputs ("neq", file);
11098 fputs ("nlt", file);
11102 fputs ("nle", file);
11105 fputs ("ord", file);
11108 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11114 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11115 if (ASSEMBLER_DIALECT == ASM_ATT)
11117 switch (GET_MODE (x))
11119 case HImode: putc ('w', file); break;
11121 case SFmode: putc ('l', file); break;
11123 case DFmode: putc ('q', file); break;
11124 default: gcc_unreachable ();
11131 if (!COMPARISON_P (x))
11133 output_operand_lossage ("operand is neither a constant nor a "
11134 "condition code, invalid operand code "
11138 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
11141 if (!COMPARISON_P (x))
11143 output_operand_lossage ("operand is neither a constant nor a "
11144 "condition code, invalid operand code "
11148 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11149 if (ASSEMBLER_DIALECT == ASM_ATT)
11152 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
11155 /* Like above, but reverse condition */
11157 /* Check to see if argument to %c is really a constant
11158 and not a condition code which needs to be reversed. */
11159 if (!COMPARISON_P (x))
11161 output_operand_lossage ("operand is neither a constant nor a "
11162 "condition code, invalid operand "
11166 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
11169 if (!COMPARISON_P (x))
11171 output_operand_lossage ("operand is neither a constant nor a "
11172 "condition code, invalid operand "
11176 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11177 if (ASSEMBLER_DIALECT == ASM_ATT)
11180 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
11184 put_condition_code (GET_CODE (x), CCmode, 0, 0, file);
11188 put_condition_code (GET_CODE (x), CCmode, 1, 0, file);
11192 /* It doesn't actually matter what mode we use here, as we're
11193 only going to use this for printing. */
11194 x = adjust_address_nv (x, DImode, 8);
11202 || optimize_function_for_size_p (cfun) || !TARGET_BRANCH_PREDICTION_HINTS)
11205 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
11208 int pred_val = INTVAL (XEXP (x, 0));
11210 if (pred_val < REG_BR_PROB_BASE * 45 / 100
11211 || pred_val > REG_BR_PROB_BASE * 55 / 100)
11213 int taken = pred_val > REG_BR_PROB_BASE / 2;
11214 int cputaken = final_forward_branch_p (current_output_insn) == 0;
11216 /* Emit hints only in the case default branch prediction
11217 heuristics would fail. */
11218 if (taken != cputaken)
11220 /* We use 3e (DS) prefix for taken branches and
11221 2e (CS) prefix for not taken branches. */
11223 fputs ("ds ; ", file);
11225 fputs ("cs ; ", file);
11233 switch (GET_CODE (x))
11236 fputs ("neq", file);
11239 fputs ("eq", file);
11243 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
11247 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
11251 fputs ("le", file);
11255 fputs ("lt", file);
11258 fputs ("unord", file);
11261 fputs ("ord", file);
11264 fputs ("ueq", file);
11267 fputs ("nlt", file);
11270 fputs ("nle", file);
11273 fputs ("ule", file);
11276 fputs ("ult", file);
11279 fputs ("une", file);
11282 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11289 fputs (" ; ", file);
11296 output_operand_lossage ("invalid operand code '%c'", code);
11301 print_reg (x, code, file);
11303 else if (MEM_P (x))
11305 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
11306 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
11307 && GET_MODE (x) != BLKmode)
11310 switch (GET_MODE_SIZE (GET_MODE (x)))
11312 case 1: size = "BYTE"; break;
11313 case 2: size = "WORD"; break;
11314 case 4: size = "DWORD"; break;
11315 case 8: size = "QWORD"; break;
11316 case 12: size = "XWORD"; break;
11318 if (GET_MODE (x) == XFmode)
11324 gcc_unreachable ();
11327 /* Check for explicit size override (codes 'b', 'w' and 'k') */
11330 else if (code == 'w')
11332 else if (code == 'k')
11335 fputs (size, file);
11336 fputs (" PTR ", file);
11340 /* Avoid (%rip) for call operands. */
11341 if (CONSTANT_ADDRESS_P (x) && code == 'P'
11342 && !CONST_INT_P (x))
11343 output_addr_const (file, x);
11344 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
11345 output_operand_lossage ("invalid constraints for operand");
11347 output_address (x);
11350 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
11355 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11356 REAL_VALUE_TO_TARGET_SINGLE (r, l);
11358 if (ASSEMBLER_DIALECT == ASM_ATT)
11360 fprintf (file, "0x%08lx", (long unsigned int) l);
11363 /* These float cases don't actually occur as immediate operands. */
11364 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
11368 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11369 fprintf (file, "%s", dstr);
11372 else if (GET_CODE (x) == CONST_DOUBLE
11373 && GET_MODE (x) == XFmode)
11377 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11378 fprintf (file, "%s", dstr);
11383 /* We have patterns that allow zero sets of memory, for instance.
11384 In 64-bit mode, we should probably support all 8-byte vectors,
11385 since we can in fact encode that into an immediate. */
11386 if (GET_CODE (x) == CONST_VECTOR)
11388 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
11394 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
11396 if (ASSEMBLER_DIALECT == ASM_ATT)
11399 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
11400 || GET_CODE (x) == LABEL_REF)
11402 if (ASSEMBLER_DIALECT == ASM_ATT)
11405 fputs ("OFFSET FLAT:", file);
11408 if (CONST_INT_P (x))
11409 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
11411 output_pic_addr_const (file, x, code);
11413 output_addr_const (file, x);
11417 /* Print a memory operand whose address is ADDR. */
11420 print_operand_address (FILE *file, rtx addr)
11422 struct ix86_address parts;
11423 rtx base, index, disp;
11425 int ok = ix86_decompose_address (addr, &parts);
11430 index = parts.index;
11432 scale = parts.scale;
11440 if (ASSEMBLER_DIALECT == ASM_ATT)
11442 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
11445 gcc_unreachable ();
11448 /* Use one byte shorter RIP relative addressing for 64bit mode. */
11449 if (TARGET_64BIT && !base && !index)
11453 if (GET_CODE (disp) == CONST
11454 && GET_CODE (XEXP (disp, 0)) == PLUS
11455 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11456 symbol = XEXP (XEXP (disp, 0), 0);
11458 if (GET_CODE (symbol) == LABEL_REF
11459 || (GET_CODE (symbol) == SYMBOL_REF
11460 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
11463 if (!base && !index)
11465 /* Displacement only requires special attention. */
11467 if (CONST_INT_P (disp))
11469 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
11470 fputs ("ds:", file);
11471 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
11474 output_pic_addr_const (file, disp, 0);
11476 output_addr_const (file, disp);
11480 if (ASSEMBLER_DIALECT == ASM_ATT)
11485 output_pic_addr_const (file, disp, 0);
11486 else if (GET_CODE (disp) == LABEL_REF)
11487 output_asm_label (disp);
11489 output_addr_const (file, disp);
11494 print_reg (base, 0, file);
11498 print_reg (index, 0, file);
11500 fprintf (file, ",%d", scale);
11506 rtx offset = NULL_RTX;
11510 /* Pull out the offset of a symbol; print any symbol itself. */
11511 if (GET_CODE (disp) == CONST
11512 && GET_CODE (XEXP (disp, 0)) == PLUS
11513 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11515 offset = XEXP (XEXP (disp, 0), 1);
11516 disp = gen_rtx_CONST (VOIDmode,
11517 XEXP (XEXP (disp, 0), 0));
11521 output_pic_addr_const (file, disp, 0);
11522 else if (GET_CODE (disp) == LABEL_REF)
11523 output_asm_label (disp);
11524 else if (CONST_INT_P (disp))
11527 output_addr_const (file, disp);
11533 print_reg (base, 0, file);
11536 if (INTVAL (offset) >= 0)
11538 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11542 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11549 print_reg (index, 0, file);
11551 fprintf (file, "*%d", scale);
11559 output_addr_const_extra (FILE *file, rtx x)
11563 if (GET_CODE (x) != UNSPEC)
11566 op = XVECEXP (x, 0, 0);
11567 switch (XINT (x, 1))
11569 case UNSPEC_GOTTPOFF:
11570 output_addr_const (file, op);
11571 /* FIXME: This might be @TPOFF in Sun ld. */
11572 fputs ("@GOTTPOFF", file);
11575 output_addr_const (file, op);
11576 fputs ("@TPOFF", file);
11578 case UNSPEC_NTPOFF:
11579 output_addr_const (file, op);
11581 fputs ("@TPOFF", file);
11583 fputs ("@NTPOFF", file);
11585 case UNSPEC_DTPOFF:
11586 output_addr_const (file, op);
11587 fputs ("@DTPOFF", file);
11589 case UNSPEC_GOTNTPOFF:
11590 output_addr_const (file, op);
11592 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
11593 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
11595 fputs ("@GOTNTPOFF", file);
11597 case UNSPEC_INDNTPOFF:
11598 output_addr_const (file, op);
11599 fputs ("@INDNTPOFF", file);
11602 case UNSPEC_MACHOPIC_OFFSET:
11603 output_addr_const (file, op);
11605 machopic_output_function_base_name (file);
11616 /* Split one or more DImode RTL references into pairs of SImode
11617 references. The RTL can be REG, offsettable MEM, integer constant, or
11618 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11619 split and "num" is its length. lo_half and hi_half are output arrays
11620 that parallel "operands". */
11623 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11627 rtx op = operands[num];
11629 /* simplify_subreg refuse to split volatile memory addresses,
11630 but we still have to handle it. */
11633 lo_half[num] = adjust_address (op, SImode, 0);
11634 hi_half[num] = adjust_address (op, SImode, 4);
11638 lo_half[num] = simplify_gen_subreg (SImode, op,
11639 GET_MODE (op) == VOIDmode
11640 ? DImode : GET_MODE (op), 0);
11641 hi_half[num] = simplify_gen_subreg (SImode, op,
11642 GET_MODE (op) == VOIDmode
11643 ? DImode : GET_MODE (op), 4);
11647 /* Split one or more TImode RTL references into pairs of DImode
11648 references. The RTL can be REG, offsettable MEM, integer constant, or
11649 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11650 split and "num" is its length. lo_half and hi_half are output arrays
11651 that parallel "operands". */
11654 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11658 rtx op = operands[num];
11660 /* simplify_subreg refuse to split volatile memory addresses, but we
11661 still have to handle it. */
11664 lo_half[num] = adjust_address (op, DImode, 0);
11665 hi_half[num] = adjust_address (op, DImode, 8);
11669 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
11670 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
11675 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
11676 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
11677 is the expression of the binary operation. The output may either be
11678 emitted here, or returned to the caller, like all output_* functions.
11680 There is no guarantee that the operands are the same mode, as they
11681 might be within FLOAT or FLOAT_EXTEND expressions. */
11683 #ifndef SYSV386_COMPAT
11684 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
11685 wants to fix the assemblers because that causes incompatibility
11686 with gcc. No-one wants to fix gcc because that causes
11687 incompatibility with assemblers... You can use the option of
11688 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
11689 #define SYSV386_COMPAT 1
11693 output_387_binary_op (rtx insn, rtx *operands)
11695 static char buf[40];
11698 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
11700 #ifdef ENABLE_CHECKING
11701 /* Even if we do not want to check the inputs, this documents input
11702 constraints. Which helps in understanding the following code. */
11703 if (STACK_REG_P (operands[0])
11704 && ((REG_P (operands[1])
11705 && REGNO (operands[0]) == REGNO (operands[1])
11706 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
11707 || (REG_P (operands[2])
11708 && REGNO (operands[0]) == REGNO (operands[2])
11709 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
11710 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
11713 gcc_assert (is_sse);
11716 switch (GET_CODE (operands[3]))
11719 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11720 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11728 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11729 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11737 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11738 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11746 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11747 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11755 gcc_unreachable ();
11762 strcpy (buf, ssep);
11763 if (GET_MODE (operands[0]) == SFmode)
11764 strcat (buf, "ss\t{%2, %1, %0|%0, %1, %2}");
11766 strcat (buf, "sd\t{%2, %1, %0|%0, %1, %2}");
11770 strcpy (buf, ssep + 1);
11771 if (GET_MODE (operands[0]) == SFmode)
11772 strcat (buf, "ss\t{%2, %0|%0, %2}");
11774 strcat (buf, "sd\t{%2, %0|%0, %2}");
11780 switch (GET_CODE (operands[3]))
11784 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
11786 rtx temp = operands[2];
11787 operands[2] = operands[1];
11788 operands[1] = temp;
11791 /* know operands[0] == operands[1]. */
11793 if (MEM_P (operands[2]))
11799 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
11801 if (STACK_TOP_P (operands[0]))
11802 /* How is it that we are storing to a dead operand[2]?
11803 Well, presumably operands[1] is dead too. We can't
11804 store the result to st(0) as st(0) gets popped on this
11805 instruction. Instead store to operands[2] (which I
11806 think has to be st(1)). st(1) will be popped later.
11807 gcc <= 2.8.1 didn't have this check and generated
11808 assembly code that the Unixware assembler rejected. */
11809 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
11811 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
11815 if (STACK_TOP_P (operands[0]))
11816 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
11818 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
11823 if (MEM_P (operands[1]))
11829 if (MEM_P (operands[2]))
11835 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
11838 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
11839 derived assemblers, confusingly reverse the direction of
11840 the operation for fsub{r} and fdiv{r} when the
11841 destination register is not st(0). The Intel assembler
11842 doesn't have this brain damage. Read !SYSV386_COMPAT to
11843 figure out what the hardware really does. */
11844 if (STACK_TOP_P (operands[0]))
11845 p = "{p\t%0, %2|rp\t%2, %0}";
11847 p = "{rp\t%2, %0|p\t%0, %2}";
11849 if (STACK_TOP_P (operands[0]))
11850 /* As above for fmul/fadd, we can't store to st(0). */
11851 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
11853 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
11858 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
11861 if (STACK_TOP_P (operands[0]))
11862 p = "{rp\t%0, %1|p\t%1, %0}";
11864 p = "{p\t%1, %0|rp\t%0, %1}";
11866 if (STACK_TOP_P (operands[0]))
11867 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
11869 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
11874 if (STACK_TOP_P (operands[0]))
11876 if (STACK_TOP_P (operands[1]))
11877 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
11879 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
11882 else if (STACK_TOP_P (operands[1]))
11885 p = "{\t%1, %0|r\t%0, %1}";
11887 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
11893 p = "{r\t%2, %0|\t%0, %2}";
11895 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
11901 gcc_unreachable ();
11908 /* Return needed mode for entity in optimize_mode_switching pass. */
11911 ix86_mode_needed (int entity, rtx insn)
11913 enum attr_i387_cw mode;
11915 /* The mode UNINITIALIZED is used to store control word after a
11916 function call or ASM pattern. The mode ANY specify that function
11917 has no requirements on the control word and make no changes in the
11918 bits we are interested in. */
11921 || (NONJUMP_INSN_P (insn)
11922 && (asm_noperands (PATTERN (insn)) >= 0
11923 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
11924 return I387_CW_UNINITIALIZED;
11926 if (recog_memoized (insn) < 0)
11927 return I387_CW_ANY;
11929 mode = get_attr_i387_cw (insn);
11934 if (mode == I387_CW_TRUNC)
11939 if (mode == I387_CW_FLOOR)
11944 if (mode == I387_CW_CEIL)
11949 if (mode == I387_CW_MASK_PM)
11954 gcc_unreachable ();
11957 return I387_CW_ANY;
11960 /* Output code to initialize control word copies used by trunc?f?i and
11961 rounding patterns. CURRENT_MODE is set to current control word,
11962 while NEW_MODE is set to new control word. */
11965 emit_i387_cw_initialization (int mode)
11967 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
11970 enum ix86_stack_slot slot;
11972 rtx reg = gen_reg_rtx (HImode);
11974 emit_insn (gen_x86_fnstcw_1 (stored_mode));
11975 emit_move_insn (reg, copy_rtx (stored_mode));
11977 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL
11978 || optimize_function_for_size_p (cfun))
11982 case I387_CW_TRUNC:
11983 /* round toward zero (truncate) */
11984 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
11985 slot = SLOT_CW_TRUNC;
11988 case I387_CW_FLOOR:
11989 /* round down toward -oo */
11990 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
11991 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
11992 slot = SLOT_CW_FLOOR;
11996 /* round up toward +oo */
11997 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
11998 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
11999 slot = SLOT_CW_CEIL;
12002 case I387_CW_MASK_PM:
12003 /* mask precision exception for nearbyint() */
12004 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12005 slot = SLOT_CW_MASK_PM;
12009 gcc_unreachable ();
12016 case I387_CW_TRUNC:
12017 /* round toward zero (truncate) */
12018 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
12019 slot = SLOT_CW_TRUNC;
12022 case I387_CW_FLOOR:
12023 /* round down toward -oo */
12024 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
12025 slot = SLOT_CW_FLOOR;
12029 /* round up toward +oo */
12030 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
12031 slot = SLOT_CW_CEIL;
12034 case I387_CW_MASK_PM:
12035 /* mask precision exception for nearbyint() */
12036 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12037 slot = SLOT_CW_MASK_PM;
12041 gcc_unreachable ();
12045 gcc_assert (slot < MAX_386_STACK_LOCALS);
12047 new_mode = assign_386_stack_local (HImode, slot);
12048 emit_move_insn (new_mode, reg);
12051 /* Output code for INSN to convert a float to a signed int. OPERANDS
12052 are the insn operands. The output may be [HSD]Imode and the input
12053 operand may be [SDX]Fmode. */
12056 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
12058 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12059 int dimode_p = GET_MODE (operands[0]) == DImode;
12060 int round_mode = get_attr_i387_cw (insn);
12062 /* Jump through a hoop or two for DImode, since the hardware has no
12063 non-popping instruction. We used to do this a different way, but
12064 that was somewhat fragile and broke with post-reload splitters. */
12065 if ((dimode_p || fisttp) && !stack_top_dies)
12066 output_asm_insn ("fld\t%y1", operands);
12068 gcc_assert (STACK_TOP_P (operands[1]));
12069 gcc_assert (MEM_P (operands[0]));
12070 gcc_assert (GET_MODE (operands[1]) != TFmode);
12073 output_asm_insn ("fisttp%z0\t%0", operands);
12076 if (round_mode != I387_CW_ANY)
12077 output_asm_insn ("fldcw\t%3", operands);
12078 if (stack_top_dies || dimode_p)
12079 output_asm_insn ("fistp%z0\t%0", operands);
12081 output_asm_insn ("fist%z0\t%0", operands);
12082 if (round_mode != I387_CW_ANY)
12083 output_asm_insn ("fldcw\t%2", operands);
12089 /* Output code for x87 ffreep insn. The OPNO argument, which may only
12090 have the values zero or one, indicates the ffreep insn's operand
12091 from the OPERANDS array. */
12093 static const char *
12094 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
12096 if (TARGET_USE_FFREEP)
12097 #ifdef HAVE_AS_IX86_FFREEP
12098 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
12101 static char retval[32];
12102 int regno = REGNO (operands[opno]);
12104 gcc_assert (FP_REGNO_P (regno));
12106 regno -= FIRST_STACK_REG;
12108 snprintf (retval, sizeof (retval), ASM_SHORT "0xc%ddf", regno);
12113 return opno ? "fstp\t%y1" : "fstp\t%y0";
12117 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
12118 should be used. UNORDERED_P is true when fucom should be used. */
12121 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
12123 int stack_top_dies;
12124 rtx cmp_op0, cmp_op1;
12125 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
12129 cmp_op0 = operands[0];
12130 cmp_op1 = operands[1];
12134 cmp_op0 = operands[1];
12135 cmp_op1 = operands[2];
12140 static const char ucomiss[] = "vucomiss\t{%1, %0|%0, %1}";
12141 static const char ucomisd[] = "vucomisd\t{%1, %0|%0, %1}";
12142 static const char comiss[] = "vcomiss\t{%1, %0|%0, %1}";
12143 static const char comisd[] = "vcomisd\t{%1, %0|%0, %1}";
12145 if (GET_MODE (operands[0]) == SFmode)
12147 return &ucomiss[TARGET_AVX ? 0 : 1];
12149 return &comiss[TARGET_AVX ? 0 : 1];
12152 return &ucomisd[TARGET_AVX ? 0 : 1];
12154 return &comisd[TARGET_AVX ? 0 : 1];
12157 gcc_assert (STACK_TOP_P (cmp_op0));
12159 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12161 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
12163 if (stack_top_dies)
12165 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
12166 return output_387_ffreep (operands, 1);
12169 return "ftst\n\tfnstsw\t%0";
12172 if (STACK_REG_P (cmp_op1)
12174 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
12175 && REGNO (cmp_op1) != FIRST_STACK_REG)
12177 /* If both the top of the 387 stack dies, and the other operand
12178 is also a stack register that dies, then this must be a
12179 `fcompp' float compare */
12183 /* There is no double popping fcomi variant. Fortunately,
12184 eflags is immune from the fstp's cc clobbering. */
12186 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
12188 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
12189 return output_387_ffreep (operands, 0);
12194 return "fucompp\n\tfnstsw\t%0";
12196 return "fcompp\n\tfnstsw\t%0";
12201 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
12203 static const char * const alt[16] =
12205 "fcom%z2\t%y2\n\tfnstsw\t%0",
12206 "fcomp%z2\t%y2\n\tfnstsw\t%0",
12207 "fucom%z2\t%y2\n\tfnstsw\t%0",
12208 "fucomp%z2\t%y2\n\tfnstsw\t%0",
12210 "ficom%z2\t%y2\n\tfnstsw\t%0",
12211 "ficomp%z2\t%y2\n\tfnstsw\t%0",
12215 "fcomi\t{%y1, %0|%0, %y1}",
12216 "fcomip\t{%y1, %0|%0, %y1}",
12217 "fucomi\t{%y1, %0|%0, %y1}",
12218 "fucomip\t{%y1, %0|%0, %y1}",
12229 mask = eflags_p << 3;
12230 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
12231 mask |= unordered_p << 1;
12232 mask |= stack_top_dies;
12234 gcc_assert (mask < 16);
12243 ix86_output_addr_vec_elt (FILE *file, int value)
12245 const char *directive = ASM_LONG;
12249 directive = ASM_QUAD;
12251 gcc_assert (!TARGET_64BIT);
12254 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
12258 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
12260 const char *directive = ASM_LONG;
12263 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
12264 directive = ASM_QUAD;
12266 gcc_assert (!TARGET_64BIT);
12268 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
12269 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
12270 fprintf (file, "%s%s%d-%s%d\n",
12271 directive, LPREFIX, value, LPREFIX, rel);
12272 else if (HAVE_AS_GOTOFF_IN_DATA)
12273 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
12275 else if (TARGET_MACHO)
12277 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
12278 machopic_output_function_base_name (file);
12279 fprintf(file, "\n");
12283 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
12284 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
12287 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
12291 ix86_expand_clear (rtx dest)
12295 /* We play register width games, which are only valid after reload. */
12296 gcc_assert (reload_completed);
12298 /* Avoid HImode and its attendant prefix byte. */
12299 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
12300 dest = gen_rtx_REG (SImode, REGNO (dest));
12301 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
12303 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
12304 if (reload_completed && (!TARGET_USE_MOV0 || optimize_insn_for_speed_p ()))
12306 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12307 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
12313 /* X is an unchanging MEM. If it is a constant pool reference, return
12314 the constant pool rtx, else NULL. */
12317 maybe_get_pool_constant (rtx x)
12319 x = ix86_delegitimize_address (XEXP (x, 0));
12321 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
12322 return get_pool_constant (x);
12328 ix86_expand_move (enum machine_mode mode, rtx operands[])
12331 enum tls_model model;
12336 if (GET_CODE (op1) == SYMBOL_REF)
12338 model = SYMBOL_REF_TLS_MODEL (op1);
12341 op1 = legitimize_tls_address (op1, model, true);
12342 op1 = force_operand (op1, op0);
12346 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12347 && SYMBOL_REF_DLLIMPORT_P (op1))
12348 op1 = legitimize_dllimport_symbol (op1, false);
12350 else if (GET_CODE (op1) == CONST
12351 && GET_CODE (XEXP (op1, 0)) == PLUS
12352 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
12354 rtx addend = XEXP (XEXP (op1, 0), 1);
12355 rtx symbol = XEXP (XEXP (op1, 0), 0);
12358 model = SYMBOL_REF_TLS_MODEL (symbol);
12360 tmp = legitimize_tls_address (symbol, model, true);
12361 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12362 && SYMBOL_REF_DLLIMPORT_P (symbol))
12363 tmp = legitimize_dllimport_symbol (symbol, true);
12367 tmp = force_operand (tmp, NULL);
12368 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
12369 op0, 1, OPTAB_DIRECT);
12375 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
12377 if (TARGET_MACHO && !TARGET_64BIT)
12382 rtx temp = ((reload_in_progress
12383 || ((op0 && REG_P (op0))
12385 ? op0 : gen_reg_rtx (Pmode));
12386 op1 = machopic_indirect_data_reference (op1, temp);
12387 op1 = machopic_legitimize_pic_address (op1, mode,
12388 temp == op1 ? 0 : temp);
12390 else if (MACHOPIC_INDIRECT)
12391 op1 = machopic_indirect_data_reference (op1, 0);
12399 op1 = force_reg (Pmode, op1);
12400 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
12402 rtx reg = !can_create_pseudo_p () ? op0 : NULL_RTX;
12403 op1 = legitimize_pic_address (op1, reg);
12412 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
12413 || !push_operand (op0, mode))
12415 op1 = force_reg (mode, op1);
12417 if (push_operand (op0, mode)
12418 && ! general_no_elim_operand (op1, mode))
12419 op1 = copy_to_mode_reg (mode, op1);
12421 /* Force large constants in 64bit compilation into register
12422 to get them CSEed. */
12423 if (can_create_pseudo_p ()
12424 && (mode == DImode) && TARGET_64BIT
12425 && immediate_operand (op1, mode)
12426 && !x86_64_zext_immediate_operand (op1, VOIDmode)
12427 && !register_operand (op0, mode)
12429 op1 = copy_to_mode_reg (mode, op1);
12431 if (can_create_pseudo_p ()
12432 && FLOAT_MODE_P (mode)
12433 && GET_CODE (op1) == CONST_DOUBLE)
12435 /* If we are loading a floating point constant to a register,
12436 force the value to memory now, since we'll get better code
12437 out the back end. */
12439 op1 = validize_mem (force_const_mem (mode, op1));
12440 if (!register_operand (op0, mode))
12442 rtx temp = gen_reg_rtx (mode);
12443 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
12444 emit_move_insn (op0, temp);
12450 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12454 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
12456 rtx op0 = operands[0], op1 = operands[1];
12457 unsigned int align = GET_MODE_ALIGNMENT (mode);
12459 /* Force constants other than zero into memory. We do not know how
12460 the instructions used to build constants modify the upper 64 bits
12461 of the register, once we have that information we may be able
12462 to handle some of them more efficiently. */
12463 if (can_create_pseudo_p ()
12464 && register_operand (op0, mode)
12465 && (CONSTANT_P (op1)
12466 || (GET_CODE (op1) == SUBREG
12467 && CONSTANT_P (SUBREG_REG (op1))))
12468 && standard_sse_constant_p (op1) <= 0)
12469 op1 = validize_mem (force_const_mem (mode, op1));
12471 /* We need to check memory alignment for SSE mode since attribute
12472 can make operands unaligned. */
12473 if (can_create_pseudo_p ()
12474 && SSE_REG_MODE_P (mode)
12475 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
12476 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
12480 /* ix86_expand_vector_move_misalign() does not like constants ... */
12481 if (CONSTANT_P (op1)
12482 || (GET_CODE (op1) == SUBREG
12483 && CONSTANT_P (SUBREG_REG (op1))))
12484 op1 = validize_mem (force_const_mem (mode, op1));
12486 /* ... nor both arguments in memory. */
12487 if (!register_operand (op0, mode)
12488 && !register_operand (op1, mode))
12489 op1 = force_reg (mode, op1);
12491 tmp[0] = op0; tmp[1] = op1;
12492 ix86_expand_vector_move_misalign (mode, tmp);
12496 /* Make operand1 a register if it isn't already. */
12497 if (can_create_pseudo_p ()
12498 && !register_operand (op0, mode)
12499 && !register_operand (op1, mode))
12501 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
12505 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12508 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
12509 straight to ix86_expand_vector_move. */
12510 /* Code generation for scalar reg-reg moves of single and double precision data:
12511 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
12515 if (x86_sse_partial_reg_dependency == true)
12520 Code generation for scalar loads of double precision data:
12521 if (x86_sse_split_regs == true)
12522 movlpd mem, reg (gas syntax)
12526 Code generation for unaligned packed loads of single precision data
12527 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
12528 if (x86_sse_unaligned_move_optimal)
12531 if (x86_sse_partial_reg_dependency == true)
12543 Code generation for unaligned packed loads of double precision data
12544 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
12545 if (x86_sse_unaligned_move_optimal)
12548 if (x86_sse_split_regs == true)
12561 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
12570 switch (GET_MODE_CLASS (mode))
12572 case MODE_VECTOR_INT:
12574 switch (GET_MODE_SIZE (mode))
12577 op0 = gen_lowpart (V16QImode, op0);
12578 op1 = gen_lowpart (V16QImode, op1);
12579 emit_insn (gen_avx_movdqu (op0, op1));
12582 op0 = gen_lowpart (V32QImode, op0);
12583 op1 = gen_lowpart (V32QImode, op1);
12584 emit_insn (gen_avx_movdqu256 (op0, op1));
12587 gcc_unreachable ();
12590 case MODE_VECTOR_FLOAT:
12591 op0 = gen_lowpart (mode, op0);
12592 op1 = gen_lowpart (mode, op1);
12597 emit_insn (gen_avx_movups (op0, op1));
12600 emit_insn (gen_avx_movups256 (op0, op1));
12603 emit_insn (gen_avx_movupd (op0, op1));
12606 emit_insn (gen_avx_movupd256 (op0, op1));
12609 gcc_unreachable ();
12614 gcc_unreachable ();
12622 /* If we're optimizing for size, movups is the smallest. */
12623 if (optimize_insn_for_size_p ())
12625 op0 = gen_lowpart (V4SFmode, op0);
12626 op1 = gen_lowpart (V4SFmode, op1);
12627 emit_insn (gen_sse_movups (op0, op1));
12631 /* ??? If we have typed data, then it would appear that using
12632 movdqu is the only way to get unaligned data loaded with
12634 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12636 op0 = gen_lowpart (V16QImode, op0);
12637 op1 = gen_lowpart (V16QImode, op1);
12638 emit_insn (gen_sse2_movdqu (op0, op1));
12642 if (TARGET_SSE2 && mode == V2DFmode)
12646 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12648 op0 = gen_lowpart (V2DFmode, op0);
12649 op1 = gen_lowpart (V2DFmode, op1);
12650 emit_insn (gen_sse2_movupd (op0, op1));
12654 /* When SSE registers are split into halves, we can avoid
12655 writing to the top half twice. */
12656 if (TARGET_SSE_SPLIT_REGS)
12658 emit_clobber (op0);
12663 /* ??? Not sure about the best option for the Intel chips.
12664 The following would seem to satisfy; the register is
12665 entirely cleared, breaking the dependency chain. We
12666 then store to the upper half, with a dependency depth
12667 of one. A rumor has it that Intel recommends two movsd
12668 followed by an unpacklpd, but this is unconfirmed. And
12669 given that the dependency depth of the unpacklpd would
12670 still be one, I'm not sure why this would be better. */
12671 zero = CONST0_RTX (V2DFmode);
12674 m = adjust_address (op1, DFmode, 0);
12675 emit_insn (gen_sse2_loadlpd (op0, zero, m));
12676 m = adjust_address (op1, DFmode, 8);
12677 emit_insn (gen_sse2_loadhpd (op0, op0, m));
12681 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12683 op0 = gen_lowpart (V4SFmode, op0);
12684 op1 = gen_lowpart (V4SFmode, op1);
12685 emit_insn (gen_sse_movups (op0, op1));
12689 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
12690 emit_move_insn (op0, CONST0_RTX (mode));
12692 emit_clobber (op0);
12694 if (mode != V4SFmode)
12695 op0 = gen_lowpart (V4SFmode, op0);
12696 m = adjust_address (op1, V2SFmode, 0);
12697 emit_insn (gen_sse_loadlps (op0, op0, m));
12698 m = adjust_address (op1, V2SFmode, 8);
12699 emit_insn (gen_sse_loadhps (op0, op0, m));
12702 else if (MEM_P (op0))
12704 /* If we're optimizing for size, movups is the smallest. */
12705 if (optimize_insn_for_size_p ())
12707 op0 = gen_lowpart (V4SFmode, op0);
12708 op1 = gen_lowpart (V4SFmode, op1);
12709 emit_insn (gen_sse_movups (op0, op1));
12713 /* ??? Similar to above, only less clear because of quote
12714 typeless stores unquote. */
12715 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
12716 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12718 op0 = gen_lowpart (V16QImode, op0);
12719 op1 = gen_lowpart (V16QImode, op1);
12720 emit_insn (gen_sse2_movdqu (op0, op1));
12724 if (TARGET_SSE2 && mode == V2DFmode)
12726 m = adjust_address (op0, DFmode, 0);
12727 emit_insn (gen_sse2_storelpd (m, op1));
12728 m = adjust_address (op0, DFmode, 8);
12729 emit_insn (gen_sse2_storehpd (m, op1));
12733 if (mode != V4SFmode)
12734 op1 = gen_lowpart (V4SFmode, op1);
12735 m = adjust_address (op0, V2SFmode, 0);
12736 emit_insn (gen_sse_storelps (m, op1));
12737 m = adjust_address (op0, V2SFmode, 8);
12738 emit_insn (gen_sse_storehps (m, op1));
12742 gcc_unreachable ();
12745 /* Expand a push in MODE. This is some mode for which we do not support
12746 proper push instructions, at least from the registers that we expect
12747 the value to live in. */
12750 ix86_expand_push (enum machine_mode mode, rtx x)
12754 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
12755 GEN_INT (-GET_MODE_SIZE (mode)),
12756 stack_pointer_rtx, 1, OPTAB_DIRECT);
12757 if (tmp != stack_pointer_rtx)
12758 emit_move_insn (stack_pointer_rtx, tmp);
12760 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
12762 /* When we push an operand onto stack, it has to be aligned at least
12763 at the function argument boundary. However since we don't have
12764 the argument type, we can't determine the actual argument
12766 emit_move_insn (tmp, x);
12769 /* Helper function of ix86_fixup_binary_operands to canonicalize
12770 operand order. Returns true if the operands should be swapped. */
12773 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
12776 rtx dst = operands[0];
12777 rtx src1 = operands[1];
12778 rtx src2 = operands[2];
12780 /* If the operation is not commutative, we can't do anything. */
12781 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
12784 /* Highest priority is that src1 should match dst. */
12785 if (rtx_equal_p (dst, src1))
12787 if (rtx_equal_p (dst, src2))
12790 /* Next highest priority is that immediate constants come second. */
12791 if (immediate_operand (src2, mode))
12793 if (immediate_operand (src1, mode))
12796 /* Lowest priority is that memory references should come second. */
12806 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
12807 destination to use for the operation. If different from the true
12808 destination in operands[0], a copy operation will be required. */
12811 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
12814 rtx dst = operands[0];
12815 rtx src1 = operands[1];
12816 rtx src2 = operands[2];
12818 /* Canonicalize operand order. */
12819 if (ix86_swap_binary_operands_p (code, mode, operands))
12823 /* It is invalid to swap operands of different modes. */
12824 gcc_assert (GET_MODE (src1) == GET_MODE (src2));
12831 /* Both source operands cannot be in memory. */
12832 if (MEM_P (src1) && MEM_P (src2))
12834 /* Optimization: Only read from memory once. */
12835 if (rtx_equal_p (src1, src2))
12837 src2 = force_reg (mode, src2);
12841 src2 = force_reg (mode, src2);
12844 /* If the destination is memory, and we do not have matching source
12845 operands, do things in registers. */
12846 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
12847 dst = gen_reg_rtx (mode);
12849 /* Source 1 cannot be a constant. */
12850 if (CONSTANT_P (src1))
12851 src1 = force_reg (mode, src1);
12853 /* Source 1 cannot be a non-matching memory. */
12854 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
12855 src1 = force_reg (mode, src1);
12857 operands[1] = src1;
12858 operands[2] = src2;
12862 /* Similarly, but assume that the destination has already been
12863 set up properly. */
12866 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
12867 enum machine_mode mode, rtx operands[])
12869 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
12870 gcc_assert (dst == operands[0]);
12873 /* Attempt to expand a binary operator. Make the expansion closer to the
12874 actual machine, then just general_operand, which will allow 3 separate
12875 memory references (one output, two input) in a single insn. */
12878 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
12881 rtx src1, src2, dst, op, clob;
12883 dst = ix86_fixup_binary_operands (code, mode, operands);
12884 src1 = operands[1];
12885 src2 = operands[2];
12887 /* Emit the instruction. */
12889 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
12890 if (reload_in_progress)
12892 /* Reload doesn't know about the flags register, and doesn't know that
12893 it doesn't want to clobber it. We can only do this with PLUS. */
12894 gcc_assert (code == PLUS);
12899 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12900 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
12903 /* Fix up the destination if needed. */
12904 if (dst != operands[0])
12905 emit_move_insn (operands[0], dst);
12908 /* Return TRUE or FALSE depending on whether the binary operator meets the
12909 appropriate constraints. */
12912 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
12915 rtx dst = operands[0];
12916 rtx src1 = operands[1];
12917 rtx src2 = operands[2];
12919 /* Both source operands cannot be in memory. */
12920 if (MEM_P (src1) && MEM_P (src2))
12923 /* Canonicalize operand order for commutative operators. */
12924 if (ix86_swap_binary_operands_p (code, mode, operands))
12931 /* If the destination is memory, we must have a matching source operand. */
12932 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
12935 /* Source 1 cannot be a constant. */
12936 if (CONSTANT_P (src1))
12939 /* Source 1 cannot be a non-matching memory. */
12940 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
12946 /* Attempt to expand a unary operator. Make the expansion closer to the
12947 actual machine, then just general_operand, which will allow 2 separate
12948 memory references (one output, one input) in a single insn. */
12951 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
12954 int matching_memory;
12955 rtx src, dst, op, clob;
12960 /* If the destination is memory, and we do not have matching source
12961 operands, do things in registers. */
12962 matching_memory = 0;
12965 if (rtx_equal_p (dst, src))
12966 matching_memory = 1;
12968 dst = gen_reg_rtx (mode);
12971 /* When source operand is memory, destination must match. */
12972 if (MEM_P (src) && !matching_memory)
12973 src = force_reg (mode, src);
12975 /* Emit the instruction. */
12977 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
12978 if (reload_in_progress || code == NOT)
12980 /* Reload doesn't know about the flags register, and doesn't know that
12981 it doesn't want to clobber it. */
12982 gcc_assert (code == NOT);
12987 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12988 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
12991 /* Fix up the destination if needed. */
12992 if (dst != operands[0])
12993 emit_move_insn (operands[0], dst);
12996 /* Return TRUE or FALSE depending on whether the unary operator meets the
12997 appropriate constraints. */
13000 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
13001 enum machine_mode mode ATTRIBUTE_UNUSED,
13002 rtx operands[2] ATTRIBUTE_UNUSED)
13004 /* If one of operands is memory, source and destination must match. */
13005 if ((MEM_P (operands[0])
13006 || MEM_P (operands[1]))
13007 && ! rtx_equal_p (operands[0], operands[1]))
13012 /* Post-reload splitter for converting an SF or DFmode value in an
13013 SSE register into an unsigned SImode. */
13016 ix86_split_convert_uns_si_sse (rtx operands[])
13018 enum machine_mode vecmode;
13019 rtx value, large, zero_or_two31, input, two31, x;
13021 large = operands[1];
13022 zero_or_two31 = operands[2];
13023 input = operands[3];
13024 two31 = operands[4];
13025 vecmode = GET_MODE (large);
13026 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
13028 /* Load up the value into the low element. We must ensure that the other
13029 elements are valid floats -- zero is the easiest such value. */
13032 if (vecmode == V4SFmode)
13033 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
13035 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
13039 input = gen_rtx_REG (vecmode, REGNO (input));
13040 emit_move_insn (value, CONST0_RTX (vecmode));
13041 if (vecmode == V4SFmode)
13042 emit_insn (gen_sse_movss (value, value, input));
13044 emit_insn (gen_sse2_movsd (value, value, input));
13047 emit_move_insn (large, two31);
13048 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
13050 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
13051 emit_insn (gen_rtx_SET (VOIDmode, large, x));
13053 x = gen_rtx_AND (vecmode, zero_or_two31, large);
13054 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
13056 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
13057 emit_insn (gen_rtx_SET (VOIDmode, value, x));
13059 large = gen_rtx_REG (V4SImode, REGNO (large));
13060 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
13062 x = gen_rtx_REG (V4SImode, REGNO (value));
13063 if (vecmode == V4SFmode)
13064 emit_insn (gen_sse2_cvttps2dq (x, value));
13066 emit_insn (gen_sse2_cvttpd2dq (x, value));
13069 emit_insn (gen_xorv4si3 (value, value, large));
13072 /* Convert an unsigned DImode value into a DFmode, using only SSE.
13073 Expects the 64-bit DImode to be supplied in a pair of integral
13074 registers. Requires SSE2; will use SSE3 if available. For x86_32,
13075 -mfpmath=sse, !optimize_size only. */
13078 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
13080 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
13081 rtx int_xmm, fp_xmm;
13082 rtx biases, exponents;
13085 int_xmm = gen_reg_rtx (V4SImode);
13086 if (TARGET_INTER_UNIT_MOVES)
13087 emit_insn (gen_movdi_to_sse (int_xmm, input));
13088 else if (TARGET_SSE_SPLIT_REGS)
13090 emit_clobber (int_xmm);
13091 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
13095 x = gen_reg_rtx (V2DImode);
13096 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
13097 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
13100 x = gen_rtx_CONST_VECTOR (V4SImode,
13101 gen_rtvec (4, GEN_INT (0x43300000UL),
13102 GEN_INT (0x45300000UL),
13103 const0_rtx, const0_rtx));
13104 exponents = validize_mem (force_const_mem (V4SImode, x));
13106 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
13107 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
13109 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
13110 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
13111 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
13112 (0x1.0p84 + double(fp_value_hi_xmm)).
13113 Note these exponents differ by 32. */
13115 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
13117 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
13118 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
13119 real_ldexp (&bias_lo_rvt, &dconst1, 52);
13120 real_ldexp (&bias_hi_rvt, &dconst1, 84);
13121 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
13122 x = const_double_from_real_value (bias_hi_rvt, DFmode);
13123 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
13124 biases = validize_mem (force_const_mem (V2DFmode, biases));
13125 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
13127 /* Add the upper and lower DFmode values together. */
13129 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
13132 x = copy_to_mode_reg (V2DFmode, fp_xmm);
13133 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
13134 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
13137 ix86_expand_vector_extract (false, target, fp_xmm, 0);
13140 /* Not used, but eases macroization of patterns. */
13142 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
13143 rtx input ATTRIBUTE_UNUSED)
13145 gcc_unreachable ();
13148 /* Convert an unsigned SImode value into a DFmode. Only currently used
13149 for SSE, but applicable anywhere. */
13152 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
13154 REAL_VALUE_TYPE TWO31r;
13157 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
13158 NULL, 1, OPTAB_DIRECT);
13160 fp = gen_reg_rtx (DFmode);
13161 emit_insn (gen_floatsidf2 (fp, x));
13163 real_ldexp (&TWO31r, &dconst1, 31);
13164 x = const_double_from_real_value (TWO31r, DFmode);
13166 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
13168 emit_move_insn (target, x);
13171 /* Convert a signed DImode value into a DFmode. Only used for SSE in
13172 32-bit mode; otherwise we have a direct convert instruction. */
13175 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
13177 REAL_VALUE_TYPE TWO32r;
13178 rtx fp_lo, fp_hi, x;
13180 fp_lo = gen_reg_rtx (DFmode);
13181 fp_hi = gen_reg_rtx (DFmode);
13183 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
13185 real_ldexp (&TWO32r, &dconst1, 32);
13186 x = const_double_from_real_value (TWO32r, DFmode);
13187 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
13189 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
13191 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
13194 emit_move_insn (target, x);
13197 /* Convert an unsigned SImode value into a SFmode, using only SSE.
13198 For x86_32, -mfpmath=sse, !optimize_size only. */
13200 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
13202 REAL_VALUE_TYPE ONE16r;
13203 rtx fp_hi, fp_lo, int_hi, int_lo, x;
13205 real_ldexp (&ONE16r, &dconst1, 16);
13206 x = const_double_from_real_value (ONE16r, SFmode);
13207 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
13208 NULL, 0, OPTAB_DIRECT);
13209 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
13210 NULL, 0, OPTAB_DIRECT);
13211 fp_hi = gen_reg_rtx (SFmode);
13212 fp_lo = gen_reg_rtx (SFmode);
13213 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
13214 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
13215 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
13217 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
13219 if (!rtx_equal_p (target, fp_hi))
13220 emit_move_insn (target, fp_hi);
13223 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
13224 then replicate the value for all elements of the vector
13228 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
13235 v = gen_rtvec (4, value, value, value, value);
13236 return gen_rtx_CONST_VECTOR (V4SImode, v);
13240 v = gen_rtvec (2, value, value);
13241 return gen_rtx_CONST_VECTOR (V2DImode, v);
13245 v = gen_rtvec (4, value, value, value, value);
13247 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
13248 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13249 return gen_rtx_CONST_VECTOR (V4SFmode, v);
13253 v = gen_rtvec (2, value, value);
13255 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
13256 return gen_rtx_CONST_VECTOR (V2DFmode, v);
13259 gcc_unreachable ();
13263 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
13264 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
13265 for an SSE register. If VECT is true, then replicate the mask for
13266 all elements of the vector register. If INVERT is true, then create
13267 a mask excluding the sign bit. */
13270 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
13272 enum machine_mode vec_mode, imode;
13273 HOST_WIDE_INT hi, lo;
13278 /* Find the sign bit, sign extended to 2*HWI. */
13284 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
13285 lo = 0x80000000, hi = lo < 0;
13291 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
13292 if (HOST_BITS_PER_WIDE_INT >= 64)
13293 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
13295 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13300 vec_mode = VOIDmode;
13301 if (HOST_BITS_PER_WIDE_INT >= 64)
13304 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
13311 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13315 lo = ~lo, hi = ~hi;
13321 mask = immed_double_const (lo, hi, imode);
13323 vec = gen_rtvec (2, v, mask);
13324 v = gen_rtx_CONST_VECTOR (V2DImode, vec);
13325 v = copy_to_mode_reg (mode, gen_lowpart (mode, v));
13332 gcc_unreachable ();
13336 lo = ~lo, hi = ~hi;
13338 /* Force this value into the low part of a fp vector constant. */
13339 mask = immed_double_const (lo, hi, imode);
13340 mask = gen_lowpart (mode, mask);
13342 if (vec_mode == VOIDmode)
13343 return force_reg (mode, mask);
13345 v = ix86_build_const_vector (mode, vect, mask);
13346 return force_reg (vec_mode, v);
13349 /* Generate code for floating point ABS or NEG. */
13352 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
13355 rtx mask, set, use, clob, dst, src;
13356 bool use_sse = false;
13357 bool vector_mode = VECTOR_MODE_P (mode);
13358 enum machine_mode elt_mode = mode;
13362 elt_mode = GET_MODE_INNER (mode);
13365 else if (mode == TFmode)
13367 else if (TARGET_SSE_MATH)
13368 use_sse = SSE_FLOAT_MODE_P (mode);
13370 /* NEG and ABS performed with SSE use bitwise mask operations.
13371 Create the appropriate mask now. */
13373 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
13382 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
13383 set = gen_rtx_SET (VOIDmode, dst, set);
13388 set = gen_rtx_fmt_e (code, mode, src);
13389 set = gen_rtx_SET (VOIDmode, dst, set);
13392 use = gen_rtx_USE (VOIDmode, mask);
13393 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13394 emit_insn (gen_rtx_PARALLEL (VOIDmode,
13395 gen_rtvec (3, set, use, clob)));
13402 /* Expand a copysign operation. Special case operand 0 being a constant. */
13405 ix86_expand_copysign (rtx operands[])
13407 enum machine_mode mode;
13408 rtx dest, op0, op1, mask, nmask;
13410 dest = operands[0];
13414 mode = GET_MODE (dest);
13416 if (GET_CODE (op0) == CONST_DOUBLE)
13418 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
13420 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
13421 op0 = simplify_unary_operation (ABS, mode, op0, mode);
13423 if (mode == SFmode || mode == DFmode)
13425 enum machine_mode vmode;
13427 vmode = mode == SFmode ? V4SFmode : V2DFmode;
13429 if (op0 == CONST0_RTX (mode))
13430 op0 = CONST0_RTX (vmode);
13435 if (mode == SFmode)
13436 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
13437 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13439 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
13441 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
13444 else if (op0 != CONST0_RTX (mode))
13445 op0 = force_reg (mode, op0);
13447 mask = ix86_build_signbit_mask (mode, 0, 0);
13449 if (mode == SFmode)
13450 copysign_insn = gen_copysignsf3_const;
13451 else if (mode == DFmode)
13452 copysign_insn = gen_copysigndf3_const;
13454 copysign_insn = gen_copysigntf3_const;
13456 emit_insn (copysign_insn (dest, op0, op1, mask));
13460 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
13462 nmask = ix86_build_signbit_mask (mode, 0, 1);
13463 mask = ix86_build_signbit_mask (mode, 0, 0);
13465 if (mode == SFmode)
13466 copysign_insn = gen_copysignsf3_var;
13467 else if (mode == DFmode)
13468 copysign_insn = gen_copysigndf3_var;
13470 copysign_insn = gen_copysigntf3_var;
13472 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
13476 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
13477 be a constant, and so has already been expanded into a vector constant. */
13480 ix86_split_copysign_const (rtx operands[])
13482 enum machine_mode mode, vmode;
13483 rtx dest, op0, op1, mask, x;
13485 dest = operands[0];
13488 mask = operands[3];
13490 mode = GET_MODE (dest);
13491 vmode = GET_MODE (mask);
13493 dest = simplify_gen_subreg (vmode, dest, mode, 0);
13494 x = gen_rtx_AND (vmode, dest, mask);
13495 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13497 if (op0 != CONST0_RTX (vmode))
13499 x = gen_rtx_IOR (vmode, dest, op0);
13500 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13504 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
13505 so we have to do two masks. */
13508 ix86_split_copysign_var (rtx operands[])
13510 enum machine_mode mode, vmode;
13511 rtx dest, scratch, op0, op1, mask, nmask, x;
13513 dest = operands[0];
13514 scratch = operands[1];
13517 nmask = operands[4];
13518 mask = operands[5];
13520 mode = GET_MODE (dest);
13521 vmode = GET_MODE (mask);
13523 if (rtx_equal_p (op0, op1))
13525 /* Shouldn't happen often (it's useless, obviously), but when it does
13526 we'd generate incorrect code if we continue below. */
13527 emit_move_insn (dest, op0);
13531 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
13533 gcc_assert (REGNO (op1) == REGNO (scratch));
13535 x = gen_rtx_AND (vmode, scratch, mask);
13536 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13539 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
13540 x = gen_rtx_NOT (vmode, dest);
13541 x = gen_rtx_AND (vmode, x, op0);
13542 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13546 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
13548 x = gen_rtx_AND (vmode, scratch, mask);
13550 else /* alternative 2,4 */
13552 gcc_assert (REGNO (mask) == REGNO (scratch));
13553 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
13554 x = gen_rtx_AND (vmode, scratch, op1);
13556 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13558 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
13560 dest = simplify_gen_subreg (vmode, op0, mode, 0);
13561 x = gen_rtx_AND (vmode, dest, nmask);
13563 else /* alternative 3,4 */
13565 gcc_assert (REGNO (nmask) == REGNO (dest));
13567 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
13568 x = gen_rtx_AND (vmode, dest, op0);
13570 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13573 x = gen_rtx_IOR (vmode, dest, scratch);
13574 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13577 /* Return TRUE or FALSE depending on whether the first SET in INSN
13578 has source and destination with matching CC modes, and that the
13579 CC mode is at least as constrained as REQ_MODE. */
13582 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
13585 enum machine_mode set_mode;
13587 set = PATTERN (insn);
13588 if (GET_CODE (set) == PARALLEL)
13589 set = XVECEXP (set, 0, 0);
13590 gcc_assert (GET_CODE (set) == SET);
13591 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
13593 set_mode = GET_MODE (SET_DEST (set));
13597 if (req_mode != CCNOmode
13598 && (req_mode != CCmode
13599 || XEXP (SET_SRC (set), 1) != const0_rtx))
13603 if (req_mode == CCGCmode)
13607 if (req_mode == CCGOCmode || req_mode == CCNOmode)
13611 if (req_mode == CCZmode)
13622 gcc_unreachable ();
13625 return (GET_MODE (SET_SRC (set)) == set_mode);
13628 /* Generate insn patterns to do an integer compare of OPERANDS. */
13631 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
13633 enum machine_mode cmpmode;
13636 cmpmode = SELECT_CC_MODE (code, op0, op1);
13637 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
13639 /* This is very simple, but making the interface the same as in the
13640 FP case makes the rest of the code easier. */
13641 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
13642 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
13644 /* Return the test that should be put into the flags user, i.e.
13645 the bcc, scc, or cmov instruction. */
13646 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
13649 /* Figure out whether to use ordered or unordered fp comparisons.
13650 Return the appropriate mode to use. */
13653 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
13655 /* ??? In order to make all comparisons reversible, we do all comparisons
13656 non-trapping when compiling for IEEE. Once gcc is able to distinguish
13657 all forms trapping and nontrapping comparisons, we can make inequality
13658 comparisons trapping again, since it results in better code when using
13659 FCOM based compares. */
13660 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
13664 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
13666 enum machine_mode mode = GET_MODE (op0);
13668 if (SCALAR_FLOAT_MODE_P (mode))
13670 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
13671 return ix86_fp_compare_mode (code);
13676 /* Only zero flag is needed. */
13677 case EQ: /* ZF=0 */
13678 case NE: /* ZF!=0 */
13680 /* Codes needing carry flag. */
13681 case GEU: /* CF=0 */
13682 case LTU: /* CF=1 */
13683 /* Detect overflow checks. They need just the carry flag. */
13684 if (GET_CODE (op0) == PLUS
13685 && rtx_equal_p (op1, XEXP (op0, 0)))
13689 case GTU: /* CF=0 & ZF=0 */
13690 case LEU: /* CF=1 | ZF=1 */
13691 /* Detect overflow checks. They need just the carry flag. */
13692 if (GET_CODE (op0) == MINUS
13693 && rtx_equal_p (op1, XEXP (op0, 0)))
13697 /* Codes possibly doable only with sign flag when
13698 comparing against zero. */
13699 case GE: /* SF=OF or SF=0 */
13700 case LT: /* SF<>OF or SF=1 */
13701 if (op1 == const0_rtx)
13704 /* For other cases Carry flag is not required. */
13706 /* Codes doable only with sign flag when comparing
13707 against zero, but we miss jump instruction for it
13708 so we need to use relational tests against overflow
13709 that thus needs to be zero. */
13710 case GT: /* ZF=0 & SF=OF */
13711 case LE: /* ZF=1 | SF<>OF */
13712 if (op1 == const0_rtx)
13716 /* strcmp pattern do (use flags) and combine may ask us for proper
13721 gcc_unreachable ();
13725 /* Return the fixed registers used for condition codes. */
13728 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
13735 /* If two condition code modes are compatible, return a condition code
13736 mode which is compatible with both. Otherwise, return
13739 static enum machine_mode
13740 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
13745 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
13748 if ((m1 == CCGCmode && m2 == CCGOCmode)
13749 || (m1 == CCGOCmode && m2 == CCGCmode))
13755 gcc_unreachable ();
13785 /* These are only compatible with themselves, which we already
13791 /* Split comparison code CODE into comparisons we can do using branch
13792 instructions. BYPASS_CODE is comparison code for branch that will
13793 branch around FIRST_CODE and SECOND_CODE. If some of branches
13794 is not required, set value to UNKNOWN.
13795 We never require more than two branches. */
13798 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
13799 enum rtx_code *first_code,
13800 enum rtx_code *second_code)
13802 *first_code = code;
13803 *bypass_code = UNKNOWN;
13804 *second_code = UNKNOWN;
13806 /* The fcomi comparison sets flags as follows:
13816 case GT: /* GTU - CF=0 & ZF=0 */
13817 case GE: /* GEU - CF=0 */
13818 case ORDERED: /* PF=0 */
13819 case UNORDERED: /* PF=1 */
13820 case UNEQ: /* EQ - ZF=1 */
13821 case UNLT: /* LTU - CF=1 */
13822 case UNLE: /* LEU - CF=1 | ZF=1 */
13823 case LTGT: /* EQ - ZF=0 */
13825 case LT: /* LTU - CF=1 - fails on unordered */
13826 *first_code = UNLT;
13827 *bypass_code = UNORDERED;
13829 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
13830 *first_code = UNLE;
13831 *bypass_code = UNORDERED;
13833 case EQ: /* EQ - ZF=1 - fails on unordered */
13834 *first_code = UNEQ;
13835 *bypass_code = UNORDERED;
13837 case NE: /* NE - ZF=0 - fails on unordered */
13838 *first_code = LTGT;
13839 *second_code = UNORDERED;
13841 case UNGE: /* GEU - CF=0 - fails on unordered */
13843 *second_code = UNORDERED;
13845 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
13847 *second_code = UNORDERED;
13850 gcc_unreachable ();
13852 if (!TARGET_IEEE_FP)
13854 *second_code = UNKNOWN;
13855 *bypass_code = UNKNOWN;
13859 /* Return cost of comparison done fcom + arithmetics operations on AX.
13860 All following functions do use number of instructions as a cost metrics.
13861 In future this should be tweaked to compute bytes for optimize_size and
13862 take into account performance of various instructions on various CPUs. */
13864 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
13866 if (!TARGET_IEEE_FP)
13868 /* The cost of code output by ix86_expand_fp_compare. */
13892 gcc_unreachable ();
13896 /* Return cost of comparison done using fcomi operation.
13897 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13899 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
13901 enum rtx_code bypass_code, first_code, second_code;
13902 /* Return arbitrarily high cost when instruction is not supported - this
13903 prevents gcc from using it. */
13906 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13907 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
13910 /* Return cost of comparison done using sahf operation.
13911 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13913 ix86_fp_comparison_sahf_cost (enum rtx_code code)
13915 enum rtx_code bypass_code, first_code, second_code;
13916 /* Return arbitrarily high cost when instruction is not preferred - this
13917 avoids gcc from using it. */
13918 if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ())))
13920 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13921 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
13924 /* Compute cost of the comparison done using any method.
13925 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13927 ix86_fp_comparison_cost (enum rtx_code code)
13929 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
13932 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
13933 sahf_cost = ix86_fp_comparison_sahf_cost (code);
13935 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
13936 if (min > sahf_cost)
13938 if (min > fcomi_cost)
13943 /* Return true if we should use an FCOMI instruction for this
13947 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
13949 enum rtx_code swapped_code = swap_condition (code);
13951 return ((ix86_fp_comparison_cost (code)
13952 == ix86_fp_comparison_fcomi_cost (code))
13953 || (ix86_fp_comparison_cost (swapped_code)
13954 == ix86_fp_comparison_fcomi_cost (swapped_code)));
13957 /* Swap, force into registers, or otherwise massage the two operands
13958 to a fp comparison. The operands are updated in place; the new
13959 comparison code is returned. */
13961 static enum rtx_code
13962 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
13964 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
13965 rtx op0 = *pop0, op1 = *pop1;
13966 enum machine_mode op_mode = GET_MODE (op0);
13967 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
13969 /* All of the unordered compare instructions only work on registers.
13970 The same is true of the fcomi compare instructions. The XFmode
13971 compare instructions require registers except when comparing
13972 against zero or when converting operand 1 from fixed point to
13976 && (fpcmp_mode == CCFPUmode
13977 || (op_mode == XFmode
13978 && ! (standard_80387_constant_p (op0) == 1
13979 || standard_80387_constant_p (op1) == 1)
13980 && GET_CODE (op1) != FLOAT)
13981 || ix86_use_fcomi_compare (code)))
13983 op0 = force_reg (op_mode, op0);
13984 op1 = force_reg (op_mode, op1);
13988 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
13989 things around if they appear profitable, otherwise force op0
13990 into a register. */
13992 if (standard_80387_constant_p (op0) == 0
13994 && ! (standard_80387_constant_p (op1) == 0
13998 tmp = op0, op0 = op1, op1 = tmp;
13999 code = swap_condition (code);
14003 op0 = force_reg (op_mode, op0);
14005 if (CONSTANT_P (op1))
14007 int tmp = standard_80387_constant_p (op1);
14009 op1 = validize_mem (force_const_mem (op_mode, op1));
14013 op1 = force_reg (op_mode, op1);
14016 op1 = force_reg (op_mode, op1);
14020 /* Try to rearrange the comparison to make it cheaper. */
14021 if (ix86_fp_comparison_cost (code)
14022 > ix86_fp_comparison_cost (swap_condition (code))
14023 && (REG_P (op1) || can_create_pseudo_p ()))
14026 tmp = op0, op0 = op1, op1 = tmp;
14027 code = swap_condition (code);
14029 op0 = force_reg (op_mode, op0);
14037 /* Convert comparison codes we use to represent FP comparison to integer
14038 code that will result in proper branch. Return UNKNOWN if no such code
14042 ix86_fp_compare_code_to_integer (enum rtx_code code)
14071 /* Generate insn patterns to do a floating point compare of OPERANDS. */
14074 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
14075 rtx *second_test, rtx *bypass_test)
14077 enum machine_mode fpcmp_mode, intcmp_mode;
14079 int cost = ix86_fp_comparison_cost (code);
14080 enum rtx_code bypass_code, first_code, second_code;
14082 fpcmp_mode = ix86_fp_compare_mode (code);
14083 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
14086 *second_test = NULL_RTX;
14088 *bypass_test = NULL_RTX;
14090 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14092 /* Do fcomi/sahf based test when profitable. */
14093 if (ix86_fp_comparison_arithmetics_cost (code) > cost
14094 && (bypass_code == UNKNOWN || bypass_test)
14095 && (second_code == UNKNOWN || second_test))
14097 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14098 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
14104 gcc_assert (TARGET_SAHF);
14107 scratch = gen_reg_rtx (HImode);
14108 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
14110 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
14113 /* The FP codes work out to act like unsigned. */
14114 intcmp_mode = fpcmp_mode;
14116 if (bypass_code != UNKNOWN)
14117 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
14118 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14120 if (second_code != UNKNOWN)
14121 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
14122 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14127 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
14128 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14129 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
14131 scratch = gen_reg_rtx (HImode);
14132 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
14134 /* In the unordered case, we have to check C2 for NaN's, which
14135 doesn't happen to work out to anything nice combination-wise.
14136 So do some bit twiddling on the value we've got in AH to come
14137 up with an appropriate set of condition codes. */
14139 intcmp_mode = CCNOmode;
14144 if (code == GT || !TARGET_IEEE_FP)
14146 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14151 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14152 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14153 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
14154 intcmp_mode = CCmode;
14160 if (code == LT && TARGET_IEEE_FP)
14162 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14163 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
14164 intcmp_mode = CCmode;
14169 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
14175 if (code == GE || !TARGET_IEEE_FP)
14177 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
14182 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14183 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14190 if (code == LE && TARGET_IEEE_FP)
14192 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14193 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14194 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14195 intcmp_mode = CCmode;
14200 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14206 if (code == EQ && TARGET_IEEE_FP)
14208 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14209 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14210 intcmp_mode = CCmode;
14215 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14222 if (code == NE && TARGET_IEEE_FP)
14224 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14225 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14231 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14237 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14241 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14246 gcc_unreachable ();
14250 /* Return the test that should be put into the flags user, i.e.
14251 the bcc, scc, or cmov instruction. */
14252 return gen_rtx_fmt_ee (code, VOIDmode,
14253 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14258 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
14261 op0 = ix86_compare_op0;
14262 op1 = ix86_compare_op1;
14265 *second_test = NULL_RTX;
14267 *bypass_test = NULL_RTX;
14269 if (ix86_compare_emitted)
14271 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
14272 ix86_compare_emitted = NULL_RTX;
14274 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
14276 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
14277 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
14278 second_test, bypass_test);
14281 ret = ix86_expand_int_compare (code, op0, op1);
14286 /* Return true if the CODE will result in nontrivial jump sequence. */
14288 ix86_fp_jump_nontrivial_p (enum rtx_code code)
14290 enum rtx_code bypass_code, first_code, second_code;
14293 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14294 return bypass_code != UNKNOWN || second_code != UNKNOWN;
14298 ix86_expand_branch (enum rtx_code code, rtx label)
14302 /* If we have emitted a compare insn, go straight to simple.
14303 ix86_expand_compare won't emit anything if ix86_compare_emitted
14305 if (ix86_compare_emitted)
14308 switch (GET_MODE (ix86_compare_op0))
14314 tmp = ix86_expand_compare (code, NULL, NULL);
14315 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14316 gen_rtx_LABEL_REF (VOIDmode, label),
14318 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
14327 enum rtx_code bypass_code, first_code, second_code;
14329 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
14330 &ix86_compare_op1);
14332 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14334 /* Check whether we will use the natural sequence with one jump. If
14335 so, we can expand jump early. Otherwise delay expansion by
14336 creating compound insn to not confuse optimizers. */
14337 if (bypass_code == UNKNOWN && second_code == UNKNOWN)
14339 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
14340 gen_rtx_LABEL_REF (VOIDmode, label),
14341 pc_rtx, NULL_RTX, NULL_RTX);
14345 tmp = gen_rtx_fmt_ee (code, VOIDmode,
14346 ix86_compare_op0, ix86_compare_op1);
14347 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14348 gen_rtx_LABEL_REF (VOIDmode, label),
14350 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
14352 use_fcomi = ix86_use_fcomi_compare (code);
14353 vec = rtvec_alloc (3 + !use_fcomi);
14354 RTVEC_ELT (vec, 0) = tmp;
14356 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FPSR_REG));
14358 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FLAGS_REG));
14361 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
14363 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
14372 /* Expand DImode branch into multiple compare+branch. */
14374 rtx lo[2], hi[2], label2;
14375 enum rtx_code code1, code2, code3;
14376 enum machine_mode submode;
14378 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
14380 tmp = ix86_compare_op0;
14381 ix86_compare_op0 = ix86_compare_op1;
14382 ix86_compare_op1 = tmp;
14383 code = swap_condition (code);
14385 if (GET_MODE (ix86_compare_op0) == DImode)
14387 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
14388 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
14393 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
14394 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
14398 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
14399 avoid two branches. This costs one extra insn, so disable when
14400 optimizing for size. */
14402 if ((code == EQ || code == NE)
14403 && (!optimize_insn_for_size_p ()
14404 || hi[1] == const0_rtx || lo[1] == const0_rtx))
14409 if (hi[1] != const0_rtx)
14410 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
14411 NULL_RTX, 0, OPTAB_WIDEN);
14414 if (lo[1] != const0_rtx)
14415 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
14416 NULL_RTX, 0, OPTAB_WIDEN);
14418 tmp = expand_binop (submode, ior_optab, xor1, xor0,
14419 NULL_RTX, 0, OPTAB_WIDEN);
14421 ix86_compare_op0 = tmp;
14422 ix86_compare_op1 = const0_rtx;
14423 ix86_expand_branch (code, label);
14427 /* Otherwise, if we are doing less-than or greater-or-equal-than,
14428 op1 is a constant and the low word is zero, then we can just
14429 examine the high word. Similarly for low word -1 and
14430 less-or-equal-than or greater-than. */
14432 if (CONST_INT_P (hi[1]))
14435 case LT: case LTU: case GE: case GEU:
14436 if (lo[1] == const0_rtx)
14438 ix86_compare_op0 = hi[0];
14439 ix86_compare_op1 = hi[1];
14440 ix86_expand_branch (code, label);
14444 case LE: case LEU: case GT: case GTU:
14445 if (lo[1] == constm1_rtx)
14447 ix86_compare_op0 = hi[0];
14448 ix86_compare_op1 = hi[1];
14449 ix86_expand_branch (code, label);
14457 /* Otherwise, we need two or three jumps. */
14459 label2 = gen_label_rtx ();
14462 code2 = swap_condition (code);
14463 code3 = unsigned_condition (code);
14467 case LT: case GT: case LTU: case GTU:
14470 case LE: code1 = LT; code2 = GT; break;
14471 case GE: code1 = GT; code2 = LT; break;
14472 case LEU: code1 = LTU; code2 = GTU; break;
14473 case GEU: code1 = GTU; code2 = LTU; break;
14475 case EQ: code1 = UNKNOWN; code2 = NE; break;
14476 case NE: code2 = UNKNOWN; break;
14479 gcc_unreachable ();
14484 * if (hi(a) < hi(b)) goto true;
14485 * if (hi(a) > hi(b)) goto false;
14486 * if (lo(a) < lo(b)) goto true;
14490 ix86_compare_op0 = hi[0];
14491 ix86_compare_op1 = hi[1];
14493 if (code1 != UNKNOWN)
14494 ix86_expand_branch (code1, label);
14495 if (code2 != UNKNOWN)
14496 ix86_expand_branch (code2, label2);
14498 ix86_compare_op0 = lo[0];
14499 ix86_compare_op1 = lo[1];
14500 ix86_expand_branch (code3, label);
14502 if (code2 != UNKNOWN)
14503 emit_label (label2);
14508 gcc_unreachable ();
14512 /* Split branch based on floating point condition. */
14514 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
14515 rtx target1, rtx target2, rtx tmp, rtx pushed)
14517 rtx second, bypass;
14518 rtx label = NULL_RTX;
14520 int bypass_probability = -1, second_probability = -1, probability = -1;
14523 if (target2 != pc_rtx)
14526 code = reverse_condition_maybe_unordered (code);
14531 condition = ix86_expand_fp_compare (code, op1, op2,
14532 tmp, &second, &bypass);
14534 /* Remove pushed operand from stack. */
14536 ix86_free_from_memory (GET_MODE (pushed));
14538 if (split_branch_probability >= 0)
14540 /* Distribute the probabilities across the jumps.
14541 Assume the BYPASS and SECOND to be always test
14543 probability = split_branch_probability;
14545 /* Value of 1 is low enough to make no need for probability
14546 to be updated. Later we may run some experiments and see
14547 if unordered values are more frequent in practice. */
14549 bypass_probability = 1;
14551 second_probability = 1;
14553 if (bypass != NULL_RTX)
14555 label = gen_label_rtx ();
14556 i = emit_jump_insn (gen_rtx_SET
14558 gen_rtx_IF_THEN_ELSE (VOIDmode,
14560 gen_rtx_LABEL_REF (VOIDmode,
14563 if (bypass_probability >= 0)
14565 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14566 GEN_INT (bypass_probability),
14569 i = emit_jump_insn (gen_rtx_SET
14571 gen_rtx_IF_THEN_ELSE (VOIDmode,
14572 condition, target1, target2)));
14573 if (probability >= 0)
14575 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14576 GEN_INT (probability),
14578 if (second != NULL_RTX)
14580 i = emit_jump_insn (gen_rtx_SET
14582 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
14584 if (second_probability >= 0)
14586 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14587 GEN_INT (second_probability),
14590 if (label != NULL_RTX)
14591 emit_label (label);
14595 ix86_expand_setcc (enum rtx_code code, rtx dest)
14597 rtx ret, tmp, tmpreg, equiv;
14598 rtx second_test, bypass_test;
14600 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
14601 return 0; /* FAIL */
14603 gcc_assert (GET_MODE (dest) == QImode);
14605 ret = ix86_expand_compare (code, &second_test, &bypass_test);
14606 PUT_MODE (ret, QImode);
14611 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
14612 if (bypass_test || second_test)
14614 rtx test = second_test;
14616 rtx tmp2 = gen_reg_rtx (QImode);
14619 gcc_assert (!second_test);
14620 test = bypass_test;
14622 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
14624 PUT_MODE (test, QImode);
14625 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
14628 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
14630 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
14633 /* Attach a REG_EQUAL note describing the comparison result. */
14634 if (ix86_compare_op0 && ix86_compare_op1)
14636 equiv = simplify_gen_relational (code, QImode,
14637 GET_MODE (ix86_compare_op0),
14638 ix86_compare_op0, ix86_compare_op1);
14639 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
14642 return 1; /* DONE */
14645 /* Expand comparison setting or clearing carry flag. Return true when
14646 successful and set pop for the operation. */
14648 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
14650 enum machine_mode mode =
14651 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
14653 /* Do not handle DImode compares that go through special path. */
14654 if (mode == (TARGET_64BIT ? TImode : DImode))
14657 if (SCALAR_FLOAT_MODE_P (mode))
14659 rtx second_test = NULL, bypass_test = NULL;
14660 rtx compare_op, compare_seq;
14662 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
14664 /* Shortcut: following common codes never translate
14665 into carry flag compares. */
14666 if (code == EQ || code == NE || code == UNEQ || code == LTGT
14667 || code == ORDERED || code == UNORDERED)
14670 /* These comparisons require zero flag; swap operands so they won't. */
14671 if ((code == GT || code == UNLE || code == LE || code == UNGT)
14672 && !TARGET_IEEE_FP)
14677 code = swap_condition (code);
14680 /* Try to expand the comparison and verify that we end up with
14681 carry flag based comparison. This fails to be true only when
14682 we decide to expand comparison using arithmetic that is not
14683 too common scenario. */
14685 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
14686 &second_test, &bypass_test);
14687 compare_seq = get_insns ();
14690 if (second_test || bypass_test)
14693 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
14694 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
14695 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
14697 code = GET_CODE (compare_op);
14699 if (code != LTU && code != GEU)
14702 emit_insn (compare_seq);
14707 if (!INTEGRAL_MODE_P (mode))
14716 /* Convert a==0 into (unsigned)a<1. */
14719 if (op1 != const0_rtx)
14722 code = (code == EQ ? LTU : GEU);
14725 /* Convert a>b into b<a or a>=b-1. */
14728 if (CONST_INT_P (op1))
14730 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
14731 /* Bail out on overflow. We still can swap operands but that
14732 would force loading of the constant into register. */
14733 if (op1 == const0_rtx
14734 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
14736 code = (code == GTU ? GEU : LTU);
14743 code = (code == GTU ? LTU : GEU);
14747 /* Convert a>=0 into (unsigned)a<0x80000000. */
14750 if (mode == DImode || op1 != const0_rtx)
14752 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
14753 code = (code == LT ? GEU : LTU);
14757 if (mode == DImode || op1 != constm1_rtx)
14759 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
14760 code = (code == LE ? GEU : LTU);
14766 /* Swapping operands may cause constant to appear as first operand. */
14767 if (!nonimmediate_operand (op0, VOIDmode))
14769 if (!can_create_pseudo_p ())
14771 op0 = force_reg (mode, op0);
14773 ix86_compare_op0 = op0;
14774 ix86_compare_op1 = op1;
14775 *pop = ix86_expand_compare (code, NULL, NULL);
14776 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
14781 ix86_expand_int_movcc (rtx operands[])
14783 enum rtx_code code = GET_CODE (operands[1]), compare_code;
14784 rtx compare_seq, compare_op;
14785 rtx second_test, bypass_test;
14786 enum machine_mode mode = GET_MODE (operands[0]);
14787 bool sign_bit_compare_p = false;;
14790 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
14791 compare_seq = get_insns ();
14794 compare_code = GET_CODE (compare_op);
14796 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
14797 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
14798 sign_bit_compare_p = true;
14800 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
14801 HImode insns, we'd be swallowed in word prefix ops. */
14803 if ((mode != HImode || TARGET_FAST_PREFIX)
14804 && (mode != (TARGET_64BIT ? TImode : DImode))
14805 && CONST_INT_P (operands[2])
14806 && CONST_INT_P (operands[3]))
14808 rtx out = operands[0];
14809 HOST_WIDE_INT ct = INTVAL (operands[2]);
14810 HOST_WIDE_INT cf = INTVAL (operands[3]);
14811 HOST_WIDE_INT diff;
14814 /* Sign bit compares are better done using shifts than we do by using
14816 if (sign_bit_compare_p
14817 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
14818 ix86_compare_op1, &compare_op))
14820 /* Detect overlap between destination and compare sources. */
14823 if (!sign_bit_compare_p)
14825 bool fpcmp = false;
14827 compare_code = GET_CODE (compare_op);
14829 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
14830 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
14833 compare_code = ix86_fp_compare_code_to_integer (compare_code);
14836 /* To simplify rest of code, restrict to the GEU case. */
14837 if (compare_code == LTU)
14839 HOST_WIDE_INT tmp = ct;
14842 compare_code = reverse_condition (compare_code);
14843 code = reverse_condition (code);
14848 PUT_CODE (compare_op,
14849 reverse_condition_maybe_unordered
14850 (GET_CODE (compare_op)));
14852 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
14856 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
14857 || reg_overlap_mentioned_p (out, ix86_compare_op1))
14858 tmp = gen_reg_rtx (mode);
14860 if (mode == DImode)
14861 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
14863 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
14867 if (code == GT || code == GE)
14868 code = reverse_condition (code);
14871 HOST_WIDE_INT tmp = ct;
14876 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
14877 ix86_compare_op1, VOIDmode, 0, -1);
14890 tmp = expand_simple_binop (mode, PLUS,
14892 copy_rtx (tmp), 1, OPTAB_DIRECT);
14903 tmp = expand_simple_binop (mode, IOR,
14905 copy_rtx (tmp), 1, OPTAB_DIRECT);
14907 else if (diff == -1 && ct)
14917 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
14919 tmp = expand_simple_binop (mode, PLUS,
14920 copy_rtx (tmp), GEN_INT (cf),
14921 copy_rtx (tmp), 1, OPTAB_DIRECT);
14929 * andl cf - ct, dest
14939 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
14942 tmp = expand_simple_binop (mode, AND,
14944 gen_int_mode (cf - ct, mode),
14945 copy_rtx (tmp), 1, OPTAB_DIRECT);
14947 tmp = expand_simple_binop (mode, PLUS,
14948 copy_rtx (tmp), GEN_INT (ct),
14949 copy_rtx (tmp), 1, OPTAB_DIRECT);
14952 if (!rtx_equal_p (tmp, out))
14953 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
14955 return 1; /* DONE */
14960 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
14963 tmp = ct, ct = cf, cf = tmp;
14966 if (SCALAR_FLOAT_MODE_P (cmp_mode))
14968 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
14970 /* We may be reversing unordered compare to normal compare, that
14971 is not valid in general (we may convert non-trapping condition
14972 to trapping one), however on i386 we currently emit all
14973 comparisons unordered. */
14974 compare_code = reverse_condition_maybe_unordered (compare_code);
14975 code = reverse_condition_maybe_unordered (code);
14979 compare_code = reverse_condition (compare_code);
14980 code = reverse_condition (code);
14984 compare_code = UNKNOWN;
14985 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
14986 && CONST_INT_P (ix86_compare_op1))
14988 if (ix86_compare_op1 == const0_rtx
14989 && (code == LT || code == GE))
14990 compare_code = code;
14991 else if (ix86_compare_op1 == constm1_rtx)
14995 else if (code == GT)
15000 /* Optimize dest = (op0 < 0) ? -1 : cf. */
15001 if (compare_code != UNKNOWN
15002 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
15003 && (cf == -1 || ct == -1))
15005 /* If lea code below could be used, only optimize
15006 if it results in a 2 insn sequence. */
15008 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
15009 || diff == 3 || diff == 5 || diff == 9)
15010 || (compare_code == LT && ct == -1)
15011 || (compare_code == GE && cf == -1))
15014 * notl op1 (if necessary)
15022 code = reverse_condition (code);
15025 out = emit_store_flag (out, code, ix86_compare_op0,
15026 ix86_compare_op1, VOIDmode, 0, -1);
15028 out = expand_simple_binop (mode, IOR,
15030 out, 1, OPTAB_DIRECT);
15031 if (out != operands[0])
15032 emit_move_insn (operands[0], out);
15034 return 1; /* DONE */
15039 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
15040 || diff == 3 || diff == 5 || diff == 9)
15041 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
15043 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
15049 * lea cf(dest*(ct-cf)),dest
15053 * This also catches the degenerate setcc-only case.
15059 out = emit_store_flag (out, code, ix86_compare_op0,
15060 ix86_compare_op1, VOIDmode, 0, 1);
15063 /* On x86_64 the lea instruction operates on Pmode, so we need
15064 to get arithmetics done in proper mode to match. */
15066 tmp = copy_rtx (out);
15070 out1 = copy_rtx (out);
15071 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
15075 tmp = gen_rtx_PLUS (mode, tmp, out1);
15081 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
15084 if (!rtx_equal_p (tmp, out))
15087 out = force_operand (tmp, copy_rtx (out));
15089 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
15091 if (!rtx_equal_p (out, operands[0]))
15092 emit_move_insn (operands[0], copy_rtx (out));
15094 return 1; /* DONE */
15098 * General case: Jumpful:
15099 * xorl dest,dest cmpl op1, op2
15100 * cmpl op1, op2 movl ct, dest
15101 * setcc dest jcc 1f
15102 * decl dest movl cf, dest
15103 * andl (cf-ct),dest 1:
15106 * Size 20. Size 14.
15108 * This is reasonably steep, but branch mispredict costs are
15109 * high on modern cpus, so consider failing only if optimizing
15113 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15114 && BRANCH_COST (optimize_insn_for_speed_p (),
15119 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
15124 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15126 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15128 /* We may be reversing unordered compare to normal compare,
15129 that is not valid in general (we may convert non-trapping
15130 condition to trapping one), however on i386 we currently
15131 emit all comparisons unordered. */
15132 code = reverse_condition_maybe_unordered (code);
15136 code = reverse_condition (code);
15137 if (compare_code != UNKNOWN)
15138 compare_code = reverse_condition (compare_code);
15142 if (compare_code != UNKNOWN)
15144 /* notl op1 (if needed)
15149 For x < 0 (resp. x <= -1) there will be no notl,
15150 so if possible swap the constants to get rid of the
15152 True/false will be -1/0 while code below (store flag
15153 followed by decrement) is 0/-1, so the constants need
15154 to be exchanged once more. */
15156 if (compare_code == GE || !cf)
15158 code = reverse_condition (code);
15163 HOST_WIDE_INT tmp = cf;
15168 out = emit_store_flag (out, code, ix86_compare_op0,
15169 ix86_compare_op1, VOIDmode, 0, -1);
15173 out = emit_store_flag (out, code, ix86_compare_op0,
15174 ix86_compare_op1, VOIDmode, 0, 1);
15176 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
15177 copy_rtx (out), 1, OPTAB_DIRECT);
15180 out = expand_simple_binop (mode, AND, copy_rtx (out),
15181 gen_int_mode (cf - ct, mode),
15182 copy_rtx (out), 1, OPTAB_DIRECT);
15184 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
15185 copy_rtx (out), 1, OPTAB_DIRECT);
15186 if (!rtx_equal_p (out, operands[0]))
15187 emit_move_insn (operands[0], copy_rtx (out));
15189 return 1; /* DONE */
15193 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15195 /* Try a few things more with specific constants and a variable. */
15198 rtx var, orig_out, out, tmp;
15200 if (BRANCH_COST (optimize_insn_for_speed_p (), false) <= 2)
15201 return 0; /* FAIL */
15203 /* If one of the two operands is an interesting constant, load a
15204 constant with the above and mask it in with a logical operation. */
15206 if (CONST_INT_P (operands[2]))
15209 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
15210 operands[3] = constm1_rtx, op = and_optab;
15211 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
15212 operands[3] = const0_rtx, op = ior_optab;
15214 return 0; /* FAIL */
15216 else if (CONST_INT_P (operands[3]))
15219 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
15220 operands[2] = constm1_rtx, op = and_optab;
15221 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
15222 operands[2] = const0_rtx, op = ior_optab;
15224 return 0; /* FAIL */
15227 return 0; /* FAIL */
15229 orig_out = operands[0];
15230 tmp = gen_reg_rtx (mode);
15233 /* Recurse to get the constant loaded. */
15234 if (ix86_expand_int_movcc (operands) == 0)
15235 return 0; /* FAIL */
15237 /* Mask in the interesting variable. */
15238 out = expand_binop (mode, op, var, tmp, orig_out, 0,
15240 if (!rtx_equal_p (out, orig_out))
15241 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
15243 return 1; /* DONE */
15247 * For comparison with above,
15257 if (! nonimmediate_operand (operands[2], mode))
15258 operands[2] = force_reg (mode, operands[2]);
15259 if (! nonimmediate_operand (operands[3], mode))
15260 operands[3] = force_reg (mode, operands[3]);
15262 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
15264 rtx tmp = gen_reg_rtx (mode);
15265 emit_move_insn (tmp, operands[3]);
15268 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
15270 rtx tmp = gen_reg_rtx (mode);
15271 emit_move_insn (tmp, operands[2]);
15275 if (! register_operand (operands[2], VOIDmode)
15277 || ! register_operand (operands[3], VOIDmode)))
15278 operands[2] = force_reg (mode, operands[2]);
15281 && ! register_operand (operands[3], VOIDmode))
15282 operands[3] = force_reg (mode, operands[3]);
15284 emit_insn (compare_seq);
15285 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15286 gen_rtx_IF_THEN_ELSE (mode,
15287 compare_op, operands[2],
15290 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
15291 gen_rtx_IF_THEN_ELSE (mode,
15293 copy_rtx (operands[3]),
15294 copy_rtx (operands[0]))));
15296 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
15297 gen_rtx_IF_THEN_ELSE (mode,
15299 copy_rtx (operands[2]),
15300 copy_rtx (operands[0]))));
15302 return 1; /* DONE */
15305 /* Swap, force into registers, or otherwise massage the two operands
15306 to an sse comparison with a mask result. Thus we differ a bit from
15307 ix86_prepare_fp_compare_args which expects to produce a flags result.
15309 The DEST operand exists to help determine whether to commute commutative
15310 operators. The POP0/POP1 operands are updated in place. The new
15311 comparison code is returned, or UNKNOWN if not implementable. */
15313 static enum rtx_code
15314 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
15315 rtx *pop0, rtx *pop1)
15323 /* We have no LTGT as an operator. We could implement it with
15324 NE & ORDERED, but this requires an extra temporary. It's
15325 not clear that it's worth it. */
15332 /* These are supported directly. */
15339 /* For commutative operators, try to canonicalize the destination
15340 operand to be first in the comparison - this helps reload to
15341 avoid extra moves. */
15342 if (!dest || !rtx_equal_p (dest, *pop1))
15350 /* These are not supported directly. Swap the comparison operands
15351 to transform into something that is supported. */
15355 code = swap_condition (code);
15359 gcc_unreachable ();
15365 /* Detect conditional moves that exactly match min/max operational
15366 semantics. Note that this is IEEE safe, as long as we don't
15367 interchange the operands.
15369 Returns FALSE if this conditional move doesn't match a MIN/MAX,
15370 and TRUE if the operation is successful and instructions are emitted. */
15373 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
15374 rtx cmp_op1, rtx if_true, rtx if_false)
15376 enum machine_mode mode;
15382 else if (code == UNGE)
15385 if_true = if_false;
15391 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
15393 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
15398 mode = GET_MODE (dest);
15400 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
15401 but MODE may be a vector mode and thus not appropriate. */
15402 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
15404 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
15407 if_true = force_reg (mode, if_true);
15408 v = gen_rtvec (2, if_true, if_false);
15409 tmp = gen_rtx_UNSPEC (mode, v, u);
15413 code = is_min ? SMIN : SMAX;
15414 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
15417 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
15421 /* Expand an sse vector comparison. Return the register with the result. */
15424 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
15425 rtx op_true, rtx op_false)
15427 enum machine_mode mode = GET_MODE (dest);
15430 cmp_op0 = force_reg (mode, cmp_op0);
15431 if (!nonimmediate_operand (cmp_op1, mode))
15432 cmp_op1 = force_reg (mode, cmp_op1);
15435 || reg_overlap_mentioned_p (dest, op_true)
15436 || reg_overlap_mentioned_p (dest, op_false))
15437 dest = gen_reg_rtx (mode);
15439 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
15440 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15445 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
15446 operations. This is used for both scalar and vector conditional moves. */
15449 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
15451 enum machine_mode mode = GET_MODE (dest);
15454 if (op_false == CONST0_RTX (mode))
15456 op_true = force_reg (mode, op_true);
15457 x = gen_rtx_AND (mode, cmp, op_true);
15458 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15460 else if (op_true == CONST0_RTX (mode))
15462 op_false = force_reg (mode, op_false);
15463 x = gen_rtx_NOT (mode, cmp);
15464 x = gen_rtx_AND (mode, x, op_false);
15465 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15467 else if (TARGET_SSE5)
15469 rtx pcmov = gen_rtx_SET (mode, dest,
15470 gen_rtx_IF_THEN_ELSE (mode, cmp,
15477 op_true = force_reg (mode, op_true);
15478 op_false = force_reg (mode, op_false);
15480 t2 = gen_reg_rtx (mode);
15482 t3 = gen_reg_rtx (mode);
15486 x = gen_rtx_AND (mode, op_true, cmp);
15487 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
15489 x = gen_rtx_NOT (mode, cmp);
15490 x = gen_rtx_AND (mode, x, op_false);
15491 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
15493 x = gen_rtx_IOR (mode, t3, t2);
15494 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15498 /* Expand a floating-point conditional move. Return true if successful. */
15501 ix86_expand_fp_movcc (rtx operands[])
15503 enum machine_mode mode = GET_MODE (operands[0]);
15504 enum rtx_code code = GET_CODE (operands[1]);
15505 rtx tmp, compare_op, second_test, bypass_test;
15507 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
15509 enum machine_mode cmode;
15511 /* Since we've no cmove for sse registers, don't force bad register
15512 allocation just to gain access to it. Deny movcc when the
15513 comparison mode doesn't match the move mode. */
15514 cmode = GET_MODE (ix86_compare_op0);
15515 if (cmode == VOIDmode)
15516 cmode = GET_MODE (ix86_compare_op1);
15520 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15522 &ix86_compare_op1);
15523 if (code == UNKNOWN)
15526 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
15527 ix86_compare_op1, operands[2],
15531 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
15532 ix86_compare_op1, operands[2], operands[3]);
15533 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
15537 /* The floating point conditional move instructions don't directly
15538 support conditions resulting from a signed integer comparison. */
15540 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
15542 /* The floating point conditional move instructions don't directly
15543 support signed integer comparisons. */
15545 if (!fcmov_comparison_operator (compare_op, VOIDmode))
15547 gcc_assert (!second_test && !bypass_test);
15548 tmp = gen_reg_rtx (QImode);
15549 ix86_expand_setcc (code, tmp);
15551 ix86_compare_op0 = tmp;
15552 ix86_compare_op1 = const0_rtx;
15553 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
15555 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
15557 tmp = gen_reg_rtx (mode);
15558 emit_move_insn (tmp, operands[3]);
15561 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
15563 tmp = gen_reg_rtx (mode);
15564 emit_move_insn (tmp, operands[2]);
15568 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15569 gen_rtx_IF_THEN_ELSE (mode, compare_op,
15570 operands[2], operands[3])));
15572 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15573 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
15574 operands[3], operands[0])));
15576 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15577 gen_rtx_IF_THEN_ELSE (mode, second_test,
15578 operands[2], operands[0])));
15583 /* Expand a floating-point vector conditional move; a vcond operation
15584 rather than a movcc operation. */
15587 ix86_expand_fp_vcond (rtx operands[])
15589 enum rtx_code code = GET_CODE (operands[3]);
15592 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15593 &operands[4], &operands[5]);
15594 if (code == UNKNOWN)
15597 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
15598 operands[5], operands[1], operands[2]))
15601 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
15602 operands[1], operands[2]);
15603 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
15607 /* Expand a signed/unsigned integral vector conditional move. */
15610 ix86_expand_int_vcond (rtx operands[])
15612 enum machine_mode mode = GET_MODE (operands[0]);
15613 enum rtx_code code = GET_CODE (operands[3]);
15614 bool negate = false;
15617 cop0 = operands[4];
15618 cop1 = operands[5];
15620 /* SSE5 supports all of the comparisons on all vector int types. */
15623 /* Canonicalize the comparison to EQ, GT, GTU. */
15634 code = reverse_condition (code);
15640 code = reverse_condition (code);
15646 code = swap_condition (code);
15647 x = cop0, cop0 = cop1, cop1 = x;
15651 gcc_unreachable ();
15654 /* Only SSE4.1/SSE4.2 supports V2DImode. */
15655 if (mode == V2DImode)
15660 /* SSE4.1 supports EQ. */
15661 if (!TARGET_SSE4_1)
15667 /* SSE4.2 supports GT/GTU. */
15668 if (!TARGET_SSE4_2)
15673 gcc_unreachable ();
15677 /* Unsigned parallel compare is not supported by the hardware. Play some
15678 tricks to turn this into a signed comparison against 0. */
15681 cop0 = force_reg (mode, cop0);
15690 /* Perform a parallel modulo subtraction. */
15691 t1 = gen_reg_rtx (mode);
15692 emit_insn ((mode == V4SImode
15694 : gen_subv2di3) (t1, cop0, cop1));
15696 /* Extract the original sign bit of op0. */
15697 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
15699 t2 = gen_reg_rtx (mode);
15700 emit_insn ((mode == V4SImode
15702 : gen_andv2di3) (t2, cop0, mask));
15704 /* XOR it back into the result of the subtraction. This results
15705 in the sign bit set iff we saw unsigned underflow. */
15706 x = gen_reg_rtx (mode);
15707 emit_insn ((mode == V4SImode
15709 : gen_xorv2di3) (x, t1, t2));
15717 /* Perform a parallel unsigned saturating subtraction. */
15718 x = gen_reg_rtx (mode);
15719 emit_insn (gen_rtx_SET (VOIDmode, x,
15720 gen_rtx_US_MINUS (mode, cop0, cop1)));
15727 gcc_unreachable ();
15731 cop1 = CONST0_RTX (mode);
15735 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
15736 operands[1+negate], operands[2-negate]);
15738 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
15739 operands[2-negate]);
15743 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
15744 true if we should do zero extension, else sign extension. HIGH_P is
15745 true if we want the N/2 high elements, else the low elements. */
15748 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15750 enum machine_mode imode = GET_MODE (operands[1]);
15751 rtx (*unpack)(rtx, rtx, rtx);
15758 unpack = gen_vec_interleave_highv16qi;
15760 unpack = gen_vec_interleave_lowv16qi;
15764 unpack = gen_vec_interleave_highv8hi;
15766 unpack = gen_vec_interleave_lowv8hi;
15770 unpack = gen_vec_interleave_highv4si;
15772 unpack = gen_vec_interleave_lowv4si;
15775 gcc_unreachable ();
15778 dest = gen_lowpart (imode, operands[0]);
15781 se = force_reg (imode, CONST0_RTX (imode));
15783 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
15784 operands[1], pc_rtx, pc_rtx);
15786 emit_insn (unpack (dest, operands[1], se));
15789 /* This function performs the same task as ix86_expand_sse_unpack,
15790 but with SSE4.1 instructions. */
15793 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15795 enum machine_mode imode = GET_MODE (operands[1]);
15796 rtx (*unpack)(rtx, rtx);
15803 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
15805 unpack = gen_sse4_1_extendv8qiv8hi2;
15809 unpack = gen_sse4_1_zero_extendv4hiv4si2;
15811 unpack = gen_sse4_1_extendv4hiv4si2;
15815 unpack = gen_sse4_1_zero_extendv2siv2di2;
15817 unpack = gen_sse4_1_extendv2siv2di2;
15820 gcc_unreachable ();
15823 dest = operands[0];
15826 /* Shift higher 8 bytes to lower 8 bytes. */
15827 src = gen_reg_rtx (imode);
15828 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
15829 gen_lowpart (TImode, operands[1]),
15835 emit_insn (unpack (dest, src));
15838 /* This function performs the same task as ix86_expand_sse_unpack,
15839 but with sse5 instructions. */
15842 ix86_expand_sse5_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15844 enum machine_mode imode = GET_MODE (operands[1]);
15845 int pperm_bytes[16];
15847 int h = (high_p) ? 8 : 0;
15850 rtvec v = rtvec_alloc (16);
15853 rtx op0 = operands[0], op1 = operands[1];
15858 vs = rtvec_alloc (8);
15859 h2 = (high_p) ? 8 : 0;
15860 for (i = 0; i < 8; i++)
15862 pperm_bytes[2*i+0] = PPERM_SRC | PPERM_SRC2 | i | h;
15863 pperm_bytes[2*i+1] = ((unsigned_p)
15865 : PPERM_SIGN | PPERM_SRC2 | i | h);
15868 for (i = 0; i < 16; i++)
15869 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15871 for (i = 0; i < 8; i++)
15872 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15874 p = gen_rtx_PARALLEL (VOIDmode, vs);
15875 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15877 emit_insn (gen_sse5_pperm_zero_v16qi_v8hi (op0, op1, p, x));
15879 emit_insn (gen_sse5_pperm_sign_v16qi_v8hi (op0, op1, p, x));
15883 vs = rtvec_alloc (4);
15884 h2 = (high_p) ? 4 : 0;
15885 for (i = 0; i < 4; i++)
15887 sign_extend = ((unsigned_p)
15889 : PPERM_SIGN | PPERM_SRC2 | ((2*i) + 1 + h));
15890 pperm_bytes[4*i+0] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 0 + h);
15891 pperm_bytes[4*i+1] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 1 + h);
15892 pperm_bytes[4*i+2] = sign_extend;
15893 pperm_bytes[4*i+3] = sign_extend;
15896 for (i = 0; i < 16; i++)
15897 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15899 for (i = 0; i < 4; i++)
15900 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15902 p = gen_rtx_PARALLEL (VOIDmode, vs);
15903 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15905 emit_insn (gen_sse5_pperm_zero_v8hi_v4si (op0, op1, p, x));
15907 emit_insn (gen_sse5_pperm_sign_v8hi_v4si (op0, op1, p, x));
15911 vs = rtvec_alloc (2);
15912 h2 = (high_p) ? 2 : 0;
15913 for (i = 0; i < 2; i++)
15915 sign_extend = ((unsigned_p)
15917 : PPERM_SIGN | PPERM_SRC2 | ((4*i) + 3 + h));
15918 pperm_bytes[8*i+0] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 0 + h);
15919 pperm_bytes[8*i+1] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 1 + h);
15920 pperm_bytes[8*i+2] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 2 + h);
15921 pperm_bytes[8*i+3] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 3 + h);
15922 pperm_bytes[8*i+4] = sign_extend;
15923 pperm_bytes[8*i+5] = sign_extend;
15924 pperm_bytes[8*i+6] = sign_extend;
15925 pperm_bytes[8*i+7] = sign_extend;
15928 for (i = 0; i < 16; i++)
15929 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15931 for (i = 0; i < 2; i++)
15932 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15934 p = gen_rtx_PARALLEL (VOIDmode, vs);
15935 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15937 emit_insn (gen_sse5_pperm_zero_v4si_v2di (op0, op1, p, x));
15939 emit_insn (gen_sse5_pperm_sign_v4si_v2di (op0, op1, p, x));
15943 gcc_unreachable ();
15949 /* Pack the high bits from OPERANDS[1] and low bits from OPERANDS[2] into the
15950 next narrower integer vector type */
15952 ix86_expand_sse5_pack (rtx operands[3])
15954 enum machine_mode imode = GET_MODE (operands[0]);
15955 int pperm_bytes[16];
15957 rtvec v = rtvec_alloc (16);
15959 rtx op0 = operands[0];
15960 rtx op1 = operands[1];
15961 rtx op2 = operands[2];
15966 for (i = 0; i < 8; i++)
15968 pperm_bytes[i+0] = PPERM_SRC | PPERM_SRC1 | (i*2);
15969 pperm_bytes[i+8] = PPERM_SRC | PPERM_SRC2 | (i*2);
15972 for (i = 0; i < 16; i++)
15973 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15975 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15976 emit_insn (gen_sse5_pperm_pack_v8hi_v16qi (op0, op1, op2, x));
15980 for (i = 0; i < 4; i++)
15982 pperm_bytes[(2*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 0);
15983 pperm_bytes[(2*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 1);
15984 pperm_bytes[(2*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 0);
15985 pperm_bytes[(2*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 1);
15988 for (i = 0; i < 16; i++)
15989 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15991 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15992 emit_insn (gen_sse5_pperm_pack_v4si_v8hi (op0, op1, op2, x));
15996 for (i = 0; i < 2; i++)
15998 pperm_bytes[(4*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 0);
15999 pperm_bytes[(4*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 1);
16000 pperm_bytes[(4*i)+2] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 2);
16001 pperm_bytes[(4*i)+3] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 3);
16002 pperm_bytes[(4*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 0);
16003 pperm_bytes[(4*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 1);
16004 pperm_bytes[(4*i)+10] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 2);
16005 pperm_bytes[(4*i)+11] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 3);
16008 for (i = 0; i < 16; i++)
16009 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
16011 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
16012 emit_insn (gen_sse5_pperm_pack_v2di_v4si (op0, op1, op2, x));
16016 gcc_unreachable ();
16022 /* Expand conditional increment or decrement using adb/sbb instructions.
16023 The default case using setcc followed by the conditional move can be
16024 done by generic code. */
16026 ix86_expand_int_addcc (rtx operands[])
16028 enum rtx_code code = GET_CODE (operands[1]);
16030 rtx val = const0_rtx;
16031 bool fpcmp = false;
16032 enum machine_mode mode = GET_MODE (operands[0]);
16034 if (operands[3] != const1_rtx
16035 && operands[3] != constm1_rtx)
16037 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
16038 ix86_compare_op1, &compare_op))
16040 code = GET_CODE (compare_op);
16042 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
16043 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
16046 code = ix86_fp_compare_code_to_integer (code);
16053 PUT_CODE (compare_op,
16054 reverse_condition_maybe_unordered
16055 (GET_CODE (compare_op)));
16057 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
16059 PUT_MODE (compare_op, mode);
16061 /* Construct either adc or sbb insn. */
16062 if ((code == LTU) == (operands[3] == constm1_rtx))
16064 switch (GET_MODE (operands[0]))
16067 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
16070 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
16073 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
16076 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
16079 gcc_unreachable ();
16084 switch (GET_MODE (operands[0]))
16087 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
16090 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
16093 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
16096 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
16099 gcc_unreachable ();
16102 return 1; /* DONE */
16106 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
16107 works for floating pointer parameters and nonoffsetable memories.
16108 For pushes, it returns just stack offsets; the values will be saved
16109 in the right order. Maximally three parts are generated. */
16112 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
16117 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
16119 size = (GET_MODE_SIZE (mode) + 4) / 8;
16121 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
16122 gcc_assert (size >= 2 && size <= 4);
16124 /* Optimize constant pool reference to immediates. This is used by fp
16125 moves, that force all constants to memory to allow combining. */
16126 if (MEM_P (operand) && MEM_READONLY_P (operand))
16128 rtx tmp = maybe_get_pool_constant (operand);
16133 if (MEM_P (operand) && !offsettable_memref_p (operand))
16135 /* The only non-offsetable memories we handle are pushes. */
16136 int ok = push_operand (operand, VOIDmode);
16140 operand = copy_rtx (operand);
16141 PUT_MODE (operand, Pmode);
16142 parts[0] = parts[1] = parts[2] = parts[3] = operand;
16146 if (GET_CODE (operand) == CONST_VECTOR)
16148 enum machine_mode imode = int_mode_for_mode (mode);
16149 /* Caution: if we looked through a constant pool memory above,
16150 the operand may actually have a different mode now. That's
16151 ok, since we want to pun this all the way back to an integer. */
16152 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
16153 gcc_assert (operand != NULL);
16159 if (mode == DImode)
16160 split_di (&operand, 1, &parts[0], &parts[1]);
16165 if (REG_P (operand))
16167 gcc_assert (reload_completed);
16168 for (i = 0; i < size; i++)
16169 parts[i] = gen_rtx_REG (SImode, REGNO (operand) + i);
16171 else if (offsettable_memref_p (operand))
16173 operand = adjust_address (operand, SImode, 0);
16174 parts[0] = operand;
16175 for (i = 1; i < size; i++)
16176 parts[i] = adjust_address (operand, SImode, 4 * i);
16178 else if (GET_CODE (operand) == CONST_DOUBLE)
16183 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16187 real_to_target (l, &r, mode);
16188 parts[3] = gen_int_mode (l[3], SImode);
16189 parts[2] = gen_int_mode (l[2], SImode);
16192 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
16193 parts[2] = gen_int_mode (l[2], SImode);
16196 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
16199 gcc_unreachable ();
16201 parts[1] = gen_int_mode (l[1], SImode);
16202 parts[0] = gen_int_mode (l[0], SImode);
16205 gcc_unreachable ();
16210 if (mode == TImode)
16211 split_ti (&operand, 1, &parts[0], &parts[1]);
16212 if (mode == XFmode || mode == TFmode)
16214 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
16215 if (REG_P (operand))
16217 gcc_assert (reload_completed);
16218 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
16219 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
16221 else if (offsettable_memref_p (operand))
16223 operand = adjust_address (operand, DImode, 0);
16224 parts[0] = operand;
16225 parts[1] = adjust_address (operand, upper_mode, 8);
16227 else if (GET_CODE (operand) == CONST_DOUBLE)
16232 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16233 real_to_target (l, &r, mode);
16235 /* Do not use shift by 32 to avoid warning on 32bit systems. */
16236 if (HOST_BITS_PER_WIDE_INT >= 64)
16239 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
16240 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
16243 parts[0] = immed_double_const (l[0], l[1], DImode);
16245 if (upper_mode == SImode)
16246 parts[1] = gen_int_mode (l[2], SImode);
16247 else if (HOST_BITS_PER_WIDE_INT >= 64)
16250 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
16251 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
16254 parts[1] = immed_double_const (l[2], l[3], DImode);
16257 gcc_unreachable ();
16264 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
16265 Return false when normal moves are needed; true when all required
16266 insns have been emitted. Operands 2-4 contain the input values
16267 int the correct order; operands 5-7 contain the output values. */
16270 ix86_split_long_move (rtx operands[])
16275 int collisions = 0;
16276 enum machine_mode mode = GET_MODE (operands[0]);
16277 bool collisionparts[4];
16279 /* The DFmode expanders may ask us to move double.
16280 For 64bit target this is single move. By hiding the fact
16281 here we simplify i386.md splitters. */
16282 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
16284 /* Optimize constant pool reference to immediates. This is used by
16285 fp moves, that force all constants to memory to allow combining. */
16287 if (MEM_P (operands[1])
16288 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
16289 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
16290 operands[1] = get_pool_constant (XEXP (operands[1], 0));
16291 if (push_operand (operands[0], VOIDmode))
16293 operands[0] = copy_rtx (operands[0]);
16294 PUT_MODE (operands[0], Pmode);
16297 operands[0] = gen_lowpart (DImode, operands[0]);
16298 operands[1] = gen_lowpart (DImode, operands[1]);
16299 emit_move_insn (operands[0], operands[1]);
16303 /* The only non-offsettable memory we handle is push. */
16304 if (push_operand (operands[0], VOIDmode))
16307 gcc_assert (!MEM_P (operands[0])
16308 || offsettable_memref_p (operands[0]));
16310 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
16311 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
16313 /* When emitting push, take care for source operands on the stack. */
16314 if (push && MEM_P (operands[1])
16315 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
16317 rtx src_base = XEXP (part[1][nparts - 1], 0);
16319 /* Compensate for the stack decrement by 4. */
16320 if (!TARGET_64BIT && nparts == 3
16321 && mode == XFmode && TARGET_128BIT_LONG_DOUBLE)
16322 src_base = plus_constant (src_base, 4);
16324 /* src_base refers to the stack pointer and is
16325 automatically decreased by emitted push. */
16326 for (i = 0; i < nparts; i++)
16327 part[1][i] = change_address (part[1][i],
16328 GET_MODE (part[1][i]), src_base);
16331 /* We need to do copy in the right order in case an address register
16332 of the source overlaps the destination. */
16333 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
16337 for (i = 0; i < nparts; i++)
16340 = reg_overlap_mentioned_p (part[0][i], XEXP (part[1][0], 0));
16341 if (collisionparts[i])
16345 /* Collision in the middle part can be handled by reordering. */
16346 if (collisions == 1 && nparts == 3 && collisionparts [1])
16348 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16349 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16351 else if (collisions == 1
16353 && (collisionparts [1] || collisionparts [2]))
16355 if (collisionparts [1])
16357 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16358 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16362 tmp = part[0][2]; part[0][2] = part[0][3]; part[0][3] = tmp;
16363 tmp = part[1][2]; part[1][2] = part[1][3]; part[1][3] = tmp;
16367 /* If there are more collisions, we can't handle it by reordering.
16368 Do an lea to the last part and use only one colliding move. */
16369 else if (collisions > 1)
16375 base = part[0][nparts - 1];
16377 /* Handle the case when the last part isn't valid for lea.
16378 Happens in 64-bit mode storing the 12-byte XFmode. */
16379 if (GET_MODE (base) != Pmode)
16380 base = gen_rtx_REG (Pmode, REGNO (base));
16382 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
16383 part[1][0] = replace_equiv_address (part[1][0], base);
16384 for (i = 1; i < nparts; i++)
16386 tmp = plus_constant (base, UNITS_PER_WORD * i);
16387 part[1][i] = replace_equiv_address (part[1][i], tmp);
16398 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
16399 emit_insn (gen_addsi3 (stack_pointer_rtx,
16400 stack_pointer_rtx, GEN_INT (-4)));
16401 emit_move_insn (part[0][2], part[1][2]);
16403 else if (nparts == 4)
16405 emit_move_insn (part[0][3], part[1][3]);
16406 emit_move_insn (part[0][2], part[1][2]);
16411 /* In 64bit mode we don't have 32bit push available. In case this is
16412 register, it is OK - we will just use larger counterpart. We also
16413 retype memory - these comes from attempt to avoid REX prefix on
16414 moving of second half of TFmode value. */
16415 if (GET_MODE (part[1][1]) == SImode)
16417 switch (GET_CODE (part[1][1]))
16420 part[1][1] = adjust_address (part[1][1], DImode, 0);
16424 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
16428 gcc_unreachable ();
16431 if (GET_MODE (part[1][0]) == SImode)
16432 part[1][0] = part[1][1];
16435 emit_move_insn (part[0][1], part[1][1]);
16436 emit_move_insn (part[0][0], part[1][0]);
16440 /* Choose correct order to not overwrite the source before it is copied. */
16441 if ((REG_P (part[0][0])
16442 && REG_P (part[1][1])
16443 && (REGNO (part[0][0]) == REGNO (part[1][1])
16445 && REGNO (part[0][0]) == REGNO (part[1][2]))
16447 && REGNO (part[0][0]) == REGNO (part[1][3]))))
16449 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
16451 for (i = 0, j = nparts - 1; i < nparts; i++, j--)
16453 operands[2 + i] = part[0][j];
16454 operands[6 + i] = part[1][j];
16459 for (i = 0; i < nparts; i++)
16461 operands[2 + i] = part[0][i];
16462 operands[6 + i] = part[1][i];
16466 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
16467 if (optimize_insn_for_size_p ())
16469 for (j = 0; j < nparts - 1; j++)
16470 if (CONST_INT_P (operands[6 + j])
16471 && operands[6 + j] != const0_rtx
16472 && REG_P (operands[2 + j]))
16473 for (i = j; i < nparts - 1; i++)
16474 if (CONST_INT_P (operands[7 + i])
16475 && INTVAL (operands[7 + i]) == INTVAL (operands[6 + j]))
16476 operands[7 + i] = operands[2 + j];
16479 for (i = 0; i < nparts; i++)
16480 emit_move_insn (operands[2 + i], operands[6 + i]);
16485 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
16486 left shift by a constant, either using a single shift or
16487 a sequence of add instructions. */
16490 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
16494 emit_insn ((mode == DImode
16496 : gen_adddi3) (operand, operand, operand));
16498 else if (!optimize_insn_for_size_p ()
16499 && count * ix86_cost->add <= ix86_cost->shift_const)
16502 for (i=0; i<count; i++)
16504 emit_insn ((mode == DImode
16506 : gen_adddi3) (operand, operand, operand));
16510 emit_insn ((mode == DImode
16512 : gen_ashldi3) (operand, operand, GEN_INT (count)));
16516 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
16518 rtx low[2], high[2];
16520 const int single_width = mode == DImode ? 32 : 64;
16522 if (CONST_INT_P (operands[2]))
16524 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16525 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16527 if (count >= single_width)
16529 emit_move_insn (high[0], low[1]);
16530 emit_move_insn (low[0], const0_rtx);
16532 if (count > single_width)
16533 ix86_expand_ashl_const (high[0], count - single_width, mode);
16537 if (!rtx_equal_p (operands[0], operands[1]))
16538 emit_move_insn (operands[0], operands[1]);
16539 emit_insn ((mode == DImode
16541 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
16542 ix86_expand_ashl_const (low[0], count, mode);
16547 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16549 if (operands[1] == const1_rtx)
16551 /* Assuming we've chosen a QImode capable registers, then 1 << N
16552 can be done with two 32/64-bit shifts, no branches, no cmoves. */
16553 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
16555 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
16557 ix86_expand_clear (low[0]);
16558 ix86_expand_clear (high[0]);
16559 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
16561 d = gen_lowpart (QImode, low[0]);
16562 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16563 s = gen_rtx_EQ (QImode, flags, const0_rtx);
16564 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16566 d = gen_lowpart (QImode, high[0]);
16567 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16568 s = gen_rtx_NE (QImode, flags, const0_rtx);
16569 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16572 /* Otherwise, we can get the same results by manually performing
16573 a bit extract operation on bit 5/6, and then performing the two
16574 shifts. The two methods of getting 0/1 into low/high are exactly
16575 the same size. Avoiding the shift in the bit extract case helps
16576 pentium4 a bit; no one else seems to care much either way. */
16581 if (TARGET_PARTIAL_REG_STALL && !optimize_insn_for_size_p ())
16582 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
16584 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
16585 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
16587 emit_insn ((mode == DImode
16589 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
16590 emit_insn ((mode == DImode
16592 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
16593 emit_move_insn (low[0], high[0]);
16594 emit_insn ((mode == DImode
16596 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
16599 emit_insn ((mode == DImode
16601 : gen_ashldi3) (low[0], low[0], operands[2]));
16602 emit_insn ((mode == DImode
16604 : gen_ashldi3) (high[0], high[0], operands[2]));
16608 if (operands[1] == constm1_rtx)
16610 /* For -1 << N, we can avoid the shld instruction, because we
16611 know that we're shifting 0...31/63 ones into a -1. */
16612 emit_move_insn (low[0], constm1_rtx);
16613 if (optimize_insn_for_size_p ())
16614 emit_move_insn (high[0], low[0]);
16616 emit_move_insn (high[0], constm1_rtx);
16620 if (!rtx_equal_p (operands[0], operands[1]))
16621 emit_move_insn (operands[0], operands[1]);
16623 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16624 emit_insn ((mode == DImode
16626 : gen_x86_64_shld) (high[0], low[0], operands[2]));
16629 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
16631 if (TARGET_CMOVE && scratch)
16633 ix86_expand_clear (scratch);
16634 emit_insn ((mode == DImode
16635 ? gen_x86_shift_adj_1
16636 : gen_x86_64_shift_adj_1) (high[0], low[0], operands[2],
16640 emit_insn ((mode == DImode
16641 ? gen_x86_shift_adj_2
16642 : gen_x86_64_shift_adj_2) (high[0], low[0], operands[2]));
16646 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
16648 rtx low[2], high[2];
16650 const int single_width = mode == DImode ? 32 : 64;
16652 if (CONST_INT_P (operands[2]))
16654 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16655 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16657 if (count == single_width * 2 - 1)
16659 emit_move_insn (high[0], high[1]);
16660 emit_insn ((mode == DImode
16662 : gen_ashrdi3) (high[0], high[0],
16663 GEN_INT (single_width - 1)));
16664 emit_move_insn (low[0], high[0]);
16667 else if (count >= single_width)
16669 emit_move_insn (low[0], high[1]);
16670 emit_move_insn (high[0], low[0]);
16671 emit_insn ((mode == DImode
16673 : gen_ashrdi3) (high[0], high[0],
16674 GEN_INT (single_width - 1)));
16675 if (count > single_width)
16676 emit_insn ((mode == DImode
16678 : gen_ashrdi3) (low[0], low[0],
16679 GEN_INT (count - single_width)));
16683 if (!rtx_equal_p (operands[0], operands[1]))
16684 emit_move_insn (operands[0], operands[1]);
16685 emit_insn ((mode == DImode
16687 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16688 emit_insn ((mode == DImode
16690 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
16695 if (!rtx_equal_p (operands[0], operands[1]))
16696 emit_move_insn (operands[0], operands[1]);
16698 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16700 emit_insn ((mode == DImode
16702 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16703 emit_insn ((mode == DImode
16705 : gen_ashrdi3) (high[0], high[0], operands[2]));
16707 if (TARGET_CMOVE && scratch)
16709 emit_move_insn (scratch, high[0]);
16710 emit_insn ((mode == DImode
16712 : gen_ashrdi3) (scratch, scratch,
16713 GEN_INT (single_width - 1)));
16714 emit_insn ((mode == DImode
16715 ? gen_x86_shift_adj_1
16716 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16720 emit_insn ((mode == DImode
16721 ? gen_x86_shift_adj_3
16722 : gen_x86_64_shift_adj_3) (low[0], high[0], operands[2]));
16727 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
16729 rtx low[2], high[2];
16731 const int single_width = mode == DImode ? 32 : 64;
16733 if (CONST_INT_P (operands[2]))
16735 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16736 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16738 if (count >= single_width)
16740 emit_move_insn (low[0], high[1]);
16741 ix86_expand_clear (high[0]);
16743 if (count > single_width)
16744 emit_insn ((mode == DImode
16746 : gen_lshrdi3) (low[0], low[0],
16747 GEN_INT (count - single_width)));
16751 if (!rtx_equal_p (operands[0], operands[1]))
16752 emit_move_insn (operands[0], operands[1]);
16753 emit_insn ((mode == DImode
16755 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16756 emit_insn ((mode == DImode
16758 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
16763 if (!rtx_equal_p (operands[0], operands[1]))
16764 emit_move_insn (operands[0], operands[1]);
16766 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16768 emit_insn ((mode == DImode
16770 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16771 emit_insn ((mode == DImode
16773 : gen_lshrdi3) (high[0], high[0], operands[2]));
16775 /* Heh. By reversing the arguments, we can reuse this pattern. */
16776 if (TARGET_CMOVE && scratch)
16778 ix86_expand_clear (scratch);
16779 emit_insn ((mode == DImode
16780 ? gen_x86_shift_adj_1
16781 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16785 emit_insn ((mode == DImode
16786 ? gen_x86_shift_adj_2
16787 : gen_x86_64_shift_adj_2) (low[0], high[0], operands[2]));
16791 /* Predict just emitted jump instruction to be taken with probability PROB. */
16793 predict_jump (int prob)
16795 rtx insn = get_last_insn ();
16796 gcc_assert (JUMP_P (insn));
16798 = gen_rtx_EXPR_LIST (REG_BR_PROB,
16803 /* Helper function for the string operations below. Dest VARIABLE whether
16804 it is aligned to VALUE bytes. If true, jump to the label. */
16806 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
16808 rtx label = gen_label_rtx ();
16809 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
16810 if (GET_MODE (variable) == DImode)
16811 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
16813 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
16814 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
16817 predict_jump (REG_BR_PROB_BASE * 50 / 100);
16819 predict_jump (REG_BR_PROB_BASE * 90 / 100);
16823 /* Adjust COUNTER by the VALUE. */
16825 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
16827 if (GET_MODE (countreg) == DImode)
16828 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
16830 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
16833 /* Zero extend possibly SImode EXP to Pmode register. */
16835 ix86_zero_extend_to_Pmode (rtx exp)
16838 if (GET_MODE (exp) == VOIDmode)
16839 return force_reg (Pmode, exp);
16840 if (GET_MODE (exp) == Pmode)
16841 return copy_to_mode_reg (Pmode, exp);
16842 r = gen_reg_rtx (Pmode);
16843 emit_insn (gen_zero_extendsidi2 (r, exp));
16847 /* Divide COUNTREG by SCALE. */
16849 scale_counter (rtx countreg, int scale)
16852 rtx piece_size_mask;
16856 if (CONST_INT_P (countreg))
16857 return GEN_INT (INTVAL (countreg) / scale);
16858 gcc_assert (REG_P (countreg));
16860 piece_size_mask = GEN_INT (scale - 1);
16861 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
16862 GEN_INT (exact_log2 (scale)),
16863 NULL, 1, OPTAB_DIRECT);
16867 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
16868 DImode for constant loop counts. */
16870 static enum machine_mode
16871 counter_mode (rtx count_exp)
16873 if (GET_MODE (count_exp) != VOIDmode)
16874 return GET_MODE (count_exp);
16875 if (GET_CODE (count_exp) != CONST_INT)
16877 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
16882 /* When SRCPTR is non-NULL, output simple loop to move memory
16883 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
16884 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
16885 equivalent loop to set memory by VALUE (supposed to be in MODE).
16887 The size is rounded down to whole number of chunk size moved at once.
16888 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
16892 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
16893 rtx destptr, rtx srcptr, rtx value,
16894 rtx count, enum machine_mode mode, int unroll,
16897 rtx out_label, top_label, iter, tmp;
16898 enum machine_mode iter_mode = counter_mode (count);
16899 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
16900 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
16906 top_label = gen_label_rtx ();
16907 out_label = gen_label_rtx ();
16908 iter = gen_reg_rtx (iter_mode);
16910 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
16911 NULL, 1, OPTAB_DIRECT);
16912 /* Those two should combine. */
16913 if (piece_size == const1_rtx)
16915 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
16917 predict_jump (REG_BR_PROB_BASE * 10 / 100);
16919 emit_move_insn (iter, const0_rtx);
16921 emit_label (top_label);
16923 tmp = convert_modes (Pmode, iter_mode, iter, true);
16924 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
16925 destmem = change_address (destmem, mode, x_addr);
16929 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
16930 srcmem = change_address (srcmem, mode, y_addr);
16932 /* When unrolling for chips that reorder memory reads and writes,
16933 we can save registers by using single temporary.
16934 Also using 4 temporaries is overkill in 32bit mode. */
16935 if (!TARGET_64BIT && 0)
16937 for (i = 0; i < unroll; i++)
16942 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16944 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
16946 emit_move_insn (destmem, srcmem);
16952 gcc_assert (unroll <= 4);
16953 for (i = 0; i < unroll; i++)
16955 tmpreg[i] = gen_reg_rtx (mode);
16959 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
16961 emit_move_insn (tmpreg[i], srcmem);
16963 for (i = 0; i < unroll; i++)
16968 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16970 emit_move_insn (destmem, tmpreg[i]);
16975 for (i = 0; i < unroll; i++)
16979 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16980 emit_move_insn (destmem, value);
16983 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
16984 true, OPTAB_LIB_WIDEN);
16986 emit_move_insn (iter, tmp);
16988 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
16990 if (expected_size != -1)
16992 expected_size /= GET_MODE_SIZE (mode) * unroll;
16993 if (expected_size == 0)
16995 else if (expected_size > REG_BR_PROB_BASE)
16996 predict_jump (REG_BR_PROB_BASE - 1);
16998 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
17001 predict_jump (REG_BR_PROB_BASE * 80 / 100);
17002 iter = ix86_zero_extend_to_Pmode (iter);
17003 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
17004 true, OPTAB_LIB_WIDEN);
17005 if (tmp != destptr)
17006 emit_move_insn (destptr, tmp);
17009 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
17010 true, OPTAB_LIB_WIDEN);
17012 emit_move_insn (srcptr, tmp);
17014 emit_label (out_label);
17017 /* Output "rep; mov" instruction.
17018 Arguments have same meaning as for previous function */
17020 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
17021 rtx destptr, rtx srcptr,
17023 enum machine_mode mode)
17029 /* If the size is known, it is shorter to use rep movs. */
17030 if (mode == QImode && CONST_INT_P (count)
17031 && !(INTVAL (count) & 3))
17034 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17035 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17036 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
17037 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
17038 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17039 if (mode != QImode)
17041 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17042 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17043 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17044 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
17045 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17046 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
17050 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17051 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
17053 if (CONST_INT_P (count))
17055 count = GEN_INT (INTVAL (count)
17056 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17057 destmem = shallow_copy_rtx (destmem);
17058 srcmem = shallow_copy_rtx (srcmem);
17059 set_mem_size (destmem, count);
17060 set_mem_size (srcmem, count);
17064 if (MEM_SIZE (destmem))
17065 set_mem_size (destmem, NULL_RTX);
17066 if (MEM_SIZE (srcmem))
17067 set_mem_size (srcmem, NULL_RTX);
17069 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
17073 /* Output "rep; stos" instruction.
17074 Arguments have same meaning as for previous function */
17076 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
17077 rtx count, enum machine_mode mode,
17083 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17084 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17085 value = force_reg (mode, gen_lowpart (mode, value));
17086 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17087 if (mode != QImode)
17089 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17090 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17091 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17094 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17095 if (orig_value == const0_rtx && CONST_INT_P (count))
17097 count = GEN_INT (INTVAL (count)
17098 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17099 destmem = shallow_copy_rtx (destmem);
17100 set_mem_size (destmem, count);
17102 else if (MEM_SIZE (destmem))
17103 set_mem_size (destmem, NULL_RTX);
17104 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
17108 emit_strmov (rtx destmem, rtx srcmem,
17109 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
17111 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
17112 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
17113 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17116 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
17118 expand_movmem_epilogue (rtx destmem, rtx srcmem,
17119 rtx destptr, rtx srcptr, rtx count, int max_size)
17122 if (CONST_INT_P (count))
17124 HOST_WIDE_INT countval = INTVAL (count);
17127 if ((countval & 0x10) && max_size > 16)
17131 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17132 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
17135 gcc_unreachable ();
17138 if ((countval & 0x08) && max_size > 8)
17141 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17144 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17145 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
17149 if ((countval & 0x04) && max_size > 4)
17151 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17154 if ((countval & 0x02) && max_size > 2)
17156 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
17159 if ((countval & 0x01) && max_size > 1)
17161 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
17168 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
17169 count, 1, OPTAB_DIRECT);
17170 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
17171 count, QImode, 1, 4);
17175 /* When there are stringops, we can cheaply increase dest and src pointers.
17176 Otherwise we save code size by maintaining offset (zero is readily
17177 available from preceding rep operation) and using x86 addressing modes.
17179 if (TARGET_SINGLE_STRINGOP)
17183 rtx label = ix86_expand_aligntest (count, 4, true);
17184 src = change_address (srcmem, SImode, srcptr);
17185 dest = change_address (destmem, SImode, destptr);
17186 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17187 emit_label (label);
17188 LABEL_NUSES (label) = 1;
17192 rtx label = ix86_expand_aligntest (count, 2, true);
17193 src = change_address (srcmem, HImode, srcptr);
17194 dest = change_address (destmem, HImode, destptr);
17195 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17196 emit_label (label);
17197 LABEL_NUSES (label) = 1;
17201 rtx label = ix86_expand_aligntest (count, 1, true);
17202 src = change_address (srcmem, QImode, srcptr);
17203 dest = change_address (destmem, QImode, destptr);
17204 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17205 emit_label (label);
17206 LABEL_NUSES (label) = 1;
17211 rtx offset = force_reg (Pmode, const0_rtx);
17216 rtx label = ix86_expand_aligntest (count, 4, true);
17217 src = change_address (srcmem, SImode, srcptr);
17218 dest = change_address (destmem, SImode, destptr);
17219 emit_move_insn (dest, src);
17220 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
17221 true, OPTAB_LIB_WIDEN);
17223 emit_move_insn (offset, tmp);
17224 emit_label (label);
17225 LABEL_NUSES (label) = 1;
17229 rtx label = ix86_expand_aligntest (count, 2, true);
17230 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17231 src = change_address (srcmem, HImode, tmp);
17232 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17233 dest = change_address (destmem, HImode, tmp);
17234 emit_move_insn (dest, src);
17235 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
17236 true, OPTAB_LIB_WIDEN);
17238 emit_move_insn (offset, tmp);
17239 emit_label (label);
17240 LABEL_NUSES (label) = 1;
17244 rtx label = ix86_expand_aligntest (count, 1, true);
17245 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17246 src = change_address (srcmem, QImode, tmp);
17247 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17248 dest = change_address (destmem, QImode, tmp);
17249 emit_move_insn (dest, src);
17250 emit_label (label);
17251 LABEL_NUSES (label) = 1;
17256 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17258 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
17259 rtx count, int max_size)
17262 expand_simple_binop (counter_mode (count), AND, count,
17263 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
17264 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
17265 gen_lowpart (QImode, value), count, QImode,
17269 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17271 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
17275 if (CONST_INT_P (count))
17277 HOST_WIDE_INT countval = INTVAL (count);
17280 if ((countval & 0x10) && max_size > 16)
17284 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17285 emit_insn (gen_strset (destptr, dest, value));
17286 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
17287 emit_insn (gen_strset (destptr, dest, value));
17290 gcc_unreachable ();
17293 if ((countval & 0x08) && max_size > 8)
17297 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17298 emit_insn (gen_strset (destptr, dest, value));
17302 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17303 emit_insn (gen_strset (destptr, dest, value));
17304 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
17305 emit_insn (gen_strset (destptr, dest, value));
17309 if ((countval & 0x04) && max_size > 4)
17311 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17312 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17315 if ((countval & 0x02) && max_size > 2)
17317 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
17318 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17321 if ((countval & 0x01) && max_size > 1)
17323 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
17324 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17331 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
17336 rtx label = ix86_expand_aligntest (count, 16, true);
17339 dest = change_address (destmem, DImode, destptr);
17340 emit_insn (gen_strset (destptr, dest, value));
17341 emit_insn (gen_strset (destptr, dest, value));
17345 dest = change_address (destmem, SImode, destptr);
17346 emit_insn (gen_strset (destptr, dest, value));
17347 emit_insn (gen_strset (destptr, dest, value));
17348 emit_insn (gen_strset (destptr, dest, value));
17349 emit_insn (gen_strset (destptr, dest, value));
17351 emit_label (label);
17352 LABEL_NUSES (label) = 1;
17356 rtx label = ix86_expand_aligntest (count, 8, true);
17359 dest = change_address (destmem, DImode, destptr);
17360 emit_insn (gen_strset (destptr, dest, value));
17364 dest = change_address (destmem, SImode, destptr);
17365 emit_insn (gen_strset (destptr, dest, value));
17366 emit_insn (gen_strset (destptr, dest, value));
17368 emit_label (label);
17369 LABEL_NUSES (label) = 1;
17373 rtx label = ix86_expand_aligntest (count, 4, true);
17374 dest = change_address (destmem, SImode, destptr);
17375 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17376 emit_label (label);
17377 LABEL_NUSES (label) = 1;
17381 rtx label = ix86_expand_aligntest (count, 2, true);
17382 dest = change_address (destmem, HImode, destptr);
17383 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17384 emit_label (label);
17385 LABEL_NUSES (label) = 1;
17389 rtx label = ix86_expand_aligntest (count, 1, true);
17390 dest = change_address (destmem, QImode, destptr);
17391 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17392 emit_label (label);
17393 LABEL_NUSES (label) = 1;
17397 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
17398 DESIRED_ALIGNMENT. */
17400 expand_movmem_prologue (rtx destmem, rtx srcmem,
17401 rtx destptr, rtx srcptr, rtx count,
17402 int align, int desired_alignment)
17404 if (align <= 1 && desired_alignment > 1)
17406 rtx label = ix86_expand_aligntest (destptr, 1, false);
17407 srcmem = change_address (srcmem, QImode, srcptr);
17408 destmem = change_address (destmem, QImode, destptr);
17409 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17410 ix86_adjust_counter (count, 1);
17411 emit_label (label);
17412 LABEL_NUSES (label) = 1;
17414 if (align <= 2 && desired_alignment > 2)
17416 rtx label = ix86_expand_aligntest (destptr, 2, false);
17417 srcmem = change_address (srcmem, HImode, srcptr);
17418 destmem = change_address (destmem, HImode, destptr);
17419 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17420 ix86_adjust_counter (count, 2);
17421 emit_label (label);
17422 LABEL_NUSES (label) = 1;
17424 if (align <= 4 && desired_alignment > 4)
17426 rtx label = ix86_expand_aligntest (destptr, 4, false);
17427 srcmem = change_address (srcmem, SImode, srcptr);
17428 destmem = change_address (destmem, SImode, destptr);
17429 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17430 ix86_adjust_counter (count, 4);
17431 emit_label (label);
17432 LABEL_NUSES (label) = 1;
17434 gcc_assert (desired_alignment <= 8);
17437 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
17438 ALIGN_BYTES is how many bytes need to be copied. */
17440 expand_constant_movmem_prologue (rtx dst, rtx *srcp, rtx destreg, rtx srcreg,
17441 int desired_align, int align_bytes)
17444 rtx src_size, dst_size;
17446 int src_align_bytes = get_mem_align_offset (src, desired_align * BITS_PER_UNIT);
17447 if (src_align_bytes >= 0)
17448 src_align_bytes = desired_align - src_align_bytes;
17449 src_size = MEM_SIZE (src);
17450 dst_size = MEM_SIZE (dst);
17451 if (align_bytes & 1)
17453 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17454 src = adjust_automodify_address_nv (src, QImode, srcreg, 0);
17456 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17458 if (align_bytes & 2)
17460 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17461 src = adjust_automodify_address_nv (src, HImode, srcreg, off);
17462 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17463 set_mem_align (dst, 2 * BITS_PER_UNIT);
17464 if (src_align_bytes >= 0
17465 && (src_align_bytes & 1) == (align_bytes & 1)
17466 && MEM_ALIGN (src) < 2 * BITS_PER_UNIT)
17467 set_mem_align (src, 2 * BITS_PER_UNIT);
17469 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17471 if (align_bytes & 4)
17473 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17474 src = adjust_automodify_address_nv (src, SImode, srcreg, off);
17475 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17476 set_mem_align (dst, 4 * BITS_PER_UNIT);
17477 if (src_align_bytes >= 0)
17479 unsigned int src_align = 0;
17480 if ((src_align_bytes & 3) == (align_bytes & 3))
17482 else if ((src_align_bytes & 1) == (align_bytes & 1))
17484 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17485 set_mem_align (src, src_align * BITS_PER_UNIT);
17488 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17490 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17491 src = adjust_automodify_address_nv (src, BLKmode, srcreg, off);
17492 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17493 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17494 if (src_align_bytes >= 0)
17496 unsigned int src_align = 0;
17497 if ((src_align_bytes & 7) == (align_bytes & 7))
17499 else if ((src_align_bytes & 3) == (align_bytes & 3))
17501 else if ((src_align_bytes & 1) == (align_bytes & 1))
17503 if (src_align > (unsigned int) desired_align)
17504 src_align = desired_align;
17505 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17506 set_mem_align (src, src_align * BITS_PER_UNIT);
17509 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17511 set_mem_size (dst, GEN_INT (INTVAL (src_size) - align_bytes));
17516 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
17517 DESIRED_ALIGNMENT. */
17519 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
17520 int align, int desired_alignment)
17522 if (align <= 1 && desired_alignment > 1)
17524 rtx label = ix86_expand_aligntest (destptr, 1, false);
17525 destmem = change_address (destmem, QImode, destptr);
17526 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
17527 ix86_adjust_counter (count, 1);
17528 emit_label (label);
17529 LABEL_NUSES (label) = 1;
17531 if (align <= 2 && desired_alignment > 2)
17533 rtx label = ix86_expand_aligntest (destptr, 2, false);
17534 destmem = change_address (destmem, HImode, destptr);
17535 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
17536 ix86_adjust_counter (count, 2);
17537 emit_label (label);
17538 LABEL_NUSES (label) = 1;
17540 if (align <= 4 && desired_alignment > 4)
17542 rtx label = ix86_expand_aligntest (destptr, 4, false);
17543 destmem = change_address (destmem, SImode, destptr);
17544 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
17545 ix86_adjust_counter (count, 4);
17546 emit_label (label);
17547 LABEL_NUSES (label) = 1;
17549 gcc_assert (desired_alignment <= 8);
17552 /* Set enough from DST to align DST known to by aligned by ALIGN to
17553 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
17555 expand_constant_setmem_prologue (rtx dst, rtx destreg, rtx value,
17556 int desired_align, int align_bytes)
17559 rtx dst_size = MEM_SIZE (dst);
17560 if (align_bytes & 1)
17562 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17564 emit_insn (gen_strset (destreg, dst,
17565 gen_lowpart (QImode, value)));
17567 if (align_bytes & 2)
17569 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17570 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17571 set_mem_align (dst, 2 * BITS_PER_UNIT);
17573 emit_insn (gen_strset (destreg, dst,
17574 gen_lowpart (HImode, value)));
17576 if (align_bytes & 4)
17578 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17579 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17580 set_mem_align (dst, 4 * BITS_PER_UNIT);
17582 emit_insn (gen_strset (destreg, dst,
17583 gen_lowpart (SImode, value)));
17585 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17586 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17587 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17589 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17593 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
17594 static enum stringop_alg
17595 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
17596 int *dynamic_check)
17598 const struct stringop_algs * algs;
17599 bool optimize_for_speed;
17600 /* Algorithms using the rep prefix want at least edi and ecx;
17601 additionally, memset wants eax and memcpy wants esi. Don't
17602 consider such algorithms if the user has appropriated those
17603 registers for their own purposes. */
17604 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
17606 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
17608 #define ALG_USABLE_P(alg) (rep_prefix_usable \
17609 || (alg != rep_prefix_1_byte \
17610 && alg != rep_prefix_4_byte \
17611 && alg != rep_prefix_8_byte))
17612 const struct processor_costs *cost;
17614 /* Even if the string operation call is cold, we still might spend a lot
17615 of time processing large blocks. */
17616 if (optimize_function_for_size_p (cfun)
17617 || (optimize_insn_for_size_p ()
17618 && expected_size != -1 && expected_size < 256))
17619 optimize_for_speed = false;
17621 optimize_for_speed = true;
17623 cost = optimize_for_speed ? ix86_cost : &ix86_size_cost;
17625 *dynamic_check = -1;
17627 algs = &cost->memset[TARGET_64BIT != 0];
17629 algs = &cost->memcpy[TARGET_64BIT != 0];
17630 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
17631 return stringop_alg;
17632 /* rep; movq or rep; movl is the smallest variant. */
17633 else if (!optimize_for_speed)
17635 if (!count || (count & 3))
17636 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
17638 return rep_prefix_usable ? rep_prefix_4_byte : loop;
17640 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
17642 else if (expected_size != -1 && expected_size < 4)
17643 return loop_1_byte;
17644 else if (expected_size != -1)
17647 enum stringop_alg alg = libcall;
17648 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17650 /* We get here if the algorithms that were not libcall-based
17651 were rep-prefix based and we are unable to use rep prefixes
17652 based on global register usage. Break out of the loop and
17653 use the heuristic below. */
17654 if (algs->size[i].max == 0)
17656 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
17658 enum stringop_alg candidate = algs->size[i].alg;
17660 if (candidate != libcall && ALG_USABLE_P (candidate))
17662 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
17663 last non-libcall inline algorithm. */
17664 if (TARGET_INLINE_ALL_STRINGOPS)
17666 /* When the current size is best to be copied by a libcall,
17667 but we are still forced to inline, run the heuristic below
17668 that will pick code for medium sized blocks. */
17669 if (alg != libcall)
17673 else if (ALG_USABLE_P (candidate))
17677 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
17679 /* When asked to inline the call anyway, try to pick meaningful choice.
17680 We look for maximal size of block that is faster to copy by hand and
17681 take blocks of at most of that size guessing that average size will
17682 be roughly half of the block.
17684 If this turns out to be bad, we might simply specify the preferred
17685 choice in ix86_costs. */
17686 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17687 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
17690 enum stringop_alg alg;
17692 bool any_alg_usable_p = true;
17694 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17696 enum stringop_alg candidate = algs->size[i].alg;
17697 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
17699 if (candidate != libcall && candidate
17700 && ALG_USABLE_P (candidate))
17701 max = algs->size[i].max;
17703 /* If there aren't any usable algorithms, then recursing on
17704 smaller sizes isn't going to find anything. Just return the
17705 simple byte-at-a-time copy loop. */
17706 if (!any_alg_usable_p)
17708 /* Pick something reasonable. */
17709 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17710 *dynamic_check = 128;
17711 return loop_1_byte;
17715 alg = decide_alg (count, max / 2, memset, dynamic_check);
17716 gcc_assert (*dynamic_check == -1);
17717 gcc_assert (alg != libcall);
17718 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17719 *dynamic_check = max;
17722 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
17723 #undef ALG_USABLE_P
17726 /* Decide on alignment. We know that the operand is already aligned to ALIGN
17727 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
17729 decide_alignment (int align,
17730 enum stringop_alg alg,
17733 int desired_align = 0;
17737 gcc_unreachable ();
17739 case unrolled_loop:
17740 desired_align = GET_MODE_SIZE (Pmode);
17742 case rep_prefix_8_byte:
17745 case rep_prefix_4_byte:
17746 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17747 copying whole cacheline at once. */
17748 if (TARGET_PENTIUMPRO)
17753 case rep_prefix_1_byte:
17754 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17755 copying whole cacheline at once. */
17756 if (TARGET_PENTIUMPRO)
17770 if (desired_align < align)
17771 desired_align = align;
17772 if (expected_size != -1 && expected_size < 4)
17773 desired_align = align;
17774 return desired_align;
17777 /* Return the smallest power of 2 greater than VAL. */
17779 smallest_pow2_greater_than (int val)
17787 /* Expand string move (memcpy) operation. Use i386 string operations when
17788 profitable. expand_setmem contains similar code. The code depends upon
17789 architecture, block size and alignment, but always has the same
17792 1) Prologue guard: Conditional that jumps up to epilogues for small
17793 blocks that can be handled by epilogue alone. This is faster but
17794 also needed for correctness, since prologue assume the block is larger
17795 than the desired alignment.
17797 Optional dynamic check for size and libcall for large
17798 blocks is emitted here too, with -minline-stringops-dynamically.
17800 2) Prologue: copy first few bytes in order to get destination aligned
17801 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
17802 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
17803 We emit either a jump tree on power of two sized blocks, or a byte loop.
17805 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
17806 with specified algorithm.
17808 4) Epilogue: code copying tail of the block that is too small to be
17809 handled by main body (or up to size guarded by prologue guard). */
17812 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
17813 rtx expected_align_exp, rtx expected_size_exp)
17819 rtx jump_around_label = NULL;
17820 HOST_WIDE_INT align = 1;
17821 unsigned HOST_WIDE_INT count = 0;
17822 HOST_WIDE_INT expected_size = -1;
17823 int size_needed = 0, epilogue_size_needed;
17824 int desired_align = 0, align_bytes = 0;
17825 enum stringop_alg alg;
17827 bool need_zero_guard = false;
17829 if (CONST_INT_P (align_exp))
17830 align = INTVAL (align_exp);
17831 /* i386 can do misaligned access on reasonably increased cost. */
17832 if (CONST_INT_P (expected_align_exp)
17833 && INTVAL (expected_align_exp) > align)
17834 align = INTVAL (expected_align_exp);
17835 /* ALIGN is the minimum of destination and source alignment, but we care here
17836 just about destination alignment. */
17837 else if (MEM_ALIGN (dst) > (unsigned HOST_WIDE_INT) align * BITS_PER_UNIT)
17838 align = MEM_ALIGN (dst) / BITS_PER_UNIT;
17840 if (CONST_INT_P (count_exp))
17841 count = expected_size = INTVAL (count_exp);
17842 if (CONST_INT_P (expected_size_exp) && count == 0)
17843 expected_size = INTVAL (expected_size_exp);
17845 /* Make sure we don't need to care about overflow later on. */
17846 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
17849 /* Step 0: Decide on preferred algorithm, desired alignment and
17850 size of chunks to be copied by main loop. */
17852 alg = decide_alg (count, expected_size, false, &dynamic_check);
17853 desired_align = decide_alignment (align, alg, expected_size);
17855 if (!TARGET_ALIGN_STRINGOPS)
17856 align = desired_align;
17858 if (alg == libcall)
17860 gcc_assert (alg != no_stringop);
17862 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
17863 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
17864 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
17869 gcc_unreachable ();
17871 need_zero_guard = true;
17872 size_needed = GET_MODE_SIZE (Pmode);
17874 case unrolled_loop:
17875 need_zero_guard = true;
17876 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
17878 case rep_prefix_8_byte:
17881 case rep_prefix_4_byte:
17884 case rep_prefix_1_byte:
17888 need_zero_guard = true;
17893 epilogue_size_needed = size_needed;
17895 /* Step 1: Prologue guard. */
17897 /* Alignment code needs count to be in register. */
17898 if (CONST_INT_P (count_exp) && desired_align > align)
17900 if (INTVAL (count_exp) > desired_align
17901 && INTVAL (count_exp) > size_needed)
17904 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
17905 if (align_bytes <= 0)
17908 align_bytes = desired_align - align_bytes;
17910 if (align_bytes == 0)
17911 count_exp = force_reg (counter_mode (count_exp), count_exp);
17913 gcc_assert (desired_align >= 1 && align >= 1);
17915 /* Ensure that alignment prologue won't copy past end of block. */
17916 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
17918 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
17919 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
17920 Make sure it is power of 2. */
17921 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
17925 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
17927 /* If main algorithm works on QImode, no epilogue is needed.
17928 For small sizes just don't align anything. */
17929 if (size_needed == 1)
17930 desired_align = align;
17937 label = gen_label_rtx ();
17938 emit_cmp_and_jump_insns (count_exp,
17939 GEN_INT (epilogue_size_needed),
17940 LTU, 0, counter_mode (count_exp), 1, label);
17941 if (expected_size == -1 || expected_size < epilogue_size_needed)
17942 predict_jump (REG_BR_PROB_BASE * 60 / 100);
17944 predict_jump (REG_BR_PROB_BASE * 20 / 100);
17948 /* Emit code to decide on runtime whether library call or inline should be
17950 if (dynamic_check != -1)
17952 if (CONST_INT_P (count_exp))
17954 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
17956 emit_block_move_via_libcall (dst, src, count_exp, false);
17957 count_exp = const0_rtx;
17963 rtx hot_label = gen_label_rtx ();
17964 jump_around_label = gen_label_rtx ();
17965 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
17966 LEU, 0, GET_MODE (count_exp), 1, hot_label);
17967 predict_jump (REG_BR_PROB_BASE * 90 / 100);
17968 emit_block_move_via_libcall (dst, src, count_exp, false);
17969 emit_jump (jump_around_label);
17970 emit_label (hot_label);
17974 /* Step 2: Alignment prologue. */
17976 if (desired_align > align)
17978 if (align_bytes == 0)
17980 /* Except for the first move in epilogue, we no longer know
17981 constant offset in aliasing info. It don't seems to worth
17982 the pain to maintain it for the first move, so throw away
17984 src = change_address (src, BLKmode, srcreg);
17985 dst = change_address (dst, BLKmode, destreg);
17986 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
17991 /* If we know how many bytes need to be stored before dst is
17992 sufficiently aligned, maintain aliasing info accurately. */
17993 dst = expand_constant_movmem_prologue (dst, &src, destreg, srcreg,
17994 desired_align, align_bytes);
17995 count_exp = plus_constant (count_exp, -align_bytes);
17996 count -= align_bytes;
17998 if (need_zero_guard
17999 && (count < (unsigned HOST_WIDE_INT) size_needed
18000 || (align_bytes == 0
18001 && count < ((unsigned HOST_WIDE_INT) size_needed
18002 + desired_align - align))))
18004 /* It is possible that we copied enough so the main loop will not
18006 gcc_assert (size_needed > 1);
18007 if (label == NULL_RTX)
18008 label = gen_label_rtx ();
18009 emit_cmp_and_jump_insns (count_exp,
18010 GEN_INT (size_needed),
18011 LTU, 0, counter_mode (count_exp), 1, label);
18012 if (expected_size == -1
18013 || expected_size < (desired_align - align) / 2 + size_needed)
18014 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18016 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18019 if (label && size_needed == 1)
18021 emit_label (label);
18022 LABEL_NUSES (label) = 1;
18024 epilogue_size_needed = 1;
18026 else if (label == NULL_RTX)
18027 epilogue_size_needed = size_needed;
18029 /* Step 3: Main loop. */
18035 gcc_unreachable ();
18037 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18038 count_exp, QImode, 1, expected_size);
18041 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18042 count_exp, Pmode, 1, expected_size);
18044 case unrolled_loop:
18045 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
18046 registers for 4 temporaries anyway. */
18047 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18048 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
18051 case rep_prefix_8_byte:
18052 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18055 case rep_prefix_4_byte:
18056 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18059 case rep_prefix_1_byte:
18060 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18064 /* Adjust properly the offset of src and dest memory for aliasing. */
18065 if (CONST_INT_P (count_exp))
18067 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
18068 (count / size_needed) * size_needed);
18069 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18070 (count / size_needed) * size_needed);
18074 src = change_address (src, BLKmode, srcreg);
18075 dst = change_address (dst, BLKmode, destreg);
18078 /* Step 4: Epilogue to copy the remaining bytes. */
18082 /* When the main loop is done, COUNT_EXP might hold original count,
18083 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18084 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18085 bytes. Compensate if needed. */
18087 if (size_needed < epilogue_size_needed)
18090 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18091 GEN_INT (size_needed - 1), count_exp, 1,
18093 if (tmp != count_exp)
18094 emit_move_insn (count_exp, tmp);
18096 emit_label (label);
18097 LABEL_NUSES (label) = 1;
18100 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18101 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
18102 epilogue_size_needed);
18103 if (jump_around_label)
18104 emit_label (jump_around_label);
18108 /* Helper function for memcpy. For QImode value 0xXY produce
18109 0xXYXYXYXY of wide specified by MODE. This is essentially
18110 a * 0x10101010, but we can do slightly better than
18111 synth_mult by unwinding the sequence by hand on CPUs with
18114 promote_duplicated_reg (enum machine_mode mode, rtx val)
18116 enum machine_mode valmode = GET_MODE (val);
18118 int nops = mode == DImode ? 3 : 2;
18120 gcc_assert (mode == SImode || mode == DImode);
18121 if (val == const0_rtx)
18122 return copy_to_mode_reg (mode, const0_rtx);
18123 if (CONST_INT_P (val))
18125 HOST_WIDE_INT v = INTVAL (val) & 255;
18129 if (mode == DImode)
18130 v |= (v << 16) << 16;
18131 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
18134 if (valmode == VOIDmode)
18136 if (valmode != QImode)
18137 val = gen_lowpart (QImode, val);
18138 if (mode == QImode)
18140 if (!TARGET_PARTIAL_REG_STALL)
18142 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
18143 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
18144 <= (ix86_cost->shift_const + ix86_cost->add) * nops
18145 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
18147 rtx reg = convert_modes (mode, QImode, val, true);
18148 tmp = promote_duplicated_reg (mode, const1_rtx);
18149 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
18154 rtx reg = convert_modes (mode, QImode, val, true);
18156 if (!TARGET_PARTIAL_REG_STALL)
18157 if (mode == SImode)
18158 emit_insn (gen_movsi_insv_1 (reg, reg));
18160 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
18163 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
18164 NULL, 1, OPTAB_DIRECT);
18166 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18168 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
18169 NULL, 1, OPTAB_DIRECT);
18170 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18171 if (mode == SImode)
18173 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
18174 NULL, 1, OPTAB_DIRECT);
18175 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18180 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
18181 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
18182 alignment from ALIGN to DESIRED_ALIGN. */
18184 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
18189 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
18190 promoted_val = promote_duplicated_reg (DImode, val);
18191 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
18192 promoted_val = promote_duplicated_reg (SImode, val);
18193 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
18194 promoted_val = promote_duplicated_reg (HImode, val);
18196 promoted_val = val;
18198 return promoted_val;
18201 /* Expand string clear operation (bzero). Use i386 string operations when
18202 profitable. See expand_movmem comment for explanation of individual
18203 steps performed. */
18205 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
18206 rtx expected_align_exp, rtx expected_size_exp)
18211 rtx jump_around_label = NULL;
18212 HOST_WIDE_INT align = 1;
18213 unsigned HOST_WIDE_INT count = 0;
18214 HOST_WIDE_INT expected_size = -1;
18215 int size_needed = 0, epilogue_size_needed;
18216 int desired_align = 0, align_bytes = 0;
18217 enum stringop_alg alg;
18218 rtx promoted_val = NULL;
18219 bool force_loopy_epilogue = false;
18221 bool need_zero_guard = false;
18223 if (CONST_INT_P (align_exp))
18224 align = INTVAL (align_exp);
18225 /* i386 can do misaligned access on reasonably increased cost. */
18226 if (CONST_INT_P (expected_align_exp)
18227 && INTVAL (expected_align_exp) > align)
18228 align = INTVAL (expected_align_exp);
18229 if (CONST_INT_P (count_exp))
18230 count = expected_size = INTVAL (count_exp);
18231 if (CONST_INT_P (expected_size_exp) && count == 0)
18232 expected_size = INTVAL (expected_size_exp);
18234 /* Make sure we don't need to care about overflow later on. */
18235 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
18238 /* Step 0: Decide on preferred algorithm, desired alignment and
18239 size of chunks to be copied by main loop. */
18241 alg = decide_alg (count, expected_size, true, &dynamic_check);
18242 desired_align = decide_alignment (align, alg, expected_size);
18244 if (!TARGET_ALIGN_STRINGOPS)
18245 align = desired_align;
18247 if (alg == libcall)
18249 gcc_assert (alg != no_stringop);
18251 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
18252 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18257 gcc_unreachable ();
18259 need_zero_guard = true;
18260 size_needed = GET_MODE_SIZE (Pmode);
18262 case unrolled_loop:
18263 need_zero_guard = true;
18264 size_needed = GET_MODE_SIZE (Pmode) * 4;
18266 case rep_prefix_8_byte:
18269 case rep_prefix_4_byte:
18272 case rep_prefix_1_byte:
18276 need_zero_guard = true;
18280 epilogue_size_needed = size_needed;
18282 /* Step 1: Prologue guard. */
18284 /* Alignment code needs count to be in register. */
18285 if (CONST_INT_P (count_exp) && desired_align > align)
18287 if (INTVAL (count_exp) > desired_align
18288 && INTVAL (count_exp) > size_needed)
18291 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18292 if (align_bytes <= 0)
18295 align_bytes = desired_align - align_bytes;
18297 if (align_bytes == 0)
18299 enum machine_mode mode = SImode;
18300 if (TARGET_64BIT && (count & ~0xffffffff))
18302 count_exp = force_reg (mode, count_exp);
18305 /* Do the cheap promotion to allow better CSE across the
18306 main loop and epilogue (ie one load of the big constant in the
18307 front of all code. */
18308 if (CONST_INT_P (val_exp))
18309 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18310 desired_align, align);
18311 /* Ensure that alignment prologue won't copy past end of block. */
18312 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18314 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18315 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
18316 Make sure it is power of 2. */
18317 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18319 /* To improve performance of small blocks, we jump around the VAL
18320 promoting mode. This mean that if the promoted VAL is not constant,
18321 we might not use it in the epilogue and have to use byte
18323 if (epilogue_size_needed > 2 && !promoted_val)
18324 force_loopy_epilogue = true;
18327 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18329 /* If main algorithm works on QImode, no epilogue is needed.
18330 For small sizes just don't align anything. */
18331 if (size_needed == 1)
18332 desired_align = align;
18339 label = gen_label_rtx ();
18340 emit_cmp_and_jump_insns (count_exp,
18341 GEN_INT (epilogue_size_needed),
18342 LTU, 0, counter_mode (count_exp), 1, label);
18343 if (expected_size == -1 || expected_size <= epilogue_size_needed)
18344 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18346 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18349 if (dynamic_check != -1)
18351 rtx hot_label = gen_label_rtx ();
18352 jump_around_label = gen_label_rtx ();
18353 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18354 LEU, 0, counter_mode (count_exp), 1, hot_label);
18355 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18356 set_storage_via_libcall (dst, count_exp, val_exp, false);
18357 emit_jump (jump_around_label);
18358 emit_label (hot_label);
18361 /* Step 2: Alignment prologue. */
18363 /* Do the expensive promotion once we branched off the small blocks. */
18365 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18366 desired_align, align);
18367 gcc_assert (desired_align >= 1 && align >= 1);
18369 if (desired_align > align)
18371 if (align_bytes == 0)
18373 /* Except for the first move in epilogue, we no longer know
18374 constant offset in aliasing info. It don't seems to worth
18375 the pain to maintain it for the first move, so throw away
18377 dst = change_address (dst, BLKmode, destreg);
18378 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
18383 /* If we know how many bytes need to be stored before dst is
18384 sufficiently aligned, maintain aliasing info accurately. */
18385 dst = expand_constant_setmem_prologue (dst, destreg, promoted_val,
18386 desired_align, align_bytes);
18387 count_exp = plus_constant (count_exp, -align_bytes);
18388 count -= align_bytes;
18390 if (need_zero_guard
18391 && (count < (unsigned HOST_WIDE_INT) size_needed
18392 || (align_bytes == 0
18393 && count < ((unsigned HOST_WIDE_INT) size_needed
18394 + desired_align - align))))
18396 /* It is possible that we copied enough so the main loop will not
18398 gcc_assert (size_needed > 1);
18399 if (label == NULL_RTX)
18400 label = gen_label_rtx ();
18401 emit_cmp_and_jump_insns (count_exp,
18402 GEN_INT (size_needed),
18403 LTU, 0, counter_mode (count_exp), 1, label);
18404 if (expected_size == -1
18405 || expected_size < (desired_align - align) / 2 + size_needed)
18406 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18408 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18411 if (label && size_needed == 1)
18413 emit_label (label);
18414 LABEL_NUSES (label) = 1;
18416 promoted_val = val_exp;
18417 epilogue_size_needed = 1;
18419 else if (label == NULL_RTX)
18420 epilogue_size_needed = size_needed;
18422 /* Step 3: Main loop. */
18428 gcc_unreachable ();
18430 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18431 count_exp, QImode, 1, expected_size);
18434 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18435 count_exp, Pmode, 1, expected_size);
18437 case unrolled_loop:
18438 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18439 count_exp, Pmode, 4, expected_size);
18441 case rep_prefix_8_byte:
18442 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18445 case rep_prefix_4_byte:
18446 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18449 case rep_prefix_1_byte:
18450 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18454 /* Adjust properly the offset of src and dest memory for aliasing. */
18455 if (CONST_INT_P (count_exp))
18456 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18457 (count / size_needed) * size_needed);
18459 dst = change_address (dst, BLKmode, destreg);
18461 /* Step 4: Epilogue to copy the remaining bytes. */
18465 /* When the main loop is done, COUNT_EXP might hold original count,
18466 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18467 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18468 bytes. Compensate if needed. */
18470 if (size_needed < epilogue_size_needed)
18473 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18474 GEN_INT (size_needed - 1), count_exp, 1,
18476 if (tmp != count_exp)
18477 emit_move_insn (count_exp, tmp);
18479 emit_label (label);
18480 LABEL_NUSES (label) = 1;
18483 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18485 if (force_loopy_epilogue)
18486 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
18487 epilogue_size_needed);
18489 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
18490 epilogue_size_needed);
18492 if (jump_around_label)
18493 emit_label (jump_around_label);
18497 /* Expand the appropriate insns for doing strlen if not just doing
18500 out = result, initialized with the start address
18501 align_rtx = alignment of the address.
18502 scratch = scratch register, initialized with the startaddress when
18503 not aligned, otherwise undefined
18505 This is just the body. It needs the initializations mentioned above and
18506 some address computing at the end. These things are done in i386.md. */
18509 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
18513 rtx align_2_label = NULL_RTX;
18514 rtx align_3_label = NULL_RTX;
18515 rtx align_4_label = gen_label_rtx ();
18516 rtx end_0_label = gen_label_rtx ();
18518 rtx tmpreg = gen_reg_rtx (SImode);
18519 rtx scratch = gen_reg_rtx (SImode);
18523 if (CONST_INT_P (align_rtx))
18524 align = INTVAL (align_rtx);
18526 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
18528 /* Is there a known alignment and is it less than 4? */
18531 rtx scratch1 = gen_reg_rtx (Pmode);
18532 emit_move_insn (scratch1, out);
18533 /* Is there a known alignment and is it not 2? */
18536 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
18537 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
18539 /* Leave just the 3 lower bits. */
18540 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
18541 NULL_RTX, 0, OPTAB_WIDEN);
18543 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18544 Pmode, 1, align_4_label);
18545 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
18546 Pmode, 1, align_2_label);
18547 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
18548 Pmode, 1, align_3_label);
18552 /* Since the alignment is 2, we have to check 2 or 0 bytes;
18553 check if is aligned to 4 - byte. */
18555 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
18556 NULL_RTX, 0, OPTAB_WIDEN);
18558 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18559 Pmode, 1, align_4_label);
18562 mem = change_address (src, QImode, out);
18564 /* Now compare the bytes. */
18566 /* Compare the first n unaligned byte on a byte per byte basis. */
18567 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
18568 QImode, 1, end_0_label);
18570 /* Increment the address. */
18571 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18573 /* Not needed with an alignment of 2 */
18576 emit_label (align_2_label);
18578 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18581 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18583 emit_label (align_3_label);
18586 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18589 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18592 /* Generate loop to check 4 bytes at a time. It is not a good idea to
18593 align this loop. It gives only huge programs, but does not help to
18595 emit_label (align_4_label);
18597 mem = change_address (src, SImode, out);
18598 emit_move_insn (scratch, mem);
18599 emit_insn ((*ix86_gen_add3) (out, out, GEN_INT (4)));
18601 /* This formula yields a nonzero result iff one of the bytes is zero.
18602 This saves three branches inside loop and many cycles. */
18604 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
18605 emit_insn (gen_one_cmplsi2 (scratch, scratch));
18606 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
18607 emit_insn (gen_andsi3 (tmpreg, tmpreg,
18608 gen_int_mode (0x80808080, SImode)));
18609 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
18614 rtx reg = gen_reg_rtx (SImode);
18615 rtx reg2 = gen_reg_rtx (Pmode);
18616 emit_move_insn (reg, tmpreg);
18617 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
18619 /* If zero is not in the first two bytes, move two bytes forward. */
18620 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18621 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18622 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18623 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
18624 gen_rtx_IF_THEN_ELSE (SImode, tmp,
18627 /* Emit lea manually to avoid clobbering of flags. */
18628 emit_insn (gen_rtx_SET (SImode, reg2,
18629 gen_rtx_PLUS (Pmode, out, const2_rtx)));
18631 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18632 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18633 emit_insn (gen_rtx_SET (VOIDmode, out,
18634 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
18641 rtx end_2_label = gen_label_rtx ();
18642 /* Is zero in the first two bytes? */
18644 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18645 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18646 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
18647 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
18648 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
18650 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
18651 JUMP_LABEL (tmp) = end_2_label;
18653 /* Not in the first two. Move two bytes forward. */
18654 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
18655 emit_insn ((*ix86_gen_add3) (out, out, const2_rtx));
18657 emit_label (end_2_label);
18661 /* Avoid branch in fixing the byte. */
18662 tmpreg = gen_lowpart (QImode, tmpreg);
18663 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
18664 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
18665 emit_insn ((*ix86_gen_sub3_carry) (out, out, GEN_INT (3), cmp));
18667 emit_label (end_0_label);
18670 /* Expand strlen. */
18673 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
18675 rtx addr, scratch1, scratch2, scratch3, scratch4;
18677 /* The generic case of strlen expander is long. Avoid it's
18678 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
18680 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18681 && !TARGET_INLINE_ALL_STRINGOPS
18682 && !optimize_insn_for_size_p ()
18683 && (!CONST_INT_P (align) || INTVAL (align) < 4))
18686 addr = force_reg (Pmode, XEXP (src, 0));
18687 scratch1 = gen_reg_rtx (Pmode);
18689 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18690 && !optimize_insn_for_size_p ())
18692 /* Well it seems that some optimizer does not combine a call like
18693 foo(strlen(bar), strlen(bar));
18694 when the move and the subtraction is done here. It does calculate
18695 the length just once when these instructions are done inside of
18696 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
18697 often used and I use one fewer register for the lifetime of
18698 output_strlen_unroll() this is better. */
18700 emit_move_insn (out, addr);
18702 ix86_expand_strlensi_unroll_1 (out, src, align);
18704 /* strlensi_unroll_1 returns the address of the zero at the end of
18705 the string, like memchr(), so compute the length by subtracting
18706 the start address. */
18707 emit_insn ((*ix86_gen_sub3) (out, out, addr));
18713 /* Can't use this if the user has appropriated eax, ecx, or edi. */
18714 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
18717 scratch2 = gen_reg_rtx (Pmode);
18718 scratch3 = gen_reg_rtx (Pmode);
18719 scratch4 = force_reg (Pmode, constm1_rtx);
18721 emit_move_insn (scratch3, addr);
18722 eoschar = force_reg (QImode, eoschar);
18724 src = replace_equiv_address_nv (src, scratch3);
18726 /* If .md starts supporting :P, this can be done in .md. */
18727 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
18728 scratch4), UNSPEC_SCAS);
18729 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
18730 emit_insn ((*ix86_gen_one_cmpl2) (scratch2, scratch1));
18731 emit_insn ((*ix86_gen_add3) (out, scratch2, constm1_rtx));
18736 /* For given symbol (function) construct code to compute address of it's PLT
18737 entry in large x86-64 PIC model. */
18739 construct_plt_address (rtx symbol)
18741 rtx tmp = gen_reg_rtx (Pmode);
18742 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
18744 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
18745 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
18747 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
18748 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
18753 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
18755 rtx pop, int sibcall)
18757 rtx use = NULL, call;
18759 if (pop == const0_rtx)
18761 gcc_assert (!TARGET_64BIT || !pop);
18763 if (TARGET_MACHO && !TARGET_64BIT)
18766 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
18767 fnaddr = machopic_indirect_call_target (fnaddr);
18772 /* Static functions and indirect calls don't need the pic register. */
18773 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
18774 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18775 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
18776 use_reg (&use, pic_offset_table_rtx);
18779 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
18781 rtx al = gen_rtx_REG (QImode, AX_REG);
18782 emit_move_insn (al, callarg2);
18783 use_reg (&use, al);
18786 if (ix86_cmodel == CM_LARGE_PIC
18787 && GET_CODE (fnaddr) == MEM
18788 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18789 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
18790 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
18792 ? !sibcall_insn_operand (XEXP (fnaddr, 0), Pmode)
18793 : !call_insn_operand (XEXP (fnaddr, 0), Pmode))
18795 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
18796 fnaddr = gen_rtx_MEM (QImode, fnaddr);
18799 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
18801 call = gen_rtx_SET (VOIDmode, retval, call);
18804 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
18805 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
18806 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
18809 && ix86_cfun_abi () == MS_ABI
18810 && (!callarg2 || INTVAL (callarg2) != -2))
18812 /* We need to represent that SI and DI registers are clobbered
18814 static int clobbered_registers[] = {
18815 XMM6_REG, XMM7_REG, XMM8_REG,
18816 XMM9_REG, XMM10_REG, XMM11_REG,
18817 XMM12_REG, XMM13_REG, XMM14_REG,
18818 XMM15_REG, SI_REG, DI_REG
18821 rtx vec[ARRAY_SIZE (clobbered_registers) + 2];
18822 rtx unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx),
18823 UNSPEC_MS_TO_SYSV_CALL);
18827 for (i = 0; i < ARRAY_SIZE (clobbered_registers); i++)
18828 vec[i + 2] = gen_rtx_CLOBBER (SSE_REGNO_P (clobbered_registers[i])
18831 (SSE_REGNO_P (clobbered_registers[i])
18833 clobbered_registers[i]));
18835 call = gen_rtx_PARALLEL (VOIDmode,
18836 gen_rtvec_v (ARRAY_SIZE (clobbered_registers)
18840 call = emit_call_insn (call);
18842 CALL_INSN_FUNCTION_USAGE (call) = use;
18846 /* Clear stack slot assignments remembered from previous functions.
18847 This is called from INIT_EXPANDERS once before RTL is emitted for each
18850 static struct machine_function *
18851 ix86_init_machine_status (void)
18853 struct machine_function *f;
18855 f = GGC_CNEW (struct machine_function);
18856 f->use_fast_prologue_epilogue_nregs = -1;
18857 f->tls_descriptor_call_expanded_p = 0;
18858 f->call_abi = DEFAULT_ABI;
18863 /* Return a MEM corresponding to a stack slot with mode MODE.
18864 Allocate a new slot if necessary.
18866 The RTL for a function can have several slots available: N is
18867 which slot to use. */
18870 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
18872 struct stack_local_entry *s;
18874 gcc_assert (n < MAX_386_STACK_LOCALS);
18876 /* Virtual slot is valid only before vregs are instantiated. */
18877 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
18879 for (s = ix86_stack_locals; s; s = s->next)
18880 if (s->mode == mode && s->n == n)
18881 return copy_rtx (s->rtl);
18883 s = (struct stack_local_entry *)
18884 ggc_alloc (sizeof (struct stack_local_entry));
18887 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
18889 s->next = ix86_stack_locals;
18890 ix86_stack_locals = s;
18894 /* Construct the SYMBOL_REF for the tls_get_addr function. */
18896 static GTY(()) rtx ix86_tls_symbol;
18898 ix86_tls_get_addr (void)
18901 if (!ix86_tls_symbol)
18903 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
18904 (TARGET_ANY_GNU_TLS
18906 ? "___tls_get_addr"
18907 : "__tls_get_addr");
18910 return ix86_tls_symbol;
18913 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
18915 static GTY(()) rtx ix86_tls_module_base_symbol;
18917 ix86_tls_module_base (void)
18920 if (!ix86_tls_module_base_symbol)
18922 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
18923 "_TLS_MODULE_BASE_");
18924 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
18925 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
18928 return ix86_tls_module_base_symbol;
18931 /* Calculate the length of the memory address in the instruction
18932 encoding. Does not include the one-byte modrm, opcode, or prefix. */
18935 memory_address_length (rtx addr)
18937 struct ix86_address parts;
18938 rtx base, index, disp;
18942 if (GET_CODE (addr) == PRE_DEC
18943 || GET_CODE (addr) == POST_INC
18944 || GET_CODE (addr) == PRE_MODIFY
18945 || GET_CODE (addr) == POST_MODIFY)
18948 ok = ix86_decompose_address (addr, &parts);
18951 if (parts.base && GET_CODE (parts.base) == SUBREG)
18952 parts.base = SUBREG_REG (parts.base);
18953 if (parts.index && GET_CODE (parts.index) == SUBREG)
18954 parts.index = SUBREG_REG (parts.index);
18957 index = parts.index;
18962 - esp as the base always wants an index,
18963 - ebp as the base always wants a displacement. */
18965 /* Register Indirect. */
18966 if (base && !index && !disp)
18968 /* esp (for its index) and ebp (for its displacement) need
18969 the two-byte modrm form. */
18970 if (addr == stack_pointer_rtx
18971 || addr == arg_pointer_rtx
18972 || addr == frame_pointer_rtx
18973 || addr == hard_frame_pointer_rtx)
18977 /* Direct Addressing. */
18978 else if (disp && !base && !index)
18983 /* Find the length of the displacement constant. */
18986 if (base && satisfies_constraint_K (disp))
18991 /* ebp always wants a displacement. */
18992 else if (base == hard_frame_pointer_rtx)
18995 /* An index requires the two-byte modrm form.... */
18997 /* ...like esp, which always wants an index. */
18998 || base == stack_pointer_rtx
18999 || base == arg_pointer_rtx
19000 || base == frame_pointer_rtx)
19007 /* Compute default value for "length_immediate" attribute. When SHORTFORM
19008 is set, expect that insn have 8bit immediate alternative. */
19010 ix86_attr_length_immediate_default (rtx insn, int shortform)
19014 extract_insn_cached (insn);
19015 for (i = recog_data.n_operands - 1; i >= 0; --i)
19016 if (CONSTANT_P (recog_data.operand[i]))
19019 if (shortform && satisfies_constraint_K (recog_data.operand[i]))
19023 switch (get_attr_mode (insn))
19034 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
19039 fatal_insn ("unknown insn mode", insn);
19045 /* Compute default value for "length_address" attribute. */
19047 ix86_attr_length_address_default (rtx insn)
19051 if (get_attr_type (insn) == TYPE_LEA)
19053 rtx set = PATTERN (insn);
19055 if (GET_CODE (set) == PARALLEL)
19056 set = XVECEXP (set, 0, 0);
19058 gcc_assert (GET_CODE (set) == SET);
19060 return memory_address_length (SET_SRC (set));
19063 extract_insn_cached (insn);
19064 for (i = recog_data.n_operands - 1; i >= 0; --i)
19065 if (MEM_P (recog_data.operand[i]))
19067 return memory_address_length (XEXP (recog_data.operand[i], 0));
19073 /* Compute default value for "length_vex" attribute. It includes
19074 2 or 3 byte VEX prefix and 1 opcode byte. */
19077 ix86_attr_length_vex_default (rtx insn, int has_0f_opcode,
19082 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
19083 byte VEX prefix. */
19084 if (!has_0f_opcode || has_vex_w)
19087 /* We can always use 2 byte VEX prefix in 32bit. */
19091 extract_insn_cached (insn);
19093 for (i = recog_data.n_operands - 1; i >= 0; --i)
19094 if (REG_P (recog_data.operand[i]))
19096 /* REX.W bit uses 3 byte VEX prefix. */
19097 if (GET_MODE (recog_data.operand[i]) == DImode)
19102 /* REX.X or REX.B bits use 3 byte VEX prefix. */
19103 if (MEM_P (recog_data.operand[i])
19104 && x86_extended_reg_mentioned_p (recog_data.operand[i]))
19111 /* Return the maximum number of instructions a cpu can issue. */
19114 ix86_issue_rate (void)
19118 case PROCESSOR_PENTIUM:
19122 case PROCESSOR_PENTIUMPRO:
19123 case PROCESSOR_PENTIUM4:
19124 case PROCESSOR_ATHLON:
19126 case PROCESSOR_AMDFAM10:
19127 case PROCESSOR_NOCONA:
19128 case PROCESSOR_GENERIC32:
19129 case PROCESSOR_GENERIC64:
19132 case PROCESSOR_CORE2:
19140 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
19141 by DEP_INSN and nothing set by DEP_INSN. */
19144 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19148 /* Simplify the test for uninteresting insns. */
19149 if (insn_type != TYPE_SETCC
19150 && insn_type != TYPE_ICMOV
19151 && insn_type != TYPE_FCMOV
19152 && insn_type != TYPE_IBR)
19155 if ((set = single_set (dep_insn)) != 0)
19157 set = SET_DEST (set);
19160 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
19161 && XVECLEN (PATTERN (dep_insn), 0) == 2
19162 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
19163 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
19165 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19166 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19171 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
19174 /* This test is true if the dependent insn reads the flags but
19175 not any other potentially set register. */
19176 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
19179 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
19185 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
19186 address with operands set by DEP_INSN. */
19189 ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19193 if (insn_type == TYPE_LEA
19196 addr = PATTERN (insn);
19198 if (GET_CODE (addr) == PARALLEL)
19199 addr = XVECEXP (addr, 0, 0);
19201 gcc_assert (GET_CODE (addr) == SET);
19203 addr = SET_SRC (addr);
19208 extract_insn_cached (insn);
19209 for (i = recog_data.n_operands - 1; i >= 0; --i)
19210 if (MEM_P (recog_data.operand[i]))
19212 addr = XEXP (recog_data.operand[i], 0);
19219 return modified_in_p (addr, dep_insn);
19223 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
19225 enum attr_type insn_type, dep_insn_type;
19226 enum attr_memory memory;
19228 int dep_insn_code_number;
19230 /* Anti and output dependencies have zero cost on all CPUs. */
19231 if (REG_NOTE_KIND (link) != 0)
19234 dep_insn_code_number = recog_memoized (dep_insn);
19236 /* If we can't recognize the insns, we can't really do anything. */
19237 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
19240 insn_type = get_attr_type (insn);
19241 dep_insn_type = get_attr_type (dep_insn);
19245 case PROCESSOR_PENTIUM:
19246 /* Address Generation Interlock adds a cycle of latency. */
19247 if (ix86_agi_dependent (insn, dep_insn, insn_type))
19250 /* ??? Compares pair with jump/setcc. */
19251 if (ix86_flags_dependent (insn, dep_insn, insn_type))
19254 /* Floating point stores require value to be ready one cycle earlier. */
19255 if (insn_type == TYPE_FMOV
19256 && get_attr_memory (insn) == MEMORY_STORE
19257 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19261 case PROCESSOR_PENTIUMPRO:
19262 memory = get_attr_memory (insn);
19264 /* INT->FP conversion is expensive. */
19265 if (get_attr_fp_int_src (dep_insn))
19268 /* There is one cycle extra latency between an FP op and a store. */
19269 if (insn_type == TYPE_FMOV
19270 && (set = single_set (dep_insn)) != NULL_RTX
19271 && (set2 = single_set (insn)) != NULL_RTX
19272 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
19273 && MEM_P (SET_DEST (set2)))
19276 /* Show ability of reorder buffer to hide latency of load by executing
19277 in parallel with previous instruction in case
19278 previous instruction is not needed to compute the address. */
19279 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19280 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19282 /* Claim moves to take one cycle, as core can issue one load
19283 at time and the next load can start cycle later. */
19284 if (dep_insn_type == TYPE_IMOV
19285 || dep_insn_type == TYPE_FMOV)
19293 memory = get_attr_memory (insn);
19295 /* The esp dependency is resolved before the instruction is really
19297 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
19298 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
19301 /* INT->FP conversion is expensive. */
19302 if (get_attr_fp_int_src (dep_insn))
19305 /* Show ability of reorder buffer to hide latency of load by executing
19306 in parallel with previous instruction in case
19307 previous instruction is not needed to compute the address. */
19308 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19309 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19311 /* Claim moves to take one cycle, as core can issue one load
19312 at time and the next load can start cycle later. */
19313 if (dep_insn_type == TYPE_IMOV
19314 || dep_insn_type == TYPE_FMOV)
19323 case PROCESSOR_ATHLON:
19325 case PROCESSOR_AMDFAM10:
19326 case PROCESSOR_GENERIC32:
19327 case PROCESSOR_GENERIC64:
19328 memory = get_attr_memory (insn);
19330 /* Show ability of reorder buffer to hide latency of load by executing
19331 in parallel with previous instruction in case
19332 previous instruction is not needed to compute the address. */
19333 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19334 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19336 enum attr_unit unit = get_attr_unit (insn);
19339 /* Because of the difference between the length of integer and
19340 floating unit pipeline preparation stages, the memory operands
19341 for floating point are cheaper.
19343 ??? For Athlon it the difference is most probably 2. */
19344 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
19347 loadcost = TARGET_ATHLON ? 2 : 0;
19349 if (cost >= loadcost)
19362 /* How many alternative schedules to try. This should be as wide as the
19363 scheduling freedom in the DFA, but no wider. Making this value too
19364 large results extra work for the scheduler. */
19367 ia32_multipass_dfa_lookahead (void)
19371 case PROCESSOR_PENTIUM:
19374 case PROCESSOR_PENTIUMPRO:
19384 /* Compute the alignment given to a constant that is being placed in memory.
19385 EXP is the constant and ALIGN is the alignment that the object would
19387 The value of this function is used instead of that alignment to align
19391 ix86_constant_alignment (tree exp, int align)
19393 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
19394 || TREE_CODE (exp) == INTEGER_CST)
19396 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
19398 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
19401 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
19402 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
19403 return BITS_PER_WORD;
19408 /* Compute the alignment for a static variable.
19409 TYPE is the data type, and ALIGN is the alignment that
19410 the object would ordinarily have. The value of this function is used
19411 instead of that alignment to align the object. */
19414 ix86_data_alignment (tree type, int align)
19416 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
19418 if (AGGREGATE_TYPE_P (type)
19419 && TYPE_SIZE (type)
19420 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19421 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
19422 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
19423 && align < max_align)
19426 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19427 to 16byte boundary. */
19430 if (AGGREGATE_TYPE_P (type)
19431 && TYPE_SIZE (type)
19432 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19433 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
19434 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19438 if (TREE_CODE (type) == ARRAY_TYPE)
19440 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19442 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19445 else if (TREE_CODE (type) == COMPLEX_TYPE)
19448 if (TYPE_MODE (type) == DCmode && align < 64)
19450 if ((TYPE_MODE (type) == XCmode
19451 || TYPE_MODE (type) == TCmode) && align < 128)
19454 else if ((TREE_CODE (type) == RECORD_TYPE
19455 || TREE_CODE (type) == UNION_TYPE
19456 || TREE_CODE (type) == QUAL_UNION_TYPE)
19457 && TYPE_FIELDS (type))
19459 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19461 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19464 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19465 || TREE_CODE (type) == INTEGER_TYPE)
19467 if (TYPE_MODE (type) == DFmode && align < 64)
19469 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19476 /* Compute the alignment for a local variable or a stack slot. EXP is
19477 the data type or decl itself, MODE is the widest mode available and
19478 ALIGN is the alignment that the object would ordinarily have. The
19479 value of this macro is used instead of that alignment to align the
19483 ix86_local_alignment (tree exp, enum machine_mode mode,
19484 unsigned int align)
19488 if (exp && DECL_P (exp))
19490 type = TREE_TYPE (exp);
19499 /* Don't do dynamic stack realignment for long long objects with
19500 -mpreferred-stack-boundary=2. */
19503 && ix86_preferred_stack_boundary < 64
19504 && (mode == DImode || (type && TYPE_MODE (type) == DImode))
19505 && (!type || !TYPE_USER_ALIGN (type))
19506 && (!decl || !DECL_USER_ALIGN (decl)))
19509 /* If TYPE is NULL, we are allocating a stack slot for caller-save
19510 register in MODE. We will return the largest alignment of XF
19514 if (mode == XFmode && align < GET_MODE_ALIGNMENT (DFmode))
19515 align = GET_MODE_ALIGNMENT (DFmode);
19519 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19520 to 16byte boundary. */
19523 if (AGGREGATE_TYPE_P (type)
19524 && TYPE_SIZE (type)
19525 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19526 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
19527 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19530 if (TREE_CODE (type) == ARRAY_TYPE)
19532 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19534 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19537 else if (TREE_CODE (type) == COMPLEX_TYPE)
19539 if (TYPE_MODE (type) == DCmode && align < 64)
19541 if ((TYPE_MODE (type) == XCmode
19542 || TYPE_MODE (type) == TCmode) && align < 128)
19545 else if ((TREE_CODE (type) == RECORD_TYPE
19546 || TREE_CODE (type) == UNION_TYPE
19547 || TREE_CODE (type) == QUAL_UNION_TYPE)
19548 && TYPE_FIELDS (type))
19550 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19552 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19555 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19556 || TREE_CODE (type) == INTEGER_TYPE)
19559 if (TYPE_MODE (type) == DFmode && align < 64)
19561 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19567 /* Compute the minimum required alignment for dynamic stack realignment
19568 purposes for a local variable, parameter or a stack slot. EXP is
19569 the data type or decl itself, MODE is its mode and ALIGN is the
19570 alignment that the object would ordinarily have. */
19573 ix86_minimum_alignment (tree exp, enum machine_mode mode,
19574 unsigned int align)
19578 if (TARGET_64BIT || align != 64 || ix86_preferred_stack_boundary >= 64)
19581 if (exp && DECL_P (exp))
19583 type = TREE_TYPE (exp);
19592 /* Don't do dynamic stack realignment for long long objects with
19593 -mpreferred-stack-boundary=2. */
19594 if ((mode == DImode || (type && TYPE_MODE (type) == DImode))
19595 && (!type || !TYPE_USER_ALIGN (type))
19596 && (!decl || !DECL_USER_ALIGN (decl)))
19602 /* Emit RTL insns to initialize the variable parts of a trampoline.
19603 FNADDR is an RTX for the address of the function's pure code.
19604 CXT is an RTX for the static chain value for the function. */
19606 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
19610 /* Compute offset from the end of the jmp to the target function. */
19611 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
19612 plus_constant (tramp, 10),
19613 NULL_RTX, 1, OPTAB_DIRECT);
19614 emit_move_insn (gen_rtx_MEM (QImode, tramp),
19615 gen_int_mode (0xb9, QImode));
19616 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
19617 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
19618 gen_int_mode (0xe9, QImode));
19619 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
19624 /* Try to load address using shorter movl instead of movabs.
19625 We may want to support movq for kernel mode, but kernel does not use
19626 trampolines at the moment. */
19627 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
19629 fnaddr = copy_to_mode_reg (DImode, fnaddr);
19630 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19631 gen_int_mode (0xbb41, HImode));
19632 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
19633 gen_lowpart (SImode, fnaddr));
19638 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19639 gen_int_mode (0xbb49, HImode));
19640 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
19644 /* Load static chain using movabs to r10. */
19645 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19646 gen_int_mode (0xba49, HImode));
19647 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
19650 /* Jump to the r11 */
19651 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19652 gen_int_mode (0xff49, HImode));
19653 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
19654 gen_int_mode (0xe3, QImode));
19656 gcc_assert (offset <= TRAMPOLINE_SIZE);
19659 #ifdef ENABLE_EXECUTE_STACK
19660 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
19661 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
19665 /* Codes for all the SSE/MMX builtins. */
19668 IX86_BUILTIN_ADDPS,
19669 IX86_BUILTIN_ADDSS,
19670 IX86_BUILTIN_DIVPS,
19671 IX86_BUILTIN_DIVSS,
19672 IX86_BUILTIN_MULPS,
19673 IX86_BUILTIN_MULSS,
19674 IX86_BUILTIN_SUBPS,
19675 IX86_BUILTIN_SUBSS,
19677 IX86_BUILTIN_CMPEQPS,
19678 IX86_BUILTIN_CMPLTPS,
19679 IX86_BUILTIN_CMPLEPS,
19680 IX86_BUILTIN_CMPGTPS,
19681 IX86_BUILTIN_CMPGEPS,
19682 IX86_BUILTIN_CMPNEQPS,
19683 IX86_BUILTIN_CMPNLTPS,
19684 IX86_BUILTIN_CMPNLEPS,
19685 IX86_BUILTIN_CMPNGTPS,
19686 IX86_BUILTIN_CMPNGEPS,
19687 IX86_BUILTIN_CMPORDPS,
19688 IX86_BUILTIN_CMPUNORDPS,
19689 IX86_BUILTIN_CMPEQSS,
19690 IX86_BUILTIN_CMPLTSS,
19691 IX86_BUILTIN_CMPLESS,
19692 IX86_BUILTIN_CMPNEQSS,
19693 IX86_BUILTIN_CMPNLTSS,
19694 IX86_BUILTIN_CMPNLESS,
19695 IX86_BUILTIN_CMPNGTSS,
19696 IX86_BUILTIN_CMPNGESS,
19697 IX86_BUILTIN_CMPORDSS,
19698 IX86_BUILTIN_CMPUNORDSS,
19700 IX86_BUILTIN_COMIEQSS,
19701 IX86_BUILTIN_COMILTSS,
19702 IX86_BUILTIN_COMILESS,
19703 IX86_BUILTIN_COMIGTSS,
19704 IX86_BUILTIN_COMIGESS,
19705 IX86_BUILTIN_COMINEQSS,
19706 IX86_BUILTIN_UCOMIEQSS,
19707 IX86_BUILTIN_UCOMILTSS,
19708 IX86_BUILTIN_UCOMILESS,
19709 IX86_BUILTIN_UCOMIGTSS,
19710 IX86_BUILTIN_UCOMIGESS,
19711 IX86_BUILTIN_UCOMINEQSS,
19713 IX86_BUILTIN_CVTPI2PS,
19714 IX86_BUILTIN_CVTPS2PI,
19715 IX86_BUILTIN_CVTSI2SS,
19716 IX86_BUILTIN_CVTSI642SS,
19717 IX86_BUILTIN_CVTSS2SI,
19718 IX86_BUILTIN_CVTSS2SI64,
19719 IX86_BUILTIN_CVTTPS2PI,
19720 IX86_BUILTIN_CVTTSS2SI,
19721 IX86_BUILTIN_CVTTSS2SI64,
19723 IX86_BUILTIN_MAXPS,
19724 IX86_BUILTIN_MAXSS,
19725 IX86_BUILTIN_MINPS,
19726 IX86_BUILTIN_MINSS,
19728 IX86_BUILTIN_LOADUPS,
19729 IX86_BUILTIN_STOREUPS,
19730 IX86_BUILTIN_MOVSS,
19732 IX86_BUILTIN_MOVHLPS,
19733 IX86_BUILTIN_MOVLHPS,
19734 IX86_BUILTIN_LOADHPS,
19735 IX86_BUILTIN_LOADLPS,
19736 IX86_BUILTIN_STOREHPS,
19737 IX86_BUILTIN_STORELPS,
19739 IX86_BUILTIN_MASKMOVQ,
19740 IX86_BUILTIN_MOVMSKPS,
19741 IX86_BUILTIN_PMOVMSKB,
19743 IX86_BUILTIN_MOVNTPS,
19744 IX86_BUILTIN_MOVNTQ,
19746 IX86_BUILTIN_LOADDQU,
19747 IX86_BUILTIN_STOREDQU,
19749 IX86_BUILTIN_PACKSSWB,
19750 IX86_BUILTIN_PACKSSDW,
19751 IX86_BUILTIN_PACKUSWB,
19753 IX86_BUILTIN_PADDB,
19754 IX86_BUILTIN_PADDW,
19755 IX86_BUILTIN_PADDD,
19756 IX86_BUILTIN_PADDQ,
19757 IX86_BUILTIN_PADDSB,
19758 IX86_BUILTIN_PADDSW,
19759 IX86_BUILTIN_PADDUSB,
19760 IX86_BUILTIN_PADDUSW,
19761 IX86_BUILTIN_PSUBB,
19762 IX86_BUILTIN_PSUBW,
19763 IX86_BUILTIN_PSUBD,
19764 IX86_BUILTIN_PSUBQ,
19765 IX86_BUILTIN_PSUBSB,
19766 IX86_BUILTIN_PSUBSW,
19767 IX86_BUILTIN_PSUBUSB,
19768 IX86_BUILTIN_PSUBUSW,
19771 IX86_BUILTIN_PANDN,
19775 IX86_BUILTIN_PAVGB,
19776 IX86_BUILTIN_PAVGW,
19778 IX86_BUILTIN_PCMPEQB,
19779 IX86_BUILTIN_PCMPEQW,
19780 IX86_BUILTIN_PCMPEQD,
19781 IX86_BUILTIN_PCMPGTB,
19782 IX86_BUILTIN_PCMPGTW,
19783 IX86_BUILTIN_PCMPGTD,
19785 IX86_BUILTIN_PMADDWD,
19787 IX86_BUILTIN_PMAXSW,
19788 IX86_BUILTIN_PMAXUB,
19789 IX86_BUILTIN_PMINSW,
19790 IX86_BUILTIN_PMINUB,
19792 IX86_BUILTIN_PMULHUW,
19793 IX86_BUILTIN_PMULHW,
19794 IX86_BUILTIN_PMULLW,
19796 IX86_BUILTIN_PSADBW,
19797 IX86_BUILTIN_PSHUFW,
19799 IX86_BUILTIN_PSLLW,
19800 IX86_BUILTIN_PSLLD,
19801 IX86_BUILTIN_PSLLQ,
19802 IX86_BUILTIN_PSRAW,
19803 IX86_BUILTIN_PSRAD,
19804 IX86_BUILTIN_PSRLW,
19805 IX86_BUILTIN_PSRLD,
19806 IX86_BUILTIN_PSRLQ,
19807 IX86_BUILTIN_PSLLWI,
19808 IX86_BUILTIN_PSLLDI,
19809 IX86_BUILTIN_PSLLQI,
19810 IX86_BUILTIN_PSRAWI,
19811 IX86_BUILTIN_PSRADI,
19812 IX86_BUILTIN_PSRLWI,
19813 IX86_BUILTIN_PSRLDI,
19814 IX86_BUILTIN_PSRLQI,
19816 IX86_BUILTIN_PUNPCKHBW,
19817 IX86_BUILTIN_PUNPCKHWD,
19818 IX86_BUILTIN_PUNPCKHDQ,
19819 IX86_BUILTIN_PUNPCKLBW,
19820 IX86_BUILTIN_PUNPCKLWD,
19821 IX86_BUILTIN_PUNPCKLDQ,
19823 IX86_BUILTIN_SHUFPS,
19825 IX86_BUILTIN_RCPPS,
19826 IX86_BUILTIN_RCPSS,
19827 IX86_BUILTIN_RSQRTPS,
19828 IX86_BUILTIN_RSQRTPS_NR,
19829 IX86_BUILTIN_RSQRTSS,
19830 IX86_BUILTIN_RSQRTF,
19831 IX86_BUILTIN_SQRTPS,
19832 IX86_BUILTIN_SQRTPS_NR,
19833 IX86_BUILTIN_SQRTSS,
19835 IX86_BUILTIN_UNPCKHPS,
19836 IX86_BUILTIN_UNPCKLPS,
19838 IX86_BUILTIN_ANDPS,
19839 IX86_BUILTIN_ANDNPS,
19841 IX86_BUILTIN_XORPS,
19844 IX86_BUILTIN_LDMXCSR,
19845 IX86_BUILTIN_STMXCSR,
19846 IX86_BUILTIN_SFENCE,
19848 /* 3DNow! Original */
19849 IX86_BUILTIN_FEMMS,
19850 IX86_BUILTIN_PAVGUSB,
19851 IX86_BUILTIN_PF2ID,
19852 IX86_BUILTIN_PFACC,
19853 IX86_BUILTIN_PFADD,
19854 IX86_BUILTIN_PFCMPEQ,
19855 IX86_BUILTIN_PFCMPGE,
19856 IX86_BUILTIN_PFCMPGT,
19857 IX86_BUILTIN_PFMAX,
19858 IX86_BUILTIN_PFMIN,
19859 IX86_BUILTIN_PFMUL,
19860 IX86_BUILTIN_PFRCP,
19861 IX86_BUILTIN_PFRCPIT1,
19862 IX86_BUILTIN_PFRCPIT2,
19863 IX86_BUILTIN_PFRSQIT1,
19864 IX86_BUILTIN_PFRSQRT,
19865 IX86_BUILTIN_PFSUB,
19866 IX86_BUILTIN_PFSUBR,
19867 IX86_BUILTIN_PI2FD,
19868 IX86_BUILTIN_PMULHRW,
19870 /* 3DNow! Athlon Extensions */
19871 IX86_BUILTIN_PF2IW,
19872 IX86_BUILTIN_PFNACC,
19873 IX86_BUILTIN_PFPNACC,
19874 IX86_BUILTIN_PI2FW,
19875 IX86_BUILTIN_PSWAPDSI,
19876 IX86_BUILTIN_PSWAPDSF,
19879 IX86_BUILTIN_ADDPD,
19880 IX86_BUILTIN_ADDSD,
19881 IX86_BUILTIN_DIVPD,
19882 IX86_BUILTIN_DIVSD,
19883 IX86_BUILTIN_MULPD,
19884 IX86_BUILTIN_MULSD,
19885 IX86_BUILTIN_SUBPD,
19886 IX86_BUILTIN_SUBSD,
19888 IX86_BUILTIN_CMPEQPD,
19889 IX86_BUILTIN_CMPLTPD,
19890 IX86_BUILTIN_CMPLEPD,
19891 IX86_BUILTIN_CMPGTPD,
19892 IX86_BUILTIN_CMPGEPD,
19893 IX86_BUILTIN_CMPNEQPD,
19894 IX86_BUILTIN_CMPNLTPD,
19895 IX86_BUILTIN_CMPNLEPD,
19896 IX86_BUILTIN_CMPNGTPD,
19897 IX86_BUILTIN_CMPNGEPD,
19898 IX86_BUILTIN_CMPORDPD,
19899 IX86_BUILTIN_CMPUNORDPD,
19900 IX86_BUILTIN_CMPEQSD,
19901 IX86_BUILTIN_CMPLTSD,
19902 IX86_BUILTIN_CMPLESD,
19903 IX86_BUILTIN_CMPNEQSD,
19904 IX86_BUILTIN_CMPNLTSD,
19905 IX86_BUILTIN_CMPNLESD,
19906 IX86_BUILTIN_CMPORDSD,
19907 IX86_BUILTIN_CMPUNORDSD,
19909 IX86_BUILTIN_COMIEQSD,
19910 IX86_BUILTIN_COMILTSD,
19911 IX86_BUILTIN_COMILESD,
19912 IX86_BUILTIN_COMIGTSD,
19913 IX86_BUILTIN_COMIGESD,
19914 IX86_BUILTIN_COMINEQSD,
19915 IX86_BUILTIN_UCOMIEQSD,
19916 IX86_BUILTIN_UCOMILTSD,
19917 IX86_BUILTIN_UCOMILESD,
19918 IX86_BUILTIN_UCOMIGTSD,
19919 IX86_BUILTIN_UCOMIGESD,
19920 IX86_BUILTIN_UCOMINEQSD,
19922 IX86_BUILTIN_MAXPD,
19923 IX86_BUILTIN_MAXSD,
19924 IX86_BUILTIN_MINPD,
19925 IX86_BUILTIN_MINSD,
19927 IX86_BUILTIN_ANDPD,
19928 IX86_BUILTIN_ANDNPD,
19930 IX86_BUILTIN_XORPD,
19932 IX86_BUILTIN_SQRTPD,
19933 IX86_BUILTIN_SQRTSD,
19935 IX86_BUILTIN_UNPCKHPD,
19936 IX86_BUILTIN_UNPCKLPD,
19938 IX86_BUILTIN_SHUFPD,
19940 IX86_BUILTIN_LOADUPD,
19941 IX86_BUILTIN_STOREUPD,
19942 IX86_BUILTIN_MOVSD,
19944 IX86_BUILTIN_LOADHPD,
19945 IX86_BUILTIN_LOADLPD,
19947 IX86_BUILTIN_CVTDQ2PD,
19948 IX86_BUILTIN_CVTDQ2PS,
19950 IX86_BUILTIN_CVTPD2DQ,
19951 IX86_BUILTIN_CVTPD2PI,
19952 IX86_BUILTIN_CVTPD2PS,
19953 IX86_BUILTIN_CVTTPD2DQ,
19954 IX86_BUILTIN_CVTTPD2PI,
19956 IX86_BUILTIN_CVTPI2PD,
19957 IX86_BUILTIN_CVTSI2SD,
19958 IX86_BUILTIN_CVTSI642SD,
19960 IX86_BUILTIN_CVTSD2SI,
19961 IX86_BUILTIN_CVTSD2SI64,
19962 IX86_BUILTIN_CVTSD2SS,
19963 IX86_BUILTIN_CVTSS2SD,
19964 IX86_BUILTIN_CVTTSD2SI,
19965 IX86_BUILTIN_CVTTSD2SI64,
19967 IX86_BUILTIN_CVTPS2DQ,
19968 IX86_BUILTIN_CVTPS2PD,
19969 IX86_BUILTIN_CVTTPS2DQ,
19971 IX86_BUILTIN_MOVNTI,
19972 IX86_BUILTIN_MOVNTPD,
19973 IX86_BUILTIN_MOVNTDQ,
19975 IX86_BUILTIN_MOVQ128,
19978 IX86_BUILTIN_MASKMOVDQU,
19979 IX86_BUILTIN_MOVMSKPD,
19980 IX86_BUILTIN_PMOVMSKB128,
19982 IX86_BUILTIN_PACKSSWB128,
19983 IX86_BUILTIN_PACKSSDW128,
19984 IX86_BUILTIN_PACKUSWB128,
19986 IX86_BUILTIN_PADDB128,
19987 IX86_BUILTIN_PADDW128,
19988 IX86_BUILTIN_PADDD128,
19989 IX86_BUILTIN_PADDQ128,
19990 IX86_BUILTIN_PADDSB128,
19991 IX86_BUILTIN_PADDSW128,
19992 IX86_BUILTIN_PADDUSB128,
19993 IX86_BUILTIN_PADDUSW128,
19994 IX86_BUILTIN_PSUBB128,
19995 IX86_BUILTIN_PSUBW128,
19996 IX86_BUILTIN_PSUBD128,
19997 IX86_BUILTIN_PSUBQ128,
19998 IX86_BUILTIN_PSUBSB128,
19999 IX86_BUILTIN_PSUBSW128,
20000 IX86_BUILTIN_PSUBUSB128,
20001 IX86_BUILTIN_PSUBUSW128,
20003 IX86_BUILTIN_PAND128,
20004 IX86_BUILTIN_PANDN128,
20005 IX86_BUILTIN_POR128,
20006 IX86_BUILTIN_PXOR128,
20008 IX86_BUILTIN_PAVGB128,
20009 IX86_BUILTIN_PAVGW128,
20011 IX86_BUILTIN_PCMPEQB128,
20012 IX86_BUILTIN_PCMPEQW128,
20013 IX86_BUILTIN_PCMPEQD128,
20014 IX86_BUILTIN_PCMPGTB128,
20015 IX86_BUILTIN_PCMPGTW128,
20016 IX86_BUILTIN_PCMPGTD128,
20018 IX86_BUILTIN_PMADDWD128,
20020 IX86_BUILTIN_PMAXSW128,
20021 IX86_BUILTIN_PMAXUB128,
20022 IX86_BUILTIN_PMINSW128,
20023 IX86_BUILTIN_PMINUB128,
20025 IX86_BUILTIN_PMULUDQ,
20026 IX86_BUILTIN_PMULUDQ128,
20027 IX86_BUILTIN_PMULHUW128,
20028 IX86_BUILTIN_PMULHW128,
20029 IX86_BUILTIN_PMULLW128,
20031 IX86_BUILTIN_PSADBW128,
20032 IX86_BUILTIN_PSHUFHW,
20033 IX86_BUILTIN_PSHUFLW,
20034 IX86_BUILTIN_PSHUFD,
20036 IX86_BUILTIN_PSLLDQI128,
20037 IX86_BUILTIN_PSLLWI128,
20038 IX86_BUILTIN_PSLLDI128,
20039 IX86_BUILTIN_PSLLQI128,
20040 IX86_BUILTIN_PSRAWI128,
20041 IX86_BUILTIN_PSRADI128,
20042 IX86_BUILTIN_PSRLDQI128,
20043 IX86_BUILTIN_PSRLWI128,
20044 IX86_BUILTIN_PSRLDI128,
20045 IX86_BUILTIN_PSRLQI128,
20047 IX86_BUILTIN_PSLLDQ128,
20048 IX86_BUILTIN_PSLLW128,
20049 IX86_BUILTIN_PSLLD128,
20050 IX86_BUILTIN_PSLLQ128,
20051 IX86_BUILTIN_PSRAW128,
20052 IX86_BUILTIN_PSRAD128,
20053 IX86_BUILTIN_PSRLW128,
20054 IX86_BUILTIN_PSRLD128,
20055 IX86_BUILTIN_PSRLQ128,
20057 IX86_BUILTIN_PUNPCKHBW128,
20058 IX86_BUILTIN_PUNPCKHWD128,
20059 IX86_BUILTIN_PUNPCKHDQ128,
20060 IX86_BUILTIN_PUNPCKHQDQ128,
20061 IX86_BUILTIN_PUNPCKLBW128,
20062 IX86_BUILTIN_PUNPCKLWD128,
20063 IX86_BUILTIN_PUNPCKLDQ128,
20064 IX86_BUILTIN_PUNPCKLQDQ128,
20066 IX86_BUILTIN_CLFLUSH,
20067 IX86_BUILTIN_MFENCE,
20068 IX86_BUILTIN_LFENCE,
20071 IX86_BUILTIN_ADDSUBPS,
20072 IX86_BUILTIN_HADDPS,
20073 IX86_BUILTIN_HSUBPS,
20074 IX86_BUILTIN_MOVSHDUP,
20075 IX86_BUILTIN_MOVSLDUP,
20076 IX86_BUILTIN_ADDSUBPD,
20077 IX86_BUILTIN_HADDPD,
20078 IX86_BUILTIN_HSUBPD,
20079 IX86_BUILTIN_LDDQU,
20081 IX86_BUILTIN_MONITOR,
20082 IX86_BUILTIN_MWAIT,
20085 IX86_BUILTIN_PHADDW,
20086 IX86_BUILTIN_PHADDD,
20087 IX86_BUILTIN_PHADDSW,
20088 IX86_BUILTIN_PHSUBW,
20089 IX86_BUILTIN_PHSUBD,
20090 IX86_BUILTIN_PHSUBSW,
20091 IX86_BUILTIN_PMADDUBSW,
20092 IX86_BUILTIN_PMULHRSW,
20093 IX86_BUILTIN_PSHUFB,
20094 IX86_BUILTIN_PSIGNB,
20095 IX86_BUILTIN_PSIGNW,
20096 IX86_BUILTIN_PSIGND,
20097 IX86_BUILTIN_PALIGNR,
20098 IX86_BUILTIN_PABSB,
20099 IX86_BUILTIN_PABSW,
20100 IX86_BUILTIN_PABSD,
20102 IX86_BUILTIN_PHADDW128,
20103 IX86_BUILTIN_PHADDD128,
20104 IX86_BUILTIN_PHADDSW128,
20105 IX86_BUILTIN_PHSUBW128,
20106 IX86_BUILTIN_PHSUBD128,
20107 IX86_BUILTIN_PHSUBSW128,
20108 IX86_BUILTIN_PMADDUBSW128,
20109 IX86_BUILTIN_PMULHRSW128,
20110 IX86_BUILTIN_PSHUFB128,
20111 IX86_BUILTIN_PSIGNB128,
20112 IX86_BUILTIN_PSIGNW128,
20113 IX86_BUILTIN_PSIGND128,
20114 IX86_BUILTIN_PALIGNR128,
20115 IX86_BUILTIN_PABSB128,
20116 IX86_BUILTIN_PABSW128,
20117 IX86_BUILTIN_PABSD128,
20119 /* AMDFAM10 - SSE4A New Instructions. */
20120 IX86_BUILTIN_MOVNTSD,
20121 IX86_BUILTIN_MOVNTSS,
20122 IX86_BUILTIN_EXTRQI,
20123 IX86_BUILTIN_EXTRQ,
20124 IX86_BUILTIN_INSERTQI,
20125 IX86_BUILTIN_INSERTQ,
20128 IX86_BUILTIN_BLENDPD,
20129 IX86_BUILTIN_BLENDPS,
20130 IX86_BUILTIN_BLENDVPD,
20131 IX86_BUILTIN_BLENDVPS,
20132 IX86_BUILTIN_PBLENDVB128,
20133 IX86_BUILTIN_PBLENDW128,
20138 IX86_BUILTIN_INSERTPS128,
20140 IX86_BUILTIN_MOVNTDQA,
20141 IX86_BUILTIN_MPSADBW128,
20142 IX86_BUILTIN_PACKUSDW128,
20143 IX86_BUILTIN_PCMPEQQ,
20144 IX86_BUILTIN_PHMINPOSUW128,
20146 IX86_BUILTIN_PMAXSB128,
20147 IX86_BUILTIN_PMAXSD128,
20148 IX86_BUILTIN_PMAXUD128,
20149 IX86_BUILTIN_PMAXUW128,
20151 IX86_BUILTIN_PMINSB128,
20152 IX86_BUILTIN_PMINSD128,
20153 IX86_BUILTIN_PMINUD128,
20154 IX86_BUILTIN_PMINUW128,
20156 IX86_BUILTIN_PMOVSXBW128,
20157 IX86_BUILTIN_PMOVSXBD128,
20158 IX86_BUILTIN_PMOVSXBQ128,
20159 IX86_BUILTIN_PMOVSXWD128,
20160 IX86_BUILTIN_PMOVSXWQ128,
20161 IX86_BUILTIN_PMOVSXDQ128,
20163 IX86_BUILTIN_PMOVZXBW128,
20164 IX86_BUILTIN_PMOVZXBD128,
20165 IX86_BUILTIN_PMOVZXBQ128,
20166 IX86_BUILTIN_PMOVZXWD128,
20167 IX86_BUILTIN_PMOVZXWQ128,
20168 IX86_BUILTIN_PMOVZXDQ128,
20170 IX86_BUILTIN_PMULDQ128,
20171 IX86_BUILTIN_PMULLD128,
20173 IX86_BUILTIN_ROUNDPD,
20174 IX86_BUILTIN_ROUNDPS,
20175 IX86_BUILTIN_ROUNDSD,
20176 IX86_BUILTIN_ROUNDSS,
20178 IX86_BUILTIN_PTESTZ,
20179 IX86_BUILTIN_PTESTC,
20180 IX86_BUILTIN_PTESTNZC,
20182 IX86_BUILTIN_VEC_INIT_V2SI,
20183 IX86_BUILTIN_VEC_INIT_V4HI,
20184 IX86_BUILTIN_VEC_INIT_V8QI,
20185 IX86_BUILTIN_VEC_EXT_V2DF,
20186 IX86_BUILTIN_VEC_EXT_V2DI,
20187 IX86_BUILTIN_VEC_EXT_V4SF,
20188 IX86_BUILTIN_VEC_EXT_V4SI,
20189 IX86_BUILTIN_VEC_EXT_V8HI,
20190 IX86_BUILTIN_VEC_EXT_V2SI,
20191 IX86_BUILTIN_VEC_EXT_V4HI,
20192 IX86_BUILTIN_VEC_EXT_V16QI,
20193 IX86_BUILTIN_VEC_SET_V2DI,
20194 IX86_BUILTIN_VEC_SET_V4SF,
20195 IX86_BUILTIN_VEC_SET_V4SI,
20196 IX86_BUILTIN_VEC_SET_V8HI,
20197 IX86_BUILTIN_VEC_SET_V4HI,
20198 IX86_BUILTIN_VEC_SET_V16QI,
20200 IX86_BUILTIN_VEC_PACK_SFIX,
20203 IX86_BUILTIN_CRC32QI,
20204 IX86_BUILTIN_CRC32HI,
20205 IX86_BUILTIN_CRC32SI,
20206 IX86_BUILTIN_CRC32DI,
20208 IX86_BUILTIN_PCMPESTRI128,
20209 IX86_BUILTIN_PCMPESTRM128,
20210 IX86_BUILTIN_PCMPESTRA128,
20211 IX86_BUILTIN_PCMPESTRC128,
20212 IX86_BUILTIN_PCMPESTRO128,
20213 IX86_BUILTIN_PCMPESTRS128,
20214 IX86_BUILTIN_PCMPESTRZ128,
20215 IX86_BUILTIN_PCMPISTRI128,
20216 IX86_BUILTIN_PCMPISTRM128,
20217 IX86_BUILTIN_PCMPISTRA128,
20218 IX86_BUILTIN_PCMPISTRC128,
20219 IX86_BUILTIN_PCMPISTRO128,
20220 IX86_BUILTIN_PCMPISTRS128,
20221 IX86_BUILTIN_PCMPISTRZ128,
20223 IX86_BUILTIN_PCMPGTQ,
20225 /* AES instructions */
20226 IX86_BUILTIN_AESENC128,
20227 IX86_BUILTIN_AESENCLAST128,
20228 IX86_BUILTIN_AESDEC128,
20229 IX86_BUILTIN_AESDECLAST128,
20230 IX86_BUILTIN_AESIMC128,
20231 IX86_BUILTIN_AESKEYGENASSIST128,
20233 /* PCLMUL instruction */
20234 IX86_BUILTIN_PCLMULQDQ128,
20237 IX86_BUILTIN_ADDPD256,
20238 IX86_BUILTIN_ADDPS256,
20239 IX86_BUILTIN_ADDSUBPD256,
20240 IX86_BUILTIN_ADDSUBPS256,
20241 IX86_BUILTIN_ANDPD256,
20242 IX86_BUILTIN_ANDPS256,
20243 IX86_BUILTIN_ANDNPD256,
20244 IX86_BUILTIN_ANDNPS256,
20245 IX86_BUILTIN_BLENDPD256,
20246 IX86_BUILTIN_BLENDPS256,
20247 IX86_BUILTIN_BLENDVPD256,
20248 IX86_BUILTIN_BLENDVPS256,
20249 IX86_BUILTIN_DIVPD256,
20250 IX86_BUILTIN_DIVPS256,
20251 IX86_BUILTIN_DPPS256,
20252 IX86_BUILTIN_HADDPD256,
20253 IX86_BUILTIN_HADDPS256,
20254 IX86_BUILTIN_HSUBPD256,
20255 IX86_BUILTIN_HSUBPS256,
20256 IX86_BUILTIN_MAXPD256,
20257 IX86_BUILTIN_MAXPS256,
20258 IX86_BUILTIN_MINPD256,
20259 IX86_BUILTIN_MINPS256,
20260 IX86_BUILTIN_MULPD256,
20261 IX86_BUILTIN_MULPS256,
20262 IX86_BUILTIN_ORPD256,
20263 IX86_BUILTIN_ORPS256,
20264 IX86_BUILTIN_SHUFPD256,
20265 IX86_BUILTIN_SHUFPS256,
20266 IX86_BUILTIN_SUBPD256,
20267 IX86_BUILTIN_SUBPS256,
20268 IX86_BUILTIN_XORPD256,
20269 IX86_BUILTIN_XORPS256,
20270 IX86_BUILTIN_CMPSD,
20271 IX86_BUILTIN_CMPSS,
20272 IX86_BUILTIN_CMPPD,
20273 IX86_BUILTIN_CMPPS,
20274 IX86_BUILTIN_CMPPD256,
20275 IX86_BUILTIN_CMPPS256,
20276 IX86_BUILTIN_CVTDQ2PD256,
20277 IX86_BUILTIN_CVTDQ2PS256,
20278 IX86_BUILTIN_CVTPD2PS256,
20279 IX86_BUILTIN_CVTPS2DQ256,
20280 IX86_BUILTIN_CVTPS2PD256,
20281 IX86_BUILTIN_CVTTPD2DQ256,
20282 IX86_BUILTIN_CVTPD2DQ256,
20283 IX86_BUILTIN_CVTTPS2DQ256,
20284 IX86_BUILTIN_EXTRACTF128PD256,
20285 IX86_BUILTIN_EXTRACTF128PS256,
20286 IX86_BUILTIN_EXTRACTF128SI256,
20287 IX86_BUILTIN_VZEROALL,
20288 IX86_BUILTIN_VZEROUPPER,
20289 IX86_BUILTIN_VZEROUPPER_REX64,
20290 IX86_BUILTIN_VPERMILVARPD,
20291 IX86_BUILTIN_VPERMILVARPS,
20292 IX86_BUILTIN_VPERMILVARPD256,
20293 IX86_BUILTIN_VPERMILVARPS256,
20294 IX86_BUILTIN_VPERMILPD,
20295 IX86_BUILTIN_VPERMILPS,
20296 IX86_BUILTIN_VPERMILPD256,
20297 IX86_BUILTIN_VPERMILPS256,
20298 IX86_BUILTIN_VPERM2F128PD256,
20299 IX86_BUILTIN_VPERM2F128PS256,
20300 IX86_BUILTIN_VPERM2F128SI256,
20301 IX86_BUILTIN_VBROADCASTSS,
20302 IX86_BUILTIN_VBROADCASTSD256,
20303 IX86_BUILTIN_VBROADCASTSS256,
20304 IX86_BUILTIN_VBROADCASTPD256,
20305 IX86_BUILTIN_VBROADCASTPS256,
20306 IX86_BUILTIN_VINSERTF128PD256,
20307 IX86_BUILTIN_VINSERTF128PS256,
20308 IX86_BUILTIN_VINSERTF128SI256,
20309 IX86_BUILTIN_LOADUPD256,
20310 IX86_BUILTIN_LOADUPS256,
20311 IX86_BUILTIN_STOREUPD256,
20312 IX86_BUILTIN_STOREUPS256,
20313 IX86_BUILTIN_LDDQU256,
20314 IX86_BUILTIN_MOVNTDQ256,
20315 IX86_BUILTIN_MOVNTPD256,
20316 IX86_BUILTIN_MOVNTPS256,
20317 IX86_BUILTIN_LOADDQU256,
20318 IX86_BUILTIN_STOREDQU256,
20319 IX86_BUILTIN_MASKLOADPD,
20320 IX86_BUILTIN_MASKLOADPS,
20321 IX86_BUILTIN_MASKSTOREPD,
20322 IX86_BUILTIN_MASKSTOREPS,
20323 IX86_BUILTIN_MASKLOADPD256,
20324 IX86_BUILTIN_MASKLOADPS256,
20325 IX86_BUILTIN_MASKSTOREPD256,
20326 IX86_BUILTIN_MASKSTOREPS256,
20327 IX86_BUILTIN_MOVSHDUP256,
20328 IX86_BUILTIN_MOVSLDUP256,
20329 IX86_BUILTIN_MOVDDUP256,
20331 IX86_BUILTIN_SQRTPD256,
20332 IX86_BUILTIN_SQRTPS256,
20333 IX86_BUILTIN_SQRTPS_NR256,
20334 IX86_BUILTIN_RSQRTPS256,
20335 IX86_BUILTIN_RSQRTPS_NR256,
20337 IX86_BUILTIN_RCPPS256,
20339 IX86_BUILTIN_ROUNDPD256,
20340 IX86_BUILTIN_ROUNDPS256,
20342 IX86_BUILTIN_UNPCKHPD256,
20343 IX86_BUILTIN_UNPCKLPD256,
20344 IX86_BUILTIN_UNPCKHPS256,
20345 IX86_BUILTIN_UNPCKLPS256,
20347 IX86_BUILTIN_SI256_SI,
20348 IX86_BUILTIN_PS256_PS,
20349 IX86_BUILTIN_PD256_PD,
20350 IX86_BUILTIN_SI_SI256,
20351 IX86_BUILTIN_PS_PS256,
20352 IX86_BUILTIN_PD_PD256,
20354 IX86_BUILTIN_VTESTZPD,
20355 IX86_BUILTIN_VTESTCPD,
20356 IX86_BUILTIN_VTESTNZCPD,
20357 IX86_BUILTIN_VTESTZPS,
20358 IX86_BUILTIN_VTESTCPS,
20359 IX86_BUILTIN_VTESTNZCPS,
20360 IX86_BUILTIN_VTESTZPD256,
20361 IX86_BUILTIN_VTESTCPD256,
20362 IX86_BUILTIN_VTESTNZCPD256,
20363 IX86_BUILTIN_VTESTZPS256,
20364 IX86_BUILTIN_VTESTCPS256,
20365 IX86_BUILTIN_VTESTNZCPS256,
20366 IX86_BUILTIN_PTESTZ256,
20367 IX86_BUILTIN_PTESTC256,
20368 IX86_BUILTIN_PTESTNZC256,
20370 IX86_BUILTIN_MOVMSKPD256,
20371 IX86_BUILTIN_MOVMSKPS256,
20373 /* TFmode support builtins. */
20375 IX86_BUILTIN_FABSQ,
20376 IX86_BUILTIN_COPYSIGNQ,
20378 /* SSE5 instructions */
20379 IX86_BUILTIN_FMADDSS,
20380 IX86_BUILTIN_FMADDSD,
20381 IX86_BUILTIN_FMADDPS,
20382 IX86_BUILTIN_FMADDPD,
20383 IX86_BUILTIN_FMSUBSS,
20384 IX86_BUILTIN_FMSUBSD,
20385 IX86_BUILTIN_FMSUBPS,
20386 IX86_BUILTIN_FMSUBPD,
20387 IX86_BUILTIN_FNMADDSS,
20388 IX86_BUILTIN_FNMADDSD,
20389 IX86_BUILTIN_FNMADDPS,
20390 IX86_BUILTIN_FNMADDPD,
20391 IX86_BUILTIN_FNMSUBSS,
20392 IX86_BUILTIN_FNMSUBSD,
20393 IX86_BUILTIN_FNMSUBPS,
20394 IX86_BUILTIN_FNMSUBPD,
20395 IX86_BUILTIN_PCMOV,
20396 IX86_BUILTIN_PCMOV_V2DI,
20397 IX86_BUILTIN_PCMOV_V4SI,
20398 IX86_BUILTIN_PCMOV_V8HI,
20399 IX86_BUILTIN_PCMOV_V16QI,
20400 IX86_BUILTIN_PCMOV_V4SF,
20401 IX86_BUILTIN_PCMOV_V2DF,
20402 IX86_BUILTIN_PPERM,
20403 IX86_BUILTIN_PERMPS,
20404 IX86_BUILTIN_PERMPD,
20405 IX86_BUILTIN_PMACSSWW,
20406 IX86_BUILTIN_PMACSWW,
20407 IX86_BUILTIN_PMACSSWD,
20408 IX86_BUILTIN_PMACSWD,
20409 IX86_BUILTIN_PMACSSDD,
20410 IX86_BUILTIN_PMACSDD,
20411 IX86_BUILTIN_PMACSSDQL,
20412 IX86_BUILTIN_PMACSSDQH,
20413 IX86_BUILTIN_PMACSDQL,
20414 IX86_BUILTIN_PMACSDQH,
20415 IX86_BUILTIN_PMADCSSWD,
20416 IX86_BUILTIN_PMADCSWD,
20417 IX86_BUILTIN_PHADDBW,
20418 IX86_BUILTIN_PHADDBD,
20419 IX86_BUILTIN_PHADDBQ,
20420 IX86_BUILTIN_PHADDWD,
20421 IX86_BUILTIN_PHADDWQ,
20422 IX86_BUILTIN_PHADDDQ,
20423 IX86_BUILTIN_PHADDUBW,
20424 IX86_BUILTIN_PHADDUBD,
20425 IX86_BUILTIN_PHADDUBQ,
20426 IX86_BUILTIN_PHADDUWD,
20427 IX86_BUILTIN_PHADDUWQ,
20428 IX86_BUILTIN_PHADDUDQ,
20429 IX86_BUILTIN_PHSUBBW,
20430 IX86_BUILTIN_PHSUBWD,
20431 IX86_BUILTIN_PHSUBDQ,
20432 IX86_BUILTIN_PROTB,
20433 IX86_BUILTIN_PROTW,
20434 IX86_BUILTIN_PROTD,
20435 IX86_BUILTIN_PROTQ,
20436 IX86_BUILTIN_PROTB_IMM,
20437 IX86_BUILTIN_PROTW_IMM,
20438 IX86_BUILTIN_PROTD_IMM,
20439 IX86_BUILTIN_PROTQ_IMM,
20440 IX86_BUILTIN_PSHLB,
20441 IX86_BUILTIN_PSHLW,
20442 IX86_BUILTIN_PSHLD,
20443 IX86_BUILTIN_PSHLQ,
20444 IX86_BUILTIN_PSHAB,
20445 IX86_BUILTIN_PSHAW,
20446 IX86_BUILTIN_PSHAD,
20447 IX86_BUILTIN_PSHAQ,
20448 IX86_BUILTIN_FRCZSS,
20449 IX86_BUILTIN_FRCZSD,
20450 IX86_BUILTIN_FRCZPS,
20451 IX86_BUILTIN_FRCZPD,
20452 IX86_BUILTIN_CVTPH2PS,
20453 IX86_BUILTIN_CVTPS2PH,
20455 IX86_BUILTIN_COMEQSS,
20456 IX86_BUILTIN_COMNESS,
20457 IX86_BUILTIN_COMLTSS,
20458 IX86_BUILTIN_COMLESS,
20459 IX86_BUILTIN_COMGTSS,
20460 IX86_BUILTIN_COMGESS,
20461 IX86_BUILTIN_COMUEQSS,
20462 IX86_BUILTIN_COMUNESS,
20463 IX86_BUILTIN_COMULTSS,
20464 IX86_BUILTIN_COMULESS,
20465 IX86_BUILTIN_COMUGTSS,
20466 IX86_BUILTIN_COMUGESS,
20467 IX86_BUILTIN_COMORDSS,
20468 IX86_BUILTIN_COMUNORDSS,
20469 IX86_BUILTIN_COMFALSESS,
20470 IX86_BUILTIN_COMTRUESS,
20472 IX86_BUILTIN_COMEQSD,
20473 IX86_BUILTIN_COMNESD,
20474 IX86_BUILTIN_COMLTSD,
20475 IX86_BUILTIN_COMLESD,
20476 IX86_BUILTIN_COMGTSD,
20477 IX86_BUILTIN_COMGESD,
20478 IX86_BUILTIN_COMUEQSD,
20479 IX86_BUILTIN_COMUNESD,
20480 IX86_BUILTIN_COMULTSD,
20481 IX86_BUILTIN_COMULESD,
20482 IX86_BUILTIN_COMUGTSD,
20483 IX86_BUILTIN_COMUGESD,
20484 IX86_BUILTIN_COMORDSD,
20485 IX86_BUILTIN_COMUNORDSD,
20486 IX86_BUILTIN_COMFALSESD,
20487 IX86_BUILTIN_COMTRUESD,
20489 IX86_BUILTIN_COMEQPS,
20490 IX86_BUILTIN_COMNEPS,
20491 IX86_BUILTIN_COMLTPS,
20492 IX86_BUILTIN_COMLEPS,
20493 IX86_BUILTIN_COMGTPS,
20494 IX86_BUILTIN_COMGEPS,
20495 IX86_BUILTIN_COMUEQPS,
20496 IX86_BUILTIN_COMUNEPS,
20497 IX86_BUILTIN_COMULTPS,
20498 IX86_BUILTIN_COMULEPS,
20499 IX86_BUILTIN_COMUGTPS,
20500 IX86_BUILTIN_COMUGEPS,
20501 IX86_BUILTIN_COMORDPS,
20502 IX86_BUILTIN_COMUNORDPS,
20503 IX86_BUILTIN_COMFALSEPS,
20504 IX86_BUILTIN_COMTRUEPS,
20506 IX86_BUILTIN_COMEQPD,
20507 IX86_BUILTIN_COMNEPD,
20508 IX86_BUILTIN_COMLTPD,
20509 IX86_BUILTIN_COMLEPD,
20510 IX86_BUILTIN_COMGTPD,
20511 IX86_BUILTIN_COMGEPD,
20512 IX86_BUILTIN_COMUEQPD,
20513 IX86_BUILTIN_COMUNEPD,
20514 IX86_BUILTIN_COMULTPD,
20515 IX86_BUILTIN_COMULEPD,
20516 IX86_BUILTIN_COMUGTPD,
20517 IX86_BUILTIN_COMUGEPD,
20518 IX86_BUILTIN_COMORDPD,
20519 IX86_BUILTIN_COMUNORDPD,
20520 IX86_BUILTIN_COMFALSEPD,
20521 IX86_BUILTIN_COMTRUEPD,
20523 IX86_BUILTIN_PCOMEQUB,
20524 IX86_BUILTIN_PCOMNEUB,
20525 IX86_BUILTIN_PCOMLTUB,
20526 IX86_BUILTIN_PCOMLEUB,
20527 IX86_BUILTIN_PCOMGTUB,
20528 IX86_BUILTIN_PCOMGEUB,
20529 IX86_BUILTIN_PCOMFALSEUB,
20530 IX86_BUILTIN_PCOMTRUEUB,
20531 IX86_BUILTIN_PCOMEQUW,
20532 IX86_BUILTIN_PCOMNEUW,
20533 IX86_BUILTIN_PCOMLTUW,
20534 IX86_BUILTIN_PCOMLEUW,
20535 IX86_BUILTIN_PCOMGTUW,
20536 IX86_BUILTIN_PCOMGEUW,
20537 IX86_BUILTIN_PCOMFALSEUW,
20538 IX86_BUILTIN_PCOMTRUEUW,
20539 IX86_BUILTIN_PCOMEQUD,
20540 IX86_BUILTIN_PCOMNEUD,
20541 IX86_BUILTIN_PCOMLTUD,
20542 IX86_BUILTIN_PCOMLEUD,
20543 IX86_BUILTIN_PCOMGTUD,
20544 IX86_BUILTIN_PCOMGEUD,
20545 IX86_BUILTIN_PCOMFALSEUD,
20546 IX86_BUILTIN_PCOMTRUEUD,
20547 IX86_BUILTIN_PCOMEQUQ,
20548 IX86_BUILTIN_PCOMNEUQ,
20549 IX86_BUILTIN_PCOMLTUQ,
20550 IX86_BUILTIN_PCOMLEUQ,
20551 IX86_BUILTIN_PCOMGTUQ,
20552 IX86_BUILTIN_PCOMGEUQ,
20553 IX86_BUILTIN_PCOMFALSEUQ,
20554 IX86_BUILTIN_PCOMTRUEUQ,
20556 IX86_BUILTIN_PCOMEQB,
20557 IX86_BUILTIN_PCOMNEB,
20558 IX86_BUILTIN_PCOMLTB,
20559 IX86_BUILTIN_PCOMLEB,
20560 IX86_BUILTIN_PCOMGTB,
20561 IX86_BUILTIN_PCOMGEB,
20562 IX86_BUILTIN_PCOMFALSEB,
20563 IX86_BUILTIN_PCOMTRUEB,
20564 IX86_BUILTIN_PCOMEQW,
20565 IX86_BUILTIN_PCOMNEW,
20566 IX86_BUILTIN_PCOMLTW,
20567 IX86_BUILTIN_PCOMLEW,
20568 IX86_BUILTIN_PCOMGTW,
20569 IX86_BUILTIN_PCOMGEW,
20570 IX86_BUILTIN_PCOMFALSEW,
20571 IX86_BUILTIN_PCOMTRUEW,
20572 IX86_BUILTIN_PCOMEQD,
20573 IX86_BUILTIN_PCOMNED,
20574 IX86_BUILTIN_PCOMLTD,
20575 IX86_BUILTIN_PCOMLED,
20576 IX86_BUILTIN_PCOMGTD,
20577 IX86_BUILTIN_PCOMGED,
20578 IX86_BUILTIN_PCOMFALSED,
20579 IX86_BUILTIN_PCOMTRUED,
20580 IX86_BUILTIN_PCOMEQQ,
20581 IX86_BUILTIN_PCOMNEQ,
20582 IX86_BUILTIN_PCOMLTQ,
20583 IX86_BUILTIN_PCOMLEQ,
20584 IX86_BUILTIN_PCOMGTQ,
20585 IX86_BUILTIN_PCOMGEQ,
20586 IX86_BUILTIN_PCOMFALSEQ,
20587 IX86_BUILTIN_PCOMTRUEQ,
20592 /* Table for the ix86 builtin decls. */
20593 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
20595 /* Table of all of the builtin functions that are possible with different ISA's
20596 but are waiting to be built until a function is declared to use that
20598 struct builtin_isa GTY(())
20600 tree type; /* builtin type to use in the declaration */
20601 const char *name; /* function name */
20602 int isa; /* isa_flags this builtin is defined for */
20603 bool const_p; /* true if the declaration is constant */
20606 static GTY(()) struct builtin_isa ix86_builtins_isa[(int) IX86_BUILTIN_MAX];
20609 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
20610 * of which isa_flags to use in the ix86_builtins_isa array. Stores the
20611 * function decl in the ix86_builtins array. Returns the function decl or
20612 * NULL_TREE, if the builtin was not added.
20614 * If the front end has a special hook for builtin functions, delay adding
20615 * builtin functions that aren't in the current ISA until the ISA is changed
20616 * with function specific optimization. Doing so, can save about 300K for the
20617 * default compiler. When the builtin is expanded, check at that time whether
20620 * If the front end doesn't have a special hook, record all builtins, even if
20621 * it isn't an instruction set in the current ISA in case the user uses
20622 * function specific options for a different ISA, so that we don't get scope
20623 * errors if a builtin is added in the middle of a function scope. */
20626 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
20628 tree decl = NULL_TREE;
20630 if (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT)
20632 ix86_builtins_isa[(int) code].isa = mask;
20634 if ((mask & ix86_isa_flags) != 0
20635 || (lang_hooks.builtin_function
20636 == lang_hooks.builtin_function_ext_scope))
20639 decl = add_builtin_function (name, type, code, BUILT_IN_MD, NULL,
20641 ix86_builtins[(int) code] = decl;
20642 ix86_builtins_isa[(int) code].type = NULL_TREE;
20646 ix86_builtins[(int) code] = NULL_TREE;
20647 ix86_builtins_isa[(int) code].const_p = false;
20648 ix86_builtins_isa[(int) code].type = type;
20649 ix86_builtins_isa[(int) code].name = name;
20656 /* Like def_builtin, but also marks the function decl "const". */
20659 def_builtin_const (int mask, const char *name, tree type,
20660 enum ix86_builtins code)
20662 tree decl = def_builtin (mask, name, type, code);
20664 TREE_READONLY (decl) = 1;
20666 ix86_builtins_isa[(int) code].const_p = true;
20671 /* Add any new builtin functions for a given ISA that may not have been
20672 declared. This saves a bit of space compared to adding all of the
20673 declarations to the tree, even if we didn't use them. */
20676 ix86_add_new_builtins (int isa)
20681 for (i = 0; i < (int)IX86_BUILTIN_MAX; i++)
20683 if ((ix86_builtins_isa[i].isa & isa) != 0
20684 && ix86_builtins_isa[i].type != NULL_TREE)
20686 decl = add_builtin_function_ext_scope (ix86_builtins_isa[i].name,
20687 ix86_builtins_isa[i].type,
20688 i, BUILT_IN_MD, NULL,
20691 ix86_builtins[i] = decl;
20692 ix86_builtins_isa[i].type = NULL_TREE;
20693 if (ix86_builtins_isa[i].const_p)
20694 TREE_READONLY (decl) = 1;
20699 /* Bits for builtin_description.flag. */
20701 /* Set when we don't support the comparison natively, and should
20702 swap_comparison in order to support it. */
20703 #define BUILTIN_DESC_SWAP_OPERANDS 1
20705 struct builtin_description
20707 const unsigned int mask;
20708 const enum insn_code icode;
20709 const char *const name;
20710 const enum ix86_builtins code;
20711 const enum rtx_code comparison;
20715 static const struct builtin_description bdesc_comi[] =
20717 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
20718 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
20719 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
20720 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
20721 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
20722 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
20723 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
20724 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
20725 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
20726 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
20727 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
20728 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
20729 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
20730 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
20731 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
20732 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
20733 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
20734 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
20735 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
20736 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
20737 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
20738 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
20739 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
20740 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
20743 static const struct builtin_description bdesc_pcmpestr[] =
20746 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
20747 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
20748 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
20749 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
20750 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
20751 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
20752 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
20755 static const struct builtin_description bdesc_pcmpistr[] =
20758 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
20759 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
20760 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
20761 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
20762 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
20763 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
20764 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
20767 /* Special builtin types */
20768 enum ix86_special_builtin_type
20770 SPECIAL_FTYPE_UNKNOWN,
20772 V32QI_FTYPE_PCCHAR,
20773 V16QI_FTYPE_PCCHAR,
20775 V8SF_FTYPE_PCFLOAT,
20777 V4DF_FTYPE_PCDOUBLE,
20778 V4SF_FTYPE_PCFLOAT,
20779 V2DF_FTYPE_PCDOUBLE,
20780 V8SF_FTYPE_PCV8SF_V8SF,
20781 V4DF_FTYPE_PCV4DF_V4DF,
20782 V4SF_FTYPE_V4SF_PCV2SF,
20783 V4SF_FTYPE_PCV4SF_V4SF,
20784 V2DF_FTYPE_V2DF_PCDOUBLE,
20785 V2DF_FTYPE_PCV2DF_V2DF,
20787 VOID_FTYPE_PV2SF_V4SF,
20788 VOID_FTYPE_PV4DI_V4DI,
20789 VOID_FTYPE_PV2DI_V2DI,
20790 VOID_FTYPE_PCHAR_V32QI,
20791 VOID_FTYPE_PCHAR_V16QI,
20792 VOID_FTYPE_PFLOAT_V8SF,
20793 VOID_FTYPE_PFLOAT_V4SF,
20794 VOID_FTYPE_PDOUBLE_V4DF,
20795 VOID_FTYPE_PDOUBLE_V2DF,
20797 VOID_FTYPE_PINT_INT,
20798 VOID_FTYPE_PV8SF_V8SF_V8SF,
20799 VOID_FTYPE_PV4DF_V4DF_V4DF,
20800 VOID_FTYPE_PV4SF_V4SF_V4SF,
20801 VOID_FTYPE_PV2DF_V2DF_V2DF
20804 /* Builtin types */
20805 enum ix86_builtin_type
20808 FLOAT128_FTYPE_FLOAT128,
20810 FLOAT128_FTYPE_FLOAT128_FLOAT128,
20811 INT_FTYPE_V8SF_V8SF_PTEST,
20812 INT_FTYPE_V4DI_V4DI_PTEST,
20813 INT_FTYPE_V4DF_V4DF_PTEST,
20814 INT_FTYPE_V4SF_V4SF_PTEST,
20815 INT_FTYPE_V2DI_V2DI_PTEST,
20816 INT_FTYPE_V2DF_V2DF_PTEST,
20848 V4SF_FTYPE_V4SF_VEC_MERGE,
20857 V2DF_FTYPE_V2DF_VEC_MERGE,
20868 V16QI_FTYPE_V16QI_V16QI,
20869 V16QI_FTYPE_V8HI_V8HI,
20870 V8QI_FTYPE_V8QI_V8QI,
20871 V8QI_FTYPE_V4HI_V4HI,
20872 V8HI_FTYPE_V8HI_V8HI,
20873 V8HI_FTYPE_V8HI_V8HI_COUNT,
20874 V8HI_FTYPE_V16QI_V16QI,
20875 V8HI_FTYPE_V4SI_V4SI,
20876 V8HI_FTYPE_V8HI_SI_COUNT,
20877 V8SF_FTYPE_V8SF_V8SF,
20878 V8SF_FTYPE_V8SF_V8SI,
20879 V4SI_FTYPE_V4SI_V4SI,
20880 V4SI_FTYPE_V4SI_V4SI_COUNT,
20881 V4SI_FTYPE_V8HI_V8HI,
20882 V4SI_FTYPE_V4SF_V4SF,
20883 V4SI_FTYPE_V2DF_V2DF,
20884 V4SI_FTYPE_V4SI_SI_COUNT,
20885 V4HI_FTYPE_V4HI_V4HI,
20886 V4HI_FTYPE_V4HI_V4HI_COUNT,
20887 V4HI_FTYPE_V8QI_V8QI,
20888 V4HI_FTYPE_V2SI_V2SI,
20889 V4HI_FTYPE_V4HI_SI_COUNT,
20890 V4DF_FTYPE_V4DF_V4DF,
20891 V4DF_FTYPE_V4DF_V4DI,
20892 V4SF_FTYPE_V4SF_V4SF,
20893 V4SF_FTYPE_V4SF_V4SF_SWAP,
20894 V4SF_FTYPE_V4SF_V4SI,
20895 V4SF_FTYPE_V4SF_V2SI,
20896 V4SF_FTYPE_V4SF_V2DF,
20897 V4SF_FTYPE_V4SF_DI,
20898 V4SF_FTYPE_V4SF_SI,
20899 V2DI_FTYPE_V2DI_V2DI,
20900 V2DI_FTYPE_V2DI_V2DI_COUNT,
20901 V2DI_FTYPE_V16QI_V16QI,
20902 V2DI_FTYPE_V4SI_V4SI,
20903 V2DI_FTYPE_V2DI_V16QI,
20904 V2DI_FTYPE_V2DF_V2DF,
20905 V2DI_FTYPE_V2DI_SI_COUNT,
20906 V2SI_FTYPE_V2SI_V2SI,
20907 V2SI_FTYPE_V2SI_V2SI_COUNT,
20908 V2SI_FTYPE_V4HI_V4HI,
20909 V2SI_FTYPE_V2SF_V2SF,
20910 V2SI_FTYPE_V2SI_SI_COUNT,
20911 V2DF_FTYPE_V2DF_V2DF,
20912 V2DF_FTYPE_V2DF_V2DF_SWAP,
20913 V2DF_FTYPE_V2DF_V4SF,
20914 V2DF_FTYPE_V2DF_V2DI,
20915 V2DF_FTYPE_V2DF_DI,
20916 V2DF_FTYPE_V2DF_SI,
20917 V2SF_FTYPE_V2SF_V2SF,
20918 V1DI_FTYPE_V1DI_V1DI,
20919 V1DI_FTYPE_V1DI_V1DI_COUNT,
20920 V1DI_FTYPE_V8QI_V8QI,
20921 V1DI_FTYPE_V2SI_V2SI,
20922 V1DI_FTYPE_V1DI_SI_COUNT,
20923 UINT64_FTYPE_UINT64_UINT64,
20924 UINT_FTYPE_UINT_UINT,
20925 UINT_FTYPE_UINT_USHORT,
20926 UINT_FTYPE_UINT_UCHAR,
20927 V8HI_FTYPE_V8HI_INT,
20928 V4SI_FTYPE_V4SI_INT,
20929 V4HI_FTYPE_V4HI_INT,
20930 V8SF_FTYPE_V8SF_INT,
20931 V4SI_FTYPE_V8SI_INT,
20932 V4SF_FTYPE_V8SF_INT,
20933 V2DF_FTYPE_V4DF_INT,
20934 V4DF_FTYPE_V4DF_INT,
20935 V4SF_FTYPE_V4SF_INT,
20936 V2DI_FTYPE_V2DI_INT,
20937 V2DI2TI_FTYPE_V2DI_INT,
20938 V2DF_FTYPE_V2DF_INT,
20939 V16QI_FTYPE_V16QI_V16QI_V16QI,
20940 V8SF_FTYPE_V8SF_V8SF_V8SF,
20941 V4DF_FTYPE_V4DF_V4DF_V4DF,
20942 V4SF_FTYPE_V4SF_V4SF_V4SF,
20943 V2DF_FTYPE_V2DF_V2DF_V2DF,
20944 V16QI_FTYPE_V16QI_V16QI_INT,
20945 V8SI_FTYPE_V8SI_V8SI_INT,
20946 V8SI_FTYPE_V8SI_V4SI_INT,
20947 V8HI_FTYPE_V8HI_V8HI_INT,
20948 V8SF_FTYPE_V8SF_V8SF_INT,
20949 V8SF_FTYPE_V8SF_V4SF_INT,
20950 V4SI_FTYPE_V4SI_V4SI_INT,
20951 V4DF_FTYPE_V4DF_V4DF_INT,
20952 V4DF_FTYPE_V4DF_V2DF_INT,
20953 V4SF_FTYPE_V4SF_V4SF_INT,
20954 V2DI_FTYPE_V2DI_V2DI_INT,
20955 V2DI2TI_FTYPE_V2DI_V2DI_INT,
20956 V1DI2DI_FTYPE_V1DI_V1DI_INT,
20957 V2DF_FTYPE_V2DF_V2DF_INT,
20958 V2DI_FTYPE_V2DI_UINT_UINT,
20959 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
20962 /* Special builtins with variable number of arguments. */
20963 static const struct builtin_description bdesc_special_args[] =
20966 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
20969 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
20972 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20973 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20974 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
20976 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
20977 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
20978 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
20979 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
20981 /* SSE or 3DNow!A */
20982 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20983 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
20986 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20987 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20988 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20989 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
20990 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20991 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
20992 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
20993 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
20994 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
20996 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
20997 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21000 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21003 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
21006 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21007 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21010 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
21011 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, 0, IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
21012 { OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_64BIT, CODE_FOR_avx_vzeroupper_rex64, 0, IX86_BUILTIN_VZEROUPPER_REX64, UNKNOWN, (int) VOID_FTYPE_VOID },
21014 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21015 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastsd256, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21016 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss256, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21017 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_pd256, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
21018 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_ps256, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
21020 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21021 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21022 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21023 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21024 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21025 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
21026 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21028 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
21029 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21030 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21032 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
21033 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
21034 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
21035 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
21036 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
21037 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
21038 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
21039 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
21042 /* Builtins with variable number of arguments. */
21043 static const struct builtin_description bdesc_args[] =
21046 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21047 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21048 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21049 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21050 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21051 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21053 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21054 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21055 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21056 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21057 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21058 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21059 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21060 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21062 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21063 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21065 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21066 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21067 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21068 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21070 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21071 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21072 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21073 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21074 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21075 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21077 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21078 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21079 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21080 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21081 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
21082 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
21084 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21085 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
21086 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21088 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
21090 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21091 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21092 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21093 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21094 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21095 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21097 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21098 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21099 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21100 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21101 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21102 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21104 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21105 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21106 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21107 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21110 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21111 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21112 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21113 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21115 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21116 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21117 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21118 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21119 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21120 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21121 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21122 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21123 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21124 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21125 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21126 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21127 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21128 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21129 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21132 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21133 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21134 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21135 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21136 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21137 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21140 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
21141 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21142 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21143 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21144 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21145 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21146 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21147 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21148 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21149 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21150 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21151 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21153 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21155 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21156 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21157 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21158 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21159 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21160 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21161 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21162 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21164 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21165 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21166 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21167 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21168 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21169 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21170 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21171 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21172 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21173 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21174 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
21175 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21176 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21177 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21178 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21179 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21180 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21181 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21182 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21183 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21184 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21185 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21187 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21188 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21189 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21190 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21192 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21193 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21194 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21195 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21197 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21198 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21199 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21200 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21201 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21203 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
21204 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
21205 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
21207 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
21209 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21210 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21211 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21213 /* SSE MMX or 3Dnow!A */
21214 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21215 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21216 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21218 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21219 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21220 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21221 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21223 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
21224 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
21226 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
21229 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21231 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
21232 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
21233 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
21234 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
21235 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21237 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21238 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21239 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
21240 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21241 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21243 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
21245 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21246 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21247 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21248 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21250 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21251 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
21252 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21254 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21255 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21256 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21257 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21258 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21259 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21260 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21261 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21263 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21264 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21265 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21266 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21267 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
21268 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21269 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21270 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21271 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21272 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21273 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21274 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21275 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21276 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21277 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21278 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21279 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21280 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21281 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21282 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21284 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21285 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21286 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21287 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21289 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21290 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21291 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21292 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21294 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21295 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21296 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21298 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
21300 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21301 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21302 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21303 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21304 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21305 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21306 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21307 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21309 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21310 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21311 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21312 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21313 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21314 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21315 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21316 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21318 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21319 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
21321 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21322 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21323 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21324 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21326 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21327 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21329 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21330 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21331 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21332 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21333 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21334 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21336 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21337 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21338 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21339 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21341 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21342 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21343 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21344 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21345 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21346 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21347 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21348 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21350 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21351 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21352 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21354 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21355 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
21357 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
21358 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21360 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
21362 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
21363 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
21364 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
21365 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
21367 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21368 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21369 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21370 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21371 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21372 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21373 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21375 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21376 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21377 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21378 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21379 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21380 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21381 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21383 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21384 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21385 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21386 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21388 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
21389 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21390 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21392 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
21394 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
21395 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
21397 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21400 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21401 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21404 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
21405 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21407 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21408 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21409 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21410 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21411 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21412 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21415 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
21416 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
21417 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21418 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
21419 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
21420 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21422 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21423 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21424 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21425 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21426 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21427 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21428 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21429 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21430 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21431 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21432 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21433 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21434 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
21435 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
21436 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21437 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21438 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21439 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21440 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21441 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21442 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21443 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21444 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21445 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21448 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
21449 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
21452 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21453 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21454 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
21455 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
21456 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21457 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21458 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21459 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
21460 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
21461 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
21463 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21464 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21465 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21466 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21467 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21468 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21469 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21470 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21471 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21472 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21473 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21474 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21475 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21477 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21478 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21479 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21480 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21481 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21482 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21483 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21484 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21485 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21486 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21487 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21488 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21490 /* SSE4.1 and SSE5 */
21491 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21492 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21493 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21494 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21496 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21497 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21498 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21501 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21502 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
21503 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
21504 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
21505 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
21508 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
21509 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
21510 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
21511 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21514 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
21515 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21517 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21518 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21519 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21520 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21523 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
21526 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21527 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21528 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21529 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21530 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21531 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21532 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21533 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21534 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21535 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21536 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21537 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21538 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21539 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21540 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21541 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21542 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21543 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21544 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21545 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21546 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21547 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21548 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21549 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21550 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21551 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21553 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
21554 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
21555 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
21556 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
21558 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21559 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21560 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
21561 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
21562 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21563 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21564 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21565 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21566 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21567 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21568 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21569 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21570 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21571 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
21572 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
21573 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
21574 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
21575 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
21576 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
21577 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21578 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
21579 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21580 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21581 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21582 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21583 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21584 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
21585 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21586 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21587 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21588 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21589 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
21590 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
21591 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
21593 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21594 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21595 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21597 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21598 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21599 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21600 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21601 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21603 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21605 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21606 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21608 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21609 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21610 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21611 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21613 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
21614 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
21615 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
21616 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
21617 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
21618 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
21620 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21621 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21622 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21623 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21624 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21625 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21626 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21627 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21628 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21629 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21630 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21631 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21632 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21633 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21634 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21636 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
21637 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
21641 enum multi_arg_type {
21651 MULTI_ARG_3_PERMPS,
21652 MULTI_ARG_3_PERMPD,
21659 MULTI_ARG_2_DI_IMM,
21660 MULTI_ARG_2_SI_IMM,
21661 MULTI_ARG_2_HI_IMM,
21662 MULTI_ARG_2_QI_IMM,
21663 MULTI_ARG_2_SF_CMP,
21664 MULTI_ARG_2_DF_CMP,
21665 MULTI_ARG_2_DI_CMP,
21666 MULTI_ARG_2_SI_CMP,
21667 MULTI_ARG_2_HI_CMP,
21668 MULTI_ARG_2_QI_CMP,
21691 static const struct builtin_description bdesc_multi_arg[] =
21693 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, 0, (int)MULTI_ARG_3_SF },
21694 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, 0, (int)MULTI_ARG_3_DF },
21695 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, 0, (int)MULTI_ARG_3_SF },
21696 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, 0, (int)MULTI_ARG_3_DF },
21697 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, 0, (int)MULTI_ARG_3_SF },
21698 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, 0, (int)MULTI_ARG_3_DF },
21699 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, 0, (int)MULTI_ARG_3_SF },
21700 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, 0, (int)MULTI_ARG_3_DF },
21701 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, 0, (int)MULTI_ARG_3_SF },
21702 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, 0, (int)MULTI_ARG_3_DF },
21703 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, 0, (int)MULTI_ARG_3_SF },
21704 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, 0, (int)MULTI_ARG_3_DF },
21705 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, 0, (int)MULTI_ARG_3_SF },
21706 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, 0, (int)MULTI_ARG_3_DF },
21707 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, 0, (int)MULTI_ARG_3_SF },
21708 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, 0, (int)MULTI_ARG_3_DF },
21709 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV, 0, (int)MULTI_ARG_3_DI },
21710 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
21711 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, 0, (int)MULTI_ARG_3_SI },
21712 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, 0, (int)MULTI_ARG_3_HI },
21713 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,0, (int)MULTI_ARG_3_QI },
21714 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, 0, (int)MULTI_ARG_3_DF },
21715 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, 0, (int)MULTI_ARG_3_SF },
21716 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, 0, (int)MULTI_ARG_3_QI },
21717 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, 0, (int)MULTI_ARG_3_PERMPS },
21718 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, 0, (int)MULTI_ARG_3_PERMPD },
21719 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, 0, (int)MULTI_ARG_3_HI },
21720 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, 0, (int)MULTI_ARG_3_HI },
21721 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, 0, (int)MULTI_ARG_3_HI_SI },
21722 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, 0, (int)MULTI_ARG_3_HI_SI },
21723 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, 0, (int)MULTI_ARG_3_SI },
21724 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, 0, (int)MULTI_ARG_3_SI },
21725 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, 0, (int)MULTI_ARG_3_SI_DI },
21726 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, 0, (int)MULTI_ARG_3_SI_DI },
21727 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, 0, (int)MULTI_ARG_3_SI_DI },
21728 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, 0, (int)MULTI_ARG_3_SI_DI },
21729 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, 0, (int)MULTI_ARG_3_HI_SI },
21730 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, 0, (int)MULTI_ARG_3_HI_SI },
21731 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, 0, (int)MULTI_ARG_2_DI },
21732 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, 0, (int)MULTI_ARG_2_SI },
21733 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, 0, (int)MULTI_ARG_2_HI },
21734 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, 0, (int)MULTI_ARG_2_QI },
21735 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, 0, (int)MULTI_ARG_2_DI_IMM },
21736 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, 0, (int)MULTI_ARG_2_SI_IMM },
21737 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, 0, (int)MULTI_ARG_2_HI_IMM },
21738 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, 0, (int)MULTI_ARG_2_QI_IMM },
21739 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, 0, (int)MULTI_ARG_2_DI },
21740 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, 0, (int)MULTI_ARG_2_SI },
21741 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, 0, (int)MULTI_ARG_2_HI },
21742 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, 0, (int)MULTI_ARG_2_QI },
21743 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, 0, (int)MULTI_ARG_2_DI },
21744 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, 0, (int)MULTI_ARG_2_SI },
21745 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, 0, (int)MULTI_ARG_2_HI },
21746 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, 0, (int)MULTI_ARG_2_QI },
21747 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, 0, (int)MULTI_ARG_2_SF },
21748 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, 0, (int)MULTI_ARG_2_DF },
21749 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, 0, (int)MULTI_ARG_1_SF },
21750 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, 0, (int)MULTI_ARG_1_DF },
21751 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, 0, (int)MULTI_ARG_1_PH2PS },
21752 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, 0, (int)MULTI_ARG_1_PS2PH },
21753 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, 0, (int)MULTI_ARG_1_QI_HI },
21754 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, 0, (int)MULTI_ARG_1_QI_SI },
21755 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, 0, (int)MULTI_ARG_1_QI_DI },
21756 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, 0, (int)MULTI_ARG_1_HI_SI },
21757 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, 0, (int)MULTI_ARG_1_HI_DI },
21758 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, 0, (int)MULTI_ARG_1_SI_DI },
21759 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, 0, (int)MULTI_ARG_1_QI_HI },
21760 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, 0, (int)MULTI_ARG_1_QI_SI },
21761 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, 0, (int)MULTI_ARG_1_QI_DI },
21762 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, 0, (int)MULTI_ARG_1_HI_SI },
21763 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, 0, (int)MULTI_ARG_1_HI_DI },
21764 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, 0, (int)MULTI_ARG_1_SI_DI },
21765 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, 0, (int)MULTI_ARG_1_QI_HI },
21766 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, 0, (int)MULTI_ARG_1_HI_SI },
21767 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, 0, (int)MULTI_ARG_1_SI_DI },
21769 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
21770 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
21771 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comneqss", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
21772 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comltss", IX86_BUILTIN_COMLTSS, LT, (int)MULTI_ARG_2_SF_CMP },
21773 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comless", IX86_BUILTIN_COMLESS, LE, (int)MULTI_ARG_2_SF_CMP },
21774 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgtss", IX86_BUILTIN_COMGTSS, GT, (int)MULTI_ARG_2_SF_CMP },
21775 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgess", IX86_BUILTIN_COMGESS, GE, (int)MULTI_ARG_2_SF_CMP },
21776 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comueqss", IX86_BUILTIN_COMUEQSS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
21777 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuness", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21778 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuneqss", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21779 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunltss", IX86_BUILTIN_COMULTSS, UNLT, (int)MULTI_ARG_2_SF_CMP },
21780 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunless", IX86_BUILTIN_COMULESS, UNLE, (int)MULTI_ARG_2_SF_CMP },
21781 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungtss", IX86_BUILTIN_COMUGTSS, UNGT, (int)MULTI_ARG_2_SF_CMP },
21782 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungess", IX86_BUILTIN_COMUGESS, UNGE, (int)MULTI_ARG_2_SF_CMP },
21783 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comordss", IX86_BUILTIN_COMORDSS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
21784 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunordss", IX86_BUILTIN_COMUNORDSS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
21786 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comeqsd", IX86_BUILTIN_COMEQSD, EQ, (int)MULTI_ARG_2_DF_CMP },
21787 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comnesd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
21788 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comneqsd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
21789 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comltsd", IX86_BUILTIN_COMLTSD, LT, (int)MULTI_ARG_2_DF_CMP },
21790 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comlesd", IX86_BUILTIN_COMLESD, LE, (int)MULTI_ARG_2_DF_CMP },
21791 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgtsd", IX86_BUILTIN_COMGTSD, GT, (int)MULTI_ARG_2_DF_CMP },
21792 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgesd", IX86_BUILTIN_COMGESD, GE, (int)MULTI_ARG_2_DF_CMP },
21793 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comueqsd", IX86_BUILTIN_COMUEQSD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
21794 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunesd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21795 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comuneqsd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21796 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunltsd", IX86_BUILTIN_COMULTSD, UNLT, (int)MULTI_ARG_2_DF_CMP },
21797 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunlesd", IX86_BUILTIN_COMULESD, UNLE, (int)MULTI_ARG_2_DF_CMP },
21798 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungtsd", IX86_BUILTIN_COMUGTSD, UNGT, (int)MULTI_ARG_2_DF_CMP },
21799 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungesd", IX86_BUILTIN_COMUGESD, UNGE, (int)MULTI_ARG_2_DF_CMP },
21800 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comordsd", IX86_BUILTIN_COMORDSD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
21801 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunordsd", IX86_BUILTIN_COMUNORDSD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
21803 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comeqps", IX86_BUILTIN_COMEQPS, EQ, (int)MULTI_ARG_2_SF_CMP },
21804 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
21805 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneqps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
21806 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comltps", IX86_BUILTIN_COMLTPS, LT, (int)MULTI_ARG_2_SF_CMP },
21807 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comleps", IX86_BUILTIN_COMLEPS, LE, (int)MULTI_ARG_2_SF_CMP },
21808 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgtps", IX86_BUILTIN_COMGTPS, GT, (int)MULTI_ARG_2_SF_CMP },
21809 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgeps", IX86_BUILTIN_COMGEPS, GE, (int)MULTI_ARG_2_SF_CMP },
21810 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comueqps", IX86_BUILTIN_COMUEQPS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
21811 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21812 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneqps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21813 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunltps", IX86_BUILTIN_COMULTPS, UNLT, (int)MULTI_ARG_2_SF_CMP },
21814 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunleps", IX86_BUILTIN_COMULEPS, UNLE, (int)MULTI_ARG_2_SF_CMP },
21815 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungtps", IX86_BUILTIN_COMUGTPS, UNGT, (int)MULTI_ARG_2_SF_CMP },
21816 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungeps", IX86_BUILTIN_COMUGEPS, UNGE, (int)MULTI_ARG_2_SF_CMP },
21817 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comordps", IX86_BUILTIN_COMORDPS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
21818 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunordps", IX86_BUILTIN_COMUNORDPS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
21820 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comeqpd", IX86_BUILTIN_COMEQPD, EQ, (int)MULTI_ARG_2_DF_CMP },
21821 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comnepd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
21822 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comneqpd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
21823 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comltpd", IX86_BUILTIN_COMLTPD, LT, (int)MULTI_ARG_2_DF_CMP },
21824 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comlepd", IX86_BUILTIN_COMLEPD, LE, (int)MULTI_ARG_2_DF_CMP },
21825 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgtpd", IX86_BUILTIN_COMGTPD, GT, (int)MULTI_ARG_2_DF_CMP },
21826 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgepd", IX86_BUILTIN_COMGEPD, GE, (int)MULTI_ARG_2_DF_CMP },
21827 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comueqpd", IX86_BUILTIN_COMUEQPD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
21828 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunepd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21829 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comuneqpd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21830 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunltpd", IX86_BUILTIN_COMULTPD, UNLT, (int)MULTI_ARG_2_DF_CMP },
21831 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunlepd", IX86_BUILTIN_COMULEPD, UNLE, (int)MULTI_ARG_2_DF_CMP },
21832 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungtpd", IX86_BUILTIN_COMUGTPD, UNGT, (int)MULTI_ARG_2_DF_CMP },
21833 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungepd", IX86_BUILTIN_COMUGEPD, UNGE, (int)MULTI_ARG_2_DF_CMP },
21834 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comordpd", IX86_BUILTIN_COMORDPD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
21835 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunordpd", IX86_BUILTIN_COMUNORDPD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
21837 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomeqb", IX86_BUILTIN_PCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
21838 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
21839 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneqb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
21840 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomltb", IX86_BUILTIN_PCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
21841 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomleb", IX86_BUILTIN_PCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
21842 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgtb", IX86_BUILTIN_PCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
21843 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgeb", IX86_BUILTIN_PCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
21845 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomeqw", IX86_BUILTIN_PCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
21846 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomnew", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
21847 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomneqw", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
21848 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomltw", IX86_BUILTIN_PCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
21849 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomlew", IX86_BUILTIN_PCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
21850 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgtw", IX86_BUILTIN_PCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
21851 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgew", IX86_BUILTIN_PCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
21853 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomeqd", IX86_BUILTIN_PCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
21854 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomned", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
21855 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomneqd", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
21856 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomltd", IX86_BUILTIN_PCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
21857 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomled", IX86_BUILTIN_PCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
21858 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomgtd", IX86_BUILTIN_PCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
21859 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomged", IX86_BUILTIN_PCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
21861 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomeqq", IX86_BUILTIN_PCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
21862 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
21863 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneqq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
21864 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomltq", IX86_BUILTIN_PCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
21865 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomleq", IX86_BUILTIN_PCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
21866 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgtq", IX86_BUILTIN_PCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
21867 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgeq", IX86_BUILTIN_PCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
21869 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomequb", IX86_BUILTIN_PCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
21870 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomneub", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
21871 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomnequb", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
21872 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomltub", IX86_BUILTIN_PCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
21873 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomleub", IX86_BUILTIN_PCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
21874 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgtub", IX86_BUILTIN_PCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
21875 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgeub", IX86_BUILTIN_PCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
21877 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomequw", IX86_BUILTIN_PCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
21878 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomneuw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
21879 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomnequw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
21880 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomltuw", IX86_BUILTIN_PCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
21881 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomleuw", IX86_BUILTIN_PCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
21882 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgtuw", IX86_BUILTIN_PCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
21883 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgeuw", IX86_BUILTIN_PCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
21885 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomequd", IX86_BUILTIN_PCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
21886 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomneud", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
21887 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomnequd", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
21888 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomltud", IX86_BUILTIN_PCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
21889 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomleud", IX86_BUILTIN_PCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
21890 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgtud", IX86_BUILTIN_PCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
21891 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgeud", IX86_BUILTIN_PCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
21893 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomequq", IX86_BUILTIN_PCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
21894 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomneuq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
21895 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomnequq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
21896 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomltuq", IX86_BUILTIN_PCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
21897 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomleuq", IX86_BUILTIN_PCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
21898 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
21899 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
21901 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
21902 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
21903 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
21904 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
21905 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
21906 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
21907 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
21908 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
21910 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
21911 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
21912 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
21913 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
21914 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
21915 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
21916 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
21917 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
21919 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
21920 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
21921 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
21922 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
21923 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
21924 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
21925 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
21926 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
21929 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
21930 in the current target ISA to allow the user to compile particular modules
21931 with different target specific options that differ from the command line
21934 ix86_init_mmx_sse_builtins (void)
21936 const struct builtin_description * d;
21939 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
21940 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
21941 tree V1DI_type_node
21942 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
21943 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
21944 tree V2DI_type_node
21945 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
21946 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
21947 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
21948 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
21949 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
21950 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
21951 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
21953 tree pchar_type_node = build_pointer_type (char_type_node);
21954 tree pcchar_type_node
21955 = build_pointer_type (build_type_variant (char_type_node, 1, 0));
21956 tree pfloat_type_node = build_pointer_type (float_type_node);
21957 tree pcfloat_type_node
21958 = build_pointer_type (build_type_variant (float_type_node, 1, 0));
21959 tree pv2sf_type_node = build_pointer_type (V2SF_type_node);
21960 tree pcv2sf_type_node
21961 = build_pointer_type (build_type_variant (V2SF_type_node, 1, 0));
21962 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
21963 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
21966 tree int_ftype_v4sf_v4sf
21967 = build_function_type_list (integer_type_node,
21968 V4SF_type_node, V4SF_type_node, NULL_TREE);
21969 tree v4si_ftype_v4sf_v4sf
21970 = build_function_type_list (V4SI_type_node,
21971 V4SF_type_node, V4SF_type_node, NULL_TREE);
21972 /* MMX/SSE/integer conversions. */
21973 tree int_ftype_v4sf
21974 = build_function_type_list (integer_type_node,
21975 V4SF_type_node, NULL_TREE);
21976 tree int64_ftype_v4sf
21977 = build_function_type_list (long_long_integer_type_node,
21978 V4SF_type_node, NULL_TREE);
21979 tree int_ftype_v8qi
21980 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
21981 tree v4sf_ftype_v4sf_int
21982 = build_function_type_list (V4SF_type_node,
21983 V4SF_type_node, integer_type_node, NULL_TREE);
21984 tree v4sf_ftype_v4sf_int64
21985 = build_function_type_list (V4SF_type_node,
21986 V4SF_type_node, long_long_integer_type_node,
21988 tree v4sf_ftype_v4sf_v2si
21989 = build_function_type_list (V4SF_type_node,
21990 V4SF_type_node, V2SI_type_node, NULL_TREE);
21992 /* Miscellaneous. */
21993 tree v8qi_ftype_v4hi_v4hi
21994 = build_function_type_list (V8QI_type_node,
21995 V4HI_type_node, V4HI_type_node, NULL_TREE);
21996 tree v4hi_ftype_v2si_v2si
21997 = build_function_type_list (V4HI_type_node,
21998 V2SI_type_node, V2SI_type_node, NULL_TREE);
21999 tree v4sf_ftype_v4sf_v4sf_int
22000 = build_function_type_list (V4SF_type_node,
22001 V4SF_type_node, V4SF_type_node,
22002 integer_type_node, NULL_TREE);
22003 tree v2si_ftype_v4hi_v4hi
22004 = build_function_type_list (V2SI_type_node,
22005 V4HI_type_node, V4HI_type_node, NULL_TREE);
22006 tree v4hi_ftype_v4hi_int
22007 = build_function_type_list (V4HI_type_node,
22008 V4HI_type_node, integer_type_node, NULL_TREE);
22009 tree v2si_ftype_v2si_int
22010 = build_function_type_list (V2SI_type_node,
22011 V2SI_type_node, integer_type_node, NULL_TREE);
22012 tree v1di_ftype_v1di_int
22013 = build_function_type_list (V1DI_type_node,
22014 V1DI_type_node, integer_type_node, NULL_TREE);
22016 tree void_ftype_void
22017 = build_function_type (void_type_node, void_list_node);
22018 tree void_ftype_unsigned
22019 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
22020 tree void_ftype_unsigned_unsigned
22021 = build_function_type_list (void_type_node, unsigned_type_node,
22022 unsigned_type_node, NULL_TREE);
22023 tree void_ftype_pcvoid_unsigned_unsigned
22024 = build_function_type_list (void_type_node, const_ptr_type_node,
22025 unsigned_type_node, unsigned_type_node,
22027 tree unsigned_ftype_void
22028 = build_function_type (unsigned_type_node, void_list_node);
22029 tree v2si_ftype_v4sf
22030 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
22031 /* Loads/stores. */
22032 tree void_ftype_v8qi_v8qi_pchar
22033 = build_function_type_list (void_type_node,
22034 V8QI_type_node, V8QI_type_node,
22035 pchar_type_node, NULL_TREE);
22036 tree v4sf_ftype_pcfloat
22037 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
22038 tree v4sf_ftype_v4sf_pcv2sf
22039 = build_function_type_list (V4SF_type_node,
22040 V4SF_type_node, pcv2sf_type_node, NULL_TREE);
22041 tree void_ftype_pv2sf_v4sf
22042 = build_function_type_list (void_type_node,
22043 pv2sf_type_node, V4SF_type_node, NULL_TREE);
22044 tree void_ftype_pfloat_v4sf
22045 = build_function_type_list (void_type_node,
22046 pfloat_type_node, V4SF_type_node, NULL_TREE);
22047 tree void_ftype_pdi_di
22048 = build_function_type_list (void_type_node,
22049 pdi_type_node, long_long_unsigned_type_node,
22051 tree void_ftype_pv2di_v2di
22052 = build_function_type_list (void_type_node,
22053 pv2di_type_node, V2DI_type_node, NULL_TREE);
22054 /* Normal vector unops. */
22055 tree v4sf_ftype_v4sf
22056 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
22057 tree v16qi_ftype_v16qi
22058 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
22059 tree v8hi_ftype_v8hi
22060 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
22061 tree v4si_ftype_v4si
22062 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
22063 tree v8qi_ftype_v8qi
22064 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
22065 tree v4hi_ftype_v4hi
22066 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
22068 /* Normal vector binops. */
22069 tree v4sf_ftype_v4sf_v4sf
22070 = build_function_type_list (V4SF_type_node,
22071 V4SF_type_node, V4SF_type_node, NULL_TREE);
22072 tree v8qi_ftype_v8qi_v8qi
22073 = build_function_type_list (V8QI_type_node,
22074 V8QI_type_node, V8QI_type_node, NULL_TREE);
22075 tree v4hi_ftype_v4hi_v4hi
22076 = build_function_type_list (V4HI_type_node,
22077 V4HI_type_node, V4HI_type_node, NULL_TREE);
22078 tree v2si_ftype_v2si_v2si
22079 = build_function_type_list (V2SI_type_node,
22080 V2SI_type_node, V2SI_type_node, NULL_TREE);
22081 tree v1di_ftype_v1di_v1di
22082 = build_function_type_list (V1DI_type_node,
22083 V1DI_type_node, V1DI_type_node, NULL_TREE);
22084 tree v1di_ftype_v1di_v1di_int
22085 = build_function_type_list (V1DI_type_node,
22086 V1DI_type_node, V1DI_type_node,
22087 integer_type_node, NULL_TREE);
22088 tree v2si_ftype_v2sf
22089 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
22090 tree v2sf_ftype_v2si
22091 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
22092 tree v2si_ftype_v2si
22093 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
22094 tree v2sf_ftype_v2sf
22095 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
22096 tree v2sf_ftype_v2sf_v2sf
22097 = build_function_type_list (V2SF_type_node,
22098 V2SF_type_node, V2SF_type_node, NULL_TREE);
22099 tree v2si_ftype_v2sf_v2sf
22100 = build_function_type_list (V2SI_type_node,
22101 V2SF_type_node, V2SF_type_node, NULL_TREE);
22102 tree pint_type_node = build_pointer_type (integer_type_node);
22103 tree pdouble_type_node = build_pointer_type (double_type_node);
22104 tree pcdouble_type_node = build_pointer_type (
22105 build_type_variant (double_type_node, 1, 0));
22106 tree int_ftype_v2df_v2df
22107 = build_function_type_list (integer_type_node,
22108 V2DF_type_node, V2DF_type_node, NULL_TREE);
22110 tree void_ftype_pcvoid
22111 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
22112 tree v4sf_ftype_v4si
22113 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
22114 tree v4si_ftype_v4sf
22115 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
22116 tree v2df_ftype_v4si
22117 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
22118 tree v4si_ftype_v2df
22119 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
22120 tree v4si_ftype_v2df_v2df
22121 = build_function_type_list (V4SI_type_node,
22122 V2DF_type_node, V2DF_type_node, NULL_TREE);
22123 tree v2si_ftype_v2df
22124 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
22125 tree v4sf_ftype_v2df
22126 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
22127 tree v2df_ftype_v2si
22128 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
22129 tree v2df_ftype_v4sf
22130 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
22131 tree int_ftype_v2df
22132 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
22133 tree int64_ftype_v2df
22134 = build_function_type_list (long_long_integer_type_node,
22135 V2DF_type_node, NULL_TREE);
22136 tree v2df_ftype_v2df_int
22137 = build_function_type_list (V2DF_type_node,
22138 V2DF_type_node, integer_type_node, NULL_TREE);
22139 tree v2df_ftype_v2df_int64
22140 = build_function_type_list (V2DF_type_node,
22141 V2DF_type_node, long_long_integer_type_node,
22143 tree v4sf_ftype_v4sf_v2df
22144 = build_function_type_list (V4SF_type_node,
22145 V4SF_type_node, V2DF_type_node, NULL_TREE);
22146 tree v2df_ftype_v2df_v4sf
22147 = build_function_type_list (V2DF_type_node,
22148 V2DF_type_node, V4SF_type_node, NULL_TREE);
22149 tree v2df_ftype_v2df_v2df_int
22150 = build_function_type_list (V2DF_type_node,
22151 V2DF_type_node, V2DF_type_node,
22154 tree v2df_ftype_v2df_pcdouble
22155 = build_function_type_list (V2DF_type_node,
22156 V2DF_type_node, pcdouble_type_node, NULL_TREE);
22157 tree void_ftype_pdouble_v2df
22158 = build_function_type_list (void_type_node,
22159 pdouble_type_node, V2DF_type_node, NULL_TREE);
22160 tree void_ftype_pint_int
22161 = build_function_type_list (void_type_node,
22162 pint_type_node, integer_type_node, NULL_TREE);
22163 tree void_ftype_v16qi_v16qi_pchar
22164 = build_function_type_list (void_type_node,
22165 V16QI_type_node, V16QI_type_node,
22166 pchar_type_node, NULL_TREE);
22167 tree v2df_ftype_pcdouble
22168 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
22169 tree v2df_ftype_v2df_v2df
22170 = build_function_type_list (V2DF_type_node,
22171 V2DF_type_node, V2DF_type_node, NULL_TREE);
22172 tree v16qi_ftype_v16qi_v16qi
22173 = build_function_type_list (V16QI_type_node,
22174 V16QI_type_node, V16QI_type_node, NULL_TREE);
22175 tree v8hi_ftype_v8hi_v8hi
22176 = build_function_type_list (V8HI_type_node,
22177 V8HI_type_node, V8HI_type_node, NULL_TREE);
22178 tree v4si_ftype_v4si_v4si
22179 = build_function_type_list (V4SI_type_node,
22180 V4SI_type_node, V4SI_type_node, NULL_TREE);
22181 tree v2di_ftype_v2di_v2di
22182 = build_function_type_list (V2DI_type_node,
22183 V2DI_type_node, V2DI_type_node, NULL_TREE);
22184 tree v2di_ftype_v2df_v2df
22185 = build_function_type_list (V2DI_type_node,
22186 V2DF_type_node, V2DF_type_node, NULL_TREE);
22187 tree v2df_ftype_v2df
22188 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
22189 tree v2di_ftype_v2di_int
22190 = build_function_type_list (V2DI_type_node,
22191 V2DI_type_node, integer_type_node, NULL_TREE);
22192 tree v2di_ftype_v2di_v2di_int
22193 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22194 V2DI_type_node, integer_type_node, NULL_TREE);
22195 tree v4si_ftype_v4si_int
22196 = build_function_type_list (V4SI_type_node,
22197 V4SI_type_node, integer_type_node, NULL_TREE);
22198 tree v8hi_ftype_v8hi_int
22199 = build_function_type_list (V8HI_type_node,
22200 V8HI_type_node, integer_type_node, NULL_TREE);
22201 tree v4si_ftype_v8hi_v8hi
22202 = build_function_type_list (V4SI_type_node,
22203 V8HI_type_node, V8HI_type_node, NULL_TREE);
22204 tree v1di_ftype_v8qi_v8qi
22205 = build_function_type_list (V1DI_type_node,
22206 V8QI_type_node, V8QI_type_node, NULL_TREE);
22207 tree v1di_ftype_v2si_v2si
22208 = build_function_type_list (V1DI_type_node,
22209 V2SI_type_node, V2SI_type_node, NULL_TREE);
22210 tree v2di_ftype_v16qi_v16qi
22211 = build_function_type_list (V2DI_type_node,
22212 V16QI_type_node, V16QI_type_node, NULL_TREE);
22213 tree v2di_ftype_v4si_v4si
22214 = build_function_type_list (V2DI_type_node,
22215 V4SI_type_node, V4SI_type_node, NULL_TREE);
22216 tree int_ftype_v16qi
22217 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
22218 tree v16qi_ftype_pcchar
22219 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
22220 tree void_ftype_pchar_v16qi
22221 = build_function_type_list (void_type_node,
22222 pchar_type_node, V16QI_type_node, NULL_TREE);
22224 tree v2di_ftype_v2di_unsigned_unsigned
22225 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22226 unsigned_type_node, unsigned_type_node,
22228 tree v2di_ftype_v2di_v2di_unsigned_unsigned
22229 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
22230 unsigned_type_node, unsigned_type_node,
22232 tree v2di_ftype_v2di_v16qi
22233 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
22235 tree v2df_ftype_v2df_v2df_v2df
22236 = build_function_type_list (V2DF_type_node,
22237 V2DF_type_node, V2DF_type_node,
22238 V2DF_type_node, NULL_TREE);
22239 tree v4sf_ftype_v4sf_v4sf_v4sf
22240 = build_function_type_list (V4SF_type_node,
22241 V4SF_type_node, V4SF_type_node,
22242 V4SF_type_node, NULL_TREE);
22243 tree v8hi_ftype_v16qi
22244 = build_function_type_list (V8HI_type_node, V16QI_type_node,
22246 tree v4si_ftype_v16qi
22247 = build_function_type_list (V4SI_type_node, V16QI_type_node,
22249 tree v2di_ftype_v16qi
22250 = build_function_type_list (V2DI_type_node, V16QI_type_node,
22252 tree v4si_ftype_v8hi
22253 = build_function_type_list (V4SI_type_node, V8HI_type_node,
22255 tree v2di_ftype_v8hi
22256 = build_function_type_list (V2DI_type_node, V8HI_type_node,
22258 tree v2di_ftype_v4si
22259 = build_function_type_list (V2DI_type_node, V4SI_type_node,
22261 tree v2di_ftype_pv2di
22262 = build_function_type_list (V2DI_type_node, pv2di_type_node,
22264 tree v16qi_ftype_v16qi_v16qi_int
22265 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22266 V16QI_type_node, integer_type_node,
22268 tree v16qi_ftype_v16qi_v16qi_v16qi
22269 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22270 V16QI_type_node, V16QI_type_node,
22272 tree v8hi_ftype_v8hi_v8hi_int
22273 = build_function_type_list (V8HI_type_node, V8HI_type_node,
22274 V8HI_type_node, integer_type_node,
22276 tree v4si_ftype_v4si_v4si_int
22277 = build_function_type_list (V4SI_type_node, V4SI_type_node,
22278 V4SI_type_node, integer_type_node,
22280 tree int_ftype_v2di_v2di
22281 = build_function_type_list (integer_type_node,
22282 V2DI_type_node, V2DI_type_node,
22284 tree int_ftype_v16qi_int_v16qi_int_int
22285 = build_function_type_list (integer_type_node,
22292 tree v16qi_ftype_v16qi_int_v16qi_int_int
22293 = build_function_type_list (V16QI_type_node,
22300 tree int_ftype_v16qi_v16qi_int
22301 = build_function_type_list (integer_type_node,
22307 /* SSE5 instructions */
22308 tree v2di_ftype_v2di_v2di_v2di
22309 = build_function_type_list (V2DI_type_node,
22315 tree v4si_ftype_v4si_v4si_v4si
22316 = build_function_type_list (V4SI_type_node,
22322 tree v4si_ftype_v4si_v4si_v2di
22323 = build_function_type_list (V4SI_type_node,
22329 tree v8hi_ftype_v8hi_v8hi_v8hi
22330 = build_function_type_list (V8HI_type_node,
22336 tree v8hi_ftype_v8hi_v8hi_v4si
22337 = build_function_type_list (V8HI_type_node,
22343 tree v2df_ftype_v2df_v2df_v16qi
22344 = build_function_type_list (V2DF_type_node,
22350 tree v4sf_ftype_v4sf_v4sf_v16qi
22351 = build_function_type_list (V4SF_type_node,
22357 tree v2di_ftype_v2di_si
22358 = build_function_type_list (V2DI_type_node,
22363 tree v4si_ftype_v4si_si
22364 = build_function_type_list (V4SI_type_node,
22369 tree v8hi_ftype_v8hi_si
22370 = build_function_type_list (V8HI_type_node,
22375 tree v16qi_ftype_v16qi_si
22376 = build_function_type_list (V16QI_type_node,
22380 tree v4sf_ftype_v4hi
22381 = build_function_type_list (V4SF_type_node,
22385 tree v4hi_ftype_v4sf
22386 = build_function_type_list (V4HI_type_node,
22390 tree v2di_ftype_v2di
22391 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
22393 tree v16qi_ftype_v8hi_v8hi
22394 = build_function_type_list (V16QI_type_node,
22395 V8HI_type_node, V8HI_type_node,
22397 tree v8hi_ftype_v4si_v4si
22398 = build_function_type_list (V8HI_type_node,
22399 V4SI_type_node, V4SI_type_node,
22401 tree v8hi_ftype_v16qi_v16qi
22402 = build_function_type_list (V8HI_type_node,
22403 V16QI_type_node, V16QI_type_node,
22405 tree v4hi_ftype_v8qi_v8qi
22406 = build_function_type_list (V4HI_type_node,
22407 V8QI_type_node, V8QI_type_node,
22409 tree unsigned_ftype_unsigned_uchar
22410 = build_function_type_list (unsigned_type_node,
22411 unsigned_type_node,
22412 unsigned_char_type_node,
22414 tree unsigned_ftype_unsigned_ushort
22415 = build_function_type_list (unsigned_type_node,
22416 unsigned_type_node,
22417 short_unsigned_type_node,
22419 tree unsigned_ftype_unsigned_unsigned
22420 = build_function_type_list (unsigned_type_node,
22421 unsigned_type_node,
22422 unsigned_type_node,
22424 tree uint64_ftype_uint64_uint64
22425 = build_function_type_list (long_long_unsigned_type_node,
22426 long_long_unsigned_type_node,
22427 long_long_unsigned_type_node,
22429 tree float_ftype_float
22430 = build_function_type_list (float_type_node,
22435 tree V32QI_type_node = build_vector_type_for_mode (char_type_node,
22437 tree V8SI_type_node = build_vector_type_for_mode (intSI_type_node,
22439 tree V8SF_type_node = build_vector_type_for_mode (float_type_node,
22441 tree V4DI_type_node = build_vector_type_for_mode (long_long_integer_type_node,
22443 tree V4DF_type_node = build_vector_type_for_mode (double_type_node,
22445 tree v8sf_ftype_v8sf
22446 = build_function_type_list (V8SF_type_node,
22449 tree v8si_ftype_v8sf
22450 = build_function_type_list (V8SI_type_node,
22453 tree v8sf_ftype_v8si
22454 = build_function_type_list (V8SF_type_node,
22457 tree v4si_ftype_v4df
22458 = build_function_type_list (V4SI_type_node,
22461 tree v4df_ftype_v4df
22462 = build_function_type_list (V4DF_type_node,
22465 tree v4df_ftype_v4si
22466 = build_function_type_list (V4DF_type_node,
22469 tree v4df_ftype_v4sf
22470 = build_function_type_list (V4DF_type_node,
22473 tree v4sf_ftype_v4df
22474 = build_function_type_list (V4SF_type_node,
22477 tree v8sf_ftype_v8sf_v8sf
22478 = build_function_type_list (V8SF_type_node,
22479 V8SF_type_node, V8SF_type_node,
22481 tree v4df_ftype_v4df_v4df
22482 = build_function_type_list (V4DF_type_node,
22483 V4DF_type_node, V4DF_type_node,
22485 tree v8sf_ftype_v8sf_int
22486 = build_function_type_list (V8SF_type_node,
22487 V8SF_type_node, integer_type_node,
22489 tree v4si_ftype_v8si_int
22490 = build_function_type_list (V4SI_type_node,
22491 V8SI_type_node, integer_type_node,
22493 tree v4df_ftype_v4df_int
22494 = build_function_type_list (V4DF_type_node,
22495 V4DF_type_node, integer_type_node,
22497 tree v4sf_ftype_v8sf_int
22498 = build_function_type_list (V4SF_type_node,
22499 V8SF_type_node, integer_type_node,
22501 tree v2df_ftype_v4df_int
22502 = build_function_type_list (V2DF_type_node,
22503 V4DF_type_node, integer_type_node,
22505 tree v8sf_ftype_v8sf_v8sf_int
22506 = build_function_type_list (V8SF_type_node,
22507 V8SF_type_node, V8SF_type_node,
22510 tree v8sf_ftype_v8sf_v8sf_v8sf
22511 = build_function_type_list (V8SF_type_node,
22512 V8SF_type_node, V8SF_type_node,
22515 tree v4df_ftype_v4df_v4df_v4df
22516 = build_function_type_list (V4DF_type_node,
22517 V4DF_type_node, V4DF_type_node,
22520 tree v8si_ftype_v8si_v8si_int
22521 = build_function_type_list (V8SI_type_node,
22522 V8SI_type_node, V8SI_type_node,
22525 tree v4df_ftype_v4df_v4df_int
22526 = build_function_type_list (V4DF_type_node,
22527 V4DF_type_node, V4DF_type_node,
22530 tree v8sf_ftype_pcfloat
22531 = build_function_type_list (V8SF_type_node,
22534 tree v4df_ftype_pcdouble
22535 = build_function_type_list (V4DF_type_node,
22536 pcdouble_type_node,
22538 tree pcv4sf_type_node
22539 = build_pointer_type (build_type_variant (V4SF_type_node, 1, 0));
22540 tree pcv2df_type_node
22541 = build_pointer_type (build_type_variant (V2DF_type_node, 1, 0));
22542 tree v8sf_ftype_pcv4sf
22543 = build_function_type_list (V8SF_type_node,
22546 tree v4df_ftype_pcv2df
22547 = build_function_type_list (V4DF_type_node,
22550 tree v32qi_ftype_pcchar
22551 = build_function_type_list (V32QI_type_node,
22554 tree void_ftype_pchar_v32qi
22555 = build_function_type_list (void_type_node,
22556 pchar_type_node, V32QI_type_node,
22558 tree v8si_ftype_v8si_v4si_int
22559 = build_function_type_list (V8SI_type_node,
22560 V8SI_type_node, V4SI_type_node,
22563 tree pv4di_type_node = build_pointer_type (V4DI_type_node);
22564 tree void_ftype_pv4di_v4di
22565 = build_function_type_list (void_type_node,
22566 pv4di_type_node, V4DI_type_node,
22568 tree v8sf_ftype_v8sf_v4sf_int
22569 = build_function_type_list (V8SF_type_node,
22570 V8SF_type_node, V4SF_type_node,
22573 tree v4df_ftype_v4df_v2df_int
22574 = build_function_type_list (V4DF_type_node,
22575 V4DF_type_node, V2DF_type_node,
22578 tree void_ftype_pfloat_v8sf
22579 = build_function_type_list (void_type_node,
22580 pfloat_type_node, V8SF_type_node,
22582 tree void_ftype_pdouble_v4df
22583 = build_function_type_list (void_type_node,
22584 pdouble_type_node, V4DF_type_node,
22586 tree pv8sf_type_node = build_pointer_type (V8SF_type_node);
22587 tree pv4sf_type_node = build_pointer_type (V4SF_type_node);
22588 tree pv4df_type_node = build_pointer_type (V4DF_type_node);
22589 tree pv2df_type_node = build_pointer_type (V2DF_type_node);
22590 tree pcv8sf_type_node
22591 = build_pointer_type (build_type_variant (V8SF_type_node, 1, 0));
22592 tree pcv4df_type_node
22593 = build_pointer_type (build_type_variant (V4DF_type_node, 1, 0));
22594 tree v8sf_ftype_pcv8sf_v8sf
22595 = build_function_type_list (V8SF_type_node,
22596 pcv8sf_type_node, V8SF_type_node,
22598 tree v4df_ftype_pcv4df_v4df
22599 = build_function_type_list (V4DF_type_node,
22600 pcv4df_type_node, V4DF_type_node,
22602 tree v4sf_ftype_pcv4sf_v4sf
22603 = build_function_type_list (V4SF_type_node,
22604 pcv4sf_type_node, V4SF_type_node,
22606 tree v2df_ftype_pcv2df_v2df
22607 = build_function_type_list (V2DF_type_node,
22608 pcv2df_type_node, V2DF_type_node,
22610 tree void_ftype_pv8sf_v8sf_v8sf
22611 = build_function_type_list (void_type_node,
22612 pv8sf_type_node, V8SF_type_node,
22615 tree void_ftype_pv4df_v4df_v4df
22616 = build_function_type_list (void_type_node,
22617 pv4df_type_node, V4DF_type_node,
22620 tree void_ftype_pv4sf_v4sf_v4sf
22621 = build_function_type_list (void_type_node,
22622 pv4sf_type_node, V4SF_type_node,
22625 tree void_ftype_pv2df_v2df_v2df
22626 = build_function_type_list (void_type_node,
22627 pv2df_type_node, V2DF_type_node,
22630 tree v4df_ftype_v2df
22631 = build_function_type_list (V4DF_type_node,
22634 tree v8sf_ftype_v4sf
22635 = build_function_type_list (V8SF_type_node,
22638 tree v8si_ftype_v4si
22639 = build_function_type_list (V8SI_type_node,
22642 tree v2df_ftype_v4df
22643 = build_function_type_list (V2DF_type_node,
22646 tree v4sf_ftype_v8sf
22647 = build_function_type_list (V4SF_type_node,
22650 tree v4si_ftype_v8si
22651 = build_function_type_list (V4SI_type_node,
22654 tree int_ftype_v4df
22655 = build_function_type_list (integer_type_node,
22658 tree int_ftype_v8sf
22659 = build_function_type_list (integer_type_node,
22662 tree int_ftype_v8sf_v8sf
22663 = build_function_type_list (integer_type_node,
22664 V8SF_type_node, V8SF_type_node,
22666 tree int_ftype_v4di_v4di
22667 = build_function_type_list (integer_type_node,
22668 V4DI_type_node, V4DI_type_node,
22670 tree int_ftype_v4df_v4df
22671 = build_function_type_list (integer_type_node,
22672 V4DF_type_node, V4DF_type_node,
22674 tree v8sf_ftype_v8sf_v8si
22675 = build_function_type_list (V8SF_type_node,
22676 V8SF_type_node, V8SI_type_node,
22678 tree v4df_ftype_v4df_v4di
22679 = build_function_type_list (V4DF_type_node,
22680 V4DF_type_node, V4DI_type_node,
22682 tree v4sf_ftype_v4sf_v4si
22683 = build_function_type_list (V4SF_type_node,
22684 V4SF_type_node, V4SI_type_node, NULL_TREE);
22685 tree v2df_ftype_v2df_v2di
22686 = build_function_type_list (V2DF_type_node,
22687 V2DF_type_node, V2DI_type_node, NULL_TREE);
22691 /* Add all special builtins with variable number of operands. */
22692 for (i = 0, d = bdesc_special_args;
22693 i < ARRAY_SIZE (bdesc_special_args);
22701 switch ((enum ix86_special_builtin_type) d->flag)
22703 case VOID_FTYPE_VOID:
22704 type = void_ftype_void;
22706 case V32QI_FTYPE_PCCHAR:
22707 type = v32qi_ftype_pcchar;
22709 case V16QI_FTYPE_PCCHAR:
22710 type = v16qi_ftype_pcchar;
22712 case V8SF_FTYPE_PCV4SF:
22713 type = v8sf_ftype_pcv4sf;
22715 case V8SF_FTYPE_PCFLOAT:
22716 type = v8sf_ftype_pcfloat;
22718 case V4DF_FTYPE_PCV2DF:
22719 type = v4df_ftype_pcv2df;
22721 case V4DF_FTYPE_PCDOUBLE:
22722 type = v4df_ftype_pcdouble;
22724 case V4SF_FTYPE_PCFLOAT:
22725 type = v4sf_ftype_pcfloat;
22727 case V2DI_FTYPE_PV2DI:
22728 type = v2di_ftype_pv2di;
22730 case V2DF_FTYPE_PCDOUBLE:
22731 type = v2df_ftype_pcdouble;
22733 case V8SF_FTYPE_PCV8SF_V8SF:
22734 type = v8sf_ftype_pcv8sf_v8sf;
22736 case V4DF_FTYPE_PCV4DF_V4DF:
22737 type = v4df_ftype_pcv4df_v4df;
22739 case V4SF_FTYPE_V4SF_PCV2SF:
22740 type = v4sf_ftype_v4sf_pcv2sf;
22742 case V4SF_FTYPE_PCV4SF_V4SF:
22743 type = v4sf_ftype_pcv4sf_v4sf;
22745 case V2DF_FTYPE_V2DF_PCDOUBLE:
22746 type = v2df_ftype_v2df_pcdouble;
22748 case V2DF_FTYPE_PCV2DF_V2DF:
22749 type = v2df_ftype_pcv2df_v2df;
22751 case VOID_FTYPE_PV2SF_V4SF:
22752 type = void_ftype_pv2sf_v4sf;
22754 case VOID_FTYPE_PV4DI_V4DI:
22755 type = void_ftype_pv4di_v4di;
22757 case VOID_FTYPE_PV2DI_V2DI:
22758 type = void_ftype_pv2di_v2di;
22760 case VOID_FTYPE_PCHAR_V32QI:
22761 type = void_ftype_pchar_v32qi;
22763 case VOID_FTYPE_PCHAR_V16QI:
22764 type = void_ftype_pchar_v16qi;
22766 case VOID_FTYPE_PFLOAT_V8SF:
22767 type = void_ftype_pfloat_v8sf;
22769 case VOID_FTYPE_PFLOAT_V4SF:
22770 type = void_ftype_pfloat_v4sf;
22772 case VOID_FTYPE_PDOUBLE_V4DF:
22773 type = void_ftype_pdouble_v4df;
22775 case VOID_FTYPE_PDOUBLE_V2DF:
22776 type = void_ftype_pdouble_v2df;
22778 case VOID_FTYPE_PDI_DI:
22779 type = void_ftype_pdi_di;
22781 case VOID_FTYPE_PINT_INT:
22782 type = void_ftype_pint_int;
22784 case VOID_FTYPE_PV8SF_V8SF_V8SF:
22785 type = void_ftype_pv8sf_v8sf_v8sf;
22787 case VOID_FTYPE_PV4DF_V4DF_V4DF:
22788 type = void_ftype_pv4df_v4df_v4df;
22790 case VOID_FTYPE_PV4SF_V4SF_V4SF:
22791 type = void_ftype_pv4sf_v4sf_v4sf;
22793 case VOID_FTYPE_PV2DF_V2DF_V2DF:
22794 type = void_ftype_pv2df_v2df_v2df;
22797 gcc_unreachable ();
22800 def_builtin (d->mask, d->name, type, d->code);
22803 /* Add all builtins with variable number of operands. */
22804 for (i = 0, d = bdesc_args;
22805 i < ARRAY_SIZE (bdesc_args);
22813 switch ((enum ix86_builtin_type) d->flag)
22815 case FLOAT_FTYPE_FLOAT:
22816 type = float_ftype_float;
22818 case INT_FTYPE_V8SF_V8SF_PTEST:
22819 type = int_ftype_v8sf_v8sf;
22821 case INT_FTYPE_V4DI_V4DI_PTEST:
22822 type = int_ftype_v4di_v4di;
22824 case INT_FTYPE_V4DF_V4DF_PTEST:
22825 type = int_ftype_v4df_v4df;
22827 case INT_FTYPE_V4SF_V4SF_PTEST:
22828 type = int_ftype_v4sf_v4sf;
22830 case INT_FTYPE_V2DI_V2DI_PTEST:
22831 type = int_ftype_v2di_v2di;
22833 case INT_FTYPE_V2DF_V2DF_PTEST:
22834 type = int_ftype_v2df_v2df;
22836 case INT64_FTYPE_V4SF:
22837 type = int64_ftype_v4sf;
22839 case INT64_FTYPE_V2DF:
22840 type = int64_ftype_v2df;
22842 case INT_FTYPE_V16QI:
22843 type = int_ftype_v16qi;
22845 case INT_FTYPE_V8QI:
22846 type = int_ftype_v8qi;
22848 case INT_FTYPE_V8SF:
22849 type = int_ftype_v8sf;
22851 case INT_FTYPE_V4DF:
22852 type = int_ftype_v4df;
22854 case INT_FTYPE_V4SF:
22855 type = int_ftype_v4sf;
22857 case INT_FTYPE_V2DF:
22858 type = int_ftype_v2df;
22860 case V16QI_FTYPE_V16QI:
22861 type = v16qi_ftype_v16qi;
22863 case V8SI_FTYPE_V8SF:
22864 type = v8si_ftype_v8sf;
22866 case V8SI_FTYPE_V4SI:
22867 type = v8si_ftype_v4si;
22869 case V8HI_FTYPE_V8HI:
22870 type = v8hi_ftype_v8hi;
22872 case V8HI_FTYPE_V16QI:
22873 type = v8hi_ftype_v16qi;
22875 case V8QI_FTYPE_V8QI:
22876 type = v8qi_ftype_v8qi;
22878 case V8SF_FTYPE_V8SF:
22879 type = v8sf_ftype_v8sf;
22881 case V8SF_FTYPE_V8SI:
22882 type = v8sf_ftype_v8si;
22884 case V8SF_FTYPE_V4SF:
22885 type = v8sf_ftype_v4sf;
22887 case V4SI_FTYPE_V4DF:
22888 type = v4si_ftype_v4df;
22890 case V4SI_FTYPE_V4SI:
22891 type = v4si_ftype_v4si;
22893 case V4SI_FTYPE_V16QI:
22894 type = v4si_ftype_v16qi;
22896 case V4SI_FTYPE_V8SI:
22897 type = v4si_ftype_v8si;
22899 case V4SI_FTYPE_V8HI:
22900 type = v4si_ftype_v8hi;
22902 case V4SI_FTYPE_V4SF:
22903 type = v4si_ftype_v4sf;
22905 case V4SI_FTYPE_V2DF:
22906 type = v4si_ftype_v2df;
22908 case V4HI_FTYPE_V4HI:
22909 type = v4hi_ftype_v4hi;
22911 case V4DF_FTYPE_V4DF:
22912 type = v4df_ftype_v4df;
22914 case V4DF_FTYPE_V4SI:
22915 type = v4df_ftype_v4si;
22917 case V4DF_FTYPE_V4SF:
22918 type = v4df_ftype_v4sf;
22920 case V4DF_FTYPE_V2DF:
22921 type = v4df_ftype_v2df;
22923 case V4SF_FTYPE_V4SF:
22924 case V4SF_FTYPE_V4SF_VEC_MERGE:
22925 type = v4sf_ftype_v4sf;
22927 case V4SF_FTYPE_V8SF:
22928 type = v4sf_ftype_v8sf;
22930 case V4SF_FTYPE_V4SI:
22931 type = v4sf_ftype_v4si;
22933 case V4SF_FTYPE_V4DF:
22934 type = v4sf_ftype_v4df;
22936 case V4SF_FTYPE_V2DF:
22937 type = v4sf_ftype_v2df;
22939 case V2DI_FTYPE_V2DI:
22940 type = v2di_ftype_v2di;
22942 case V2DI_FTYPE_V16QI:
22943 type = v2di_ftype_v16qi;
22945 case V2DI_FTYPE_V8HI:
22946 type = v2di_ftype_v8hi;
22948 case V2DI_FTYPE_V4SI:
22949 type = v2di_ftype_v4si;
22951 case V2SI_FTYPE_V2SI:
22952 type = v2si_ftype_v2si;
22954 case V2SI_FTYPE_V4SF:
22955 type = v2si_ftype_v4sf;
22957 case V2SI_FTYPE_V2DF:
22958 type = v2si_ftype_v2df;
22960 case V2SI_FTYPE_V2SF:
22961 type = v2si_ftype_v2sf;
22963 case V2DF_FTYPE_V4DF:
22964 type = v2df_ftype_v4df;
22966 case V2DF_FTYPE_V4SF:
22967 type = v2df_ftype_v4sf;
22969 case V2DF_FTYPE_V2DF:
22970 case V2DF_FTYPE_V2DF_VEC_MERGE:
22971 type = v2df_ftype_v2df;
22973 case V2DF_FTYPE_V2SI:
22974 type = v2df_ftype_v2si;
22976 case V2DF_FTYPE_V4SI:
22977 type = v2df_ftype_v4si;
22979 case V2SF_FTYPE_V2SF:
22980 type = v2sf_ftype_v2sf;
22982 case V2SF_FTYPE_V2SI:
22983 type = v2sf_ftype_v2si;
22985 case V16QI_FTYPE_V16QI_V16QI:
22986 type = v16qi_ftype_v16qi_v16qi;
22988 case V16QI_FTYPE_V8HI_V8HI:
22989 type = v16qi_ftype_v8hi_v8hi;
22991 case V8QI_FTYPE_V8QI_V8QI:
22992 type = v8qi_ftype_v8qi_v8qi;
22994 case V8QI_FTYPE_V4HI_V4HI:
22995 type = v8qi_ftype_v4hi_v4hi;
22997 case V8HI_FTYPE_V8HI_V8HI:
22998 case V8HI_FTYPE_V8HI_V8HI_COUNT:
22999 type = v8hi_ftype_v8hi_v8hi;
23001 case V8HI_FTYPE_V16QI_V16QI:
23002 type = v8hi_ftype_v16qi_v16qi;
23004 case V8HI_FTYPE_V4SI_V4SI:
23005 type = v8hi_ftype_v4si_v4si;
23007 case V8HI_FTYPE_V8HI_SI_COUNT:
23008 type = v8hi_ftype_v8hi_int;
23010 case V8SF_FTYPE_V8SF_V8SF:
23011 type = v8sf_ftype_v8sf_v8sf;
23013 case V8SF_FTYPE_V8SF_V8SI:
23014 type = v8sf_ftype_v8sf_v8si;
23016 case V4SI_FTYPE_V4SI_V4SI:
23017 case V4SI_FTYPE_V4SI_V4SI_COUNT:
23018 type = v4si_ftype_v4si_v4si;
23020 case V4SI_FTYPE_V8HI_V8HI:
23021 type = v4si_ftype_v8hi_v8hi;
23023 case V4SI_FTYPE_V4SF_V4SF:
23024 type = v4si_ftype_v4sf_v4sf;
23026 case V4SI_FTYPE_V2DF_V2DF:
23027 type = v4si_ftype_v2df_v2df;
23029 case V4SI_FTYPE_V4SI_SI_COUNT:
23030 type = v4si_ftype_v4si_int;
23032 case V4HI_FTYPE_V4HI_V4HI:
23033 case V4HI_FTYPE_V4HI_V4HI_COUNT:
23034 type = v4hi_ftype_v4hi_v4hi;
23036 case V4HI_FTYPE_V8QI_V8QI:
23037 type = v4hi_ftype_v8qi_v8qi;
23039 case V4HI_FTYPE_V2SI_V2SI:
23040 type = v4hi_ftype_v2si_v2si;
23042 case V4HI_FTYPE_V4HI_SI_COUNT:
23043 type = v4hi_ftype_v4hi_int;
23045 case V4DF_FTYPE_V4DF_V4DF:
23046 type = v4df_ftype_v4df_v4df;
23048 case V4DF_FTYPE_V4DF_V4DI:
23049 type = v4df_ftype_v4df_v4di;
23051 case V4SF_FTYPE_V4SF_V4SF:
23052 case V4SF_FTYPE_V4SF_V4SF_SWAP:
23053 type = v4sf_ftype_v4sf_v4sf;
23055 case V4SF_FTYPE_V4SF_V4SI:
23056 type = v4sf_ftype_v4sf_v4si;
23058 case V4SF_FTYPE_V4SF_V2SI:
23059 type = v4sf_ftype_v4sf_v2si;
23061 case V4SF_FTYPE_V4SF_V2DF:
23062 type = v4sf_ftype_v4sf_v2df;
23064 case V4SF_FTYPE_V4SF_DI:
23065 type = v4sf_ftype_v4sf_int64;
23067 case V4SF_FTYPE_V4SF_SI:
23068 type = v4sf_ftype_v4sf_int;
23070 case V2DI_FTYPE_V2DI_V2DI:
23071 case V2DI_FTYPE_V2DI_V2DI_COUNT:
23072 type = v2di_ftype_v2di_v2di;
23074 case V2DI_FTYPE_V16QI_V16QI:
23075 type = v2di_ftype_v16qi_v16qi;
23077 case V2DI_FTYPE_V4SI_V4SI:
23078 type = v2di_ftype_v4si_v4si;
23080 case V2DI_FTYPE_V2DI_V16QI:
23081 type = v2di_ftype_v2di_v16qi;
23083 case V2DI_FTYPE_V2DF_V2DF:
23084 type = v2di_ftype_v2df_v2df;
23086 case V2DI_FTYPE_V2DI_SI_COUNT:
23087 type = v2di_ftype_v2di_int;
23089 case V2SI_FTYPE_V2SI_V2SI:
23090 case V2SI_FTYPE_V2SI_V2SI_COUNT:
23091 type = v2si_ftype_v2si_v2si;
23093 case V2SI_FTYPE_V4HI_V4HI:
23094 type = v2si_ftype_v4hi_v4hi;
23096 case V2SI_FTYPE_V2SF_V2SF:
23097 type = v2si_ftype_v2sf_v2sf;
23099 case V2SI_FTYPE_V2SI_SI_COUNT:
23100 type = v2si_ftype_v2si_int;
23102 case V2DF_FTYPE_V2DF_V2DF:
23103 case V2DF_FTYPE_V2DF_V2DF_SWAP:
23104 type = v2df_ftype_v2df_v2df;
23106 case V2DF_FTYPE_V2DF_V4SF:
23107 type = v2df_ftype_v2df_v4sf;
23109 case V2DF_FTYPE_V2DF_V2DI:
23110 type = v2df_ftype_v2df_v2di;
23112 case V2DF_FTYPE_V2DF_DI:
23113 type = v2df_ftype_v2df_int64;
23115 case V2DF_FTYPE_V2DF_SI:
23116 type = v2df_ftype_v2df_int;
23118 case V2SF_FTYPE_V2SF_V2SF:
23119 type = v2sf_ftype_v2sf_v2sf;
23121 case V1DI_FTYPE_V1DI_V1DI:
23122 case V1DI_FTYPE_V1DI_V1DI_COUNT:
23123 type = v1di_ftype_v1di_v1di;
23125 case V1DI_FTYPE_V8QI_V8QI:
23126 type = v1di_ftype_v8qi_v8qi;
23128 case V1DI_FTYPE_V2SI_V2SI:
23129 type = v1di_ftype_v2si_v2si;
23131 case V1DI_FTYPE_V1DI_SI_COUNT:
23132 type = v1di_ftype_v1di_int;
23134 case UINT64_FTYPE_UINT64_UINT64:
23135 type = uint64_ftype_uint64_uint64;
23137 case UINT_FTYPE_UINT_UINT:
23138 type = unsigned_ftype_unsigned_unsigned;
23140 case UINT_FTYPE_UINT_USHORT:
23141 type = unsigned_ftype_unsigned_ushort;
23143 case UINT_FTYPE_UINT_UCHAR:
23144 type = unsigned_ftype_unsigned_uchar;
23146 case V8HI_FTYPE_V8HI_INT:
23147 type = v8hi_ftype_v8hi_int;
23149 case V8SF_FTYPE_V8SF_INT:
23150 type = v8sf_ftype_v8sf_int;
23152 case V4SI_FTYPE_V4SI_INT:
23153 type = v4si_ftype_v4si_int;
23155 case V4SI_FTYPE_V8SI_INT:
23156 type = v4si_ftype_v8si_int;
23158 case V4HI_FTYPE_V4HI_INT:
23159 type = v4hi_ftype_v4hi_int;
23161 case V4DF_FTYPE_V4DF_INT:
23162 type = v4df_ftype_v4df_int;
23164 case V4SF_FTYPE_V4SF_INT:
23165 type = v4sf_ftype_v4sf_int;
23167 case V4SF_FTYPE_V8SF_INT:
23168 type = v4sf_ftype_v8sf_int;
23170 case V2DI_FTYPE_V2DI_INT:
23171 case V2DI2TI_FTYPE_V2DI_INT:
23172 type = v2di_ftype_v2di_int;
23174 case V2DF_FTYPE_V2DF_INT:
23175 type = v2df_ftype_v2df_int;
23177 case V2DF_FTYPE_V4DF_INT:
23178 type = v2df_ftype_v4df_int;
23180 case V16QI_FTYPE_V16QI_V16QI_V16QI:
23181 type = v16qi_ftype_v16qi_v16qi_v16qi;
23183 case V8SF_FTYPE_V8SF_V8SF_V8SF:
23184 type = v8sf_ftype_v8sf_v8sf_v8sf;
23186 case V4DF_FTYPE_V4DF_V4DF_V4DF:
23187 type = v4df_ftype_v4df_v4df_v4df;
23189 case V4SF_FTYPE_V4SF_V4SF_V4SF:
23190 type = v4sf_ftype_v4sf_v4sf_v4sf;
23192 case V2DF_FTYPE_V2DF_V2DF_V2DF:
23193 type = v2df_ftype_v2df_v2df_v2df;
23195 case V16QI_FTYPE_V16QI_V16QI_INT:
23196 type = v16qi_ftype_v16qi_v16qi_int;
23198 case V8SI_FTYPE_V8SI_V8SI_INT:
23199 type = v8si_ftype_v8si_v8si_int;
23201 case V8SI_FTYPE_V8SI_V4SI_INT:
23202 type = v8si_ftype_v8si_v4si_int;
23204 case V8HI_FTYPE_V8HI_V8HI_INT:
23205 type = v8hi_ftype_v8hi_v8hi_int;
23207 case V8SF_FTYPE_V8SF_V8SF_INT:
23208 type = v8sf_ftype_v8sf_v8sf_int;
23210 case V8SF_FTYPE_V8SF_V4SF_INT:
23211 type = v8sf_ftype_v8sf_v4sf_int;
23213 case V4SI_FTYPE_V4SI_V4SI_INT:
23214 type = v4si_ftype_v4si_v4si_int;
23216 case V4DF_FTYPE_V4DF_V4DF_INT:
23217 type = v4df_ftype_v4df_v4df_int;
23219 case V4DF_FTYPE_V4DF_V2DF_INT:
23220 type = v4df_ftype_v4df_v2df_int;
23222 case V4SF_FTYPE_V4SF_V4SF_INT:
23223 type = v4sf_ftype_v4sf_v4sf_int;
23225 case V2DI_FTYPE_V2DI_V2DI_INT:
23226 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
23227 type = v2di_ftype_v2di_v2di_int;
23229 case V2DF_FTYPE_V2DF_V2DF_INT:
23230 type = v2df_ftype_v2df_v2df_int;
23232 case V2DI_FTYPE_V2DI_UINT_UINT:
23233 type = v2di_ftype_v2di_unsigned_unsigned;
23235 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
23236 type = v2di_ftype_v2di_v2di_unsigned_unsigned;
23238 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
23239 type = v1di_ftype_v1di_v1di_int;
23242 gcc_unreachable ();
23245 def_builtin_const (d->mask, d->name, type, d->code);
23248 /* pcmpestr[im] insns. */
23249 for (i = 0, d = bdesc_pcmpestr;
23250 i < ARRAY_SIZE (bdesc_pcmpestr);
23253 if (d->code == IX86_BUILTIN_PCMPESTRM128)
23254 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
23256 ftype = int_ftype_v16qi_int_v16qi_int_int;
23257 def_builtin_const (d->mask, d->name, ftype, d->code);
23260 /* pcmpistr[im] insns. */
23261 for (i = 0, d = bdesc_pcmpistr;
23262 i < ARRAY_SIZE (bdesc_pcmpistr);
23265 if (d->code == IX86_BUILTIN_PCMPISTRM128)
23266 ftype = v16qi_ftype_v16qi_v16qi_int;
23268 ftype = int_ftype_v16qi_v16qi_int;
23269 def_builtin_const (d->mask, d->name, ftype, d->code);
23272 /* comi/ucomi insns. */
23273 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
23274 if (d->mask == OPTION_MASK_ISA_SSE2)
23275 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
23277 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
23280 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
23281 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
23283 /* SSE or 3DNow!A */
23284 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
23287 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
23289 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
23290 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
23293 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
23294 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
23297 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
23298 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
23299 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
23300 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
23301 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
23302 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
23305 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
23308 def_builtin (OPTION_MASK_ISA_AVX, "__builtin_ia32_vzeroupper", void_ftype_void,
23309 TARGET_64BIT ? IX86_BUILTIN_VZEROUPPER_REX64 : IX86_BUILTIN_VZEROUPPER);
23311 /* Access to the vec_init patterns. */
23312 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
23313 integer_type_node, NULL_TREE);
23314 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
23316 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
23317 short_integer_type_node,
23318 short_integer_type_node,
23319 short_integer_type_node, NULL_TREE);
23320 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
23322 ftype = build_function_type_list (V8QI_type_node, char_type_node,
23323 char_type_node, char_type_node,
23324 char_type_node, char_type_node,
23325 char_type_node, char_type_node,
23326 char_type_node, NULL_TREE);
23327 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
23329 /* Access to the vec_extract patterns. */
23330 ftype = build_function_type_list (double_type_node, V2DF_type_node,
23331 integer_type_node, NULL_TREE);
23332 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
23334 ftype = build_function_type_list (long_long_integer_type_node,
23335 V2DI_type_node, integer_type_node,
23337 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
23339 ftype = build_function_type_list (float_type_node, V4SF_type_node,
23340 integer_type_node, NULL_TREE);
23341 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
23343 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
23344 integer_type_node, NULL_TREE);
23345 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
23347 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
23348 integer_type_node, NULL_TREE);
23349 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
23351 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
23352 integer_type_node, NULL_TREE);
23353 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
23355 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
23356 integer_type_node, NULL_TREE);
23357 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
23359 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
23360 integer_type_node, NULL_TREE);
23361 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
23363 /* Access to the vec_set patterns. */
23364 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
23366 integer_type_node, NULL_TREE);
23367 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
23369 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
23371 integer_type_node, NULL_TREE);
23372 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
23374 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
23376 integer_type_node, NULL_TREE);
23377 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
23379 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
23381 integer_type_node, NULL_TREE);
23382 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
23384 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
23386 integer_type_node, NULL_TREE);
23387 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
23389 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
23391 integer_type_node, NULL_TREE);
23392 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
23394 /* Add SSE5 multi-arg argument instructions */
23395 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
23397 tree mtype = NULL_TREE;
23402 switch ((enum multi_arg_type)d->flag)
23404 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
23405 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
23406 case MULTI_ARG_3_DI: mtype = v2di_ftype_v2di_v2di_v2di; break;
23407 case MULTI_ARG_3_SI: mtype = v4si_ftype_v4si_v4si_v4si; break;
23408 case MULTI_ARG_3_SI_DI: mtype = v4si_ftype_v4si_v4si_v2di; break;
23409 case MULTI_ARG_3_HI: mtype = v8hi_ftype_v8hi_v8hi_v8hi; break;
23410 case MULTI_ARG_3_HI_SI: mtype = v8hi_ftype_v8hi_v8hi_v4si; break;
23411 case MULTI_ARG_3_QI: mtype = v16qi_ftype_v16qi_v16qi_v16qi; break;
23412 case MULTI_ARG_3_PERMPS: mtype = v4sf_ftype_v4sf_v4sf_v16qi; break;
23413 case MULTI_ARG_3_PERMPD: mtype = v2df_ftype_v2df_v2df_v16qi; break;
23414 case MULTI_ARG_2_SF: mtype = v4sf_ftype_v4sf_v4sf; break;
23415 case MULTI_ARG_2_DF: mtype = v2df_ftype_v2df_v2df; break;
23416 case MULTI_ARG_2_DI: mtype = v2di_ftype_v2di_v2di; break;
23417 case MULTI_ARG_2_SI: mtype = v4si_ftype_v4si_v4si; break;
23418 case MULTI_ARG_2_HI: mtype = v8hi_ftype_v8hi_v8hi; break;
23419 case MULTI_ARG_2_QI: mtype = v16qi_ftype_v16qi_v16qi; break;
23420 case MULTI_ARG_2_DI_IMM: mtype = v2di_ftype_v2di_si; break;
23421 case MULTI_ARG_2_SI_IMM: mtype = v4si_ftype_v4si_si; break;
23422 case MULTI_ARG_2_HI_IMM: mtype = v8hi_ftype_v8hi_si; break;
23423 case MULTI_ARG_2_QI_IMM: mtype = v16qi_ftype_v16qi_si; break;
23424 case MULTI_ARG_2_SF_CMP: mtype = v4sf_ftype_v4sf_v4sf; break;
23425 case MULTI_ARG_2_DF_CMP: mtype = v2df_ftype_v2df_v2df; break;
23426 case MULTI_ARG_2_DI_CMP: mtype = v2di_ftype_v2di_v2di; break;
23427 case MULTI_ARG_2_SI_CMP: mtype = v4si_ftype_v4si_v4si; break;
23428 case MULTI_ARG_2_HI_CMP: mtype = v8hi_ftype_v8hi_v8hi; break;
23429 case MULTI_ARG_2_QI_CMP: mtype = v16qi_ftype_v16qi_v16qi; break;
23430 case MULTI_ARG_2_SF_TF: mtype = v4sf_ftype_v4sf_v4sf; break;
23431 case MULTI_ARG_2_DF_TF: mtype = v2df_ftype_v2df_v2df; break;
23432 case MULTI_ARG_2_DI_TF: mtype = v2di_ftype_v2di_v2di; break;
23433 case MULTI_ARG_2_SI_TF: mtype = v4si_ftype_v4si_v4si; break;
23434 case MULTI_ARG_2_HI_TF: mtype = v8hi_ftype_v8hi_v8hi; break;
23435 case MULTI_ARG_2_QI_TF: mtype = v16qi_ftype_v16qi_v16qi; break;
23436 case MULTI_ARG_1_SF: mtype = v4sf_ftype_v4sf; break;
23437 case MULTI_ARG_1_DF: mtype = v2df_ftype_v2df; break;
23438 case MULTI_ARG_1_DI: mtype = v2di_ftype_v2di; break;
23439 case MULTI_ARG_1_SI: mtype = v4si_ftype_v4si; break;
23440 case MULTI_ARG_1_HI: mtype = v8hi_ftype_v8hi; break;
23441 case MULTI_ARG_1_QI: mtype = v16qi_ftype_v16qi; break;
23442 case MULTI_ARG_1_SI_DI: mtype = v2di_ftype_v4si; break;
23443 case MULTI_ARG_1_HI_DI: mtype = v2di_ftype_v8hi; break;
23444 case MULTI_ARG_1_HI_SI: mtype = v4si_ftype_v8hi; break;
23445 case MULTI_ARG_1_QI_DI: mtype = v2di_ftype_v16qi; break;
23446 case MULTI_ARG_1_QI_SI: mtype = v4si_ftype_v16qi; break;
23447 case MULTI_ARG_1_QI_HI: mtype = v8hi_ftype_v16qi; break;
23448 case MULTI_ARG_1_PH2PS: mtype = v4sf_ftype_v4hi; break;
23449 case MULTI_ARG_1_PS2PH: mtype = v4hi_ftype_v4sf; break;
23450 case MULTI_ARG_UNKNOWN:
23452 gcc_unreachable ();
23456 def_builtin_const (d->mask, d->name, mtype, d->code);
23460 /* Internal method for ix86_init_builtins. */
23463 ix86_init_builtins_va_builtins_abi (void)
23465 tree ms_va_ref, sysv_va_ref;
23466 tree fnvoid_va_end_ms, fnvoid_va_end_sysv;
23467 tree fnvoid_va_start_ms, fnvoid_va_start_sysv;
23468 tree fnvoid_va_copy_ms, fnvoid_va_copy_sysv;
23469 tree fnattr_ms = NULL_TREE, fnattr_sysv = NULL_TREE;
23473 fnattr_ms = build_tree_list (get_identifier ("ms_abi"), NULL_TREE);
23474 fnattr_sysv = build_tree_list (get_identifier ("sysv_abi"), NULL_TREE);
23475 ms_va_ref = build_reference_type (ms_va_list_type_node);
23477 build_pointer_type (TREE_TYPE (sysv_va_list_type_node));
23480 build_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23481 fnvoid_va_start_ms =
23482 build_varargs_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23483 fnvoid_va_end_sysv =
23484 build_function_type_list (void_type_node, sysv_va_ref, NULL_TREE);
23485 fnvoid_va_start_sysv =
23486 build_varargs_function_type_list (void_type_node, sysv_va_ref,
23488 fnvoid_va_copy_ms =
23489 build_function_type_list (void_type_node, ms_va_ref, ms_va_list_type_node,
23491 fnvoid_va_copy_sysv =
23492 build_function_type_list (void_type_node, sysv_va_ref,
23493 sysv_va_ref, NULL_TREE);
23495 add_builtin_function ("__builtin_ms_va_start", fnvoid_va_start_ms,
23496 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_ms);
23497 add_builtin_function ("__builtin_ms_va_end", fnvoid_va_end_ms,
23498 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_ms);
23499 add_builtin_function ("__builtin_ms_va_copy", fnvoid_va_copy_ms,
23500 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_ms);
23501 add_builtin_function ("__builtin_sysv_va_start", fnvoid_va_start_sysv,
23502 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23503 add_builtin_function ("__builtin_sysv_va_end", fnvoid_va_end_sysv,
23504 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23505 add_builtin_function ("__builtin_sysv_va_copy", fnvoid_va_copy_sysv,
23506 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23510 ix86_init_builtins (void)
23512 tree float128_type_node = make_node (REAL_TYPE);
23515 /* The __float80 type. */
23516 if (TYPE_MODE (long_double_type_node) == XFmode)
23517 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
23521 /* The __float80 type. */
23522 tree float80_type_node = make_node (REAL_TYPE);
23524 TYPE_PRECISION (float80_type_node) = 80;
23525 layout_type (float80_type_node);
23526 (*lang_hooks.types.register_builtin_type) (float80_type_node,
23530 /* The __float128 type. */
23531 TYPE_PRECISION (float128_type_node) = 128;
23532 layout_type (float128_type_node);
23533 (*lang_hooks.types.register_builtin_type) (float128_type_node,
23536 /* TFmode support builtins. */
23537 ftype = build_function_type (float128_type_node, void_list_node);
23538 decl = add_builtin_function ("__builtin_infq", ftype,
23539 IX86_BUILTIN_INFQ, BUILT_IN_MD,
23541 ix86_builtins[(int) IX86_BUILTIN_INFQ] = decl;
23543 /* We will expand them to normal call if SSE2 isn't available since
23544 they are used by libgcc. */
23545 ftype = build_function_type_list (float128_type_node,
23546 float128_type_node,
23548 decl = add_builtin_function ("__builtin_fabsq", ftype,
23549 IX86_BUILTIN_FABSQ, BUILT_IN_MD,
23550 "__fabstf2", NULL_TREE);
23551 ix86_builtins[(int) IX86_BUILTIN_FABSQ] = decl;
23552 TREE_READONLY (decl) = 1;
23554 ftype = build_function_type_list (float128_type_node,
23555 float128_type_node,
23556 float128_type_node,
23558 decl = add_builtin_function ("__builtin_copysignq", ftype,
23559 IX86_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
23560 "__copysigntf3", NULL_TREE);
23561 ix86_builtins[(int) IX86_BUILTIN_COPYSIGNQ] = decl;
23562 TREE_READONLY (decl) = 1;
23564 ix86_init_mmx_sse_builtins ();
23566 ix86_init_builtins_va_builtins_abi ();
23569 /* Errors in the source file can cause expand_expr to return const0_rtx
23570 where we expect a vector. To avoid crashing, use one of the vector
23571 clear instructions. */
23573 safe_vector_operand (rtx x, enum machine_mode mode)
23575 if (x == const0_rtx)
23576 x = CONST0_RTX (mode);
23580 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
23583 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
23586 tree arg0 = CALL_EXPR_ARG (exp, 0);
23587 tree arg1 = CALL_EXPR_ARG (exp, 1);
23588 rtx op0 = expand_normal (arg0);
23589 rtx op1 = expand_normal (arg1);
23590 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23591 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23592 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
23594 if (VECTOR_MODE_P (mode0))
23595 op0 = safe_vector_operand (op0, mode0);
23596 if (VECTOR_MODE_P (mode1))
23597 op1 = safe_vector_operand (op1, mode1);
23599 if (optimize || !target
23600 || GET_MODE (target) != tmode
23601 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23602 target = gen_reg_rtx (tmode);
23604 if (GET_MODE (op1) == SImode && mode1 == TImode)
23606 rtx x = gen_reg_rtx (V4SImode);
23607 emit_insn (gen_sse2_loadd (x, op1));
23608 op1 = gen_lowpart (TImode, x);
23611 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
23612 op0 = copy_to_mode_reg (mode0, op0);
23613 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
23614 op1 = copy_to_mode_reg (mode1, op1);
23616 pat = GEN_FCN (icode) (target, op0, op1);
23625 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
23628 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
23629 enum multi_arg_type m_type,
23630 enum insn_code sub_code)
23635 bool comparison_p = false;
23637 bool last_arg_constant = false;
23638 int num_memory = 0;
23641 enum machine_mode mode;
23644 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23648 case MULTI_ARG_3_SF:
23649 case MULTI_ARG_3_DF:
23650 case MULTI_ARG_3_DI:
23651 case MULTI_ARG_3_SI:
23652 case MULTI_ARG_3_SI_DI:
23653 case MULTI_ARG_3_HI:
23654 case MULTI_ARG_3_HI_SI:
23655 case MULTI_ARG_3_QI:
23656 case MULTI_ARG_3_PERMPS:
23657 case MULTI_ARG_3_PERMPD:
23661 case MULTI_ARG_2_SF:
23662 case MULTI_ARG_2_DF:
23663 case MULTI_ARG_2_DI:
23664 case MULTI_ARG_2_SI:
23665 case MULTI_ARG_2_HI:
23666 case MULTI_ARG_2_QI:
23670 case MULTI_ARG_2_DI_IMM:
23671 case MULTI_ARG_2_SI_IMM:
23672 case MULTI_ARG_2_HI_IMM:
23673 case MULTI_ARG_2_QI_IMM:
23675 last_arg_constant = true;
23678 case MULTI_ARG_1_SF:
23679 case MULTI_ARG_1_DF:
23680 case MULTI_ARG_1_DI:
23681 case MULTI_ARG_1_SI:
23682 case MULTI_ARG_1_HI:
23683 case MULTI_ARG_1_QI:
23684 case MULTI_ARG_1_SI_DI:
23685 case MULTI_ARG_1_HI_DI:
23686 case MULTI_ARG_1_HI_SI:
23687 case MULTI_ARG_1_QI_DI:
23688 case MULTI_ARG_1_QI_SI:
23689 case MULTI_ARG_1_QI_HI:
23690 case MULTI_ARG_1_PH2PS:
23691 case MULTI_ARG_1_PS2PH:
23695 case MULTI_ARG_2_SF_CMP:
23696 case MULTI_ARG_2_DF_CMP:
23697 case MULTI_ARG_2_DI_CMP:
23698 case MULTI_ARG_2_SI_CMP:
23699 case MULTI_ARG_2_HI_CMP:
23700 case MULTI_ARG_2_QI_CMP:
23702 comparison_p = true;
23705 case MULTI_ARG_2_SF_TF:
23706 case MULTI_ARG_2_DF_TF:
23707 case MULTI_ARG_2_DI_TF:
23708 case MULTI_ARG_2_SI_TF:
23709 case MULTI_ARG_2_HI_TF:
23710 case MULTI_ARG_2_QI_TF:
23715 case MULTI_ARG_UNKNOWN:
23717 gcc_unreachable ();
23720 if (optimize || !target
23721 || GET_MODE (target) != tmode
23722 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23723 target = gen_reg_rtx (tmode);
23725 gcc_assert (nargs <= 4);
23727 for (i = 0; i < nargs; i++)
23729 tree arg = CALL_EXPR_ARG (exp, i);
23730 rtx op = expand_normal (arg);
23731 int adjust = (comparison_p) ? 1 : 0;
23732 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
23734 if (last_arg_constant && i == nargs-1)
23736 if (GET_CODE (op) != CONST_INT)
23738 error ("last argument must be an immediate");
23739 return gen_reg_rtx (tmode);
23744 if (VECTOR_MODE_P (mode))
23745 op = safe_vector_operand (op, mode);
23747 /* If we aren't optimizing, only allow one memory operand to be
23749 if (memory_operand (op, mode))
23752 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
23755 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
23757 op = force_reg (mode, op);
23761 args[i].mode = mode;
23767 pat = GEN_FCN (icode) (target, args[0].op);
23772 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
23773 GEN_INT ((int)sub_code));
23774 else if (! comparison_p)
23775 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
23778 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
23782 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
23787 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
23791 gcc_unreachable ();
23801 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
23802 insns with vec_merge. */
23805 ix86_expand_unop_vec_merge_builtin (enum insn_code icode, tree exp,
23809 tree arg0 = CALL_EXPR_ARG (exp, 0);
23810 rtx op1, op0 = expand_normal (arg0);
23811 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23812 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23814 if (optimize || !target
23815 || GET_MODE (target) != tmode
23816 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23817 target = gen_reg_rtx (tmode);
23819 if (VECTOR_MODE_P (mode0))
23820 op0 = safe_vector_operand (op0, mode0);
23822 if ((optimize && !register_operand (op0, mode0))
23823 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
23824 op0 = copy_to_mode_reg (mode0, op0);
23827 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
23828 op1 = copy_to_mode_reg (mode0, op1);
23830 pat = GEN_FCN (icode) (target, op0, op1);
23837 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
23840 ix86_expand_sse_compare (const struct builtin_description *d,
23841 tree exp, rtx target, bool swap)
23844 tree arg0 = CALL_EXPR_ARG (exp, 0);
23845 tree arg1 = CALL_EXPR_ARG (exp, 1);
23846 rtx op0 = expand_normal (arg0);
23847 rtx op1 = expand_normal (arg1);
23849 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
23850 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
23851 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
23852 enum rtx_code comparison = d->comparison;
23854 if (VECTOR_MODE_P (mode0))
23855 op0 = safe_vector_operand (op0, mode0);
23856 if (VECTOR_MODE_P (mode1))
23857 op1 = safe_vector_operand (op1, mode1);
23859 /* Swap operands if we have a comparison that isn't available in
23863 rtx tmp = gen_reg_rtx (mode1);
23864 emit_move_insn (tmp, op1);
23869 if (optimize || !target
23870 || GET_MODE (target) != tmode
23871 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
23872 target = gen_reg_rtx (tmode);
23874 if ((optimize && !register_operand (op0, mode0))
23875 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
23876 op0 = copy_to_mode_reg (mode0, op0);
23877 if ((optimize && !register_operand (op1, mode1))
23878 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
23879 op1 = copy_to_mode_reg (mode1, op1);
23881 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
23882 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
23889 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
23892 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
23896 tree arg0 = CALL_EXPR_ARG (exp, 0);
23897 tree arg1 = CALL_EXPR_ARG (exp, 1);
23898 rtx op0 = expand_normal (arg0);
23899 rtx op1 = expand_normal (arg1);
23900 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23901 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23902 enum rtx_code comparison = d->comparison;
23904 if (VECTOR_MODE_P (mode0))
23905 op0 = safe_vector_operand (op0, mode0);
23906 if (VECTOR_MODE_P (mode1))
23907 op1 = safe_vector_operand (op1, mode1);
23909 /* Swap operands if we have a comparison that isn't available in
23911 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
23918 target = gen_reg_rtx (SImode);
23919 emit_move_insn (target, const0_rtx);
23920 target = gen_rtx_SUBREG (QImode, target, 0);
23922 if ((optimize && !register_operand (op0, mode0))
23923 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23924 op0 = copy_to_mode_reg (mode0, op0);
23925 if ((optimize && !register_operand (op1, mode1))
23926 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23927 op1 = copy_to_mode_reg (mode1, op1);
23929 pat = GEN_FCN (d->icode) (op0, op1);
23933 emit_insn (gen_rtx_SET (VOIDmode,
23934 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23935 gen_rtx_fmt_ee (comparison, QImode,
23939 return SUBREG_REG (target);
23942 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
23945 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
23949 tree arg0 = CALL_EXPR_ARG (exp, 0);
23950 tree arg1 = CALL_EXPR_ARG (exp, 1);
23951 rtx op0 = expand_normal (arg0);
23952 rtx op1 = expand_normal (arg1);
23953 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23954 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23955 enum rtx_code comparison = d->comparison;
23957 if (VECTOR_MODE_P (mode0))
23958 op0 = safe_vector_operand (op0, mode0);
23959 if (VECTOR_MODE_P (mode1))
23960 op1 = safe_vector_operand (op1, mode1);
23962 target = gen_reg_rtx (SImode);
23963 emit_move_insn (target, const0_rtx);
23964 target = gen_rtx_SUBREG (QImode, target, 0);
23966 if ((optimize && !register_operand (op0, mode0))
23967 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23968 op0 = copy_to_mode_reg (mode0, op0);
23969 if ((optimize && !register_operand (op1, mode1))
23970 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23971 op1 = copy_to_mode_reg (mode1, op1);
23973 pat = GEN_FCN (d->icode) (op0, op1);
23977 emit_insn (gen_rtx_SET (VOIDmode,
23978 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23979 gen_rtx_fmt_ee (comparison, QImode,
23983 return SUBREG_REG (target);
23986 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
23989 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
23990 tree exp, rtx target)
23993 tree arg0 = CALL_EXPR_ARG (exp, 0);
23994 tree arg1 = CALL_EXPR_ARG (exp, 1);
23995 tree arg2 = CALL_EXPR_ARG (exp, 2);
23996 tree arg3 = CALL_EXPR_ARG (exp, 3);
23997 tree arg4 = CALL_EXPR_ARG (exp, 4);
23998 rtx scratch0, scratch1;
23999 rtx op0 = expand_normal (arg0);
24000 rtx op1 = expand_normal (arg1);
24001 rtx op2 = expand_normal (arg2);
24002 rtx op3 = expand_normal (arg3);
24003 rtx op4 = expand_normal (arg4);
24004 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
24006 tmode0 = insn_data[d->icode].operand[0].mode;
24007 tmode1 = insn_data[d->icode].operand[1].mode;
24008 modev2 = insn_data[d->icode].operand[2].mode;
24009 modei3 = insn_data[d->icode].operand[3].mode;
24010 modev4 = insn_data[d->icode].operand[4].mode;
24011 modei5 = insn_data[d->icode].operand[5].mode;
24012 modeimm = insn_data[d->icode].operand[6].mode;
24014 if (VECTOR_MODE_P (modev2))
24015 op0 = safe_vector_operand (op0, modev2);
24016 if (VECTOR_MODE_P (modev4))
24017 op2 = safe_vector_operand (op2, modev4);
24019 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
24020 op0 = copy_to_mode_reg (modev2, op0);
24021 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
24022 op1 = copy_to_mode_reg (modei3, op1);
24023 if ((optimize && !register_operand (op2, modev4))
24024 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
24025 op2 = copy_to_mode_reg (modev4, op2);
24026 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
24027 op3 = copy_to_mode_reg (modei5, op3);
24029 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
24031 error ("the fifth argument must be a 8-bit immediate");
24035 if (d->code == IX86_BUILTIN_PCMPESTRI128)
24037 if (optimize || !target
24038 || GET_MODE (target) != tmode0
24039 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
24040 target = gen_reg_rtx (tmode0);
24042 scratch1 = gen_reg_rtx (tmode1);
24044 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
24046 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
24048 if (optimize || !target
24049 || GET_MODE (target) != tmode1
24050 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
24051 target = gen_reg_rtx (tmode1);
24053 scratch0 = gen_reg_rtx (tmode0);
24055 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
24059 gcc_assert (d->flag);
24061 scratch0 = gen_reg_rtx (tmode0);
24062 scratch1 = gen_reg_rtx (tmode1);
24064 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
24074 target = gen_reg_rtx (SImode);
24075 emit_move_insn (target, const0_rtx);
24076 target = gen_rtx_SUBREG (QImode, target, 0);
24079 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24080 gen_rtx_fmt_ee (EQ, QImode,
24081 gen_rtx_REG ((enum machine_mode) d->flag,
24084 return SUBREG_REG (target);
24091 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
24094 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
24095 tree exp, rtx target)
24098 tree arg0 = CALL_EXPR_ARG (exp, 0);
24099 tree arg1 = CALL_EXPR_ARG (exp, 1);
24100 tree arg2 = CALL_EXPR_ARG (exp, 2);
24101 rtx scratch0, scratch1;
24102 rtx op0 = expand_normal (arg0);
24103 rtx op1 = expand_normal (arg1);
24104 rtx op2 = expand_normal (arg2);
24105 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
24107 tmode0 = insn_data[d->icode].operand[0].mode;
24108 tmode1 = insn_data[d->icode].operand[1].mode;
24109 modev2 = insn_data[d->icode].operand[2].mode;
24110 modev3 = insn_data[d->icode].operand[3].mode;
24111 modeimm = insn_data[d->icode].operand[4].mode;
24113 if (VECTOR_MODE_P (modev2))
24114 op0 = safe_vector_operand (op0, modev2);
24115 if (VECTOR_MODE_P (modev3))
24116 op1 = safe_vector_operand (op1, modev3);
24118 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
24119 op0 = copy_to_mode_reg (modev2, op0);
24120 if ((optimize && !register_operand (op1, modev3))
24121 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
24122 op1 = copy_to_mode_reg (modev3, op1);
24124 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
24126 error ("the third argument must be a 8-bit immediate");
24130 if (d->code == IX86_BUILTIN_PCMPISTRI128)
24132 if (optimize || !target
24133 || GET_MODE (target) != tmode0
24134 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
24135 target = gen_reg_rtx (tmode0);
24137 scratch1 = gen_reg_rtx (tmode1);
24139 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
24141 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
24143 if (optimize || !target
24144 || GET_MODE (target) != tmode1
24145 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
24146 target = gen_reg_rtx (tmode1);
24148 scratch0 = gen_reg_rtx (tmode0);
24150 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
24154 gcc_assert (d->flag);
24156 scratch0 = gen_reg_rtx (tmode0);
24157 scratch1 = gen_reg_rtx (tmode1);
24159 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
24169 target = gen_reg_rtx (SImode);
24170 emit_move_insn (target, const0_rtx);
24171 target = gen_rtx_SUBREG (QImode, target, 0);
24174 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24175 gen_rtx_fmt_ee (EQ, QImode,
24176 gen_rtx_REG ((enum machine_mode) d->flag,
24179 return SUBREG_REG (target);
24185 /* Subroutine of ix86_expand_builtin to take care of insns with
24186 variable number of operands. */
24189 ix86_expand_args_builtin (const struct builtin_description *d,
24190 tree exp, rtx target)
24192 rtx pat, real_target;
24193 unsigned int i, nargs;
24194 unsigned int nargs_constant = 0;
24195 int num_memory = 0;
24199 enum machine_mode mode;
24201 bool last_arg_count = false;
24202 enum insn_code icode = d->icode;
24203 const struct insn_data *insn_p = &insn_data[icode];
24204 enum machine_mode tmode = insn_p->operand[0].mode;
24205 enum machine_mode rmode = VOIDmode;
24207 enum rtx_code comparison = d->comparison;
24209 switch ((enum ix86_builtin_type) d->flag)
24211 case INT_FTYPE_V8SF_V8SF_PTEST:
24212 case INT_FTYPE_V4DI_V4DI_PTEST:
24213 case INT_FTYPE_V4DF_V4DF_PTEST:
24214 case INT_FTYPE_V4SF_V4SF_PTEST:
24215 case INT_FTYPE_V2DI_V2DI_PTEST:
24216 case INT_FTYPE_V2DF_V2DF_PTEST:
24217 return ix86_expand_sse_ptest (d, exp, target);
24218 case FLOAT128_FTYPE_FLOAT128:
24219 case FLOAT_FTYPE_FLOAT:
24220 case INT64_FTYPE_V4SF:
24221 case INT64_FTYPE_V2DF:
24222 case INT_FTYPE_V16QI:
24223 case INT_FTYPE_V8QI:
24224 case INT_FTYPE_V8SF:
24225 case INT_FTYPE_V4DF:
24226 case INT_FTYPE_V4SF:
24227 case INT_FTYPE_V2DF:
24228 case V16QI_FTYPE_V16QI:
24229 case V8SI_FTYPE_V8SF:
24230 case V8SI_FTYPE_V4SI:
24231 case V8HI_FTYPE_V8HI:
24232 case V8HI_FTYPE_V16QI:
24233 case V8QI_FTYPE_V8QI:
24234 case V8SF_FTYPE_V8SF:
24235 case V8SF_FTYPE_V8SI:
24236 case V8SF_FTYPE_V4SF:
24237 case V4SI_FTYPE_V4SI:
24238 case V4SI_FTYPE_V16QI:
24239 case V4SI_FTYPE_V4SF:
24240 case V4SI_FTYPE_V8SI:
24241 case V4SI_FTYPE_V8HI:
24242 case V4SI_FTYPE_V4DF:
24243 case V4SI_FTYPE_V2DF:
24244 case V4HI_FTYPE_V4HI:
24245 case V4DF_FTYPE_V4DF:
24246 case V4DF_FTYPE_V4SI:
24247 case V4DF_FTYPE_V4SF:
24248 case V4DF_FTYPE_V2DF:
24249 case V4SF_FTYPE_V4SF:
24250 case V4SF_FTYPE_V4SI:
24251 case V4SF_FTYPE_V8SF:
24252 case V4SF_FTYPE_V4DF:
24253 case V4SF_FTYPE_V2DF:
24254 case V2DI_FTYPE_V2DI:
24255 case V2DI_FTYPE_V16QI:
24256 case V2DI_FTYPE_V8HI:
24257 case V2DI_FTYPE_V4SI:
24258 case V2DF_FTYPE_V2DF:
24259 case V2DF_FTYPE_V4SI:
24260 case V2DF_FTYPE_V4DF:
24261 case V2DF_FTYPE_V4SF:
24262 case V2DF_FTYPE_V2SI:
24263 case V2SI_FTYPE_V2SI:
24264 case V2SI_FTYPE_V4SF:
24265 case V2SI_FTYPE_V2SF:
24266 case V2SI_FTYPE_V2DF:
24267 case V2SF_FTYPE_V2SF:
24268 case V2SF_FTYPE_V2SI:
24271 case V4SF_FTYPE_V4SF_VEC_MERGE:
24272 case V2DF_FTYPE_V2DF_VEC_MERGE:
24273 return ix86_expand_unop_vec_merge_builtin (icode, exp, target);
24274 case FLOAT128_FTYPE_FLOAT128_FLOAT128:
24275 case V16QI_FTYPE_V16QI_V16QI:
24276 case V16QI_FTYPE_V8HI_V8HI:
24277 case V8QI_FTYPE_V8QI_V8QI:
24278 case V8QI_FTYPE_V4HI_V4HI:
24279 case V8HI_FTYPE_V8HI_V8HI:
24280 case V8HI_FTYPE_V16QI_V16QI:
24281 case V8HI_FTYPE_V4SI_V4SI:
24282 case V8SF_FTYPE_V8SF_V8SF:
24283 case V8SF_FTYPE_V8SF_V8SI:
24284 case V4SI_FTYPE_V4SI_V4SI:
24285 case V4SI_FTYPE_V8HI_V8HI:
24286 case V4SI_FTYPE_V4SF_V4SF:
24287 case V4SI_FTYPE_V2DF_V2DF:
24288 case V4HI_FTYPE_V4HI_V4HI:
24289 case V4HI_FTYPE_V8QI_V8QI:
24290 case V4HI_FTYPE_V2SI_V2SI:
24291 case V4DF_FTYPE_V4DF_V4DF:
24292 case V4DF_FTYPE_V4DF_V4DI:
24293 case V4SF_FTYPE_V4SF_V4SF:
24294 case V4SF_FTYPE_V4SF_V4SI:
24295 case V4SF_FTYPE_V4SF_V2SI:
24296 case V4SF_FTYPE_V4SF_V2DF:
24297 case V4SF_FTYPE_V4SF_DI:
24298 case V4SF_FTYPE_V4SF_SI:
24299 case V2DI_FTYPE_V2DI_V2DI:
24300 case V2DI_FTYPE_V16QI_V16QI:
24301 case V2DI_FTYPE_V4SI_V4SI:
24302 case V2DI_FTYPE_V2DI_V16QI:
24303 case V2DI_FTYPE_V2DF_V2DF:
24304 case V2SI_FTYPE_V2SI_V2SI:
24305 case V2SI_FTYPE_V4HI_V4HI:
24306 case V2SI_FTYPE_V2SF_V2SF:
24307 case V2DF_FTYPE_V2DF_V2DF:
24308 case V2DF_FTYPE_V2DF_V4SF:
24309 case V2DF_FTYPE_V2DF_V2DI:
24310 case V2DF_FTYPE_V2DF_DI:
24311 case V2DF_FTYPE_V2DF_SI:
24312 case V2SF_FTYPE_V2SF_V2SF:
24313 case V1DI_FTYPE_V1DI_V1DI:
24314 case V1DI_FTYPE_V8QI_V8QI:
24315 case V1DI_FTYPE_V2SI_V2SI:
24316 if (comparison == UNKNOWN)
24317 return ix86_expand_binop_builtin (icode, exp, target);
24320 case V4SF_FTYPE_V4SF_V4SF_SWAP:
24321 case V2DF_FTYPE_V2DF_V2DF_SWAP:
24322 gcc_assert (comparison != UNKNOWN);
24326 case V8HI_FTYPE_V8HI_V8HI_COUNT:
24327 case V8HI_FTYPE_V8HI_SI_COUNT:
24328 case V4SI_FTYPE_V4SI_V4SI_COUNT:
24329 case V4SI_FTYPE_V4SI_SI_COUNT:
24330 case V4HI_FTYPE_V4HI_V4HI_COUNT:
24331 case V4HI_FTYPE_V4HI_SI_COUNT:
24332 case V2DI_FTYPE_V2DI_V2DI_COUNT:
24333 case V2DI_FTYPE_V2DI_SI_COUNT:
24334 case V2SI_FTYPE_V2SI_V2SI_COUNT:
24335 case V2SI_FTYPE_V2SI_SI_COUNT:
24336 case V1DI_FTYPE_V1DI_V1DI_COUNT:
24337 case V1DI_FTYPE_V1DI_SI_COUNT:
24339 last_arg_count = true;
24341 case UINT64_FTYPE_UINT64_UINT64:
24342 case UINT_FTYPE_UINT_UINT:
24343 case UINT_FTYPE_UINT_USHORT:
24344 case UINT_FTYPE_UINT_UCHAR:
24347 case V2DI2TI_FTYPE_V2DI_INT:
24350 nargs_constant = 1;
24352 case V8HI_FTYPE_V8HI_INT:
24353 case V8SF_FTYPE_V8SF_INT:
24354 case V4SI_FTYPE_V4SI_INT:
24355 case V4SI_FTYPE_V8SI_INT:
24356 case V4HI_FTYPE_V4HI_INT:
24357 case V4DF_FTYPE_V4DF_INT:
24358 case V4SF_FTYPE_V4SF_INT:
24359 case V4SF_FTYPE_V8SF_INT:
24360 case V2DI_FTYPE_V2DI_INT:
24361 case V2DF_FTYPE_V2DF_INT:
24362 case V2DF_FTYPE_V4DF_INT:
24364 nargs_constant = 1;
24366 case V16QI_FTYPE_V16QI_V16QI_V16QI:
24367 case V8SF_FTYPE_V8SF_V8SF_V8SF:
24368 case V4DF_FTYPE_V4DF_V4DF_V4DF:
24369 case V4SF_FTYPE_V4SF_V4SF_V4SF:
24370 case V2DF_FTYPE_V2DF_V2DF_V2DF:
24373 case V16QI_FTYPE_V16QI_V16QI_INT:
24374 case V8HI_FTYPE_V8HI_V8HI_INT:
24375 case V8SI_FTYPE_V8SI_V8SI_INT:
24376 case V8SI_FTYPE_V8SI_V4SI_INT:
24377 case V8SF_FTYPE_V8SF_V8SF_INT:
24378 case V8SF_FTYPE_V8SF_V4SF_INT:
24379 case V4SI_FTYPE_V4SI_V4SI_INT:
24380 case V4DF_FTYPE_V4DF_V4DF_INT:
24381 case V4DF_FTYPE_V4DF_V2DF_INT:
24382 case V4SF_FTYPE_V4SF_V4SF_INT:
24383 case V2DI_FTYPE_V2DI_V2DI_INT:
24384 case V2DF_FTYPE_V2DF_V2DF_INT:
24386 nargs_constant = 1;
24388 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
24391 nargs_constant = 1;
24393 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
24396 nargs_constant = 1;
24398 case V2DI_FTYPE_V2DI_UINT_UINT:
24400 nargs_constant = 2;
24402 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
24404 nargs_constant = 2;
24407 gcc_unreachable ();
24410 gcc_assert (nargs <= ARRAY_SIZE (args));
24412 if (comparison != UNKNOWN)
24414 gcc_assert (nargs == 2);
24415 return ix86_expand_sse_compare (d, exp, target, swap);
24418 if (rmode == VOIDmode || rmode == tmode)
24422 || GET_MODE (target) != tmode
24423 || ! (*insn_p->operand[0].predicate) (target, tmode))
24424 target = gen_reg_rtx (tmode);
24425 real_target = target;
24429 target = gen_reg_rtx (rmode);
24430 real_target = simplify_gen_subreg (tmode, target, rmode, 0);
24433 for (i = 0; i < nargs; i++)
24435 tree arg = CALL_EXPR_ARG (exp, i);
24436 rtx op = expand_normal (arg);
24437 enum machine_mode mode = insn_p->operand[i + 1].mode;
24438 bool match = (*insn_p->operand[i + 1].predicate) (op, mode);
24440 if (last_arg_count && (i + 1) == nargs)
24442 /* SIMD shift insns take either an 8-bit immediate or
24443 register as count. But builtin functions take int as
24444 count. If count doesn't match, we put it in register. */
24447 op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
24448 if (!(*insn_p->operand[i + 1].predicate) (op, mode))
24449 op = copy_to_reg (op);
24452 else if ((nargs - i) <= nargs_constant)
24457 case CODE_FOR_sse4_1_roundpd:
24458 case CODE_FOR_sse4_1_roundps:
24459 case CODE_FOR_sse4_1_roundsd:
24460 case CODE_FOR_sse4_1_roundss:
24461 case CODE_FOR_sse4_1_blendps:
24462 case CODE_FOR_avx_blendpd256:
24463 case CODE_FOR_avx_vpermilv4df:
24464 case CODE_FOR_avx_roundpd256:
24465 case CODE_FOR_avx_roundps256:
24466 error ("the last argument must be a 4-bit immediate");
24469 case CODE_FOR_sse4_1_blendpd:
24470 case CODE_FOR_avx_vpermilv2df:
24471 error ("the last argument must be a 2-bit immediate");
24474 case CODE_FOR_avx_vextractf128v4df:
24475 case CODE_FOR_avx_vextractf128v8sf:
24476 case CODE_FOR_avx_vextractf128v8si:
24477 case CODE_FOR_avx_vinsertf128v4df:
24478 case CODE_FOR_avx_vinsertf128v8sf:
24479 case CODE_FOR_avx_vinsertf128v8si:
24480 error ("the last argument must be a 1-bit immediate");
24483 case CODE_FOR_avx_cmpsdv2df3:
24484 case CODE_FOR_avx_cmpssv4sf3:
24485 case CODE_FOR_avx_cmppdv2df3:
24486 case CODE_FOR_avx_cmppsv4sf3:
24487 case CODE_FOR_avx_cmppdv4df3:
24488 case CODE_FOR_avx_cmppsv8sf3:
24489 error ("the last argument must be a 5-bit immediate");
24493 switch (nargs_constant)
24496 if ((nargs - i) == nargs_constant)
24498 error ("the next to last argument must be an 8-bit immediate");
24502 error ("the last argument must be an 8-bit immediate");
24505 gcc_unreachable ();
24512 if (VECTOR_MODE_P (mode))
24513 op = safe_vector_operand (op, mode);
24515 /* If we aren't optimizing, only allow one memory operand to
24517 if (memory_operand (op, mode))
24520 if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
24522 if (optimize || !match || num_memory > 1)
24523 op = copy_to_mode_reg (mode, op);
24527 op = copy_to_reg (op);
24528 op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
24533 args[i].mode = mode;
24539 pat = GEN_FCN (icode) (real_target, args[0].op);
24542 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
24545 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24549 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24550 args[2].op, args[3].op);
24553 gcc_unreachable ();
24563 /* Subroutine of ix86_expand_builtin to take care of special insns
24564 with variable number of operands. */
24567 ix86_expand_special_args_builtin (const struct builtin_description *d,
24568 tree exp, rtx target)
24572 unsigned int i, nargs, arg_adjust, memory;
24576 enum machine_mode mode;
24578 enum insn_code icode = d->icode;
24579 bool last_arg_constant = false;
24580 const struct insn_data *insn_p = &insn_data[icode];
24581 enum machine_mode tmode = insn_p->operand[0].mode;
24582 enum { load, store } klass;
24584 switch ((enum ix86_special_builtin_type) d->flag)
24586 case VOID_FTYPE_VOID:
24587 emit_insn (GEN_FCN (icode) (target));
24589 case V2DI_FTYPE_PV2DI:
24590 case V32QI_FTYPE_PCCHAR:
24591 case V16QI_FTYPE_PCCHAR:
24592 case V8SF_FTYPE_PCV4SF:
24593 case V8SF_FTYPE_PCFLOAT:
24594 case V4SF_FTYPE_PCFLOAT:
24595 case V4DF_FTYPE_PCV2DF:
24596 case V4DF_FTYPE_PCDOUBLE:
24597 case V2DF_FTYPE_PCDOUBLE:
24602 case VOID_FTYPE_PV2SF_V4SF:
24603 case VOID_FTYPE_PV4DI_V4DI:
24604 case VOID_FTYPE_PV2DI_V2DI:
24605 case VOID_FTYPE_PCHAR_V32QI:
24606 case VOID_FTYPE_PCHAR_V16QI:
24607 case VOID_FTYPE_PFLOAT_V8SF:
24608 case VOID_FTYPE_PFLOAT_V4SF:
24609 case VOID_FTYPE_PDOUBLE_V4DF:
24610 case VOID_FTYPE_PDOUBLE_V2DF:
24611 case VOID_FTYPE_PDI_DI:
24612 case VOID_FTYPE_PINT_INT:
24615 /* Reserve memory operand for target. */
24616 memory = ARRAY_SIZE (args);
24618 case V4SF_FTYPE_V4SF_PCV2SF:
24619 case V2DF_FTYPE_V2DF_PCDOUBLE:
24624 case V8SF_FTYPE_PCV8SF_V8SF:
24625 case V4DF_FTYPE_PCV4DF_V4DF:
24626 case V4SF_FTYPE_PCV4SF_V4SF:
24627 case V2DF_FTYPE_PCV2DF_V2DF:
24632 case VOID_FTYPE_PV8SF_V8SF_V8SF:
24633 case VOID_FTYPE_PV4DF_V4DF_V4DF:
24634 case VOID_FTYPE_PV4SF_V4SF_V4SF:
24635 case VOID_FTYPE_PV2DF_V2DF_V2DF:
24638 /* Reserve memory operand for target. */
24639 memory = ARRAY_SIZE (args);
24642 gcc_unreachable ();
24645 gcc_assert (nargs <= ARRAY_SIZE (args));
24647 if (klass == store)
24649 arg = CALL_EXPR_ARG (exp, 0);
24650 op = expand_normal (arg);
24651 gcc_assert (target == 0);
24652 target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
24660 || GET_MODE (target) != tmode
24661 || ! (*insn_p->operand[0].predicate) (target, tmode))
24662 target = gen_reg_rtx (tmode);
24665 for (i = 0; i < nargs; i++)
24667 enum machine_mode mode = insn_p->operand[i + 1].mode;
24670 arg = CALL_EXPR_ARG (exp, i + arg_adjust);
24671 op = expand_normal (arg);
24672 match = (*insn_p->operand[i + 1].predicate) (op, mode);
24674 if (last_arg_constant && (i + 1) == nargs)
24680 error ("the last argument must be an 8-bit immediate");
24688 /* This must be the memory operand. */
24689 op = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, op));
24690 gcc_assert (GET_MODE (op) == mode
24691 || GET_MODE (op) == VOIDmode);
24695 /* This must be register. */
24696 if (VECTOR_MODE_P (mode))
24697 op = safe_vector_operand (op, mode);
24699 gcc_assert (GET_MODE (op) == mode
24700 || GET_MODE (op) == VOIDmode);
24701 op = copy_to_mode_reg (mode, op);
24706 args[i].mode = mode;
24712 pat = GEN_FCN (icode) (target, args[0].op);
24715 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
24718 gcc_unreachable ();
24724 return klass == store ? 0 : target;
24727 /* Return the integer constant in ARG. Constrain it to be in the range
24728 of the subparts of VEC_TYPE; issue an error if not. */
24731 get_element_number (tree vec_type, tree arg)
24733 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
24735 if (!host_integerp (arg, 1)
24736 || (elt = tree_low_cst (arg, 1), elt > max))
24738 error ("selector must be an integer constant in the range 0..%wi", max);
24745 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24746 ix86_expand_vector_init. We DO have language-level syntax for this, in
24747 the form of (type){ init-list }. Except that since we can't place emms
24748 instructions from inside the compiler, we can't allow the use of MMX
24749 registers unless the user explicitly asks for it. So we do *not* define
24750 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
24751 we have builtins invoked by mmintrin.h that gives us license to emit
24752 these sorts of instructions. */
24755 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
24757 enum machine_mode tmode = TYPE_MODE (type);
24758 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
24759 int i, n_elt = GET_MODE_NUNITS (tmode);
24760 rtvec v = rtvec_alloc (n_elt);
24762 gcc_assert (VECTOR_MODE_P (tmode));
24763 gcc_assert (call_expr_nargs (exp) == n_elt);
24765 for (i = 0; i < n_elt; ++i)
24767 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
24768 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
24771 if (!target || !register_operand (target, tmode))
24772 target = gen_reg_rtx (tmode);
24774 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
24778 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24779 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
24780 had a language-level syntax for referencing vector elements. */
24783 ix86_expand_vec_ext_builtin (tree exp, rtx target)
24785 enum machine_mode tmode, mode0;
24790 arg0 = CALL_EXPR_ARG (exp, 0);
24791 arg1 = CALL_EXPR_ARG (exp, 1);
24793 op0 = expand_normal (arg0);
24794 elt = get_element_number (TREE_TYPE (arg0), arg1);
24796 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24797 mode0 = TYPE_MODE (TREE_TYPE (arg0));
24798 gcc_assert (VECTOR_MODE_P (mode0));
24800 op0 = force_reg (mode0, op0);
24802 if (optimize || !target || !register_operand (target, tmode))
24803 target = gen_reg_rtx (tmode);
24805 ix86_expand_vector_extract (true, target, op0, elt);
24810 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24811 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
24812 a language-level syntax for referencing vector elements. */
24815 ix86_expand_vec_set_builtin (tree exp)
24817 enum machine_mode tmode, mode1;
24818 tree arg0, arg1, arg2;
24820 rtx op0, op1, target;
24822 arg0 = CALL_EXPR_ARG (exp, 0);
24823 arg1 = CALL_EXPR_ARG (exp, 1);
24824 arg2 = CALL_EXPR_ARG (exp, 2);
24826 tmode = TYPE_MODE (TREE_TYPE (arg0));
24827 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24828 gcc_assert (VECTOR_MODE_P (tmode));
24830 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
24831 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
24832 elt = get_element_number (TREE_TYPE (arg0), arg2);
24834 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
24835 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
24837 op0 = force_reg (tmode, op0);
24838 op1 = force_reg (mode1, op1);
24840 /* OP0 is the source of these builtin functions and shouldn't be
24841 modified. Create a copy, use it and return it as target. */
24842 target = gen_reg_rtx (tmode);
24843 emit_move_insn (target, op0);
24844 ix86_expand_vector_set (true, target, op1, elt);
24849 /* Expand an expression EXP that calls a built-in function,
24850 with result going to TARGET if that's convenient
24851 (and in mode MODE if that's convenient).
24852 SUBTARGET may be used as the target for computing one of EXP's operands.
24853 IGNORE is nonzero if the value is to be ignored. */
24856 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
24857 enum machine_mode mode ATTRIBUTE_UNUSED,
24858 int ignore ATTRIBUTE_UNUSED)
24860 const struct builtin_description *d;
24862 enum insn_code icode;
24863 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
24864 tree arg0, arg1, arg2;
24865 rtx op0, op1, op2, pat;
24866 enum machine_mode mode0, mode1, mode2;
24867 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
24869 /* Determine whether the builtin function is available under the current ISA.
24870 Originally the builtin was not created if it wasn't applicable to the
24871 current ISA based on the command line switches. With function specific
24872 options, we need to check in the context of the function making the call
24873 whether it is supported. */
24874 if (ix86_builtins_isa[fcode].isa
24875 && !(ix86_builtins_isa[fcode].isa & ix86_isa_flags))
24877 char *opts = ix86_target_string (ix86_builtins_isa[fcode].isa, 0, NULL,
24878 NULL, NULL, false);
24881 error ("%qE needs unknown isa option", fndecl);
24884 gcc_assert (opts != NULL);
24885 error ("%qE needs isa option %s", fndecl, opts);
24893 case IX86_BUILTIN_MASKMOVQ:
24894 case IX86_BUILTIN_MASKMOVDQU:
24895 icode = (fcode == IX86_BUILTIN_MASKMOVQ
24896 ? CODE_FOR_mmx_maskmovq
24897 : CODE_FOR_sse2_maskmovdqu);
24898 /* Note the arg order is different from the operand order. */
24899 arg1 = CALL_EXPR_ARG (exp, 0);
24900 arg2 = CALL_EXPR_ARG (exp, 1);
24901 arg0 = CALL_EXPR_ARG (exp, 2);
24902 op0 = expand_normal (arg0);
24903 op1 = expand_normal (arg1);
24904 op2 = expand_normal (arg2);
24905 mode0 = insn_data[icode].operand[0].mode;
24906 mode1 = insn_data[icode].operand[1].mode;
24907 mode2 = insn_data[icode].operand[2].mode;
24909 op0 = force_reg (Pmode, op0);
24910 op0 = gen_rtx_MEM (mode1, op0);
24912 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
24913 op0 = copy_to_mode_reg (mode0, op0);
24914 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
24915 op1 = copy_to_mode_reg (mode1, op1);
24916 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
24917 op2 = copy_to_mode_reg (mode2, op2);
24918 pat = GEN_FCN (icode) (op0, op1, op2);
24924 case IX86_BUILTIN_LDMXCSR:
24925 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
24926 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24927 emit_move_insn (target, op0);
24928 emit_insn (gen_sse_ldmxcsr (target));
24931 case IX86_BUILTIN_STMXCSR:
24932 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24933 emit_insn (gen_sse_stmxcsr (target));
24934 return copy_to_mode_reg (SImode, target);
24936 case IX86_BUILTIN_CLFLUSH:
24937 arg0 = CALL_EXPR_ARG (exp, 0);
24938 op0 = expand_normal (arg0);
24939 icode = CODE_FOR_sse2_clflush;
24940 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
24941 op0 = copy_to_mode_reg (Pmode, op0);
24943 emit_insn (gen_sse2_clflush (op0));
24946 case IX86_BUILTIN_MONITOR:
24947 arg0 = CALL_EXPR_ARG (exp, 0);
24948 arg1 = CALL_EXPR_ARG (exp, 1);
24949 arg2 = CALL_EXPR_ARG (exp, 2);
24950 op0 = expand_normal (arg0);
24951 op1 = expand_normal (arg1);
24952 op2 = expand_normal (arg2);
24954 op0 = copy_to_mode_reg (Pmode, op0);
24956 op1 = copy_to_mode_reg (SImode, op1);
24958 op2 = copy_to_mode_reg (SImode, op2);
24959 emit_insn ((*ix86_gen_monitor) (op0, op1, op2));
24962 case IX86_BUILTIN_MWAIT:
24963 arg0 = CALL_EXPR_ARG (exp, 0);
24964 arg1 = CALL_EXPR_ARG (exp, 1);
24965 op0 = expand_normal (arg0);
24966 op1 = expand_normal (arg1);
24968 op0 = copy_to_mode_reg (SImode, op0);
24970 op1 = copy_to_mode_reg (SImode, op1);
24971 emit_insn (gen_sse3_mwait (op0, op1));
24974 case IX86_BUILTIN_VEC_INIT_V2SI:
24975 case IX86_BUILTIN_VEC_INIT_V4HI:
24976 case IX86_BUILTIN_VEC_INIT_V8QI:
24977 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
24979 case IX86_BUILTIN_VEC_EXT_V2DF:
24980 case IX86_BUILTIN_VEC_EXT_V2DI:
24981 case IX86_BUILTIN_VEC_EXT_V4SF:
24982 case IX86_BUILTIN_VEC_EXT_V4SI:
24983 case IX86_BUILTIN_VEC_EXT_V8HI:
24984 case IX86_BUILTIN_VEC_EXT_V2SI:
24985 case IX86_BUILTIN_VEC_EXT_V4HI:
24986 case IX86_BUILTIN_VEC_EXT_V16QI:
24987 return ix86_expand_vec_ext_builtin (exp, target);
24989 case IX86_BUILTIN_VEC_SET_V2DI:
24990 case IX86_BUILTIN_VEC_SET_V4SF:
24991 case IX86_BUILTIN_VEC_SET_V4SI:
24992 case IX86_BUILTIN_VEC_SET_V8HI:
24993 case IX86_BUILTIN_VEC_SET_V4HI:
24994 case IX86_BUILTIN_VEC_SET_V16QI:
24995 return ix86_expand_vec_set_builtin (exp);
24997 case IX86_BUILTIN_INFQ:
24999 REAL_VALUE_TYPE inf;
25003 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
25005 tmp = validize_mem (force_const_mem (mode, tmp));
25008 target = gen_reg_rtx (mode);
25010 emit_move_insn (target, tmp);
25018 for (i = 0, d = bdesc_special_args;
25019 i < ARRAY_SIZE (bdesc_special_args);
25021 if (d->code == fcode)
25022 return ix86_expand_special_args_builtin (d, exp, target);
25024 for (i = 0, d = bdesc_args;
25025 i < ARRAY_SIZE (bdesc_args);
25027 if (d->code == fcode)
25030 case IX86_BUILTIN_FABSQ:
25031 case IX86_BUILTIN_COPYSIGNQ:
25033 /* Emit a normal call if SSE2 isn't available. */
25034 return expand_call (exp, target, ignore);
25036 return ix86_expand_args_builtin (d, exp, target);
25039 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
25040 if (d->code == fcode)
25041 return ix86_expand_sse_comi (d, exp, target);
25043 for (i = 0, d = bdesc_pcmpestr;
25044 i < ARRAY_SIZE (bdesc_pcmpestr);
25046 if (d->code == fcode)
25047 return ix86_expand_sse_pcmpestr (d, exp, target);
25049 for (i = 0, d = bdesc_pcmpistr;
25050 i < ARRAY_SIZE (bdesc_pcmpistr);
25052 if (d->code == fcode)
25053 return ix86_expand_sse_pcmpistr (d, exp, target);
25055 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
25056 if (d->code == fcode)
25057 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
25058 (enum multi_arg_type)d->flag,
25061 gcc_unreachable ();
25064 /* Returns a function decl for a vectorized version of the builtin function
25065 with builtin function code FN and the result vector type TYPE, or NULL_TREE
25066 if it is not available. */
25069 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
25072 enum machine_mode in_mode, out_mode;
25075 if (TREE_CODE (type_out) != VECTOR_TYPE
25076 || TREE_CODE (type_in) != VECTOR_TYPE)
25079 out_mode = TYPE_MODE (TREE_TYPE (type_out));
25080 out_n = TYPE_VECTOR_SUBPARTS (type_out);
25081 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25082 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25086 case BUILT_IN_SQRT:
25087 if (out_mode == DFmode && out_n == 2
25088 && in_mode == DFmode && in_n == 2)
25089 return ix86_builtins[IX86_BUILTIN_SQRTPD];
25092 case BUILT_IN_SQRTF:
25093 if (out_mode == SFmode && out_n == 4
25094 && in_mode == SFmode && in_n == 4)
25095 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
25098 case BUILT_IN_LRINT:
25099 if (out_mode == SImode && out_n == 4
25100 && in_mode == DFmode && in_n == 2)
25101 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
25104 case BUILT_IN_LRINTF:
25105 if (out_mode == SImode && out_n == 4
25106 && in_mode == SFmode && in_n == 4)
25107 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
25114 /* Dispatch to a handler for a vectorization library. */
25115 if (ix86_veclib_handler)
25116 return (*ix86_veclib_handler)(fn, type_out, type_in);
25121 /* Handler for an SVML-style interface to
25122 a library with vectorized intrinsics. */
25125 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
25128 tree fntype, new_fndecl, args;
25131 enum machine_mode el_mode, in_mode;
25134 /* The SVML is suitable for unsafe math only. */
25135 if (!flag_unsafe_math_optimizations)
25138 el_mode = TYPE_MODE (TREE_TYPE (type_out));
25139 n = TYPE_VECTOR_SUBPARTS (type_out);
25140 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25141 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25142 if (el_mode != in_mode
25150 case BUILT_IN_LOG10:
25152 case BUILT_IN_TANH:
25154 case BUILT_IN_ATAN:
25155 case BUILT_IN_ATAN2:
25156 case BUILT_IN_ATANH:
25157 case BUILT_IN_CBRT:
25158 case BUILT_IN_SINH:
25160 case BUILT_IN_ASINH:
25161 case BUILT_IN_ASIN:
25162 case BUILT_IN_COSH:
25164 case BUILT_IN_ACOSH:
25165 case BUILT_IN_ACOS:
25166 if (el_mode != DFmode || n != 2)
25170 case BUILT_IN_EXPF:
25171 case BUILT_IN_LOGF:
25172 case BUILT_IN_LOG10F:
25173 case BUILT_IN_POWF:
25174 case BUILT_IN_TANHF:
25175 case BUILT_IN_TANF:
25176 case BUILT_IN_ATANF:
25177 case BUILT_IN_ATAN2F:
25178 case BUILT_IN_ATANHF:
25179 case BUILT_IN_CBRTF:
25180 case BUILT_IN_SINHF:
25181 case BUILT_IN_SINF:
25182 case BUILT_IN_ASINHF:
25183 case BUILT_IN_ASINF:
25184 case BUILT_IN_COSHF:
25185 case BUILT_IN_COSF:
25186 case BUILT_IN_ACOSHF:
25187 case BUILT_IN_ACOSF:
25188 if (el_mode != SFmode || n != 4)
25196 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
25198 if (fn == BUILT_IN_LOGF)
25199 strcpy (name, "vmlsLn4");
25200 else if (fn == BUILT_IN_LOG)
25201 strcpy (name, "vmldLn2");
25204 sprintf (name, "vmls%s", bname+10);
25205 name[strlen (name)-1] = '4';
25208 sprintf (name, "vmld%s2", bname+10);
25210 /* Convert to uppercase. */
25214 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25215 args = TREE_CHAIN (args))
25219 fntype = build_function_type_list (type_out, type_in, NULL);
25221 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25223 /* Build a function declaration for the vectorized function. */
25224 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
25225 TREE_PUBLIC (new_fndecl) = 1;
25226 DECL_EXTERNAL (new_fndecl) = 1;
25227 DECL_IS_NOVOPS (new_fndecl) = 1;
25228 TREE_READONLY (new_fndecl) = 1;
25233 /* Handler for an ACML-style interface to
25234 a library with vectorized intrinsics. */
25237 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
25239 char name[20] = "__vr.._";
25240 tree fntype, new_fndecl, args;
25243 enum machine_mode el_mode, in_mode;
25246 /* The ACML is 64bits only and suitable for unsafe math only as
25247 it does not correctly support parts of IEEE with the required
25248 precision such as denormals. */
25250 || !flag_unsafe_math_optimizations)
25253 el_mode = TYPE_MODE (TREE_TYPE (type_out));
25254 n = TYPE_VECTOR_SUBPARTS (type_out);
25255 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25256 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25257 if (el_mode != in_mode
25267 case BUILT_IN_LOG2:
25268 case BUILT_IN_LOG10:
25271 if (el_mode != DFmode
25276 case BUILT_IN_SINF:
25277 case BUILT_IN_COSF:
25278 case BUILT_IN_EXPF:
25279 case BUILT_IN_POWF:
25280 case BUILT_IN_LOGF:
25281 case BUILT_IN_LOG2F:
25282 case BUILT_IN_LOG10F:
25285 if (el_mode != SFmode
25294 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
25295 sprintf (name + 7, "%s", bname+10);
25298 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25299 args = TREE_CHAIN (args))
25303 fntype = build_function_type_list (type_out, type_in, NULL);
25305 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25307 /* Build a function declaration for the vectorized function. */
25308 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
25309 TREE_PUBLIC (new_fndecl) = 1;
25310 DECL_EXTERNAL (new_fndecl) = 1;
25311 DECL_IS_NOVOPS (new_fndecl) = 1;
25312 TREE_READONLY (new_fndecl) = 1;
25318 /* Returns a decl of a function that implements conversion of an integer vector
25319 into a floating-point vector, or vice-versa. TYPE is the type of the integer
25320 side of the conversion.
25321 Return NULL_TREE if it is not available. */
25324 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
25326 if (!TARGET_SSE2 || TREE_CODE (type) != VECTOR_TYPE
25327 /* There are only conversions from/to signed integers. */
25328 || TYPE_UNSIGNED (TREE_TYPE (type)))
25334 switch (TYPE_MODE (type))
25337 return ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
25342 case FIX_TRUNC_EXPR:
25343 switch (TYPE_MODE (type))
25346 return ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
25356 /* Returns a code for a target-specific builtin that implements
25357 reciprocal of the function, or NULL_TREE if not available. */
25360 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
25361 bool sqrt ATTRIBUTE_UNUSED)
25363 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
25364 && flag_finite_math_only && !flag_trapping_math
25365 && flag_unsafe_math_optimizations))
25369 /* Machine dependent builtins. */
25372 /* Vectorized version of sqrt to rsqrt conversion. */
25373 case IX86_BUILTIN_SQRTPS_NR:
25374 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
25380 /* Normal builtins. */
25383 /* Sqrt to rsqrt conversion. */
25384 case BUILT_IN_SQRTF:
25385 return ix86_builtins[IX86_BUILTIN_RSQRTF];
25392 /* Store OPERAND to the memory after reload is completed. This means
25393 that we can't easily use assign_stack_local. */
25395 ix86_force_to_memory (enum machine_mode mode, rtx operand)
25399 gcc_assert (reload_completed);
25400 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE)
25402 result = gen_rtx_MEM (mode,
25403 gen_rtx_PLUS (Pmode,
25405 GEN_INT (-RED_ZONE_SIZE)));
25406 emit_move_insn (result, operand);
25408 else if ((TARGET_64BIT_MS_ABI || !TARGET_RED_ZONE) && TARGET_64BIT)
25414 operand = gen_lowpart (DImode, operand);
25418 gen_rtx_SET (VOIDmode,
25419 gen_rtx_MEM (DImode,
25420 gen_rtx_PRE_DEC (DImode,
25421 stack_pointer_rtx)),
25425 gcc_unreachable ();
25427 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25436 split_di (&operand, 1, operands, operands + 1);
25438 gen_rtx_SET (VOIDmode,
25439 gen_rtx_MEM (SImode,
25440 gen_rtx_PRE_DEC (Pmode,
25441 stack_pointer_rtx)),
25444 gen_rtx_SET (VOIDmode,
25445 gen_rtx_MEM (SImode,
25446 gen_rtx_PRE_DEC (Pmode,
25447 stack_pointer_rtx)),
25452 /* Store HImodes as SImodes. */
25453 operand = gen_lowpart (SImode, operand);
25457 gen_rtx_SET (VOIDmode,
25458 gen_rtx_MEM (GET_MODE (operand),
25459 gen_rtx_PRE_DEC (SImode,
25460 stack_pointer_rtx)),
25464 gcc_unreachable ();
25466 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25471 /* Free operand from the memory. */
25473 ix86_free_from_memory (enum machine_mode mode)
25475 if (!TARGET_RED_ZONE || TARGET_64BIT_MS_ABI)
25479 if (mode == DImode || TARGET_64BIT)
25483 /* Use LEA to deallocate stack space. In peephole2 it will be converted
25484 to pop or add instruction if registers are available. */
25485 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
25486 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25491 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
25492 QImode must go into class Q_REGS.
25493 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
25494 movdf to do mem-to-mem moves through integer regs. */
25496 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
25498 enum machine_mode mode = GET_MODE (x);
25500 /* We're only allowed to return a subclass of CLASS. Many of the
25501 following checks fail for NO_REGS, so eliminate that early. */
25502 if (regclass == NO_REGS)
25505 /* All classes can load zeros. */
25506 if (x == CONST0_RTX (mode))
25509 /* Force constants into memory if we are loading a (nonzero) constant into
25510 an MMX or SSE register. This is because there are no MMX/SSE instructions
25511 to load from a constant. */
25513 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
25516 /* Prefer SSE regs only, if we can use them for math. */
25517 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
25518 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
25520 /* Floating-point constants need more complex checks. */
25521 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
25523 /* General regs can load everything. */
25524 if (reg_class_subset_p (regclass, GENERAL_REGS))
25527 /* Floats can load 0 and 1 plus some others. Note that we eliminated
25528 zero above. We only want to wind up preferring 80387 registers if
25529 we plan on doing computation with them. */
25531 && standard_80387_constant_p (x))
25533 /* Limit class to non-sse. */
25534 if (regclass == FLOAT_SSE_REGS)
25536 if (regclass == FP_TOP_SSE_REGS)
25538 if (regclass == FP_SECOND_SSE_REGS)
25539 return FP_SECOND_REG;
25540 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
25547 /* Generally when we see PLUS here, it's the function invariant
25548 (plus soft-fp const_int). Which can only be computed into general
25550 if (GET_CODE (x) == PLUS)
25551 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
25553 /* QImode constants are easy to load, but non-constant QImode data
25554 must go into Q_REGS. */
25555 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
25557 if (reg_class_subset_p (regclass, Q_REGS))
25559 if (reg_class_subset_p (Q_REGS, regclass))
25567 /* Discourage putting floating-point values in SSE registers unless
25568 SSE math is being used, and likewise for the 387 registers. */
25570 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
25572 enum machine_mode mode = GET_MODE (x);
25574 /* Restrict the output reload class to the register bank that we are doing
25575 math on. If we would like not to return a subset of CLASS, reject this
25576 alternative: if reload cannot do this, it will still use its choice. */
25577 mode = GET_MODE (x);
25578 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
25579 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
25581 if (X87_FLOAT_MODE_P (mode))
25583 if (regclass == FP_TOP_SSE_REGS)
25585 else if (regclass == FP_SECOND_SSE_REGS)
25586 return FP_SECOND_REG;
25588 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
25594 static enum reg_class
25595 ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
25596 enum machine_mode mode,
25597 secondary_reload_info *sri ATTRIBUTE_UNUSED)
25599 /* QImode spills from non-QI registers require
25600 intermediate register on 32bit targets. */
25601 if (!in_p && mode == QImode && !TARGET_64BIT
25602 && (rclass == GENERAL_REGS
25603 || rclass == LEGACY_REGS
25604 || rclass == INDEX_REGS))
25613 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
25614 regno = true_regnum (x);
25616 /* Return Q_REGS if the operand is in memory. */
25624 /* If we are copying between general and FP registers, we need a memory
25625 location. The same is true for SSE and MMX registers.
25627 To optimize register_move_cost performance, allow inline variant.
25629 The macro can't work reliably when one of the CLASSES is class containing
25630 registers from multiple units (SSE, MMX, integer). We avoid this by never
25631 combining those units in single alternative in the machine description.
25632 Ensure that this constraint holds to avoid unexpected surprises.
25634 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
25635 enforce these sanity checks. */
25638 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25639 enum machine_mode mode, int strict)
25641 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
25642 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
25643 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
25644 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
25645 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
25646 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
25648 gcc_assert (!strict);
25652 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
25655 /* ??? This is a lie. We do have moves between mmx/general, and for
25656 mmx/sse2. But by saying we need secondary memory we discourage the
25657 register allocator from using the mmx registers unless needed. */
25658 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
25661 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25663 /* SSE1 doesn't have any direct moves from other classes. */
25667 /* If the target says that inter-unit moves are more expensive
25668 than moving through memory, then don't generate them. */
25669 if (!TARGET_INTER_UNIT_MOVES)
25672 /* Between SSE and general, we have moves no larger than word size. */
25673 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
25681 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25682 enum machine_mode mode, int strict)
25684 return inline_secondary_memory_needed (class1, class2, mode, strict);
25687 /* Return true if the registers in CLASS cannot represent the change from
25688 modes FROM to TO. */
25691 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
25692 enum reg_class regclass)
25697 /* x87 registers can't do subreg at all, as all values are reformatted
25698 to extended precision. */
25699 if (MAYBE_FLOAT_CLASS_P (regclass))
25702 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
25704 /* Vector registers do not support QI or HImode loads. If we don't
25705 disallow a change to these modes, reload will assume it's ok to
25706 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
25707 the vec_dupv4hi pattern. */
25708 if (GET_MODE_SIZE (from) < 4)
25711 /* Vector registers do not support subreg with nonzero offsets, which
25712 are otherwise valid for integer registers. Since we can't see
25713 whether we have a nonzero offset from here, prohibit all
25714 nonparadoxical subregs changing size. */
25715 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
25722 /* Return the cost of moving data of mode M between a
25723 register and memory. A value of 2 is the default; this cost is
25724 relative to those in `REGISTER_MOVE_COST'.
25726 This function is used extensively by register_move_cost that is used to
25727 build tables at startup. Make it inline in this case.
25728 When IN is 2, return maximum of in and out move cost.
25730 If moving between registers and memory is more expensive than
25731 between two registers, you should define this macro to express the
25734 Model also increased moving costs of QImode registers in non
25738 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
25742 if (FLOAT_CLASS_P (regclass))
25760 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
25761 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
25763 if (SSE_CLASS_P (regclass))
25766 switch (GET_MODE_SIZE (mode))
25781 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
25782 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
25784 if (MMX_CLASS_P (regclass))
25787 switch (GET_MODE_SIZE (mode))
25799 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
25800 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
25802 switch (GET_MODE_SIZE (mode))
25805 if (Q_CLASS_P (regclass) || TARGET_64BIT)
25808 return ix86_cost->int_store[0];
25809 if (TARGET_PARTIAL_REG_DEPENDENCY
25810 && optimize_function_for_speed_p (cfun))
25811 cost = ix86_cost->movzbl_load;
25813 cost = ix86_cost->int_load[0];
25815 return MAX (cost, ix86_cost->int_store[0]);
25821 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
25823 return ix86_cost->movzbl_load;
25825 return ix86_cost->int_store[0] + 4;
25830 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
25831 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
25833 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
25834 if (mode == TFmode)
25837 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
25839 cost = ix86_cost->int_load[2];
25841 cost = ix86_cost->int_store[2];
25842 return (cost * (((int) GET_MODE_SIZE (mode)
25843 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
25848 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
25850 return inline_memory_move_cost (mode, regclass, in);
25854 /* Return the cost of moving data from a register in class CLASS1 to
25855 one in class CLASS2.
25857 It is not required that the cost always equal 2 when FROM is the same as TO;
25858 on some machines it is expensive to move between registers if they are not
25859 general registers. */
25862 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
25863 enum reg_class class2)
25865 /* In case we require secondary memory, compute cost of the store followed
25866 by load. In order to avoid bad register allocation choices, we need
25867 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
25869 if (inline_secondary_memory_needed (class1, class2, mode, 0))
25873 cost += inline_memory_move_cost (mode, class1, 2);
25874 cost += inline_memory_move_cost (mode, class2, 2);
25876 /* In case of copying from general_purpose_register we may emit multiple
25877 stores followed by single load causing memory size mismatch stall.
25878 Count this as arbitrarily high cost of 20. */
25879 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
25882 /* In the case of FP/MMX moves, the registers actually overlap, and we
25883 have to switch modes in order to treat them differently. */
25884 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
25885 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
25891 /* Moves between SSE/MMX and integer unit are expensive. */
25892 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
25893 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25895 /* ??? By keeping returned value relatively high, we limit the number
25896 of moves between integer and MMX/SSE registers for all targets.
25897 Additionally, high value prevents problem with x86_modes_tieable_p(),
25898 where integer modes in MMX/SSE registers are not tieable
25899 because of missing QImode and HImode moves to, from or between
25900 MMX/SSE registers. */
25901 return MAX (8, ix86_cost->mmxsse_to_integer);
25903 if (MAYBE_FLOAT_CLASS_P (class1))
25904 return ix86_cost->fp_move;
25905 if (MAYBE_SSE_CLASS_P (class1))
25906 return ix86_cost->sse_move;
25907 if (MAYBE_MMX_CLASS_P (class1))
25908 return ix86_cost->mmx_move;
25912 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
25915 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
25917 /* Flags and only flags can only hold CCmode values. */
25918 if (CC_REGNO_P (regno))
25919 return GET_MODE_CLASS (mode) == MODE_CC;
25920 if (GET_MODE_CLASS (mode) == MODE_CC
25921 || GET_MODE_CLASS (mode) == MODE_RANDOM
25922 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
25924 if (FP_REGNO_P (regno))
25925 return VALID_FP_MODE_P (mode);
25926 if (SSE_REGNO_P (regno))
25928 /* We implement the move patterns for all vector modes into and
25929 out of SSE registers, even when no operation instructions
25930 are available. OImode move is available only when AVX is
25932 return ((TARGET_AVX && mode == OImode)
25933 || VALID_AVX256_REG_MODE (mode)
25934 || VALID_SSE_REG_MODE (mode)
25935 || VALID_SSE2_REG_MODE (mode)
25936 || VALID_MMX_REG_MODE (mode)
25937 || VALID_MMX_REG_MODE_3DNOW (mode));
25939 if (MMX_REGNO_P (regno))
25941 /* We implement the move patterns for 3DNOW modes even in MMX mode,
25942 so if the register is available at all, then we can move data of
25943 the given mode into or out of it. */
25944 return (VALID_MMX_REG_MODE (mode)
25945 || VALID_MMX_REG_MODE_3DNOW (mode));
25948 if (mode == QImode)
25950 /* Take care for QImode values - they can be in non-QI regs,
25951 but then they do cause partial register stalls. */
25952 if (regno <= BX_REG || TARGET_64BIT)
25954 if (!TARGET_PARTIAL_REG_STALL)
25956 return reload_in_progress || reload_completed;
25958 /* We handle both integer and floats in the general purpose registers. */
25959 else if (VALID_INT_MODE_P (mode))
25961 else if (VALID_FP_MODE_P (mode))
25963 else if (VALID_DFP_MODE_P (mode))
25965 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
25966 on to use that value in smaller contexts, this can easily force a
25967 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
25968 supporting DImode, allow it. */
25969 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
25975 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
25976 tieable integer mode. */
25979 ix86_tieable_integer_mode_p (enum machine_mode mode)
25988 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
25991 return TARGET_64BIT;
25998 /* Return true if MODE1 is accessible in a register that can hold MODE2
25999 without copying. That is, all register classes that can hold MODE2
26000 can also hold MODE1. */
26003 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
26005 if (mode1 == mode2)
26008 if (ix86_tieable_integer_mode_p (mode1)
26009 && ix86_tieable_integer_mode_p (mode2))
26012 /* MODE2 being XFmode implies fp stack or general regs, which means we
26013 can tie any smaller floating point modes to it. Note that we do not
26014 tie this with TFmode. */
26015 if (mode2 == XFmode)
26016 return mode1 == SFmode || mode1 == DFmode;
26018 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
26019 that we can tie it with SFmode. */
26020 if (mode2 == DFmode)
26021 return mode1 == SFmode;
26023 /* If MODE2 is only appropriate for an SSE register, then tie with
26024 any other mode acceptable to SSE registers. */
26025 if (GET_MODE_SIZE (mode2) == 16
26026 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
26027 return (GET_MODE_SIZE (mode1) == 16
26028 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
26030 /* If MODE2 is appropriate for an MMX register, then tie
26031 with any other mode acceptable to MMX registers. */
26032 if (GET_MODE_SIZE (mode2) == 8
26033 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
26034 return (GET_MODE_SIZE (mode1) == 8
26035 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
26040 /* Compute a (partial) cost for rtx X. Return true if the complete
26041 cost has been computed, and false if subexpressions should be
26042 scanned. In either case, *TOTAL contains the cost result. */
26045 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total, bool speed)
26047 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
26048 enum machine_mode mode = GET_MODE (x);
26049 const struct processor_costs *cost = speed ? ix86_cost : &ix86_size_cost;
26057 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
26059 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
26061 else if (flag_pic && SYMBOLIC_CONST (x)
26063 || (!GET_CODE (x) != LABEL_REF
26064 && (GET_CODE (x) != SYMBOL_REF
26065 || !SYMBOL_REF_LOCAL_P (x)))))
26072 if (mode == VOIDmode)
26075 switch (standard_80387_constant_p (x))
26080 default: /* Other constants */
26085 /* Start with (MEM (SYMBOL_REF)), since that's where
26086 it'll probably end up. Add a penalty for size. */
26087 *total = (COSTS_N_INSNS (1)
26088 + (flag_pic != 0 && !TARGET_64BIT)
26089 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
26095 /* The zero extensions is often completely free on x86_64, so make
26096 it as cheap as possible. */
26097 if (TARGET_64BIT && mode == DImode
26098 && GET_MODE (XEXP (x, 0)) == SImode)
26100 else if (TARGET_ZERO_EXTEND_WITH_AND)
26101 *total = cost->add;
26103 *total = cost->movzx;
26107 *total = cost->movsx;
26111 if (CONST_INT_P (XEXP (x, 1))
26112 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
26114 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
26117 *total = cost->add;
26120 if ((value == 2 || value == 3)
26121 && cost->lea <= cost->shift_const)
26123 *total = cost->lea;
26133 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
26135 if (CONST_INT_P (XEXP (x, 1)))
26137 if (INTVAL (XEXP (x, 1)) > 32)
26138 *total = cost->shift_const + COSTS_N_INSNS (2);
26140 *total = cost->shift_const * 2;
26144 if (GET_CODE (XEXP (x, 1)) == AND)
26145 *total = cost->shift_var * 2;
26147 *total = cost->shift_var * 6 + COSTS_N_INSNS (2);
26152 if (CONST_INT_P (XEXP (x, 1)))
26153 *total = cost->shift_const;
26155 *total = cost->shift_var;
26160 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26162 /* ??? SSE scalar cost should be used here. */
26163 *total = cost->fmul;
26166 else if (X87_FLOAT_MODE_P (mode))
26168 *total = cost->fmul;
26171 else if (FLOAT_MODE_P (mode))
26173 /* ??? SSE vector cost should be used here. */
26174 *total = cost->fmul;
26179 rtx op0 = XEXP (x, 0);
26180 rtx op1 = XEXP (x, 1);
26182 if (CONST_INT_P (XEXP (x, 1)))
26184 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
26185 for (nbits = 0; value != 0; value &= value - 1)
26189 /* This is arbitrary. */
26192 /* Compute costs correctly for widening multiplication. */
26193 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
26194 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
26195 == GET_MODE_SIZE (mode))
26197 int is_mulwiden = 0;
26198 enum machine_mode inner_mode = GET_MODE (op0);
26200 if (GET_CODE (op0) == GET_CODE (op1))
26201 is_mulwiden = 1, op1 = XEXP (op1, 0);
26202 else if (CONST_INT_P (op1))
26204 if (GET_CODE (op0) == SIGN_EXTEND)
26205 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
26208 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
26212 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
26215 *total = (cost->mult_init[MODE_INDEX (mode)]
26216 + nbits * cost->mult_bit
26217 + rtx_cost (op0, outer_code, speed) + rtx_cost (op1, outer_code, speed));
26226 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26227 /* ??? SSE cost should be used here. */
26228 *total = cost->fdiv;
26229 else if (X87_FLOAT_MODE_P (mode))
26230 *total = cost->fdiv;
26231 else if (FLOAT_MODE_P (mode))
26232 /* ??? SSE vector cost should be used here. */
26233 *total = cost->fdiv;
26235 *total = cost->divide[MODE_INDEX (mode)];
26239 if (GET_MODE_CLASS (mode) == MODE_INT
26240 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
26242 if (GET_CODE (XEXP (x, 0)) == PLUS
26243 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
26244 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
26245 && CONSTANT_P (XEXP (x, 1)))
26247 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
26248 if (val == 2 || val == 4 || val == 8)
26250 *total = cost->lea;
26251 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26252 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
26253 outer_code, speed);
26254 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26258 else if (GET_CODE (XEXP (x, 0)) == MULT
26259 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
26261 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
26262 if (val == 2 || val == 4 || val == 8)
26264 *total = cost->lea;
26265 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
26266 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26270 else if (GET_CODE (XEXP (x, 0)) == PLUS)
26272 *total = cost->lea;
26273 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
26274 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26275 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26282 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26284 /* ??? SSE cost should be used here. */
26285 *total = cost->fadd;
26288 else if (X87_FLOAT_MODE_P (mode))
26290 *total = cost->fadd;
26293 else if (FLOAT_MODE_P (mode))
26295 /* ??? SSE vector cost should be used here. */
26296 *total = cost->fadd;
26304 if (!TARGET_64BIT && mode == DImode)
26306 *total = (cost->add * 2
26307 + (rtx_cost (XEXP (x, 0), outer_code, speed)
26308 << (GET_MODE (XEXP (x, 0)) != DImode))
26309 + (rtx_cost (XEXP (x, 1), outer_code, speed)
26310 << (GET_MODE (XEXP (x, 1)) != DImode)));
26316 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26318 /* ??? SSE cost should be used here. */
26319 *total = cost->fchs;
26322 else if (X87_FLOAT_MODE_P (mode))
26324 *total = cost->fchs;
26327 else if (FLOAT_MODE_P (mode))
26329 /* ??? SSE vector cost should be used here. */
26330 *total = cost->fchs;
26336 if (!TARGET_64BIT && mode == DImode)
26337 *total = cost->add * 2;
26339 *total = cost->add;
26343 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
26344 && XEXP (XEXP (x, 0), 1) == const1_rtx
26345 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
26346 && XEXP (x, 1) == const0_rtx)
26348 /* This kind of construct is implemented using test[bwl].
26349 Treat it as if we had an AND. */
26350 *total = (cost->add
26351 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed)
26352 + rtx_cost (const1_rtx, outer_code, speed));
26358 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
26363 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26364 /* ??? SSE cost should be used here. */
26365 *total = cost->fabs;
26366 else if (X87_FLOAT_MODE_P (mode))
26367 *total = cost->fabs;
26368 else if (FLOAT_MODE_P (mode))
26369 /* ??? SSE vector cost should be used here. */
26370 *total = cost->fabs;
26374 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26375 /* ??? SSE cost should be used here. */
26376 *total = cost->fsqrt;
26377 else if (X87_FLOAT_MODE_P (mode))
26378 *total = cost->fsqrt;
26379 else if (FLOAT_MODE_P (mode))
26380 /* ??? SSE vector cost should be used here. */
26381 *total = cost->fsqrt;
26385 if (XINT (x, 1) == UNSPEC_TP)
26396 static int current_machopic_label_num;
26398 /* Given a symbol name and its associated stub, write out the
26399 definition of the stub. */
26402 machopic_output_stub (FILE *file, const char *symb, const char *stub)
26404 unsigned int length;
26405 char *binder_name, *symbol_name, lazy_ptr_name[32];
26406 int label = ++current_machopic_label_num;
26408 /* For 64-bit we shouldn't get here. */
26409 gcc_assert (!TARGET_64BIT);
26411 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
26412 symb = (*targetm.strip_name_encoding) (symb);
26414 length = strlen (stub);
26415 binder_name = XALLOCAVEC (char, length + 32);
26416 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
26418 length = strlen (symb);
26419 symbol_name = XALLOCAVEC (char, length + 32);
26420 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
26422 sprintf (lazy_ptr_name, "L%d$lz", label);
26425 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
26427 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
26429 fprintf (file, "%s:\n", stub);
26430 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26434 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
26435 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
26436 fprintf (file, "\tjmp\t*%%edx\n");
26439 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
26441 fprintf (file, "%s:\n", binder_name);
26445 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
26446 fprintf (file, "\tpushl\t%%eax\n");
26449 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
26451 fprintf (file, "\tjmp\tdyld_stub_binding_helper\n");
26453 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
26454 fprintf (file, "%s:\n", lazy_ptr_name);
26455 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26456 fprintf (file, "\t.long %s\n", binder_name);
26460 darwin_x86_file_end (void)
26462 darwin_file_end ();
26465 #endif /* TARGET_MACHO */
26467 /* Order the registers for register allocator. */
26470 x86_order_regs_for_local_alloc (void)
26475 /* First allocate the local general purpose registers. */
26476 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26477 if (GENERAL_REGNO_P (i) && call_used_regs[i])
26478 reg_alloc_order [pos++] = i;
26480 /* Global general purpose registers. */
26481 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26482 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
26483 reg_alloc_order [pos++] = i;
26485 /* x87 registers come first in case we are doing FP math
26487 if (!TARGET_SSE_MATH)
26488 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26489 reg_alloc_order [pos++] = i;
26491 /* SSE registers. */
26492 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
26493 reg_alloc_order [pos++] = i;
26494 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
26495 reg_alloc_order [pos++] = i;
26497 /* x87 registers. */
26498 if (TARGET_SSE_MATH)
26499 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26500 reg_alloc_order [pos++] = i;
26502 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
26503 reg_alloc_order [pos++] = i;
26505 /* Initialize the rest of array as we do not allocate some registers
26507 while (pos < FIRST_PSEUDO_REGISTER)
26508 reg_alloc_order [pos++] = 0;
26511 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
26512 struct attribute_spec.handler. */
26514 ix86_handle_abi_attribute (tree *node, tree name,
26515 tree args ATTRIBUTE_UNUSED,
26516 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26518 if (TREE_CODE (*node) != FUNCTION_TYPE
26519 && TREE_CODE (*node) != METHOD_TYPE
26520 && TREE_CODE (*node) != FIELD_DECL
26521 && TREE_CODE (*node) != TYPE_DECL)
26523 warning (OPT_Wattributes, "%qs attribute only applies to functions",
26524 IDENTIFIER_POINTER (name));
26525 *no_add_attrs = true;
26530 warning (OPT_Wattributes, "%qs attribute only available for 64-bit",
26531 IDENTIFIER_POINTER (name));
26532 *no_add_attrs = true;
26536 /* Can combine regparm with all attributes but fastcall. */
26537 if (is_attribute_p ("ms_abi", name))
26539 if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (*node)))
26541 error ("ms_abi and sysv_abi attributes are not compatible");
26546 else if (is_attribute_p ("sysv_abi", name))
26548 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (*node)))
26550 error ("ms_abi and sysv_abi attributes are not compatible");
26559 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
26560 struct attribute_spec.handler. */
26562 ix86_handle_struct_attribute (tree *node, tree name,
26563 tree args ATTRIBUTE_UNUSED,
26564 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26567 if (DECL_P (*node))
26569 if (TREE_CODE (*node) == TYPE_DECL)
26570 type = &TREE_TYPE (*node);
26575 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
26576 || TREE_CODE (*type) == UNION_TYPE)))
26578 warning (OPT_Wattributes, "%qs attribute ignored",
26579 IDENTIFIER_POINTER (name));
26580 *no_add_attrs = true;
26583 else if ((is_attribute_p ("ms_struct", name)
26584 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
26585 || ((is_attribute_p ("gcc_struct", name)
26586 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
26588 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
26589 IDENTIFIER_POINTER (name));
26590 *no_add_attrs = true;
26597 ix86_ms_bitfield_layout_p (const_tree record_type)
26599 return (TARGET_MS_BITFIELD_LAYOUT &&
26600 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
26601 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
26604 /* Returns an expression indicating where the this parameter is
26605 located on entry to the FUNCTION. */
26608 x86_this_parameter (tree function)
26610 tree type = TREE_TYPE (function);
26611 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
26616 const int *parm_regs;
26618 if (ix86_function_type_abi (type) == MS_ABI)
26619 parm_regs = x86_64_ms_abi_int_parameter_registers;
26621 parm_regs = x86_64_int_parameter_registers;
26622 return gen_rtx_REG (DImode, parm_regs[aggr]);
26625 nregs = ix86_function_regparm (type, function);
26627 if (nregs > 0 && !stdarg_p (type))
26631 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
26632 regno = aggr ? DX_REG : CX_REG;
26640 return gen_rtx_MEM (SImode,
26641 plus_constant (stack_pointer_rtx, 4));
26644 return gen_rtx_REG (SImode, regno);
26647 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
26650 /* Determine whether x86_output_mi_thunk can succeed. */
26653 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
26654 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
26655 HOST_WIDE_INT vcall_offset, const_tree function)
26657 /* 64-bit can handle anything. */
26661 /* For 32-bit, everything's fine if we have one free register. */
26662 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
26665 /* Need a free register for vcall_offset. */
26669 /* Need a free register for GOT references. */
26670 if (flag_pic && !(*targetm.binds_local_p) (function))
26673 /* Otherwise ok. */
26677 /* Output the assembler code for a thunk function. THUNK_DECL is the
26678 declaration for the thunk function itself, FUNCTION is the decl for
26679 the target function. DELTA is an immediate constant offset to be
26680 added to THIS. If VCALL_OFFSET is nonzero, the word at
26681 *(*this + vcall_offset) should be added to THIS. */
26684 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
26685 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
26686 HOST_WIDE_INT vcall_offset, tree function)
26689 rtx this_param = x86_this_parameter (function);
26692 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
26693 pull it in now and let DELTA benefit. */
26694 if (REG_P (this_param))
26695 this_reg = this_param;
26696 else if (vcall_offset)
26698 /* Put the this parameter into %eax. */
26699 xops[0] = this_param;
26700 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
26701 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26704 this_reg = NULL_RTX;
26706 /* Adjust the this parameter by a fixed constant. */
26709 xops[0] = GEN_INT (delta);
26710 xops[1] = this_reg ? this_reg : this_param;
26713 if (!x86_64_general_operand (xops[0], DImode))
26715 tmp = gen_rtx_REG (DImode, R10_REG);
26717 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
26719 xops[1] = this_param;
26721 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
26724 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
26727 /* Adjust the this parameter by a value stored in the vtable. */
26731 tmp = gen_rtx_REG (DImode, R10_REG);
26734 int tmp_regno = CX_REG;
26735 if (lookup_attribute ("fastcall",
26736 TYPE_ATTRIBUTES (TREE_TYPE (function))))
26737 tmp_regno = AX_REG;
26738 tmp = gen_rtx_REG (SImode, tmp_regno);
26741 xops[0] = gen_rtx_MEM (Pmode, this_reg);
26743 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26745 /* Adjust the this parameter. */
26746 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
26747 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
26749 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
26750 xops[0] = GEN_INT (vcall_offset);
26752 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
26753 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
26755 xops[1] = this_reg;
26756 output_asm_insn ("add%z1\t{%0, %1|%1, %0}", xops);
26759 /* If necessary, drop THIS back to its stack slot. */
26760 if (this_reg && this_reg != this_param)
26762 xops[0] = this_reg;
26763 xops[1] = this_param;
26764 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26767 xops[0] = XEXP (DECL_RTL (function), 0);
26770 if (!flag_pic || (*targetm.binds_local_p) (function))
26771 output_asm_insn ("jmp\t%P0", xops);
26772 /* All thunks should be in the same object as their target,
26773 and thus binds_local_p should be true. */
26774 else if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
26775 gcc_unreachable ();
26778 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
26779 tmp = gen_rtx_CONST (Pmode, tmp);
26780 tmp = gen_rtx_MEM (QImode, tmp);
26782 output_asm_insn ("jmp\t%A0", xops);
26787 if (!flag_pic || (*targetm.binds_local_p) (function))
26788 output_asm_insn ("jmp\t%P0", xops);
26793 rtx sym_ref = XEXP (DECL_RTL (function), 0);
26794 tmp = (gen_rtx_SYMBOL_REF
26796 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
26797 tmp = gen_rtx_MEM (QImode, tmp);
26799 output_asm_insn ("jmp\t%0", xops);
26802 #endif /* TARGET_MACHO */
26804 tmp = gen_rtx_REG (SImode, CX_REG);
26805 output_set_got (tmp, NULL_RTX);
26808 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
26809 output_asm_insn ("jmp\t{*}%1", xops);
26815 x86_file_start (void)
26817 default_file_start ();
26819 darwin_file_start ();
26821 if (X86_FILE_START_VERSION_DIRECTIVE)
26822 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
26823 if (X86_FILE_START_FLTUSED)
26824 fputs ("\t.global\t__fltused\n", asm_out_file);
26825 if (ix86_asm_dialect == ASM_INTEL)
26826 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
26830 x86_field_alignment (tree field, int computed)
26832 enum machine_mode mode;
26833 tree type = TREE_TYPE (field);
26835 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
26837 mode = TYPE_MODE (strip_array_types (type));
26838 if (mode == DFmode || mode == DCmode
26839 || GET_MODE_CLASS (mode) == MODE_INT
26840 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
26841 return MIN (32, computed);
26845 /* Output assembler code to FILE to increment profiler label # LABELNO
26846 for profiling a function entry. */
26848 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
26852 #ifndef NO_PROFILE_COUNTERS
26853 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
26856 if (DEFAULT_ABI == SYSV_ABI && flag_pic)
26857 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
26859 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
26863 #ifndef NO_PROFILE_COUNTERS
26864 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
26865 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
26867 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
26871 #ifndef NO_PROFILE_COUNTERS
26872 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
26873 PROFILE_COUNT_REGISTER);
26875 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
26879 /* We don't have exact information about the insn sizes, but we may assume
26880 quite safely that we are informed about all 1 byte insns and memory
26881 address sizes. This is enough to eliminate unnecessary padding in
26885 min_insn_size (rtx insn)
26889 if (!INSN_P (insn) || !active_insn_p (insn))
26892 /* Discard alignments we've emit and jump instructions. */
26893 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
26894 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
26897 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
26898 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
26901 /* Important case - calls are always 5 bytes.
26902 It is common to have many calls in the row. */
26904 && symbolic_reference_mentioned_p (PATTERN (insn))
26905 && !SIBLING_CALL_P (insn))
26907 if (get_attr_length (insn) <= 1)
26910 /* For normal instructions we may rely on the sizes of addresses
26911 and the presence of symbol to require 4 bytes of encoding.
26912 This is not the case for jumps where references are PC relative. */
26913 if (!JUMP_P (insn))
26915 l = get_attr_length_address (insn);
26916 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
26925 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
26929 ix86_avoid_jump_misspredicts (void)
26931 rtx insn, start = get_insns ();
26932 int nbytes = 0, njumps = 0;
26935 /* Look for all minimal intervals of instructions containing 4 jumps.
26936 The intervals are bounded by START and INSN. NBYTES is the total
26937 size of instructions in the interval including INSN and not including
26938 START. When the NBYTES is smaller than 16 bytes, it is possible
26939 that the end of START and INSN ends up in the same 16byte page.
26941 The smallest offset in the page INSN can start is the case where START
26942 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
26943 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
26945 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
26948 nbytes += min_insn_size (insn);
26950 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
26951 INSN_UID (insn), min_insn_size (insn));
26953 && GET_CODE (PATTERN (insn)) != ADDR_VEC
26954 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
26962 start = NEXT_INSN (start);
26963 if ((JUMP_P (start)
26964 && GET_CODE (PATTERN (start)) != ADDR_VEC
26965 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
26967 njumps--, isjump = 1;
26970 nbytes -= min_insn_size (start);
26972 gcc_assert (njumps >= 0);
26974 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
26975 INSN_UID (start), INSN_UID (insn), nbytes);
26977 if (njumps == 3 && isjump && nbytes < 16)
26979 int padsize = 15 - nbytes + min_insn_size (insn);
26982 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
26983 INSN_UID (insn), padsize);
26984 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
26989 /* AMD Athlon works faster
26990 when RET is not destination of conditional jump or directly preceded
26991 by other jump instruction. We avoid the penalty by inserting NOP just
26992 before the RET instructions in such cases. */
26994 ix86_pad_returns (void)
26999 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
27001 basic_block bb = e->src;
27002 rtx ret = BB_END (bb);
27004 bool replace = false;
27006 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
27007 || optimize_bb_for_size_p (bb))
27009 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
27010 if (active_insn_p (prev) || LABEL_P (prev))
27012 if (prev && LABEL_P (prev))
27017 FOR_EACH_EDGE (e, ei, bb->preds)
27018 if (EDGE_FREQUENCY (e) && e->src->index >= 0
27019 && !(e->flags & EDGE_FALLTHRU))
27024 prev = prev_active_insn (ret);
27026 && ((JUMP_P (prev) && any_condjump_p (prev))
27029 /* Empty functions get branch mispredict even when the jump destination
27030 is not visible to us. */
27031 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
27036 emit_insn_before (gen_return_internal_long (), ret);
27042 /* Implement machine specific optimizations. We implement padding of returns
27043 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
27047 if (TARGET_PAD_RETURNS && optimize
27048 && optimize_function_for_speed_p (cfun))
27049 ix86_pad_returns ();
27050 if (TARGET_FOUR_JUMP_LIMIT && optimize
27051 && optimize_function_for_speed_p (cfun))
27052 ix86_avoid_jump_misspredicts ();
27055 /* Return nonzero when QImode register that must be represented via REX prefix
27058 x86_extended_QIreg_mentioned_p (rtx insn)
27061 extract_insn_cached (insn);
27062 for (i = 0; i < recog_data.n_operands; i++)
27063 if (REG_P (recog_data.operand[i])
27064 && REGNO (recog_data.operand[i]) > BX_REG)
27069 /* Return nonzero when P points to register encoded via REX prefix.
27070 Called via for_each_rtx. */
27072 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
27074 unsigned int regno;
27077 regno = REGNO (*p);
27078 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
27081 /* Return true when INSN mentions register that must be encoded using REX
27084 x86_extended_reg_mentioned_p (rtx insn)
27086 return for_each_rtx (INSN_P (insn) ? &PATTERN (insn) : &insn,
27087 extended_reg_mentioned_1, NULL);
27090 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
27091 optabs would emit if we didn't have TFmode patterns. */
27094 x86_emit_floatuns (rtx operands[2])
27096 rtx neglab, donelab, i0, i1, f0, in, out;
27097 enum machine_mode mode, inmode;
27099 inmode = GET_MODE (operands[1]);
27100 gcc_assert (inmode == SImode || inmode == DImode);
27103 in = force_reg (inmode, operands[1]);
27104 mode = GET_MODE (out);
27105 neglab = gen_label_rtx ();
27106 donelab = gen_label_rtx ();
27107 f0 = gen_reg_rtx (mode);
27109 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
27111 expand_float (out, in, 0);
27113 emit_jump_insn (gen_jump (donelab));
27116 emit_label (neglab);
27118 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
27120 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
27122 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
27124 expand_float (f0, i0, 0);
27126 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
27128 emit_label (donelab);
27131 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27132 with all elements equal to VAR. Return true if successful. */
27135 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
27136 rtx target, rtx val)
27138 enum machine_mode hmode, smode, wsmode, wvmode;
27153 val = force_reg (GET_MODE_INNER (mode), val);
27154 x = gen_rtx_VEC_DUPLICATE (mode, val);
27155 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27161 if (TARGET_SSE || TARGET_3DNOW_A)
27163 val = gen_lowpart (SImode, val);
27164 x = gen_rtx_TRUNCATE (HImode, val);
27165 x = gen_rtx_VEC_DUPLICATE (mode, x);
27166 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27188 /* Extend HImode to SImode using a paradoxical SUBREG. */
27189 tmp1 = gen_reg_rtx (SImode);
27190 emit_move_insn (tmp1, gen_lowpart (SImode, val));
27191 /* Insert the SImode value as low element of V4SImode vector. */
27192 tmp2 = gen_reg_rtx (V4SImode);
27193 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
27194 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
27195 CONST0_RTX (V4SImode),
27197 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
27198 /* Cast the V4SImode vector back to a V8HImode vector. */
27199 tmp1 = gen_reg_rtx (V8HImode);
27200 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
27201 /* Duplicate the low short through the whole low SImode word. */
27202 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
27203 /* Cast the V8HImode vector back to a V4SImode vector. */
27204 tmp2 = gen_reg_rtx (V4SImode);
27205 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
27206 /* Replicate the low element of the V4SImode vector. */
27207 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
27208 /* Cast the V2SImode back to V8HImode, and store in target. */
27209 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
27220 /* Extend QImode to SImode using a paradoxical SUBREG. */
27221 tmp1 = gen_reg_rtx (SImode);
27222 emit_move_insn (tmp1, gen_lowpart (SImode, val));
27223 /* Insert the SImode value as low element of V4SImode vector. */
27224 tmp2 = gen_reg_rtx (V4SImode);
27225 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
27226 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
27227 CONST0_RTX (V4SImode),
27229 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
27230 /* Cast the V4SImode vector back to a V16QImode vector. */
27231 tmp1 = gen_reg_rtx (V16QImode);
27232 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
27233 /* Duplicate the low byte through the whole low SImode word. */
27234 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
27235 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
27236 /* Cast the V16QImode vector back to a V4SImode vector. */
27237 tmp2 = gen_reg_rtx (V4SImode);
27238 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
27239 /* Replicate the low element of the V4SImode vector. */
27240 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
27241 /* Cast the V2SImode back to V16QImode, and store in target. */
27242 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
27250 /* Replicate the value once into the next wider mode and recurse. */
27251 val = convert_modes (wsmode, smode, val, true);
27252 x = expand_simple_binop (wsmode, ASHIFT, val,
27253 GEN_INT (GET_MODE_BITSIZE (smode)),
27254 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27255 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
27257 x = gen_reg_rtx (wvmode);
27258 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
27259 gcc_unreachable ();
27260 emit_move_insn (target, gen_lowpart (mode, x));
27283 rtx tmp = gen_reg_rtx (hmode);
27284 ix86_expand_vector_init_duplicate (mmx_ok, hmode, tmp, val);
27285 emit_insn (gen_rtx_SET (VOIDmode, target,
27286 gen_rtx_VEC_CONCAT (mode, tmp, tmp)));
27295 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27296 whose ONE_VAR element is VAR, and other elements are zero. Return true
27300 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
27301 rtx target, rtx var, int one_var)
27303 enum machine_mode vsimode;
27306 bool use_vector_set = false;
27311 /* For SSE4.1, we normally use vector set. But if the second
27312 element is zero and inter-unit moves are OK, we use movq
27314 use_vector_set = (TARGET_64BIT
27316 && !(TARGET_INTER_UNIT_MOVES
27322 use_vector_set = TARGET_SSE4_1;
27325 use_vector_set = TARGET_SSE2;
27328 use_vector_set = TARGET_SSE || TARGET_3DNOW_A;
27335 use_vector_set = TARGET_AVX;
27338 /* Use ix86_expand_vector_set in 64bit mode only. */
27339 use_vector_set = TARGET_AVX && TARGET_64BIT;
27345 if (use_vector_set)
27347 emit_insn (gen_rtx_SET (VOIDmode, target, CONST0_RTX (mode)));
27348 var = force_reg (GET_MODE_INNER (mode), var);
27349 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27365 var = force_reg (GET_MODE_INNER (mode), var);
27366 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
27367 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27372 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
27373 new_target = gen_reg_rtx (mode);
27375 new_target = target;
27376 var = force_reg (GET_MODE_INNER (mode), var);
27377 x = gen_rtx_VEC_DUPLICATE (mode, var);
27378 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
27379 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
27382 /* We need to shuffle the value to the correct position, so
27383 create a new pseudo to store the intermediate result. */
27385 /* With SSE2, we can use the integer shuffle insns. */
27386 if (mode != V4SFmode && TARGET_SSE2)
27388 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
27390 GEN_INT (one_var == 1 ? 0 : 1),
27391 GEN_INT (one_var == 2 ? 0 : 1),
27392 GEN_INT (one_var == 3 ? 0 : 1)));
27393 if (target != new_target)
27394 emit_move_insn (target, new_target);
27398 /* Otherwise convert the intermediate result to V4SFmode and
27399 use the SSE1 shuffle instructions. */
27400 if (mode != V4SFmode)
27402 tmp = gen_reg_rtx (V4SFmode);
27403 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
27408 emit_insn (gen_sse_shufps_v4sf (tmp, tmp, tmp,
27410 GEN_INT (one_var == 1 ? 0 : 1),
27411 GEN_INT (one_var == 2 ? 0+4 : 1+4),
27412 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
27414 if (mode != V4SFmode)
27415 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
27416 else if (tmp != target)
27417 emit_move_insn (target, tmp);
27419 else if (target != new_target)
27420 emit_move_insn (target, new_target);
27425 vsimode = V4SImode;
27431 vsimode = V2SImode;
27437 /* Zero extend the variable element to SImode and recurse. */
27438 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
27440 x = gen_reg_rtx (vsimode);
27441 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
27443 gcc_unreachable ();
27445 emit_move_insn (target, gen_lowpart (mode, x));
27453 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27454 consisting of the values in VALS. It is known that all elements
27455 except ONE_VAR are constants. Return true if successful. */
27458 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
27459 rtx target, rtx vals, int one_var)
27461 rtx var = XVECEXP (vals, 0, one_var);
27462 enum machine_mode wmode;
27465 const_vec = copy_rtx (vals);
27466 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
27467 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
27475 /* For the two element vectors, it's just as easy to use
27476 the general case. */
27480 /* Use ix86_expand_vector_set in 64bit mode only. */
27503 /* There's no way to set one QImode entry easily. Combine
27504 the variable value with its adjacent constant value, and
27505 promote to an HImode set. */
27506 x = XVECEXP (vals, 0, one_var ^ 1);
27509 var = convert_modes (HImode, QImode, var, true);
27510 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
27511 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27512 x = GEN_INT (INTVAL (x) & 0xff);
27516 var = convert_modes (HImode, QImode, var, true);
27517 x = gen_int_mode (INTVAL (x) << 8, HImode);
27519 if (x != const0_rtx)
27520 var = expand_simple_binop (HImode, IOR, var, x, var,
27521 1, OPTAB_LIB_WIDEN);
27523 x = gen_reg_rtx (wmode);
27524 emit_move_insn (x, gen_lowpart (wmode, const_vec));
27525 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
27527 emit_move_insn (target, gen_lowpart (mode, x));
27534 emit_move_insn (target, const_vec);
27535 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27539 /* A subroutine of ix86_expand_vector_init_general. Use vector
27540 concatenate to handle the most general case: all values variable,
27541 and none identical. */
27544 ix86_expand_vector_init_concat (enum machine_mode mode,
27545 rtx target, rtx *ops, int n)
27547 enum machine_mode cmode, hmode = VOIDmode;
27548 rtx first[8], second[4];
27588 gcc_unreachable ();
27591 if (!register_operand (ops[1], cmode))
27592 ops[1] = force_reg (cmode, ops[1]);
27593 if (!register_operand (ops[0], cmode))
27594 ops[0] = force_reg (cmode, ops[0]);
27595 emit_insn (gen_rtx_SET (VOIDmode, target,
27596 gen_rtx_VEC_CONCAT (mode, ops[0],
27616 gcc_unreachable ();
27632 gcc_unreachable ();
27637 /* FIXME: We process inputs backward to help RA. PR 36222. */
27640 for (; i > 0; i -= 2, j--)
27642 first[j] = gen_reg_rtx (cmode);
27643 v = gen_rtvec (2, ops[i - 1], ops[i]);
27644 ix86_expand_vector_init (false, first[j],
27645 gen_rtx_PARALLEL (cmode, v));
27651 gcc_assert (hmode != VOIDmode);
27652 for (i = j = 0; i < n; i += 2, j++)
27654 second[j] = gen_reg_rtx (hmode);
27655 ix86_expand_vector_init_concat (hmode, second [j],
27659 ix86_expand_vector_init_concat (mode, target, second, n);
27662 ix86_expand_vector_init_concat (mode, target, first, n);
27666 gcc_unreachable ();
27670 /* A subroutine of ix86_expand_vector_init_general. Use vector
27671 interleave to handle the most general case: all values variable,
27672 and none identical. */
27675 ix86_expand_vector_init_interleave (enum machine_mode mode,
27676 rtx target, rtx *ops, int n)
27678 enum machine_mode first_imode, second_imode, third_imode, inner_mode;
27681 rtx (*gen_load_even) (rtx, rtx, rtx);
27682 rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
27683 rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
27688 gen_load_even = gen_vec_setv8hi;
27689 gen_interleave_first_low = gen_vec_interleave_lowv4si;
27690 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27691 inner_mode = HImode;
27692 first_imode = V4SImode;
27693 second_imode = V2DImode;
27694 third_imode = VOIDmode;
27697 gen_load_even = gen_vec_setv16qi;
27698 gen_interleave_first_low = gen_vec_interleave_lowv8hi;
27699 gen_interleave_second_low = gen_vec_interleave_lowv4si;
27700 inner_mode = QImode;
27701 first_imode = V8HImode;
27702 second_imode = V4SImode;
27703 third_imode = V2DImode;
27706 gcc_unreachable ();
27709 for (i = 0; i < n; i++)
27711 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
27712 op0 = gen_reg_rtx (SImode);
27713 emit_move_insn (op0, gen_lowpart (SImode, ops [i + i]));
27715 /* Insert the SImode value as low element of V4SImode vector. */
27716 op1 = gen_reg_rtx (V4SImode);
27717 op0 = gen_rtx_VEC_MERGE (V4SImode,
27718 gen_rtx_VEC_DUPLICATE (V4SImode,
27720 CONST0_RTX (V4SImode),
27722 emit_insn (gen_rtx_SET (VOIDmode, op1, op0));
27724 /* Cast the V4SImode vector back to a vector in orignal mode. */
27725 op0 = gen_reg_rtx (mode);
27726 emit_move_insn (op0, gen_lowpart (mode, op1));
27728 /* Load even elements into the second positon. */
27729 emit_insn ((*gen_load_even) (op0,
27730 force_reg (inner_mode,
27734 /* Cast vector to FIRST_IMODE vector. */
27735 ops[i] = gen_reg_rtx (first_imode);
27736 emit_move_insn (ops[i], gen_lowpart (first_imode, op0));
27739 /* Interleave low FIRST_IMODE vectors. */
27740 for (i = j = 0; i < n; i += 2, j++)
27742 op0 = gen_reg_rtx (first_imode);
27743 emit_insn ((*gen_interleave_first_low) (op0, ops[i], ops[i + 1]));
27745 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
27746 ops[j] = gen_reg_rtx (second_imode);
27747 emit_move_insn (ops[j], gen_lowpart (second_imode, op0));
27750 /* Interleave low SECOND_IMODE vectors. */
27751 switch (second_imode)
27754 for (i = j = 0; i < n / 2; i += 2, j++)
27756 op0 = gen_reg_rtx (second_imode);
27757 emit_insn ((*gen_interleave_second_low) (op0, ops[i],
27760 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
27762 ops[j] = gen_reg_rtx (third_imode);
27763 emit_move_insn (ops[j], gen_lowpart (third_imode, op0));
27765 second_imode = V2DImode;
27766 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27770 op0 = gen_reg_rtx (second_imode);
27771 emit_insn ((*gen_interleave_second_low) (op0, ops[0],
27774 /* Cast the SECOND_IMODE vector back to a vector on original
27776 emit_insn (gen_rtx_SET (VOIDmode, target,
27777 gen_lowpart (mode, op0)));
27781 gcc_unreachable ();
27785 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
27786 all values variable, and none identical. */
27789 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
27790 rtx target, rtx vals)
27792 rtx ops[32], op0, op1;
27793 enum machine_mode half_mode = VOIDmode;
27800 if (!mmx_ok && !TARGET_SSE)
27812 n = GET_MODE_NUNITS (mode);
27813 for (i = 0; i < n; i++)
27814 ops[i] = XVECEXP (vals, 0, i);
27815 ix86_expand_vector_init_concat (mode, target, ops, n);
27819 half_mode = V16QImode;
27823 half_mode = V8HImode;
27827 n = GET_MODE_NUNITS (mode);
27828 for (i = 0; i < n; i++)
27829 ops[i] = XVECEXP (vals, 0, i);
27830 op0 = gen_reg_rtx (half_mode);
27831 op1 = gen_reg_rtx (half_mode);
27832 ix86_expand_vector_init_interleave (half_mode, op0, ops,
27834 ix86_expand_vector_init_interleave (half_mode, op1,
27835 &ops [n >> 1], n >> 2);
27836 emit_insn (gen_rtx_SET (VOIDmode, target,
27837 gen_rtx_VEC_CONCAT (mode, op0, op1)));
27841 if (!TARGET_SSE4_1)
27849 /* Don't use ix86_expand_vector_init_interleave if we can't
27850 move from GPR to SSE register directly. */
27851 if (!TARGET_INTER_UNIT_MOVES)
27854 n = GET_MODE_NUNITS (mode);
27855 for (i = 0; i < n; i++)
27856 ops[i] = XVECEXP (vals, 0, i);
27857 ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
27865 gcc_unreachable ();
27869 int i, j, n_elts, n_words, n_elt_per_word;
27870 enum machine_mode inner_mode;
27871 rtx words[4], shift;
27873 inner_mode = GET_MODE_INNER (mode);
27874 n_elts = GET_MODE_NUNITS (mode);
27875 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
27876 n_elt_per_word = n_elts / n_words;
27877 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
27879 for (i = 0; i < n_words; ++i)
27881 rtx word = NULL_RTX;
27883 for (j = 0; j < n_elt_per_word; ++j)
27885 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
27886 elt = convert_modes (word_mode, inner_mode, elt, true);
27892 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
27893 word, 1, OPTAB_LIB_WIDEN);
27894 word = expand_simple_binop (word_mode, IOR, word, elt,
27895 word, 1, OPTAB_LIB_WIDEN);
27903 emit_move_insn (target, gen_lowpart (mode, words[0]));
27904 else if (n_words == 2)
27906 rtx tmp = gen_reg_rtx (mode);
27907 emit_clobber (tmp);
27908 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
27909 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
27910 emit_move_insn (target, tmp);
27912 else if (n_words == 4)
27914 rtx tmp = gen_reg_rtx (V4SImode);
27915 gcc_assert (word_mode == SImode);
27916 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
27917 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
27918 emit_move_insn (target, gen_lowpart (mode, tmp));
27921 gcc_unreachable ();
27925 /* Initialize vector TARGET via VALS. Suppress the use of MMX
27926 instructions unless MMX_OK is true. */
27929 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
27931 enum machine_mode mode = GET_MODE (target);
27932 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27933 int n_elts = GET_MODE_NUNITS (mode);
27934 int n_var = 0, one_var = -1;
27935 bool all_same = true, all_const_zero = true;
27939 for (i = 0; i < n_elts; ++i)
27941 x = XVECEXP (vals, 0, i);
27942 if (!(CONST_INT_P (x)
27943 || GET_CODE (x) == CONST_DOUBLE
27944 || GET_CODE (x) == CONST_FIXED))
27945 n_var++, one_var = i;
27946 else if (x != CONST0_RTX (inner_mode))
27947 all_const_zero = false;
27948 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
27952 /* Constants are best loaded from the constant pool. */
27955 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
27959 /* If all values are identical, broadcast the value. */
27961 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
27962 XVECEXP (vals, 0, 0)))
27965 /* Values where only one field is non-constant are best loaded from
27966 the pool and overwritten via move later. */
27970 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
27971 XVECEXP (vals, 0, one_var),
27975 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
27979 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
27983 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
27985 enum machine_mode mode = GET_MODE (target);
27986 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27987 enum machine_mode half_mode;
27988 bool use_vec_merge = false;
27990 static rtx (*gen_extract[6][2]) (rtx, rtx)
27992 { gen_vec_extract_lo_v32qi, gen_vec_extract_hi_v32qi },
27993 { gen_vec_extract_lo_v16hi, gen_vec_extract_hi_v16hi },
27994 { gen_vec_extract_lo_v8si, gen_vec_extract_hi_v8si },
27995 { gen_vec_extract_lo_v4di, gen_vec_extract_hi_v4di },
27996 { gen_vec_extract_lo_v8sf, gen_vec_extract_hi_v8sf },
27997 { gen_vec_extract_lo_v4df, gen_vec_extract_hi_v4df }
27999 static rtx (*gen_insert[6][2]) (rtx, rtx, rtx)
28001 { gen_vec_set_lo_v32qi, gen_vec_set_hi_v32qi },
28002 { gen_vec_set_lo_v16hi, gen_vec_set_hi_v16hi },
28003 { gen_vec_set_lo_v8si, gen_vec_set_hi_v8si },
28004 { gen_vec_set_lo_v4di, gen_vec_set_hi_v4di },
28005 { gen_vec_set_lo_v8sf, gen_vec_set_hi_v8sf },
28006 { gen_vec_set_lo_v4df, gen_vec_set_hi_v4df }
28016 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
28017 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
28019 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
28021 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
28022 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28028 use_vec_merge = TARGET_SSE4_1;
28036 /* For the two element vectors, we implement a VEC_CONCAT with
28037 the extraction of the other element. */
28039 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
28040 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
28043 op0 = val, op1 = tmp;
28045 op0 = tmp, op1 = val;
28047 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
28048 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28053 use_vec_merge = TARGET_SSE4_1;
28060 use_vec_merge = true;
28064 /* tmp = target = A B C D */
28065 tmp = copy_to_reg (target);
28066 /* target = A A B B */
28067 emit_insn (gen_sse_unpcklps (target, target, target));
28068 /* target = X A B B */
28069 ix86_expand_vector_set (false, target, val, 0);
28070 /* target = A X C D */
28071 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28072 GEN_INT (1), GEN_INT (0),
28073 GEN_INT (2+4), GEN_INT (3+4)));
28077 /* tmp = target = A B C D */
28078 tmp = copy_to_reg (target);
28079 /* tmp = X B C D */
28080 ix86_expand_vector_set (false, tmp, val, 0);
28081 /* target = A B X D */
28082 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28083 GEN_INT (0), GEN_INT (1),
28084 GEN_INT (0+4), GEN_INT (3+4)));
28088 /* tmp = target = A B C D */
28089 tmp = copy_to_reg (target);
28090 /* tmp = X B C D */
28091 ix86_expand_vector_set (false, tmp, val, 0);
28092 /* target = A B X D */
28093 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28094 GEN_INT (0), GEN_INT (1),
28095 GEN_INT (2+4), GEN_INT (0+4)));
28099 gcc_unreachable ();
28104 use_vec_merge = TARGET_SSE4_1;
28108 /* Element 0 handled by vec_merge below. */
28111 use_vec_merge = true;
28117 /* With SSE2, use integer shuffles to swap element 0 and ELT,
28118 store into element 0, then shuffle them back. */
28122 order[0] = GEN_INT (elt);
28123 order[1] = const1_rtx;
28124 order[2] = const2_rtx;
28125 order[3] = GEN_INT (3);
28126 order[elt] = const0_rtx;
28128 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
28129 order[1], order[2], order[3]));
28131 ix86_expand_vector_set (false, target, val, 0);
28133 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
28134 order[1], order[2], order[3]));
28138 /* For SSE1, we have to reuse the V4SF code. */
28139 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
28140 gen_lowpart (SFmode, val), elt);
28145 use_vec_merge = TARGET_SSE2;
28148 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
28152 use_vec_merge = TARGET_SSE4_1;
28159 half_mode = V16QImode;
28165 half_mode = V8HImode;
28171 half_mode = V4SImode;
28177 half_mode = V2DImode;
28183 half_mode = V4SFmode;
28189 half_mode = V2DFmode;
28195 /* Compute offset. */
28199 gcc_assert (i <= 1);
28201 /* Extract the half. */
28202 tmp = gen_reg_rtx (half_mode);
28203 emit_insn ((*gen_extract[j][i]) (tmp, target));
28205 /* Put val in tmp at elt. */
28206 ix86_expand_vector_set (false, tmp, val, elt);
28209 emit_insn ((*gen_insert[j][i]) (target, target, tmp));
28218 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
28219 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
28220 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28224 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
28226 emit_move_insn (mem, target);
28228 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
28229 emit_move_insn (tmp, val);
28231 emit_move_insn (target, mem);
28236 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
28238 enum machine_mode mode = GET_MODE (vec);
28239 enum machine_mode inner_mode = GET_MODE_INNER (mode);
28240 bool use_vec_extr = false;
28253 use_vec_extr = true;
28257 use_vec_extr = TARGET_SSE4_1;
28269 tmp = gen_reg_rtx (mode);
28270 emit_insn (gen_sse_shufps_v4sf (tmp, vec, vec,
28271 GEN_INT (elt), GEN_INT (elt),
28272 GEN_INT (elt+4), GEN_INT (elt+4)));
28276 tmp = gen_reg_rtx (mode);
28277 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
28281 gcc_unreachable ();
28284 use_vec_extr = true;
28289 use_vec_extr = TARGET_SSE4_1;
28303 tmp = gen_reg_rtx (mode);
28304 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
28305 GEN_INT (elt), GEN_INT (elt),
28306 GEN_INT (elt), GEN_INT (elt)));
28310 tmp = gen_reg_rtx (mode);
28311 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
28315 gcc_unreachable ();
28318 use_vec_extr = true;
28323 /* For SSE1, we have to reuse the V4SF code. */
28324 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
28325 gen_lowpart (V4SFmode, vec), elt);
28331 use_vec_extr = TARGET_SSE2;
28334 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
28338 use_vec_extr = TARGET_SSE4_1;
28342 /* ??? Could extract the appropriate HImode element and shift. */
28349 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
28350 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
28352 /* Let the rtl optimizers know about the zero extension performed. */
28353 if (inner_mode == QImode || inner_mode == HImode)
28355 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
28356 target = gen_lowpart (SImode, target);
28359 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28363 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
28365 emit_move_insn (mem, vec);
28367 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
28368 emit_move_insn (target, tmp);
28372 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
28373 pattern to reduce; DEST is the destination; IN is the input vector. */
28376 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
28378 rtx tmp1, tmp2, tmp3;
28380 tmp1 = gen_reg_rtx (V4SFmode);
28381 tmp2 = gen_reg_rtx (V4SFmode);
28382 tmp3 = gen_reg_rtx (V4SFmode);
28384 emit_insn (gen_sse_movhlps (tmp1, in, in));
28385 emit_insn (fn (tmp2, tmp1, in));
28387 emit_insn (gen_sse_shufps_v4sf (tmp3, tmp2, tmp2,
28388 GEN_INT (1), GEN_INT (1),
28389 GEN_INT (1+4), GEN_INT (1+4)));
28390 emit_insn (fn (dest, tmp2, tmp3));
28393 /* Target hook for scalar_mode_supported_p. */
28395 ix86_scalar_mode_supported_p (enum machine_mode mode)
28397 if (DECIMAL_FLOAT_MODE_P (mode))
28399 else if (mode == TFmode)
28402 return default_scalar_mode_supported_p (mode);
28405 /* Implements target hook vector_mode_supported_p. */
28407 ix86_vector_mode_supported_p (enum machine_mode mode)
28409 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
28411 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
28413 if (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
28415 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
28417 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
28422 /* Target hook for c_mode_for_suffix. */
28423 static enum machine_mode
28424 ix86_c_mode_for_suffix (char suffix)
28434 /* Worker function for TARGET_MD_ASM_CLOBBERS.
28436 We do this in the new i386 backend to maintain source compatibility
28437 with the old cc0-based compiler. */
28440 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
28441 tree inputs ATTRIBUTE_UNUSED,
28444 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
28446 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
28451 /* Implements target vector targetm.asm.encode_section_info. This
28452 is not used by netware. */
28454 static void ATTRIBUTE_UNUSED
28455 ix86_encode_section_info (tree decl, rtx rtl, int first)
28457 default_encode_section_info (decl, rtl, first);
28459 if (TREE_CODE (decl) == VAR_DECL
28460 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
28461 && ix86_in_large_data_p (decl))
28462 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
28465 /* Worker function for REVERSE_CONDITION. */
28468 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
28470 return (mode != CCFPmode && mode != CCFPUmode
28471 ? reverse_condition (code)
28472 : reverse_condition_maybe_unordered (code));
28475 /* Output code to perform an x87 FP register move, from OPERANDS[1]
28479 output_387_reg_move (rtx insn, rtx *operands)
28481 if (REG_P (operands[0]))
28483 if (REG_P (operands[1])
28484 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28486 if (REGNO (operands[0]) == FIRST_STACK_REG)
28487 return output_387_ffreep (operands, 0);
28488 return "fstp\t%y0";
28490 if (STACK_TOP_P (operands[0]))
28491 return "fld%z1\t%y1";
28494 else if (MEM_P (operands[0]))
28496 gcc_assert (REG_P (operands[1]));
28497 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28498 return "fstp%z0\t%y0";
28501 /* There is no non-popping store to memory for XFmode.
28502 So if we need one, follow the store with a load. */
28503 if (GET_MODE (operands[0]) == XFmode)
28504 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
28506 return "fst%z0\t%y0";
28513 /* Output code to perform a conditional jump to LABEL, if C2 flag in
28514 FP status register is set. */
28517 ix86_emit_fp_unordered_jump (rtx label)
28519 rtx reg = gen_reg_rtx (HImode);
28522 emit_insn (gen_x86_fnstsw_1 (reg));
28524 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ()))
28526 emit_insn (gen_x86_sahf_1 (reg));
28528 temp = gen_rtx_REG (CCmode, FLAGS_REG);
28529 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
28533 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
28535 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
28536 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
28539 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
28540 gen_rtx_LABEL_REF (VOIDmode, label),
28542 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
28544 emit_jump_insn (temp);
28545 predict_jump (REG_BR_PROB_BASE * 10 / 100);
28548 /* Output code to perform a log1p XFmode calculation. */
28550 void ix86_emit_i387_log1p (rtx op0, rtx op1)
28552 rtx label1 = gen_label_rtx ();
28553 rtx label2 = gen_label_rtx ();
28555 rtx tmp = gen_reg_rtx (XFmode);
28556 rtx tmp2 = gen_reg_rtx (XFmode);
28558 emit_insn (gen_absxf2 (tmp, op1));
28559 emit_insn (gen_cmpxf (tmp,
28560 CONST_DOUBLE_FROM_REAL_VALUE (
28561 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
28563 emit_jump_insn (gen_bge (label1));
28565 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28566 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
28567 emit_jump (label2);
28569 emit_label (label1);
28570 emit_move_insn (tmp, CONST1_RTX (XFmode));
28571 emit_insn (gen_addxf3 (tmp, op1, tmp));
28572 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28573 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
28575 emit_label (label2);
28578 /* Output code to perform a Newton-Rhapson approximation of a single precision
28579 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
28581 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
28583 rtx x0, x1, e0, e1, two;
28585 x0 = gen_reg_rtx (mode);
28586 e0 = gen_reg_rtx (mode);
28587 e1 = gen_reg_rtx (mode);
28588 x1 = gen_reg_rtx (mode);
28590 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
28592 if (VECTOR_MODE_P (mode))
28593 two = ix86_build_const_vector (SFmode, true, two);
28595 two = force_reg (mode, two);
28597 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
28599 /* x0 = rcp(b) estimate */
28600 emit_insn (gen_rtx_SET (VOIDmode, x0,
28601 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
28604 emit_insn (gen_rtx_SET (VOIDmode, e0,
28605 gen_rtx_MULT (mode, x0, b)));
28607 emit_insn (gen_rtx_SET (VOIDmode, e1,
28608 gen_rtx_MINUS (mode, two, e0)));
28610 emit_insn (gen_rtx_SET (VOIDmode, x1,
28611 gen_rtx_MULT (mode, x0, e1)));
28613 emit_insn (gen_rtx_SET (VOIDmode, res,
28614 gen_rtx_MULT (mode, a, x1)));
28617 /* Output code to perform a Newton-Rhapson approximation of a
28618 single precision floating point [reciprocal] square root. */
28620 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
28623 rtx x0, e0, e1, e2, e3, mthree, mhalf;
28626 x0 = gen_reg_rtx (mode);
28627 e0 = gen_reg_rtx (mode);
28628 e1 = gen_reg_rtx (mode);
28629 e2 = gen_reg_rtx (mode);
28630 e3 = gen_reg_rtx (mode);
28632 real_from_integer (&r, VOIDmode, -3, -1, 0);
28633 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28635 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
28636 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28638 if (VECTOR_MODE_P (mode))
28640 mthree = ix86_build_const_vector (SFmode, true, mthree);
28641 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
28644 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
28645 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
28647 /* x0 = rsqrt(a) estimate */
28648 emit_insn (gen_rtx_SET (VOIDmode, x0,
28649 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
28652 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
28657 zero = gen_reg_rtx (mode);
28658 mask = gen_reg_rtx (mode);
28660 zero = force_reg (mode, CONST0_RTX(mode));
28661 emit_insn (gen_rtx_SET (VOIDmode, mask,
28662 gen_rtx_NE (mode, zero, a)));
28664 emit_insn (gen_rtx_SET (VOIDmode, x0,
28665 gen_rtx_AND (mode, x0, mask)));
28669 emit_insn (gen_rtx_SET (VOIDmode, e0,
28670 gen_rtx_MULT (mode, x0, a)));
28672 emit_insn (gen_rtx_SET (VOIDmode, e1,
28673 gen_rtx_MULT (mode, e0, x0)));
28676 mthree = force_reg (mode, mthree);
28677 emit_insn (gen_rtx_SET (VOIDmode, e2,
28678 gen_rtx_PLUS (mode, e1, mthree)));
28680 mhalf = force_reg (mode, mhalf);
28682 /* e3 = -.5 * x0 */
28683 emit_insn (gen_rtx_SET (VOIDmode, e3,
28684 gen_rtx_MULT (mode, x0, mhalf)));
28686 /* e3 = -.5 * e0 */
28687 emit_insn (gen_rtx_SET (VOIDmode, e3,
28688 gen_rtx_MULT (mode, e0, mhalf)));
28689 /* ret = e2 * e3 */
28690 emit_insn (gen_rtx_SET (VOIDmode, res,
28691 gen_rtx_MULT (mode, e2, e3)));
28694 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
28696 static void ATTRIBUTE_UNUSED
28697 i386_solaris_elf_named_section (const char *name, unsigned int flags,
28700 /* With Binutils 2.15, the "@unwind" marker must be specified on
28701 every occurrence of the ".eh_frame" section, not just the first
28704 && strcmp (name, ".eh_frame") == 0)
28706 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
28707 flags & SECTION_WRITE ? "aw" : "a");
28710 default_elf_asm_named_section (name, flags, decl);
28713 /* Return the mangling of TYPE if it is an extended fundamental type. */
28715 static const char *
28716 ix86_mangle_type (const_tree type)
28718 type = TYPE_MAIN_VARIANT (type);
28720 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
28721 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
28724 switch (TYPE_MODE (type))
28727 /* __float128 is "g". */
28730 /* "long double" or __float80 is "e". */
28737 /* For 32-bit code we can save PIC register setup by using
28738 __stack_chk_fail_local hidden function instead of calling
28739 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
28740 register, so it is better to call __stack_chk_fail directly. */
28743 ix86_stack_protect_fail (void)
28745 return TARGET_64BIT
28746 ? default_external_stack_protect_fail ()
28747 : default_hidden_stack_protect_fail ();
28750 /* Select a format to encode pointers in exception handling data. CODE
28751 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
28752 true if the symbol may be affected by dynamic relocations.
28754 ??? All x86 object file formats are capable of representing this.
28755 After all, the relocation needed is the same as for the call insn.
28756 Whether or not a particular assembler allows us to enter such, I
28757 guess we'll have to see. */
28759 asm_preferred_eh_data_format (int code, int global)
28763 int type = DW_EH_PE_sdata8;
28765 || ix86_cmodel == CM_SMALL_PIC
28766 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
28767 type = DW_EH_PE_sdata4;
28768 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
28770 if (ix86_cmodel == CM_SMALL
28771 || (ix86_cmodel == CM_MEDIUM && code))
28772 return DW_EH_PE_udata4;
28773 return DW_EH_PE_absptr;
28776 /* Expand copysign from SIGN to the positive value ABS_VALUE
28777 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
28780 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
28782 enum machine_mode mode = GET_MODE (sign);
28783 rtx sgn = gen_reg_rtx (mode);
28784 if (mask == NULL_RTX)
28786 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
28787 if (!VECTOR_MODE_P (mode))
28789 /* We need to generate a scalar mode mask in this case. */
28790 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28791 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28792 mask = gen_reg_rtx (mode);
28793 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28797 mask = gen_rtx_NOT (mode, mask);
28798 emit_insn (gen_rtx_SET (VOIDmode, sgn,
28799 gen_rtx_AND (mode, mask, sign)));
28800 emit_insn (gen_rtx_SET (VOIDmode, result,
28801 gen_rtx_IOR (mode, abs_value, sgn)));
28804 /* Expand fabs (OP0) and return a new rtx that holds the result. The
28805 mask for masking out the sign-bit is stored in *SMASK, if that is
28808 ix86_expand_sse_fabs (rtx op0, rtx *smask)
28810 enum machine_mode mode = GET_MODE (op0);
28813 xa = gen_reg_rtx (mode);
28814 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
28815 if (!VECTOR_MODE_P (mode))
28817 /* We need to generate a scalar mode mask in this case. */
28818 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28819 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28820 mask = gen_reg_rtx (mode);
28821 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28823 emit_insn (gen_rtx_SET (VOIDmode, xa,
28824 gen_rtx_AND (mode, op0, mask)));
28832 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
28833 swapping the operands if SWAP_OPERANDS is true. The expanded
28834 code is a forward jump to a newly created label in case the
28835 comparison is true. The generated label rtx is returned. */
28837 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
28838 bool swap_operands)
28849 label = gen_label_rtx ();
28850 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
28851 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28852 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
28853 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
28854 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
28855 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
28856 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
28857 JUMP_LABEL (tmp) = label;
28862 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
28863 using comparison code CODE. Operands are swapped for the comparison if
28864 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
28866 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
28867 bool swap_operands)
28869 enum machine_mode mode = GET_MODE (op0);
28870 rtx mask = gen_reg_rtx (mode);
28879 if (mode == DFmode)
28880 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
28881 gen_rtx_fmt_ee (code, mode, op0, op1)));
28883 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
28884 gen_rtx_fmt_ee (code, mode, op0, op1)));
28889 /* Generate and return a rtx of mode MODE for 2**n where n is the number
28890 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
28892 ix86_gen_TWO52 (enum machine_mode mode)
28894 REAL_VALUE_TYPE TWO52r;
28897 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
28898 TWO52 = const_double_from_real_value (TWO52r, mode);
28899 TWO52 = force_reg (mode, TWO52);
28904 /* Expand SSE sequence for computing lround from OP1 storing
28907 ix86_expand_lround (rtx op0, rtx op1)
28909 /* C code for the stuff we're doing below:
28910 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
28913 enum machine_mode mode = GET_MODE (op1);
28914 const struct real_format *fmt;
28915 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
28918 /* load nextafter (0.5, 0.0) */
28919 fmt = REAL_MODE_FORMAT (mode);
28920 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
28921 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
28923 /* adj = copysign (0.5, op1) */
28924 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
28925 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
28927 /* adj = op1 + adj */
28928 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
28930 /* op0 = (imode)adj */
28931 expand_fix (op0, adj, 0);
28934 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
28937 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
28939 /* C code for the stuff we're doing below (for do_floor):
28941 xi -= (double)xi > op1 ? 1 : 0;
28944 enum machine_mode fmode = GET_MODE (op1);
28945 enum machine_mode imode = GET_MODE (op0);
28946 rtx ireg, freg, label, tmp;
28948 /* reg = (long)op1 */
28949 ireg = gen_reg_rtx (imode);
28950 expand_fix (ireg, op1, 0);
28952 /* freg = (double)reg */
28953 freg = gen_reg_rtx (fmode);
28954 expand_float (freg, ireg, 0);
28956 /* ireg = (freg > op1) ? ireg - 1 : ireg */
28957 label = ix86_expand_sse_compare_and_jump (UNLE,
28958 freg, op1, !do_floor);
28959 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
28960 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
28961 emit_move_insn (ireg, tmp);
28963 emit_label (label);
28964 LABEL_NUSES (label) = 1;
28966 emit_move_insn (op0, ireg);
28969 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
28970 result in OPERAND0. */
28972 ix86_expand_rint (rtx operand0, rtx operand1)
28974 /* C code for the stuff we're doing below:
28975 xa = fabs (operand1);
28976 if (!isless (xa, 2**52))
28978 xa = xa + 2**52 - 2**52;
28979 return copysign (xa, operand1);
28981 enum machine_mode mode = GET_MODE (operand0);
28982 rtx res, xa, label, TWO52, mask;
28984 res = gen_reg_rtx (mode);
28985 emit_move_insn (res, operand1);
28987 /* xa = abs (operand1) */
28988 xa = ix86_expand_sse_fabs (res, &mask);
28990 /* if (!isless (xa, TWO52)) goto label; */
28991 TWO52 = ix86_gen_TWO52 (mode);
28992 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28994 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28995 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
28997 ix86_sse_copysign_to_positive (res, xa, res, mask);
28999 emit_label (label);
29000 LABEL_NUSES (label) = 1;
29002 emit_move_insn (operand0, res);
29005 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
29008 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
29010 /* C code for the stuff we expand below.
29011 double xa = fabs (x), x2;
29012 if (!isless (xa, TWO52))
29014 xa = xa + TWO52 - TWO52;
29015 x2 = copysign (xa, x);
29024 enum machine_mode mode = GET_MODE (operand0);
29025 rtx xa, TWO52, tmp, label, one, res, mask;
29027 TWO52 = ix86_gen_TWO52 (mode);
29029 /* Temporary for holding the result, initialized to the input
29030 operand to ease control flow. */
29031 res = gen_reg_rtx (mode);
29032 emit_move_insn (res, operand1);
29034 /* xa = abs (operand1) */
29035 xa = ix86_expand_sse_fabs (res, &mask);
29037 /* if (!isless (xa, TWO52)) goto label; */
29038 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29040 /* xa = xa + TWO52 - TWO52; */
29041 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29042 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
29044 /* xa = copysign (xa, operand1) */
29045 ix86_sse_copysign_to_positive (xa, xa, res, mask);
29047 /* generate 1.0 or -1.0 */
29048 one = force_reg (mode,
29049 const_double_from_real_value (do_floor
29050 ? dconst1 : dconstm1, mode));
29052 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
29053 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
29054 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29055 gen_rtx_AND (mode, one, tmp)));
29056 /* We always need to subtract here to preserve signed zero. */
29057 tmp = expand_simple_binop (mode, MINUS,
29058 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29059 emit_move_insn (res, tmp);
29061 emit_label (label);
29062 LABEL_NUSES (label) = 1;
29064 emit_move_insn (operand0, res);
29067 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
29070 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
29072 /* C code for the stuff we expand below.
29073 double xa = fabs (x), x2;
29074 if (!isless (xa, TWO52))
29076 x2 = (double)(long)x;
29083 if (HONOR_SIGNED_ZEROS (mode))
29084 return copysign (x2, x);
29087 enum machine_mode mode = GET_MODE (operand0);
29088 rtx xa, xi, TWO52, tmp, label, one, res, mask;
29090 TWO52 = ix86_gen_TWO52 (mode);
29092 /* Temporary for holding the result, initialized to the input
29093 operand to ease control flow. */
29094 res = gen_reg_rtx (mode);
29095 emit_move_insn (res, operand1);
29097 /* xa = abs (operand1) */
29098 xa = ix86_expand_sse_fabs (res, &mask);
29100 /* if (!isless (xa, TWO52)) goto label; */
29101 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29103 /* xa = (double)(long)x */
29104 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29105 expand_fix (xi, res, 0);
29106 expand_float (xa, xi, 0);
29109 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
29111 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
29112 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
29113 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29114 gen_rtx_AND (mode, one, tmp)));
29115 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
29116 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29117 emit_move_insn (res, tmp);
29119 if (HONOR_SIGNED_ZEROS (mode))
29120 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
29122 emit_label (label);
29123 LABEL_NUSES (label) = 1;
29125 emit_move_insn (operand0, res);
29128 /* Expand SSE sequence for computing round from OPERAND1 storing
29129 into OPERAND0. Sequence that works without relying on DImode truncation
29130 via cvttsd2siq that is only available on 64bit targets. */
29132 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
29134 /* C code for the stuff we expand below.
29135 double xa = fabs (x), xa2, x2;
29136 if (!isless (xa, TWO52))
29138 Using the absolute value and copying back sign makes
29139 -0.0 -> -0.0 correct.
29140 xa2 = xa + TWO52 - TWO52;
29145 else if (dxa > 0.5)
29147 x2 = copysign (xa2, x);
29150 enum machine_mode mode = GET_MODE (operand0);
29151 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
29153 TWO52 = ix86_gen_TWO52 (mode);
29155 /* Temporary for holding the result, initialized to the input
29156 operand to ease control flow. */
29157 res = gen_reg_rtx (mode);
29158 emit_move_insn (res, operand1);
29160 /* xa = abs (operand1) */
29161 xa = ix86_expand_sse_fabs (res, &mask);
29163 /* if (!isless (xa, TWO52)) goto label; */
29164 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29166 /* xa2 = xa + TWO52 - TWO52; */
29167 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29168 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
29170 /* dxa = xa2 - xa; */
29171 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
29173 /* generate 0.5, 1.0 and -0.5 */
29174 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
29175 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
29176 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
29180 tmp = gen_reg_rtx (mode);
29181 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
29182 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
29183 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29184 gen_rtx_AND (mode, one, tmp)));
29185 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29186 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
29187 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
29188 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29189 gen_rtx_AND (mode, one, tmp)));
29190 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29192 /* res = copysign (xa2, operand1) */
29193 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
29195 emit_label (label);
29196 LABEL_NUSES (label) = 1;
29198 emit_move_insn (operand0, res);
29201 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29204 ix86_expand_trunc (rtx operand0, rtx operand1)
29206 /* C code for SSE variant we expand below.
29207 double xa = fabs (x), x2;
29208 if (!isless (xa, TWO52))
29210 x2 = (double)(long)x;
29211 if (HONOR_SIGNED_ZEROS (mode))
29212 return copysign (x2, x);
29215 enum machine_mode mode = GET_MODE (operand0);
29216 rtx xa, xi, TWO52, label, res, mask;
29218 TWO52 = ix86_gen_TWO52 (mode);
29220 /* Temporary for holding the result, initialized to the input
29221 operand to ease control flow. */
29222 res = gen_reg_rtx (mode);
29223 emit_move_insn (res, operand1);
29225 /* xa = abs (operand1) */
29226 xa = ix86_expand_sse_fabs (res, &mask);
29228 /* if (!isless (xa, TWO52)) goto label; */
29229 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29231 /* x = (double)(long)x */
29232 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29233 expand_fix (xi, res, 0);
29234 expand_float (res, xi, 0);
29236 if (HONOR_SIGNED_ZEROS (mode))
29237 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
29239 emit_label (label);
29240 LABEL_NUSES (label) = 1;
29242 emit_move_insn (operand0, res);
29245 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29248 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
29250 enum machine_mode mode = GET_MODE (operand0);
29251 rtx xa, mask, TWO52, label, one, res, smask, tmp;
29253 /* C code for SSE variant we expand below.
29254 double xa = fabs (x), x2;
29255 if (!isless (xa, TWO52))
29257 xa2 = xa + TWO52 - TWO52;
29261 x2 = copysign (xa2, x);
29265 TWO52 = ix86_gen_TWO52 (mode);
29267 /* Temporary for holding the result, initialized to the input
29268 operand to ease control flow. */
29269 res = gen_reg_rtx (mode);
29270 emit_move_insn (res, operand1);
29272 /* xa = abs (operand1) */
29273 xa = ix86_expand_sse_fabs (res, &smask);
29275 /* if (!isless (xa, TWO52)) goto label; */
29276 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29278 /* res = xa + TWO52 - TWO52; */
29279 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29280 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
29281 emit_move_insn (res, tmp);
29284 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
29286 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
29287 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
29288 emit_insn (gen_rtx_SET (VOIDmode, mask,
29289 gen_rtx_AND (mode, mask, one)));
29290 tmp = expand_simple_binop (mode, MINUS,
29291 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
29292 emit_move_insn (res, tmp);
29294 /* res = copysign (res, operand1) */
29295 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
29297 emit_label (label);
29298 LABEL_NUSES (label) = 1;
29300 emit_move_insn (operand0, res);
29303 /* Expand SSE sequence for computing round from OPERAND1 storing
29306 ix86_expand_round (rtx operand0, rtx operand1)
29308 /* C code for the stuff we're doing below:
29309 double xa = fabs (x);
29310 if (!isless (xa, TWO52))
29312 xa = (double)(long)(xa + nextafter (0.5, 0.0));
29313 return copysign (xa, x);
29315 enum machine_mode mode = GET_MODE (operand0);
29316 rtx res, TWO52, xa, label, xi, half, mask;
29317 const struct real_format *fmt;
29318 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
29320 /* Temporary for holding the result, initialized to the input
29321 operand to ease control flow. */
29322 res = gen_reg_rtx (mode);
29323 emit_move_insn (res, operand1);
29325 TWO52 = ix86_gen_TWO52 (mode);
29326 xa = ix86_expand_sse_fabs (res, &mask);
29327 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29329 /* load nextafter (0.5, 0.0) */
29330 fmt = REAL_MODE_FORMAT (mode);
29331 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
29332 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
29334 /* xa = xa + 0.5 */
29335 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
29336 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
29338 /* xa = (double)(int64_t)xa */
29339 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29340 expand_fix (xi, xa, 0);
29341 expand_float (xa, xi, 0);
29343 /* res = copysign (xa, operand1) */
29344 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
29346 emit_label (label);
29347 LABEL_NUSES (label) = 1;
29349 emit_move_insn (operand0, res);
29353 /* Validate whether a SSE5 instruction is valid or not.
29354 OPERANDS is the array of operands.
29355 NUM is the number of operands.
29356 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
29357 NUM_MEMORY is the maximum number of memory operands to accept.
29358 when COMMUTATIVE is set, operand 1 and 2 can be swapped. */
29361 ix86_sse5_valid_op_p (rtx operands[], rtx insn ATTRIBUTE_UNUSED, int num,
29362 bool uses_oc0, int num_memory, bool commutative)
29368 /* Count the number of memory arguments */
29371 for (i = 0; i < num; i++)
29373 enum machine_mode mode = GET_MODE (operands[i]);
29374 if (register_operand (operands[i], mode))
29377 else if (memory_operand (operands[i], mode))
29379 mem_mask |= (1 << i);
29385 rtx pattern = PATTERN (insn);
29387 /* allow 0 for pcmov */
29388 if (GET_CODE (pattern) != SET
29389 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
29391 || operands[i] != CONST0_RTX (mode))
29396 /* Special case pmacsdq{l,h} where we allow the 3rd argument to be
29397 a memory operation. */
29398 if (num_memory < 0)
29400 num_memory = -num_memory;
29401 if ((mem_mask & (1 << (num-1))) != 0)
29403 mem_mask &= ~(1 << (num-1));
29408 /* If there were no memory operations, allow the insn */
29412 /* Do not allow the destination register to be a memory operand. */
29413 else if (mem_mask & (1 << 0))
29416 /* If there are too many memory operations, disallow the instruction. While
29417 the hardware only allows 1 memory reference, before register allocation
29418 for some insns, we allow two memory operations sometimes in order to allow
29419 code like the following to be optimized:
29421 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
29423 or similar cases that are vectorized into using the fmaddss
29425 else if (mem_count > num_memory)
29428 /* Don't allow more than one memory operation if not optimizing. */
29429 else if (mem_count > 1 && !optimize)
29432 else if (num == 4 && mem_count == 1)
29434 /* formats (destination is the first argument), example fmaddss:
29435 xmm1, xmm1, xmm2, xmm3/mem
29436 xmm1, xmm1, xmm2/mem, xmm3
29437 xmm1, xmm2, xmm3/mem, xmm1
29438 xmm1, xmm2/mem, xmm3, xmm1 */
29440 return ((mem_mask == (1 << 1))
29441 || (mem_mask == (1 << 2))
29442 || (mem_mask == (1 << 3)));
29444 /* format, example pmacsdd:
29445 xmm1, xmm2, xmm3/mem, xmm1 */
29447 return (mem_mask == (1 << 2) || mem_mask == (1 << 1));
29449 return (mem_mask == (1 << 2));
29452 else if (num == 4 && num_memory == 2)
29454 /* If there are two memory operations, we can load one of the memory ops
29455 into the destination register. This is for optimizing the
29456 multiply/add ops, which the combiner has optimized both the multiply
29457 and the add insns to have a memory operation. We have to be careful
29458 that the destination doesn't overlap with the inputs. */
29459 rtx op0 = operands[0];
29461 if (reg_mentioned_p (op0, operands[1])
29462 || reg_mentioned_p (op0, operands[2])
29463 || reg_mentioned_p (op0, operands[3]))
29466 /* formats (destination is the first argument), example fmaddss:
29467 xmm1, xmm1, xmm2, xmm3/mem
29468 xmm1, xmm1, xmm2/mem, xmm3
29469 xmm1, xmm2, xmm3/mem, xmm1
29470 xmm1, xmm2/mem, xmm3, xmm1
29472 For the oc0 case, we will load either operands[1] or operands[3] into
29473 operands[0], so any combination of 2 memory operands is ok. */
29477 /* format, example pmacsdd:
29478 xmm1, xmm2, xmm3/mem, xmm1
29480 For the integer multiply/add instructions be more restrictive and
29481 require operands[2] and operands[3] to be the memory operands. */
29483 return (mem_mask == ((1 << 1) | (1 << 3)) || ((1 << 2) | (1 << 3)));
29485 return (mem_mask == ((1 << 2) | (1 << 3)));
29488 else if (num == 3 && num_memory == 1)
29490 /* formats, example protb:
29491 xmm1, xmm2, xmm3/mem
29492 xmm1, xmm2/mem, xmm3 */
29494 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
29496 /* format, example comeq:
29497 xmm1, xmm2, xmm3/mem */
29499 return (mem_mask == (1 << 2));
29503 gcc_unreachable ();
29509 /* Fixup an SSE5 instruction that has 2 memory input references into a form the
29510 hardware will allow by using the destination register to load one of the
29511 memory operations. Presently this is used by the multiply/add routines to
29512 allow 2 memory references. */
29515 ix86_expand_sse5_multiple_memory (rtx operands[],
29517 enum machine_mode mode)
29519 rtx op0 = operands[0];
29521 || memory_operand (op0, mode)
29522 || reg_mentioned_p (op0, operands[1])
29523 || reg_mentioned_p (op0, operands[2])
29524 || reg_mentioned_p (op0, operands[3]))
29525 gcc_unreachable ();
29527 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
29528 the destination register. */
29529 if (memory_operand (operands[1], mode))
29531 emit_move_insn (op0, operands[1]);
29534 else if (memory_operand (operands[3], mode))
29536 emit_move_insn (op0, operands[3]);
29540 gcc_unreachable ();
29546 /* Table of valid machine attributes. */
29547 static const struct attribute_spec ix86_attribute_table[] =
29549 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
29550 /* Stdcall attribute says callee is responsible for popping arguments
29551 if they are not variable. */
29552 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29553 /* Fastcall attribute says callee is responsible for popping arguments
29554 if they are not variable. */
29555 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29556 /* Cdecl attribute says the callee is a normal C declaration */
29557 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29558 /* Regparm attribute specifies how many integer arguments are to be
29559 passed in registers. */
29560 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
29561 /* Sseregparm attribute says we are using x86_64 calling conventions
29562 for FP arguments. */
29563 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29564 /* force_align_arg_pointer says this function realigns the stack at entry. */
29565 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
29566 false, true, true, ix86_handle_cconv_attribute },
29567 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29568 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
29569 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
29570 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
29572 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29573 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29574 #ifdef SUBTARGET_ATTRIBUTE_TABLE
29575 SUBTARGET_ATTRIBUTE_TABLE,
29577 /* ms_abi and sysv_abi calling convention function attributes. */
29578 { "ms_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29579 { "sysv_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29581 { NULL, 0, 0, false, false, false, NULL }
29584 /* Implement targetm.vectorize.builtin_vectorization_cost. */
29586 x86_builtin_vectorization_cost (bool runtime_test)
29588 /* If the branch of the runtime test is taken - i.e. - the vectorized
29589 version is skipped - this incurs a misprediction cost (because the
29590 vectorized version is expected to be the fall-through). So we subtract
29591 the latency of a mispredicted branch from the costs that are incured
29592 when the vectorized version is executed.
29594 TODO: The values in individual target tables have to be tuned or new
29595 fields may be needed. For eg. on K8, the default branch path is the
29596 not-taken path. If the taken path is predicted correctly, the minimum
29597 penalty of going down the taken-path is 1 cycle. If the taken-path is
29598 not predicted correctly, then the minimum penalty is 10 cycles. */
29602 return (-(ix86_cost->cond_taken_branch_cost));
29608 /* This function returns the calling abi specific va_list type node.
29609 It returns the FNDECL specific va_list type. */
29612 ix86_fn_abi_va_list (tree fndecl)
29617 return va_list_type_node;
29618 gcc_assert (fndecl != NULL_TREE);
29619 abi = ix86_function_abi ((const_tree) fndecl);
29622 return ms_va_list_type_node;
29624 return sysv_va_list_type_node;
29627 /* Returns the canonical va_list type specified by TYPE. If there
29628 is no valid TYPE provided, it return NULL_TREE. */
29631 ix86_canonical_va_list_type (tree type)
29635 /* Resolve references and pointers to va_list type. */
29636 if (INDIRECT_REF_P (type))
29637 type = TREE_TYPE (type);
29638 else if (POINTER_TYPE_P (type) && POINTER_TYPE_P (TREE_TYPE(type)))
29639 type = TREE_TYPE (type);
29643 wtype = va_list_type_node;
29644 gcc_assert (wtype != NULL_TREE);
29646 if (TREE_CODE (wtype) == ARRAY_TYPE)
29648 /* If va_list is an array type, the argument may have decayed
29649 to a pointer type, e.g. by being passed to another function.
29650 In that case, unwrap both types so that we can compare the
29651 underlying records. */
29652 if (TREE_CODE (htype) == ARRAY_TYPE
29653 || POINTER_TYPE_P (htype))
29655 wtype = TREE_TYPE (wtype);
29656 htype = TREE_TYPE (htype);
29659 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29660 return va_list_type_node;
29661 wtype = sysv_va_list_type_node;
29662 gcc_assert (wtype != NULL_TREE);
29664 if (TREE_CODE (wtype) == ARRAY_TYPE)
29666 /* If va_list is an array type, the argument may have decayed
29667 to a pointer type, e.g. by being passed to another function.
29668 In that case, unwrap both types so that we can compare the
29669 underlying records. */
29670 if (TREE_CODE (htype) == ARRAY_TYPE
29671 || POINTER_TYPE_P (htype))
29673 wtype = TREE_TYPE (wtype);
29674 htype = TREE_TYPE (htype);
29677 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29678 return sysv_va_list_type_node;
29679 wtype = ms_va_list_type_node;
29680 gcc_assert (wtype != NULL_TREE);
29682 if (TREE_CODE (wtype) == ARRAY_TYPE)
29684 /* If va_list is an array type, the argument may have decayed
29685 to a pointer type, e.g. by being passed to another function.
29686 In that case, unwrap both types so that we can compare the
29687 underlying records. */
29688 if (TREE_CODE (htype) == ARRAY_TYPE
29689 || POINTER_TYPE_P (htype))
29691 wtype = TREE_TYPE (wtype);
29692 htype = TREE_TYPE (htype);
29695 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29696 return ms_va_list_type_node;
29699 return std_canonical_va_list_type (type);
29702 /* Iterate through the target-specific builtin types for va_list.
29703 IDX denotes the iterator, *PTREE is set to the result type of
29704 the va_list builtin, and *PNAME to its internal type.
29705 Returns zero if there is no element for this index, otherwise
29706 IDX should be increased upon the next call.
29707 Note, do not iterate a base builtin's name like __builtin_va_list.
29708 Used from c_common_nodes_and_builtins. */
29711 ix86_enum_va_list (int idx, const char **pname, tree *ptree)
29717 *ptree = ms_va_list_type_node;
29718 *pname = "__builtin_ms_va_list";
29721 *ptree = sysv_va_list_type_node;
29722 *pname = "__builtin_sysv_va_list";
29730 /* Initialize the GCC target structure. */
29731 #undef TARGET_RETURN_IN_MEMORY
29732 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
29734 #undef TARGET_ATTRIBUTE_TABLE
29735 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
29736 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29737 # undef TARGET_MERGE_DECL_ATTRIBUTES
29738 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
29741 #undef TARGET_COMP_TYPE_ATTRIBUTES
29742 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
29744 #undef TARGET_INIT_BUILTINS
29745 #define TARGET_INIT_BUILTINS ix86_init_builtins
29746 #undef TARGET_EXPAND_BUILTIN
29747 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
29749 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
29750 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
29751 ix86_builtin_vectorized_function
29753 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
29754 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
29756 #undef TARGET_BUILTIN_RECIPROCAL
29757 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
29759 #undef TARGET_ASM_FUNCTION_EPILOGUE
29760 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
29762 #undef TARGET_ENCODE_SECTION_INFO
29763 #ifndef SUBTARGET_ENCODE_SECTION_INFO
29764 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
29766 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
29769 #undef TARGET_ASM_OPEN_PAREN
29770 #define TARGET_ASM_OPEN_PAREN ""
29771 #undef TARGET_ASM_CLOSE_PAREN
29772 #define TARGET_ASM_CLOSE_PAREN ""
29774 #undef TARGET_ASM_ALIGNED_HI_OP
29775 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
29776 #undef TARGET_ASM_ALIGNED_SI_OP
29777 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
29779 #undef TARGET_ASM_ALIGNED_DI_OP
29780 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
29783 #undef TARGET_ASM_UNALIGNED_HI_OP
29784 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
29785 #undef TARGET_ASM_UNALIGNED_SI_OP
29786 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
29787 #undef TARGET_ASM_UNALIGNED_DI_OP
29788 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
29790 #undef TARGET_SCHED_ADJUST_COST
29791 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
29792 #undef TARGET_SCHED_ISSUE_RATE
29793 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
29794 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
29795 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
29796 ia32_multipass_dfa_lookahead
29798 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
29799 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
29802 #undef TARGET_HAVE_TLS
29803 #define TARGET_HAVE_TLS true
29805 #undef TARGET_CANNOT_FORCE_CONST_MEM
29806 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
29807 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
29808 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
29810 #undef TARGET_DELEGITIMIZE_ADDRESS
29811 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
29813 #undef TARGET_MS_BITFIELD_LAYOUT_P
29814 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
29817 #undef TARGET_BINDS_LOCAL_P
29818 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
29820 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29821 #undef TARGET_BINDS_LOCAL_P
29822 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
29825 #undef TARGET_ASM_OUTPUT_MI_THUNK
29826 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
29827 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
29828 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
29830 #undef TARGET_ASM_FILE_START
29831 #define TARGET_ASM_FILE_START x86_file_start
29833 #undef TARGET_DEFAULT_TARGET_FLAGS
29834 #define TARGET_DEFAULT_TARGET_FLAGS \
29836 | TARGET_SUBTARGET_DEFAULT \
29837 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
29839 #undef TARGET_HANDLE_OPTION
29840 #define TARGET_HANDLE_OPTION ix86_handle_option
29842 #undef TARGET_RTX_COSTS
29843 #define TARGET_RTX_COSTS ix86_rtx_costs
29844 #undef TARGET_ADDRESS_COST
29845 #define TARGET_ADDRESS_COST ix86_address_cost
29847 #undef TARGET_FIXED_CONDITION_CODE_REGS
29848 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
29849 #undef TARGET_CC_MODES_COMPATIBLE
29850 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
29852 #undef TARGET_MACHINE_DEPENDENT_REORG
29853 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
29855 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
29856 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
29858 #undef TARGET_BUILD_BUILTIN_VA_LIST
29859 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
29861 #undef TARGET_FN_ABI_VA_LIST
29862 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
29864 #undef TARGET_CANONICAL_VA_LIST_TYPE
29865 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
29867 #undef TARGET_EXPAND_BUILTIN_VA_START
29868 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
29870 #undef TARGET_MD_ASM_CLOBBERS
29871 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
29873 #undef TARGET_PROMOTE_PROTOTYPES
29874 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
29875 #undef TARGET_STRUCT_VALUE_RTX
29876 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
29877 #undef TARGET_SETUP_INCOMING_VARARGS
29878 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
29879 #undef TARGET_MUST_PASS_IN_STACK
29880 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
29881 #undef TARGET_PASS_BY_REFERENCE
29882 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
29883 #undef TARGET_INTERNAL_ARG_POINTER
29884 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
29885 #undef TARGET_UPDATE_STACK_BOUNDARY
29886 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
29887 #undef TARGET_GET_DRAP_RTX
29888 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
29889 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
29890 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
29891 #undef TARGET_STRICT_ARGUMENT_NAMING
29892 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
29894 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
29895 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
29897 #undef TARGET_SCALAR_MODE_SUPPORTED_P
29898 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
29900 #undef TARGET_VECTOR_MODE_SUPPORTED_P
29901 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
29903 #undef TARGET_C_MODE_FOR_SUFFIX
29904 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
29907 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
29908 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
29911 #ifdef SUBTARGET_INSERT_ATTRIBUTES
29912 #undef TARGET_INSERT_ATTRIBUTES
29913 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
29916 #undef TARGET_MANGLE_TYPE
29917 #define TARGET_MANGLE_TYPE ix86_mangle_type
29919 #undef TARGET_STACK_PROTECT_FAIL
29920 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
29922 #undef TARGET_FUNCTION_VALUE
29923 #define TARGET_FUNCTION_VALUE ix86_function_value
29925 #undef TARGET_SECONDARY_RELOAD
29926 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
29928 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
29929 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
29931 #undef TARGET_SET_CURRENT_FUNCTION
29932 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
29934 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
29935 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
29937 #undef TARGET_OPTION_SAVE
29938 #define TARGET_OPTION_SAVE ix86_function_specific_save
29940 #undef TARGET_OPTION_RESTORE
29941 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
29943 #undef TARGET_OPTION_PRINT
29944 #define TARGET_OPTION_PRINT ix86_function_specific_print
29946 #undef TARGET_OPTION_CAN_INLINE_P
29947 #define TARGET_OPTION_CAN_INLINE_P ix86_can_inline_p
29949 #undef TARGET_EXPAND_TO_RTL_HOOK
29950 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
29952 struct gcc_target targetm = TARGET_INITIALIZER;
29954 #include "gt-i386.h"
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