2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416phy.h 203682 2010-02-08 20:12:01Z rpaulo $
20 #ifndef _DEV_ATH_AR5416PHY_H_
21 #define _DEV_ATH_AR5416PHY_H_
23 #include "ar5212/ar5212phy.h"
25 #define AR_PHY_CHIP_ID_REV_0 0x80 /* 5416 Rev 0 (owl 1.0) BB */
26 #define AR_PHY_CHIP_ID_REV_1 0x81 /* 5416 Rev 1 (owl 2.0) BB */
28 #define RFSILENT_BB 0x00002000 /* shush bb */
29 #define AR_PHY_RESTART 0x9970 /* restart */
30 #define AR_PHY_RESTART_DIV_GC 0x001C0000 /* bb_ant_fast_div_gc_limit */
31 #define AR_PHY_RESTART_DIV_GC_S 18
33 /* PLL settling times */
34 #define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */
35 #define HT40_CHANNEL_CENTER_SHIFT 10 /* MHz */
37 #define AR_PHY_RFBUS_REQ 0x997C
38 #define AR_PHY_RFBUS_REQ_EN 0x00000001
40 #define AR_2040_MODE 0x8318
41 #define AR_2040_JOINED_RX_CLEAR 0x00000001 // use ctl + ext rx_clear for cca
43 #define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */
44 #define AR_PHY_FC_DYN2040_EN 0x00000004 /* Enable dyn 20/40 mode */
45 #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */
46 #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/
47 #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */
48 #define AR_PHY_FC_HT_EN 0x00000040 /* ht enable */
49 #define AR_PHY_FC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */
50 #define AR_PHY_FC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */
51 #define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */
52 #define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800
54 #define AR_PHY_TIMING2 0x9810 /* Timing Control 2 */
55 #define AR_PHY_TIMING2_USE_FORCE 0x00001000
56 #define AR_PHY_TIMING2_FORCE_VAL 0x00000fff
58 #define AR_PHY_TIMING_CTRL4_CHAIN(_i) \
59 (AR_PHY_TIMING_CTRL4 + ((_i) << 12))
60 #define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000 /* perform calibration */
61 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F /* Mask for kcos_theta-1 for q correction */
62 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0 /* shift for Q_COFF */
63 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0 /* Mask for sin_theta for i correction */
64 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5 /* Shift for sin_theta for i correction */
65 #define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800 /* enable IQ correction */
66 #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000 /* Mask for max number of samples (logarithmic) */
67 #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12 /* Shift for max number of samples */
69 #define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000
70 #define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000 /* Enable spur filter */
71 #define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000
72 #define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000
74 #define AR_PHY_ADC_SERIAL_CTL 0x9830
75 #define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000
76 #define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001
78 #define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00
79 #define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
80 #define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F
81 #define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
83 #define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000
84 #define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17
85 #define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000
86 #define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12
87 #define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0
88 #define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6
89 #define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F
90 #define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
92 #define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
93 #define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
94 #define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
95 #define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
97 #define AR_PHY_EXT_CCA 0x99bc
98 #define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00
99 #define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
100 #define AR_PHY_EXT_MINCCA_PWR 0xFF800000
101 #define AR_PHY_EXT_MINCCA_PWR_S 23
102 #define AR_PHY_EXT_CCA_THRESH62 0x007F0000
103 #define AR_PHY_EXT_CCA_THRESH62_S 16
104 #define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000
105 #define AR9280_PHY_EXT_MINCCA_PWR_S 16
107 #define AR_PHY_HALFGI 0x99D0 /* Timing control 3 */
108 #define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0
109 #define AR_PHY_HALFGI_DSC_MAN_S 4
110 #define AR_PHY_HALFGI_DSC_EXP 0x0000000F
111 #define AR_PHY_HALFGI_DSC_EXP_S 0
113 #define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0
115 #define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99ec
116 #define AR_PHY_RIFS_INIT_DELAY 0x03ff0000
118 #define AR_PHY_M_SLEEP 0x99f0 /* sleep control registers */
119 #define AR_PHY_REFCLKDLY 0x99f4
120 #define AR_PHY_REFCLKPD 0x99f8
122 #define AR_PHY_CALMODE 0x99f0
123 /* Calibration Types */
124 #define AR_PHY_CALMODE_IQ 0x00000000
125 #define AR_PHY_CALMODE_ADC_GAIN 0x00000001
126 #define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
127 #define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
128 /* Calibration results */
129 #define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12))
130 #define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12))
131 #define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12))
132 #define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12))
135 #define AR_PHY_CCA 0x9864
136 #define AR_PHY_MINCCA_PWR 0x0FF80000
137 #define AR_PHY_MINCCA_PWR_S 19
138 #define AR9280_PHY_MINCCA_PWR 0x1FF00000
139 #define AR9280_PHY_MINCCA_PWR_S 20
140 #define AR9280_PHY_CCA_THRESH62 0x000FF000
141 #define AR9280_PHY_CCA_THRESH62_S 12
143 #define AR_PHY_CH1_CCA 0xa864
144 #define AR_PHY_CH1_MINCCA_PWR 0x0FF80000
145 #define AR_PHY_CH1_MINCCA_PWR_S 19
146 #define AR_PHY_CCA_THRESH62 0x0007F000
147 #define AR_PHY_CCA_THRESH62_S 12
148 #define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000
149 #define AR9280_PHY_CH1_MINCCA_PWR_S 20
151 #define AR_PHY_CH2_CCA 0xb864
152 #define AR_PHY_CH2_MINCCA_PWR 0x0FF80000
153 #define AR_PHY_CH2_MINCCA_PWR_S 19
155 #define AR_PHY_CH1_EXT_CCA 0xa9bc
156 #define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
157 #define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
158 #define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
159 #define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
161 #define AR_PHY_CH2_EXT_CCA 0xb9bc
162 #define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
163 #define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
165 #define AR_PHY_RX_CHAINMASK 0x99a4
167 #define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12))
168 #define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
169 #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
170 #define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac
172 #define AR_PHY_EXT_CCA0 0x99b8
173 #define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
174 #define AR_PHY_EXT_CCA0_THRESH62_S 0
176 #define AR_PHY_CH1_EXT_CCA 0xa9bc
177 #define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
178 #define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
180 #define AR_PHY_CH2_EXT_CCA 0xb9bc
181 #define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
182 #define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
183 #define AR_PHY_ANALOG_SWAP 0xa268
184 #define AR_PHY_SWAP_ALT_CHAIN 0x00000040
185 #define AR_PHY_CAL_CHAINMASK 0xa39c
187 #define AR_PHY_SWITCH_CHAIN_0 0x9960
188 #define AR_PHY_SWITCH_COM 0x9964
190 #define AR_PHY_RF_CTL2 0x9824
191 #define AR_PHY_TX_FRAME_TO_DATA_START 0x000000FF
192 #define AR_PHY_TX_FRAME_TO_DATA_START_S 0
193 #define AR_PHY_TX_FRAME_TO_PA_ON 0x0000FF00
194 #define AR_PHY_TX_FRAME_TO_PA_ON_S 8
196 #define AR_PHY_RF_CTL3 0x9828
197 #define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
198 #define AR_PHY_TX_END_TO_A2_RX_ON_S 16
200 #define AR_PHY_RF_CTL4 0x9834
201 #define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000
202 #define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24
203 #define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000
204 #define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16
205 #define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00
206 #define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8
207 #define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF
208 #define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
210 #define AR_PHY_SYNTH_CONTROL 0x9874
212 #define AR_PHY_FORCE_CLKEN_CCK 0xA22C
213 #define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040
215 #define AR_PHY_POWER_TX_SUB 0xA3C8
216 #define AR_PHY_POWER_TX_RATE5 0xA38C
217 #define AR_PHY_POWER_TX_RATE6 0xA390
218 #define AR_PHY_POWER_TX_RATE7 0xA3CC
219 #define AR_PHY_POWER_TX_RATE8 0xA3D0
220 #define AR_PHY_POWER_TX_RATE9 0xA3D4
222 #define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
223 #define AR_PHY_TPCRG1_PD_GAIN_1_S 16
224 #define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
225 #define AR_PHY_TPCRG1_PD_GAIN_2_S 18
226 #define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
227 #define AR_PHY_TPCRG1_PD_GAIN_3_S 20
229 #define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
230 #define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
232 #define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
233 #define AR_PHY_MASK2_M_31_45 0xa3a4
234 #define AR_PHY_MASK2_M_16_30 0xa3a8
235 #define AR_PHY_MASK2_M_00_15 0xa3ac
236 #define AR_PHY_MASK2_P_15_01 0xa3b8
237 #define AR_PHY_MASK2_P_30_16 0xa3bc
238 #define AR_PHY_MASK2_P_45_31 0xa3c0
239 #define AR_PHY_MASK2_P_61_45 0xa3c4
241 #define AR_PHY_SPUR_REG 0x994c
242 #define AR_PHY_SFCORR_EXT 0x99c0
243 #define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
244 #define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
245 #define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
246 #define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
247 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
248 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
249 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
250 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
251 #define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
253 /* enable vit puncture per rate, 8 bits, lsb is low rate */
254 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18)
255 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
257 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */
258 #define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9) /* use mask1 or mask2, one per rate */
259 #define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9
260 #define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100
261 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F
262 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
264 #define AR_PHY_PILOT_MASK_01_30 0xa3b0
265 #define AR_PHY_PILOT_MASK_31_60 0xa3b4
267 #define AR_PHY_CHANNEL_MASK_01_30 0x99d4
268 #define AR_PHY_CHANNEL_MASK_31_60 0x99d8
270 #define AR_PHY_CL_CAL_CTL 0xA358 /* carrier leak cal control */
271 #define AR_PHY_CL_CAL_ENABLE 0x00000002
272 #define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
273 #endif /* _DEV_ATH_AR5416PHY_H_ */