4 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org>
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 * Copyright (c) 2009 The DragonFly Project. All rights reserved.
21 * This code is derived from software contributed to The DragonFly Project
22 * by Matthew Dillon <dillon@backplane.com>
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
28 * 1. Redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer.
30 * 2. Redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in
32 * the documentation and/or other materials provided with the
34 * 3. Neither the name of The DragonFly Project nor the names of its
35 * contributors may be used to endorse or promote products derived
36 * from this software without specific, prior written permission.
38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
39 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
41 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
42 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
43 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
44 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
45 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
46 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
48 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
51 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $
56 void ahci_port_interrupt_enable(struct ahci_port *ap);
58 int ahci_load_prdt(struct ahci_ccb *);
59 void ahci_unload_prdt(struct ahci_ccb *);
60 static void ahci_load_prdt_callback(void *info, bus_dma_segment_t *segs,
61 int nsegs, int error);
62 void ahci_start(struct ahci_ccb *);
63 int ahci_port_softreset(struct ahci_port *ap);
64 int ahci_port_hardreset(struct ahci_port *ap, int hard);
65 void ahci_port_hardstop(struct ahci_port *ap);
67 static void ahci_ata_cmd_timeout_unserialized(void *);
68 void ahci_check_active_timeouts(struct ahci_port *ap);
70 void ahci_beg_exclusive_access(struct ahci_port *ap, struct ata_port *at);
71 void ahci_end_exclusive_access(struct ahci_port *ap, struct ata_port *at);
72 void ahci_issue_pending_commands(struct ahci_port *ap, struct ahci_ccb *ccb);
73 void ahci_issue_saved_commands(struct ahci_port *ap, u_int32_t mask);
75 int ahci_port_read_ncq_error(struct ahci_port *, int);
77 struct ahci_dmamem *ahci_dmamem_alloc(struct ahci_softc *, bus_dma_tag_t tag);
78 void ahci_dmamem_free(struct ahci_softc *, struct ahci_dmamem *);
79 static void ahci_dmamem_saveseg(void *info, bus_dma_segment_t *segs, int nsegs, int error);
81 static void ahci_dummy_done(struct ata_xfer *xa);
82 static void ahci_empty_done(struct ahci_ccb *ccb);
83 static void ahci_ata_cmd_done(struct ahci_ccb *ccb);
84 static u_int32_t ahci_pactive(struct ahci_port *ap);
87 * Initialize the global AHCI hardware. This code does not set up any of
91 ahci_init(struct ahci_softc *sc)
93 u_int32_t cap, pi, pleft;
97 DPRINTF(AHCI_D_VERBOSE, " GHC 0x%b",
98 ahci_read(sc, AHCI_REG_GHC), AHCI_FMT_GHC);
101 * save BIOS initialised parameters, enable staggered spin up
103 cap = ahci_read(sc, AHCI_REG_CAP);
104 cap &= AHCI_REG_CAP_SMPS;
105 cap |= AHCI_REG_CAP_SSS;
106 pi = ahci_read(sc, AHCI_REG_PI);
109 * Unconditionally reset the controller, do not conditionalize on
110 * trying to figure it if it was previously active or not.
112 * NOTE: On AE before HR. The AHCI-1.1 spec has a note in section
113 * 5.2.2.1 regarding this. HR should be set to 1 only after
114 * AE is set to 1. The reset sequence will clear HR when
115 * it completes, and will also clear AE if SAM is 0. AE must
116 * then be set again. When SAM is 1 the AE bit typically reads
117 * as 1 (and is read-only).
119 * NOTE: Avoid PCI[e] transaction burst by issuing dummy reads,
120 * otherwise the writes will only be separated by a few
125 * If you have a port multiplier and it does not have a device
126 * in target 0, and it probes normally, but a later operation
127 * mis-probes a target behind that PM, it is possible for the
128 * port to brick such that only (a) a power cycle of the host
129 * or (b) placing a device in target 0 will fix the problem.
130 * Power cycling the PM has no effect (it works fine on another
131 * host port). This issue is unrelated to CLO.
134 * Wait for any prior reset sequence to complete
136 if (ahci_wait_ne(sc, AHCI_REG_GHC,
137 AHCI_REG_GHC_HR, AHCI_REG_GHC_HR) != 0) {
138 device_printf(sc->sc_dev, "Controller is stuck in reset\n");
141 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE);
143 ahci_read(sc, AHCI_REG_GHC); /* flush */
144 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE | AHCI_REG_GHC_HR);
146 ahci_read(sc, AHCI_REG_GHC); /* flush */
147 if (ahci_wait_ne(sc, AHCI_REG_GHC,
148 AHCI_REG_GHC_HR, AHCI_REG_GHC_HR) != 0) {
149 device_printf(sc->sc_dev, "unable to reset controller\n");
152 if (ahci_read(sc, AHCI_REG_GHC) & AHCI_REG_GHC_AE) {
153 device_printf(sc->sc_dev, "AE did not auto-clear!\n");
154 ahci_write(sc, AHCI_REG_GHC, 0);
159 * Enable ahci (global interrupts disabled)
161 * Restore saved parameters. Avoid pci transaction burst write
162 * by issuing dummy reads.
165 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE);
168 ahci_read(sc, AHCI_REG_GHC); /* flush */
169 ahci_write(sc, AHCI_REG_CAP, cap);
170 ahci_write(sc, AHCI_REG_PI, pi);
171 ahci_read(sc, AHCI_REG_GHC); /* flush */
174 * Intel hocus pocus in case the BIOS has not set the chip up
175 * properly for AHCI operation.
177 if (pci_get_vendor(sc->sc_dev) == PCI_VENDOR_INTEL) {
178 if ((pci_read_config(sc->sc_dev, 0x92, 2) & 0x0F) != 0x0F)
179 device_printf(sc->sc_dev, "Intel hocus pocus\n");
180 pci_write_config(sc->sc_dev, 0x92,
181 pci_read_config(sc->sc_dev, 0x92, 2) | 0x0F, 2);
185 * This is a hack that currently does not appear to have
186 * a significant effect, but I noticed the port registers
187 * do not appear to be completely cleared after the host
188 * controller is reset.
190 * Use a temporary ap structure so we can call ahci_pwrite().
192 * We must be sure to stop the port
194 ap = kmalloc(sizeof(*ap), M_DEVBUF, M_WAITOK | M_ZERO);
197 for (i = 0; i < AHCI_MAX_PORTS; ++i) {
200 if ((pi & (1 << i)) == 0)
202 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh,
203 AHCI_PORT_REGION(i), AHCI_PORT_SIZE, &ap->ap_ioh) != 0) {
204 device_printf(sc->sc_dev, "can't map port\n");
208 * NOTE! Setting AHCI_PREG_SCTL_DET_DISABLE on AHCI1.0 or
209 * AHCI1.1 can brick the chipset. Not only brick it,
210 * but also crash the PC. The bit seems unreliable
211 * on AHCI1.2 as well.
213 ahci_port_stop(ap, 1);
214 ahci_pwrite(ap, AHCI_PREG_SCTL, AHCI_PREG_SCTL_IPM_DISABLED);
215 ahci_pwrite(ap, AHCI_PREG_SERR, -1);
216 ahci_pwrite(ap, AHCI_PREG_IE, 0);
217 ahci_write(ap->ap_sc, AHCI_REG_IS, 1 << i);
218 ahci_pwrite(ap, AHCI_PREG_CMD, 0);
219 ahci_pwrite(ap, AHCI_PREG_IS, -1);
220 sc->sc_portmask |= (1 << i);
230 * Allocate and initialize an AHCI port.
233 ahci_port_alloc(struct ahci_softc *sc, u_int port)
235 struct ahci_port *ap;
237 struct ahci_ccb *ccb;
241 struct ahci_cmd_hdr *hdr;
242 struct ahci_cmd_table *table;
247 ap = kmalloc(sizeof(*ap), M_DEVBUF, M_WAITOK | M_ZERO);
248 ap->ap_err_scratch = kmalloc(512, M_DEVBUF, M_WAITOK | M_ZERO);
250 ksnprintf(ap->ap_name, sizeof(ap->ap_name), "%s%d.%d",
251 device_get_name(sc->sc_dev),
252 device_get_unit(sc->sc_dev),
254 sc->sc_ports[port] = ap;
257 * Allocate enough so we never have to reallocate, it makes
260 * ap_pmcount will be reduced by the scan if we encounter the
261 * port multiplier port prior to target 15.
263 * kmalloc power-of-2 allocations are guaranteed not to cross
264 * a page boundary. Make sure the identify sub-structure in the
265 * at structure does not cross a page boundary, just in case the
266 * part is AHCI-1.1 and can't handle multiple DRQ blocks.
268 if (ap->ap_ata[0] == NULL) {
271 for (pw2 = 1; pw2 < sizeof(*at); pw2 <<= 1)
273 for (i = 0; i < AHCI_MAX_PMPORTS; ++i) {
274 at = kmalloc(pw2, M_DEVBUF, M_INTWAIT | M_ZERO);
276 at->at_ahci_port = ap;
278 at->at_probe = ATA_PROBE_NEED_INIT;
279 at->at_features |= ATA_PORT_F_RESCAN;
280 ksnprintf(at->at_name, sizeof(at->at_name),
281 "%s.%d", ap->ap_name, i);
284 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh,
285 AHCI_PORT_REGION(port), AHCI_PORT_SIZE, &ap->ap_ioh) != 0) {
286 device_printf(sc->sc_dev,
287 "unable to create register window for port %d\n",
294 ap->ap_probe = ATA_PROBE_NEED_INIT;
295 ap->link_pwr_mgmt = AHCI_LINK_PWR_MGMT_NONE;
296 ap->sysctl_tree = NULL;
297 TAILQ_INIT(&ap->ap_ccb_free);
298 TAILQ_INIT(&ap->ap_ccb_pending);
299 lockinit(&ap->ap_ccb_lock, "ahcipo", 0, 0);
301 /* Disable port interrupts */
302 ahci_pwrite(ap, AHCI_PREG_IE, 0);
303 ahci_pwrite(ap, AHCI_PREG_SERR, -1);
306 * Sec 10.1.2 - deinitialise port if it is already running
308 cmd = ahci_pread(ap, AHCI_PREG_CMD);
309 kprintf("%s: Caps %b\n", PORTNAME(ap), cmd, AHCI_PFMT_CMD);
311 if ((cmd & (AHCI_PREG_CMD_ST | AHCI_PREG_CMD_CR |
312 AHCI_PREG_CMD_FRE | AHCI_PREG_CMD_FR)) ||
313 (ahci_pread(ap, AHCI_PREG_SCTL) & AHCI_PREG_SCTL_DET)) {
316 r = ahci_port_stop(ap, 1);
318 device_printf(sc->sc_dev,
319 "unable to disable %s, ignoring port %d\n",
320 ((r == 2) ? "CR" : "FR"), port);
325 /* Write DET to zero */
326 ahci_pwrite(ap, AHCI_PREG_SCTL, AHCI_PREG_SCTL_IPM_DISABLED);
330 ap->ap_dmamem_rfis = ahci_dmamem_alloc(sc, sc->sc_tag_rfis);
331 if (ap->ap_dmamem_rfis == NULL) {
332 kprintf("%s: NORFIS\n", PORTNAME(ap));
336 /* Setup RFIS base address */
337 ap->ap_rfis = (struct ahci_rfis *) AHCI_DMA_KVA(ap->ap_dmamem_rfis);
338 dva = AHCI_DMA_DVA(ap->ap_dmamem_rfis);
339 ahci_pwrite(ap, AHCI_PREG_FBU, (u_int32_t)(dva >> 32));
340 ahci_pwrite(ap, AHCI_PREG_FB, (u_int32_t)dva);
342 /* Clear SERR before starting FIS reception or ST or anything */
344 ahci_pwrite(ap, AHCI_PREG_SERR, -1);
346 /* Enable FIS reception and activate port. */
347 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC;
348 cmd &= ~(AHCI_PREG_CMD_CLO | AHCI_PREG_CMD_PMA);
349 cmd |= AHCI_PREG_CMD_FRE | AHCI_PREG_CMD_POD | AHCI_PREG_CMD_SUD;
350 ahci_pwrite(ap, AHCI_PREG_CMD, cmd | AHCI_PREG_CMD_ICC_ACTIVE);
352 /* Check whether port activated. Skip it if not. */
353 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC;
354 if ((cmd & AHCI_PREG_CMD_FRE) == 0) {
355 kprintf("%s: NOT-ACTIVATED\n", PORTNAME(ap));
360 /* Allocate a CCB for each command slot */
361 ap->ap_ccbs = kmalloc(sizeof(struct ahci_ccb) * sc->sc_ncmds, M_DEVBUF,
363 if (ap->ap_ccbs == NULL) {
364 device_printf(sc->sc_dev,
365 "unable to allocate command list for port %d\n",
370 /* Command List Structures and Command Tables */
371 ap->ap_dmamem_cmd_list = ahci_dmamem_alloc(sc, sc->sc_tag_cmdh);
372 ap->ap_dmamem_cmd_table = ahci_dmamem_alloc(sc, sc->sc_tag_cmdt);
373 if (ap->ap_dmamem_cmd_table == NULL ||
374 ap->ap_dmamem_cmd_list == NULL) {
376 device_printf(sc->sc_dev,
377 "unable to allocate DMA memory for port %d\n",
382 /* Setup command list base address */
383 dva = AHCI_DMA_DVA(ap->ap_dmamem_cmd_list);
384 ahci_pwrite(ap, AHCI_PREG_CLBU, (u_int32_t)(dva >> 32));
385 ahci_pwrite(ap, AHCI_PREG_CLB, (u_int32_t)dva);
387 /* Split CCB allocation into CCBs and assign to command header/table */
388 hdr = AHCI_DMA_KVA(ap->ap_dmamem_cmd_list);
389 table = AHCI_DMA_KVA(ap->ap_dmamem_cmd_table);
390 for (i = 0; i < sc->sc_ncmds; i++) {
391 ccb = &ap->ap_ccbs[i];
393 error = bus_dmamap_create(sc->sc_tag_data, BUS_DMA_ALLOCNOW,
396 device_printf(sc->sc_dev,
397 "unable to create dmamap for port %d "
398 "ccb %d\n", port, i);
402 callout_init(&ccb->ccb_timeout);
405 ccb->ccb_cmd_hdr = &hdr[i];
406 ccb->ccb_cmd_table = &table[i];
407 dva = AHCI_DMA_DVA(ap->ap_dmamem_cmd_table) +
408 ccb->ccb_slot * sizeof(struct ahci_cmd_table);
409 ccb->ccb_cmd_hdr->ctba_hi = htole32((u_int32_t)(dva >> 32));
410 ccb->ccb_cmd_hdr->ctba_lo = htole32((u_int32_t)dva);
413 (struct ata_fis_h2d *)ccb->ccb_cmd_table->cfis;
414 ccb->ccb_xa.packetcmd = ccb->ccb_cmd_table->acmd;
417 ccb->ccb_xa.state = ATA_S_COMPLETE;
420 * CCB[1] is the error CCB and is not get or put. It is
421 * also used for probing. Numerous HBAs only load the
422 * signature from CCB[1] so it MUST be used for the second
426 ap->ap_err_ccb = ccb;
432 * Wait for ICC change to complete
434 ahci_pwait_clr(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_ICC);
437 * Calculate the interrupt mask
439 data = AHCI_PREG_IE_TFEE | AHCI_PREG_IE_HBFE |
440 AHCI_PREG_IE_IFE | AHCI_PREG_IE_OFE |
441 AHCI_PREG_IE_DPE | AHCI_PREG_IE_UFE |
442 AHCI_PREG_IE_PCE | AHCI_PREG_IE_PRCE |
443 AHCI_PREG_IE_DHRE | AHCI_PREG_IE_SDBE;
444 if (ap->ap_sc->sc_cap & AHCI_REG_CAP_SSNTF)
445 data |= AHCI_PREG_IE_IPME;
447 if (sc->sc_ccc_ports & (1 << port)
448 data &= ~(AHCI_PREG_IE_SDBE | AHCI_PREG_IE_DHRE);
450 ap->ap_intmask = data;
453 * Start the port helper thread. The helper thread will call
454 * ahci_port_init() so the ports can all be started in parallel.
455 * A failure by ahci_port_init() does not deallocate the port
456 * since we still want hot-plug events.
458 ahci_os_start_port(ap);
461 ahci_port_free(sc, port);
466 * [re]initialize an idle port. No CCBs should be active. (from port thread)
468 * This function is called during the initial port allocation sequence
469 * and is also called on hot-plug insertion. We take no chances and
470 * use a portreset instead of a softreset.
472 * This function is the only way to move a failed port back to active
475 * Returns 0 if a device is successfully detected.
478 ahci_port_init(struct ahci_port *ap)
483 * Register [re]initialization
485 * Flush the TFD and SERR and make sure the port is stopped before
486 * enabling its interrupt. We no longer cycle the port start as
487 * the port should not be started unless a device is present.
489 * XXX should we enable FIS reception? (FRE)?
491 ahci_pwrite(ap, AHCI_PREG_IE, 0);
492 ahci_port_stop(ap, 0);
493 if (ap->ap_sc->sc_cap & AHCI_REG_CAP_SSNTF)
494 ahci_pwrite(ap, AHCI_PREG_SNTF, -1);
496 ahci_pwrite(ap, AHCI_PREG_SERR, -1);
499 * If we are being harsh try to kill the port completely.
501 * AP_F_HARSH_REINIT is cleared in the hard reset state
503 if (ap->ap_flags & AP_F_HARSH_REINIT) {
504 ahci_pwrite(ap, AHCI_PREG_SCTL, AHCI_PREG_SCTL_IPM_DISABLED);
505 ahci_pwrite(ap, AHCI_PREG_CMD, 0);
509 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC;
510 cmd &= ~(AHCI_PREG_CMD_CLO | AHCI_PREG_CMD_PMA);
511 cmd |= AHCI_PREG_CMD_FRE | AHCI_PREG_CMD_POD |
513 ahci_pwrite(ap, AHCI_PREG_CMD, cmd | AHCI_PREG_CMD_ICC_ACTIVE);
514 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC;
515 if ((cmd & AHCI_PREG_CMD_FRE) == 0) {
516 kprintf("%s: Warning: FRE did not come up during "
517 "harsh reinitialization\n",
524 * Clear any pending garbage and re-enable the interrupt before
525 * going to the next stage.
527 ap->ap_probe = ATA_PROBE_NEED_HARD_RESET;
530 if (ap->ap_sc->sc_cap & AHCI_REG_CAP_SSNTF)
531 ahci_pwrite(ap, AHCI_PREG_SNTF, -1);
533 ahci_pwrite(ap, AHCI_PREG_SERR, -1);
534 ahci_pwrite(ap, AHCI_PREG_IS, -1);
536 ahci_port_interrupt_enable(ap);
542 * Enable or re-enable interrupts on a port.
544 * This routine is called from the port initialization code or from the
545 * helper thread as the real interrupt may be forced to turn off certain
549 ahci_port_interrupt_enable(struct ahci_port *ap)
551 ahci_pwrite(ap, AHCI_PREG_IE, ap->ap_intmask);
555 * Manage the agressive link power management capability.
558 ahci_port_link_pwr_mgmt(struct ahci_port *ap, int link_pwr_mgmt)
562 if (link_pwr_mgmt == ap->link_pwr_mgmt)
565 if ((ap->ap_sc->sc_cap & AHCI_REG_CAP_SALP) == 0) {
566 kprintf("%s: link power management not supported.\n",
571 ahci_os_lock_port(ap);
573 if (link_pwr_mgmt == AHCI_LINK_PWR_MGMT_AGGR &&
574 (ap->ap_sc->sc_cap & AHCI_REG_CAP_SSC)) {
575 kprintf("%s: enabling aggressive link power management.\n",
578 ap->link_pwr_mgmt = link_pwr_mgmt;
580 ap->ap_intmask &= ~AHCI_PREG_IE_PRCE;
581 ahci_port_interrupt_enable(ap);
583 sctl = ahci_pread(ap, AHCI_PREG_SCTL);
584 sctl &= ~(AHCI_PREG_SCTL_IPM_DISABLED);
585 ahci_pwrite(ap, AHCI_PREG_SCTL, sctl);
588 * Enable device initiated link power management for
589 * directly attached devices that support it.
591 if (ap->ap_type != ATA_PORT_T_PM &&
592 ap->ap_ata[0]->at_identify.satafsup & (1 << 3)) {
593 if (ahci_set_feature(ap, NULL, ATA_SATAFT_DEVIPS, 1))
594 kprintf("%s: Could not enable device initiated "
595 "link power management.\n",
599 cmd = ahci_pread(ap, AHCI_PREG_CMD);
600 cmd |= AHCI_PREG_CMD_ASP;
601 cmd |= AHCI_PREG_CMD_ALPE;
602 ahci_pwrite(ap, AHCI_PREG_CMD, cmd);
604 } else if (link_pwr_mgmt == AHCI_LINK_PWR_MGMT_MEDIUM &&
605 (ap->ap_sc->sc_cap & AHCI_REG_CAP_PSC)) {
606 kprintf("%s: enabling medium link power management.\n",
609 ap->link_pwr_mgmt = link_pwr_mgmt;
611 ap->ap_intmask &= ~AHCI_PREG_IE_PRCE;
612 ahci_port_interrupt_enable(ap);
614 sctl = ahci_pread(ap, AHCI_PREG_SCTL);
615 sctl |= AHCI_PREG_SCTL_IPM_DISABLED;
616 sctl &= ~AHCI_PREG_SCTL_IPM_NOPARTIAL;
617 ahci_pwrite(ap, AHCI_PREG_SCTL, sctl);
619 cmd = ahci_pread(ap, AHCI_PREG_CMD);
620 cmd &= ~AHCI_PREG_CMD_ASP;
621 cmd |= AHCI_PREG_CMD_ALPE;
622 ahci_pwrite(ap, AHCI_PREG_CMD, cmd);
624 } else if (link_pwr_mgmt == AHCI_LINK_PWR_MGMT_NONE) {
625 kprintf("%s: disabling link power management.\n",
628 /* Disable device initiated link power management */
629 if (ap->ap_type != ATA_PORT_T_PM &&
630 ap->ap_ata[0]->at_identify.satafsup & (1 << 3))
631 ahci_set_feature(ap, NULL, ATA_SATAFT_DEVIPS, 0);
633 cmd = ahci_pread(ap, AHCI_PREG_CMD);
634 cmd &= ~(AHCI_PREG_CMD_ALPE | AHCI_PREG_CMD_ASP);
635 ahci_pwrite(ap, AHCI_PREG_CMD, cmd);
637 sctl = ahci_pread(ap, AHCI_PREG_SCTL);
638 sctl |= AHCI_PREG_SCTL_IPM_DISABLED;
639 ahci_pwrite(ap, AHCI_PREG_SCTL, sctl);
641 /* let the drive come back to avoid PRCS interrupts later */
642 ahci_os_unlock_port(ap);
644 ahci_os_lock_port(ap);
646 ahci_pwrite(ap, AHCI_PREG_SERR,
647 AHCI_PREG_SERR_DIAG_N | AHCI_PREG_SERR_DIAG_W);
648 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_PRCS);
650 ap->ap_intmask |= AHCI_PREG_IE_PRCE;
651 ahci_port_interrupt_enable(ap);
653 ap->link_pwr_mgmt = link_pwr_mgmt;
655 kprintf("%s: unsupported link power management state %d.\n",
656 PORTNAME(ap), link_pwr_mgmt);
659 ahci_os_unlock_port(ap);
663 * Return current link power state.
666 ahci_port_link_pwr_state(struct ahci_port *ap)
670 r = ahci_pread(ap, AHCI_PREG_SSTS);
671 switch (r & SATA_PM_SSTS_IPM) {
672 case SATA_PM_SSTS_IPM_ACTIVE:
674 case SATA_PM_SSTS_IPM_PARTIAL:
676 case SATA_PM_SSTS_IPM_SLUMBER:
684 * Run the port / target state machine from a main context.
686 * The state machine for the port is always run.
688 * If atx is non-NULL run the state machine for a particular target.
689 * If atx is NULL run the state machine for all targets.
692 ahci_port_state_machine(struct ahci_port *ap, int initial)
701 * State machine for port. Note that CAM is not yet associated
702 * during the initial parallel probe and the port's probe state
703 * will not get past ATA_PROBE_NEED_IDENT.
706 if (initial == 0 && ap->ap_probe <= ATA_PROBE_NEED_HARD_RESET) {
707 kprintf("%s: Waiting 10 seconds on insertion\n",
709 ahci_os_sleep(10000);
712 if (ap->ap_probe == ATA_PROBE_NEED_INIT)
714 if (ap->ap_probe == ATA_PROBE_NEED_HARD_RESET)
715 ahci_port_reset(ap, NULL, 1);
716 if (ap->ap_probe == ATA_PROBE_NEED_SOFT_RESET)
717 ahci_port_reset(ap, NULL, 0);
718 if (ap->ap_probe == ATA_PROBE_NEED_IDENT)
719 ahci_cam_probe(ap, NULL);
721 if (ap->ap_type != ATA_PORT_T_PM) {
722 if (ap->ap_probe == ATA_PROBE_FAILED) {
723 ahci_cam_changed(ap, NULL, 0);
724 } else if (ap->ap_probe >= ATA_PROBE_NEED_IDENT) {
725 ahci_cam_changed(ap, NULL, 1);
731 * Port Multiplier state machine.
733 * Get a mask of changed targets and combine with any runnable
734 * states already present.
736 for (loop = 0; ;++loop) {
737 if (ahci_pm_read(ap, 15, SATA_PMREG_EINFO, &data)) {
738 kprintf("%s: PM unable to read hot-plug bitmap\n",
744 * Do at least one loop, then stop if no more state changes
745 * have occured. The PM might not generate a new
746 * notification until we clear the entire bitmap.
748 if (loop && data == 0)
752 * New devices showing up in the bitmap require some spin-up
753 * time before we start probing them. Reset didsleep. The
754 * first new device we detect will sleep before probing.
756 * This only applies to devices whos change bit is set in
757 * the data, and does not apply to the initial boot-time
762 for (target = 0; target < ap->ap_pmcount; ++target) {
763 at = ap->ap_ata[target];
766 * Check the target state for targets behind the PM
767 * which have changed state. This will adjust
768 * at_probe and set ATA_PORT_F_RESCAN
770 * We want to wait at least 10 seconds before probing
771 * a newly inserted device. If the check status
772 * indicates a device is present and in need of a
773 * hard reset, we make sure we have slept before
776 * We also need to wait at least 1 second for the
777 * PHY state to change after insertion, if we
778 * haven't already waited the 10 seconds.
780 * NOTE: When pm_check_good finds a good port it
781 * typically starts us in probe state
782 * NEED_HARD_RESET rather than INIT.
784 if (data & (1 << target)) {
785 if (initial == 0 && didsleep == 0)
787 ahci_pm_check_good(ap, target);
788 if (initial == 0 && didsleep == 0 &&
789 at->at_probe <= ATA_PROBE_NEED_HARD_RESET
792 kprintf("%s: Waiting 10 seconds on insertion\n", PORTNAME(ap));
793 ahci_os_sleep(10000);
798 * Report hot-plug events before the probe state
799 * really gets hot. Only actual events are reported
800 * here to reduce spew.
802 if (data & (1 << target)) {
803 kprintf("%s: HOTPLUG (PM) - ", ATANAME(ap, at));
804 switch(at->at_probe) {
805 case ATA_PROBE_NEED_INIT:
806 case ATA_PROBE_NEED_HARD_RESET:
807 kprintf("Device inserted\n");
809 case ATA_PROBE_FAILED:
810 kprintf("Device removed\n");
813 kprintf("Device probe in progress\n");
819 * Run through the state machine as necessary if
820 * the port is not marked failed.
822 * The state machine may stop at NEED_IDENT if
823 * CAM is not yet attached.
825 * Acquire exclusive access to the port while we
826 * are doing this. This prevents command-completion
827 * from queueing commands for non-polled targets
828 * inbetween our probe steps. We need to do this
829 * because the reset probes can generate severe PHY
830 * and protocol errors and soft-brick the port.
832 if (at->at_probe != ATA_PROBE_FAILED &&
833 at->at_probe != ATA_PROBE_GOOD) {
834 ahci_beg_exclusive_access(ap, at);
835 if (at->at_probe == ATA_PROBE_NEED_INIT)
836 ahci_pm_port_init(ap, at);
837 if (at->at_probe == ATA_PROBE_NEED_HARD_RESET)
838 ahci_port_reset(ap, at, 1);
839 if (at->at_probe == ATA_PROBE_NEED_SOFT_RESET)
840 ahci_port_reset(ap, at, 0);
841 if (at->at_probe == ATA_PROBE_NEED_IDENT)
842 ahci_cam_probe(ap, at);
843 ahci_end_exclusive_access(ap, at);
847 * Add or remove from CAM
849 if (at->at_features & ATA_PORT_F_RESCAN) {
850 at->at_features &= ~ATA_PORT_F_RESCAN;
851 if (at->at_probe == ATA_PROBE_FAILED) {
852 ahci_cam_changed(ap, at, 0);
853 } else if (at->at_probe >= ATA_PROBE_NEED_IDENT) {
854 ahci_cam_changed(ap, at, 1);
857 data &= ~(1 << target);
860 kprintf("%s: WARNING (PM): extra bits set in "
861 "EINFO: %08x\n", PORTNAME(ap), data);
862 while (target < AHCI_MAX_PMPORTS) {
863 ahci_pm_check_good(ap, target);
872 * De-initialize and detach a port.
875 ahci_port_free(struct ahci_softc *sc, u_int port)
877 struct ahci_port *ap = sc->sc_ports[port];
878 struct ahci_ccb *ccb;
882 * Ensure port is disabled and its interrupts are all flushed.
885 ahci_port_stop(ap, 1);
886 ahci_os_stop_port(ap);
887 ahci_pwrite(ap, AHCI_PREG_CMD, 0);
888 ahci_pwrite(ap, AHCI_PREG_IE, 0);
889 ahci_pwrite(ap, AHCI_PREG_IS, ahci_pread(ap, AHCI_PREG_IS));
890 ahci_write(sc, AHCI_REG_IS, 1 << port);
894 while ((ccb = ahci_get_ccb(ap)) != NULL) {
895 if (ccb->ccb_dmamap) {
896 bus_dmamap_destroy(sc->sc_tag_data,
898 ccb->ccb_dmamap = NULL;
901 if ((ccb = ap->ap_err_ccb) != NULL) {
902 if (ccb->ccb_dmamap) {
903 bus_dmamap_destroy(sc->sc_tag_data,
905 ccb->ccb_dmamap = NULL;
907 ap->ap_err_ccb = NULL;
909 kfree(ap->ap_ccbs, M_DEVBUF);
913 if (ap->ap_dmamem_cmd_list) {
914 ahci_dmamem_free(sc, ap->ap_dmamem_cmd_list);
915 ap->ap_dmamem_cmd_list = NULL;
917 if (ap->ap_dmamem_rfis) {
918 ahci_dmamem_free(sc, ap->ap_dmamem_rfis);
919 ap->ap_dmamem_rfis = NULL;
921 if (ap->ap_dmamem_cmd_table) {
922 ahci_dmamem_free(sc, ap->ap_dmamem_cmd_table);
923 ap->ap_dmamem_cmd_table = NULL;
926 for (i = 0; i < AHCI_MAX_PMPORTS; ++i) {
928 kfree(ap->ap_ata[i], M_DEVBUF);
929 ap->ap_ata[i] = NULL;
933 if (ap->ap_err_scratch) {
934 kfree(ap->ap_err_scratch, M_DEVBUF);
935 ap->ap_err_scratch = NULL;
938 /* bus_space(9) says we dont free the subregions handle */
941 sc->sc_ports[port] = NULL;
946 ahci_pactive(struct ahci_port *ap)
950 mask = ahci_pread(ap, AHCI_PREG_CI);
951 if (ap->ap_sc->sc_cap & AHCI_REG_CAP_SNCQ)
952 mask |= ahci_pread(ap, AHCI_PREG_SACT);
957 * Start high-level command processing on the port
960 ahci_port_start(struct ahci_port *ap)
962 u_int32_t r, s, is, tfd;
965 * FRE must be turned on before ST. Wait for FR to go active
966 * before turning on ST. The spec doesn't seem to think this
967 * is necessary but waiting here avoids an on-off race in the
968 * ahci_port_stop() code.
970 r = ahci_pread(ap, AHCI_PREG_CMD);
971 if ((r & AHCI_PREG_CMD_FRE) == 0) {
972 r |= AHCI_PREG_CMD_FRE;
973 ahci_pwrite(ap, AHCI_PREG_CMD, r);
975 if ((ap->ap_sc->sc_flags & AHCI_F_IGN_FR) == 0) {
976 if (ahci_pwait_set(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_FR)) {
977 kprintf("%s: Cannot start FIS reception\n",
986 * Turn on ST, wait for CR to come up.
988 r |= AHCI_PREG_CMD_ST;
989 ahci_pwrite(ap, AHCI_PREG_CMD, r);
990 if (ahci_pwait_set_to(ap, 2000, AHCI_PREG_CMD, AHCI_PREG_CMD_CR)) {
991 s = ahci_pread(ap, AHCI_PREG_SERR);
992 is = ahci_pread(ap, AHCI_PREG_IS);
993 tfd = ahci_pread(ap, AHCI_PREG_TFD);
994 kprintf("%s: Cannot start command DMA\n"
999 r, AHCI_PFMT_CMD, s, AHCI_PFMT_SERR,
1001 tfd, AHCI_PFMT_TFD_STS);
1005 #ifdef AHCI_COALESCE
1007 * (Re-)enable coalescing on the port.
1009 if (ap->ap_sc->sc_ccc_ports & (1 << ap->ap_num)) {
1010 ap->ap_sc->sc_ccc_ports_cur |= (1 << ap->ap_num);
1011 ahci_write(ap->ap_sc, AHCI_REG_CCC_PORTS,
1012 ap->ap_sc->sc_ccc_ports_cur);
1020 * Stop high-level command processing on a port
1022 * WARNING! If the port is stopped while CR is still active our saved
1023 * CI/SACT will race any commands completed by the command
1024 * processor prior to being able to stop. Thus we never call
1025 * this function unless we intend to dispose of any remaining
1026 * active commands. In particular, this complicates the timeout
1030 ahci_port_stop(struct ahci_port *ap, int stop_fis_rx)
1034 #ifdef AHCI_COALESCE
1036 * Disable coalescing on the port while it is stopped.
1038 if (ap->ap_sc->sc_ccc_ports & (1 << ap->ap_num)) {
1039 ap->ap_sc->sc_ccc_ports_cur &= ~(1 << ap->ap_num);
1040 ahci_write(ap->ap_sc, AHCI_REG_CCC_PORTS,
1041 ap->ap_sc->sc_ccc_ports_cur);
1046 * Turn off ST, then wait for CR to go off.
1048 r = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC;
1049 r &= ~AHCI_PREG_CMD_ST;
1050 ahci_pwrite(ap, AHCI_PREG_CMD, r);
1052 if (ahci_pwait_clr(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_CR)) {
1053 kprintf("%s: Port bricked, unable to stop (ST)\n",
1060 * Turn off FRE, then wait for FR to go off. FRE cannot
1061 * be turned off until CR transitions to 0.
1063 if ((r & AHCI_PREG_CMD_FR) == 0) {
1064 kprintf("%s: FR stopped, clear FRE for next start\n",
1070 r &= ~AHCI_PREG_CMD_FRE;
1071 ahci_pwrite(ap, AHCI_PREG_CMD, r);
1072 if (ahci_pwait_clr(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_FR)) {
1073 kprintf("%s: Port bricked, unable to stop (FRE)\n",
1083 * AHCI command list override -> forcibly clear TFD.STS.{BSY,DRQ}
1086 ahci_port_clo(struct ahci_port *ap)
1088 struct ahci_softc *sc = ap->ap_sc;
1091 /* Only attempt CLO if supported by controller */
1092 if ((ahci_read(sc, AHCI_REG_CAP) & AHCI_REG_CAP_SCLO) == 0)
1096 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC;
1097 ahci_pwrite(ap, AHCI_PREG_CMD, cmd | AHCI_PREG_CMD_CLO);
1099 /* Wait for completion */
1100 if (ahci_pwait_clr(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_CLO)) {
1101 kprintf("%s: CLO did not complete\n", PORTNAME(ap));
1111 * If hard is 0 perform a softreset of the port.
1112 * If hard is 1 perform a hard reset of the port.
1114 * If at is non-NULL an indirect port via a port-multiplier is being
1115 * reset, otherwise a direct port is being reset.
1117 * NOTE: Indirect ports can only be soft-reset.
1120 ahci_port_reset(struct ahci_port *ap, struct ata_port *at, int hard)
1126 rc = ahci_pm_hardreset(ap, at->at_target, hard);
1128 rc = ahci_port_hardreset(ap, hard);
1131 rc = ahci_pm_softreset(ap, at->at_target);
1133 rc = ahci_port_softreset(ap);
1139 * AHCI soft reset, Section 10.4.1
1141 * (at) will be NULL when soft-resetting a directly-attached device, and
1142 * non-NULL when soft-resetting a device through a port multiplier.
1144 * This function keeps port communications intact and attempts to generate
1145 * a reset to the connected device using device commands.
1148 ahci_port_softreset(struct ahci_port *ap)
1150 struct ahci_ccb *ccb = NULL;
1151 struct ahci_cmd_hdr *cmd_slot;
1158 kprintf("%s: START SOFTRESET %b\n", PORTNAME(ap),
1159 ahci_pread(ap, AHCI_PREG_CMD), AHCI_PFMT_CMD);
1162 DPRINTF(AHCI_D_VERBOSE, "%s: soft reset\n", PORTNAME(ap));
1165 ap->ap_flags |= AP_F_IN_RESET;
1166 ap->ap_state = AP_S_NORMAL;
1169 * Remember port state in cmd (main to restore start/stop)
1173 if (ahci_port_stop(ap, 0)) {
1174 kprintf("%s: failed to stop port, cannot softreset\n",
1180 * Request CLO if device appears hung.
1182 if (ahci_pread(ap, AHCI_PREG_TFD) &
1183 (AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) {
1188 * This is an attempt to clear errors so a new signature will
1189 * be latched. It isn't working properly. XXX
1192 ahci_pwrite(ap, AHCI_PREG_SERR, -1);
1195 if (ahci_port_start(ap)) {
1196 kprintf("%s: failed to start port, cannot softreset\n",
1201 /* Check whether CLO worked */
1202 if (ahci_pwait_clr(ap, AHCI_PREG_TFD,
1203 AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) {
1204 kprintf("%s: CLO %s, need port reset\n",
1206 (ahci_read(ap->ap_sc, AHCI_REG_CAP) & AHCI_REG_CAP_SCLO)
1207 ? "failed" : "unsupported");
1213 * Prep first D2H command with SRST feature & clear busy/reset flags
1215 * It is unclear which other fields in the FIS are used. Just zero
1218 * NOTE! This CCB is used for both the first and second commands.
1219 * The second command must use CCB slot 1 to properly load
1222 ccb = ahci_get_err_ccb(ap);
1223 ccb->ccb_xa.complete = ahci_dummy_done;
1224 ccb->ccb_xa.flags = ATA_F_POLL | ATA_F_EXCLUSIVE;
1225 KKASSERT(ccb->ccb_slot == 1);
1226 ccb->ccb_xa.at = NULL;
1227 cmd_slot = ccb->ccb_cmd_hdr;
1229 fis = ccb->ccb_cmd_table->cfis;
1230 bzero(fis, sizeof(ccb->ccb_cmd_table->cfis));
1231 fis[0] = ATA_FIS_TYPE_H2D;
1232 fis[15] = ATA_FIS_CONTROL_SRST|ATA_FIS_CONTROL_4BIT;
1234 cmd_slot->prdtl = 0;
1235 cmd_slot->flags = htole16(5); /* FIS length: 5 DWORDS */
1236 cmd_slot->flags |= htole16(AHCI_CMD_LIST_FLAG_C); /* Clear busy on OK */
1237 cmd_slot->flags |= htole16(AHCI_CMD_LIST_FLAG_R); /* Reset */
1239 ccb->ccb_xa.state = ATA_S_PENDING;
1241 if (ahci_poll(ccb, 1000, ahci_quick_timeout) != ATA_S_COMPLETE) {
1242 kprintf("%s: First FIS failed\n", PORTNAME(ap));
1247 * WARNING! TIME SENSITIVE SPACE! WARNING!
1249 * The two FISes are supposed to be back to back. Don't issue other
1250 * commands or even delay if we can help it.
1254 * Prep second D2H command to read status and complete reset sequence
1255 * AHCI 10.4.1 and "Serial ATA Revision 2.6". I can't find the ATA
1256 * Rev 2.6 and it is unclear how the second FIS should be set up
1257 * from the AHCI document.
1259 * Give the device 3ms before sending the second FIS.
1261 * It is unclear which other fields in the FIS are used. Just zero
1264 ccb->ccb_xa.flags = ATA_F_POLL | ATA_F_AUTOSENSE | ATA_F_EXCLUSIVE;
1266 bzero(fis, sizeof(ccb->ccb_cmd_table->cfis));
1267 fis[0] = ATA_FIS_TYPE_H2D;
1268 fis[15] = ATA_FIS_CONTROL_4BIT;
1270 cmd_slot->prdtl = 0;
1271 cmd_slot->flags = htole16(5); /* FIS length: 5 DWORDS */
1273 ccb->ccb_xa.state = ATA_S_PENDING;
1274 if (ahci_poll(ccb, 1000, ahci_quick_timeout) != ATA_S_COMPLETE) {
1275 kprintf("%s: Second FIS failed\n", PORTNAME(ap));
1279 if (ahci_pwait_clr(ap, AHCI_PREG_TFD,
1280 AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) {
1281 kprintf("%s: device didn't come ready after reset, TFD: 0x%b\n",
1283 ahci_pread(ap, AHCI_PREG_TFD), AHCI_PFMT_TFD_STS);
1290 * If the softreset is trying to clear a BSY condition after a
1291 * normal portreset we assign the port type.
1293 * If the softreset is being run first as part of the ccb error
1294 * processing code then report if the device signature changed
1297 if (ap->ap_type == ATA_PORT_T_NONE) {
1298 ap->ap_type = ahci_port_signature_detect(ap, NULL);
1300 if (ahci_port_signature_detect(ap, NULL) != ap->ap_type) {
1301 kprintf("%s: device signature unexpectedly "
1302 "changed\n", PORTNAME(ap));
1303 error = EBUSY; /* XXX */
1311 ahci_put_err_ccb(ccb);
1314 * If the target is busy use CLO to clear the busy
1315 * condition. The BSY should be cleared on the next
1318 if (ahci_pread(ap, AHCI_PREG_TFD) &
1319 (AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) {
1325 * If we failed to softreset make the port quiescent, otherwise
1326 * make sure the port's start/stop state matches what it was on
1329 * Don't kill the port if the softreset is on a port multiplier
1330 * target, that would kill all the targets!
1333 ahci_port_hardstop(ap);
1334 /* ap_probe set to failed */
1336 ap->ap_probe = ATA_PROBE_NEED_IDENT;
1338 ahci_port_start(ap);
1340 ap->ap_flags &= ~AP_F_IN_RESET;
1344 kprintf("%s: END SOFTRESET\n", PORTNAME(ap));
1350 * AHCI port reset, Section 10.4.2
1352 * This function does a hard reset of the port. Note that the device
1353 * connected to the port could still end-up hung.
1356 ahci_port_hardreset(struct ahci_port *ap, int hard)
1364 kprintf("%s: START HARDRESET\n", PORTNAME(ap));
1365 ap->ap_flags |= AP_F_IN_RESET;
1370 ahci_port_stop(ap, 0);
1371 ap->ap_state = AP_S_NORMAL;
1374 * The port may have been quiescent with its SUD bit cleared, so
1375 * set the SUD (spin up device).
1377 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC;
1378 cmd |= AHCI_PREG_CMD_SUD;
1379 ahci_pwrite(ap, AHCI_PREG_CMD, cmd);
1382 * Perform device detection.
1384 * NOTE! AHCi_PREG_SCTL_DET_DISABLE seems to be highly unreliable
1385 * on multiple chipsets and can brick the chipset or even
1386 * the whole PC. Never use it.
1388 ap->ap_type = ATA_PORT_T_NONE;
1390 r = AHCI_PREG_SCTL_IPM_DISABLED;
1391 ahci_pwrite(ap, AHCI_PREG_SCTL, r);
1395 * Start transmitting COMRESET. COMRESET must be sent for at
1398 r = AHCI_PREG_SCTL_IPM_DISABLED | AHCI_PREG_SCTL_DET_INIT;
1399 if (AhciForceGen1 & (1 << ap->ap_num))
1400 r |= AHCI_PREG_SCTL_SPD_GEN1;
1402 r |= AHCI_PREG_SCTL_SPD_ANY;
1403 ahci_pwrite(ap, AHCI_PREG_SCTL, r);
1406 * Through trial and error it seems to take around 100ms
1407 * for the detect logic to settle down. If this is too
1408 * short the softreset code will fail.
1410 if (ap->ap_flags & AP_F_HARSH_REINIT)
1411 ahci_os_sleep(1000);
1414 ap->ap_flags &= ~AP_F_HARSH_REINIT;
1417 * Only SERR_DIAG_X needs to be cleared for TFD updates, but
1418 * since we are hard-resetting the port we might as well clear
1419 * the whole enchillada
1422 ahci_pwrite(ap, AHCI_PREG_SERR, -1);
1423 r &= ~AHCI_PREG_SCTL_DET_INIT;
1424 r |= AHCI_PREG_SCTL_DET_NONE;
1425 ahci_pwrite(ap, AHCI_PREG_SCTL, r);
1428 * Try to determine if there is a device on the port.
1430 * Give the device 3/10 second to at least be detected.
1431 * If we fail clear PRCS (phy detect) since we may cycled
1432 * the phy and probably caused another PRCS interrupt.
1436 r = ahci_pread(ap, AHCI_PREG_SSTS);
1437 if (r & AHCI_PREG_SSTS_DET)
1439 loop -= ahci_os_softsleep();
1442 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_PRCS);
1444 kprintf("%s: Port appears to be unplugged\n",
1452 * There is something on the port. Give the device 3 seconds
1453 * to fully negotiate.
1455 if (ahci_pwait_eq(ap, 3000, AHCI_PREG_SSTS,
1456 AHCI_PREG_SSTS_DET, AHCI_PREG_SSTS_DET_DEV)) {
1458 kprintf("%s: Device may be powered down\n",
1466 * We got something that definitely looks like a device. Give
1467 * the device time to send us its first D2H FIS. Waiting for
1468 * BSY to clear accomplishes this.
1470 * NOTE that a port multiplier may or may not clear BSY here,
1471 * depending on what is sitting in target 0 behind it.
1475 if (ahci_pwait_clr_to(ap, 3000, AHCI_PREG_TFD,
1476 AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) {
1484 * Do the PM port probe regardless of how things turned out on
1487 if (ap->ap_sc->sc_cap & AHCI_REG_CAP_SPM)
1488 error = ahci_pm_port_probe(ap, error);
1497 * All good, make sure the port is running and set the
1498 * probe state. Ignore the signature junk (it's unreliable)
1499 * until we get to the softreset code.
1501 if (ahci_port_start(ap)) {
1502 kprintf("%s: failed to start command DMA on port, "
1503 "disabling\n", PORTNAME(ap));
1507 if (ap->ap_type == ATA_PORT_T_PM)
1508 ap->ap_probe = ATA_PROBE_GOOD;
1510 ap->ap_probe = ATA_PROBE_NEED_SOFT_RESET;
1514 * Normal device probe failure
1516 data = ahci_pread(ap, AHCI_PREG_SSTS);
1518 switch(data & AHCI_PREG_SSTS_DET) {
1519 case AHCI_PREG_SSTS_DET_DEV_NE:
1520 kprintf("%s: Device not communicating\n",
1523 case AHCI_PREG_SSTS_DET_PHYOFFLINE:
1524 kprintf("%s: PHY offline\n",
1528 kprintf("%s: No device detected\n",
1532 ahci_port_hardstop(ap);
1536 * Abnormal probe (EBUSY)
1538 kprintf("%s: Device on port is bricked\n",
1540 ahci_port_hardstop(ap);
1542 rc = ahci_port_reset(ap, atx, 0);
1544 kprintf("%s: Unable unbrick device\n",
1547 kprintf("%s: Successfully unbricked\n",
1557 ahci_pwrite(ap, AHCI_PREG_SERR, -1);
1558 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_PCS | AHCI_PREG_IS_PRCS);
1560 ap->ap_flags &= ~AP_F_IN_RESET;
1563 kprintf("%s: END HARDRESET %d\n", PORTNAME(ap), error);
1568 * Hard-stop on hot-swap device removal. See 10.10.1
1570 * Place the port in a mode that will allow it to detect hot-swap insertions.
1571 * This is a bit imprecise because just setting-up SCTL to DET_INIT doesn't
1572 * seem to do the job.
1574 * FIS reception is left enabled but command processing is disabled.
1575 * Cycling FIS reception (FRE) can brick ports.
1578 ahci_port_hardstop(struct ahci_port *ap)
1580 struct ahci_ccb *ccb;
1581 struct ata_port *at;
1588 * Stop the port. We can't modify things like SUD if the port
1591 ap->ap_state = AP_S_FATAL_ERROR;
1592 ap->ap_probe = ATA_PROBE_FAILED;
1593 ap->ap_type = ATA_PORT_T_NONE;
1594 ahci_port_stop(ap, 0);
1595 cmd = ahci_pread(ap, AHCI_PREG_CMD);
1596 cmd &= ~(AHCI_PREG_CMD_CLO | AHCI_PREG_CMD_PMA | AHCI_PREG_CMD_ICC);
1597 ahci_pwrite(ap, AHCI_PREG_CMD, cmd);
1600 * Clean up AT sub-ports on SATA port.
1602 for (i = 0; ap->ap_ata && i < AHCI_MAX_PMPORTS; ++i) {
1604 at->at_type = ATA_PORT_T_NONE;
1605 at->at_probe = ATA_PROBE_FAILED;
1609 * Make sure FRE is active. There isn't anything we can do if it
1610 * fails so just ignore errors.
1612 if ((cmd & AHCI_PREG_CMD_FRE) == 0) {
1613 cmd |= AHCI_PREG_CMD_FRE;
1614 ahci_pwrite(ap, AHCI_PREG_CMD, cmd);
1615 if ((ap->ap_sc->sc_flags & AHCI_F_IGN_FR) == 0)
1616 ahci_pwait_set(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_FR);
1620 * 10.10.3 DET must be set to 0 before setting SUD to 0.
1621 * 10.10.1 place us in the Listen state.
1623 * Deactivating SUD only applies if the controller supports SUD.
1625 ahci_pwrite(ap, AHCI_PREG_SCTL, AHCI_PREG_SCTL_IPM_DISABLED);
1627 if (cmd & AHCI_PREG_CMD_SUD) {
1628 cmd &= ~AHCI_PREG_CMD_SUD;
1629 ahci_pwrite(ap, AHCI_PREG_CMD, cmd);
1634 * Transition su to the spin-up state. HVA shall send COMRESET and
1635 * begin initialization sequence (whatever that means).
1637 * This only applies if the controller supports SUD.
1638 * NEVER use AHCI_PREG_DET_DISABLE.
1640 cmd |= AHCI_PREG_CMD_POD | AHCI_PREG_CMD_SUD;
1641 cmd |= AHCI_PREG_CMD_ICC_ACTIVE;
1642 ahci_pwrite(ap, AHCI_PREG_CMD, cmd);
1646 * Transition us to the Reset state. Theoretically we send a
1647 * continuous stream of COMRESETs in this state.
1649 r = AHCI_PREG_SCTL_IPM_DISABLED | AHCI_PREG_SCTL_DET_INIT;
1650 if (AhciForceGen1 & (1 << ap->ap_num)) {
1651 kprintf("%s: Force 1.5Gbits\n", PORTNAME(ap));
1652 r |= AHCI_PREG_SCTL_SPD_GEN1;
1654 r |= AHCI_PREG_SCTL_SPD_ANY;
1656 ahci_pwrite(ap, AHCI_PREG_SCTL, r);
1660 * Flush SERR_DIAG_X so the TFD can update.
1665 * Clean out pending ccbs
1667 while (ap->ap_active) {
1668 slot = ffs(ap->ap_active) - 1;
1669 ap->ap_active &= ~(1 << slot);
1670 ap->ap_expired &= ~(1 << slot);
1671 --ap->ap_active_cnt;
1672 ccb = &ap->ap_ccbs[slot];
1673 if (ccb->ccb_xa.flags & ATA_F_TIMEOUT_RUNNING) {
1674 callout_stop(&ccb->ccb_timeout);
1675 ccb->ccb_xa.flags &= ~ATA_F_TIMEOUT_RUNNING;
1677 ccb->ccb_xa.flags &= ~(ATA_F_TIMEOUT_DESIRED |
1678 ATA_F_TIMEOUT_EXPIRED);
1679 ccb->ccb_xa.state = ATA_S_TIMEOUT;
1681 ccb->ccb_xa.complete(&ccb->ccb_xa);
1683 while (ap->ap_sactive) {
1684 slot = ffs(ap->ap_sactive) - 1;
1685 ap->ap_sactive &= ~(1 << slot);
1686 ap->ap_expired &= ~(1 << slot);
1687 ccb = &ap->ap_ccbs[slot];
1688 if (ccb->ccb_xa.flags & ATA_F_TIMEOUT_RUNNING) {
1689 callout_stop(&ccb->ccb_timeout);
1690 ccb->ccb_xa.flags &= ~ATA_F_TIMEOUT_RUNNING;
1692 ccb->ccb_xa.flags &= ~(ATA_F_TIMEOUT_DESIRED |
1693 ATA_F_TIMEOUT_EXPIRED);
1694 ccb->ccb_xa.state = ATA_S_TIMEOUT;
1696 ccb->ccb_xa.complete(&ccb->ccb_xa);
1698 KKASSERT(ap->ap_active_cnt == 0);
1700 while ((ccb = TAILQ_FIRST(&ap->ap_ccb_pending)) != NULL) {
1701 TAILQ_REMOVE(&ap->ap_ccb_pending, ccb, ccb_entry);
1702 ccb->ccb_xa.state = ATA_S_TIMEOUT;
1703 ccb->ccb_xa.flags &= ~ATA_F_TIMEOUT_DESIRED;
1705 ccb->ccb_xa.complete(&ccb->ccb_xa);
1709 * Leave us in COMRESET (both SUD and INIT active), the HBA should
1710 * hopefully send us a DIAG_X-related interrupt if it receives
1711 * a COMINIT, and if not that then at least a Phy transition
1714 * If we transition INIT from 1->0 to begin the initalization
1715 * sequence it is unclear if that sequence will remain active
1716 * until the next device insertion.
1718 * If we go back to the listen state it is unclear if the
1719 * device will actually send us a COMINIT, since we aren't
1720 * sending any COMRESET's
1726 * We can't loop on the X bit, a continuous COMINIT received will make
1727 * it loop forever. Just assume one event has built up and clear X
1728 * so the task file descriptor can update.
1731 ahci_flush_tfd(struct ahci_port *ap)
1735 r = ahci_pread(ap, AHCI_PREG_SERR);
1736 if (r & AHCI_PREG_SERR_DIAG_X)
1737 ahci_pwrite(ap, AHCI_PREG_SERR, AHCI_PREG_SERR_DIAG_X);
1741 * Figure out what type of device is connected to the port, ATAPI or
1745 ahci_port_signature_detect(struct ahci_port *ap, struct ata_port *at)
1749 sig = ahci_pread(ap, AHCI_PREG_SIG);
1751 kprintf("%s: sig %08x\n", ATANAME(ap, at), sig);
1752 if ((sig & 0xffff0000) == (SATA_SIGNATURE_ATAPI & 0xffff0000)) {
1753 return(ATA_PORT_T_ATAPI);
1754 } else if ((sig & 0xffff0000) ==
1755 (SATA_SIGNATURE_PORT_MULTIPLIER & 0xffff0000)) {
1756 return(ATA_PORT_T_PM);
1758 return(ATA_PORT_T_DISK);
1763 * Load the DMA descriptor table for a CCB's buffer.
1766 ahci_load_prdt(struct ahci_ccb *ccb)
1768 struct ahci_port *ap = ccb->ccb_port;
1769 struct ahci_softc *sc = ap->ap_sc;
1770 struct ata_xfer *xa = &ccb->ccb_xa;
1771 struct ahci_prdt *prdt = ccb->ccb_cmd_table->prdt;
1772 bus_dmamap_t dmap = ccb->ccb_dmamap;
1773 struct ahci_cmd_hdr *cmd_slot = ccb->ccb_cmd_hdr;
1776 if (xa->datalen == 0) {
1777 ccb->ccb_cmd_hdr->prdtl = 0;
1781 error = bus_dmamap_load(sc->sc_tag_data, dmap,
1782 xa->data, xa->datalen,
1783 ahci_load_prdt_callback,
1785 ((xa->flags & ATA_F_NOWAIT) ?
1786 BUS_DMA_NOWAIT : BUS_DMA_WAITOK));
1788 kprintf("%s: error %d loading dmamap\n", PORTNAME(ap), error);
1792 if (xa->flags & ATA_F_PIO)
1793 prdt->flags |= htole32(AHCI_PRDT_FLAG_INTR);
1796 cmd_slot->prdtl = htole16(prdt - ccb->ccb_cmd_table->prdt + 1);
1798 if (xa->flags & ATA_F_READ)
1799 bus_dmamap_sync(sc->sc_tag_data, dmap, BUS_DMASYNC_PREREAD);
1800 if (xa->flags & ATA_F_WRITE)
1801 bus_dmamap_sync(sc->sc_tag_data, dmap, BUS_DMASYNC_PREWRITE);
1807 * Callback from BUSDMA system to load the segment list. The passed segment
1808 * list is a temporary structure.
1812 ahci_load_prdt_callback(void *info, bus_dma_segment_t *segs, int nsegs,
1815 struct ahci_prdt *prd = *(void **)info;
1818 KKASSERT(nsegs <= AHCI_MAX_PRDT);
1821 addr = segs->ds_addr;
1822 prd->dba_hi = htole32((u_int32_t)(addr >> 32));
1823 prd->dba_lo = htole32((u_int32_t)addr);
1824 prd->flags = htole32(segs->ds_len - 1);
1830 *(void **)info = prd; /* return last valid segment */
1834 ahci_unload_prdt(struct ahci_ccb *ccb)
1836 struct ahci_port *ap = ccb->ccb_port;
1837 struct ahci_softc *sc = ap->ap_sc;
1838 struct ata_xfer *xa = &ccb->ccb_xa;
1839 bus_dmamap_t dmap = ccb->ccb_dmamap;
1841 if (xa->datalen != 0) {
1842 if (xa->flags & ATA_F_READ) {
1843 bus_dmamap_sync(sc->sc_tag_data, dmap,
1844 BUS_DMASYNC_POSTREAD);
1846 if (xa->flags & ATA_F_WRITE) {
1847 bus_dmamap_sync(sc->sc_tag_data, dmap,
1848 BUS_DMASYNC_POSTWRITE);
1850 bus_dmamap_unload(sc->sc_tag_data, dmap);
1853 * prdbc is only updated by hardware for non-NCQ commands.
1855 if (ccb->ccb_xa.flags & ATA_F_NCQ) {
1858 if (ccb->ccb_cmd_hdr->prdbc == 0 &&
1859 ccb->ccb_xa.state == ATA_S_COMPLETE) {
1860 kprintf("%s: WARNING! Unload prdbc resid "
1861 "was zero! tag=%d\n",
1862 ATANAME(ap, xa->at), ccb->ccb_slot);
1864 xa->resid = xa->datalen -
1865 le32toh(ccb->ccb_cmd_hdr->prdbc);
1871 * Start a command and poll for completion.
1873 * timeout is in ms and only counts once the command gets on-chip.
1875 * Returns ATA_S_* state, compare against ATA_S_COMPLETE to determine
1876 * that no error occured.
1878 * NOTE: If the caller specifies a NULL timeout function the caller is
1879 * responsible for clearing hardware state on failure, but we will
1880 * deal with removing the ccb from any pending queue.
1882 * NOTE: NCQ should never be used with this function.
1884 * NOTE: If the port is in a failed state and stopped we do not try
1885 * to activate the ccb.
1888 ahci_poll(struct ahci_ccb *ccb, int timeout,
1889 void (*timeout_fn)(struct ahci_ccb *))
1891 struct ahci_port *ap = ccb->ccb_port;
1893 if (ccb->ccb_port->ap_state == AP_S_FATAL_ERROR) {
1894 ccb->ccb_xa.state = ATA_S_ERROR;
1895 return(ccb->ccb_xa.state);
1899 kprintf("%s: Start command %02x tag=%d\n",
1900 ATANAME(ccb->ccb_port, ccb->ccb_xa.at),
1901 ccb->ccb_xa.fis->command, ccb->ccb_slot);
1906 ahci_port_intr(ap, 1);
1907 switch(ccb->ccb_xa.state) {
1909 timeout -= ahci_os_softsleep();
1912 ahci_os_softsleep();
1913 ahci_check_active_timeouts(ap);
1917 return (ccb->ccb_xa.state);
1919 } while (timeout > 0);
1921 if ((ccb->ccb_xa.flags & ATA_F_SILENT) == 0) {
1922 kprintf("%s: Poll timeout slot %d CMD: %b TFD: 0x%b SERR: %b\n",
1923 ATANAME(ap, ccb->ccb_xa.at), ccb->ccb_slot,
1924 ahci_pread(ap, AHCI_PREG_CMD), AHCI_PFMT_CMD,
1925 ahci_pread(ap, AHCI_PREG_TFD), AHCI_PFMT_TFD_STS,
1926 ahci_pread(ap, AHCI_PREG_SERR), AHCI_PFMT_SERR);
1933 return(ccb->ccb_xa.state);
1937 * When polling we have to check if the currently active CCB(s)
1938 * have timed out as the callout will be deadlocked while we
1939 * hold the port lock.
1942 ahci_check_active_timeouts(struct ahci_port *ap)
1944 struct ahci_ccb *ccb;
1948 mask = ap->ap_active | ap->ap_sactive;
1950 tag = ffs(mask) - 1;
1951 mask &= ~(1 << tag);
1952 ccb = &ap->ap_ccbs[tag];
1953 if (ccb->ccb_xa.flags & ATA_F_TIMEOUT_EXPIRED) {
1954 ahci_ata_cmd_timeout(ccb);
1962 ahci_start_timeout(struct ahci_ccb *ccb)
1964 if (ccb->ccb_xa.flags & ATA_F_TIMEOUT_DESIRED) {
1965 ccb->ccb_xa.flags |= ATA_F_TIMEOUT_RUNNING;
1966 callout_reset(&ccb->ccb_timeout,
1967 (ccb->ccb_xa.timeout * hz + 999) / 1000,
1968 ahci_ata_cmd_timeout_unserialized, ccb);
1973 ahci_start(struct ahci_ccb *ccb)
1975 struct ahci_port *ap = ccb->ccb_port;
1976 struct ahci_softc *sc = ap->ap_sc;
1978 KKASSERT(ccb->ccb_xa.state == ATA_S_PENDING);
1980 /* Zero transferred byte count before transfer */
1981 ccb->ccb_cmd_hdr->prdbc = 0;
1983 /* Sync command list entry and corresponding command table entry */
1984 bus_dmamap_sync(sc->sc_tag_cmdh,
1985 AHCI_DMA_MAP(ap->ap_dmamem_cmd_list),
1986 BUS_DMASYNC_PREWRITE);
1987 bus_dmamap_sync(sc->sc_tag_cmdt,
1988 AHCI_DMA_MAP(ap->ap_dmamem_cmd_table),
1989 BUS_DMASYNC_PREWRITE);
1991 /* Prepare RFIS area for write by controller */
1992 bus_dmamap_sync(sc->sc_tag_rfis,
1993 AHCI_DMA_MAP(ap->ap_dmamem_rfis),
1994 BUS_DMASYNC_PREREAD);
1997 * There's no point trying to optimize this, it only shaves a few
1998 * nanoseconds so just queue the command and call our generic issue.
2000 ahci_issue_pending_commands(ap, ccb);
2004 * While holding the port lock acquire exclusive access to the port.
2006 * This is used when running the state machine to initialize and identify
2007 * targets over a port multiplier. Setting exclusive access prevents
2008 * ahci_port_intr() from activating any requests sitting on the pending
2012 ahci_beg_exclusive_access(struct ahci_port *ap, struct ata_port *at)
2014 KKASSERT((ap->ap_flags & AP_F_EXCLUSIVE_ACCESS) == 0);
2015 ap->ap_flags |= AP_F_EXCLUSIVE_ACCESS;
2016 while (ap->ap_active || ap->ap_sactive) {
2017 ahci_port_intr(ap, 1);
2018 ahci_os_softsleep();
2023 ahci_end_exclusive_access(struct ahci_port *ap, struct ata_port *at)
2025 KKASSERT((ap->ap_flags & AP_F_EXCLUSIVE_ACCESS) != 0);
2026 ap->ap_flags &= ~AP_F_EXCLUSIVE_ACCESS;
2027 ahci_issue_pending_commands(ap, NULL);
2033 fubar(struct ahci_ccb *ccb)
2035 struct ahci_port *ap = ccb->ccb_port;
2036 struct ahci_cmd_hdr *cmd;
2037 struct ahci_cmd_table *tab;
2038 struct ahci_prdt *prdt;
2041 kprintf("%s: ISSUE %02x\n",
2042 ATANAME(ap, ccb->ccb_xa.at),
2043 ccb->ccb_xa.fis->command);
2044 cmd = ccb->ccb_cmd_hdr;
2045 tab = ccb->ccb_cmd_table;
2046 prdt = ccb->ccb_cmd_table->prdt;
2047 kprintf("cmd flags=%04x prdtl=%d prdbc=%d ctba=%08x%08x\n",
2048 cmd->flags, cmd->prdtl, cmd->prdbc,
2049 cmd->ctba_hi, cmd->ctba_lo);
2050 for (i = 0; i < cmd->prdtl; ++i) {
2051 kprintf("\t%d dba=%08x%08x res=%08x flags=%08x\n",
2052 i, prdt->dba_hi, prdt->dba_lo, prdt->reserved,
2061 * If ccb is not NULL enqueue and/or issue it.
2063 * If ccb is NULL issue whatever we can from the queue. However, nothing
2064 * new is issued if the exclusive access flag is set or expired ccb's are
2067 * If existing commands are still active (ap_active/ap_sactive) we can only
2068 * issue matching new commands.
2071 ahci_issue_pending_commands(struct ahci_port *ap, struct ahci_ccb *ccb)
2079 * If just running the queue and in exclusive access mode we
2080 * just return. Also in this case if there are any expired ccb's
2081 * we want to clear the queue so the port can be safely stopped.
2084 TAILQ_INSERT_TAIL(&ap->ap_ccb_pending, ccb, ccb_entry);
2085 } else if ((ap->ap_flags & AP_F_EXCLUSIVE_ACCESS) || ap->ap_expired) {
2090 * Pull the next ccb off the queue and run it if possible.
2092 if ((ccb = TAILQ_FIRST(&ap->ap_ccb_pending)) == NULL)
2096 * Handle exclusivity requirements.
2098 * ATA_F_EXCLUSIVE is used when we want to be the only command
2101 * ATA_F_AUTOSENSE is used when we want the D2H rfis loaded
2102 * back into the ccb on a normal (non-errored) command completion.
2103 * For example, for PM requests to target 15. Because the AHCI
2104 * spec does not stop the command processor and has only one rfis
2105 * area (for non-FBSS anyway), AUTOSENSE currently implies EXCLUSIVE.
2106 * Otherwise multiple completions can destroy the rfis data before
2107 * we have a chance to copy it.
2109 if (ap->ap_active & ~ap->ap_expired) {
2111 * There may be multiple ccb's already running,
2112 * if any are running and ap_run_flags sets
2113 * one of these flags then we know only one is
2116 * XXX Current AUTOSENSE code forces exclusivity
2117 * to simplify the code.
2119 if (ap->ap_run_flags &
2120 (ATA_F_EXCLUSIVE | ATA_F_AUTOSENSE)) {
2124 if (ccb->ccb_xa.flags &
2125 (ATA_F_EXCLUSIVE | ATA_F_AUTOSENSE)) {
2130 if (ccb->ccb_xa.flags & ATA_F_NCQ) {
2132 * The next command is a NCQ command and can be issued as
2133 * long as currently active commands are not standard.
2135 if (ap->ap_active) {
2136 KKASSERT(ap->ap_active_cnt > 0);
2139 KKASSERT(ap->ap_active_cnt == 0);
2143 TAILQ_REMOVE(&ap->ap_ccb_pending, ccb, ccb_entry);
2144 mask |= 1 << ccb->ccb_slot;
2145 ccb->ccb_xa.state = ATA_S_ONCHIP;
2146 ahci_start_timeout(ccb);
2147 ap->ap_run_flags = ccb->ccb_xa.flags;
2148 ccb = TAILQ_FIRST(&ap->ap_ccb_pending);
2149 } while (ccb && (ccb->ccb_xa.flags & ATA_F_NCQ) &&
2151 (ATA_F_EXCLUSIVE | ATA_F_AUTOSENSE)) == 0);
2153 ap->ap_sactive |= mask;
2154 ahci_pwrite(ap, AHCI_PREG_SACT, mask);
2155 ahci_pwrite(ap, AHCI_PREG_CI, mask);
2158 * The next command is a standard command and can be issued
2159 * as long as currently active commands are not NCQ.
2161 * We limit ourself to 1 command if we have a port multiplier,
2162 * (at least without FBSS support), otherwise timeouts on
2163 * one port can race completions on other ports (see
2164 * ahci_ata_cmd_timeout() for more information).
2166 * If not on a port multiplier generally allow up to 4
2167 * standard commands to be enqueued. Remember that the
2168 * command processor will still process them sequentially.
2172 if (ap->ap_type == ATA_PORT_T_PM)
2174 else if (ap->ap_sc->sc_ncmds > 4)
2179 while (ap->ap_active_cnt < limit && ccb &&
2180 (ccb->ccb_xa.flags & ATA_F_NCQ) == 0) {
2181 TAILQ_REMOVE(&ap->ap_ccb_pending, ccb, ccb_entry);
2185 ap->ap_active |= 1 << ccb->ccb_slot;
2186 ap->ap_active_cnt++;
2187 ap->ap_run_flags = ccb->ccb_xa.flags;
2188 ccb->ccb_xa.state = ATA_S_ONCHIP;
2189 ahci_pwrite(ap, AHCI_PREG_CI, 1 << ccb->ccb_slot);
2190 ahci_start_timeout(ccb);
2191 if ((ap->ap_run_flags &
2192 (ATA_F_EXCLUSIVE | ATA_F_AUTOSENSE)) == 0) {
2195 ccb = TAILQ_FIRST(&ap->ap_ccb_pending);
2196 if (ccb && (ccb->ccb_xa.flags &
2197 (ATA_F_EXCLUSIVE | ATA_F_AUTOSENSE))) {
2205 ahci_intr(void *arg)
2207 struct ahci_softc *sc = arg;
2208 struct ahci_port *ap;
2214 * Check if the master enable is up, and whether any interrupts are
2217 if ((sc->sc_flags & AHCI_F_INT_GOOD) == 0)
2219 is = ahci_read(sc, AHCI_REG_IS);
2220 if (is == 0 || is == 0xffffffff) {
2223 is &= sc->sc_portmask;
2225 #ifdef AHCI_COALESCE
2226 /* Check coalescing interrupt first */
2227 if (is & sc->sc_ccc_mask) {
2228 DPRINTF(AHCI_D_INTR, "%s: command coalescing interrupt\n",
2230 is &= ~sc->sc_ccc_mask;
2231 is |= sc->sc_ccc_ports_cur;
2236 * Process interrupts for each port in a non-blocking fashion.
2238 * The global IS bit is forced on if any unmasked port interrupts
2239 * are pending, even if we clear.
2241 for (ack = 0; is; is &= ~(1 << port)) {
2245 ap = sc->sc_ports[port];
2249 if (ahci_os_lock_port_nb(ap) == 0) {
2250 ahci_port_intr(ap, 0);
2251 ahci_os_unlock_port(ap);
2253 ahci_pwrite(ap, AHCI_PREG_IE, 0);
2254 ahci_os_signal_port_thread(ap, AP_SIGF_PORTINT);
2257 ahci_write(sc, AHCI_REG_IS, ack);
2261 * Core called from helper thread.
2264 ahci_port_thread_core(struct ahci_port *ap, int mask)
2267 * Process any expired timedouts.
2269 ahci_os_lock_port(ap);
2270 if (mask & AP_SIGF_TIMEOUT) {
2271 ahci_check_active_timeouts(ap);
2275 * Process port interrupts which require a higher level of
2278 if (mask & AP_SIGF_PORTINT) {
2279 ahci_port_intr(ap, 1);
2280 ahci_port_interrupt_enable(ap);
2281 ahci_os_unlock_port(ap);
2282 } else if (ap->ap_probe != ATA_PROBE_FAILED) {
2283 ahci_port_intr(ap, 1);
2284 ahci_port_interrupt_enable(ap);
2285 ahci_os_unlock_port(ap);
2287 ahci_os_unlock_port(ap);
2292 * Core per-port interrupt handler.
2294 * If blockable is 0 we cannot call ahci_os_sleep() at all and we can only
2295 * deal with normal command completions which do not require blocking.
2298 ahci_port_intr(struct ahci_port *ap, int blockable)
2300 struct ahci_softc *sc = ap->ap_sc;
2301 u_int32_t is, ci_saved, ci_masked;
2304 struct ahci_ccb *ccb = NULL;
2305 struct ata_port *ccb_at = NULL;
2306 volatile u_int32_t *active;
2307 const u_int32_t blockable_mask = AHCI_PREG_IS_TFES |
2315 enum { NEED_NOTHING, NEED_REINIT, NEED_RESTART,
2316 NEED_HOTPLUG_INSERT, NEED_HOTPLUG_REMOVE } need = NEED_NOTHING;
2319 * All basic command completions are always processed.
2321 is = ahci_pread(ap, AHCI_PREG_IS);
2322 if (is & AHCI_PREG_IS_DPS)
2323 ahci_pwrite(ap, AHCI_PREG_IS, is & AHCI_PREG_IS_DPS);
2326 * If we can't block then we can't handle these here. Disable
2327 * the interrupts in question so we don't live-lock, the helper
2328 * thread will re-enable them.
2330 * If the port is in a completely failed state we do not want
2331 * to drop through to failed-command-processing if blockable is 0,
2332 * just let the thread deal with it all.
2334 * Otherwise we fall through and still handle DHRS and any commands
2335 * which completed normally. Even if we are errored we haven't
2336 * stopped the port yet so CI/SACT are still good.
2338 if (blockable == 0) {
2339 if (ap->ap_state == AP_S_FATAL_ERROR) {
2340 ahci_pwrite(ap, AHCI_PREG_IE, 0);
2341 ahci_os_signal_port_thread(ap, AP_SIGF_PORTINT);
2344 if (is & blockable_mask) {
2345 ahci_pwrite(ap, AHCI_PREG_IE, 0);
2346 ahci_os_signal_port_thread(ap, AP_SIGF_PORTINT);
2352 * Either NCQ or non-NCQ commands will be active, never both.
2354 if (ap->ap_sactive) {
2355 KKASSERT(ap->ap_active == 0);
2356 KKASSERT(ap->ap_active_cnt == 0);
2357 ci_saved = ahci_pread(ap, AHCI_PREG_SACT);
2358 active = &ap->ap_sactive;
2360 ci_saved = ahci_pread(ap, AHCI_PREG_CI);
2361 active = &ap->ap_active;
2363 KKASSERT(!(ap->ap_sactive && ap->ap_active));
2365 kprintf("CHECK act=%08x/%08x sact=%08x/%08x\n",
2366 ap->ap_active, ahci_pread(ap, AHCI_PREG_CI),
2367 ap->ap_sactive, ahci_pread(ap, AHCI_PREG_SACT));
2371 * Ignore AHCI_PREG_IS_PRCS when link power management is on
2373 if (ap->link_pwr_mgmt != AHCI_LINK_PWR_MGMT_NONE) {
2374 is &= ~AHCI_PREG_IS_PRCS;
2375 ahci_pwrite(ap, AHCI_PREG_SERR,
2376 AHCI_PREG_SERR_DIAG_N | AHCI_PREG_SERR_DIAG_W);
2380 * Command failed (blockable).
2382 * See AHCI 1.1 spec 6.2.2.1 and 6.2.2.2.
2384 * This stops command processing.
2386 if (is & AHCI_PREG_IS_TFES) {
2387 u_int32_t tfd, serr;
2391 tfd = ahci_pread(ap, AHCI_PREG_TFD);
2392 serr = ahci_pread(ap, AHCI_PREG_SERR);
2395 * Load the error slot and restart command processing.
2396 * CLO if we need to. The error slot may not be valid.
2397 * MUST BE DONE BEFORE CLEARING ST!
2401 * It is unclear but we may have to clear SERR to reenable
2404 err_slot = AHCI_PREG_CMD_CCS(ahci_pread(ap, AHCI_PREG_CMD));
2405 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_TFES |
2409 is &= ~(AHCI_PREG_IS_TFES | AHCI_PREG_IS_PSS |
2410 AHCI_PREG_IS_DHRS | AHCI_PREG_IS_SDBS);
2411 ahci_pwrite(ap, AHCI_PREG_SERR, serr);
2412 ahci_port_stop(ap, 0);
2413 ahci_os_hardsleep(10);
2414 if (tfd & (AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) {
2415 kprintf("%s: Issuing CLO\n", PORTNAME(ap));
2420 * We are now stopped and need a restart. If we have to
2421 * process a NCQ error we will temporarily start and then
2422 * stop the port again, so this condition holds.
2425 need = NEED_RESTART;
2428 * ATAPI errors are fairly common from probing, just
2429 * report disk errors or if bootverbose is on.
2431 if (bootverbose || ap->ap_type != ATA_PORT_T_ATAPI) {
2432 kprintf("%s: TFES slot %d ci_saved = %08x\n",
2433 PORTNAME(ap), err_slot, ci_saved);
2437 * If we got an error on an error CCB just complete it
2438 * with an error. ci_saved has the mask to restart
2439 * (the err_ccb will be removed from it by finish_error).
2441 if (ap->ap_flags & AP_F_ERR_CCB_RESERVED) {
2442 err_slot = ap->ap_err_ccb->ccb_slot;
2447 * If NCQ commands were active get the error slot from
2448 * the log page. NCQ is not supported for PM's so this
2449 * is a direct-attached target.
2451 * Otherwise if no commands were active we have a problem.
2453 * Otherwise if the error slot is bad we have a problem.
2455 * Otherwise process the error for the slot.
2457 if (ap->ap_sactive) {
2458 ahci_port_start(ap);
2459 err_slot = ahci_port_read_ncq_error(ap, 0);
2460 ahci_port_stop(ap, 0);
2461 } else if (ap->ap_active == 0) {
2462 kprintf("%s: TFES with no commands pending\n",
2465 } else if (err_slot < 0 || err_slot >= ap->ap_sc->sc_ncmds) {
2466 kprintf("%s: bad error slot %d\n",
2467 PORTNAME(ap), err_slot);
2470 ccb = &ap->ap_ccbs[err_slot];
2473 * Validate the errored ccb. Note that ccb_at can
2474 * be NULL for direct-attached ccb's.
2476 * Copy received taskfile data from the RFIS.
2478 if (ccb->ccb_xa.state == ATA_S_ONCHIP) {
2479 ccb_at = ccb->ccb_xa.at;
2480 memcpy(&ccb->ccb_xa.rfis, ap->ap_rfis->rfis,
2481 sizeof(struct ata_fis_d2h));
2483 kprintf("%s: Copying rfis slot %d\n",
2484 ATANAME(ap, ccb_at), err_slot);
2487 kprintf("%s: Cannot copy rfis, CCB slot "
2488 "%d is not on-chip (state=%d)\n",
2489 ATANAME(ap, ccb->ccb_xa.at),
2490 err_slot, ccb->ccb_xa.state);
2496 * If we could not determine the errored slot then
2500 kprintf("%s: TFES: Unable to determine errored slot\n",
2502 if (ap->ap_flags & AP_F_IN_RESET)
2508 * Finish error on slot. We will restart ci_saved
2509 * commands except the errored slot which we generate
2513 ccb = &ap->ap_ccbs[err_slot];
2514 ci_saved &= ~(1 << err_slot);
2515 KKASSERT(ccb->ccb_xa.state == ATA_S_ONCHIP);
2516 ccb->ccb_xa.state = ATA_S_ERROR;
2517 } else if (is & AHCI_PREG_IS_DHRS) {
2519 * Command posted D2H register FIS to the rfis (non-blocking).
2521 * A normal completion with an error may set DHRS instead
2522 * of TFES. The CCS bits are only valid if ERR was set.
2523 * If ERR is set command processing was probably stopped.
2525 * If ERR was not set we can only copy-back data for
2526 * exclusive-mode commands because otherwise we won't know
2527 * which tag the rfis belonged to.
2529 * err_slot must be read from the CCS before any other port
2530 * action, such as stopping the port.
2532 * WARNING! This is not well documented in the AHCI spec.
2533 * It can be found in the state machine tables
2534 * but not in the explanations.
2540 tfd = ahci_pread(ap, AHCI_PREG_TFD);
2541 cmd = ahci_pread(ap, AHCI_PREG_CMD);
2543 if ((tfd & AHCI_PREG_TFD_STS_ERR) &&
2544 (cmd & AHCI_PREG_CMD_CR) == 0) {
2545 err_slot = AHCI_PREG_CMD_CCS(
2546 ahci_pread(ap, AHCI_PREG_CMD));
2547 ccb = &ap->ap_ccbs[err_slot];
2548 kprintf("%s: DHRS tfd=%b err_slot=%d cmd=%02x\n",
2550 tfd, AHCI_PFMT_TFD_STS,
2551 err_slot, ccb->ccb_xa.fis->command);
2555 * NO ELSE... copy back is in the normal command completion
2556 * code and only if no error occured and ATA_F_AUTOSENSE
2559 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_DHRS);
2563 * Device notification to us (non-blocking)
2565 * NOTE! On some parts notification bits can cause an IPMS
2566 * interrupt instead of a SDBS interrupt.
2568 * NOTE! On some parts (e.g. VBOX, probably intel ICHx),
2569 * SDBS notifies us of the completion of a NCQ command
2572 if (is & (AHCI_PREG_IS_SDBS | AHCI_PREG_IS_IPMS)) {
2575 ahci_pwrite(ap, AHCI_PREG_IS,
2576 AHCI_PREG_IS_SDBS | AHCI_PREG_IS_IPMS);
2577 if (sc->sc_cap & AHCI_REG_CAP_SSNTF) {
2578 data = ahci_pread(ap, AHCI_PREG_SNTF);
2580 ahci_pwrite(ap, AHCI_PREG_IS,
2582 kprintf("%s: NOTIFY %08x\n",
2583 PORTNAME(ap), data);
2584 ahci_pwrite(ap, AHCI_PREG_SERR,
2585 AHCI_PREG_SERR_DIAG_N);
2586 ahci_pwrite(ap, AHCI_PREG_SNTF, data);
2587 ahci_cam_changed(ap, NULL, -1);
2590 is &= ~(AHCI_PREG_IS_SDBS | AHCI_PREG_IS_IPMS);
2594 * Spurious IFS errors (blockable) - when AP_F_IGNORE_IFS is set.
2596 * Spurious IFS errors can occur while we are doing a reset
2597 * sequence through a PM, probably due to an unexpected FIS
2598 * being received during the PM target reset sequence. Chipsets
2599 * are supposed to mask these events but some do not.
2601 * Try to recover from the condition.
2603 if ((is & AHCI_PREG_IS_IFS) && (ap->ap_flags & AP_F_IGNORE_IFS)) {
2604 u_int32_t serr = ahci_pread(ap, AHCI_PREG_SERR);
2605 if ((ap->ap_flags & AP_F_IFS_IGNORED) == 0) {
2606 kprintf("%s: IFS during PM probe (ignored) "
2610 serr, AHCI_PFMT_SERR);
2611 ap->ap_flags |= AP_F_IFS_IGNORED;
2615 * Try to clear the error condition. The IFS error killed
2616 * the port so stop it so we can restart it.
2618 ahci_pwrite(ap, AHCI_PREG_SERR, -1);
2619 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_IFS);
2620 is &= ~AHCI_PREG_IS_IFS;
2621 need = NEED_RESTART;
2626 * Port change (hot-plug) (blockable).
2628 * A PRCS interrupt can occur:
2629 * (1) On hot-unplug / normal-unplug (phy lost)
2630 * (2) Sometimes on hot-plug too.
2632 * A PCS interrupt can occur in a number of situations:
2633 * (1) On hot-plug once communication is established
2634 * (2) On hot-unplug sometimes.
2635 * (3) For chipsets with badly written firmware it can occur
2636 * during INIT/RESET sequences due to the device reset.
2637 * (4) For chipsets with badly written firmware it can occur
2638 * when it thinks an unsolicited COMRESET is received
2639 * during a INIT/RESET sequence, even though we actually
2642 * XXX We can then check the CPS (Cold Presence State) bit, if
2643 * supported, to determine if a device is plugged in or not and do
2646 * PCS interrupts are cleared by clearing DIAG_X. If this occurs
2647 * command processing is automatically stopped (CR goes inactive)
2648 * and the port must be stopped and restarted.
2650 * WARNING: AMD parts (e.g. 880G chipset, probably others) can
2651 * generate PCS on initialization even when device is
2652 * already connected up. It is unclear why this happens.
2653 * Depending on the state of the device detect this can
2654 * cause us to go into harsh reinit or hot-plug insertion
2657 * WARNING: PCS errors can be repetitive (e.g. unsolicited COMRESET
2658 * continues to flow in from the device), we must clear the
2659 * interrupt in all cases and enforce a delay to prevent
2660 * a livelock and give the port time to settle down.
2661 * Only print something if we aren't in INIT/HARD-RESET.
2663 if (is & (AHCI_PREG_IS_PCS | AHCI_PREG_IS_PRCS)) {
2665 * Try to clear the error. Because of the repetitiveness
2666 * of this interrupt avoid any harsh action if the port is
2667 * already in the init or hard-reset probe state.
2669 ahci_pwrite(ap, AHCI_PREG_SERR, -1);
2670 /* (AHCI_PREG_SERR_DIAG_N | AHCI_PREG_SERR_DIAG_X) */
2671 ahci_pwrite(ap, AHCI_PREG_IS,
2672 is & (AHCI_PREG_IS_PCS | AHCI_PREG_IS_PRCS));
2674 if (ap->ap_probe == ATA_PROBE_NEED_INIT ||
2675 ap->ap_probe == ATA_PROBE_NEED_HARD_RESET) {
2676 is &= ~(AHCI_PREG_IS_PCS | AHCI_PREG_IS_PRCS);
2677 need = NEED_NOTHING;
2678 ahci_os_sleep(1000);
2681 kprintf("%s: Transient Errors: %b (%d)\n",
2682 PORTNAME(ap), is, AHCI_PFMT_IS, ap->ap_probe);
2683 is &= ~(AHCI_PREG_IS_PCS | AHCI_PREG_IS_PRCS);
2687 * Stop the port and figure out what to do next.
2689 ahci_port_stop(ap, 0);
2692 switch (ahci_pread(ap, AHCI_PREG_SSTS) & AHCI_PREG_SSTS_DET) {
2693 case AHCI_PREG_SSTS_DET_DEV:
2697 if (ap->ap_probe == ATA_PROBE_FAILED) {
2698 need = NEED_HOTPLUG_INSERT;
2701 need = NEED_RESTART;
2703 case AHCI_PREG_SSTS_DET_DEV_NE:
2705 * Device not communicating. AMD parts seem to
2706 * like to throw this error on initialization
2707 * for no reason that I can fathom.
2709 kprintf("%s: Device present but not communicating, "
2710 "attempting port restart\n",
2715 if (ap->ap_probe != ATA_PROBE_FAILED) {
2716 need = NEED_HOTPLUG_REMOVE;
2719 need = NEED_RESTART;
2725 * Check for remaining errors - they are fatal. (blockable)
2727 if (is & (AHCI_PREG_IS_TFES | AHCI_PREG_IS_HBFS | AHCI_PREG_IS_IFS |
2728 AHCI_PREG_IS_OFS | AHCI_PREG_IS_UFS)) {
2731 ahci_pwrite(ap, AHCI_PREG_IS,
2732 is & (AHCI_PREG_IS_TFES | AHCI_PREG_IS_HBFS |
2733 AHCI_PREG_IS_IFS | AHCI_PREG_IS_OFS |
2735 serr = ahci_pread(ap, AHCI_PREG_SERR);
2736 kprintf("%s: Unrecoverable errors (IS: %b, SERR: %b), "
2737 "disabling port.\n",
2740 serr, AHCI_PFMT_SERR
2742 is &= ~(AHCI_PREG_IS_TFES | AHCI_PREG_IS_HBFS |
2743 AHCI_PREG_IS_IFS | AHCI_PREG_IS_OFS |
2747 * Fail all commands but then what? For now try to
2748 * reinitialize the port.
2755 * Fail all outstanding commands if we know the port won't recover.
2757 * We may have a ccb_at if the failed command is known and was
2758 * being sent to a device over a port multiplier (PM). In this
2759 * case if the port itself has not completely failed we fail just
2760 * the commands related to that target.
2762 * ci_saved contains the mask of active commands as of when the
2763 * error occured, prior to any port stops.
2765 if (ap->ap_state == AP_S_FATAL_ERROR) {
2767 ap->ap_state = AP_S_FATAL_ERROR;
2769 ahci_port_stop(ap, 0);
2773 * Error all the active slots not already errored.
2775 ci_masked = ci_saved & *active & ~ap->ap_expired;
2777 kprintf("%s: Failing all commands: %08x\n",
2778 PORTNAME(ap), ci_masked);
2782 slot = ffs(ci_masked) - 1;
2783 ccb = &ap->ap_ccbs[slot];
2784 ccb->ccb_xa.state = ATA_S_TIMEOUT;
2785 ap->ap_expired |= 1 << slot;
2786 ci_saved &= ~(1 << slot);
2787 ci_masked &= ~(1 << slot);
2791 * Clear bits in ci_saved (cause completions to be run)
2792 * for all slots which are not active.
2794 ci_saved &= ~*active;
2797 * Don't restart the port if our problems were deemed fatal.
2799 * Also acknowlege all fatal interrupt sources to prevent
2802 if (ap->ap_state == AP_S_FATAL_ERROR) {
2803 if (need == NEED_RESTART)
2804 need = NEED_NOTHING;
2805 ahci_pwrite(ap, AHCI_PREG_IS,
2806 AHCI_PREG_IS_TFES | AHCI_PREG_IS_HBFS |
2807 AHCI_PREG_IS_IFS | AHCI_PREG_IS_OFS |
2813 * If we are stopped the AHCI chipset is supposed to have cleared
2814 * CI and SACT. Did it? If it didn't we try very hard to clear
2815 * the fields otherwise we may end up completing CCBs which are
2816 * actually still active.
2818 * IFS errors on (at least) AMD chipsets create this confusion.
2822 if ((mask = ahci_pactive(ap)) != 0) {
2823 kprintf("%s: chipset failed to clear "
2824 "active cmds %08x\n",
2825 PORTNAME(ap), mask);
2826 ahci_port_start(ap);
2827 ahci_port_stop(ap, 0);
2828 if ((mask = ahci_pactive(ap)) != 0) {
2829 kprintf("%s: unable to prod the chip into "
2830 "clearing active cmds %08x\n",
2831 PORTNAME(ap), mask);
2832 /* what do we do now? */
2838 * CCB completion (non blocking).
2840 * CCB completion is detected by noticing its slot's bit in CI has
2841 * changed to zero some time after we activated it.
2842 * If we are polling, we may only be interested in particular slot(s).
2844 * Any active bits not saved are completed within the restrictions
2845 * imposed by the caller.
2847 ci_masked = ~ci_saved & *active;
2849 slot = ffs(ci_masked) - 1;
2850 ccb = &ap->ap_ccbs[slot];
2851 ci_masked &= ~(1 << slot);
2853 DPRINTF(AHCI_D_INTR, "%s: slot %d is complete%s\n",
2854 PORTNAME(ap), slot, ccb->ccb_xa.state == ATA_S_ERROR ?
2857 bus_dmamap_sync(sc->sc_tag_cmdh,
2858 AHCI_DMA_MAP(ap->ap_dmamem_cmd_list),
2859 BUS_DMASYNC_POSTWRITE);
2861 bus_dmamap_sync(sc->sc_tag_cmdt,
2862 AHCI_DMA_MAP(ap->ap_dmamem_cmd_table),
2863 BUS_DMASYNC_POSTWRITE);
2865 bus_dmamap_sync(sc->sc_tag_rfis,
2866 AHCI_DMA_MAP(ap->ap_dmamem_rfis),
2867 BUS_DMASYNC_POSTREAD);
2869 *active &= ~(1 << ccb->ccb_slot);
2870 if (active == &ap->ap_active) {
2871 KKASSERT(ap->ap_active_cnt > 0);
2872 --ap->ap_active_cnt;
2876 * Complete the ccb. If the ccb was marked expired it
2877 * was probably already removed from the command processor,
2878 * so don't take the clear ci_saved bit as meaning the
2879 * command actually succeeded, it didn't.
2881 if (ap->ap_expired & (1 << ccb->ccb_slot)) {
2882 ap->ap_expired &= ~(1 << ccb->ccb_slot);
2883 ccb->ccb_xa.state = ATA_S_TIMEOUT;
2885 ccb->ccb_xa.complete(&ccb->ccb_xa);
2887 if (ccb->ccb_xa.state == ATA_S_ONCHIP) {
2888 ccb->ccb_xa.state = ATA_S_COMPLETE;
2889 if (ccb->ccb_xa.flags & ATA_F_AUTOSENSE) {
2890 memcpy(&ccb->ccb_xa.rfis,
2892 sizeof(struct ata_fis_d2h));
2893 if (ccb->ccb_xa.state == ATA_S_TIMEOUT)
2894 ccb->ccb_xa.state = ATA_S_ERROR;
2902 * Cleanup. Will not be set if non-blocking.
2907 * A recoverable error occured and we can restart outstanding
2908 * commands on the port.
2910 ci_saved &= ~ap->ap_expired;
2912 kprintf("%s: Restart %08x\n", PORTNAME(ap), ci_saved);
2913 ahci_issue_saved_commands(ap, ci_saved);
2917 * Potentially issue new commands if not in a failed
2920 if (ap->ap_state != AP_S_FATAL_ERROR) {
2921 ahci_port_start(ap);
2922 ahci_issue_pending_commands(ap, NULL);
2927 * Something horrible happened to the port and we
2928 * need to reinitialize it.
2930 kprintf("%s: REINIT - Attempting to reinitialize the port "
2931 "after it had a horrible accident\n",
2933 ap->ap_flags |= AP_F_IN_RESET;
2934 ap->ap_flags |= AP_F_HARSH_REINIT;
2935 ap->ap_probe = ATA_PROBE_NEED_INIT;
2936 ahci_cam_changed(ap, NULL, -1);
2938 case NEED_HOTPLUG_INSERT:
2940 * A hot-plug insertion event has occured and all
2941 * outstanding commands have already been revoked.
2943 * Don't recurse if this occurs while we are
2944 * resetting the port.
2946 if ((ap->ap_flags & AP_F_IN_RESET) == 0) {
2947 kprintf("%s: HOTPLUG - Device inserted\n",
2949 ap->ap_probe = ATA_PROBE_NEED_INIT;
2950 ahci_cam_changed(ap, NULL, -1);
2953 case NEED_HOTPLUG_REMOVE:
2955 * A hot-plug removal event has occured and all
2956 * outstanding commands have already been revoked.
2958 * Don't recurse if this occurs while we are
2959 * resetting the port.
2961 if ((ap->ap_flags & AP_F_IN_RESET) == 0) {
2962 kprintf("%s: HOTPLUG - Device removed\n",
2964 ahci_port_hardstop(ap);
2965 /* ap_probe set to failed */
2966 ahci_cam_changed(ap, NULL, -1);
2975 ahci_get_ccb(struct ahci_port *ap)
2977 struct ahci_ccb *ccb;
2979 lockmgr(&ap->ap_ccb_lock, LK_EXCLUSIVE);
2980 ccb = TAILQ_FIRST(&ap->ap_ccb_free);
2982 KKASSERT(ccb->ccb_xa.state == ATA_S_PUT);
2983 TAILQ_REMOVE(&ap->ap_ccb_free, ccb, ccb_entry);
2984 ccb->ccb_xa.state = ATA_S_SETUP;
2985 ccb->ccb_xa.flags = 0;
2986 ccb->ccb_xa.at = NULL;
2988 lockmgr(&ap->ap_ccb_lock, LK_RELEASE);
2994 ahci_put_ccb(struct ahci_ccb *ccb)
2996 struct ahci_port *ap = ccb->ccb_port;
2998 ccb->ccb_xa.state = ATA_S_PUT;
2999 lockmgr(&ap->ap_ccb_lock, LK_EXCLUSIVE);
3000 TAILQ_INSERT_TAIL(&ap->ap_ccb_free, ccb, ccb_entry);
3001 lockmgr(&ap->ap_ccb_lock, LK_RELEASE);
3005 ahci_get_err_ccb(struct ahci_port *ap)
3007 struct ahci_ccb *err_ccb;
3011 /* No commands may be active on the chip. */
3013 if (ap->ap_sc->sc_cap & AHCI_REG_CAP_SNCQ) {
3014 sact = ahci_pread(ap, AHCI_PREG_SACT);
3016 kprintf("%s: ahci_get_err_ccb but SACT %08x != 0?\n",
3017 PORTNAME(ap), sact);
3020 ci = ahci_pread(ap, AHCI_PREG_CI);
3022 kprintf("%s: ahci_get_err_ccb: ci not 0 (%08x)\n",
3026 KKASSERT((ap->ap_flags & AP_F_ERR_CCB_RESERVED) == 0);
3027 ap->ap_flags |= AP_F_ERR_CCB_RESERVED;
3029 /* Save outstanding command state. */
3030 ap->ap_err_saved_active = ap->ap_active;
3031 ap->ap_err_saved_active_cnt = ap->ap_active_cnt;
3032 ap->ap_err_saved_sactive = ap->ap_sactive;
3035 * Pretend we have no commands outstanding, so that completions won't
3038 ap->ap_active = ap->ap_active_cnt = ap->ap_sactive = 0;
3041 * Grab a CCB to use for error recovery. This should never fail, as
3042 * we ask atascsi to reserve one for us at init time.
3044 err_ccb = ap->ap_err_ccb;
3045 KKASSERT(err_ccb != NULL);
3046 err_ccb->ccb_xa.flags = 0;
3047 err_ccb->ccb_done = ahci_empty_done;
3053 ahci_put_err_ccb(struct ahci_ccb *ccb)
3055 struct ahci_port *ap = ccb->ccb_port;
3059 KKASSERT((ap->ap_flags & AP_F_ERR_CCB_RESERVED) != 0);
3062 * No commands may be active on the chip
3064 if (ap->ap_sc->sc_cap & AHCI_REG_CAP_SNCQ) {
3065 sact = ahci_pread(ap, AHCI_PREG_SACT);
3067 panic("ahci_port_err_ccb(%d) but SACT %08x != 0\n",
3068 ccb->ccb_slot, sact);
3071 ci = ahci_pread(ap, AHCI_PREG_CI);
3073 panic("ahci_put_err_ccb(%d) but CI %08x != 0 "
3074 "(act=%08x sact=%08x)\n",
3076 ap->ap_active, ap->ap_sactive);
3079 KKASSERT(ccb == ap->ap_err_ccb);
3081 /* Restore outstanding command state */
3082 ap->ap_sactive = ap->ap_err_saved_sactive;
3083 ap->ap_active_cnt = ap->ap_err_saved_active_cnt;
3084 ap->ap_active = ap->ap_err_saved_active;
3086 ap->ap_flags &= ~AP_F_ERR_CCB_RESERVED;
3090 * Read log page to get NCQ error.
3092 * NOTE: NCQ not currently supported on port multipliers. XXX
3095 ahci_port_read_ncq_error(struct ahci_port *ap, int target)
3097 struct ata_log_page_10h *log;
3098 struct ahci_ccb *ccb;
3099 struct ahci_ccb *ccb2;
3100 struct ahci_cmd_hdr *cmd_slot;
3101 struct ata_fis_h2d *fis;
3105 kprintf("%s: READ LOG PAGE target %d\n", PORTNAME(ap),
3110 * Prep error CCB for READ LOG EXT, page 10h, 1 sector.
3112 * Getting err_ccb clears active/sactive/active_cnt, putting
3113 * it back restores the fields.
3115 ccb = ahci_get_err_ccb(ap);
3116 ccb->ccb_xa.flags = ATA_F_READ | ATA_F_POLL;
3117 ccb->ccb_xa.data = ap->ap_err_scratch;
3118 ccb->ccb_xa.datalen = 512;
3119 ccb->ccb_xa.complete = ahci_dummy_done;
3120 ccb->ccb_xa.at = ap->ap_ata[target];
3122 fis = (struct ata_fis_h2d *)ccb->ccb_cmd_table->cfis;
3123 bzero(fis, sizeof(*fis));
3124 fis->type = ATA_FIS_TYPE_H2D;
3125 fis->flags = ATA_H2D_FLAGS_CMD | target;
3126 fis->command = ATA_C_READ_LOG_EXT;
3127 fis->lba_low = 0x10; /* queued error log page (10h) */
3128 fis->sector_count = 1; /* number of sectors (1) */
3129 fis->sector_count_exp = 0;
3130 fis->lba_mid = 0; /* starting offset */
3131 fis->lba_mid_exp = 0;
3134 cmd_slot = ccb->ccb_cmd_hdr;
3135 cmd_slot->flags = htole16(5); /* FIS length: 5 DWORDS */
3137 if (ahci_load_prdt(ccb) != 0) {
3142 ccb->ccb_xa.state = ATA_S_PENDING;
3143 if (ahci_poll(ccb, 1000, ahci_quick_timeout) != ATA_S_COMPLETE) {
3145 ahci_unload_prdt(ccb);
3148 ahci_unload_prdt(ccb);
3151 * Success, extract failed register set and tags from the scratch
3154 log = (struct ata_log_page_10h *)ap->ap_err_scratch;
3155 if (log->err_regs.type & ATA_LOG_10H_TYPE_NOTQUEUED) {
3156 /* Not queued bit was set - wasn't an NCQ error? */
3157 kprintf("%s: read NCQ error page, but not an NCQ error?\n",
3161 /* Copy back the log record as a D2H register FIS. */
3162 err_slot = log->err_regs.type & ATA_LOG_10H_TYPE_TAG_MASK;
3164 ccb2 = &ap->ap_ccbs[err_slot];
3165 if (ccb2->ccb_xa.state == ATA_S_ONCHIP) {
3166 kprintf("%s: read NCQ error page slot=%d\n",
3167 ATANAME(ap, ccb2->ccb_xa.at),
3169 memcpy(&ccb2->ccb_xa.rfis, &log->err_regs,
3170 sizeof(struct ata_fis_d2h));
3171 ccb2->ccb_xa.rfis.type = ATA_FIS_TYPE_D2H;
3172 ccb2->ccb_xa.rfis.flags = 0;
3174 kprintf("%s: read NCQ error page slot=%d, "
3175 "slot does not match any cmds\n",
3176 ATANAME(ccb2->ccb_port, ccb2->ccb_xa.at),
3182 ahci_put_err_ccb(ccb);
3183 kprintf("%s: DONE log page target %d err_slot=%d\n",
3184 PORTNAME(ap), target, err_slot);
3189 * Allocate memory for various structures DMAd by hardware. The maximum
3190 * number of segments for these tags is 1 so the DMA memory will have a
3191 * single physical base address.
3193 struct ahci_dmamem *
3194 ahci_dmamem_alloc(struct ahci_softc *sc, bus_dma_tag_t tag)
3196 struct ahci_dmamem *adm;
3199 adm = kmalloc(sizeof(*adm), M_DEVBUF, M_INTWAIT | M_ZERO);
3201 error = bus_dmamem_alloc(tag, (void **)&adm->adm_kva,
3202 BUS_DMA_ZERO, &adm->adm_map);
3205 error = bus_dmamap_load(tag, adm->adm_map,
3207 bus_dma_tag_getmaxsize(tag),
3208 ahci_dmamem_saveseg, &adm->adm_busaddr,
3213 bus_dmamap_destroy(tag, adm->adm_map);
3214 adm->adm_map = NULL;
3215 adm->adm_tag = NULL;
3216 adm->adm_kva = NULL;
3218 kfree(adm, M_DEVBUF);
3226 ahci_dmamem_saveseg(void *info, bus_dma_segment_t *segs, int nsegs, int error)
3228 KKASSERT(error == 0);
3229 KKASSERT(nsegs == 1);
3230 *(bus_addr_t *)info = segs->ds_addr;
3235 ahci_dmamem_free(struct ahci_softc *sc, struct ahci_dmamem *adm)
3238 bus_dmamap_unload(adm->adm_tag, adm->adm_map);
3239 bus_dmamap_destroy(adm->adm_tag, adm->adm_map);
3240 adm->adm_map = NULL;
3241 adm->adm_tag = NULL;
3242 adm->adm_kva = NULL;
3244 kfree(adm, M_DEVBUF);
3248 ahci_read(struct ahci_softc *sc, bus_size_t r)
3250 bus_space_barrier(sc->sc_iot, sc->sc_ioh, r, 4,
3251 BUS_SPACE_BARRIER_READ);
3252 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, r));
3256 ahci_write(struct ahci_softc *sc, bus_size_t r, u_int32_t v)
3258 bus_space_write_4(sc->sc_iot, sc->sc_ioh, r, v);
3259 bus_space_barrier(sc->sc_iot, sc->sc_ioh, r, 4,
3260 BUS_SPACE_BARRIER_WRITE);
3264 ahci_pread(struct ahci_port *ap, bus_size_t r)
3266 bus_space_barrier(ap->ap_sc->sc_iot, ap->ap_ioh, r, 4,
3267 BUS_SPACE_BARRIER_READ);
3268 return (bus_space_read_4(ap->ap_sc->sc_iot, ap->ap_ioh, r));
3272 ahci_pwrite(struct ahci_port *ap, bus_size_t r, u_int32_t v)
3274 bus_space_write_4(ap->ap_sc->sc_iot, ap->ap_ioh, r, v);
3275 bus_space_barrier(ap->ap_sc->sc_iot, ap->ap_ioh, r, 4,
3276 BUS_SPACE_BARRIER_WRITE);
3280 * Wait up to (timeout) milliseconds for the masked port register to
3283 * Timeout is in milliseconds.
3286 ahci_pwait_eq(struct ahci_port *ap, int timeout,
3287 bus_size_t r, u_int32_t mask, u_int32_t target)
3292 * Loop hard up to 100uS
3294 for (t = 0; t < 100; ++t) {
3295 if ((ahci_pread(ap, r) & mask) == target)
3297 ahci_os_hardsleep(1); /* us */
3301 timeout -= ahci_os_softsleep();
3302 if ((ahci_pread(ap, r) & mask) == target)
3304 } while (timeout > 0);
3309 ahci_wait_ne(struct ahci_softc *sc, bus_size_t r, u_int32_t mask,
3315 * Loop hard up to 100uS
3317 for (t = 0; t < 100; ++t) {
3318 if ((ahci_read(sc, r) & mask) != target)
3320 ahci_os_hardsleep(1); /* us */
3324 * And one millisecond the slow way
3328 t -= ahci_os_softsleep();
3329 if ((ahci_read(sc, r) & mask) != target)
3338 * Acquire an ata transfer.
3340 * Pass a NULL at for direct-attached transfers, and a non-NULL at for
3341 * targets that go through the port multiplier.
3344 ahci_ata_get_xfer(struct ahci_port *ap, struct ata_port *at)
3346 struct ahci_ccb *ccb;
3348 ccb = ahci_get_ccb(ap);
3350 DPRINTF(AHCI_D_XFER, "%s: ahci_ata_get_xfer: NULL ccb\n",
3355 DPRINTF(AHCI_D_XFER, "%s: ahci_ata_get_xfer got slot %d\n",
3356 PORTNAME(ap), ccb->ccb_slot);
3358 bzero(ccb->ccb_xa.fis, sizeof(*ccb->ccb_xa.fis));
3359 ccb->ccb_xa.at = at;
3360 ccb->ccb_xa.fis->type = ATA_FIS_TYPE_H2D;
3362 return (&ccb->ccb_xa);
3366 ahci_ata_put_xfer(struct ata_xfer *xa)
3368 struct ahci_ccb *ccb = (struct ahci_ccb *)xa;
3370 DPRINTF(AHCI_D_XFER, "ahci_ata_put_xfer slot %d\n", ccb->ccb_slot);
3376 ahci_ata_cmd(struct ata_xfer *xa)
3378 struct ahci_ccb *ccb = (struct ahci_ccb *)xa;
3379 struct ahci_cmd_hdr *cmd_slot;
3381 KKASSERT(xa->state == ATA_S_SETUP);
3383 if (ccb->ccb_port->ap_state == AP_S_FATAL_ERROR)
3385 ccb->ccb_done = ahci_ata_cmd_done;
3387 cmd_slot = ccb->ccb_cmd_hdr;
3388 cmd_slot->flags = htole16(5); /* FIS length (in DWORDs) */
3389 if (ccb->ccb_xa.at) {
3390 cmd_slot->flags |= htole16(ccb->ccb_xa.at->at_target <<
3391 AHCI_CMD_LIST_FLAG_PMP_SHIFT);
3394 if (xa->flags & ATA_F_WRITE)
3395 cmd_slot->flags |= htole16(AHCI_CMD_LIST_FLAG_W);
3397 if (xa->flags & ATA_F_PACKET)
3398 cmd_slot->flags |= htole16(AHCI_CMD_LIST_FLAG_A);
3400 if (ahci_load_prdt(ccb) != 0)
3403 xa->state = ATA_S_PENDING;
3405 if (xa->flags & ATA_F_POLL)
3406 return (ahci_poll(ccb, xa->timeout, ahci_ata_cmd_timeout));
3409 KKASSERT((xa->flags & ATA_F_TIMEOUT_EXPIRED) == 0);
3410 xa->flags |= ATA_F_TIMEOUT_DESIRED;
3417 xa->state = ATA_S_ERROR;
3420 return (ATA_S_ERROR);
3424 ahci_ata_cmd_done(struct ahci_ccb *ccb)
3426 struct ata_xfer *xa = &ccb->ccb_xa;
3429 * NOTE: callout does not lock port and may race us modifying
3430 * the flags, so make sure its stopped.
3432 if (xa->flags & ATA_F_TIMEOUT_RUNNING) {
3433 callout_stop(&ccb->ccb_timeout);
3434 xa->flags &= ~ATA_F_TIMEOUT_RUNNING;
3436 xa->flags &= ~(ATA_F_TIMEOUT_DESIRED | ATA_F_TIMEOUT_EXPIRED);
3438 KKASSERT(xa->state != ATA_S_ONCHIP);
3439 ahci_unload_prdt(ccb);
3441 if (xa->state != ATA_S_TIMEOUT)
3446 * Timeout from callout, MPSAFE - nothing can mess with the CCB's flags
3447 * while the callout is runing.
3449 * We can't safely get the port lock here or delay, we could block
3450 * the callout thread.
3453 ahci_ata_cmd_timeout_unserialized(void *arg)
3455 struct ahci_ccb *ccb = arg;
3456 struct ahci_port *ap = ccb->ccb_port;
3458 ccb->ccb_xa.flags &= ~ATA_F_TIMEOUT_RUNNING;
3459 ccb->ccb_xa.flags |= ATA_F_TIMEOUT_EXPIRED;
3460 ahci_os_signal_port_thread(ap, AP_SIGF_TIMEOUT);
3464 * Timeout code, typically called when the port command processor is running.
3466 * We have to be very very careful here. We cannot stop the port unless
3467 * CR is already clear or the only active commands remaining are timed-out
3468 * ones. Otherwise stopping the port will race the command processor and
3469 * we can lose events. While we can theoretically just restart everything
3470 * that could result in a double-issue which will not work for ATAPI commands.
3473 ahci_ata_cmd_timeout(struct ahci_ccb *ccb)
3475 struct ata_xfer *xa = &ccb->ccb_xa;
3476 struct ahci_port *ap = ccb->ccb_port;
3477 struct ata_port *at;
3482 at = ccb->ccb_xa.at;
3484 kprintf("%s: CMD TIMEOUT state=%d slot=%d\n"
3486 "\tsactive=%08x active=%08x expired=%08x\n"
3487 "\t sact=%08x ci=%08x\n"
3490 ccb->ccb_xa.state, ccb->ccb_slot,
3491 ahci_pread(ap, AHCI_PREG_CMD), AHCI_PFMT_CMD,
3492 ap->ap_sactive, ap->ap_active, ap->ap_expired,
3493 ahci_pread(ap, AHCI_PREG_SACT),
3494 ahci_pread(ap, AHCI_PREG_CI),
3495 ahci_pread(ap, AHCI_PREG_TFD), AHCI_PFMT_TFD_STS
3500 * NOTE: Timeout will not be running if the command was polled.
3501 * If we got here at least one of these flags should be set.
3503 KKASSERT(xa->flags & (ATA_F_POLL | ATA_F_TIMEOUT_DESIRED |
3504 ATA_F_TIMEOUT_RUNNING));
3505 xa->flags &= ~(ATA_F_TIMEOUT_RUNNING | ATA_F_TIMEOUT_EXPIRED);
3507 if (ccb->ccb_xa.state == ATA_S_PENDING) {
3508 TAILQ_REMOVE(&ap->ap_ccb_pending, ccb, ccb_entry);
3509 ccb->ccb_xa.state = ATA_S_TIMEOUT;
3512 ahci_issue_pending_commands(ap, NULL);
3515 if (ccb->ccb_xa.state != ATA_S_ONCHIP) {
3516 kprintf("%s: Unexpected state during timeout: %d\n",
3517 ATANAME(ap, at), ccb->ccb_xa.state);
3522 * Ok, we can only get this command off the chip if CR is inactive
3523 * or if the only commands running on the chip are all expired.
3524 * Otherwise we have to wait until the port is in a safe state.
3526 * Do not set state here, it will cause polls to return when the
3527 * ccb is not yet off the chip.
3529 ap->ap_expired |= 1 << ccb->ccb_slot;
3531 if ((ahci_pread(ap, AHCI_PREG_CMD) & AHCI_PREG_CMD_CR) &&
3532 (ap->ap_active | ap->ap_sactive) != ap->ap_expired) {
3534 * If using FBSS or NCQ we can't safely stop the port
3537 kprintf("%s: Deferred timeout until its safe, slot %d\n",
3538 ATANAME(ap, at), ccb->ccb_slot);
3543 * We can safely stop the port and process all expired ccb's,
3544 * which will include our current ccb.
3546 ci_saved = (ap->ap_sactive) ? ahci_pread(ap, AHCI_PREG_SACT) :
3547 ahci_pread(ap, AHCI_PREG_CI);
3548 ahci_port_stop(ap, 0);
3550 while (ap->ap_expired) {
3551 slot = ffs(ap->ap_expired) - 1;
3552 ap->ap_expired &= ~(1 << slot);
3553 ci_saved &= ~(1 << slot);
3554 ccb = &ap->ap_ccbs[slot];
3555 ccb->ccb_xa.state = ATA_S_TIMEOUT;
3556 if (ccb->ccb_xa.flags & ATA_F_NCQ) {
3557 KKASSERT(ap->ap_sactive & (1 << slot));
3558 ap->ap_sactive &= ~(1 << slot);
3560 KKASSERT(ap->ap_active & (1 << slot));
3561 ap->ap_active &= ~(1 << slot);
3562 --ap->ap_active_cnt;
3565 ccb->ccb_xa.complete(&ccb->ccb_xa);
3567 /* ccb invalid now */
3570 * We can safely CLO the port to clear any BSY/DRQ, a case which
3571 * can occur with port multipliers. This will unbrick the port
3572 * and allow commands to other targets behind the PM continue.
3575 * Finally, once the port has been restarted we can issue any
3576 * previously saved pending commands, and run the port interrupt
3577 * code to handle any completions which may have occured when
3580 if (ahci_pread(ap, AHCI_PREG_TFD) &
3581 (AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) {
3582 kprintf("%s: Warning, issuing CLO after timeout\n",
3586 ahci_port_start(ap);
3589 * We absolutely must make sure the chipset cleared activity on
3590 * all slots. This sometimes might not happen due to races with
3591 * a chipset interrupt which stops the port before we can manage
3592 * to. For some reason some chipsets don't clear the active
3593 * commands when we turn off CMD_ST after the chip has stopped
3594 * operations itself.
3596 if (ahci_pactive(ap) != 0) {
3597 ahci_port_stop(ap, 0);
3598 ahci_port_start(ap);
3599 if ((mask = ahci_pactive(ap)) != 0) {
3600 kprintf("%s: quick-timeout: chipset failed "
3601 "to clear active cmds %08x\n",
3602 PORTNAME(ap), mask);
3605 ahci_issue_saved_commands(ap, ci_saved & ~ap->ap_expired);
3606 ahci_issue_pending_commands(ap, NULL);
3607 ahci_port_intr(ap, 0);
3611 * Issue a previously saved set of commands
3614 ahci_issue_saved_commands(struct ahci_port *ap, u_int32_t ci_saved)
3617 KKASSERT(!((ap->ap_active & ci_saved) &&
3618 (ap->ap_sactive & ci_saved)));
3619 KKASSERT((ci_saved & ap->ap_expired) == 0);
3620 if (ap->ap_sactive & ci_saved)
3621 ahci_pwrite(ap, AHCI_PREG_SACT, ci_saved);
3622 ahci_pwrite(ap, AHCI_PREG_CI, ci_saved);
3627 * Used by the softreset, pmprobe, and read_ncq_error only, in very
3628 * specialized, controlled circumstances.
3630 * Only one command may be pending.
3633 ahci_quick_timeout(struct ahci_ccb *ccb)
3635 struct ahci_port *ap = ccb->ccb_port;
3638 switch (ccb->ccb_xa.state) {
3640 TAILQ_REMOVE(&ap->ap_ccb_pending, ccb, ccb_entry);
3641 ccb->ccb_xa.state = ATA_S_TIMEOUT;
3645 * We have to clear the command on-chip.
3647 KKASSERT(ap->ap_active == (1 << ccb->ccb_slot) &&
3648 ap->ap_sactive == 0);
3649 ahci_port_stop(ap, 0);
3650 ahci_port_start(ap);
3651 if (ahci_pactive(ap) != 0) {
3652 ahci_port_stop(ap, 0);
3653 ahci_port_start(ap);
3654 if ((mask = ahci_pactive(ap)) != 0) {
3655 kprintf("%s: quick-timeout: chipset failed "
3656 "to clear active cmds %08x\n",
3657 PORTNAME(ap), mask);
3661 ccb->ccb_xa.state = ATA_S_TIMEOUT;
3662 ap->ap_active &= ~(1 << ccb->ccb_slot);
3663 KKASSERT(ap->ap_active_cnt > 0);
3664 --ap->ap_active_cnt;
3667 panic("%s: ahci_quick_timeout: ccb in bad state %d",
3668 ATANAME(ap, ccb->ccb_xa.at), ccb->ccb_xa.state);
3673 ahci_dummy_done(struct ata_xfer *xa)
3678 ahci_empty_done(struct ahci_ccb *ccb)
3683 ahci_set_feature(struct ahci_port *ap, struct ata_port *atx,
3684 int feature, int enable)
3686 struct ata_port *at;
3687 struct ata_xfer *xa;
3690 at = atx ? atx : ap->ap_ata[0];
3692 xa = ahci_ata_get_xfer(ap, atx);
3694 xa->fis->type = ATA_FIS_TYPE_H2D;
3695 xa->fis->flags = ATA_H2D_FLAGS_CMD | at->at_target;
3696 xa->fis->command = ATA_C_SET_FEATURES;
3697 xa->fis->features = enable ? ATA_C_SATA_FEATURE_ENA :
3698 ATA_C_SATA_FEATURE_DIS;
3699 xa->fis->sector_count = feature;
3700 xa->fis->control = ATA_FIS_CONTROL_4BIT;
3702 xa->complete = ahci_dummy_done;
3704 xa->flags = ATA_F_POLL;
3707 if (ahci_ata_cmd(xa) == ATA_S_COMPLETE)
3711 ahci_ata_put_xfer(xa);