2 * Copyright (c) 2002 Myson Technology Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions, and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. The name of the author may not be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * Written by: yen_cw@myson.com.tw available at: http://www.myson.com.tw/
28 * $FreeBSD: src/sys/dev/my/if_my.c,v 1.2.2.4 2002/04/17 02:05:27 julian Exp $
29 * $DragonFly: src/sys/dev/netif/my/if_my.c,v 1.10 2004/06/02 14:42:53 eirikn Exp $
31 * Myson fast ethernet PCI NIC driver
33 * $Id: if_my.c,v 1.40 2001/11/30 03:55:00 <yen_cw@myson.com.tw> wpaul Exp $
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sockio.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/queue.h>
43 #include <sys/types.h>
45 #include <sys/module.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_media.h>
53 #include <net/if_dl.h>
56 #include <vm/vm.h> /* for vtophys */
57 #include <vm/pmap.h> /* for vtophys */
58 #include <machine/clock.h> /* for DELAY */
59 #include <machine/bus_memio.h>
60 #include <machine/bus_pio.h>
61 #include <machine/bus.h>
62 #include <machine/resource.h>
66 #include <bus/pci/pcireg.h>
67 #include <bus/pci/pcivar.h>
69 #include "../mii_layer/mii.h"
70 #include "../mii_layer/miivar.h"
72 #include "miibus_if.h"
75 * #define MY_USEIOSPACE
78 static int MY_USEIOSPACE = 1;
81 #define MY_RES SYS_RES_IOPORT
82 #define MY_RID MY_PCI_LOIO
84 #define MY_RES SYS_RES_MEMORY
85 #define MY_RID MY_PCI_LOMEM
92 * Various supported device vendors/types and their names.
94 struct my_type *my_info_tmp;
95 static struct my_type my_devs[] = {
96 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"},
97 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"},
98 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"},
103 * Various supported PHY vendors/types and their names. Note that this driver
104 * will work with pretty much any MII-compliant PHY, so failure to positively
105 * identify the chip is not a fatal error.
107 static struct my_type my_phys[] = {
108 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"},
109 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"},
110 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"},
111 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"},
112 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"},
113 {0, 0, "<MII-compliant physical interface>"}
116 static int my_probe(device_t);
117 static int my_attach(device_t);
118 static int my_detach(device_t);
119 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *);
120 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *);
121 static void my_rxeof(struct my_softc *);
122 static void my_txeof(struct my_softc *);
123 static void my_txeoc(struct my_softc *);
124 static void my_intr(void *);
125 static void my_start(struct ifnet *);
126 static int my_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
127 static void my_init(void *);
128 static void my_stop(struct my_softc *);
129 static void my_watchdog(struct ifnet *);
130 static void my_shutdown(device_t);
131 static int my_ifmedia_upd(struct ifnet *);
132 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *);
133 static u_int16_t my_phy_readreg(struct my_softc *, int);
134 static void my_phy_writereg(struct my_softc *, int, int);
135 static void my_autoneg_xmit(struct my_softc *);
136 static void my_autoneg_mii(struct my_softc *, int, int);
137 static void my_setmode_mii(struct my_softc *, int);
138 static void my_getmode_mii(struct my_softc *);
139 static void my_setcfg(struct my_softc *, int);
140 static u_int8_t my_calchash(caddr_t);
141 static void my_setmulti(struct my_softc *);
142 static void my_reset(struct my_softc *);
143 static int my_list_rx_init(struct my_softc *);
144 static int my_list_tx_init(struct my_softc *);
145 static long my_send_cmd_to_phy(struct my_softc *, int, int);
147 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
148 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
150 static device_method_t my_methods[] = {
151 /* Device interface */
152 DEVMETHOD(device_probe, my_probe),
153 DEVMETHOD(device_attach, my_attach),
154 DEVMETHOD(device_detach, my_detach),
155 DEVMETHOD(device_shutdown, my_shutdown),
160 static driver_t my_driver = {
163 sizeof(struct my_softc)
166 static devclass_t my_devclass;
168 DECLARE_DUMMY_MODULE(if_my);
169 DRIVER_MODULE(if_my, pci, my_driver, my_devclass, 0, 0);
172 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad)
180 /* enable MII output */
181 miir = CSR_READ_4(sc, MY_MANAGEMENT);
184 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO;
186 /* send 32 1's preamble */
187 for (i = 0; i < 32; i++) {
188 /* low MDC; MDO is already high (miir) */
189 miir &= ~MY_MASK_MIIR_MII_MDC;
190 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
193 miir |= MY_MASK_MIIR_MII_MDC;
194 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
197 /* calculate ST+OP+PHYAD+REGAD+TA */
198 data = opcode | (sc->my_phy_addr << 7) | (regad << 2);
203 /* low MDC, prepare MDO */
204 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
206 miir |= MY_MASK_MIIR_MII_MDO;
208 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
210 miir |= MY_MASK_MIIR_MII_MDC;
211 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
216 if (mask == 0x2 && opcode == MY_OP_READ)
217 miir &= ~MY_MASK_MIIR_MII_WRITE;
226 my_phy_readreg(struct my_softc * sc, int reg)
233 if (sc->my_info->my_did == MTD803ID)
234 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2);
236 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg);
243 miir &= ~MY_MASK_MIIR_MII_MDC;
244 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
247 miir = CSR_READ_4(sc, MY_MANAGEMENT);
248 if (miir & MY_MASK_MIIR_MII_MDI)
251 /* high MDC, and wait */
252 miir |= MY_MASK_MIIR_MII_MDC;
253 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
261 miir &= ~MY_MASK_MIIR_MII_MDC;
262 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
266 return (u_int16_t) data;
271 my_phy_writereg(struct my_softc * sc, int reg, int data)
278 if (sc->my_info->my_did == MTD803ID)
279 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data);
281 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg);
286 /* low MDC, prepare MDO */
287 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
289 miir |= MY_MASK_MIIR_MII_MDO;
290 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
294 miir |= MY_MASK_MIIR_MII_MDC;
295 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
303 miir &= ~MY_MASK_MIIR_MII_MDC;
304 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
311 my_calchash(caddr_t addr)
313 u_int32_t crc, carry;
317 /* Compute CRC for the address value. */
318 crc = 0xFFFFFFFF; /* initial value */
320 for (i = 0; i < 6; i++) {
322 for (j = 0; j < 8; j++) {
323 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
327 crc = (crc ^ 0x04c11db6) | carry;
332 * return the filter bit position Note: I arrived at the following
333 * nonsense through experimentation. It's not the usual way to
334 * generate the bit position but it's the only thing I could come up
337 return (~(crc >> 26) & 0x0000003F);
342 * Program the 64-bit multicast hash filter.
345 my_setmulti(struct my_softc * sc)
349 u_int32_t hashes[2] = {0, 0};
350 struct ifmultiaddr *ifma;
356 ifp = &sc->arpcom.ac_if;
358 rxfilt = CSR_READ_4(sc, MY_TCRRCR);
360 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
362 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
363 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF);
364 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF);
370 /* first, zot all the existing hash bits */
371 CSR_WRITE_4(sc, MY_MAR0, 0);
372 CSR_WRITE_4(sc, MY_MAR1, 0);
374 /* now program new ones */
375 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
376 if (ifma->ifma_addr->sa_family != AF_LINK)
378 h = my_calchash(LLADDR((struct sockaddr_dl *) ifma->ifma_addr));
380 hashes[0] |= (1 << h);
382 hashes[1] |= (1 << (h - 32));
390 CSR_WRITE_4(sc, MY_MAR0, hashes[0]);
391 CSR_WRITE_4(sc, MY_MAR1, hashes[1]);
392 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
398 * Initiate an autonegotiation session.
401 my_autoneg_xmit(struct my_softc * sc)
403 u_int16_t phy_sts = 0;
407 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
409 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
411 phy_sts = my_phy_readreg(sc, PHY_BMCR);
412 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR;
413 my_phy_writereg(sc, PHY_BMCR, phy_sts);
421 * Invoke autonegotiation on a PHY.
424 my_autoneg_mii(struct my_softc * sc, int flag, int verbose)
426 u_int16_t phy_sts = 0, media, advert, ability;
427 u_int16_t ability2 = 0;
434 ifp = &sc->arpcom.ac_if;
436 ifm->ifm_media = IFM_ETHER | IFM_AUTO;
438 #ifndef FORCE_AUTONEG_TFOUR
440 * First, see if autoneg is supported. If not, there's no point in
443 phy_sts = my_phy_readreg(sc, PHY_BMSR);
444 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
446 printf("my%d: autonegotiation not supported\n",
448 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
454 case MY_FLAG_FORCEDELAY:
456 * XXX Never use this option anywhere but in the probe
457 * routine: making the kernel stop dead in its tracks for
458 * three whole seconds after we've gone multi-user is really
464 case MY_FLAG_SCHEDDELAY:
466 * Wait for the transmitter to go idle before starting an
467 * autoneg session, otherwise my_start() may clobber our
468 * timeout, and we don't want to allow transmission during an
469 * autoneg session since that can screw it up.
471 if (sc->my_cdata.my_tx_head != NULL) {
472 sc->my_want_auto = 1;
479 sc->my_want_auto = 0;
482 case MY_FLAG_DELAYTIMEO:
487 printf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag);
492 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
494 printf("my%d: autoneg complete, ", sc->my_unit);
495 phy_sts = my_phy_readreg(sc, PHY_BMSR);
498 printf("my%d: autoneg not complete, ", sc->my_unit);
501 media = my_phy_readreg(sc, PHY_BMCR);
503 /* Link is good. Report modes and set duplex mode. */
504 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
506 printf("my%d: link status good. ", sc->my_unit);
507 advert = my_phy_readreg(sc, PHY_ANAR);
508 ability = my_phy_readreg(sc, PHY_LPAR);
509 if ((sc->my_pinfo->my_vid == MarvellPHYID0) ||
510 (sc->my_pinfo->my_vid == LevelOnePHYID0)) {
511 ability2 = my_phy_readreg(sc, PHY_1000SR);
512 if (ability2 & PHY_1000SR_1000BTXFULL) {
516 * this version did not support 1000M,
518 * IFM_ETHER|IFM_1000_TX|IFM_FDX;
521 IFM_ETHER | IFM_100_TX | IFM_FDX;
522 media &= ~PHY_BMCR_SPEEDSEL;
523 media |= PHY_BMCR_1000;
524 media |= PHY_BMCR_DUPLEX;
525 printf("(full-duplex, 1000Mbps)\n");
526 } else if (ability2 & PHY_1000SR_1000BTXHALF) {
530 * this version did not support 1000M,
531 * ifm->ifm_media = IFM_ETHER|IFM_1000_TX;
533 ifm->ifm_media = IFM_ETHER | IFM_100_TX;
534 media &= ~PHY_BMCR_SPEEDSEL;
535 media &= ~PHY_BMCR_DUPLEX;
536 media |= PHY_BMCR_1000;
537 printf("(half-duplex, 1000Mbps)\n");
540 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
541 ifm->ifm_media = IFM_ETHER | IFM_100_T4;
542 media |= PHY_BMCR_SPEEDSEL;
543 media &= ~PHY_BMCR_DUPLEX;
544 printf("(100baseT4)\n");
545 } else if (advert & PHY_ANAR_100BTXFULL &&
546 ability & PHY_ANAR_100BTXFULL) {
547 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
548 media |= PHY_BMCR_SPEEDSEL;
549 media |= PHY_BMCR_DUPLEX;
550 printf("(full-duplex, 100Mbps)\n");
551 } else if (advert & PHY_ANAR_100BTXHALF &&
552 ability & PHY_ANAR_100BTXHALF) {
553 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
554 media |= PHY_BMCR_SPEEDSEL;
555 media &= ~PHY_BMCR_DUPLEX;
556 printf("(half-duplex, 100Mbps)\n");
557 } else if (advert & PHY_ANAR_10BTFULL &&
558 ability & PHY_ANAR_10BTFULL) {
559 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
560 media &= ~PHY_BMCR_SPEEDSEL;
561 media |= PHY_BMCR_DUPLEX;
562 printf("(full-duplex, 10Mbps)\n");
564 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
565 media &= ~PHY_BMCR_SPEEDSEL;
566 media &= ~PHY_BMCR_DUPLEX;
567 printf("(half-duplex, 10Mbps)\n");
569 media &= ~PHY_BMCR_AUTONEGENBL;
571 /* Set ASIC's duplex mode to match the PHY. */
572 my_phy_writereg(sc, PHY_BMCR, media);
573 my_setcfg(sc, media);
576 printf("my%d: no carrier\n", sc->my_unit);
580 if (sc->my_tx_pend) {
590 * To get PHY ability.
593 my_getmode_mii(struct my_softc * sc)
599 ifp = &sc->arpcom.ac_if;
600 bmsr = my_phy_readreg(sc, PHY_BMSR);
602 printf("my%d: PHY status word: %x\n", sc->my_unit, bmsr);
605 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
607 if (bmsr & PHY_BMSR_10BTHALF) {
609 printf("my%d: 10Mbps half-duplex mode supported\n",
611 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX,
613 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
615 if (bmsr & PHY_BMSR_10BTFULL) {
617 printf("my%d: 10Mbps full-duplex mode supported\n",
620 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX,
622 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
624 if (bmsr & PHY_BMSR_100BTXHALF) {
626 printf("my%d: 100Mbps half-duplex mode supported\n",
628 ifp->if_baudrate = 100000000;
629 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
630 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX,
632 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
634 if (bmsr & PHY_BMSR_100BTXFULL) {
636 printf("my%d: 100Mbps full-duplex mode supported\n",
638 ifp->if_baudrate = 100000000;
639 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX,
641 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
643 /* Some also support 100BaseT4. */
644 if (bmsr & PHY_BMSR_100BT4) {
646 printf("my%d: 100baseT4 mode supported\n", sc->my_unit);
647 ifp->if_baudrate = 100000000;
648 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL);
649 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4;
650 #ifdef FORCE_AUTONEG_TFOUR
652 printf("my%d: forcing on autoneg support for BT4\n",
654 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL):
655 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
658 #if 0 /* this version did not support 1000M, */
659 if (sc->my_pinfo->my_vid == MarvellPHYID0) {
661 printf("my%d: 1000Mbps half-duplex mode supported\n",
664 ifp->if_baudrate = 1000000000;
665 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_TX, 0, NULL);
666 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_TX | IFM_HDX,
669 printf("my%d: 1000Mbps full-duplex mode supported\n",
671 ifp->if_baudrate = 1000000000;
672 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_TX | IFM_FDX,
674 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_TX | IFM_FDX;
677 if (bmsr & PHY_BMSR_CANAUTONEG) {
679 printf("my%d: autoneg supported\n", sc->my_unit);
680 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
681 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
688 * Set speed and duplex mode.
691 my_setmode_mii(struct my_softc * sc, int media)
697 ifp = &sc->arpcom.ac_if;
699 * If an autoneg session is in progress, stop it.
701 if (sc->my_autoneg) {
702 printf("my%d: canceling autoneg session\n", sc->my_unit);
703 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0;
704 bmcr = my_phy_readreg(sc, PHY_BMCR);
705 bmcr &= ~PHY_BMCR_AUTONEGENBL;
706 my_phy_writereg(sc, PHY_BMCR, bmcr);
708 printf("my%d: selecting MII, ", sc->my_unit);
709 bmcr = my_phy_readreg(sc, PHY_BMCR);
710 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 |
711 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK);
713 #if 0 /* this version did not support 1000M, */
714 if (IFM_SUBTYPE(media) == IFM_1000_TX) {
715 printf("1000Mbps/T4, half-duplex\n");
716 bmcr &= ~PHY_BMCR_SPEEDSEL;
717 bmcr &= ~PHY_BMCR_DUPLEX;
718 bmcr |= PHY_BMCR_1000;
721 if (IFM_SUBTYPE(media) == IFM_100_T4) {
722 printf("100Mbps/T4, half-duplex\n");
723 bmcr |= PHY_BMCR_SPEEDSEL;
724 bmcr &= ~PHY_BMCR_DUPLEX;
726 if (IFM_SUBTYPE(media) == IFM_100_TX) {
728 bmcr |= PHY_BMCR_SPEEDSEL;
730 if (IFM_SUBTYPE(media) == IFM_10_T) {
732 bmcr &= ~PHY_BMCR_SPEEDSEL;
734 if ((media & IFM_GMASK) == IFM_FDX) {
735 printf("full duplex\n");
736 bmcr |= PHY_BMCR_DUPLEX;
738 printf("half duplex\n");
739 bmcr &= ~PHY_BMCR_DUPLEX;
741 my_phy_writereg(sc, PHY_BMCR, bmcr);
748 * The Myson manual states that in order to fiddle with the 'full-duplex' and
749 * '100Mbps' bits in the netconfig register, we first have to put the
750 * transmit and/or receive logic in the idle state.
753 my_setcfg(struct my_softc * sc, int bmcr)
758 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) {
760 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE));
761 for (i = 0; i < MY_TIMEOUT; i++) {
763 if (!(CSR_READ_4(sc, MY_TCRRCR) &
764 (MY_TXRUN | MY_RXRUN)))
768 printf("my%d: failed to force tx and rx to idle \n",
771 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000);
772 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10);
773 if (bmcr & PHY_BMCR_1000)
774 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000);
775 else if (!(bmcr & PHY_BMCR_SPEEDSEL))
776 MY_SETBIT(sc, MY_TCRRCR, MY_PS10);
777 if (bmcr & PHY_BMCR_DUPLEX)
778 MY_SETBIT(sc, MY_TCRRCR, MY_FD);
780 MY_CLRBIT(sc, MY_TCRRCR, MY_FD);
782 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE);
788 my_reset(struct my_softc * sc)
793 MY_SETBIT(sc, MY_BCR, MY_SWR);
794 for (i = 0; i < MY_TIMEOUT; i++) {
796 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR))
800 printf("m0x%d: reset never completed!\n", sc->my_unit);
802 /* Wait a little while for the chip to get its brains in order. */
809 * Probe for a Myson chip. Check the PCI vendor and device IDs against our
810 * list and return a device name if we find a match.
813 my_probe(device_t dev)
818 while (t->my_name != NULL) {
819 if ((pci_get_vendor(dev) == t->my_vid) &&
820 (pci_get_device(dev) == t->my_did)) {
821 device_set_desc(dev, t->my_name);
831 * Attach the interface. Allocate softc structures, do ifmedia setup and
832 * ethernet/BPF attach.
835 my_attach(device_t dev)
838 u_char eaddr[ETHER_ADDR_LEN];
839 u_int32_t command, iobase;
842 int media = IFM_ETHER | IFM_100_TX | IFM_FDX;
846 u_int16_t phy_vid, phy_did, phy_sts = 0;
847 int rid, unit, error = 0;
850 sc = device_get_softc(dev);
851 unit = device_get_unit(dev);
853 printf("my%d: no memory for softc struct!\n", unit);
858 bzero(sc, sizeof(struct my_softc));
859 /*mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);*/
863 * Map control/status registers.
866 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
867 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
868 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command & 0x000000ff, 4);
869 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
871 command = pci_read_config(dev, PCIR_COMMAND, 4);
872 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
873 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4);
874 command = pci_read_config(dev, PCIR_COMMAND, 4);
876 if (my_info_tmp->my_did == MTD800ID) {
877 iobase = pci_read_config(dev, MY_PCI_LOIO, 4);
882 if (!(command & PCIM_CMD_PORTEN)) {
883 printf("my%d: failed to enable I/O ports!\n", unit);
889 if (!pci_map_port(config_id, MY_PCI_LOIO, (u_int16_t *) & (sc->my_bhandle))) {
890 printf("my%d: couldn't map ports\n", unit);
895 sc->my_btag = I386_BUS_SPACE_IO;
898 if (!(command & PCIM_CMD_MEMEN)) {
899 printf("my%d: failed to enable memory mapping!\n",
905 if (!pci_map_mem(config_id, MY_PCI_LOMEM, &vbase, &pbase)) {
906 printf ("my%d: couldn't map memory\n", unit);
910 sc->my_btag = I386_BUS_SPACE_MEM;
911 sc->my_bhandle = vbase;
916 sc->my_res = bus_alloc_resource(dev, MY_RES, &rid,
917 0, ~0, 1, RF_ACTIVE);
919 if (sc->my_res == NULL) {
920 printf("my%d: couldn't map ports/memory\n", unit);
924 sc->my_btag = rman_get_bustag(sc->my_res);
925 sc->my_bhandle = rman_get_bushandle(sc->my_res);
928 sc->my_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
929 RF_SHAREABLE | RF_ACTIVE);
931 if (sc->my_irq == NULL) {
932 printf("my%d: couldn't map interrupt\n", unit);
933 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
937 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET,
938 my_intr, sc, &sc->my_intrhand);
941 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
942 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
943 printf("my%d: couldn't set up irq\n", unit);
946 callout_handle_init(&sc->my_stat_ch);
948 sc->my_info = my_info_tmp;
950 /* Reset the adapter. */
954 * Get station address
956 for (i = 0; i < ETHER_ADDR_LEN; ++i)
957 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i);
960 * A Myson chip was detected. Inform the world.
962 printf("my%d: Ethernet address: %6D\n", unit, eaddr, ":");
966 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8,
968 if (sc->my_ldata_ptr == NULL) {
970 printf("my%d: no memory for list buffers!\n", unit);
974 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr;
975 round = (unsigned int)sc->my_ldata_ptr & 0xF;
976 roundptr = sc->my_ldata_ptr;
977 for (i = 0; i < 8; i++) {
984 sc->my_ldata = (struct my_list_data *) roundptr;
985 bzero(sc->my_ldata, sizeof(struct my_list_data));
987 ifp = &sc->arpcom.ac_if;
989 if_initname(ifp, "my", unit);
990 ifp->if_mtu = ETHERMTU;
991 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
992 ifp->if_ioctl = my_ioctl;
993 ifp->if_output = ether_output;
994 ifp->if_start = my_start;
995 ifp->if_watchdog = my_watchdog;
996 ifp->if_init = my_init;
997 ifp->if_baudrate = 10000000;
998 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1000 if (sc->my_info->my_did == MTD803ID)
1001 sc->my_pinfo = my_phys;
1004 printf("my%d: probing for a PHY\n", sc->my_unit);
1005 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) {
1007 printf("my%d: checking address: %d\n",
1009 sc->my_phy_addr = i;
1010 phy_sts = my_phy_readreg(sc, PHY_BMSR);
1011 if ((phy_sts != 0) && (phy_sts != 0xffff))
1017 phy_vid = my_phy_readreg(sc, PHY_VENID);
1018 phy_did = my_phy_readreg(sc, PHY_DEVID);
1020 printf("my%d: found PHY at address %d, ",
1021 sc->my_unit, sc->my_phy_addr);
1022 printf("vendor id: %x device id: %x\n",
1027 if (phy_vid == p->my_vid) {
1033 if (sc->my_pinfo == NULL)
1034 sc->my_pinfo = &my_phys[PHY_UNKNOWN];
1036 printf("my%d: PHY type: %s\n",
1037 sc->my_unit, sc->my_pinfo->my_name);
1039 printf("my%d: MII without any phy!\n", sc->my_unit);
1045 /* Do ifmedia setup. */
1046 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts);
1048 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1);
1049 media = sc->ifmedia.ifm_media;
1051 ifmedia_set(&sc->ifmedia, media);
1053 ether_ifattach(ifp, eaddr);
1056 at_shutdown(my_shutdown, sc, SHUTDOWN_POST_SYNC);
1057 shutdownhook_establish(my_shutdown, sc);
1065 /*mtx_destroy(&sc->my_mtx);*/
1071 my_detach(device_t dev)
1073 struct my_softc *sc;
1078 sc = device_get_softc(dev);
1080 ifp = &sc->arpcom.ac_if;
1081 ether_ifdetach(ifp);
1085 bus_generic_detach(dev);
1086 device_delete_child(dev, sc->rl_miibus);
1089 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand);
1090 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
1091 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
1093 contigfree(sc->my_cdata.my_rx_buf, MY_RXBUFLEN + 32, M_DEVBUF);
1098 /*mtx_destroy(&sc->my_mtx);*/
1104 * Initialize the transmit descriptors.
1107 my_list_tx_init(struct my_softc * sc)
1109 struct my_chain_data *cd;
1110 struct my_list_data *ld;
1116 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1117 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i];
1118 if (i == (MY_TX_LIST_CNT - 1))
1119 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0];
1121 cd->my_tx_chain[i].my_nextdesc =
1122 &cd->my_tx_chain[i + 1];
1124 cd->my_tx_free = &cd->my_tx_chain[0];
1125 cd->my_tx_tail = cd->my_tx_head = NULL;
1131 * Initialize the RX descriptors and allocate mbufs for them. Note that we
1132 * arrange the descriptors in a closed ring, so that the last descriptor
1133 * points back to the first.
1136 my_list_rx_init(struct my_softc * sc)
1138 struct my_chain_data *cd;
1139 struct my_list_data *ld;
1145 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1146 cd->my_rx_chain[i].my_ptr =
1147 (struct my_desc *) & ld->my_rx_list[i];
1148 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS)
1150 if (i == (MY_RX_LIST_CNT - 1)) {
1151 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0];
1152 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]);
1154 cd->my_rx_chain[i].my_nextdesc =
1155 &cd->my_rx_chain[i + 1];
1156 ld->my_rx_list[i].my_next =
1157 vtophys(&ld->my_rx_list[i + 1]);
1160 cd->my_rx_head = &cd->my_rx_chain[0];
1166 * Initialize an RX descriptor and attach an MBUF cluster.
1169 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c)
1171 struct mbuf *m_new = NULL;
1174 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1175 if (m_new == NULL) {
1176 printf("my%d: no memory for rx list -- packet dropped!\n",
1180 MCLGET(m_new, MB_DONTWAIT);
1181 if (!(m_new->m_flags & M_EXT)) {
1182 printf("my%d: no memory for rx list -- packet dropped!\n",
1188 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t));
1189 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift;
1190 c->my_ptr->my_status = MY_OWNByNIC;
1196 * A frame has been uploaded: pass the resulting mbuf chain up to the higher
1200 my_rxeof(struct my_softc * sc)
1202 struct ether_header *eh;
1205 struct my_chain_onefrag *cur_rx;
1210 ifp = &sc->arpcom.ac_if;
1211 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status)
1213 cur_rx = sc->my_cdata.my_rx_head;
1214 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc;
1216 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */
1218 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1221 /* No errors; receive the packet. */
1222 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift;
1223 total_len -= ETHER_CRC_LEN;
1225 if (total_len < MINCLSIZE) {
1226 m = m_devget(mtod(cur_rx->my_mbuf, char *),
1227 total_len, 0, ifp, NULL);
1228 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1234 m = cur_rx->my_mbuf;
1236 * Try to conjure up a new mbuf cluster. If that
1237 * fails, it means we have an out of memory condition
1238 * and should leave the buffer in place and continue.
1239 * This will result in a lost packet, but there's
1240 * little else we can do in this situation.
1242 if (my_newbuf(sc, cur_rx) == ENOBUFS) {
1244 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1247 m->m_pkthdr.rcvif = ifp;
1248 m->m_pkthdr.len = m->m_len = total_len;
1251 eh = mtod(m, struct ether_header *);
1254 * Handle BPF listeners. Let the BPF user see the packet, but
1255 * don't pass it up to the ether_input() layer unless it's a
1256 * broadcast packet, multicast packet, matches our ethernet
1257 * address or the interface is in promiscuous mode.
1261 if (ifp->if_flags & IFF_PROMISC &&
1262 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
1264 (eh->ether_dhost[0] & 1) == 0)) {
1270 /* Remove header from mbuf and pass it on. */
1271 m_adj(m, sizeof(struct ether_header));
1272 ether_input(ifp, eh, m);
1280 * A frame was downloaded to the chip. It's safe for us to clean up the list
1284 my_txeof(struct my_softc * sc)
1286 struct my_chain *cur_tx;
1290 ifp = &sc->arpcom.ac_if;
1291 /* Clear the timeout timer. */
1293 if (sc->my_cdata.my_tx_head == NULL)
1296 * Go through our tx list and free mbufs for those frames that have
1299 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) {
1302 cur_tx = sc->my_cdata.my_tx_head;
1303 txstat = MY_TXSTATUS(cur_tx);
1304 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT)
1306 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) {
1307 if (txstat & MY_TXERR) {
1309 if (txstat & MY_EC) /* excessive collision */
1310 ifp->if_collisions++;
1311 if (txstat & MY_LC) /* late collision */
1312 ifp->if_collisions++;
1314 ifp->if_collisions += (txstat & MY_NCRMASK) >>
1318 m_freem(cur_tx->my_mbuf);
1319 cur_tx->my_mbuf = NULL;
1320 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) {
1321 sc->my_cdata.my_tx_head = NULL;
1322 sc->my_cdata.my_tx_tail = NULL;
1325 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc;
1327 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) {
1328 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask);
1335 * TX 'end of channel' interrupt handler.
1338 my_txeoc(struct my_softc * sc)
1343 ifp = &sc->arpcom.ac_if;
1345 if (sc->my_cdata.my_tx_head == NULL) {
1346 ifp->if_flags &= ~IFF_OACTIVE;
1347 sc->my_cdata.my_tx_tail = NULL;
1348 if (sc->my_want_auto)
1349 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1351 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) {
1352 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC;
1354 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF);
1364 struct my_softc *sc;
1370 ifp = &sc->arpcom.ac_if;
1371 if (!(ifp->if_flags & IFF_UP)) {
1375 /* Disable interrupts. */
1376 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1379 status = CSR_READ_4(sc, MY_ISR);
1382 CSR_WRITE_4(sc, MY_ISR, status);
1386 if (status & MY_RI) /* receive interrupt */
1389 if ((status & MY_RBU) || (status & MY_RxErr)) {
1390 /* rx buffer unavailable or rx error */
1398 if (status & MY_TI) /* tx interrupt */
1400 if (status & MY_ETI) /* tx early interrupt */
1402 if (status & MY_TBU) /* tx buffer unavailable */
1405 #if 0 /* 90/1/18 delete */
1406 if (status & MY_FBE) {
1414 /* Re-enable interrupts. */
1415 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1416 if (ifp->if_snd.ifq_head != NULL)
1423 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1424 * pointers to the fragment pointers.
1427 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head)
1429 struct my_desc *f = NULL;
1431 struct mbuf *m, *m_new = NULL;
1434 /* calculate the total tx pkt length */
1436 for (m = m_head; m != NULL; m = m->m_next)
1437 total_len += m->m_len;
1439 * Start packing the mbufs in this chain into the fragment pointers.
1440 * Stop when we run out of fragments or hit the end of the mbuf
1444 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1445 if (m_new == NULL) {
1446 printf("my%d: no memory for tx list", sc->my_unit);
1449 if (m_head->m_pkthdr.len > MHLEN) {
1450 MCLGET(m_new, MB_DONTWAIT);
1451 if (!(m_new->m_flags & M_EXT)) {
1453 printf("my%d: no memory for tx list", sc->my_unit);
1457 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1458 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1461 f = &c->my_ptr->my_frag[0];
1463 f->my_data = vtophys(mtod(m_new, caddr_t));
1464 total_len = m_new->m_len;
1465 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable;
1466 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */
1467 f->my_ctl |= total_len; /* buffer size */
1468 /* 89/12/29 add, for mtd891 *//* [ 89? ] */
1469 if (sc->my_info->my_did == MTD891ID)
1470 f->my_ctl |= MY_ETIControl | MY_RetryTxLC;
1471 c->my_mbuf = m_head;
1473 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]);
1479 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1480 * to the mbuf data regions directly in the transmit lists. We also save a
1481 * copy of the pointers since the transmit list fragment pointers are
1482 * physical addresses.
1485 my_start(struct ifnet * ifp)
1487 struct my_softc *sc;
1488 struct mbuf *m_head = NULL;
1489 struct my_chain *cur_tx = NULL, *start_tx;
1493 if (sc->my_autoneg) {
1499 * Check for an available queue slot. If there are none, punt.
1501 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) {
1502 ifp->if_flags |= IFF_OACTIVE;
1506 start_tx = sc->my_cdata.my_tx_free;
1507 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) {
1508 IF_DEQUEUE(&ifp->if_snd, m_head);
1512 /* Pick a descriptor off the free list. */
1513 cur_tx = sc->my_cdata.my_tx_free;
1514 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc;
1516 /* Pack the data into the descriptor. */
1517 my_encap(sc, cur_tx, m_head);
1519 if (cur_tx != start_tx)
1520 MY_TXOWN(cur_tx) = MY_OWNByNIC;
1523 * If there's a BPF listener, bounce a copy of this frame to
1527 bpf_mtap(ifp, cur_tx->my_mbuf);
1531 * If there are no packets queued, bail.
1533 if (cur_tx == NULL) {
1538 * Place the request for the upload interrupt in the last descriptor
1539 * in the chain. This way, if we're chaining several packets at once,
1540 * we'll only get an interupt once for the whole chain rather than
1541 * once for each packet.
1543 MY_TXCTL(cur_tx) |= MY_TXIC;
1544 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC;
1545 sc->my_cdata.my_tx_tail = cur_tx;
1546 if (sc->my_cdata.my_tx_head == NULL)
1547 sc->my_cdata.my_tx_head = start_tx;
1548 MY_TXOWN(start_tx) = MY_OWNByNIC;
1549 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */
1552 * Set a timeout in case the chip goes out to lunch.
1562 struct my_softc *sc = xsc;
1563 struct ifnet *ifp = &sc->arpcom.ac_if;
1565 u_int16_t phy_bmcr = 0;
1568 if (sc->my_autoneg) {
1573 if (sc->my_pinfo != NULL)
1574 phy_bmcr = my_phy_readreg(sc, PHY_BMCR);
1576 * Cancel pending I/O and free all RX/TX buffers.
1582 * Set cache alignment and burst length.
1584 #if 0 /* 89/9/1 modify, */
1585 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512);
1586 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF);
1588 CSR_WRITE_4(sc, MY_BCR, MY_PBL8);
1589 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512);
1591 * 89/12/29 add, for mtd891,
1593 if (sc->my_info->my_did == MTD891ID) {
1594 MY_SETBIT(sc, MY_BCR, MY_PROG);
1595 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced);
1597 my_setcfg(sc, phy_bmcr);
1598 /* Init circular RX list. */
1599 if (my_list_rx_init(sc) == ENOBUFS) {
1600 printf("my%d: init failed: no memory for rx buffers\n",
1607 /* Init TX descriptors. */
1608 my_list_tx_init(sc);
1610 /* If we want promiscuous mode, set the allframes bit. */
1611 if (ifp->if_flags & IFF_PROMISC)
1612 MY_SETBIT(sc, MY_TCRRCR, MY_PROM);
1614 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM);
1617 * Set capture broadcast bit to capture broadcast frames.
1619 if (ifp->if_flags & IFF_BROADCAST)
1620 MY_SETBIT(sc, MY_TCRRCR, MY_AB);
1622 MY_CLRBIT(sc, MY_TCRRCR, MY_AB);
1625 * Program the multicast filter, if necessary.
1630 * Load the address of the RX list.
1632 MY_CLRBIT(sc, MY_TCRRCR, MY_RE);
1633 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0]));
1636 * Enable interrupts.
1638 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1639 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF);
1641 /* Enable receiver and transmitter. */
1642 MY_SETBIT(sc, MY_TCRRCR, MY_RE);
1643 MY_CLRBIT(sc, MY_TCRRCR, MY_TE);
1644 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0]));
1645 MY_SETBIT(sc, MY_TCRRCR, MY_TE);
1647 /* Restore state of BMCR */
1648 if (sc->my_pinfo != NULL)
1649 my_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1650 ifp->if_flags |= IFF_RUNNING;
1651 ifp->if_flags &= ~IFF_OACTIVE;
1658 * Set media options.
1662 my_ifmedia_upd(struct ifnet * ifp)
1664 struct my_softc *sc;
1665 struct ifmedia *ifm;
1670 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
1674 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1675 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1677 my_setmode_mii(sc, ifm->ifm_media);
1683 * Report current media status.
1687 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr)
1689 struct my_softc *sc;
1690 u_int16_t advert = 0, ability = 0;
1694 ifmr->ifm_active = IFM_ETHER;
1695 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1696 #if 0 /* this version did not support 1000M, */
1697 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000)
1698 ifmr->ifm_active = IFM_ETHER | IFM_1000TX;
1700 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1701 ifmr->ifm_active = IFM_ETHER | IFM_100_TX;
1703 ifmr->ifm_active = IFM_ETHER | IFM_10_T;
1704 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1705 ifmr->ifm_active |= IFM_FDX;
1707 ifmr->ifm_active |= IFM_HDX;
1712 ability = my_phy_readreg(sc, PHY_LPAR);
1713 advert = my_phy_readreg(sc, PHY_ANAR);
1715 #if 0 /* this version did not support 1000M, */
1716 if (sc->my_pinfo->my_vid = MarvellPHYID0) {
1717 ability2 = my_phy_readreg(sc, PHY_1000SR);
1718 if (ability2 & PHY_1000SR_1000BTXFULL) {
1721 ifmr->ifm_active = IFM_ETHER|IFM_1000_TX|IFM_FDX;
1722 } else if (ability & PHY_1000SR_1000BTXHALF) {
1725 ifmr->ifm_active = IFM_ETHER|IFM_1000_TX|IFM_HDX;
1729 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4)
1730 ifmr->ifm_active = IFM_ETHER | IFM_100_T4;
1731 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL)
1732 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1733 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF)
1734 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
1735 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL)
1736 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX;
1737 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF)
1738 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX;
1744 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data, struct ucred *cr)
1746 struct my_softc *sc = ifp->if_softc;
1747 struct ifreq *ifr = (struct ifreq *) data;
1756 error = ether_ioctl(ifp, command, data);
1759 if (ifp->if_flags & IFF_UP)
1761 else if (ifp->if_flags & IFF_RUNNING)
1772 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1784 my_watchdog(struct ifnet * ifp)
1786 struct my_softc *sc;
1790 if (sc->my_autoneg) {
1791 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1);
1796 printf("my%d: watchdog timeout\n", sc->my_unit);
1797 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1798 printf("my%d: no carrier - transceiver cable problem?\n",
1803 if (ifp->if_snd.ifq_head != NULL)
1811 * Stop the adapter and free any mbufs allocated to the RX and TX lists.
1814 my_stop(struct my_softc * sc)
1820 ifp = &sc->arpcom.ac_if;
1823 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE));
1824 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1825 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000);
1826 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000);
1829 * Free data in the RX lists.
1831 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1832 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) {
1833 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf);
1834 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL;
1837 bzero((char *)&sc->my_ldata->my_rx_list,
1838 sizeof(sc->my_ldata->my_rx_list));
1840 * Free the TX list buffers.
1842 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1843 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) {
1844 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf);
1845 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL;
1848 bzero((char *)&sc->my_ldata->my_tx_list,
1849 sizeof(sc->my_ldata->my_tx_list));
1850 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1856 * Stop all chip I/O so that the kernel's probe routines don't get confused
1857 * by errant DMAs when rebooting.
1860 my_shutdown(device_t dev)
1862 struct my_softc *sc;
1864 sc = device_get_softc(dev);