2 * Copyright (c) 1996 - 2001 John Hay.
3 * Copyright (c) 1996 SDL Communications, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of the author nor the names of any co-contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * $FreeBSD: src/sys/dev/sr/if_sr.c,v 1.48.2.1 2002/06/17 15:10:58 jhay Exp $
31 * $DragonFly: src/sys/dev/netif/sr/if_sr.c,v 1.14 2005/05/24 20:59:02 dillon Exp $
35 * Programming assumptions and other issues.
37 * Only a 16K window will be used.
39 * The descriptors of a DMA channel will fit in a 16K memory window.
41 * The buffers of a transmit DMA channel will fit in a 16K memory window.
43 * When interface is going up, handshaking is set and it is only cleared
44 * when the interface is down'ed.
46 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE,
47 * internal/external clock, etc.....
51 #include "opt_netgraph.h"
56 #include <sys/param.h>
57 #include <sys/systm.h>
58 #include <sys/kernel.h>
59 #include <sys/malloc.h>
61 #include <sys/sockio.h>
62 #include <sys/socket.h>
64 #include <machine/bus.h>
65 #include <machine/resource.h>
66 #include <machine/bus_pio.h>
67 #include <machine/bus_memio.h>
72 #include <sys/syslog.h>
74 #include <net/sppp/if_sppp.h>
79 #include <machine/md_var.h>
81 #include "../ic_layer/hd64570.h"
82 #include "if_srregs.h"
85 #include <netgraph/ng_message.h>
86 #include <netgraph/netgraph.h>
88 /* #define USE_MODEMCK */
95 #define PPP_HEADER_LEN 4
98 static int next_sc_unit = 0;
101 static int sr_watcher = 0;
103 #endif /* NETGRAPH */
106 * Define the software interface for the card... There is one for
107 * every channel (port).
111 struct sppp ifsppp; /* PPP service w/in system */
112 #endif /* NETGRAPH */
113 struct sr_hardc *hc; /* card-level information */
115 int unit; /* With regard to all sr devices */
116 int subunit; /* With regard to this card */
119 u_int txdesc; /* DPRAM offset */
120 u_int txstart;/* DPRAM offset */
121 u_int txend; /* DPRAM offset */
122 u_int txtail; /* # of 1st free gran */
123 u_int txmax; /* # of free grans */
124 u_int txeda; /* err descr addr */
125 } block[SR_TX_BLOCKS];
127 char xmit_busy; /* Transmitter is busy */
128 char txb_inuse; /* # of tx grans in use */
129 u_int txb_new; /* ndx to new buffer */
130 u_int txb_next_tx; /* ndx to next gran rdy tx */
132 u_int rxdesc; /* DPRAM offset */
133 u_int rxstart; /* DPRAM offset */
134 u_int rxend; /* DPRAM offset */
135 u_int rxhind; /* ndx to the hd of rx bufrs */
136 u_int rxmax; /* # of avail grans */
138 u_int clk_cfg; /* Clock configuration */
140 int scachan; /* channel # on card */
142 int running; /* something is attached so we are running */
143 int dcd; /* do we have dcd? */
144 /* ---netgraph bits --- */
145 char nodename[NG_NODELEN + 1]; /* store our node name */
146 int datahooks; /* number of data hooks attached */
147 node_p node; /* netgraph node */
148 hook_p hook; /* data hook */
150 struct ifqueue xmitq_hipri; /* hi-priority transmit queue */
151 struct ifqueue xmitq; /* transmit queue */
152 int flags; /* state */
153 #define SCF_RUNNING 0x01 /* board is active */
154 #define SCF_OACTIVE 0x02 /* output is active */
155 int out_dog; /* watchdog cycles output count-down */
156 struct callout sr_timer; /* timeout(9) handle */
157 u_long inbytes, outbytes; /* stats */
158 u_long lastinbytes, lastoutbytes; /* a second ago */
159 u_long inrate, outrate; /* highest rate seen */
160 u_long inlast; /* last input N secs ago */
161 u_long out_deficit; /* output since last input */
162 u_long oerrors, ierrors[6];
163 u_long opackets, ipackets;
164 #endif /* NETGRAPH */
168 #define DOG_HOLDOFF 6 /* dog holds off for 6 secs */
169 #define QUITE_A_WHILE 300 /* 5 MINUTES */
170 #define LOTS_OF_PACKETS 100
171 #endif /* NETGRAPH */
174 * Baud Rate table for Sync Mode.
175 * Each entry consists of 3 elements:
176 * Baud Rate (x100) , TMC, BR
178 * Baud Rate = FCLK / TMC / 2^BR
179 * Baud table for Crystal freq. of 9.8304 Mhz
183 int target; /* target rate/100 */
184 int tmc_reg; /* TMC register value */
185 int br_reg; /* BR (BaudRateClk) selector */
187 /* Baudx100 TMC BR */
208 int sr_test_speed[] = {
214 SR_MCR_ETC0, /* ISA channel 0 */
215 SR_MCR_ETC1, /* ISA channel 1 */
216 SR_FECR_ETC0, /* PCI channel 0 */
217 SR_FECR_ETC1 /* PCI channel 1 */
221 devclass_t sr_devclass;
223 DECLARE_DUMMY_MODULE(if_sr);
224 MODULE_DEPEND(if_sr, sppp, 1, 1, 1);
226 MODULE_DEPEND(ng_sync_sr, netgraph, 1, 1, 1);
229 static void srintr(void *arg);
230 static void sr_xmit(struct sr_softc *sc);
232 static void srstart(struct ifnet *ifp);
233 static int srioctl(struct ifnet *ifp, u_long cmd, caddr_t data,
235 static void srwatchdog(struct ifnet *ifp);
237 static void srstart(struct sr_softc *sc);
238 static void srwatchdog(struct sr_softc *sc);
239 #endif /* NETGRAPH */
240 static int sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat);
241 static void sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len);
242 static void sr_eat_packet(struct sr_softc *sc, int single);
243 static void sr_get_packets(struct sr_softc *sc);
245 static void sr_up(struct sr_softc *sc);
246 static void sr_down(struct sr_softc *sc);
247 static void src_init(struct sr_hardc *hc);
248 static void sr_init_sca(struct sr_hardc *hc);
249 static void sr_init_msci(struct sr_softc *sc);
250 static void sr_init_rx_dmac(struct sr_softc *sc);
251 static void sr_init_tx_dmac(struct sr_softc *sc);
252 static void sr_dmac_intr(struct sr_hardc *hc, u_char isr);
253 static void sr_msci_intr(struct sr_hardc *hc, u_char isr);
254 static void sr_timer_intr(struct sr_hardc *hc, u_char isr);
257 static void sr_modemck(void *x);
260 static void sr_modemck(struct sr_softc *x);
261 #endif /* NETGRAPH */
264 static void ngsr_watchdog_frame(void * arg);
265 static void ngsr_init(void* ignored);
267 static ng_constructor_t ngsr_constructor;
268 static ng_rcvmsg_t ngsr_rcvmsg;
269 static ng_shutdown_t ngsr_rmnode;
270 static ng_newhook_t ngsr_newhook;
271 /*static ng_findhook_t ngsr_findhook; */
272 static ng_connect_t ngsr_connect;
273 static ng_rcvdata_t ngsr_rcvdata;
274 static ng_disconnect_t ngsr_disconnect;
276 static struct ng_type typestruct = {
292 static int ngsr_done_init = 0;
293 #endif /* NETGRAPH */
296 * Register the ports on the adapter.
297 * Fill in the info for each port.
299 * Attach each port to sppp and bpf.
303 sr_attach(device_t device)
312 #endif /* NETGRAPH */
313 int unit; /* index: channel w/in card */
315 hc = (struct sr_hardc *)device_get_softc(device);
316 MALLOC(sc, struct sr_softc *,
317 hc->numports * sizeof(struct sr_softc),
318 M_DEVBUF, M_WAITOK | M_ZERO);
324 * Get the TX clock direction and configuration. The default is a
325 * single external clock which is used by RX and TX.
327 switch(hc->cardtype) {
329 flags = device_get_flags(device);
331 if (sr_test_speed[0] > 0)
332 hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
335 if (flags & SR_FLAGS_0_CLK_MSK)
337 (flags & SR_FLAGS_0_CLK_MSK)
338 >> SR_FLAGS_CLK_SHFT;
340 if (hc->numports == 2)
342 if (sr_test_speed[1] > 0)
343 hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
346 if (flags & SR_FLAGS_1_CLK_MSK)
347 hc->sc[1].clk_cfg = (flags & SR_FLAGS_1_CLK_MSK)
348 >> (SR_FLAGS_CLK_SHFT +
349 SR_FLAGS_CLK_CHAN_SHFT);
352 fecrp = (u_int *)(hc->sca_base + SR_FECR);
354 for (pndx = 0; pndx < hc->numports; pndx++, sc++) {
357 intf_sw = fecr & SR_FECR_ID1 >> SR_FE_ID1_SHFT;
361 intf_sw = fecr & SR_FECR_ID0 >> SR_FE_ID0_SHFT;
365 if (sr_test_speed[pndx] > 0)
366 sc->clk_cfg = SR_FLAGS_INT_CLK;
378 sc->clk_cfg = SR_FLAGS_EXT_SEP_CLK;
382 sc->clk_cfg = SR_FLAGS_EXT_CLK;
391 * Report Card configuration information before we start configuring
392 * each channel on the card...
394 printf("src%d: %uK RAM (%d mempages) @ %08x-%08x, %u ports.\n",
395 hc->cunit, hc->memsize / 1024, hc->mempages,
396 (u_int)hc->mem_start, (u_int)hc->mem_end, hc->numports);
401 if (BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq,
402 INTR_TYPE_NET, srintr, hc,
403 &hc->intr_cookie, NULL) != 0)
407 * Now configure each port on the card.
409 for (unit = 0; unit < hc->numports; sc++, unit++) {
412 sc->unit = next_sc_unit;
414 sc->scachan = unit % NCHAN;
420 printf("sr%d: Adapter %d, port %d.\n",
421 sc->unit, hc->cunit, sc->subunit);
424 ifp = &sc->ifsppp.pp_if;
426 if_initname(ifp, "sr", sc->unit);
427 ifp->if_mtu = PP_MTU;
428 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST;
429 ifp->if_ioctl = srioctl;
430 ifp->if_start = srstart;
431 ifp->if_watchdog = srwatchdog;
433 sc->ifsppp.pp_flags = PP_KEEPALIVE;
434 sppp_attach((struct ifnet *)&sc->ifsppp);
437 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN);
440 * we have found a node, make sure our 'type' is availabe.
442 if (ngsr_done_init == 0) ngsr_init(NULL);
443 if (ng_make_node_common(&typestruct, &sc->node) != 0)
445 sc->node->private = sc;
446 callout_init(&sc->sr_timer);
447 sc->xmitq.ifq_maxlen = IFQ_MAXLEN;
448 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN;
449 sprintf(sc->nodename, "%s%d", NG_SR_NODE_TYPE, sc->unit);
450 if (ng_name_node(sc->node, sc->nodename)) {
456 #endif /* NETGRAPH */
460 SRC_SET_OFF(hc->iobase);
465 sr_deallocate_resources(device);
470 sr_detach(device_t device)
472 device_t parent = device_get_parent(device);
473 struct sr_hardc *hc = device_get_softc(device);
475 if (hc->intr_cookie != NULL) {
476 if (BUS_TEARDOWN_INTR(parent, device,
477 hc->res_irq, hc->intr_cookie) != 0) {
478 printf("intr teardown failed.. continuing\n");
480 hc->intr_cookie = NULL;
483 /* XXX Stop the DMA. */
486 * deallocate any system resources we may have
487 * allocated on behalf of this driver.
489 FREE(hc->sc, M_DEVBUF);
491 hc->mem_start = NULL;
492 return (sr_deallocate_resources(device));
496 sr_allocate_ioport(device_t device, int rid, u_long size)
498 struct sr_hardc *hc = device_get_softc(device);
500 hc->rid_ioport = rid;
501 hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT,
502 &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE);
503 if (hc->res_ioport == NULL) {
509 sr_deallocate_resources(device);
514 sr_allocate_irq(device_t device, int rid, u_long size)
516 struct sr_hardc *hc = device_get_softc(device);
519 hc->res_irq = bus_alloc_resource_any(device, SYS_RES_IRQ,
520 &hc->rid_irq, RF_SHAREABLE|RF_ACTIVE);
521 if (hc->res_irq == NULL) {
527 sr_deallocate_resources(device);
532 sr_allocate_memory(device_t device, int rid, u_long size)
534 struct sr_hardc *hc = device_get_softc(device);
536 hc->rid_memory = rid;
537 hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
538 &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE);
539 if (hc->res_memory == NULL) {
545 sr_deallocate_resources(device);
550 sr_allocate_plx_memory(device_t device, int rid, u_long size)
552 struct sr_hardc *hc = device_get_softc(device);
554 hc->rid_plx_memory = rid;
555 hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
556 &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE);
557 if (hc->res_plx_memory == NULL) {
563 sr_deallocate_resources(device);
568 sr_deallocate_resources(device_t device)
570 struct sr_hardc *hc = device_get_softc(device);
572 if (hc->res_irq != 0) {
573 bus_deactivate_resource(device, SYS_RES_IRQ,
574 hc->rid_irq, hc->res_irq);
575 bus_release_resource(device, SYS_RES_IRQ,
576 hc->rid_irq, hc->res_irq);
579 if (hc->res_ioport != 0) {
580 bus_deactivate_resource(device, SYS_RES_IOPORT,
581 hc->rid_ioport, hc->res_ioport);
582 bus_release_resource(device, SYS_RES_IOPORT,
583 hc->rid_ioport, hc->res_ioport);
586 if (hc->res_memory != 0) {
587 bus_deactivate_resource(device, SYS_RES_MEMORY,
588 hc->rid_memory, hc->res_memory);
589 bus_release_resource(device, SYS_RES_MEMORY,
590 hc->rid_memory, hc->res_memory);
593 if (hc->res_plx_memory != 0) {
594 bus_deactivate_resource(device, SYS_RES_MEMORY,
595 hc->rid_plx_memory, hc->res_plx_memory);
596 bus_release_resource(device, SYS_RES_MEMORY,
597 hc->rid_plx_memory, hc->res_plx_memory);
598 hc->res_plx_memory = 0;
604 * N2 Interrupt Service Routine
606 * First figure out which SCA gave the interrupt.
608 * See if there is other interrupts pending.
609 * Repeat until there no interrupts remain.
614 struct sr_hardc *hc = (struct sr_hardc *)arg;
615 sca_regs *sca = hc->sca; /* MSCI register tree */
616 u_char isr0, isr1, isr2; /* interrupt statii captured */
619 printf("sr: srintr_hc(hc=%08x)\n", hc);
623 * Since multiple interfaces may share this interrupt, we must loop
624 * until no interrupts are still pending service.
628 * Read all three interrupt status registers from the N2
631 isr0 = SRC_GET8(hc->sca_base, sca->isr0);
632 isr1 = SRC_GET8(hc->sca_base, sca->isr1);
633 isr2 = SRC_GET8(hc->sca_base, sca->isr2);
636 * If all three registers returned 0, we've finished
637 * processing interrupts from this device, so we can quit
640 if ((isr0 | isr1 | isr2) == 0)
644 printf("src%d: srintr_hc isr0 %x, isr1 %x, isr2 %x\n",
646 unit, isr0, isr1, isr2);
648 hc->cunit, isr0, isr1, isr2);
649 #endif /* NETGRAPH */
653 * Now we can dispatch the interrupts. Since we don't expect
654 * either MSCI or timer interrupts, we'll test for DMA
655 * interrupts first...
657 if (isr1) /* DMA-initiated interrupt */
658 sr_dmac_intr(hc, isr1);
660 if (isr0) /* serial part IRQ? */
661 sr_msci_intr(hc, isr0);
663 if (isr2) /* timer-initiated interrupt */
664 sr_timer_intr(hc, isr2);
669 * This will only start the transmitter. It is assumed that the data
671 * It is normally called from srstart() or sr_dmac_intr().
674 sr_xmit(struct sr_softc *sc)
676 u_short cda_value; /* starting descriptor */
677 u_short eda_value; /* ending descriptor */
680 struct ifnet *ifp; /* O/S Network Services */
681 #endif /* NETGRAPH */
682 dmac_channel *dmac; /* DMA channel registers */
685 printf("sr: sr_xmit( sc=%08x)\n", sc);
690 ifp = &sc->ifsppp.pp_if;
691 #endif /* NETGRAPH */
692 dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];
695 * Get the starting and ending addresses of the chain to be
696 * transmitted and pass these on to the DMA engine on-chip.
698 cda_value = sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart;
699 cda_value &= 0x00ffff;
700 eda_value = sc->block[sc->txb_next_tx].txeda + hc->mem_pstart;
701 eda_value &= 0x00ffff;
703 SRC_PUT16(hc->sca_base, dmac->cda, cda_value);
704 SRC_PUT16(hc->sca_base, dmac->eda, eda_value);
707 * Now we'll let the DMA status register know about this change
709 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);
711 sc->xmit_busy = 1; /* mark transmitter busy */
714 printf("sr%d: XMIT cda=%04x, eda=%4x, rcda=%08lx\n",
715 sc->unit, cda_value, eda_value,
716 sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart);
719 sc->txb_next_tx++; /* update next transmit seq# */
721 if (sc->txb_next_tx == SR_TX_BLOCKS) /* handle wrap... */
726 * Finally, we'll set a timout (which will start srwatchdog())
727 * within the O/S network services layer...
729 ifp->if_timer = 2; /* Value in seconds. */
732 * Don't time out for a while.
734 sc->out_dog = DOG_HOLDOFF; /* give ourself some breathing space*/
735 #endif /* NETGRAPH */
739 * This function will be called from the upper level when a user add a
740 * packet to be send, and from the interrupt handler after a finished
743 * NOTE: it should run at spl_imp().
745 * This function only place the data in the oncard buffers. It does not
746 * start the transmition. sr_xmit() does that.
748 * Transmitter idle state is indicated by the IFF_OACTIVE flag.
749 * The function that clears that should ensure that the transmitter
750 * and its DMA is in a "good" idle state.
754 srstart(struct ifnet *ifp)
756 struct sr_softc *sc; /* channel control structure */
759 srstart(struct sr_softc *sc)
761 #endif /* NETGRAPH */
762 struct sr_hardc *hc; /* card control/config block */
763 int len; /* total length of a packet */
764 int pkts; /* packets placed in DPRAM */
765 int tlen; /* working length of pkt */
767 struct mbuf *mtx; /* message buffer from O/S */
768 u_char *txdata; /* buffer address in DPRAM */
769 sca_descriptor *txdesc; /* working descriptor pointr */
770 struct buf_block *blkp;
774 printf("sr: srstart( ifp=%08x)\n", ifp);
777 if ((ifp->if_flags & IFF_RUNNING) == 0)
779 #endif /* NETGRAPH */
782 * It is OK to set the memory window outside the loop because all tx
783 * buffers and descriptors are assumed to be in the same 16K window.
786 SRC_SET_ON(hc->iobase);
787 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc);
791 * Loop to place packets into DPRAM.
793 * We stay in this loop until there is nothing in
794 * the TX queue left or the tx buffers are full.
799 * See if we have space for more packets.
801 if (sc->txb_inuse == SR_TX_BLOCKS) { /* out of space? */
803 ifp->if_flags |= IFF_OACTIVE; /* yes, mark active */
805 /*ifp->if_flags |= IFF_OACTIVE;*/ /* yes, mark active */
806 #endif /* NETGRAPH */
809 SRC_SET_OFF(hc->iobase);
812 printf("sr%d.srstart: sc->txb_inuse=%d; DPRAM full...\n",
813 sc->unit, sc->txb_inuse);
818 * OK, the card can take more traffic. Let's see if there's any
819 * pending from the system...
822 * The architecture of the networking interface doesn't
823 * actually call us like 'write()', providing an address. We get
824 * started, a lot like a disk strategy routine, and we actually call
825 * back out to the system to get traffic to send...
828 * If we were gonna run through another layer, we would use a
829 * dispatch table to select the service we're getting a packet
833 mtx = sppp_dequeue(ifp);
835 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
837 IF_DEQUEUE(&sc->xmitq, mtx);
839 #endif /* NETGRAPH */
842 SRC_SET_OFF(hc->iobase);
846 * OK, we got a packet from the network services of the O/S. Now we
847 * can move it into the DPRAM (under control of the descriptors) and
851 i = 0; /* counts # of granules used */
853 blkp = &sc->block[sc->txb_new]; /* address of free granule */
854 txdesc = (sca_descriptor *)
855 (hc->mem_start + (blkp->txdesc & hc->winmsk));
857 txdata = (u_char *)(hc->mem_start
858 + (blkp->txstart & hc->winmsk));
861 * Now we'll try to install as many packets as possible into the
862 * card's DP RAM buffers.
864 for (;;) { /* perform actual copy of packet */
865 len = mtx->m_pkthdr.len; /* length of message */
868 printf("sr%d.srstart: mbuf @ %08lx, %d bytes\n",
876 #endif /* NETGRAPH */
879 * We can perform a straight copy because the tranmit
880 * buffers won't wrap.
882 m_copydata(mtx, 0, len, txdata);
885 * Now we know how big the message is gonna be. We must now
886 * construct the descriptors to drive this message out...
889 while (tlen > SR_BUF_SIZ) { /* loop for full granules */
890 txdesc->stat = 0; /* reset bits */
891 txdesc->len = SR_BUF_SIZ; /* size of granule */
894 txdesc++; /* move to next dscr */
895 txdata += SR_BUF_SIZ; /* adjust data addr */
900 * This section handles the setting of the final piece of a
903 txdesc->stat = SCA_DESC_EOM;
908 * prepare for subsequent packets (if any)
911 txdata += SR_BUF_SIZ; /* next mem granule */
912 i++; /* count of granules */
915 * OK, we've now placed the message into the DPRAM where it
916 * can be transmitted. We'll now release the message memory
917 * and update the statistics...
921 ++sc->ifsppp.pp_if.if_opackets;
924 #endif /* NETGRAPH */
927 * Check if we have space for another packet. XXX This is
928 * hardcoded. A packet can't be larger than 3 buffers (3 x
931 if ((i + 3) >= blkp->txmax) { /* enough remains? */
933 printf("sr%d.srstart: i=%d (%d pkts); card full.\n",
939 * We'll pull the next message to be sent (if any)
942 mtx = sppp_dequeue(ifp);
944 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
946 IF_DEQUEUE(&sc->xmitq, mtx);
948 #endif /* NETGRAPH */
949 if (!mtx) { /* no message? We're done! */
951 printf("sr%d.srstart: pending=0, pkts=%d\n",
958 blkp->txtail = i; /* record next free granule */
961 * Mark the last descriptor, so that the SCA know where to stop.
963 txdesc--; /* back up to last descriptor in list */
964 txdesc->stat |= SCA_DESC_EOT; /* mark as end of list */
967 * Now we'll reset the transmit granule's descriptor address so we
968 * can record this in the structure and fire it off w/ the DMA
969 * processor of the serial chip...
971 txdesc = (sca_descriptor *)blkp->txdesc;
972 blkp->txeda = (u_short)((u_int)&txdesc[i]);
974 sc->txb_inuse++; /* update inuse status */
975 sc->txb_new++; /* new traffic wuz added */
977 if (sc->txb_new == SR_TX_BLOCKS)
981 * If the tranmitter wasn't marked as "busy" we will force it to be
984 if (sc->xmit_busy == 0) {
987 printf("sr%d.srstart: called sr_xmit()\n", sc->unit);
995 * Handle ioctl's at the device level, though we *will* call up
999 static int bug_splats[] = {0, 0, 0, 0, 0, 0, 0, 0};
1003 srioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1005 int s, error, was_up, should_be_up;
1006 struct sr_softc *sc = ifp->if_softc;
1009 printf("%s: srioctl(ifp=%08x, cmd=%08x, data=%08x)\n",
1010 ifp->if_xname, ifp, cmd, data);
1013 was_up = ifp->if_flags & IFF_RUNNING;
1015 error = sppp_ioctl(ifp, cmd, data);
1018 printf("%s: ioctl: ifsppp.pp_flags = %08x, if_flags %08x.\n",
1019 ifp->if_xname, ((struct sppp *)ifp)->pp_flags, ifp->if_flags);
1025 if ((cmd != SIOCSIFFLAGS) && (cmd != SIOCSIFADDR)) {
1027 if (bug_splats[sc->unit]++ < 2) {
1028 printf("sr(%d).if_addrlist = %08x\n",
1029 sc->unit, ifp->if_addrlist);
1030 printf("sr(%d).if_bpf = %08x\n",
1031 sc->unit, ifp->if_bpf);
1032 printf("sr(%d).if_init = %08x\n",
1033 sc->unit, ifp->if_init);
1034 printf("sr(%d).if_output = %08x\n",
1035 sc->unit, ifp->if_output);
1036 printf("sr(%d).if_start = %08x\n",
1037 sc->unit, ifp->if_start);
1038 printf("sr(%d).if_done = %08x\n",
1039 sc->unit, ifp->if_done);
1040 printf("sr(%d).if_ioctl = %08x\n",
1041 sc->unit, ifp->if_ioctl);
1042 printf("sr(%d).if_reset = %08x\n",
1043 sc->unit, ifp->if_reset);
1044 printf("sr(%d).if_watchdog = %08x\n",
1045 sc->unit, ifp->if_watchdog);
1052 should_be_up = ifp->if_flags & IFF_RUNNING;
1054 if (!was_up && should_be_up) {
1056 * Interface should be up -- start it.
1062 * XXX Clear the IFF_UP flag so that the link will only go
1063 * up after sppp lcp and ipcp negotiation.
1065 /* ifp->if_flags &= ~IFF_UP; */
1066 } else if (was_up && !should_be_up) {
1068 * Interface should be down -- stop it.
1076 #endif /* NETGRAPH */
1079 * This is to catch lost tx interrupts.
1083 srwatchdog(struct ifnet *ifp)
1085 srwatchdog(struct sr_softc *sc)
1086 #endif /* NETGRAPH */
1088 int got_st0, got_st1, got_st3, got_dsr;
1090 struct sr_softc *sc = ifp->if_softc;
1091 #endif /* NETGRAPH */
1092 struct sr_hardc *hc = sc->hc;
1093 msci_channel *msci = &hc->sca->msci[sc->scachan];
1094 dmac_channel *dmac = &sc->hc->sca->dmac[sc->scachan];
1098 printf("srwatchdog(unit=%d)\n", unit);
1100 printf("srwatchdog(unit=%d)\n", sc->unit);
1101 #endif /* NETGRAPH */
1105 if (!(ifp->if_flags & IFF_RUNNING))
1108 ifp->if_oerrors++; /* update output error count */
1109 #else /* NETGRAPH */
1110 sc->oerrors++; /* update output error count */
1111 #endif /* NETGRAPH */
1113 got_st0 = SRC_GET8(hc->sca_base, msci->st0);
1114 got_st1 = SRC_GET8(hc->sca_base, msci->st1);
1115 got_st3 = SRC_GET8(hc->sca_base, msci->st3);
1116 got_dsr = SRC_GET8(hc->sca_base, dmac->dsr);
1120 if (ifp->if_flags & IFF_DEBUG)
1122 printf("sr%d: transmit failed, "
1123 #else /* NETGRAPH */
1124 printf("sr%d: transmit failed, "
1125 #endif /* NETGRAPH */
1126 "ST0 %02x, ST1 %02x, ST3 %02x, DSR %02x.\n",
1128 got_st0, got_st1, got_st3, got_dsr);
1130 if (SRC_GET8(hc->sca_base, msci->st1) & SCA_ST1_UDRN) {
1131 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXABORT);
1132 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE);
1133 SRC_PUT8(hc->sca_base, msci->st1, SCA_ST1_UDRN);
1137 ifp->if_flags &= ~IFF_OACTIVE;
1139 /*ifp->if_flags &= ~IFF_OACTIVE; */
1140 #endif /* NETGRAPH */
1142 if (sc->txb_inuse && --sc->txb_inuse)
1146 srstart(ifp); /* restart transmitter */
1148 srstart(sc); /* restart transmitter */
1149 #endif /* NETGRAPH */
1153 sr_up(struct sr_softc *sc)
1156 struct sr_hardc *hc = sc->hc;
1157 sca_regs *sca = hc->sca;
1158 msci_channel *msci = &sca->msci[sc->scachan];
1161 printf("sr_up(sc=%08x)\n", sc);
1165 * Enable transmitter and receiver. Raise DTR and RTS. Enable
1168 * XXX What about using AUTO mode in msci->md0 ???
1170 SRC_PUT8(hc->sca_base, msci->ctl,
1171 SRC_GET8(hc->sca_base, msci->ctl) & ~SCA_CTL_RTS);
1173 if (sc->scachan == 0)
1174 switch (hc->cardtype) {
1176 outb(hc->iobase + SR_MCR,
1177 (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR0));
1180 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1181 *fecrp &= ~SR_FECR_DTR0;
1185 switch (hc->cardtype) {
1187 outb(hc->iobase + SR_MCR,
1188 (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR1));
1191 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1192 *fecrp &= ~SR_FECR_DTR1;
1196 if (sc->scachan == 0) {
1197 SRC_PUT8(hc->sca_base, sca->ier0,
1198 SRC_GET8(hc->sca_base, sca->ier0) | 0x000F);
1199 SRC_PUT8(hc->sca_base, sca->ier1,
1200 SRC_GET8(hc->sca_base, sca->ier1) | 0x000F);
1202 SRC_PUT8(hc->sca_base, sca->ier0,
1203 SRC_GET8(hc->sca_base, sca->ier0) | 0x00F0);
1204 SRC_PUT8(hc->sca_base, sca->ier1,
1205 SRC_GET8(hc->sca_base, sca->ier1) | 0x00F0);
1208 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXENABLE);
1209 inb(hc->iobase); /* XXX slow it down a bit. */
1210 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE);
1214 if (sr_watcher == 0)
1217 #else /* NETGRAPH */
1218 callout_reset(&sc->sr_timer, hz, ngsr_watchdog_frame, sc);
1220 #endif /* NETGRAPH */
1224 sr_down(struct sr_softc *sc)
1227 struct sr_hardc *hc = sc->hc;
1228 sca_regs *sca = hc->sca;
1229 msci_channel *msci = &sca->msci[sc->scachan];
1232 printf("sr_down(sc=%08x)\n", sc);
1235 callout_stop(&sc->sr_timer);
1237 #endif /* NETGRAPH */
1240 * Disable transmitter and receiver. Lower DTR and RTS. Disable
1243 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXDISABLE);
1244 inb(hc->iobase); /* XXX slow it down a bit. */
1245 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXDISABLE);
1247 SRC_PUT8(hc->sca_base, msci->ctl,
1248 SRC_GET8(hc->sca_base, msci->ctl) | SCA_CTL_RTS);
1250 if (sc->scachan == 0)
1251 switch (hc->cardtype) {
1253 outb(hc->iobase + SR_MCR,
1254 (inb(hc->iobase + SR_MCR) | SR_MCR_DTR0));
1257 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1258 *fecrp |= SR_FECR_DTR0;
1262 switch (hc->cardtype) {
1264 outb(hc->iobase + SR_MCR,
1265 (inb(hc->iobase + SR_MCR) | SR_MCR_DTR1));
1268 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1269 *fecrp |= SR_FECR_DTR1;
1273 if (sc->scachan == 0) {
1274 SRC_PUT8(hc->sca_base, sca->ier0,
1275 SRC_GET8(hc->sca_base, sca->ier0) & ~0x0F);
1276 SRC_PUT8(hc->sca_base, sca->ier1,
1277 SRC_GET8(hc->sca_base, sca->ier1) & ~0x0F);
1279 SRC_PUT8(hc->sca_base, sca->ier0,
1280 SRC_GET8(hc->sca_base, sca->ier0) & ~0xF0);
1281 SRC_PUT8(hc->sca_base, sca->ier1,
1282 SRC_GET8(hc->sca_base, sca->ier1) & ~0xF0);
1287 * Initialize the card, allocate memory for the sr_softc structures
1288 * and fill in the pointers.
1291 src_init(struct sr_hardc *hc)
1293 struct sr_softc *sc = hc->sc;
1301 printf("src_init(hc=%08x)\n", hc);
1304 chanmem = hc->memsize / hc->numports;
1307 for (x = 0; x < hc->numports; x++, sc++) {
1310 for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
1311 sc->block[blk].txdesc = next;
1312 bufmem = (16 * 1024) / SR_TX_BLOCKS;
1313 descneeded = bufmem / SR_BUF_SIZ;
1315 sc->block[blk].txstart = sc->block[blk].txdesc
1316 + ((((descneeded * sizeof(sca_descriptor))
1320 sc->block[blk].txend = next + bufmem;
1321 sc->block[blk].txmax =
1322 (sc->block[blk].txend - sc->block[blk].txstart)
1327 printf("sr%d: blk %d: txdesc %08x, txstart %08x\n",
1329 sc->block[blk].txdesc, sc->block[blk].txstart);
1334 bufmem = chanmem - (bufmem * SR_TX_BLOCKS);
1335 descneeded = bufmem / SR_BUF_SIZ;
1336 sc->rxstart = sc->rxdesc +
1337 ((((descneeded * sizeof(sca_descriptor)) /
1338 SR_BUF_SIZ) + 1) * SR_BUF_SIZ);
1339 sc->rxend = next + bufmem;
1340 sc->rxmax = (sc->rxend - sc->rxstart) / SR_BUF_SIZ;
1346 * The things done here are channel independent.
1348 * Configure the sca waitstates.
1349 * Configure the global interrupt registers.
1350 * Enable master dma enable.
1353 sr_init_sca(struct sr_hardc *hc)
1355 sca_regs *sca = hc->sca;
1358 printf("sr_init_sca(hc=%08x)\n", hc);
1362 * Do the wait registers. Set everything to 0 wait states.
1364 SRC_PUT8(hc->sca_base, sca->pabr0, 0);
1365 SRC_PUT8(hc->sca_base, sca->pabr1, 0);
1366 SRC_PUT8(hc->sca_base, sca->wcrl, 0);
1367 SRC_PUT8(hc->sca_base, sca->wcrm, 0);
1368 SRC_PUT8(hc->sca_base, sca->wcrh, 0);
1371 * Configure the interrupt registers. Most are cleared until the
1372 * interface is configured.
1374 SRC_PUT8(hc->sca_base, sca->ier0, 0x00); /* MSCI interrupts. */
1375 SRC_PUT8(hc->sca_base, sca->ier1, 0x00); /* DMAC interrupts */
1376 SRC_PUT8(hc->sca_base, sca->ier2, 0x00); /* TIMER interrupts. */
1377 SRC_PUT8(hc->sca_base, sca->itcr, 0x00); /* Use ivr and no intr
1379 SRC_PUT8(hc->sca_base, sca->ivr, 0x40); /* Interrupt vector. */
1380 SRC_PUT8(hc->sca_base, sca->imvr, 0x40);
1383 * Configure the timers. XXX Later
1387 * Set the DMA channel priority to rotate between all four channels.
1389 * Enable all dma channels.
1391 SRC_PUT8(hc->sca_base, sca->pcr, SCA_PCR_PR2);
1392 SRC_PUT8(hc->sca_base, sca->dmer, SCA_DMER_EN);
1396 * Configure the msci
1398 * NOTE: The serial port configuration is hardcoded at the moment.
1401 sr_init_msci(struct sr_softc *sc)
1403 int portndx; /* on-board port number */
1404 u_int mcr_v; /* contents of modem control */
1405 u_int *fecrp; /* pointer for PCI's MCR i/o */
1406 struct sr_hardc *hc = sc->hc;
1407 msci_channel *msci = &hc->sca->msci[sc->scachan];
1408 #ifdef N2_TEST_SPEED
1409 int br_v; /* contents for BR divisor */
1410 int etcndx; /* index into ETC table */
1411 int fifo_v, gotspeed; /* final tabled speed found */
1412 int tmc_v; /* timer control register */
1413 int wanted; /* speed (bitrate) wanted... */
1414 struct rate_line *rtp;
1417 portndx = sc->scachan;
1420 printf("sr: sr_init_msci( sc=%08x)\n", sc);
1423 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RESET);
1424 SRC_PUT8(hc->sca_base, msci->md0, SCA_MD0_CRC_1 |
1426 SCA_MD0_CRC_ENABLE |
1428 SRC_PUT8(hc->sca_base, msci->md1, SCA_MD1_NOADDRCHK);
1429 SRC_PUT8(hc->sca_base, msci->md2, SCA_MD2_DUPLEX | SCA_MD2_NRZ);
1432 * According to the manual I should give a reset after changing the
1435 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXRESET);
1436 SRC_PUT8(hc->sca_base, msci->ctl, SCA_CTL_IDLPAT |
1441 * XXX Later we will have to support different clock settings.
1443 switch (sc->clk_cfg) {
1446 printf("sr%: clk_cfg=%08x, selected default clock.\n",
1447 portndx, sc->clk_cfg);
1450 case SR_FLAGS_EXT_CLK:
1452 * For now all interfaces are programmed to use the RX clock
1457 printf("sr%d: External Clock Selected.\n", portndx);
1460 SRC_PUT8(hc->sca_base, msci->rxs,
1461 SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
1462 SRC_PUT8(hc->sca_base, msci->txs,
1463 SCA_TXS_CLK_RX | SCA_TXS_DIV1);
1466 case SR_FLAGS_EXT_SEP_CLK:
1468 printf("sr%d: Split Clocking Selected.\n", portndx);
1471 SRC_PUT8(hc->sca_base, msci->rxs,
1472 SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
1473 SRC_PUT8(hc->sca_base, msci->txs,
1474 SCA_TXS_CLK_TXC | SCA_TXS_DIV1);
1477 case SR_FLAGS_INT_CLK:
1479 printf("sr%d: Internal Clocking selected.\n", portndx);
1483 * XXX I do need some code to set the baud rate here!
1485 #ifdef N2_TEST_SPEED
1486 switch (hc->cardtype) {
1488 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1494 mcr_v = inb(hc->iobase + SR_MCR);
1498 fifo_v = 0x10; /* stolen from Linux version */
1501 * search for appropriate speed in table, don't calc it:
1503 wanted = sr_test_speed[portndx];
1504 rtp = &n2_rates[0]; /* point to first table item */
1506 while ((rtp->target > 0) /* search table for speed */
1507 &&(rtp->target != wanted))
1511 * We've searched the table for a matching speed. If we've
1512 * found the correct rate line, we'll get the pre-calc'd
1513 * values for the TMC and baud rate divisor for subsequent
1516 if (rtp->target > 0) { /* use table-provided values */
1518 tmc_v = rtp->tmc_reg;
1520 } else { /* otherwise assume 1MBit comm rate */
1527 * Now we mask in the enable clock output for the MCR:
1529 mcr_v |= etc0vals[etcndx + portndx];
1532 * Now we'll program the registers with these speed- related
1535 SRC_PUT8(hc->sca_base, msci->tmc, tmc_v);
1536 SRC_PUT8(hc->sca_base, msci->trc0, fifo_v);
1537 SRC_PUT8(hc->sca_base, msci->rxs, SCA_RXS_CLK_INT + br_v);
1538 SRC_PUT8(hc->sca_base, msci->txs, SCA_TXS_CLK_INT + br_v);
1540 switch (hc->cardtype) {
1546 outb(hc->iobase + SR_MCR, mcr_v);
1550 if (wanted != gotspeed)
1551 printf("sr%d: Speed wanted=%d, found=%d\n",
1554 printf("sr%d: Internal Clock %dx100 BPS, tmc=%d, div=%d\n",
1555 portndx, gotspeed, tmc_v, br_v);
1558 SRC_PUT8(hc->sca_base, msci->rxs,
1559 SCA_RXS_CLK_INT | SCA_RXS_DIV1);
1560 SRC_PUT8(hc->sca_base, msci->txs,
1561 SCA_TXS_CLK_INT | SCA_TXS_DIV1);
1563 SRC_PUT8(hc->sca_base, msci->tmc, 5);
1566 switch (hc->cardtype) {
1568 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1569 *fecrp |= SR_FECR_ETC0;
1573 mcr_v = inb(hc->iobase + SR_MCR);
1574 mcr_v |= SR_MCR_ETC0;
1575 outb(hc->iobase + SR_MCR, mcr_v);
1578 switch (hc->cardtype) {
1580 mcr_v = inb(hc->iobase + SR_MCR);
1581 mcr_v |= SR_MCR_ETC1;
1582 outb(hc->iobase + SR_MCR, mcr_v);
1585 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1586 *fecrp |= SR_FECR_ETC1;
1593 * XXX Disable all interrupts for now. I think if you are using the
1594 * dmac you don't use these interrupts.
1596 SRC_PUT8(hc->sca_base, msci->ie0, 0);
1597 SRC_PUT8(hc->sca_base, msci->ie1, 0x0C);
1598 SRC_PUT8(hc->sca_base, msci->ie2, 0);
1599 SRC_PUT8(hc->sca_base, msci->fie, 0);
1601 SRC_PUT8(hc->sca_base, msci->sa0, 0);
1602 SRC_PUT8(hc->sca_base, msci->sa1, 0);
1604 SRC_PUT8(hc->sca_base, msci->idl, 0x7E); /* set flags value */
1606 SRC_PUT8(hc->sca_base, msci->rrc, 0x0E);
1607 SRC_PUT8(hc->sca_base, msci->trc0, 0x10);
1608 SRC_PUT8(hc->sca_base, msci->trc1, 0x1F);
1612 * Configure the rx dma controller.
1615 sr_init_rx_dmac(struct sr_softc *sc)
1617 struct sr_hardc *hc;
1619 sca_descriptor *rxd;
1620 u_int cda_v, sarb_v, rxbuf, rxda, rxda_d;
1623 printf("sr_init_rx_dmac(sc=%08x)\n", sc);
1627 dmac = &hc->sca->dmac[DMAC_RXCH(sc->scachan)];
1630 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1633 * This phase initializes the contents of the descriptor table
1634 * needed to construct a circular buffer...
1636 rxd = (sca_descriptor *)(hc->mem_start + (sc->rxdesc & hc->winmsk));
1637 rxda_d = (u_int) hc->mem_start - (sc->rxdesc & ~hc->winmsk);
1639 for (rxbuf = sc->rxstart;
1641 rxbuf += SR_BUF_SIZ, rxd++) {
1643 * construct the circular chain...
1645 rxda = (u_int) & rxd[1] - rxda_d + hc->mem_pstart;
1646 rxd->cp = (u_short)(rxda & 0xffff);
1649 * set the on-card buffer address...
1651 rxd->bp = (u_short)((rxbuf + hc->mem_pstart) & 0xffff);
1652 rxd->bpb = (u_char)(((rxbuf + hc->mem_pstart) >> 16) & 0xff);
1654 rxd->len = 0; /* bytes resident w/in granule */
1655 rxd->stat = 0xff; /* The sca write here when finished */
1659 * heal the chain so that the last entry points to the first...
1662 rxd->cp = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
1665 * reset the reception handler's index...
1670 * We'll now configure the receiver's DMA logic...
1672 SRC_PUT8(hc->sca_base, dmac->dsr, 0); /* Disable DMA transfer */
1673 SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT);
1675 /* XXX maybe also SCA_DMR_CNTE */
1676 SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
1677 SRC_PUT16(hc->sca_base, dmac->bfl, SR_BUF_SIZ);
1679 cda_v = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
1680 sarb_v = (u_char)(((sc->rxdesc + hc->mem_pstart) >> 16) & 0xff);
1682 SRC_PUT16(hc->sca_base, dmac->cda, cda_v);
1683 SRC_PUT8(hc->sca_base, dmac->sarb, sarb_v);
1685 rxd = (sca_descriptor *)sc->rxstart;
1687 SRC_PUT16(hc->sca_base, dmac->eda,
1688 (u_short)((u_int) & rxd[sc->rxmax - 1] & 0xffff));
1690 SRC_PUT8(hc->sca_base, dmac->dir, 0xF0);
1693 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE); /* Enable DMA */
1697 * Configure the TX DMA descriptors.
1698 * Initialize the needed values and chain the descriptors.
1701 sr_init_tx_dmac(struct sr_softc *sc)
1704 u_int txbuf, txda, txda_d;
1705 struct sr_hardc *hc;
1706 sca_descriptor *txd;
1708 struct buf_block *blkp;
1713 printf("sr_init_tx_dmac(sc=%08x)\n", sc);
1717 dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];
1720 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc);
1723 * Initialize the array of descriptors for transmission
1725 for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
1726 blkp = &sc->block[blk];
1727 txd = (sca_descriptor *)(hc->mem_start
1728 + (blkp->txdesc & hc->winmsk));
1729 txda_d = (u_int) hc->mem_start
1730 - (blkp->txdesc & ~hc->winmsk);
1733 txbuf = blkp->txstart;
1734 for (; txbuf < blkp->txend; txbuf += SR_BUF_SIZ, txd++) {
1735 txda = (u_int) & txd[1] - txda_d + hc->mem_pstart;
1736 txd->cp = (u_short)(txda & 0xffff);
1738 txd->bp = (u_short)((txbuf + hc->mem_pstart)
1740 txd->bpb = (u_char)(((txbuf + hc->mem_pstart) >> 16)
1748 txd->cp = (u_short)((blkp->txdesc + hc->mem_pstart)
1751 blkp->txtail = (u_int)txd - (u_int)hc->mem_start;
1754 SRC_PUT8(hc->sca_base, dmac->dsr, 0); /* Disable DMA */
1755 SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT);
1756 SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
1757 SRC_PUT8(hc->sca_base, dmac->dir,
1758 SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF);
1760 sarb_v = (sc->block[0].txdesc + hc->mem_pstart) >> 16;
1763 SRC_PUT8(hc->sca_base, dmac->sarb, (u_char) sarb_v);
1767 * Look through the descriptors to see if there is a complete packet
1768 * available. Stop if we get to where the sca is busy.
1770 * Return the length and status of the packet.
1771 * Return nonzero if there is a packet available.
1774 * It seems that we get the interrupt a bit early. The updateing of
1775 * descriptor values is not always completed when this is called.
1778 sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat)
1780 int granules; /* count of granules in pkt */
1782 struct sr_hardc *hc;
1783 sca_descriptor *rxdesc; /* current descriptor */
1784 sca_descriptor *endp; /* ending descriptor */
1785 sca_descriptor *cda; /* starting descriptor */
1787 hc = sc->hc; /* get card's information */
1790 * set up starting descriptor by pulling that info from the DMA half
1793 wki = DMAC_RXCH(sc->scachan);
1794 wko = SRC_GET16(hc->sca_base, hc->sca->dmac[wki].cda);
1796 cda = (sca_descriptor *)(hc->mem_start + (wko & hc->winmsk));
1799 printf("sr_packet_avail(): wki=%d, wko=%04x, cda=%08x\n",
1804 * open the appropriate memory window and set our expectations...
1807 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1808 SRC_SET_ON(hc->iobase);
1810 rxdesc = (sca_descriptor *)
1811 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1813 rxdesc = &rxdesc[sc->rxhind];
1814 endp = &endp[sc->rxmax];
1816 *len = 0; /* reset result total length */
1817 granules = 0; /* reset count of granules */
1820 * This loop will scan descriptors, but it *will* puke up if we wrap
1821 * around to our starting point...
1823 while (rxdesc != cda) {
1824 *len += rxdesc->len; /* increment result length */
1828 * If we hit a valid packet's completion we'll know we've
1829 * got a live one, and that we can deliver the packet.
1830 * Since we're only allowed to report a packet available,
1831 * somebody else does that...
1833 if (rxdesc->stat & SCA_DESC_EOM) { /* End Of Message */
1834 *rxstat = rxdesc->stat; /* return closing */
1836 printf("sr%d: PKT AVAIL len %d, %x, bufs %u.\n",
1837 sc->unit, *len, *rxstat, granules);
1839 return 1; /* indicate success */
1842 * OK, this packet take up multiple granules. Move on to
1843 * the next descriptor so we can consider it...
1847 if (rxdesc == endp) /* recognize & act on wrap point */
1848 rxdesc = (sca_descriptor *)
1849 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1853 * Nothing found in the DPRAM. Let the caller know...
1862 * Copy a packet from the on card memory into a provided mbuf.
1863 * Take into account that buffers wrap and that a packet may
1864 * be larger than a buffer.
1867 sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len)
1869 struct sr_hardc *hc;
1870 sca_descriptor *rxdesc;
1877 printf("sr_copy_rxbuf(m=%08x,sc=%08x,len=%d)\n",
1883 rxdata = sc->rxstart + (sc->rxhind * SR_BUF_SIZ);
1884 rxmax = sc->rxstart + (sc->rxmax * SR_BUF_SIZ);
1886 rxdesc = (sca_descriptor *)
1887 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1888 rxdesc = &rxdesc[sc->rxhind];
1891 * Using the count of bytes in the received packet, we decrement it
1892 * for each granule (controller by an SCA descriptor) to control the
1897 * tlen gets the length of *this* granule... ...which is
1898 * then copied to the target buffer.
1900 tlen = (len < SR_BUF_SIZ) ? len : SR_BUF_SIZ;
1903 SRC_SET_MEM(hc->iobase, rxdata);
1905 bcopy(hc->mem_start + (rxdata & hc->winmsk),
1906 mtod(m, caddr_t) +off,
1913 * now, return to the descriptor's window in DPRAM and reset
1914 * the descriptor we've just suctioned...
1917 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1920 rxdesc->stat = 0xff;
1923 * Move on to the next granule. If we've any remaining
1924 * bytes to process we'll just continue in our loop...
1926 rxdata += SR_BUF_SIZ;
1929 if (rxdata == rxmax) { /* handle the wrap point */
1930 rxdata = sc->rxstart;
1931 rxdesc = (sca_descriptor *)
1932 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1938 * If single is set, just eat a packet. Otherwise eat everything up to
1939 * where cda points. Update pointers to point to the next packet.
1941 * This handles "flushing" of a packet as received...
1943 * If the "single" parameter is zero, all pending reeceive traffic will
1944 * be flushed out of existence. A non-zero value will only drop the
1945 * *next* (currently) pending packet...
1948 sr_eat_packet(struct sr_softc *sc, int single)
1950 struct sr_hardc *hc;
1951 sca_descriptor *rxdesc; /* current descriptor being eval'd */
1952 sca_descriptor *endp; /* last descriptor in chain */
1953 sca_descriptor *cda; /* current start point */
1954 u_int loopcnt = 0; /* count of packets flushed ??? */
1955 u_char stat; /* captured status byte from descr */
1958 cda = (sca_descriptor *)(hc->mem_start +
1959 (SRC_GET16(hc->sca_base,
1960 hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda) &
1964 * loop until desc->stat == (0xff || EOM) Clear the status and
1965 * length in the descriptor. Increment the descriptor.
1968 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1970 rxdesc = (sca_descriptor *)
1971 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1973 rxdesc = &rxdesc[sc->rxhind];
1974 endp = &endp[sc->rxmax];
1977 * allow loop, but abort it if we wrap completely...
1979 while (rxdesc != cda) {
1982 if (loopcnt > sc->rxmax) {
1983 printf("sr%d: eat pkt %d loop, cda %x, "
1984 "rxdesc %x, stat %x.\n",
1985 sc->unit, loopcnt, (u_int) cda, (u_int) rxdesc,
1989 stat = rxdesc->stat;
1992 rxdesc->stat = 0xff;
1997 if (rxdesc == endp) {
1998 rxdesc = (sca_descriptor *)
1999 (hc->mem_start + (sc->rxdesc & hc->winmsk));
2002 if (single && (stat == SCA_DESC_EOM))
2007 * Update the eda to the previous descriptor.
2009 rxdesc = (sca_descriptor *)sc->rxdesc;
2010 rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2) % sc->rxmax];
2012 SRC_PUT16(hc->sca_base,
2013 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
2014 (u_short)((u_int)(rxdesc + hc->mem_pstart) & 0xffff));
2018 * While there is packets available in the rx buffer, read them out
2019 * into mbufs and ship them off.
2022 sr_get_packets(struct sr_softc *sc)
2024 u_char rxstat; /* acquired status byte */
2026 int pkts; /* count of packets found */
2027 int rxndx; /* rcv buffer index */
2028 int tries; /* settling time counter */
2029 u_int len; /* length of pending packet */
2030 struct sr_hardc *hc; /* card-level information */
2031 sca_descriptor *rxdesc; /* descriptor in memory */
2033 struct ifnet *ifp; /* network intf ctl table */
2034 #endif /* NETGRAPH */
2035 struct mbuf *m = NULL; /* message buffer */
2038 printf("sr_get_packets(sc=%08x)\n", sc);
2043 ifp = &sc->ifsppp.pp_if;
2044 #endif /* NETGRAPH */
2047 SRC_SET_MEM(hc->iobase, sc->rxdesc);
2048 SRC_SET_ON(hc->iobase); /* enable shared memory */
2050 pkts = 0; /* reset count of found packets */
2053 * for each complete packet in the receiving pool, process each
2056 while (sr_packet_avail(sc, &len, &rxstat)) { /* packet pending? */
2058 * I have seen situations where we got the interrupt but the
2059 * status value wasn't deposited. This code should allow
2060 * the status byte's value to settle...
2065 while ((rxstat == 0x00ff)
2067 sr_packet_avail(sc, &len, &rxstat);
2070 printf("sr_packet_avail() returned len=%d, rxstat=%02ux\n",
2078 #endif /* NETGRAPH */
2081 * OK, we've settled the incoming message status. We can now
2084 if (((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) {
2086 printf("sr%d: sr_get_packet() rxstat=%02x, len=%d\n",
2087 sc->unit, rxstat, len);
2090 MGETHDR(m, MB_DONTWAIT, MT_DATA);
2093 * eat (flush) packet if get mbuf fail!!
2095 sr_eat_packet(sc, 1);
2099 * construct control information for pass-off
2102 m->m_pkthdr.rcvif = ifp;
2104 m->m_pkthdr.rcvif = NULL;
2105 #endif /* NETGRAPH */
2106 m->m_pkthdr.len = m->m_len = len;
2108 MCLGET(m, MB_DONTWAIT);
2109 if ((m->m_flags & M_EXT) == 0) {
2111 * We couldn't get a big enough
2112 * message packet, so we'll send the
2113 * packet to /dev/null...
2116 sr_eat_packet(sc, 1);
2121 * OK, we've got a good message buffer. Now we can
2122 * copy the received message into it
2124 sr_copy_rxbuf(m, sc, len); /* copy from DPRAM */
2134 printf("sr%d: rcvd=%02x%02x%02x%02x%02x%02x\n",
2136 bp[0], bp[1], bp[2],
2137 bp[4], bp[5], bp[6]);
2143 #else /* NETGRAPH */
2148 bp = mtod(m,u_char *);
2149 printf("sr%d: rd=%02x:%02x:%02x:%02x:%02x:%02x",
2151 bp[0], bp[1], bp[2],
2152 bp[4], bp[5], bp[6]);
2153 printf(":%02x:%02x:%02x:%02x:%02x:%02x\n",
2154 bp[6], bp[7], bp[8],
2155 bp[9], bp[10], bp[11]);
2158 ng_queue_data(sc->hook, m, NULL);
2160 #endif /* NETGRAPH */
2162 * Update the eda to the previous descriptor.
2164 i = (len + SR_BUF_SIZ - 1) / SR_BUF_SIZ;
2165 sc->rxhind = (sc->rxhind + i) % sc->rxmax;
2167 rxdesc = (sca_descriptor *)sc->rxdesc;
2168 rxndx = (sc->rxhind + sc->rxmax - 2) % sc->rxmax;
2169 rxdesc = &rxdesc[rxndx];
2171 SRC_PUT16(hc->sca_base,
2172 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
2173 (u_short)((u_int)(rxdesc + hc->mem_pstart)
2177 int got_st3, got_cda, got_eda;
2180 while ((rxstat == 0xff) && --tries)
2181 sr_packet_avail(sc, &len, &rxstat);
2184 * It look like we get an interrupt early
2185 * sometimes and then the status is not
2188 if (tries && (tries != 5))
2192 * This chunk of code handles the error packets.
2193 * We'll log them for posterity...
2195 sr_eat_packet(sc, 1);
2201 #endif /* NETGRAPH */
2203 got_st3 = SRC_GET8(hc->sca_base,
2204 hc->sca->msci[sc->scachan].st3);
2205 got_cda = SRC_GET16(hc->sca_base,
2206 hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda);
2207 got_eda = SRC_GET16(hc->sca_base,
2208 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda);
2211 printf("sr%d: Receive error chan %d, "
2212 "stat %02x, msci st3 %02x,"
2213 "rxhind %d, cda %04x, eda %04x.\n",
2214 sc->unit, sc->scachan, rxstat,
2215 got_st3, sc->rxhind, got_cda, got_eda);
2221 printf("sr%d: sr_get_packets() found %d packet(s)\n",
2226 SRC_SET_OFF(hc->iobase);
2230 * All DMA interrupts come here.
2232 * Each channel has two interrupts.
2233 * Interrupt A for errors and Interrupt B for normal stuff like end
2234 * of transmit or receive dmas.
2237 sr_dmac_intr(struct sr_hardc *hc, u_char isr1)
2239 u_char dsr; /* contents of DMA Stat Reg */
2240 u_char dotxstart; /* enables for tranmit part */
2241 int mch; /* channel being processed */
2242 struct sr_softc *sc; /* channel's softc structure */
2243 sca_regs *sca = hc->sca;
2244 dmac_channel *dmac; /* dma structure of chip */
2247 printf("sr_dmac_intr(hc=%08x,isr1=%04x)\n", hc, isr1);
2250 mch = 0; /* assume chan0 on card */
2251 dotxstart = isr1; /* copy for xmitter starts */
2254 * Shortcut if there is no interrupts for dma channel 0 or 1.
2255 * Skip processing for channel 0 if no incoming hit
2257 if ((isr1 & 0x0F) == 0) {
2265 * Transmit channel - DMA Status Register Evaluation
2268 dmac = &sca->dmac[DMAC_TXCH(mch)];
2271 * get the DMA Status Register contents and write
2272 * back to reset interrupt...
2274 dsr = SRC_GET8(hc->sca_base, dmac->dsr);
2275 SRC_PUT8(hc->sca_base, dmac->dsr, dsr);
2278 * Check for (& process) a Counter overflow
2280 if (dsr & SCA_DSR_COF) {
2281 printf("sr%d: TX DMA Counter overflow, "
2282 "txpacket no %lu.\n",
2284 sc->unit, sc->ifsppp.pp_if.if_opackets);
2285 sc->ifsppp.pp_if.if_oerrors++;
2287 sc->unit, sc->opackets);
2289 #endif /* NETGRAPH */
2292 * Check for (& process) a Buffer overflow
2294 if (dsr & SCA_DSR_BOF) {
2295 printf("sr%d: TX DMA Buffer overflow, "
2296 "txpacket no %lu, dsr %02x, "
2297 "cda %04x, eda %04x.\n",
2299 sc->unit, sc->ifsppp.pp_if.if_opackets,
2301 sc->unit, sc->opackets,
2302 #endif /* NETGRAPH */
2304 SRC_GET16(hc->sca_base, dmac->cda),
2305 SRC_GET16(hc->sca_base, dmac->eda));
2307 sc->ifsppp.pp_if.if_oerrors++;
2310 #endif /* NETGRAPH */
2313 * Check for (& process) an End of Transfer (OK)
2315 if (dsr & SCA_DSR_EOT) {
2317 * This should be the most common case.
2319 * Clear the IFF_OACTIVE flag.
2321 * Call srstart to start a new transmit if
2322 * there is data to transmit.
2325 printf("sr%d: TX Completed OK\n", sc->unit);
2329 sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE;
2330 sc->ifsppp.pp_if.if_timer = 0;
2332 /* XXX may need to mark tx inactive? */
2334 sc->out_dog = DOG_HOLDOFF;
2335 #endif /* NETGRAPH */
2337 if (sc->txb_inuse && --sc->txb_inuse)
2342 * Receive channel processing of DMA Status Register
2345 dmac = &sca->dmac[DMAC_RXCH(mch)];
2347 dsr = SRC_GET8(hc->sca_base, dmac->dsr);
2348 SRC_PUT8(hc->sca_base, dmac->dsr, dsr);
2351 * End of frame processing (MSG OK?)
2353 if (dsr & SCA_DSR_EOM) {
2358 tt = sc->ifsppp.pp_if.if_ipackets;
2359 #else /* NETGRAPH */
2361 #endif /* NETGRAPH */
2368 if (tt == sc->ifsppp.pp_if.if_ipackets)
2369 #else /* NETGRAPH */
2370 if (tt == sc->ipackets)
2371 #endif /* NETGRAPH */
2373 sca_descriptor *rxdesc;
2376 printf("SR: RXINTR isr1 %x, dsr %x, "
2377 "no data %d pkts, orxind %d.\n",
2378 dotxstart, dsr, tt, ind);
2379 printf("SR: rxdesc %x, rxstart %x, "
2380 "rxend %x, rxhind %d, "
2382 sc->rxdesc, sc->rxstart,
2383 sc->rxend, sc->rxhind,
2385 printf("SR: cda %x, eda %x.\n",
2386 SRC_GET16(hc->sca_base, dmac->cda),
2387 SRC_GET16(hc->sca_base, dmac->eda));
2390 SRC_SET_ON(hc->iobase);
2391 SRC_SET_MEM(hc->iobase, sc->rxdesc);
2393 rxdesc = (sca_descriptor *)
2395 (sc->rxdesc & hc->winmsk));
2396 rxdesc = &rxdesc[sc->rxhind];
2398 for (i = 0; i < 3; i++, rxdesc++)
2399 printf("SR: rxdesc->stat %x, "
2405 SRC_SET_OFF(hc->iobase);
2410 * Check for Counter overflow
2412 if (dsr & SCA_DSR_COF) {
2413 printf("sr%d: RX DMA Counter overflow, "
2416 sc->unit, sc->ifsppp.pp_if.if_ipackets);
2417 sc->ifsppp.pp_if.if_ierrors++;
2418 #else /* NETGRAPH */
2419 sc->unit, sc->ipackets);
2421 #endif /* NETGRAPH */
2424 * Check for Buffer overflow
2426 if (dsr & SCA_DSR_BOF) {
2427 printf("sr%d: RX DMA Buffer overflow, "
2428 "rxpkts %lu, rxind %d, "
2429 "cda %x, eda %x, dsr %x.\n",
2431 sc->unit, sc->ifsppp.pp_if.if_ipackets,
2432 #else /* NETGRAPH */
2433 sc->unit, sc->ipackets,
2434 #endif /* NETGRAPH */
2436 SRC_GET16(hc->sca_base, dmac->cda),
2437 SRC_GET16(hc->sca_base, dmac->eda),
2441 * Make sure we eat as many as possible.
2442 * Then get the system running again.
2445 SRC_SET_ON(hc->iobase);
2447 sr_eat_packet(sc, 0);
2449 sc->ifsppp.pp_if.if_ierrors++;
2450 #else /* NETGRAPH */
2452 #endif /* NETGRAPH */
2454 SRC_PUT8(hc->sca_base,
2458 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);
2461 printf("sr%d: RX DMA Buffer overflow, "
2462 "rxpkts %lu, rxind %d, "
2463 "cda %x, eda %x, dsr %x. After\n",
2467 #else /* NETGRAPH */
2468 sc->ifsppp.pp_if.if_ipackets,
2469 #endif /* NETGRAPH */
2471 SRC_GET16(hc->sca_base, dmac->cda),
2472 SRC_GET16(hc->sca_base, dmac->eda),
2473 SRC_GET8(hc->sca_base, dmac->dsr));
2477 SRC_SET_OFF(hc->iobase);
2482 if (dsr & SCA_DSR_EOT) {
2484 * If this happen, it means that we are
2485 * receiving faster than what the processor
2488 * XXX We should enable the dma again.
2490 printf("sr%d: RX End of xfer, rxpkts %lu.\n",
2493 sc->ifsppp.pp_if.if_ipackets);
2494 sc->ifsppp.pp_if.if_ierrors++;
2498 #endif /* NETGRAPH */
2501 isr1 >>= 4; /* process next half of ISR */
2502 mch++; /* and move to next channel */
2503 } while ((mch < NCHAN) && isr1); /* loop for each chn */
2506 * Now that we have done all the urgent things, see if we can fill
2507 * the transmit buffers.
2509 for (mch = 0; mch < NCHAN; mch++) {
2510 if (dotxstart & 0x0C) { /* TX initiation enabled? */
2513 srstart(&sc->ifsppp.pp_if);
2516 #endif /* NETGRAPH */
2518 dotxstart >>= 4;/* shift for next channel */
2524 * Perform timeout on an FR channel
2526 * Establish a periodic check of open N2 ports; If
2527 * a port is open/active, its DCD state is checked
2528 * and a loss of DCD is recognized (and eventually
2532 sr_modemck(void *arg)
2535 int card; /* card index in table */
2536 int cards; /* card list index */
2537 int mch; /* channel on card */
2538 u_char dcd_v; /* Data Carrier Detect */
2539 u_char got_st0; /* contents of ST0 */
2540 u_char got_st1; /* contents of ST1 */
2541 u_char got_st2; /* contents of ST2 */
2542 u_char got_st3; /* contents of ST3 */
2543 struct sr_hardc *hc; /* card's configuration */
2544 struct sr_hardc *Card[16];/* up to 16 cards in system */
2545 struct sr_softc *sc; /* channel's softc structure */
2546 struct ifnet *ifp; /* interface control table */
2547 msci_channel *msci; /* regs specific to channel */
2552 if (sr_opens == 0) { /* count of "up" channels */
2553 sr_watcher = 0; /* indicate no watcher */
2559 sr_watcher = 1; /* mark that we're online */
2562 * Now we'll need a list of cards to process. Since we can handle
2563 * both ISA and PCI cards (and I didn't think of making this logic
2564 * global YET) we'll generate a single table of card table
2569 for (card = 0; card < NSR; card++) {
2570 hc = &sr_hardc[card];
2572 if (hc->sc == (void *)0)
2586 * OK, we've got work we can do. Let's do it... (Please note that
2587 * this code _only_ deals w/ ISA cards)
2589 for (card = 0; card < cards; card++) {
2590 hc = Card[card];/* get card table */
2592 for (mch = 0; mch < hc->numports; mch++) {
2595 ifp = &sc->ifsppp.pp_if;
2598 * if this channel isn't "up", skip it
2600 if ((ifp->if_flags & IFF_UP) == 0)
2604 * OK, now we can go looking at this channel's
2605 * actual register contents...
2607 msci = &hc->sca->msci[sc->scachan];
2610 * OK, now we'll look into the actual status of this
2613 * I suck in more registers than strictly needed
2615 got_st0 = SRC_GET8(hc->sca_base, msci->st0);
2616 got_st1 = SRC_GET8(hc->sca_base, msci->st1);
2617 got_st2 = SRC_GET8(hc->sca_base, msci->st2);
2618 got_st3 = SRC_GET8(hc->sca_base, msci->st3);
2621 * We want to see if the DCD signal is up (DCD is
2624 dcd_v = (got_st3 & SCA_ST3_DCD) == 0;
2627 printf("sr%d: DCD lost\n", sc->unit);
2632 * OK, now set up for the next modem signal checking pass...
2634 timeout(sr_modemck, NULL, hz);
2639 #else /* NETGRAPH */
2641 * If a port is open/active, it's DCD state is checked
2642 * and a loss of DCD is recognized (and eventually processed?).
2645 sr_modemck(struct sr_softc *sc )
2648 u_char got_st3; /* contents of ST3 */
2649 struct sr_hardc *hc = sc->hc; /* card's configuration */
2650 msci_channel *msci; /* regs specific to channel */
2655 if (sc->running == 0)
2658 * OK, now we can go looking at this channel's register contents...
2660 msci = &hc->sca->msci[sc->scachan];
2661 got_st3 = SRC_GET8(hc->sca_base, msci->st3);
2664 * We want to see if the DCD signal is up (DCD is true if zero)
2666 sc->dcd = (got_st3 & SCA_ST3_DCD) == 0;
2670 #endif /* NETGRAPH */
2672 sr_msci_intr(struct sr_hardc *hc, u_char isr0)
2674 printf("src%d: SRINTR: MSCI\n", hc->cunit);
2678 sr_timer_intr(struct sr_hardc *hc, u_char isr2)
2680 printf("src%d: SRINTR: TIMER\n", hc->cunit);
2684 /*****************************************
2685 * Device timeout/watchdog routine.
2686 * called once per second.
2687 * checks to see that if activity was expected, that it hapenned.
2688 * At present we only look to see if expected output was completed.
2691 ngsr_watchdog_frame(void * arg)
2693 struct sr_softc * sc = arg;
2697 if (sc->running == 0)
2698 return; /* if we are not running let timeouts die */
2700 * calculate the apparent throughputs
2704 speed = sc->inbytes - sc->lastinbytes;
2705 sc->lastinbytes = sc->inbytes;
2706 if ( sc->inrate < speed )
2708 speed = sc->outbytes - sc->lastoutbytes;
2709 sc->lastoutbytes = sc->outbytes;
2710 if ( sc->outrate < speed )
2711 sc->outrate = speed;
2715 if ((sc->inlast > QUITE_A_WHILE)
2716 && (sc->out_deficit > LOTS_OF_PACKETS)) {
2717 log(LOG_ERR, "sr%d: No response from remote end\n", sc->unit);
2721 sc->inlast = sc->out_deficit = 0;
2723 } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */
2724 if (sc->out_dog == 0) {
2725 log(LOG_ERR, "sr%d: Transmit failure.. no clock?\n",
2734 sc->inlast = sc->out_deficit = 0;
2739 sr_modemck(sc); /* update the DCD status */
2740 callout_reset(&sc->sr_timer, hz, ngsr_watchdog_frame, sc);
2743 /***********************************************************************
2744 * This section contains the methods for the Netgraph interface
2745 ***********************************************************************/
2747 * It is not possible or allowable to create a node of this type.
2748 * If the hardware exists, it will already have created it.
2751 ngsr_constructor(node_p *nodep)
2757 * give our ok for a hook to be added...
2758 * If we are not running this should kick the device into life.
2759 * The hook's private info points to our stash of info about that
2763 ngsr_newhook(node_p node, hook_p hook, const char *name)
2765 struct sr_softc * sc = node->private;
2768 * check if it's our friend the debug hook
2770 if (strcmp(name, NG_SR_HOOK_DEBUG) == 0) {
2771 hook->private = NULL; /* paranoid */
2772 sc->debug_hook = hook;
2777 * Check for raw mode hook.
2779 if (strcmp(name, NG_SR_HOOK_RAW) != 0) {
2790 * incoming messages.
2791 * Just respond to the generic TEXT_STATUS message
2794 ngsr_rcvmsg(node_p node,
2795 struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp)
2797 struct sr_softc * sc;
2801 switch (msg->header.typecookie) {
2805 case NGM_GENERIC_COOKIE:
2806 switch(msg->header.cmd) {
2807 case NGM_TEXT_STATUS: {
2810 int resplen = sizeof(struct ng_mesg) + 512;
2811 MALLOC(*resp, struct ng_mesg *, resplen,
2812 M_NETGRAPH, M_INTWAIT | M_ZERO);
2813 if (*resp == NULL) {
2817 arg = (*resp)->data;
2820 * Put in the throughput information.
2822 pos = sprintf(arg, "%ld bytes in, %ld bytes out\n"
2823 "highest rate seen: %ld B/S in, %ld B/S out\n",
2824 sc->inbytes, sc->outbytes,
2825 sc->inrate, sc->outrate);
2826 pos += sprintf(arg + pos,
2827 "%ld output errors\n",
2829 pos += sprintf(arg + pos,
2830 "ierrors = %ld, %ld, %ld, %ld, %ld, %ld\n",
2838 (*resp)->header.version = NG_VERSION;
2839 (*resp)->header.arglen = strlen(arg) + 1;
2840 (*resp)->header.token = msg->header.token;
2841 (*resp)->header.typecookie = NG_SR_COOKIE;
2842 (*resp)->header.cmd = msg->header.cmd;
2843 strncpy((*resp)->header.cmdstr, "status",
2856 free(msg, M_NETGRAPH);
2861 * get data from another node and transmit it to the correct channel
2864 ngsr_rcvdata(hook_p hook, struct mbuf *m, meta_p meta)
2868 struct sr_softc * sc = hook->node->private;
2869 struct ifqueue *xmitq_p;
2872 * data doesn't come in from just anywhere (e.g control hook)
2874 if ( hook->private == NULL) {
2880 * Now queue the data for when it can be sent
2882 if (meta && meta->priority > 0) {
2883 xmitq_p = (&sc->xmitq_hipri);
2885 xmitq_p = (&sc->xmitq);
2888 if (IF_QFULL(xmitq_p)) {
2894 IF_ENQUEUE(xmitq_p, m);
2901 * It was an error case.
2902 * check if we need to free the mbuf, and then return the error
2904 NG_FREE_DATA(m, meta);
2909 * do local shutdown processing..
2910 * this node will refuse to go away, unless the hardware says to..
2911 * don't unref the node, or remove our name. just clear our links up.
2914 ngsr_rmnode(node_p node)
2916 struct sr_softc * sc = node->private;
2920 node->flags &= ~NG_INVALID; /* bounce back to life */
2924 /* already linked */
2926 ngsr_connect(hook_p hook)
2928 /* be really amiable and just say "YUP that's OK by me! " */
2933 * notify on hook disconnection (destruction)
2935 * Invalidate the private data associated with this dlci.
2936 * For this type, removal of the last link resets tries to destroy the node.
2937 * As the device still exists, the shutdown method will not actually
2938 * destroy the node, but reset the device and leave it 'fresh' :)
2940 * The node removal code will remove all references except that owned by the
2944 ngsr_disconnect(hook_p hook)
2946 struct sr_softc * sc = hook->node->private;
2949 * If it's the data hook, then free resources etc.
2951 if (hook->private) {
2954 if (sc->datahooks == 0)
2958 sc->debug_hook = NULL;
2964 * called during bootup
2965 * or LKM loading to put this type into the list of known modules
2968 ngsr_init(void *ignored)
2970 if (ng_newtype(&typestruct))
2971 printf("ngsr install failed\n");
2974 #endif /* NETGRAPH */
2977 ********************************* END ************************************