1 /* $FreeBSD: src/sys/dev/ubsec/ubsec.c,v 1.6.2.12 2003/06/04 17:56:59 sam Exp $ */
2 /* $DragonFly: src/sys/dev/crypto/ubsec/ubsec.c,v 1.11 2006/09/05 03:48:09 dillon Exp $ */
3 /* $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $ */
6 * Copyright (c) 2000 Jason L. Wright (jason@thought.net)
7 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org)
8 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
10 * All rights reserved.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by Jason L. Wright
23 * 4. The name of the author may not be used to endorse or promote products
24 * derived from this software without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
29 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
38 * Effort sponsored in part by the Defense Advanced Research Projects
39 * Agency (DARPA) and Air Force Research Laboratory, Air Force
40 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
45 * uBsec 5[56]01, 58xx hardware crypto accelerator
48 #include "opt_ubsec.h"
50 #include <sys/param.h>
51 #include <sys/systm.h>
53 #include <sys/errno.h>
54 #include <sys/malloc.h>
55 #include <sys/kernel.h>
57 #include <sys/sysctl.h>
58 #include <sys/endian.h>
63 #include <machine/clock.h>
64 #include <machine/bus.h>
65 #include <machine/resource.h>
68 #include <sys/thread2.h>
70 #include <crypto/sha1.h>
71 #include <opencrypto/cryptodev.h>
72 #include <opencrypto/cryptosoft.h>
74 #include <sys/random.h>
76 #include <bus/pci/pcivar.h>
77 #include <bus/pci/pcireg.h>
79 /* grr, #defines for gratuitous incompatibility in queue.h */
80 #define SIMPLEQ_HEAD STAILQ_HEAD
81 #define SIMPLEQ_ENTRY STAILQ_ENTRY
82 #define SIMPLEQ_INIT STAILQ_INIT
83 #define SIMPLEQ_INSERT_TAIL STAILQ_INSERT_TAIL
84 #define SIMPLEQ_EMPTY STAILQ_EMPTY
85 #define SIMPLEQ_FIRST STAILQ_FIRST
86 #define SIMPLEQ_REMOVE_HEAD STAILQ_REMOVE_HEAD_UNTIL
87 #define SIMPLEQ_FOREACH STAILQ_FOREACH
88 /* ditto for endian.h */
89 #define letoh16(x) le16toh(x)
90 #define letoh32(x) le32toh(x)
93 #include "../rndtest/rndtest.h"
99 * Prototypes and count for the pci_device structure
101 static int ubsec_probe(device_t);
102 static int ubsec_attach(device_t);
103 static int ubsec_detach(device_t);
104 static int ubsec_suspend(device_t);
105 static int ubsec_resume(device_t);
106 static void ubsec_shutdown(device_t);
108 static device_method_t ubsec_methods[] = {
109 /* Device interface */
110 DEVMETHOD(device_probe, ubsec_probe),
111 DEVMETHOD(device_attach, ubsec_attach),
112 DEVMETHOD(device_detach, ubsec_detach),
113 DEVMETHOD(device_suspend, ubsec_suspend),
114 DEVMETHOD(device_resume, ubsec_resume),
115 DEVMETHOD(device_shutdown, ubsec_shutdown),
118 DEVMETHOD(bus_print_child, bus_generic_print_child),
119 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
123 static driver_t ubsec_driver = {
126 sizeof (struct ubsec_softc)
128 static devclass_t ubsec_devclass;
130 DECLARE_DUMMY_MODULE(ubsec);
131 DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0);
132 MODULE_DEPEND(ubsec, crypto, 1, 1, 1);
134 MODULE_DEPEND(ubsec, rndtest, 1, 1, 1);
137 static void ubsec_intr(void *);
138 static int ubsec_newsession(void *, u_int32_t *, struct cryptoini *);
139 static int ubsec_freesession(void *, u_int64_t);
140 static int ubsec_process(void *, struct cryptop *, int);
141 static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *);
142 static void ubsec_feed(struct ubsec_softc *);
143 static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int);
144 static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *);
145 static int ubsec_feed2(struct ubsec_softc *);
146 static void ubsec_rng(void *);
147 static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t,
148 struct ubsec_dma_alloc *, int);
149 #define ubsec_dma_sync(_dma, _flags) \
150 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags))
151 static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *);
152 static int ubsec_dmamap_aligned(struct ubsec_operand *op);
154 static void ubsec_reset_board(struct ubsec_softc *sc);
155 static void ubsec_init_board(struct ubsec_softc *sc);
156 static void ubsec_init_pciregs(device_t dev);
157 static void ubsec_totalreset(struct ubsec_softc *sc);
159 static int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q);
161 static int ubsec_kprocess(void*, struct cryptkop *, int);
162 static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int);
163 static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int);
164 static int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int);
165 static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *);
166 static int ubsec_ksigbits(struct crparam *);
167 static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
168 static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
170 SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0, "Broadcom driver parameters");
173 static void ubsec_dump_pb(volatile struct ubsec_pktbuf *);
174 static void ubsec_dump_mcr(struct ubsec_mcr *);
175 static void ubsec_dump_ctx2(struct ubsec_ctx_keyop *);
177 static int ubsec_debug = 0;
178 SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug,
179 0, "control debugging msgs");
182 #define READ_REG(sc,r) \
183 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r))
185 #define WRITE_REG(sc,reg,val) \
186 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val)
188 #define SWAP32(x) (x) = htole32(ntohl((x)))
189 #define HTOLE32(x) (x) = htole32(x)
192 struct ubsec_stats ubsecstats;
193 SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats,
194 ubsec_stats, "driver statistics");
197 ubsec_probe(device_t dev)
199 if (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
200 (pci_get_device(dev) == PCI_PRODUCT_SUN_5821 ||
201 pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K))
203 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
204 (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 ||
205 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601))
207 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
208 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5801 ||
209 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
210 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 ||
211 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 ||
212 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
213 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
214 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823
221 ubsec_partname(struct ubsec_softc *sc)
223 /* XXX sprintf numbers when not decoded */
224 switch (pci_get_vendor(sc->sc_dev)) {
225 case PCI_VENDOR_BROADCOM:
226 switch (pci_get_device(sc->sc_dev)) {
227 case PCI_PRODUCT_BROADCOM_5801: return "Broadcom 5801";
228 case PCI_PRODUCT_BROADCOM_5802: return "Broadcom 5802";
229 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805";
230 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820";
231 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821";
232 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822";
233 case PCI_PRODUCT_BROADCOM_5823: return "Broadcom 5823";
235 return "Broadcom unknown-part";
236 case PCI_VENDOR_BLUESTEEL:
237 switch (pci_get_device(sc->sc_dev)) {
238 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601";
240 return "Bluesteel unknown-part";
242 switch (pci_get_device(sc->sc_dev)) {
243 case PCI_PRODUCT_SUN_5821: return "Sun Crypto 5821";
244 case PCI_PRODUCT_SUN_SCA1K: return "Sun Crypto 1K";
246 return "Sun unknown-part";
248 return "Unknown-vendor unknown-part";
252 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
254 u_int32_t *p = (u_int32_t *)buf;
255 for (count /= sizeof (u_int32_t); count; count--)
256 add_true_randomness(*p++);
260 ubsec_attach(device_t dev)
262 struct ubsec_softc *sc = device_get_softc(dev);
263 struct ubsec_dma *dmap;
267 KASSERT(sc != NULL, ("ubsec_attach: null software carrier!"));
268 bzero(sc, sizeof (*sc));
271 SIMPLEQ_INIT(&sc->sc_queue);
272 SIMPLEQ_INIT(&sc->sc_qchip);
273 SIMPLEQ_INIT(&sc->sc_queue2);
274 SIMPLEQ_INIT(&sc->sc_qchip2);
275 SIMPLEQ_INIT(&sc->sc_q2free);
277 /* XXX handle power management */
279 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR;
281 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
282 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)
283 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
285 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
286 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
287 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805))
288 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
290 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
291 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820)
292 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
293 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
295 if ((pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
296 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
297 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
298 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823)) ||
299 (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
300 (pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K ||
301 pci_get_device(dev) == PCI_PRODUCT_SUN_5821))) {
302 /* NB: the 5821/5822 defines some additional status bits */
303 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY |
304 BS_STAT_MCR2_ALLEMPTY;
305 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
306 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
309 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
310 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
311 pci_write_config(dev, PCIR_COMMAND, cmd, 4);
312 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
314 if (!(cmd & PCIM_CMD_MEMEN)) {
315 device_printf(dev, "failed to enable memory mapping\n");
319 if (!(cmd & PCIM_CMD_BUSMASTEREN)) {
320 device_printf(dev, "failed to enable bus mastering\n");
325 * Setup memory-mapping of PCI registers.
328 sc->sc_sr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
329 0, ~0, 1, RF_ACTIVE);
330 if (sc->sc_sr == NULL) {
331 device_printf(dev, "cannot map register space\n");
334 sc->sc_st = rman_get_bustag(sc->sc_sr);
335 sc->sc_sh = rman_get_bushandle(sc->sc_sr);
338 * Arrange interrupt line.
341 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
342 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE);
343 if (sc->sc_irq == NULL) {
344 device_printf(dev, "could not map interrupt\n");
348 * NB: Network code assumes we are blocked with splimp()
349 * so make sure the IRQ is mapped appropriately.
351 if (bus_setup_intr(dev, sc->sc_irq, 0,
354 device_printf(dev, "could not establish interrupt\n");
358 sc->sc_cid = crypto_get_driverid(0);
359 if (sc->sc_cid < 0) {
360 device_printf(dev, "could not get crypto driver id\n");
365 * Setup DMA descriptor area.
367 if (bus_dma_tag_create(NULL, /* parent */
368 1, 0, /* alignment, bounds */
369 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
370 BUS_SPACE_MAXADDR, /* highaddr */
371 NULL, NULL, /* filter, filterarg */
372 0x3ffff, /* maxsize */
373 UBS_MAX_SCATTER, /* nsegments */
374 0xffff, /* maxsegsize */
375 BUS_DMA_ALLOCNOW, /* flags */
377 device_printf(dev, "cannot allocate DMA tag\n");
380 SIMPLEQ_INIT(&sc->sc_freequeue);
382 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) {
385 q = kmalloc(sizeof(struct ubsec_q), M_DEVBUF, M_WAITOK);
386 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk),
387 &dmap->d_alloc, 0)) {
388 device_printf(dev, "cannot allocate dma buffers\n");
392 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr;
395 sc->sc_queuea[i] = q;
397 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
400 device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc));
402 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0,
403 ubsec_newsession, ubsec_freesession, ubsec_process, sc);
404 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0,
405 ubsec_newsession, ubsec_freesession, ubsec_process, sc);
406 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0,
407 ubsec_newsession, ubsec_freesession, ubsec_process, sc);
408 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0,
409 ubsec_newsession, ubsec_freesession, ubsec_process, sc);
412 * Reset Broadcom chip
414 ubsec_reset_board(sc);
417 * Init Broadcom specific PCI settings
419 ubsec_init_pciregs(dev);
424 ubsec_init_board(sc);
427 if (sc->sc_flags & UBS_FLAGS_RNG) {
428 sc->sc_statmask |= BS_STAT_MCR2_DONE;
430 sc->sc_rndtest = rndtest_attach(dev);
432 sc->sc_harvest = rndtest_harvest;
434 sc->sc_harvest = default_harvest;
436 sc->sc_harvest = default_harvest;
439 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
440 &sc->sc_rng.rng_q.q_mcr, 0))
443 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass),
444 &sc->sc_rng.rng_q.q_ctx, 0)) {
445 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
449 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) *
450 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) {
451 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
452 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
457 sc->sc_rnghz = hz / 100;
460 callout_init(&sc->sc_rngto);
461 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
465 #endif /* UBSEC_NO_RNG */
467 if (sc->sc_flags & UBS_FLAGS_KEY) {
468 sc->sc_statmask |= BS_STAT_MCR2_DONE;
470 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0,
473 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0,
479 crypto_unregister_all(sc->sc_cid);
481 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
483 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
485 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
491 * Detach a device that successfully probed.
494 ubsec_detach(device_t dev)
496 struct ubsec_softc *sc = device_get_softc(dev);
498 KASSERT(sc != NULL, ("ubsec_detach: null software carrier"));
500 /* XXX wait/abort active ops */
504 callout_stop(&sc->sc_rngto);
506 crypto_unregister_all(sc->sc_cid);
510 rndtest_detach(sc->sc_rndtest);
513 while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
516 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
517 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next);
518 ubsec_dma_free(sc, &q->q_dma->d_alloc);
522 if (sc->sc_flags & UBS_FLAGS_RNG) {
523 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
524 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
525 ubsec_dma_free(sc, &sc->sc_rng.rng_buf);
527 #endif /* UBSEC_NO_RNG */
529 bus_generic_detach(dev);
530 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
531 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
533 bus_dma_tag_destroy(sc->sc_dmat);
534 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
542 * Stop all chip i/o so that the kernel's probe routines don't
543 * get confused by errant DMAs when rebooting.
546 ubsec_shutdown(device_t dev)
549 ubsec_stop(device_get_softc(dev));
554 * Device suspend routine.
557 ubsec_suspend(device_t dev)
559 struct ubsec_softc *sc = device_get_softc(dev);
561 KASSERT(sc != NULL, ("ubsec_suspend: null software carrier"));
563 /* XXX stop the device and save PCI settings */
565 sc->sc_suspended = 1;
571 ubsec_resume(device_t dev)
573 struct ubsec_softc *sc = device_get_softc(dev);
575 KASSERT(sc != NULL, ("ubsec_resume: null software carrier"));
577 /* XXX retore PCI settings and start the device */
579 sc->sc_suspended = 0;
584 * UBSEC Interrupt routine
587 ubsec_intr(void *arg)
589 struct ubsec_softc *sc = arg;
590 volatile u_int32_t stat;
592 struct ubsec_dma *dmap;
595 stat = READ_REG(sc, BS_STAT);
596 stat &= sc->sc_statmask;
601 WRITE_REG(sc, BS_STAT, stat); /* IACK */
604 * Check to see if we have any packets waiting for us
606 if ((stat & BS_STAT_MCR1_DONE)) {
607 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
608 q = SIMPLEQ_FIRST(&sc->sc_qchip);
611 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0)
614 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next);
616 npkts = q->q_nstacked_mcrs;
617 sc->sc_nqchip -= 1+npkts;
619 * search for further sc_qchip ubsec_q's that share
620 * the same MCR, and complete them too, they must be
623 for (i = 0; i < npkts; i++) {
624 if(q->q_stacked_mcr[i]) {
625 ubsec_callback(sc, q->q_stacked_mcr[i]);
630 ubsec_callback(sc, q);
634 * Don't send any more packet to chip if there has been
637 if (!(stat & BS_STAT_DMAERR))
642 * Check to see if we have any key setups/rng's waiting for us
644 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) &&
645 (stat & BS_STAT_MCR2_DONE)) {
647 struct ubsec_mcr *mcr;
649 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) {
650 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2);
652 ubsec_dma_sync(&q2->q_mcr,
653 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
655 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr;
656 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) {
657 ubsec_dma_sync(&q2->q_mcr,
658 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
661 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q2, q_next);
662 ubsec_callback2(sc, q2);
664 * Don't send any more packet to chip if there has been
667 if (!(stat & BS_STAT_DMAERR))
673 * Check to see if we got any DMA Error
675 if (stat & BS_STAT_DMAERR) {
678 volatile u_int32_t a = READ_REG(sc, BS_ERR);
680 printf("dmaerr %s@%08x\n",
681 (a & BS_ERR_READ) ? "read" : "write",
684 #endif /* UBSEC_DEBUG */
685 ubsecstats.hst_dmaerr++;
686 ubsec_totalreset(sc);
690 if (sc->sc_needwakeup) { /* XXX check high watermark */
691 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);
694 device_printf(sc->sc_dev, "wakeup crypto (%x)\n",
696 #endif /* UBSEC_DEBUG */
697 sc->sc_needwakeup &= ~wakeup;
698 crypto_unblock(sc->sc_cid, wakeup);
703 * ubsec_feed() - aggregate and post requests to chip
706 ubsec_feed(struct ubsec_softc *sc)
708 struct ubsec_q *q, *q2;
714 * Decide how many ops to combine in a single MCR. We cannot
715 * aggregate more than UBS_MAX_AGGR because this is the number
716 * of slots defined in the data structure. Note that
717 * aggregation only happens if ops are marked batch'able.
718 * Aggregating ops reduces the number of interrupts to the host
719 * but also (potentially) increases the latency for processing
720 * completed ops as we only get an interrupt when all aggregated
721 * ops have completed.
723 if (sc->sc_nqueue == 0)
725 if (sc->sc_nqueue > 1) {
727 SIMPLEQ_FOREACH(q, &sc->sc_queue, q_next) {
729 if ((q->q_crp->crp_flags & CRYPTO_F_BATCH) == 0)
735 * Check device status before going any further.
737 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) {
738 if (stat & BS_STAT_DMAERR) {
739 ubsec_totalreset(sc);
740 ubsecstats.hst_dmaerr++;
742 ubsecstats.hst_mcr1full++;
745 if (sc->sc_nqueue > ubsecstats.hst_maxqueue)
746 ubsecstats.hst_maxqueue = sc->sc_nqueue;
747 if (npkts > UBS_MAX_AGGR)
748 npkts = UBS_MAX_AGGR;
749 if (npkts < 2) /* special case 1 op */
752 ubsecstats.hst_totbatch += npkts-1;
755 printf("merging %d records\n", npkts);
756 #endif /* UBSEC_DEBUG */
758 q = SIMPLEQ_FIRST(&sc->sc_queue);
759 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next);
762 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
763 if (q->q_dst_map != NULL)
764 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
766 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */
768 for (i = 0; i < q->q_nstacked_mcrs; i++) {
769 q2 = SIMPLEQ_FIRST(&sc->sc_queue);
770 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map,
771 BUS_DMASYNC_PREWRITE);
772 if (q2->q_dst_map != NULL)
773 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map,
774 BUS_DMASYNC_PREREAD);
775 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q2, q_next);
778 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) -
779 sizeof(struct ubsec_mcr_add));
780 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add));
781 q->q_stacked_mcr[i] = q2;
783 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts);
784 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
785 sc->sc_nqchip += npkts;
786 if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
787 ubsecstats.hst_maxqchip = sc->sc_nqchip;
788 ubsec_dma_sync(&q->q_dma->d_alloc,
789 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
790 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
791 offsetof(struct ubsec_dmachunk, d_mcr));
795 q = SIMPLEQ_FIRST(&sc->sc_queue);
797 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
798 if (q->q_dst_map != NULL)
799 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
800 ubsec_dma_sync(&q->q_dma->d_alloc,
801 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
803 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
804 offsetof(struct ubsec_dmachunk, d_mcr));
807 printf("feed1: q->chip %p %08x stat %08x\n",
808 q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr),
810 #endif /* UBSEC_DEBUG */
811 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next);
813 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
815 if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
816 ubsecstats.hst_maxqchip = sc->sc_nqchip;
821 * Allocate a new 'session' and return an encoded session id. 'sidp'
822 * contains our registration id, and should contain an encoded session
823 * id on successful allocation.
826 ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri)
828 struct cryptoini *c, *encini = NULL, *macini = NULL;
829 struct ubsec_softc *sc = arg;
830 struct ubsec_session *ses = NULL;
835 KASSERT(sc != NULL, ("ubsec_newsession: null softc"));
836 if (sidp == NULL || cri == NULL || sc == NULL)
839 for (c = cri; c != NULL; c = c->cri_next) {
840 if (c->cri_alg == CRYPTO_MD5_HMAC ||
841 c->cri_alg == CRYPTO_SHA1_HMAC) {
845 } else if (c->cri_alg == CRYPTO_DES_CBC ||
846 c->cri_alg == CRYPTO_3DES_CBC) {
853 if (encini == NULL && macini == NULL)
856 if (sc->sc_sessions == NULL) {
857 ses = sc->sc_sessions = kmalloc(sizeof(struct ubsec_session),
858 M_DEVBUF, M_INTWAIT);
860 sc->sc_nsessions = 1;
862 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
863 if (sc->sc_sessions[sesn].ses_used == 0) {
864 ses = &sc->sc_sessions[sesn];
870 sesn = sc->sc_nsessions;
871 ses = kmalloc((sesn + 1) * sizeof(struct ubsec_session),
872 M_DEVBUF, M_INTWAIT);
873 bcopy(sc->sc_sessions, ses, sesn *
874 sizeof(struct ubsec_session));
875 bzero(sc->sc_sessions, sesn *
876 sizeof(struct ubsec_session));
877 kfree(sc->sc_sessions, M_DEVBUF);
878 sc->sc_sessions = ses;
879 ses = &sc->sc_sessions[sesn];
884 bzero(ses, sizeof(struct ubsec_session));
887 /* get an IV, network byte order */
888 /* XXX may read fewer than requested */
889 read_random(ses->ses_iv, sizeof(ses->ses_iv));
891 /* Go ahead and compute key in ubsec's byte order */
892 if (encini->cri_alg == CRYPTO_DES_CBC) {
893 bcopy(encini->cri_key, &ses->ses_deskey[0], 8);
894 bcopy(encini->cri_key, &ses->ses_deskey[2], 8);
895 bcopy(encini->cri_key, &ses->ses_deskey[4], 8);
897 bcopy(encini->cri_key, ses->ses_deskey, 24);
899 SWAP32(ses->ses_deskey[0]);
900 SWAP32(ses->ses_deskey[1]);
901 SWAP32(ses->ses_deskey[2]);
902 SWAP32(ses->ses_deskey[3]);
903 SWAP32(ses->ses_deskey[4]);
904 SWAP32(ses->ses_deskey[5]);
908 for (i = 0; i < macini->cri_klen / 8; i++)
909 macini->cri_key[i] ^= HMAC_IPAD_VAL;
911 if (macini->cri_alg == CRYPTO_MD5_HMAC) {
913 MD5Update(&md5ctx, macini->cri_key,
914 macini->cri_klen / 8);
915 MD5Update(&md5ctx, hmac_ipad_buffer,
916 HMAC_BLOCK_LEN - (macini->cri_klen / 8));
917 bcopy(md5ctx.state, ses->ses_hminner,
918 sizeof(md5ctx.state));
921 SHA1Update(&sha1ctx, macini->cri_key,
922 macini->cri_klen / 8);
923 SHA1Update(&sha1ctx, hmac_ipad_buffer,
924 HMAC_BLOCK_LEN - (macini->cri_klen / 8));
925 bcopy(sha1ctx.h.b32, ses->ses_hminner,
926 sizeof(sha1ctx.h.b32));
929 for (i = 0; i < macini->cri_klen / 8; i++)
930 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL);
932 if (macini->cri_alg == CRYPTO_MD5_HMAC) {
934 MD5Update(&md5ctx, macini->cri_key,
935 macini->cri_klen / 8);
936 MD5Update(&md5ctx, hmac_opad_buffer,
937 HMAC_BLOCK_LEN - (macini->cri_klen / 8));
938 bcopy(md5ctx.state, ses->ses_hmouter,
939 sizeof(md5ctx.state));
942 SHA1Update(&sha1ctx, macini->cri_key,
943 macini->cri_klen / 8);
944 SHA1Update(&sha1ctx, hmac_opad_buffer,
945 HMAC_BLOCK_LEN - (macini->cri_klen / 8));
946 bcopy(sha1ctx.h.b32, ses->ses_hmouter,
947 sizeof(sha1ctx.h.b32));
950 for (i = 0; i < macini->cri_klen / 8; i++)
951 macini->cri_key[i] ^= HMAC_OPAD_VAL;
954 *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn);
959 * Deallocate a session.
962 ubsec_freesession(void *arg, u_int64_t tid)
964 struct ubsec_softc *sc = arg;
966 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff;
968 KASSERT(sc != NULL, ("ubsec_freesession: null softc"));
972 session = UBSEC_SESSION(sid);
973 if (session >= sc->sc_nsessions)
976 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session]));
981 ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error)
983 struct ubsec_operand *op = arg;
985 KASSERT(nsegs <= UBS_MAX_SCATTER,
986 ("Too many DMA segments returned when mapping operand"));
989 printf("ubsec_op_cb: mapsize %u nsegs %d\n",
990 (u_int) mapsize, nsegs);
992 op->mapsize = mapsize;
994 bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
998 ubsec_process(void *arg, struct cryptop *crp, int hint)
1000 struct ubsec_q *q = NULL;
1001 int err = 0, i, j, nicealign;
1002 struct ubsec_softc *sc = arg;
1003 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
1004 int encoffset = 0, macoffset = 0, cpskip, cpoffset;
1005 int sskip, dskip, stheend, dtheend;
1007 struct ubsec_session *ses;
1008 struct ubsec_pktctx ctx;
1009 struct ubsec_dma *dmap = NULL;
1011 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) {
1012 ubsecstats.hst_invalid++;
1015 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) {
1016 ubsecstats.hst_badsession++;
1022 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
1023 ubsecstats.hst_queuefull++;
1024 sc->sc_needwakeup |= CRYPTO_SYMQ;
1028 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
1029 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next);
1032 dmap = q->q_dma; /* Save dma pointer */
1033 bzero(q, sizeof(struct ubsec_q));
1034 bzero(&ctx, sizeof(ctx));
1036 q->q_sesn = UBSEC_SESSION(crp->crp_sid);
1038 ses = &sc->sc_sessions[q->q_sesn];
1040 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1041 q->q_src_m = (struct mbuf *)crp->crp_buf;
1042 q->q_dst_m = (struct mbuf *)crp->crp_buf;
1043 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1044 q->q_src_io = (struct uio *)crp->crp_buf;
1045 q->q_dst_io = (struct uio *)crp->crp_buf;
1047 ubsecstats.hst_badflags++;
1049 goto errout; /* XXX we don't handle contiguous blocks! */
1052 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr));
1054 dmap->d_dma->d_mcr.mcr_pkts = htole16(1);
1055 dmap->d_dma->d_mcr.mcr_flags = 0;
1058 crd1 = crp->crp_desc;
1060 ubsecstats.hst_nodesc++;
1064 crd2 = crd1->crd_next;
1067 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
1068 crd1->crd_alg == CRYPTO_SHA1_HMAC) {
1071 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
1072 crd1->crd_alg == CRYPTO_3DES_CBC) {
1076 ubsecstats.hst_badalg++;
1081 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
1082 crd1->crd_alg == CRYPTO_SHA1_HMAC) &&
1083 (crd2->crd_alg == CRYPTO_DES_CBC ||
1084 crd2->crd_alg == CRYPTO_3DES_CBC) &&
1085 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
1088 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
1089 crd1->crd_alg == CRYPTO_3DES_CBC) &&
1090 (crd2->crd_alg == CRYPTO_MD5_HMAC ||
1091 crd2->crd_alg == CRYPTO_SHA1_HMAC) &&
1092 (crd1->crd_flags & CRD_F_ENCRYPT)) {
1097 * We cannot order the ubsec as requested
1099 ubsecstats.hst_badalg++;
1106 encoffset = enccrd->crd_skip;
1107 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES);
1109 if (enccrd->crd_flags & CRD_F_ENCRYPT) {
1110 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV;
1112 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1113 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1115 ctx.pc_iv[0] = ses->ses_iv[0];
1116 ctx.pc_iv[1] = ses->ses_iv[1];
1119 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) {
1120 if (crp->crp_flags & CRYPTO_F_IMBUF)
1121 m_copyback(q->q_src_m,
1123 8, (caddr_t)ctx.pc_iv);
1124 else if (crp->crp_flags & CRYPTO_F_IOV)
1125 cuio_copyback(q->q_src_io,
1127 8, (caddr_t)ctx.pc_iv);
1130 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND);
1132 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1133 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1134 else if (crp->crp_flags & CRYPTO_F_IMBUF)
1135 m_copydata(q->q_src_m, enccrd->crd_inject,
1136 8, (caddr_t)ctx.pc_iv);
1137 else if (crp->crp_flags & CRYPTO_F_IOV)
1138 cuio_copydata(q->q_src_io,
1139 enccrd->crd_inject, 8,
1140 (caddr_t)ctx.pc_iv);
1143 ctx.pc_deskey[0] = ses->ses_deskey[0];
1144 ctx.pc_deskey[1] = ses->ses_deskey[1];
1145 ctx.pc_deskey[2] = ses->ses_deskey[2];
1146 ctx.pc_deskey[3] = ses->ses_deskey[3];
1147 ctx.pc_deskey[4] = ses->ses_deskey[4];
1148 ctx.pc_deskey[5] = ses->ses_deskey[5];
1149 SWAP32(ctx.pc_iv[0]);
1150 SWAP32(ctx.pc_iv[1]);
1154 macoffset = maccrd->crd_skip;
1156 if (maccrd->crd_alg == CRYPTO_MD5_HMAC)
1157 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5);
1159 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1);
1161 for (i = 0; i < 5; i++) {
1162 ctx.pc_hminner[i] = ses->ses_hminner[i];
1163 ctx.pc_hmouter[i] = ses->ses_hmouter[i];
1165 HTOLE32(ctx.pc_hminner[i]);
1166 HTOLE32(ctx.pc_hmouter[i]);
1170 if (enccrd && maccrd) {
1172 * ubsec cannot handle packets where the end of encryption
1173 * and authentication are not the same, or where the
1174 * encrypted part begins before the authenticated part.
1176 if ((encoffset + enccrd->crd_len) !=
1177 (macoffset + maccrd->crd_len)) {
1178 ubsecstats.hst_lenmismatch++;
1182 if (enccrd->crd_skip < maccrd->crd_skip) {
1183 ubsecstats.hst_skipmismatch++;
1187 sskip = maccrd->crd_skip;
1188 cpskip = dskip = enccrd->crd_skip;
1189 stheend = maccrd->crd_len;
1190 dtheend = enccrd->crd_len;
1191 coffset = enccrd->crd_skip - maccrd->crd_skip;
1192 cpoffset = cpskip + dtheend;
1195 printf("mac: skip %d, len %d, inject %d\n",
1196 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject);
1197 printf("enc: skip %d, len %d, inject %d\n",
1198 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject);
1199 printf("src: skip %d, len %d\n", sskip, stheend);
1200 printf("dst: skip %d, len %d\n", dskip, dtheend);
1201 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n",
1202 coffset, stheend, cpskip, cpoffset);
1206 cpskip = dskip = sskip = macoffset + encoffset;
1207 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len;
1208 cpoffset = cpskip + dtheend;
1211 ctx.pc_offset = htole16(coffset >> 2);
1213 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) {
1214 ubsecstats.hst_nomap++;
1218 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1219 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map,
1220 q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
1221 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1222 q->q_src_map = NULL;
1223 ubsecstats.hst_noload++;
1227 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1228 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map,
1229 q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
1230 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1231 q->q_src_map = NULL;
1232 ubsecstats.hst_noload++;
1237 nicealign = ubsec_dmamap_aligned(&q->q_src);
1239 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend);
1243 printf("src skip: %d nicealign: %u\n", sskip, nicealign);
1245 for (i = j = 0; i < q->q_src_nsegs; i++) {
1246 struct ubsec_pktbuf *pb;
1247 bus_size_t packl = q->q_src_segs[i].ds_len;
1248 bus_addr_t packp = q->q_src_segs[i].ds_addr;
1250 if (sskip >= packl) {
1259 if (packl > 0xfffc) {
1265 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf;
1267 pb = &dmap->d_dma->d_sbuf[j - 1];
1269 pb->pb_addr = htole32(packp);
1272 if (packl > stheend) {
1273 pb->pb_len = htole32(stheend);
1276 pb->pb_len = htole32(packl);
1280 pb->pb_len = htole32(packl);
1282 if ((i + 1) == q->q_src_nsegs)
1285 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1286 offsetof(struct ubsec_dmachunk, d_sbuf[j]));
1290 if (enccrd == NULL && maccrd != NULL) {
1291 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0;
1292 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0;
1293 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr +
1294 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1297 printf("opkt: %x %x %x\n",
1298 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr,
1299 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len,
1300 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next);
1303 if (crp->crp_flags & CRYPTO_F_IOV) {
1305 ubsecstats.hst_iovmisaligned++;
1309 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
1311 ubsecstats.hst_nomap++;
1315 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map,
1316 q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) {
1317 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1318 q->q_dst_map = NULL;
1319 ubsecstats.hst_noload++;
1323 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
1325 q->q_dst = q->q_src;
1328 struct mbuf *m, *top, **mp;
1330 ubsecstats.hst_unaligned++;
1331 totlen = q->q_src_mapsize;
1332 if (q->q_src_m->m_flags & M_PKTHDR) {
1334 MGETHDR(m, MB_DONTWAIT, MT_DATA);
1335 if (m && !m_dup_pkthdr(m, q->q_src_m, MB_DONTWAIT)) {
1341 MGET(m, MB_DONTWAIT, MT_DATA);
1344 ubsecstats.hst_nombuf++;
1345 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1348 if (totlen >= MINCLSIZE) {
1349 MCLGET(m, MB_DONTWAIT);
1350 if ((m->m_flags & M_EXT) == 0) {
1352 ubsecstats.hst_nomcl++;
1353 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1362 while (totlen > 0) {
1364 MGET(m, MB_DONTWAIT, MT_DATA);
1367 ubsecstats.hst_nombuf++;
1368 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1373 if (top && totlen >= MINCLSIZE) {
1374 MCLGET(m, MB_DONTWAIT);
1375 if ((m->m_flags & M_EXT) == 0) {
1378 ubsecstats.hst_nomcl++;
1379 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1384 m->m_len = len = min(totlen, len);
1390 ubsec_mcopy(q->q_src_m, q->q_dst_m,
1392 if (bus_dmamap_create(sc->sc_dmat,
1393 BUS_DMA_NOWAIT, &q->q_dst_map) != 0) {
1394 ubsecstats.hst_nomap++;
1398 if (bus_dmamap_load_mbuf(sc->sc_dmat,
1399 q->q_dst_map, q->q_dst_m,
1400 ubsec_op_cb, &q->q_dst,
1401 BUS_DMA_NOWAIT) != 0) {
1402 bus_dmamap_destroy(sc->sc_dmat,
1404 q->q_dst_map = NULL;
1405 ubsecstats.hst_noload++;
1411 ubsecstats.hst_badflags++;
1418 printf("dst skip: %d\n", dskip);
1420 for (i = j = 0; i < q->q_dst_nsegs; i++) {
1421 struct ubsec_pktbuf *pb;
1422 bus_size_t packl = q->q_dst_segs[i].ds_len;
1423 bus_addr_t packp = q->q_dst_segs[i].ds_addr;
1425 if (dskip >= packl) {
1434 if (packl > 0xfffc) {
1440 pb = &dmap->d_dma->d_mcr.mcr_opktbuf;
1442 pb = &dmap->d_dma->d_dbuf[j - 1];
1444 pb->pb_addr = htole32(packp);
1447 if (packl > dtheend) {
1448 pb->pb_len = htole32(dtheend);
1451 pb->pb_len = htole32(packl);
1455 pb->pb_len = htole32(packl);
1457 if ((i + 1) == q->q_dst_nsegs) {
1459 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1460 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1464 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1465 offsetof(struct ubsec_dmachunk, d_dbuf[j]));
1470 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr +
1471 offsetof(struct ubsec_dmachunk, d_ctx));
1473 if (sc->sc_flags & UBS_FLAGS_LONGCTX) {
1474 struct ubsec_pktctx_long *ctxl;
1476 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr +
1477 offsetof(struct ubsec_dmachunk, d_ctx));
1479 /* transform small context into long context */
1480 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long));
1481 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC);
1482 ctxl->pc_flags = ctx.pc_flags;
1483 ctxl->pc_offset = ctx.pc_offset;
1484 for (i = 0; i < 6; i++)
1485 ctxl->pc_deskey[i] = ctx.pc_deskey[i];
1486 for (i = 0; i < 5; i++)
1487 ctxl->pc_hminner[i] = ctx.pc_hminner[i];
1488 for (i = 0; i < 5; i++)
1489 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i];
1490 ctxl->pc_iv[0] = ctx.pc_iv[0];
1491 ctxl->pc_iv[1] = ctx.pc_iv[1];
1493 bcopy(&ctx, dmap->d_alloc.dma_vaddr +
1494 offsetof(struct ubsec_dmachunk, d_ctx),
1495 sizeof(struct ubsec_pktctx));
1498 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next);
1500 ubsecstats.hst_ipackets++;
1501 ubsecstats.hst_ibytes += dmap->d_alloc.dma_size;
1502 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= UBS_MAX_AGGR)
1509 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
1510 m_freem(q->q_dst_m);
1512 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1513 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1514 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1516 if (q->q_src_map != NULL) {
1517 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1518 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1522 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1525 if (err != ERESTART) {
1526 crp->crp_etype = err;
1529 sc->sc_needwakeup |= CRYPTO_SYMQ;
1535 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q)
1537 struct cryptop *crp = (struct cryptop *)q->q_crp;
1538 struct cryptodesc *crd;
1539 struct ubsec_dma *dmap = q->q_dma;
1541 ubsecstats.hst_opackets++;
1542 ubsecstats.hst_obytes += dmap->d_alloc.dma_size;
1544 ubsec_dma_sync(&dmap->d_alloc,
1545 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1546 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1547 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
1548 BUS_DMASYNC_POSTREAD);
1549 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1550 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1552 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE);
1553 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1554 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1556 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) {
1557 m_freem(q->q_src_m);
1558 crp->crp_buf = (caddr_t)q->q_dst_m;
1560 ubsecstats.hst_obytes += ((struct mbuf *)crp->crp_buf)->m_len;
1562 /* copy out IV for future use */
1563 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) {
1564 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1565 if (crd->crd_alg != CRYPTO_DES_CBC &&
1566 crd->crd_alg != CRYPTO_3DES_CBC)
1568 if (crp->crp_flags & CRYPTO_F_IMBUF)
1569 m_copydata((struct mbuf *)crp->crp_buf,
1570 crd->crd_skip + crd->crd_len - 8, 8,
1571 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1572 else if (crp->crp_flags & CRYPTO_F_IOV) {
1573 cuio_copydata((struct uio *)crp->crp_buf,
1574 crd->crd_skip + crd->crd_len - 8, 8,
1575 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1581 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1582 if (crd->crd_alg != CRYPTO_MD5_HMAC &&
1583 crd->crd_alg != CRYPTO_SHA1_HMAC)
1585 if (crp->crp_flags & CRYPTO_F_IMBUF)
1586 m_copyback((struct mbuf *)crp->crp_buf,
1587 crd->crd_inject, 12,
1588 (caddr_t)dmap->d_dma->d_macbuf);
1589 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac)
1590 bcopy((caddr_t)dmap->d_dma->d_macbuf,
1594 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1599 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset)
1601 int i, j, dlen, slen;
1605 sptr = srcm->m_data;
1607 dptr = dstm->m_data;
1611 for (i = 0; i < min(slen, dlen); i++) {
1612 if (j < hoffset || j >= toffset)
1619 srcm = srcm->m_next;
1622 sptr = srcm->m_data;
1626 dstm = dstm->m_next;
1629 dptr = dstm->m_data;
1636 * feed the key generator, must be called at splimp() or higher.
1639 ubsec_feed2(struct ubsec_softc *sc)
1643 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) {
1644 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL)
1646 q = SIMPLEQ_FIRST(&sc->sc_queue2);
1648 ubsec_dma_sync(&q->q_mcr,
1649 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1650 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE);
1652 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr);
1653 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q, q_next);
1655 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next);
1661 * Callback for handling random numbers
1664 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q)
1666 struct cryptkop *krp;
1667 struct ubsec_ctx_keyop *ctx;
1669 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr;
1670 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE);
1672 switch (q->q_type) {
1673 #ifndef UBSEC_NO_RNG
1674 case UBS_CTXOP_RNGBYPASS: {
1675 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q;
1677 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD);
1678 (*sc->sc_harvest)(sc->sc_rndtest,
1679 rng->rng_buf.dma_vaddr,
1680 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t));
1682 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1686 case UBS_CTXOP_MODEXP: {
1687 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
1691 rlen = (me->me_modbits + 7) / 8;
1692 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8;
1694 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE);
1695 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE);
1696 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD);
1697 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE);
1700 krp->krp_status = E2BIG;
1702 if (sc->sc_flags & UBS_FLAGS_HWNORM) {
1703 bzero(krp->krp_param[krp->krp_iparams].crp_p,
1704 (krp->krp_param[krp->krp_iparams].crp_nbits
1706 bcopy(me->me_C.dma_vaddr,
1707 krp->krp_param[krp->krp_iparams].crp_p,
1708 (me->me_modbits + 7) / 8);
1710 ubsec_kshift_l(me->me_shiftbits,
1711 me->me_C.dma_vaddr, me->me_normbits,
1712 krp->krp_param[krp->krp_iparams].crp_p,
1713 krp->krp_param[krp->krp_iparams].crp_nbits);
1718 /* bzero all potentially sensitive data */
1719 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
1720 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
1721 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
1722 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
1724 /* Can't free here, so put us on the free list. */
1725 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next);
1728 case UBS_CTXOP_RSAPRIV: {
1729 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
1733 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE);
1734 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD);
1736 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8;
1737 bcopy(rp->rpr_msgout.dma_vaddr,
1738 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len);
1742 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
1743 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
1744 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size);
1746 /* Can't free here, so put us on the free list. */
1747 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next);
1751 device_printf(sc->sc_dev, "unknown ctx op: %x\n",
1752 letoh16(ctx->ctx_op));
1757 #ifndef UBSEC_NO_RNG
1759 ubsec_rng(void *vsc)
1761 struct ubsec_softc *sc = vsc;
1762 struct ubsec_q2_rng *rng = &sc->sc_rng;
1763 struct ubsec_mcr *mcr;
1764 struct ubsec_ctx_rngbypass *ctx;
1767 if (rng->rng_used) {
1772 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE)
1775 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr;
1776 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr;
1778 mcr->mcr_pkts = htole16(1);
1780 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr);
1781 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0;
1782 mcr->mcr_ipktbuf.pb_len = 0;
1783 mcr->mcr_reserved = mcr->mcr_pktlen = 0;
1784 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr);
1785 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) &
1787 mcr->mcr_opktbuf.pb_next = 0;
1789 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass));
1790 ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS);
1791 rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS;
1793 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD);
1795 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next);
1798 ubsecstats.hst_rng++;
1805 * Something weird happened, generate our own call back.
1809 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1811 #endif /* UBSEC_NO_RNG */
1814 ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1816 bus_addr_t *paddr = (bus_addr_t*) arg;
1817 *paddr = segs->ds_addr;
1822 struct ubsec_softc *sc,
1824 struct ubsec_dma_alloc *dma,
1830 /* XXX could specify sc_dmat as parent but that just adds overhead */
1831 r = bus_dma_tag_create(NULL, /* parent */
1832 1, 0, /* alignment, bounds */
1833 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1834 BUS_SPACE_MAXADDR, /* highaddr */
1835 NULL, NULL, /* filter, filterarg */
1838 size, /* maxsegsize */
1839 BUS_DMA_ALLOCNOW, /* flags */
1842 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1843 "bus_dma_tag_create failed; error %u\n", r);
1847 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map);
1849 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1850 "bus_dmamap_create failed; error %u\n", r);
1854 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr,
1855 BUS_DMA_NOWAIT, &dma->dma_map);
1857 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1858 "bus_dmammem_alloc failed; size %u, error %u\n",
1863 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
1867 mapflags | BUS_DMA_NOWAIT);
1869 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1870 "bus_dmamap_load failed; error %u\n", r);
1874 dma->dma_size = size;
1878 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1880 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1882 bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
1883 bus_dma_tag_destroy(dma->dma_tag);
1885 dma->dma_map = NULL;
1886 dma->dma_tag = NULL;
1891 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma)
1893 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1894 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1895 bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
1896 bus_dma_tag_destroy(dma->dma_tag);
1900 * Resets the board. Values in the regesters are left as is
1901 * from the reset (i.e. initial values are assigned elsewhere).
1904 ubsec_reset_board(struct ubsec_softc *sc)
1906 volatile u_int32_t ctrl;
1908 ctrl = READ_REG(sc, BS_CTRL);
1909 ctrl |= BS_CTRL_RESET;
1910 WRITE_REG(sc, BS_CTRL, ctrl);
1913 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us
1919 * Init Broadcom registers
1922 ubsec_init_board(struct ubsec_softc *sc)
1926 ctrl = READ_REG(sc, BS_CTRL);
1927 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64);
1928 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT;
1930 if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG))
1931 ctrl |= BS_CTRL_MCR2INT;
1933 ctrl &= ~BS_CTRL_MCR2INT;
1935 if (sc->sc_flags & UBS_FLAGS_HWNORM)
1936 ctrl &= ~BS_CTRL_SWNORM;
1938 WRITE_REG(sc, BS_CTRL, ctrl);
1942 * Init Broadcom PCI registers
1945 ubsec_init_pciregs(device_t dev)
1950 misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT);
1951 misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT))
1952 | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT);
1953 misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT))
1954 | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT);
1955 pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc);
1959 * This will set the cache line size to 1, this will
1960 * force the BCM58xx chip just to do burst read/writes.
1961 * Cache line read/writes are to slow
1963 pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1);
1967 * Clean up after a chip crash.
1968 * It is assumed that the caller in splimp()
1971 ubsec_cleanchip(struct ubsec_softc *sc)
1975 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
1976 q = SIMPLEQ_FIRST(&sc->sc_qchip);
1977 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next);
1978 ubsec_free_q(sc, q);
1985 * It is assumed that the caller is within spimp()
1988 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q)
1991 struct cryptop *crp;
1995 npkts = q->q_nstacked_mcrs;
1997 for (i = 0; i < npkts; i++) {
1998 if(q->q_stacked_mcr[i]) {
1999 q2 = q->q_stacked_mcr[i];
2001 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m))
2002 m_freem(q2->q_dst_m);
2004 crp = (struct cryptop *)q2->q_crp;
2006 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next);
2008 crp->crp_etype = EFAULT;
2018 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
2019 m_freem(q->q_dst_m);
2021 crp = (struct cryptop *)q->q_crp;
2023 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
2025 crp->crp_etype = EFAULT;
2031 * Routine to reset the chip and clean up.
2032 * It is assumed that the caller is in splimp()
2035 ubsec_totalreset(struct ubsec_softc *sc)
2037 ubsec_reset_board(sc);
2038 ubsec_init_board(sc);
2039 ubsec_cleanchip(sc);
2043 ubsec_dmamap_aligned(struct ubsec_operand *op)
2047 for (i = 0; i < op->nsegs; i++) {
2048 if (op->segs[i].ds_addr & 3)
2050 if ((i != (op->nsegs - 1)) &&
2051 (op->segs[i].ds_len & 3))
2058 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q)
2060 switch (q->q_type) {
2061 case UBS_CTXOP_MODEXP: {
2062 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
2064 ubsec_dma_free(sc, &me->me_q.q_mcr);
2065 ubsec_dma_free(sc, &me->me_q.q_ctx);
2066 ubsec_dma_free(sc, &me->me_M);
2067 ubsec_dma_free(sc, &me->me_E);
2068 ubsec_dma_free(sc, &me->me_C);
2069 ubsec_dma_free(sc, &me->me_epb);
2070 kfree(me, M_DEVBUF);
2073 case UBS_CTXOP_RSAPRIV: {
2074 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
2076 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2077 ubsec_dma_free(sc, &rp->rpr_q.q_ctx);
2078 ubsec_dma_free(sc, &rp->rpr_msgin);
2079 ubsec_dma_free(sc, &rp->rpr_msgout);
2080 kfree(rp, M_DEVBUF);
2084 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type);
2090 ubsec_kprocess(void *arg, struct cryptkop *krp, int hint)
2092 struct ubsec_softc *sc = arg;
2095 if (krp == NULL || krp->krp_callback == NULL)
2098 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) {
2101 q = SIMPLEQ_FIRST(&sc->sc_q2free);
2102 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q, q_next);
2106 switch (krp->krp_op) {
2108 if (sc->sc_flags & UBS_FLAGS_HWNORM)
2109 r = ubsec_kprocess_modexp_hw(sc, krp, hint);
2111 r = ubsec_kprocess_modexp_sw(sc, krp, hint);
2113 case CRK_MOD_EXP_CRT:
2114 return (ubsec_kprocess_rsapriv(sc, krp, hint));
2116 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n",
2118 krp->krp_status = EOPNOTSUPP;
2122 return (0); /* silence compiler */
2126 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization)
2129 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2131 struct ubsec_q2_modexp *me;
2132 struct ubsec_mcr *mcr;
2133 struct ubsec_ctx_modexp *ctx;
2134 struct ubsec_pktbuf *epb;
2136 u_int nbits, normbits, mbits, shiftbits, ebits;
2138 me = kmalloc(sizeof *me, M_DEVBUF, M_INTWAIT | M_ZERO);
2140 me->me_q.q_type = UBS_CTXOP_MODEXP;
2142 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2145 else if (nbits <= 768)
2147 else if (nbits <= 1024)
2149 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2151 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2158 shiftbits = normbits - nbits;
2160 me->me_modbits = nbits;
2161 me->me_shiftbits = shiftbits;
2162 me->me_normbits = normbits;
2164 /* Sanity check: result bits must be >= true modulus bits. */
2165 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2170 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2171 &me->me_q.q_mcr, 0)) {
2175 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2177 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2178 &me->me_q.q_ctx, 0)) {
2183 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2184 if (mbits > nbits) {
2188 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2192 ubsec_kshift_r(shiftbits,
2193 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits,
2194 me->me_M.dma_vaddr, normbits);
2196 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2200 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2202 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2203 if (ebits > nbits) {
2207 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2211 ubsec_kshift_r(shiftbits,
2212 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits,
2213 me->me_E.dma_vaddr, normbits);
2215 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2220 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2221 epb->pb_addr = htole32(me->me_E.dma_paddr);
2223 epb->pb_len = htole32(normbits / 8);
2232 mcr->mcr_pkts = htole16(1);
2234 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2235 mcr->mcr_reserved = 0;
2236 mcr->mcr_pktlen = 0;
2238 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2239 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2240 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2242 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2243 mcr->mcr_opktbuf.pb_next = 0;
2244 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2247 /* Misaligned output buffer will hang the chip. */
2248 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2249 panic("%s: modexp invalid addr 0x%x\n",
2250 device_get_nameunit(sc->sc_dev),
2251 letoh32(mcr->mcr_opktbuf.pb_addr));
2252 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2253 panic("%s: modexp invalid len 0x%x\n",
2254 device_get_nameunit(sc->sc_dev),
2255 letoh32(mcr->mcr_opktbuf.pb_len));
2258 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2259 bzero(ctx, sizeof(*ctx));
2260 ubsec_kshift_r(shiftbits,
2261 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits,
2262 ctx->me_N, normbits);
2263 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2264 ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2265 ctx->me_E_len = htole16(nbits);
2266 ctx->me_N_len = htole16(nbits);
2270 ubsec_dump_mcr(mcr);
2271 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2276 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2279 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2280 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2281 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2282 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2284 /* Enqueue and we're done... */
2286 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2288 ubsecstats.hst_modexp++;
2295 if (me->me_q.q_mcr.dma_map != NULL)
2296 ubsec_dma_free(sc, &me->me_q.q_mcr);
2297 if (me->me_q.q_ctx.dma_map != NULL) {
2298 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2299 ubsec_dma_free(sc, &me->me_q.q_ctx);
2301 if (me->me_M.dma_map != NULL) {
2302 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2303 ubsec_dma_free(sc, &me->me_M);
2305 if (me->me_E.dma_map != NULL) {
2306 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2307 ubsec_dma_free(sc, &me->me_E);
2309 if (me->me_C.dma_map != NULL) {
2310 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2311 ubsec_dma_free(sc, &me->me_C);
2313 if (me->me_epb.dma_map != NULL)
2314 ubsec_dma_free(sc, &me->me_epb);
2315 kfree(me, M_DEVBUF);
2317 krp->krp_status = err;
2323 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization)
2326 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2328 struct ubsec_q2_modexp *me;
2329 struct ubsec_mcr *mcr;
2330 struct ubsec_ctx_modexp *ctx;
2331 struct ubsec_pktbuf *epb;
2333 u_int nbits, normbits, mbits, shiftbits, ebits;
2335 me = kmalloc(sizeof *me, M_DEVBUF, M_INTWAIT | M_ZERO);
2337 me->me_q.q_type = UBS_CTXOP_MODEXP;
2339 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2342 else if (nbits <= 768)
2344 else if (nbits <= 1024)
2346 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2348 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2355 shiftbits = normbits - nbits;
2358 me->me_modbits = nbits;
2359 me->me_shiftbits = shiftbits;
2360 me->me_normbits = normbits;
2362 /* Sanity check: result bits must be >= true modulus bits. */
2363 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2368 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2369 &me->me_q.q_mcr, 0)) {
2373 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2375 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2376 &me->me_q.q_ctx, 0)) {
2381 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2382 if (mbits > nbits) {
2386 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2390 bzero(me->me_M.dma_vaddr, normbits / 8);
2391 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p,
2392 me->me_M.dma_vaddr, (mbits + 7) / 8);
2394 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2398 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2400 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2401 if (ebits > nbits) {
2405 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2409 bzero(me->me_E.dma_vaddr, normbits / 8);
2410 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p,
2411 me->me_E.dma_vaddr, (ebits + 7) / 8);
2413 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2418 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2419 epb->pb_addr = htole32(me->me_E.dma_paddr);
2421 epb->pb_len = htole32((ebits + 7) / 8);
2430 mcr->mcr_pkts = htole16(1);
2432 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2433 mcr->mcr_reserved = 0;
2434 mcr->mcr_pktlen = 0;
2436 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2437 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2438 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2440 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2441 mcr->mcr_opktbuf.pb_next = 0;
2442 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2445 /* Misaligned output buffer will hang the chip. */
2446 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2447 panic("%s: modexp invalid addr 0x%x\n",
2448 device_get_nameunit(sc->sc_dev),
2449 letoh32(mcr->mcr_opktbuf.pb_addr));
2450 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2451 panic("%s: modexp invalid len 0x%x\n",
2452 device_get_nameunit(sc->sc_dev),
2453 letoh32(mcr->mcr_opktbuf.pb_len));
2456 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2457 bzero(ctx, sizeof(*ctx));
2458 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N,
2460 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2461 ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2462 ctx->me_E_len = htole16(ebits);
2463 ctx->me_N_len = htole16(nbits);
2467 ubsec_dump_mcr(mcr);
2468 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2473 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2476 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2477 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2478 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2479 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2481 /* Enqueue and we're done... */
2483 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2491 if (me->me_q.q_mcr.dma_map != NULL)
2492 ubsec_dma_free(sc, &me->me_q.q_mcr);
2493 if (me->me_q.q_ctx.dma_map != NULL) {
2494 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2495 ubsec_dma_free(sc, &me->me_q.q_ctx);
2497 if (me->me_M.dma_map != NULL) {
2498 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2499 ubsec_dma_free(sc, &me->me_M);
2501 if (me->me_E.dma_map != NULL) {
2502 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2503 ubsec_dma_free(sc, &me->me_E);
2505 if (me->me_C.dma_map != NULL) {
2506 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2507 ubsec_dma_free(sc, &me->me_C);
2509 if (me->me_epb.dma_map != NULL)
2510 ubsec_dma_free(sc, &me->me_epb);
2511 kfree(me, M_DEVBUF);
2513 krp->krp_status = err;
2519 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2521 struct ubsec_q2_rsapriv *rp = NULL;
2522 struct ubsec_mcr *mcr;
2523 struct ubsec_ctx_rsapriv *ctx;
2525 u_int padlen, msglen;
2527 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]);
2528 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]);
2529 if (msglen > padlen)
2534 else if (padlen <= 384)
2536 else if (padlen <= 512)
2538 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768)
2540 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024)
2547 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) {
2552 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) {
2557 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) {
2562 rp = kmalloc(sizeof *rp, M_DEVBUF, M_INTWAIT | M_ZERO);
2564 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV;
2566 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2567 &rp->rpr_q.q_mcr, 0)) {
2571 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr;
2573 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv),
2574 &rp->rpr_q.q_ctx, 0)) {
2578 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr;
2579 bzero(ctx, sizeof *ctx);
2582 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p,
2583 &ctx->rpr_buf[0 * (padlen / 8)],
2584 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8);
2587 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p,
2588 &ctx->rpr_buf[1 * (padlen / 8)],
2589 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8);
2592 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p,
2593 &ctx->rpr_buf[2 * (padlen / 8)],
2594 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8);
2597 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p,
2598 &ctx->rpr_buf[3 * (padlen / 8)],
2599 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8);
2602 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p,
2603 &ctx->rpr_buf[4 * (padlen / 8)],
2604 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8);
2606 msglen = padlen * 2;
2608 /* Copy in input message (aligned buffer/length). */
2609 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) {
2610 /* Is this likely? */
2614 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) {
2618 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8);
2619 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p,
2620 rp->rpr_msgin.dma_vaddr,
2621 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8);
2623 /* Prepare space for output message (aligned buffer/length). */
2624 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) {
2625 /* Is this likely? */
2629 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) {
2633 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8);
2635 mcr->mcr_pkts = htole16(1);
2637 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr);
2638 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr);
2639 mcr->mcr_ipktbuf.pb_next = 0;
2640 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size);
2641 mcr->mcr_reserved = 0;
2642 mcr->mcr_pktlen = htole16(msglen);
2643 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr);
2644 mcr->mcr_opktbuf.pb_next = 0;
2645 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size);
2648 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) {
2649 panic("%s: rsapriv: invalid msgin %x(0x%x)",
2650 device_get_nameunit(sc->sc_dev),
2651 rp->rpr_msgin.dma_paddr, rp->rpr_msgin.dma_size);
2653 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) {
2654 panic("%s: rsapriv: invalid msgout %x(0x%x)",
2655 device_get_nameunit(sc->sc_dev),
2656 rp->rpr_msgout.dma_paddr, rp->rpr_msgout.dma_size);
2660 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8));
2661 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV);
2662 ctx->rpr_q_len = htole16(padlen);
2663 ctx->rpr_p_len = htole16(padlen);
2666 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2669 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE);
2670 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD);
2672 /* Enqueue and we're done... */
2674 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next);
2676 ubsecstats.hst_modexpcrt++;
2682 if (rp->rpr_q.q_mcr.dma_map != NULL)
2683 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2684 if (rp->rpr_msgin.dma_map != NULL) {
2685 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
2686 ubsec_dma_free(sc, &rp->rpr_msgin);
2688 if (rp->rpr_msgout.dma_map != NULL) {
2689 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
2690 ubsec_dma_free(sc, &rp->rpr_msgout);
2692 kfree(rp, M_DEVBUF);
2694 krp->krp_status = err;
2701 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb)
2703 printf("addr 0x%x (0x%x) next 0x%x\n",
2704 pb->pb_addr, pb->pb_len, pb->pb_next);
2708 ubsec_dump_ctx2(struct ubsec_ctx_keyop *c)
2710 printf("CTX (0x%x):\n", c->ctx_len);
2711 switch (letoh16(c->ctx_op)) {
2712 case UBS_CTXOP_RNGBYPASS:
2713 case UBS_CTXOP_RNGSHA1:
2715 case UBS_CTXOP_MODEXP:
2717 struct ubsec_ctx_modexp *cx = (void *)c;
2720 printf(" Elen %u, Nlen %u\n",
2721 letoh16(cx->me_E_len), letoh16(cx->me_N_len));
2722 len = (cx->me_N_len + 7)/8;
2723 for (i = 0; i < len; i++)
2724 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]);
2729 printf("unknown context: %x\n", c->ctx_op);
2731 printf("END CTX\n");
2735 ubsec_dump_mcr(struct ubsec_mcr *mcr)
2737 volatile struct ubsec_mcr_add *ma;
2741 printf(" pkts: %u, flags 0x%x\n",
2742 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags));
2743 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp;
2744 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) {
2745 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i,
2746 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen),
2747 letoh16(ma->mcr_reserved));
2748 printf(" %d: ipkt ", i);
2749 ubsec_dump_pb(&ma->mcr_ipktbuf);
2750 printf(" %d: opkt ", i);
2751 ubsec_dump_pb(&ma->mcr_opktbuf);
2754 printf("END MCR\n");
2756 #endif /* UBSEC_DEBUG */
2759 * Return the number of significant bits of a big number.
2762 ubsec_ksigbits(struct crparam *cr)
2764 u_int plen = (cr->crp_nbits + 7) / 8;
2765 int i, sig = plen * 8;
2766 u_int8_t c, *p = cr->crp_p;
2768 for (i = plen - 1; i >= 0; i--) {
2771 while ((c & 0x80) == 0) {
2785 u_int8_t *src, u_int srcbits,
2786 u_int8_t *dst, u_int dstbits)
2791 slen = (srcbits + 7) / 8;
2792 dlen = (dstbits + 7) / 8;
2794 for (i = 0; i < slen; i++)
2796 for (i = 0; i < dlen - slen; i++)
2804 dst[di--] = dst[si--];
2811 for (i = dlen - 1; i > 0; i--)
2812 dst[i] = (dst[i] << n) |
2813 (dst[i - 1] >> (8 - n));
2814 dst[0] = dst[0] << n;
2821 u_int8_t *src, u_int srcbits,
2822 u_int8_t *dst, u_int dstbits)
2824 int slen, dlen, i, n;
2826 slen = (srcbits + 7) / 8;
2827 dlen = (dstbits + 7) / 8;
2830 for (i = 0; i < slen; i++)
2831 dst[i] = src[i + n];
2832 for (i = 0; i < dlen - slen; i++)
2837 for (i = 0; i < (dlen - 1); i++)
2838 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n));
2839 dst[dlen - 1] = dst[dlen - 1] >> n;