2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $
33 * $DragonFly: src/sys/dev/netif/sis/if_sis.c,v 1.30 2005/11/28 17:13:44 dillon Exp $
37 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
38 * available from http://www.sis.com.tw.
40 * This driver also supports the NatSemi DP83815. Datasheets are
41 * available from http://www.national.com.
43 * Written by Bill Paul <wpaul@ee.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
50 * simple TX and RX descriptors of 3 longwords in size. The receiver
51 * has a single perfect filter entry for the station address and a
52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
53 * transceiver while the 7016 requires an external transceiver chip.
54 * Both chips offer the standard bit-bang MII interface as well as
55 * an enchanced PHY interface which simplifies accessing MII registers.
57 * The only downside to this chipset is that RX descriptors must be
61 #include "opt_polling.h"
63 #include <sys/param.h>
64 #include <sys/systm.h>
65 #include <sys/sockio.h>
67 #include <sys/malloc.h>
68 #include <sys/kernel.h>
69 #include <sys/socket.h>
70 #include <sys/sysctl.h>
71 #include <sys/serialize.h>
72 #include <sys/thread2.h>
75 #include <net/ifq_var.h>
76 #include <net/if_arp.h>
77 #include <net/ethernet.h>
78 #include <net/if_dl.h>
79 #include <net/if_media.h>
80 #include <net/if_types.h>
81 #include <net/vlan/if_vlan_var.h>
85 #include <machine/bus_pio.h>
86 #include <machine/bus_memio.h>
87 #include <machine/bus.h>
88 #include <machine/resource.h>
92 #include <dev/netif/mii_layer/mii.h>
93 #include <dev/netif/mii_layer/miivar.h>
95 #include <bus/pci/pcireg.h>
96 #include <bus/pci/pcivar.h>
98 #define SIS_USEIOSPACE
100 #include "if_sisreg.h"
102 /* "controller miibus0" required. See GENERIC if you get errors here. */
103 #include "miibus_if.h"
106 * Various supported device vendors/types and their names.
108 static struct sis_type sis_devs[] = {
109 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
110 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
111 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
115 static int sis_probe(device_t);
116 static int sis_attach(device_t);
117 static int sis_detach(device_t);
119 static int sis_newbuf(struct sis_softc *, struct sis_desc *,
121 static int sis_encap(struct sis_softc *, struct mbuf *, uint32_t *);
122 static void sis_rxeof(struct sis_softc *);
123 static void sis_rxeoc(struct sis_softc *);
124 static void sis_txeof(struct sis_softc *);
125 static void sis_intr(void *);
126 static void sis_tick(void *);
127 static void sis_start(struct ifnet *);
128 static int sis_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
129 static void sis_init(void *);
130 static void sis_stop(struct sis_softc *);
131 static void sis_watchdog(struct ifnet *);
132 static void sis_shutdown(device_t);
133 static int sis_ifmedia_upd(struct ifnet *);
134 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
136 static uint16_t sis_reverse(uint16_t);
137 static void sis_delay(struct sis_softc *);
138 static void sis_eeprom_idle(struct sis_softc *);
139 static void sis_eeprom_putbyte(struct sis_softc *, int);
140 static void sis_eeprom_getword(struct sis_softc *, int, uint16_t *);
141 static void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int);
143 static void sis_read_cmos(struct sis_softc *, device_t, caddr_t, int, int);
144 static void sis_read_mac(struct sis_softc *, device_t, caddr_t);
145 static device_t sis_find_bridge(device_t);
148 static void sis_mii_sync(struct sis_softc *);
149 static void sis_mii_send(struct sis_softc *, uint32_t, int);
150 static int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *);
151 static int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *);
152 static int sis_miibus_readreg(device_t, int, int);
153 static int sis_miibus_writereg(device_t, int, int, int);
154 static void sis_miibus_statchg(device_t);
156 static void sis_setmulti_sis(struct sis_softc *);
157 static void sis_setmulti_ns(struct sis_softc *);
158 static uint32_t sis_mchash(struct sis_softc *, const uint8_t *);
159 static void sis_reset(struct sis_softc *);
160 static int sis_list_rx_init(struct sis_softc *);
161 static int sis_list_tx_init(struct sis_softc *);
163 static void sis_dma_map_desc_ptr(void *, bus_dma_segment_t *, int, int);
164 static void sis_dma_map_desc_next(void *, bus_dma_segment_t *, int, int);
165 static void sis_dma_map_ring(void *, bus_dma_segment_t *, int, int);
166 #ifdef DEVICE_POLLING
167 static poll_handler_t sis_poll;
169 #ifdef SIS_USEIOSPACE
170 #define SIS_RES SYS_RES_IOPORT
171 #define SIS_RID SIS_PCI_LOIO
173 #define SIS_RES SYS_RES_MEMORY
174 #define SIS_RID SIS_PCI_LOMEM
177 static device_method_t sis_methods[] = {
178 /* Device interface */
179 DEVMETHOD(device_probe, sis_probe),
180 DEVMETHOD(device_attach, sis_attach),
181 DEVMETHOD(device_detach, sis_detach),
182 DEVMETHOD(device_shutdown, sis_shutdown),
185 DEVMETHOD(bus_print_child, bus_generic_print_child),
186 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
189 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
190 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
191 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
196 static driver_t sis_driver = {
199 sizeof(struct sis_softc)
202 static devclass_t sis_devclass;
204 DECLARE_DUMMY_MODULE(if_sis);
205 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0);
206 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);
208 #define SIS_SETBIT(sc, reg, x) \
209 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
211 #define SIS_CLRBIT(sc, reg, x) \
212 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
215 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
218 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
221 sis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error)
226 r->sis_next = segs->ds_addr;
230 sis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
235 r->sis_ptr = segs->ds_addr;
239 sis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error)
248 * Routine to reverse the bits in a word. Stolen almost
249 * verbatim from /usr/games/fortune.
252 sis_reverse(uint16_t n)
254 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
255 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
256 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
257 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
263 sis_delay(struct sis_softc *sc)
267 for (idx = (300 / 33) + 1; idx > 0; idx--)
268 CSR_READ_4(sc, SIS_CSR);
272 sis_eeprom_idle(struct sis_softc *sc)
276 SIO_SET(SIS_EECTL_CSEL);
278 SIO_SET(SIS_EECTL_CLK);
281 for (i = 0; i < 25; i++) {
282 SIO_CLR(SIS_EECTL_CLK);
284 SIO_SET(SIS_EECTL_CLK);
288 SIO_CLR(SIS_EECTL_CLK);
290 SIO_CLR(SIS_EECTL_CSEL);
292 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
296 * Send a read command and address to the EEPROM, check for ACK.
299 sis_eeprom_putbyte(struct sis_softc *sc, int addr)
303 d = addr | SIS_EECMD_READ;
306 * Feed in each bit and stobe the clock.
308 for (i = 0x400; i; i >>= 1) {
310 SIO_SET(SIS_EECTL_DIN);
312 SIO_CLR(SIS_EECTL_DIN);
314 SIO_SET(SIS_EECTL_CLK);
316 SIO_CLR(SIS_EECTL_CLK);
322 * Read a word of data stored in the EEPROM at address 'addr.'
325 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
330 /* Force EEPROM to idle state. */
333 /* Enter EEPROM access mode. */
335 SIO_CLR(SIS_EECTL_CLK);
337 SIO_SET(SIS_EECTL_CSEL);
341 * Send address of word we want to read.
343 sis_eeprom_putbyte(sc, addr);
346 * Start reading bits from EEPROM.
348 for (i = 0x8000; i; i >>= 1) {
349 SIO_SET(SIS_EECTL_CLK);
351 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
354 SIO_CLR(SIS_EECTL_CLK);
358 /* Turn off EEPROM access mode. */
365 * Read a sequence of words from the EEPROM.
368 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
371 uint16_t word = 0, *ptr;
373 for (i = 0; i < cnt; i++) {
374 sis_eeprom_getword(sc, off + i, &word);
375 ptr = (uint16_t *)(dest + (i * 2));
385 sis_find_bridge(device_t dev)
387 devclass_t pci_devclass;
388 device_t *pci_devices;
390 device_t *pci_children;
391 int pci_childcount = 0;
392 device_t *busp, *childp;
393 device_t child = NULL;
396 if ((pci_devclass = devclass_find("pci")) == NULL)
399 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
401 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
403 device_get_children(*busp, &pci_children, &pci_childcount);
404 for (j = 0, childp = pci_children; j < pci_childcount;
406 if (pci_get_vendor(*childp) == SIS_VENDORID &&
407 pci_get_device(*childp) == 0x0008) {
415 free(pci_devices, M_TEMP);
416 free(pci_children, M_TEMP);
421 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off,
427 bus_space_tag_t btag;
429 bridge = sis_find_bridge(dev);
432 reg = pci_read_config(bridge, 0x48, 1);
433 pci_write_config(bridge, 0x48, reg|0x40, 1);
436 btag = I386_BUS_SPACE_IO;
438 for (i = 0; i < cnt; i++) {
439 bus_space_write_1(btag, 0x0, 0x70, i + off);
440 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
443 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
447 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
449 uint32_t filtsave, csrsave;
451 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
452 csrsave = CSR_READ_4(sc, SIS_CSR);
454 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
455 CSR_WRITE_4(sc, SIS_CSR, 0);
457 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
459 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
460 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
461 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
462 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
463 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
464 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
466 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
467 CSR_WRITE_4(sc, SIS_CSR, csrsave);
472 * Sync the PHYs by setting data bit and strobing the clock 32 times.
475 sis_mii_sync(struct sis_softc *sc)
479 SIO_SET(SIS_MII_DIR|SIS_MII_DATA);
481 for (i = 0; i < 32; i++) {
482 SIO_SET(SIS_MII_CLK);
484 SIO_CLR(SIS_MII_CLK);
490 * Clock a series of bits through the MII.
493 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt)
497 SIO_CLR(SIS_MII_CLK);
499 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
501 SIO_SET(SIS_MII_DATA);
503 SIO_CLR(SIS_MII_DATA);
505 SIO_CLR(SIS_MII_CLK);
507 SIO_SET(SIS_MII_CLK);
512 * Read an PHY register through the MII.
515 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame)
520 * Set up frame for RX.
522 frame->mii_stdelim = SIS_MII_STARTDELIM;
523 frame->mii_opcode = SIS_MII_READOP;
524 frame->mii_turnaround = 0;
530 SIO_SET(SIS_MII_DIR);
535 * Send command/address info.
537 sis_mii_send(sc, frame->mii_stdelim, 2);
538 sis_mii_send(sc, frame->mii_opcode, 2);
539 sis_mii_send(sc, frame->mii_phyaddr, 5);
540 sis_mii_send(sc, frame->mii_regaddr, 5);
543 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA));
545 SIO_SET(SIS_MII_CLK);
549 SIO_CLR(SIS_MII_DIR);
552 SIO_CLR(SIS_MII_CLK);
554 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;
555 SIO_SET(SIS_MII_CLK);
559 * Now try reading data bits. If the ack failed, we still
560 * need to clock through 16 cycles to keep the PHY(s) in sync.
563 for(i = 0; i < 16; i++) {
564 SIO_CLR(SIS_MII_CLK);
566 SIO_SET(SIS_MII_CLK);
572 for (i = 0x8000; i; i >>= 1) {
573 SIO_CLR(SIS_MII_CLK);
576 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)
577 frame->mii_data |= i;
580 SIO_SET(SIS_MII_CLK);
586 SIO_CLR(SIS_MII_CLK);
588 SIO_SET(SIS_MII_CLK);
597 * Write to a PHY register through the MII.
600 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame)
603 * Set up frame for TX.
606 frame->mii_stdelim = SIS_MII_STARTDELIM;
607 frame->mii_opcode = SIS_MII_WRITEOP;
608 frame->mii_turnaround = SIS_MII_TURNAROUND;
611 * Turn on data output.
613 SIO_SET(SIS_MII_DIR);
617 sis_mii_send(sc, frame->mii_stdelim, 2);
618 sis_mii_send(sc, frame->mii_opcode, 2);
619 sis_mii_send(sc, frame->mii_phyaddr, 5);
620 sis_mii_send(sc, frame->mii_regaddr, 5);
621 sis_mii_send(sc, frame->mii_turnaround, 2);
622 sis_mii_send(sc, frame->mii_data, 16);
625 SIO_SET(SIS_MII_CLK);
627 SIO_CLR(SIS_MII_CLK);
633 SIO_CLR(SIS_MII_DIR);
639 sis_miibus_readreg(device_t dev, int phy, int reg)
641 struct sis_softc *sc;
642 struct sis_mii_frame frame;
644 sc = device_get_softc(dev);
646 if (sc->sis_type == SIS_TYPE_83815) {
650 * The NatSemi chip can take a while after
651 * a reset to come ready, during which the BMSR
652 * returns a value of 0. This is *never* supposed
653 * to happen: some of the BMSR bits are meant to
654 * be hardwired in the on position, and this can
655 * confuse the miibus code a bit during the probe
656 * and attach phase. So we make an effort to check
657 * for this condition and wait for it to clear.
659 if (!CSR_READ_4(sc, NS_BMSR))
661 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
664 * Chipsets < SIS_635 seem not to be able to read/write
665 * through mdio. Use the enhanced PHY access register
668 if (sc->sis_type == SIS_TYPE_900 &&
669 sc->sis_rev < SIS_REV_635) {
675 CSR_WRITE_4(sc, SIS_PHYCTL,
676 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
677 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
679 for (i = 0; i < SIS_TIMEOUT; i++) {
680 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
684 if (i == SIS_TIMEOUT) {
685 device_printf(dev, "PHY failed to come ready\n");
689 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
696 bzero((char *)&frame, sizeof(frame));
698 frame.mii_phyaddr = phy;
699 frame.mii_regaddr = reg;
700 sis_mii_readreg(sc, &frame);
702 return(frame.mii_data);
707 sis_miibus_writereg(device_t dev, int phy, int reg, int data)
709 struct sis_softc *sc;
710 struct sis_mii_frame frame;
712 sc = device_get_softc(dev);
714 if (sc->sis_type == SIS_TYPE_83815) {
717 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
721 if (sc->sis_type == SIS_TYPE_900 &&
722 sc->sis_rev < SIS_REV_635) {
728 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
729 (reg << 6) | SIS_PHYOP_WRITE);
730 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
732 for (i = 0; i < SIS_TIMEOUT; i++) {
733 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
737 if (i == SIS_TIMEOUT)
738 device_printf(dev, "PHY failed to come ready\n");
740 bzero((char *)&frame, sizeof(frame));
742 frame.mii_phyaddr = phy;
743 frame.mii_regaddr = reg;
744 frame.mii_data = data;
745 sis_mii_writereg(sc, &frame);
750 static void sis_miibus_statchg(device_t dev)
752 struct sis_softc *sc;
754 sc = device_get_softc(dev);
759 sis_mchash(struct sis_softc *sc, const uint8_t *addr)
765 /* Compute CRC for the address value. */
766 crc = 0xFFFFFFFF; /* initial value */
768 for (i = 0; i < 6; i++) {
770 for (j = 0; j < 8; j++) {
771 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
775 crc = (crc ^ 0x04c11db6) | carry;
780 * return the filter bit position
782 * The NatSemi chip has a 512-bit filter, which is
783 * different than the SiS, so we special-case it.
785 if (sc->sis_type == SIS_TYPE_83815)
787 else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
794 sis_setmulti_ns(struct sis_softc *sc)
797 struct ifmultiaddr *ifma;
798 uint32_t h = 0, i, filtsave;
801 ifp = &sc->arpcom.ac_if;
803 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
804 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
805 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
810 * We have to explicitly enable the multicast hash table
811 * on the NatSemi chip if we want to use it, which we do.
813 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
814 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
816 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
818 /* first, zot all the existing hash bits */
819 for (i = 0; i < 32; i++) {
820 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2));
821 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
824 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
825 if (ifma->ifma_addr->sa_family != AF_LINK)
828 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
831 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
834 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
837 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
841 sis_setmulti_sis(struct sis_softc *sc)
844 struct ifmultiaddr *ifma;
845 uint32_t h, i, n, ctl;
848 ifp = &sc->arpcom.ac_if;
850 /* hash table size */
851 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
856 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE;
858 if (ifp->if_flags & IFF_BROADCAST)
859 ctl |= SIS_RXFILTCTL_BROAD;
861 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
862 ctl |= SIS_RXFILTCTL_ALLMULTI;
863 if (ifp->if_flags & IFF_PROMISC)
864 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS;
865 for (i = 0; i < n; i++)
868 for (i = 0; i < n; i++)
871 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
872 if (ifma->ifma_addr->sa_family != AF_LINK)
875 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
876 hashes[h >> 4] |= 1 << (h & 0xf);
880 ctl |= SIS_RXFILTCTL_ALLMULTI;
881 for (i = 0; i < n; i++)
886 for (i = 0; i < n; i++) {
887 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
888 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
891 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl);
895 sis_reset(struct sis_softc *sc)
897 struct ifnet *ifp = &sc->arpcom.ac_if;
900 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
902 for (i = 0; i < SIS_TIMEOUT; i++) {
903 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
907 if (i == SIS_TIMEOUT)
908 if_printf(ifp, "reset never completed\n");
910 /* Wait a little while for the chip to get its brains in order. */
914 * If this is a NetSemi chip, make sure to clear
917 if (sc->sis_type == SIS_TYPE_83815) {
918 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
919 CSR_WRITE_4(sc, NS_CLKRUN, 0);
924 * Probe for an SiS chip. Check the PCI vendor and device
925 * IDs against our list and return a device name if we find a match.
928 sis_probe(device_t dev)
934 while(t->sis_name != NULL) {
935 if ((pci_get_vendor(dev) == t->sis_vid) &&
936 (pci_get_device(dev) == t->sis_did)) {
937 device_set_desc(dev, t->sis_name);
947 * Attach the interface. Allocate softc structures, do ifmedia
948 * setup and ethernet/BPF attach.
951 sis_attach(device_t dev)
953 uint8_t eaddr[ETHER_ADDR_LEN];
955 struct sis_softc *sc;
957 int error, rid, waittime;
959 error = waittime = 0;
960 sc = device_get_softc(dev);
962 if (pci_get_device(dev) == SIS_DEVICEID_900)
963 sc->sis_type = SIS_TYPE_900;
964 if (pci_get_device(dev) == SIS_DEVICEID_7016)
965 sc->sis_type = SIS_TYPE_7016;
966 if (pci_get_vendor(dev) == NS_VENDORID)
967 sc->sis_type = SIS_TYPE_83815;
969 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
972 * Handle power management nonsense.
975 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF;
976 if (command == 0x01) {
978 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4);
979 if (command & SIS_PSTATE_MASK) {
980 uint32_t iobase, membase, irq;
982 /* Save important PCI config data. */
983 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4);
984 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4);
985 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4);
987 /* Reset the power state. */
988 device_printf(dev, "chip is in D%d power mode "
989 "-- setting to D0\n", command & SIS_PSTATE_MASK);
990 command &= 0xFFFFFFFC;
991 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4);
993 /* Restore PCI config data. */
994 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4);
995 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4);
996 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4);
1001 * Map control/status registers.
1003 command = pci_read_config(dev, PCIR_COMMAND, 4);
1004 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1005 pci_write_config(dev, PCIR_COMMAND, command, 4);
1006 command = pci_read_config(dev, PCIR_COMMAND, 4);
1008 #ifdef SIS_USEIOSPACE
1009 if (!(command & PCIM_CMD_PORTEN)) {
1010 device_printf(dev, "failed to enable I/O ports!\n");
1015 if (!(command & PCIM_CMD_MEMEN)) {
1016 device_printf(dev, "failed to enable memory mapping!\n");
1023 sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE);
1025 if (sc->sis_res == NULL) {
1026 device_printf(dev, "couldn't map ports/memory\n");
1031 sc->sis_btag = rman_get_bustag(sc->sis_res);
1032 sc->sis_bhandle = rman_get_bushandle(sc->sis_res);
1034 /* Allocate interrupt */
1036 sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1037 RF_SHAREABLE | RF_ACTIVE);
1039 if (sc->sis_irq == NULL) {
1040 device_printf(dev, "couldn't map interrupt\n");
1045 /* Reset the adapter. */
1048 if (sc->sis_type == SIS_TYPE_900 &&
1049 (sc->sis_rev == SIS_REV_635 ||
1050 sc->sis_rev == SIS_REV_900B)) {
1051 SIO_SET(SIS_CFG_RND_CNT);
1052 SIO_SET(SIS_CFG_PERR_DETECT);
1056 * Get station address from the EEPROM.
1058 switch (pci_get_vendor(dev)) {
1061 * Reading the MAC address out of the EEPROM on
1062 * the NatSemi chip takes a bit more work than
1063 * you'd expect. The address spans 4 16-bit words,
1064 * with the first word containing only a single bit.
1065 * You have to shift everything over one bit to
1066 * get it aligned properly. Also, the bits are
1067 * stored backwards (the LSB is really the MSB,
1068 * and so on) so you have to reverse them in order
1069 * to get the MAC address into the form we want.
1070 * Why? Who the hell knows.
1075 sis_read_eeprom(sc, (caddr_t)&tmp,
1076 NS_EE_NODEADDR, 4, 0);
1078 /* Shift everything over one bit. */
1079 tmp[3] = tmp[3] >> 1;
1080 tmp[3] |= tmp[2] << 15;
1081 tmp[2] = tmp[2] >> 1;
1082 tmp[2] |= tmp[1] << 15;
1083 tmp[1] = tmp[1] >> 1;
1084 tmp[1] |= tmp[0] << 15;
1086 /* Now reverse all the bits. */
1087 tmp[3] = sis_reverse(tmp[3]);
1088 tmp[2] = sis_reverse(tmp[2]);
1089 tmp[1] = sis_reverse(tmp[1]);
1091 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN);
1098 * If this is a SiS 630E chipset with an embedded
1099 * SiS 900 controller, we have to read the MAC address
1100 * from the APC CMOS RAM. Our method for doing this
1101 * is very ugly since we have to reach out and grab
1102 * ahold of hardware for which we cannot properly
1103 * allocate resources. This code is only compiled on
1104 * the i386 architecture since the SiS 630E chipset
1105 * is for x86 motherboards only. Note that there are
1106 * a lot of magic numbers in this hack. These are
1107 * taken from SiS's Linux driver. I'd like to replace
1108 * them with proper symbolic definitions, but that
1109 * requires some datasheets that I don't have access
1112 if (sc->sis_rev == SIS_REV_630S ||
1113 sc->sis_rev == SIS_REV_630E ||
1114 sc->sis_rev == SIS_REV_630EA1)
1115 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1117 else if (sc->sis_rev == SIS_REV_635 ||
1118 sc->sis_rev == SIS_REV_630ET)
1119 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1120 else if (sc->sis_rev == SIS_REV_96x) {
1122 * Allow to read EEPROM from LAN. It is shared
1123 * between a 1394 controller and the NIC and each
1124 * time we access it, we need to set SIS_EECMD_REQ.
1126 SIO_SET(SIS_EECMD_REQ);
1127 for (waittime = 0; waittime < SIS_TIMEOUT;
1129 /* Force EEPROM to idle state. */
1130 sis_eeprom_idle(sc);
1131 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1132 sis_read_eeprom(sc, (caddr_t)&eaddr,
1133 SIS_EE_NODEADDR, 3, 0);
1139 * Set SIS_EECTL_CLK to high, so a other master
1140 * can operate on the i2c bus.
1142 SIO_SET(SIS_EECTL_CLK);
1143 /* Refuse EEPROM access by LAN */
1144 SIO_SET(SIS_EECMD_DONE);
1147 sis_read_eeprom(sc, (caddr_t)&eaddr,
1148 SIS_EE_NODEADDR, 3, 0);
1152 callout_init(&sc->sis_timer);
1155 * Allocate the parent bus DMA tag appropriate for PCI.
1157 #define SIS_NSEG_NEW 32
1158 error = bus_dma_tag_create(NULL, /* parent */
1159 1, 0, /* alignment, boundary */
1160 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1161 BUS_SPACE_MAXADDR, /* highaddr */
1162 NULL, NULL, /* filter, filterarg */
1163 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */
1164 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1165 BUS_DMA_ALLOCNOW, /* flags */
1166 &sc->sis_parent_tag);
1171 * Now allocate a tag for the DMA descriptor lists and a chunk
1172 * of DMA-able memory based on the tag. Also obtain the physical
1173 * addresses of the RX and TX ring, which we'll need later.
1174 * All of our lists are allocated as a contiguous block of memory.
1176 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1177 1, 0, /* alignment, boundary */
1178 BUS_SPACE_MAXADDR, /* lowaddr */
1179 BUS_SPACE_MAXADDR, /* highaddr */
1180 NULL, NULL, /* filter, filterarg */
1181 SIS_RX_LIST_SZ, 1, /* maxsize, nsegments */
1182 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1184 &sc->sis_ldata.sis_rx_tag);
1188 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag,
1189 (void **)&sc->sis_ldata.sis_rx_list,
1190 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1191 &sc->sis_ldata.sis_rx_dmamap);
1194 device_printf(dev, "no memory for rx list buffers!\n");
1195 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1196 sc->sis_ldata.sis_rx_tag = NULL;
1200 error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag,
1201 sc->sis_ldata.sis_rx_dmamap,
1202 sc->sis_ldata.sis_rx_list,
1203 sizeof(struct sis_desc), sis_dma_map_ring,
1204 &sc->sis_cdata.sis_rx_paddr, 0);
1207 device_printf(dev, "cannot get address of the rx ring!\n");
1208 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
1209 sc->sis_ldata.sis_rx_list,
1210 sc->sis_ldata.sis_rx_dmamap);
1211 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1212 sc->sis_ldata.sis_rx_tag = NULL;
1216 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1217 1, 0, /* alignment, boundary */
1218 BUS_SPACE_MAXADDR, /* lowaddr */
1219 BUS_SPACE_MAXADDR, /* highaddr */
1220 NULL, NULL, /* filter, filterarg */
1221 SIS_TX_LIST_SZ, 1, /* maxsize, nsegments */
1222 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1224 &sc->sis_ldata.sis_tx_tag);
1228 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag,
1229 (void **)&sc->sis_ldata.sis_tx_list,
1230 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1231 &sc->sis_ldata.sis_tx_dmamap);
1234 device_printf(dev, "no memory for tx list buffers!\n");
1235 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1236 sc->sis_ldata.sis_tx_tag = NULL;
1240 error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag,
1241 sc->sis_ldata.sis_tx_dmamap,
1242 sc->sis_ldata.sis_tx_list,
1243 sizeof(struct sis_desc), sis_dma_map_ring,
1244 &sc->sis_cdata.sis_tx_paddr, 0);
1247 device_printf(dev, "cannot get address of the tx ring!\n");
1248 bus_dmamem_free(sc->sis_ldata.sis_tx_tag,
1249 sc->sis_ldata.sis_tx_list,
1250 sc->sis_ldata.sis_tx_dmamap);
1251 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1252 sc->sis_ldata.sis_tx_tag = NULL;
1256 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1257 1, 0, /* alignment, boundary */
1258 BUS_SPACE_MAXADDR, /* lowaddr */
1259 BUS_SPACE_MAXADDR, /* highaddr */
1260 NULL, NULL, /* filter, filterarg */
1261 MCLBYTES, 1, /* maxsize, nsegments */
1262 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1268 ifp = &sc->arpcom.ac_if;
1270 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1271 ifp->if_mtu = ETHERMTU;
1272 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1273 ifp->if_ioctl = sis_ioctl;
1274 ifp->if_start = sis_start;
1275 ifp->if_watchdog = sis_watchdog;
1276 ifp->if_init = sis_init;
1277 ifp->if_baudrate = 10000000;
1278 ifq_set_maxlen(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
1279 ifq_set_ready(&ifp->if_snd);
1280 #ifdef DEVICE_POLLING
1281 ifp->if_poll = sis_poll;
1283 ifp->if_capenable = ifp->if_capabilities;
1288 if (mii_phy_probe(dev, &sc->sis_miibus,
1289 sis_ifmedia_upd, sis_ifmedia_sts)) {
1290 device_printf(dev, "MII without any PHY!\n");
1296 * Call MI attach routine.
1298 ether_ifattach(ifp, eaddr, NULL);
1301 * Tell the upper layer(s) we support long frames.
1303 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1305 error = bus_setup_intr(dev, sc->sis_irq, INTR_NETSAFE,
1308 ifp->if_serializer);
1311 device_printf(dev, "couldn't set up irq\n");
1312 ether_ifdetach(ifp);
1324 * Shutdown hardware and free up resources. It is called in both the error case
1325 * and the normal detach case so it needs to be careful about only freeing
1326 * resources that have actually been allocated.
1329 sis_detach(device_t dev)
1331 struct sis_softc *sc = device_get_softc(dev);
1332 struct ifnet *ifp = &sc->arpcom.ac_if;
1334 lwkt_serialize_enter(ifp->if_serializer);
1336 if (device_is_attached(dev)) {
1339 ether_ifdetach(ifp);
1342 device_delete_child(dev, sc->sis_miibus);
1343 bus_generic_detach(dev);
1345 if (sc->sis_intrhand)
1346 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
1349 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1351 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1353 if (sc->sis_ldata.sis_rx_tag) {
1354 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag,
1355 sc->sis_ldata.sis_rx_dmamap);
1356 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
1357 sc->sis_ldata.sis_rx_list,
1358 sc->sis_ldata.sis_rx_dmamap);
1359 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1362 if (sc->sis_ldata.sis_tx_tag) {
1363 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag,
1364 sc->sis_ldata.sis_tx_dmamap);
1365 bus_dmamem_free(sc->sis_ldata.sis_tx_tag,
1366 sc->sis_ldata.sis_tx_list,
1367 sc->sis_ldata.sis_tx_dmamap);
1368 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1371 bus_dma_tag_destroy(sc->sis_tag);
1372 if (sc->sis_parent_tag)
1373 bus_dma_tag_destroy(sc->sis_parent_tag);
1375 lwkt_serialize_exit(ifp->if_serializer);
1380 * Initialize the transmit descriptors.
1383 sis_list_tx_init(struct sis_softc *sc)
1385 struct sis_list_data *ld;
1386 struct sis_ring_data *cd;
1389 cd = &sc->sis_cdata;
1390 ld = &sc->sis_ldata;
1392 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1393 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1;
1394 ld->sis_tx_list[i].sis_nextdesc =
1395 &ld->sis_tx_list[nexti];
1396 bus_dmamap_load(sc->sis_ldata.sis_tx_tag,
1397 sc->sis_ldata.sis_tx_dmamap,
1398 &ld->sis_tx_list[nexti],
1399 sizeof(struct sis_desc), sis_dma_map_desc_next,
1400 &ld->sis_tx_list[i], 0);
1401 ld->sis_tx_list[i].sis_mbuf = NULL;
1402 ld->sis_tx_list[i].sis_ptr = 0;
1403 ld->sis_tx_list[i].sis_ctl = 0;
1406 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0;
1408 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, sc->sis_ldata.sis_tx_dmamap,
1409 BUS_DMASYNC_PREWRITE);
1415 * Initialize the RX descriptors and allocate mbufs for them. Note that
1416 * we arrange the descriptors in a closed ring, so that the last descriptor
1417 * points back to the first.
1420 sis_list_rx_init(struct sis_softc *sc)
1422 struct sis_list_data *ld;
1423 struct sis_ring_data *cd;
1426 ld = &sc->sis_ldata;
1427 cd = &sc->sis_cdata;
1429 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1430 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS)
1432 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1;
1433 ld->sis_rx_list[i].sis_nextdesc =
1434 &ld->sis_rx_list[nexti];
1435 bus_dmamap_load(sc->sis_ldata.sis_rx_tag,
1436 sc->sis_ldata.sis_rx_dmamap,
1437 &ld->sis_rx_list[nexti],
1438 sizeof(struct sis_desc), sis_dma_map_desc_next,
1439 &ld->sis_rx_list[i], 0);
1442 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, sc->sis_ldata.sis_rx_dmamap,
1443 BUS_DMASYNC_PREWRITE);
1445 cd->sis_rx_prod = 0;
1451 * Initialize an RX descriptor and attach an MBUF cluster.
1454 sis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m)
1457 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1461 m->m_data = m->m_ext.ext_buf;
1465 c->sis_ctl = SIS_RXLEN;
1467 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map);
1468 bus_dmamap_load(sc->sis_tag, c->sis_map, mtod(m, void *), MCLBYTES,
1469 sis_dma_map_desc_ptr, c, 0);
1470 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE);
1476 * A frame has been uploaded: pass the resulting mbuf chain up to
1477 * the higher level protocols.
1480 sis_rxeof(struct sis_softc *sc)
1484 struct sis_desc *cur_rx;
1485 int i, total_len = 0;
1488 ifp = &sc->arpcom.ac_if;
1489 i = sc->sis_cdata.sis_rx_prod;
1491 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) {
1493 #ifdef DEVICE_POLLING
1494 if (ifp->if_flags & IFF_POLLING) {
1495 if (sc->rxcycles <= 0)
1499 #endif /* DEVICE_POLLING */
1500 cur_rx = &sc->sis_ldata.sis_rx_list[i];
1501 rxstat = cur_rx->sis_rxstat;
1502 bus_dmamap_sync(sc->sis_tag, cur_rx->sis_map,
1503 BUS_DMASYNC_POSTWRITE);
1504 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map);
1505 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map);
1506 m = cur_rx->sis_mbuf;
1507 cur_rx->sis_mbuf = NULL;
1508 total_len = SIS_RXBYTES(cur_rx);
1509 SIS_INC(i, SIS_RX_LIST_CNT);
1512 * If an error occurs, update stats, clear the
1513 * status word and leave the mbuf cluster in place:
1514 * it should simply get re-used next time this descriptor
1515 * comes up in the ring.
1517 if (!(rxstat & SIS_CMDSTS_PKT_OK)) {
1519 if (rxstat & SIS_RXSTAT_COLL)
1520 ifp->if_collisions++;
1521 sis_newbuf(sc, cur_rx, m);
1525 /* No errors; receive the packet. */
1528 * On the x86 we do not have alignment problems, so try to
1529 * allocate a new buffer for the receive ring, and pass up
1530 * the one where the packet is already, saving the expensive
1531 * copy done in m_devget().
1532 * If we are on an architecture with alignment problems, or
1533 * if the allocation fails, then use m_devget and leave the
1534 * existing buffer in the receive ring.
1536 if (sis_newbuf(sc, cur_rx, NULL) == 0)
1537 m->m_pkthdr.len = m->m_len = total_len;
1542 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1543 total_len + ETHER_ALIGN, 0, ifp, NULL);
1544 sis_newbuf(sc, cur_rx, m);
1549 m_adj(m0, ETHER_ALIGN);
1554 ifp->if_input(ifp, m);
1557 sc->sis_cdata.sis_rx_prod = i;
1561 sis_rxeoc(struct sis_softc *sc)
1568 * A frame was downloaded to the chip. It's safe for us to clean up
1573 sis_txeof(struct sis_softc *sc)
1575 struct sis_desc *cur_tx;
1579 ifp = &sc->arpcom.ac_if;
1582 * Go through our tx list and free mbufs for those
1583 * frames that have been transmitted.
1585 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0;
1586 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) {
1587 cur_tx = &sc->sis_ldata.sis_tx_list[idx];
1589 if (SIS_OWNDESC(cur_tx))
1592 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE)
1595 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) {
1597 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS)
1598 ifp->if_collisions++;
1599 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL)
1600 ifp->if_collisions++;
1603 ifp->if_collisions +=
1604 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16;
1607 if (cur_tx->sis_mbuf != NULL) {
1608 m_freem(cur_tx->sis_mbuf);
1609 cur_tx->sis_mbuf = NULL;
1610 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map);
1611 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map);
1615 if (idx != sc->sis_cdata.sis_tx_cons) {
1616 /* we freed up some buffers */
1617 sc->sis_cdata.sis_tx_cons = idx;
1618 ifp->if_flags &= ~IFF_OACTIVE;
1621 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5;
1627 struct sis_softc *sc = xsc;
1628 struct mii_data *mii;
1629 struct ifnet *ifp = &sc->arpcom.ac_if;
1631 lwkt_serialize_enter(ifp->if_serializer);
1633 mii = device_get_softc(sc->sis_miibus);
1636 if (!sc->sis_link) {
1638 if (mii->mii_media_status & IFM_ACTIVE &&
1639 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1641 if (!ifq_is_empty(&ifp->if_snd))
1645 callout_reset(&sc->sis_timer, hz, sis_tick, sc);
1646 lwkt_serialize_exit(ifp->if_serializer);
1649 #ifdef DEVICE_POLLING
1652 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1654 struct sis_softc *sc = ifp->if_softc;
1658 /* disable interrupts */
1659 CSR_WRITE_4(sc, SIS_IER, 0);
1661 case POLL_DEREGISTER:
1662 /* enable interrupts */
1663 CSR_WRITE_4(sc, SIS_IER, 1);
1667 * On the sis, reading the status register also clears it.
1668 * So before returning to intr mode we must make sure that all
1669 * possible pending sources of interrupts have been served.
1670 * In practice this means run to completion the *eof routines,
1671 * and then call the interrupt routine
1673 sc->rxcycles = count;
1676 if (!ifq_is_empty(&ifp->if_snd))
1679 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1682 /* Reading the ISR register clears all interrupts. */
1683 status = CSR_READ_4(sc, SIS_ISR);
1685 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1688 if (status & (SIS_ISR_RX_IDLE))
1689 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1691 if (status & SIS_ISR_SYSERR) {
1699 #endif /* DEVICE_POLLING */
1704 struct sis_softc *sc;
1709 ifp = &sc->arpcom.ac_if;
1711 /* Supress unwanted interrupts */
1712 if (!(ifp->if_flags & IFF_UP)) {
1717 /* Disable interrupts. */
1718 CSR_WRITE_4(sc, SIS_IER, 0);
1721 /* Reading the ISR register clears all interrupts. */
1722 status = CSR_READ_4(sc, SIS_ISR);
1724 if ((status & SIS_INTRS) == 0)
1728 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK |
1733 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_IDLE))
1736 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW))
1739 if (status & (SIS_ISR_RX_IDLE))
1740 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1742 if (status & SIS_ISR_SYSERR) {
1748 /* Re-enable interrupts. */
1749 CSR_WRITE_4(sc, SIS_IER, 1);
1751 if (!ifq_is_empty(&ifp->if_snd))
1756 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1757 * pointers to the fragment pointers.
1760 sis_encap(struct sis_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1762 struct sis_desc *f = NULL;
1764 int frag, cur, cnt = 0;
1767 * If there's no way we can send any packets, return now.
1769 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2)
1773 * Start packing the mbufs in this chain into
1774 * the fragment pointers. Stop when we run out
1775 * of fragments or hit the end of the mbuf chain.
1778 cur = frag = *txidx;
1780 for (m = m_head; m != NULL; m = m->m_next) {
1781 if (m->m_len != 0) {
1782 if ((SIS_TX_LIST_CNT -
1783 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2)
1785 f = &sc->sis_ldata.sis_tx_list[frag];
1786 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len;
1787 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map);
1788 bus_dmamap_load(sc->sis_tag, f->sis_map,
1789 mtod(m, void *), m->m_len,
1790 sis_dma_map_desc_ptr, f, 0);
1791 bus_dmamap_sync(sc->sis_tag, f->sis_map,
1792 BUS_DMASYNC_PREREAD);
1794 f->sis_ctl |= SIS_CMDSTS_OWN;
1796 SIS_INC(frag, SIS_TX_LIST_CNT);
1804 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head;
1805 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE;
1806 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN;
1807 sc->sis_cdata.sis_tx_cnt += cnt;
1814 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1815 * to the mbuf data regions directly in the transmit lists. We also save a
1816 * copy of the pointers since the transmit list fragment pointers are
1817 * physical addresses.
1821 sis_start(struct ifnet *ifp)
1823 struct sis_softc *sc;
1824 struct mbuf *m_head = NULL;
1833 idx = sc->sis_cdata.sis_tx_prod;
1835 if (ifp->if_flags & IFF_OACTIVE)
1839 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) {
1840 m_head = ifq_poll(&ifp->if_snd);
1844 if (sis_encap(sc, m_head, &idx)) {
1845 ifp->if_flags |= IFF_OACTIVE;
1848 ifq_dequeue(&ifp->if_snd, m_head);
1852 * If there's a BPF listener, bounce a copy of this frame
1855 BPF_MTAP(ifp, m_head);
1862 sc->sis_cdata.sis_tx_prod = idx;
1863 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1866 * Set a timeout in case the chip goes out to lunch.
1874 struct sis_softc *sc = xsc;
1875 struct ifnet *ifp = &sc->arpcom.ac_if;
1876 struct mii_data *mii;
1879 * Cancel pending I/O and free all RX/TX buffers.
1883 mii = device_get_softc(sc->sis_miibus);
1885 /* Set MAC address */
1886 if (sc->sis_type == SIS_TYPE_83815) {
1887 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1888 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1889 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1890 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1891 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1892 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1893 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1894 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1895 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1897 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1898 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1899 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1900 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1901 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1902 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1903 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1904 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1905 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1908 /* Init circular RX list. */
1909 if (sis_list_rx_init(sc) == ENOBUFS) {
1910 if_printf(ifp, "initialization failed: "
1911 "no memory for rx buffers\n");
1917 * Init tx descriptors.
1919 sis_list_tx_init(sc);
1922 * For the NatSemi chip, we have to explicitly enable the
1923 * reception of ARP frames, as well as turn on the 'perfect
1924 * match' filter where we store the station address, otherwise
1925 * we won't receive unicasts meant for this host.
1927 if (sc->sis_type == SIS_TYPE_83815) {
1928 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP);
1929 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT);
1932 /* If we want promiscuous mode, set the allframes bit. */
1933 if (ifp->if_flags & IFF_PROMISC)
1934 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1936 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1939 * Set the capture broadcast bit to capture broadcast frames.
1941 if (ifp->if_flags & IFF_BROADCAST)
1942 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1944 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1947 * Load the multicast filter.
1949 if (sc->sis_type == SIS_TYPE_83815)
1950 sis_setmulti_ns(sc);
1952 sis_setmulti_sis(sc);
1954 /* Turn the receive filter on */
1955 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
1958 * Load the address of the RX and TX lists.
1960 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr);
1961 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr);
1963 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
1964 * the PCI bus. When this bit is set, the Max DMA Burst Size
1965 * for TX/RX DMA should be no larger than 16 double words.
1967 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN)
1968 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
1970 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
1972 /* Accept Long Packets for VLAN support */
1973 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
1975 /* Set TX configuration */
1976 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)
1977 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
1979 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
1981 /* Set full/half duplex mode. */
1982 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1983 SIS_SETBIT(sc, SIS_TX_CFG,
1984 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1985 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1987 SIS_CLRBIT(sc, SIS_TX_CFG,
1988 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1989 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1993 * Enable interrupts.
1995 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
1996 #ifdef DEVICE_POLLING
1998 * ... only enable interrupts if we are not polling, make sure
1999 * they are off otherwise.
2001 if (ifp->if_flags & IFF_POLLING)
2002 CSR_WRITE_4(sc, SIS_IER, 0);
2004 #endif /* DEVICE_POLLING */
2005 CSR_WRITE_4(sc, SIS_IER, 1);
2007 /* Enable receiver and transmitter. */
2008 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2009 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
2016 * Page 75 of the DP83815 manual recommends the
2017 * following register settings "for optimum
2018 * performance." Note however that at least three
2019 * of the registers are listed as "reserved" in
2020 * the register map, so who knows what they do.
2022 if (sc->sis_type == SIS_TYPE_83815) {
2023 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
2024 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
2025 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
2026 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
2027 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
2030 ifp->if_flags |= IFF_RUNNING;
2031 ifp->if_flags &= ~IFF_OACTIVE;
2033 callout_reset(&sc->sis_timer, hz, sis_tick, sc);
2037 * Set media options.
2040 sis_ifmedia_upd(struct ifnet *ifp)
2042 struct sis_softc *sc;
2043 struct mii_data *mii;
2047 mii = device_get_softc(sc->sis_miibus);
2049 if (mii->mii_instance) {
2050 struct mii_softc *miisc;
2051 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2052 mii_phy_reset(miisc);
2060 * Report current media status.
2063 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2065 struct sis_softc *sc;
2066 struct mii_data *mii;
2070 mii = device_get_softc(sc->sis_miibus);
2072 ifmr->ifm_active = mii->mii_media_active;
2073 ifmr->ifm_status = mii->mii_media_status;
2077 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2079 struct sis_softc *sc = ifp->if_softc;
2080 struct ifreq *ifr = (struct ifreq *) data;
2081 struct mii_data *mii;
2086 if (ifp->if_flags & IFF_UP) {
2089 if (ifp->if_flags & IFF_RUNNING)
2096 if (sc->sis_type == SIS_TYPE_83815)
2097 sis_setmulti_ns(sc);
2099 sis_setmulti_sis(sc);
2104 mii = device_get_softc(sc->sis_miibus);
2105 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2108 error = ether_ioctl(ifp, command, data);
2115 sis_watchdog(struct ifnet *ifp)
2117 struct sis_softc *sc;
2122 if_printf(ifp, "watchdog timeout\n");
2128 if (!ifq_is_empty(&ifp->if_snd))
2133 * Stop the adapter and free any mbufs allocated to the
2137 sis_stop(struct sis_softc *sc)
2142 ifp = &sc->arpcom.ac_if;
2145 callout_stop(&sc->sis_timer);
2147 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2148 CSR_WRITE_4(sc, SIS_IER, 0);
2149 CSR_WRITE_4(sc, SIS_IMR, 0);
2150 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2152 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2153 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2158 * Free data in the RX lists.
2160 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
2161 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) {
2162 bus_dmamap_unload(sc->sis_tag,
2163 sc->sis_ldata.sis_rx_list[i].sis_map);
2164 bus_dmamap_destroy(sc->sis_tag,
2165 sc->sis_ldata.sis_rx_list[i].sis_map);
2166 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf);
2167 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL;
2170 bzero(sc->sis_ldata.sis_rx_list, sizeof(sc->sis_ldata.sis_rx_list));
2173 * Free the TX list buffers.
2175 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
2176 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) {
2177 bus_dmamap_unload(sc->sis_tag,
2178 sc->sis_ldata.sis_tx_list[i].sis_map);
2179 bus_dmamap_destroy(sc->sis_tag,
2180 sc->sis_ldata.sis_tx_list[i].sis_map);
2181 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf);
2182 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL;
2186 bzero(sc->sis_ldata.sis_tx_list, sizeof(sc->sis_ldata.sis_tx_list));
2190 * Stop all chip I/O so that the kernel's probe routines don't
2191 * get confused by errant DMAs when rebooting.
2194 sis_shutdown(device_t dev)
2196 struct sis_softc *sc;
2199 sc = device_get_softc(dev);
2200 ifp = &sc->arpcom.ac_if;
2201 lwkt_serialize_enter(ifp->if_serializer);
2204 lwkt_serialize_exit(ifp->if_serializer);