2 * Copyright (c) 1990 The Regents of the University of California.
3 * Copyright (c) 2008 The DragonFly Project.
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz and Don Ahn.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
38 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
42 * Routines to handle clock hardware.
46 * inittodr, settodr and support routines written
47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
54 #include "opt_clock.h"
57 #include <sys/param.h>
58 #include <sys/systm.h>
59 #include <sys/eventhandler.h>
61 #include <sys/kernel.h>
66 #include <sys/sysctl.h>
68 #include <sys/systimer.h>
69 #include <sys/globaldata.h>
70 #include <sys/thread2.h>
71 #include <sys/systimer.h>
72 #include <sys/machintr.h>
74 #include <machine/clock.h>
75 #ifdef CLK_CALIBRATION_LOOP
77 #include <machine/cputypes.h>
78 #include <machine/frame.h>
79 #include <machine/ipl.h>
80 #include <machine/limits.h>
81 #include <machine/md_var.h>
82 #include <machine/psl.h>
83 #include <machine/segments.h>
84 #include <machine/smp.h>
85 #include <machine/specialreg.h>
87 #include <machine_base/icu/icu.h>
88 #include <bus/isa/isa.h>
89 #include <bus/isa/rtc.h>
90 #include <machine_base/isa/timerreg.h>
92 #include <machine_base/isa/intr_machdep.h>
95 /* The interrupt triggered by the 8254 (timer) chip */
97 static void setup_8254_mixed_mode (void);
99 static void i8254_restore(void);
100 static void resettodr_on_shutdown(void *arg __unused);
103 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
104 * can use a simple formula for leap years.
106 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
107 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
110 #define TIMER_FREQ 1193182
113 static uint8_t i8254_walltimer_sel;
114 static uint16_t i8254_walltimer_cntr;
116 int adjkerntz; /* local offset from GMT in seconds */
117 int disable_rtc_set; /* disable resettodr() if != 0 */
118 int statclock_disable = 1; /* we don't use the statclock right now */
120 int64_t tsc_frequency;
122 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
124 enum tstate { RELEASED, ACQUIRED };
125 enum tstate timer0_state;
126 enum tstate timer1_state;
127 enum tstate timer2_state;
129 static int beeping = 0;
130 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
131 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
132 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
133 static int rtc_loaded;
135 static int i8254_cputimer_div;
137 static int i8254_nointr;
138 static int i8254_intr_disable = 0;
139 TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable);
141 static struct callout sysbeepstop_ch;
143 static sysclock_t i8254_cputimer_count(void);
144 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last);
145 static void i8254_cputimer_destruct(struct cputimer *cputimer);
147 static struct cputimer i8254_cputimer = {
148 SLIST_ENTRY_INITIALIZER,
152 i8254_cputimer_count,
153 cputimer_default_fromhz,
154 cputimer_default_fromus,
155 i8254_cputimer_construct,
156 i8254_cputimer_destruct,
161 static void i8254_intr_reload(struct cputimer_intr *, sysclock_t);
162 static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *);
163 static void i8254_intr_initclock(struct cputimer_intr *, boolean_t);
165 static struct cputimer_intr i8254_cputimer_intr = {
167 .reload = i8254_intr_reload,
168 .enable = cputimer_intr_default_enable,
169 .config = i8254_intr_config,
170 .restart = cputimer_intr_default_restart,
171 .pmfixup = cputimer_intr_default_pmfixup,
172 .initclock = i8254_intr_initclock,
173 .next = SLIST_ENTRY_INITIALIZER,
175 .type = CPUTIMER_INTR_8254,
176 .prio = CPUTIMER_INTR_PRIO_8254,
177 .caps = CPUTIMER_INTR_CAP_PS
181 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
182 * counting as of this interrupt. We use timer1 in free-running mode (not
183 * generating any interrupts) as our main counter. Each cpu has timeouts
186 * This code is INTR_MPSAFE and may be called without the BGL held.
189 clkintr(void *dummy, void *frame_arg)
191 static sysclock_t sysclock_count; /* NOTE! Must be static */
192 struct globaldata *gd = mycpu;
194 struct globaldata *gscan;
199 * SWSTROBE mode is a one-shot, the timer is no longer running
204 * XXX the dispatcher needs work. right now we call systimer_intr()
205 * directly or via IPI for any cpu with systimers queued, which is
206 * usually *ALL* of them. We need to use the LAPIC timer for this.
208 sysclock_count = sys_cputimer->count();
210 for (n = 0; n < ncpus; ++n) {
211 gscan = globaldata_find(n);
212 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL)
215 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr,
218 systimer_intr(&sysclock_count, 0, frame_arg);
222 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
223 systimer_intr(&sysclock_count, 0, frame_arg);
232 acquire_timer2(int mode)
234 if (timer2_state != RELEASED)
236 timer2_state = ACQUIRED;
239 * This access to the timer registers is as atomic as possible
240 * because it is a single instruction. We could do better if we
243 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
250 if (timer2_state != ACQUIRED)
252 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
253 timer2_state = RELEASED;
258 * This routine receives statistical clock interrupts from the RTC.
259 * As explained above, these occur at 128 interrupts per second.
260 * When profiling, we receive interrupts at a rate of 1024 Hz.
262 * This does not actually add as much overhead as it sounds, because
263 * when the statistical clock is active, the hardclock driver no longer
264 * needs to keep (inaccurate) statistics on its own. This decouples
265 * statistics gathering from scheduling interrupts.
267 * The RTC chip requires that we read status register C (RTC_INTR)
268 * to acknowledge an interrupt, before it will generate the next one.
269 * Under high interrupt load, rtcintr() can be indefinitely delayed and
270 * the clock can tick immediately after the read from RTC_INTR. In this
271 * case, the mc146818A interrupt signal will not drop for long enough
272 * to register with the 8259 PIC. If an interrupt is missed, the stat
273 * clock will halt, considerably degrading system performance. This is
274 * why we use 'while' rather than a more straightforward 'if' below.
275 * Stat clock ticks can still be lost, causing minor loss of accuracy
276 * in the statistics, but the stat clock will no longer stop.
279 rtcintr(void *dummy, void *frame)
281 while (rtcin(RTC_INTR) & RTCIR_PERIOD)
283 /* statclock(frame); no longer used */
290 DB_SHOW_COMMAND(rtc, rtc)
292 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
293 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
294 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
295 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
300 * Return the current cpu timer count as a 32 bit integer.
304 i8254_cputimer_count(void)
306 static __uint16_t cputimer_last;
311 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH);
312 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */
313 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8);
314 count = -count; /* -> countup */
315 if (count < cputimer_last) /* rollover */
316 i8254_cputimer.base += 0x00010000;
317 ret = i8254_cputimer.base | count;
318 cputimer_last = count;
324 * This function is called whenever the system timebase changes, allowing
325 * us to calculate what is needed to convert a system timebase tick
326 * into an 8254 tick for the interrupt timer. If we can convert to a
327 * simple shift, multiplication, or division, we do so. Otherwise 64
328 * bit arithmatic is required every time the interrupt timer is reloaded.
331 i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer)
337 * Will a simple divide do the trick?
339 div = (timer->freq + (cti->freq / 2)) / cti->freq;
340 freq = cti->freq * div;
342 if (freq >= timer->freq - 1 && freq <= timer->freq + 1)
343 i8254_cputimer_div = div;
345 i8254_cputimer_div = 0;
349 * Reload for the next timeout. It is possible for the reload value
350 * to be 0 or negative, indicating that an immediate timer interrupt
351 * is desired. For now make the minimum 2 ticks.
353 * We may have to convert from the system timebase to the 8254 timebase.
356 i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
360 if (i8254_cputimer_div)
361 reload /= i8254_cputimer_div;
363 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
369 if (timer0_running) {
370 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */
371 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */
372 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */
373 if (reload < count) {
374 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
375 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
376 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
381 reload = 0; /* full count */
382 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
383 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
384 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
390 * DELAY(usec) - Spin for the specified number of microseconds.
391 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds,
392 * but do a thread switch in the loop
394 * Relies on timer 1 counting down from (cputimer_freq / hz)
395 * Note: timer had better have been programmed before this is first used!
398 DODELAY(int n, int doswitch)
400 int delta, prev_tick, tick, ticks_left;
405 static int state = 0;
409 for (n1 = 1; n1 <= 10000000; n1 *= 10)
414 kprintf("DELAY(%d)...", n);
417 * Guard against the timer being uninitialized if we are called
418 * early for console i/o.
420 if (timer0_state == RELEASED)
424 * Read the counter first, so that the rest of the setup overhead is
425 * counted. Then calculate the number of hardware timer ticks
426 * required, rounding up to be sure we delay at least the requested
427 * number of microseconds.
429 prev_tick = sys_cputimer->count();
430 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) /
436 while (ticks_left > 0) {
437 tick = sys_cputimer->count();
441 delta = tick - prev_tick;
446 if (doswitch && ticks_left > 0)
452 kprintf(" %d calls to getit() at %d usec each\n",
453 getit_calls, (n + 5) / getit_calls);
458 * DELAY() never switches.
467 * DRIVERSLEEP() does not switch if called with a spinlock held or
468 * from a hard interrupt.
471 DRIVERSLEEP(int usec)
473 globaldata_t gd = mycpu;
475 if (gd->gd_intr_nesting_level || gd->gd_spinlocks_wr) {
483 sysbeepstop(void *chan)
485 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
491 sysbeep(int pitch, int period)
493 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
495 if (sysbeep_enable == 0)
498 * Nobody else is using timer2, we do not need the clock lock
500 outb(TIMER_CNTR2, pitch);
501 outb(TIMER_CNTR2, (pitch>>8));
503 /* enable counter2 output to speaker */
504 outb(IO_PPI, inb(IO_PPI) | 3);
506 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL);
512 * RTC support routines
523 val = inb(IO_RTC + 1);
530 writertc(u_char reg, u_char val)
536 outb(IO_RTC + 1, val);
537 inb(0x84); /* XXX work around wrong order in rtcin() */
544 return(bcd2bin(rtcin(port)));
548 calibrate_clocks(void)
551 u_int count, prev_count, tot_count;
552 int sec, start_sec, timeout;
555 kprintf("Calibrating clock(s) ... ");
556 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
560 /* Read the mc146818A seconds counter. */
562 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
563 sec = rtcin(RTC_SEC);
570 /* Wait for the mC146818A seconds counter to change. */
573 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
574 sec = rtcin(RTC_SEC);
575 if (sec != start_sec)
582 /* Start keeping track of the i8254 counter. */
583 prev_count = sys_cputimer->count();
589 old_tsc = 0; /* shut up gcc */
592 * Wait for the mc146818A seconds counter to change. Read the i8254
593 * counter for each iteration since this is convenient and only
594 * costs a few usec of inaccuracy. The timing of the final reads
595 * of the counters almost matches the timing of the initial reads,
596 * so the main cause of inaccuracy is the varying latency from
597 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
598 * rtcin(RTC_SEC) that returns a changed seconds count. The
599 * maximum inaccuracy from this cause is < 10 usec on 486's.
603 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
604 sec = rtcin(RTC_SEC);
605 count = sys_cputimer->count();
606 tot_count += (int)(count - prev_count);
608 if (sec != start_sec)
615 * Read the cpu cycle counter. The timing considerations are
616 * similar to those for the i8254 clock.
619 tsc_frequency = rdtsc() - old_tsc;
623 kprintf("TSC clock: %llu Hz, ", (long long)tsc_frequency);
624 kprintf("i8254 clock: %u Hz\n", tot_count);
628 kprintf("failed, using default i8254 clock of %u Hz\n",
629 i8254_cputimer.freq);
630 return (i8254_cputimer.freq);
636 timer0_state = ACQUIRED;
641 * Timer0 is our fine-grained variable clock interrupt
643 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
644 outb(TIMER_CNTR0, 2); /* lsb */
645 outb(TIMER_CNTR0, 0); /* msb */
649 cputimer_intr_register(&i8254_cputimer_intr);
650 cputimer_intr_select(&i8254_cputimer_intr, 0);
654 * Timer1 or timer2 is our free-running clock, but only if another
655 * has not been selected.
657 cputimer_register(&i8254_cputimer);
658 cputimer_select(&i8254_cputimer, 0);
662 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
667 * Should we use timer 1 or timer 2 ?
670 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which);
671 if (which != 1 && which != 2)
676 timer->name = "i8254_timer1";
677 timer->type = CPUTIMER_8254_SEL1;
678 i8254_walltimer_sel = TIMER_SEL1;
679 i8254_walltimer_cntr = TIMER_CNTR1;
680 timer1_state = ACQUIRED;
683 timer->name = "i8254_timer2";
684 timer->type = CPUTIMER_8254_SEL2;
685 i8254_walltimer_sel = TIMER_SEL2;
686 i8254_walltimer_cntr = TIMER_CNTR2;
687 timer2_state = ACQUIRED;
691 timer->base = (oldclock + 0xFFFF) & ~0xFFFF;
694 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT);
695 outb(i8254_walltimer_cntr, 0); /* lsb */
696 outb(i8254_walltimer_cntr, 0); /* msb */
697 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */
702 i8254_cputimer_destruct(struct cputimer *timer)
704 switch(timer->type) {
705 case CPUTIMER_8254_SEL1:
706 timer1_state = RELEASED;
708 case CPUTIMER_8254_SEL2:
709 timer2_state = RELEASED;
720 /* Restore all of the RTC's "status" (actually, control) registers. */
721 writertc(RTC_STATUSB, RTCSB_24HR);
722 writertc(RTC_STATUSA, rtc_statusa);
723 writertc(RTC_STATUSB, rtc_statusb);
727 * Restore all the timers.
729 * This function is called to resynchronize our core timekeeping after a
730 * long halt, e.g. from apm_default_resume() and friends. It is also
731 * called if after a BIOS call we have detected munging of the 8254.
732 * It is necessary because cputimer_count() counter's delta may have grown
733 * too large for nanouptime() and friends to handle, or (in the case of 8254
734 * munging) might cause the SYSTIMER code to prematurely trigger.
740 i8254_restore(); /* restore timer_freq and hz */
741 rtc_restore(); /* reenable RTC interrupts */
746 * Initialize 8254 timer 0 early so that it can be used in DELAY().
754 * Can we use the TSC?
756 if (cpu_feature & CPUID_TSC)
762 * Initial RTC state, don't do anything unexpected
764 writertc(RTC_STATUSA, rtc_statusa);
765 writertc(RTC_STATUSB, RTCSB_24HR);
768 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
769 * generate an interrupt, which we will ignore for now.
771 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
772 * (so it counts a full 2^16 and repeats). We will use this timer
776 freq = calibrate_clocks();
777 #ifdef CLK_CALIBRATION_LOOP
780 "Press a key on the console to abort clock calibration\n");
781 while (cncheckc() == -1)
787 * Use the calibrated i8254 frequency if it seems reasonable.
788 * Otherwise use the default, and don't use the calibrated i586
791 delta = freq > i8254_cputimer.freq ?
792 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq;
793 if (delta < i8254_cputimer.freq / 100) {
794 #ifndef CLK_USE_I8254_CALIBRATION
797 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
798 freq = i8254_cputimer.freq;
802 * Interrupt timer's freq must be adjusted
803 * before we change the cuptimer's frequency.
805 i8254_cputimer_intr.freq = freq;
806 cputimer_set_frequency(&i8254_cputimer, freq);
810 "%d Hz differs from default of %d Hz by more than 1%%\n",
811 freq, i8254_cputimer.freq);
815 #ifndef CLK_USE_TSC_CALIBRATION
816 if (tsc_frequency != 0) {
819 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
823 if (tsc_present && tsc_frequency == 0) {
825 * Calibration of the i586 clock relative to the mc146818A
826 * clock failed. Do a less accurate calibration relative
827 * to the i8254 clock.
829 u_int64_t old_tsc = rdtsc();
832 tsc_frequency = rdtsc() - old_tsc;
833 #ifdef CLK_USE_TSC_CALIBRATION
835 kprintf("TSC clock: %llu Hz (Method B)\n",
841 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST);
845 * We can not use the TSC in SMP mode, until we figure out a
846 * cheap (impossible), reliable and precise (yeah right!) way
847 * to synchronize the TSCs of all the CPUs.
848 * Curse Intel for leaving the counter out of the I/O APIC.
853 * We can not use the TSC if we support APM. Precise timekeeping
854 * on an APM'ed machine is at best a fools pursuit, since
855 * any and all of the time spent in various SMM code can't
856 * be reliably accounted for. Reading the RTC is your only
857 * source of reliable time info. The i8254 looses too of course
858 * but we need to have some kind of time...
859 * We don't know at this point whether APM is going to be used
860 * or not, nor when it might be activated. Play it safe.
863 #endif /* NAPM > 0 */
865 #endif /* !defined(SMP) */
869 * Sync the time of day back to the RTC on shutdown, but only if
870 * we have already loaded it and have not crashed.
873 resettodr_on_shutdown(void *arg __unused)
875 if (rtc_loaded && panicstr == NULL) {
881 * Initialize the time of day register, based on the time base which is, e.g.
885 inittodr(time_t base)
887 unsigned long sec, days;
898 /* Look if we have a RTC present and the time is valid */
899 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
902 /* wait for time update to complete */
903 /* If RTCSA_TUP is zero, we have at least 244us before next update */
905 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
911 #ifdef USE_RTC_CENTURY
912 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
914 year = readrtc(RTC_YEAR) + 1900;
922 month = readrtc(RTC_MONTH);
923 for (m = 1; m < month; m++)
924 days += daysinmonth[m-1];
925 if ((month > 2) && LEAPYEAR(year))
927 days += readrtc(RTC_DAY) - 1;
928 for (y = 1970; y < year; y++)
929 days += DAYSPERYEAR + LEAPYEAR(y);
930 sec = ((( days * 24 +
931 readrtc(RTC_HRS)) * 60 +
932 readrtc(RTC_MIN)) * 60 +
934 /* sec now contains the number of seconds, since Jan 1 1970,
935 in the local time zone */
937 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
939 y = time_second - sec;
940 if (y <= -2 || y >= 2) {
941 /* badly off, adjust it */
951 kprintf("Invalid time in real time clock.\n");
952 kprintf("Check and reset the date immediately!\n");
956 * Write system time back to RTC
973 /* Disable RTC updates and interrupts. */
974 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
976 /* Calculate local time to put in RTC */
978 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
980 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
981 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
982 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
984 /* We have now the days since 01-01-1970 in tm */
985 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
986 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
988 y++, m = DAYSPERYEAR + LEAPYEAR(y))
991 /* Now we have the years in y and the day-of-the-year in tm */
992 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
993 #ifdef USE_RTC_CENTURY
994 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
1000 if (m == 1 && LEAPYEAR(y))
1007 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
1008 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
1010 /* Reenable RTC updates and interrupts. */
1011 writertc(RTC_STATUSB, rtc_statusb);
1017 * Start both clocks running. DragonFly note: the stat clock is no longer
1018 * used. Instead, 8254 based systimers are used for all major clock
1019 * interrupts. statclock_disable is set by default.
1022 i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected)
1026 int apic_8254_trial;
1028 #endif /* APIC_IO */
1030 callout_init(&sysbeepstop_ch);
1032 if (!selected && i8254_intr_disable) {
1033 i8254_nointr = 1; /* don't try to register again */
1034 cputimer_intr_deregister(cti);
1038 if (statclock_disable) {
1040 * The stat interrupt mask is different without the
1041 * statistics clock. Also, don't set the interrupt
1042 * flag which would normally cause the RTC to generate
1045 rtc_statusb = RTCSB_24HR;
1047 /* Setting stathz to nonzero early helps avoid races. */
1048 stathz = RTC_NOPROFRATE;
1049 profhz = RTC_PROFRATE;
1052 /* Finish initializing 8253 timer 0. */
1055 apic_8254_intr = isa_apic_irq(0);
1056 apic_8254_trial = 0;
1057 if (apic_8254_intr >= 0 ) {
1058 if (apic_int_type(0, 0) == 3)
1059 apic_8254_trial = 1;
1061 /* look for ExtInt on pin 0 */
1062 if (apic_int_type(0, 0) == 3) {
1063 apic_8254_intr = apic_irq(0, 0);
1064 setup_8254_mixed_mode();
1066 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
1069 clkdesc = register_int(apic_8254_intr, clkintr, NULL, "clk",
1071 INTR_EXCL | INTR_CLOCK |
1072 INTR_NOPOLL | INTR_MPSAFE |
1074 machintr_intren(apic_8254_intr);
1078 register_int(0, clkintr, NULL, "clk", NULL,
1079 INTR_EXCL | INTR_CLOCK |
1080 INTR_NOPOLL | INTR_MPSAFE |
1082 machintr_intren(ICU_IRQ0);
1084 #endif /* APIC_IO */
1086 /* Initialize RTC. */
1087 writertc(RTC_STATUSA, rtc_statusa);
1088 writertc(RTC_STATUSB, RTCSB_24HR);
1090 if (statclock_disable == 0) {
1091 diag = rtcin(RTC_DIAG);
1093 kprintf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
1096 if (isa_apic_irq(8) != 8)
1097 panic("APIC RTC != 8");
1098 #endif /* APIC_IO */
1100 register_int(8, (inthand2_t *)rtcintr, NULL, "rtc", NULL,
1101 INTR_EXCL | INTR_CLOCK | INTR_NOPOLL |
1105 writertc(RTC_STATUSB, rtc_statusb);
1109 if (apic_8254_trial) {
1114 * Following code assumes the 8254 is the cpu timer,
1115 * so make sure it is.
1117 KKASSERT(sys_cputimer == &i8254_cputimer);
1118 KKASSERT(cti == &i8254_cputimer_intr);
1120 lastcnt = get_interrupt_counter(apic_8254_intr);
1123 * Force an 8254 Timer0 interrupt and wait 1/100s for
1124 * it to happen, then see if we got it.
1126 kprintf("APIC_IO: Testing 8254 interrupt delivery\n");
1127 i8254_intr_reload(cti, 2);
1128 base = sys_cputimer->count();
1129 while (sys_cputimer->count() - base < sys_cputimer->freq / 100)
1131 if (get_interrupt_counter(apic_8254_intr) - lastcnt == 0) {
1133 * The MP table is broken.
1134 * The 8254 was not connected to the specified pin
1136 * Workaround: Limited variant of mixed mode.
1138 machintr_intrdis(apic_8254_intr);
1139 unregister_int(clkdesc);
1140 kprintf("APIC_IO: Broken MP table detected: "
1141 "8254 is not connected to "
1142 "IOAPIC #%d intpin %d\n",
1143 int_to_apicintpin[apic_8254_intr].ioapic,
1144 int_to_apicintpin[apic_8254_intr].int_pin);
1146 * Revoke current ISA IRQ 0 assignment and
1147 * configure a fallback interrupt routing from
1148 * the 8254 Timer via the 8259 PIC to the
1149 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1150 * We reuse the low level interrupt handler number.
1152 if (apic_irq(0, 0) < 0) {
1153 revoke_apic_irq(apic_8254_intr);
1154 assign_apic_irq(0, 0, apic_8254_intr);
1156 apic_8254_intr = apic_irq(0, 0);
1157 setup_8254_mixed_mode();
1158 register_int(apic_8254_intr, clkintr, NULL, "clk",
1160 INTR_EXCL | INTR_CLOCK |
1161 INTR_NOPOLL | INTR_MPSAFE |
1163 machintr_intren(apic_8254_intr);
1166 if (apic_int_type(0, 0) != 3 ||
1167 int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
1168 int_to_apicintpin[apic_8254_intr].int_pin != 0) {
1169 kprintf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1170 int_to_apicintpin[apic_8254_intr].ioapic,
1171 int_to_apicintpin[apic_8254_intr].int_pin);
1174 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1182 setup_8254_mixed_mode(void)
1185 * Allow 8254 timer to INTerrupt 8259:
1186 * re-initialize master 8259:
1187 * reset; prog 4 bytes, single ICU, edge triggered
1189 outb(IO_ICU1, 0x13);
1190 outb(IO_ICU1 + 1, IDT_OFFSET); /* start vector (unused) */
1191 outb(IO_ICU1 + 1, 0x00); /* ignore slave */
1192 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
1193 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
1195 /* program IO APIC for type 3 INT on INT0 */
1196 if (ext_int_setup(0, 0) < 0)
1197 panic("8254 redirect via APIC pin0 impossible!");
1202 setstatclockrate(int newhz)
1204 if (newhz == RTC_PROFRATE)
1205 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1207 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1208 writertc(RTC_STATUSA, rtc_statusa);
1213 tsc_get_timecount(struct timecounter *tc)
1219 #ifdef KERN_TIMESTAMP
1220 #define KERN_TIMESTAMP_SIZE 16384
1221 static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1222 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1223 sizeof(tsc), "LU", "Kernel timestamps");
1229 tsc[i] = (u_int32_t)rdtsc();
1232 if (i >= KERN_TIMESTAMP_SIZE)
1234 tsc[i] = 0; /* mark last entry */
1236 #endif /* KERN_TIMESTAMP */
1243 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1250 if (sys_cputimer == &i8254_cputimer)
1251 count = sys_cputimer->count();
1259 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
1260 return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1263 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
1264 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0,
1266 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
1267 0, 0, hw_i8254_timestamp, "A", "");
1269 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD,
1270 &tsc_present, 0, "TSC Available");
1271 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD,
1272 &tsc_frequency, 0, "TSC Frequency");