sys/net/i4b/layer1/itjc/i4b_itjc_pci.c

   1 /*
   2  *   Copyright (c) 2000, 2001 Sergio Prallon. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  *
  31  *---------------------------------------------------------------------------
  32  *
  33  *      i4b_itjc_pci.c: NetJet-S hardware driver
  34  *      ----------------------------------------
  35  *
  36  * $FreeBSD: src/sys/i4b/layer1/itjc/i4b_itjc_pci.c,v 1.1.2.1 2001/08/10 14:08:39 obrien Exp $
  37  *
  38  *      last edit-date: [Thu Jan 11 11:29:38 2001]
  39  *
  40  *---------------------------------------------------------------------------*/
  41
  42 #include "use_itjc.h"
  43 #include "opt_i4b.h"
  44
  45 #if (NITJC > 0)
  46
  47 #include <sys/param.h>
  48 #include <sys/kernel.h>
  49 #include <sys/systm.h>
  50 #include <sys/mbuf.h>
  51 #include <sys/bus.h>
  52 #include <sys/rman.h>
  53 #include <sys/socket.h>
  54 #include <sys/thread2.h>
  55
  56 #include <machine/clock.h>
  57
  58 #include <bus/pci/pcireg.h>
  59 #include <bus/pci/pcivar.h>
  60
  61 #include <net/if.h>
  62 #include <net/i4b/include/machine/i4b_debug.h>
  63 #include <net/i4b/include/machine/i4b_ioctl.h>
  64 #include <net/i4b/include/machine/i4b_trace.h>
  65
  66 #include "../../include/i4b_global.h"
  67 #include "../../include/i4b_mbuf.h"
  68
  69 #include "../i4b_l1.h"
  70
  71 #include "i4b_hdlc.h"   /* XXXXXXXXXXXXXXXXXXXXXXXX */
  72
  73 #include "../isic/i4b_isic.h"
  74 #include "../isic/i4b_isac.h"
  75
  76 #include "i4b_itjc_ext.h"
  77
  78 #define PCI_TJNET_VID (0xe159)
  79 #define PCI_TJ300_DID (0x0001)
  80
  81
  82 /*
  83  * Function prototypes
  84  */
  85
  86 static int  itjc_probe(device_t dev);
  87 static int  itjc_attach(device_t dev);
  88 static void itjc_shutdown(device_t dev);
  89 static void itjc_intr(void *xsc);
  90 static int  itjc_dma_start(struct l1_softc *sc);
  91 static void itjc_dma_stop(struct l1_softc *sc);
  92 static void itjc_isac_intr(struct l1_softc *sc);
  93 static void itjc_init_linktab(struct l1_softc *sc);
  94 static void itjc_bchannel_setup(int unit, int h_chan, int bprot,
  95         int activate);
  96 static void itjc_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp);
  97
  98
  99 /*
 100  * Shorter names to bus resource manager routines.
 101  */
 102
 103 #define itjc_bus_setup(sc)                                              \
 104         bus_space_handle_t h =                                          \
 105                 rman_get_bushandle((sc)->sc_resources.io_base[0]);      \
 106         bus_space_tag_t    t =                                          \
 107                 rman_get_bustag((sc)->sc_resources.io_base[0]);
 108
 109 #define itjc_read_1(port)       (bus_space_read_1(t, h, (port)))
 110 #define itjc_read_4(port)       (bus_space_read_4(t, h, (port)))
 111 #define itjc_write_1(port, data) (bus_space_write_1(t, h, (port), (data)))
 112 #define itjc_write_4(port, data) (bus_space_write_4(t, h, (port), (data)))
 113 #define itjc_read_multi_1(port, buf, size)                              \
 114         (bus_space_read_multi_1(t, h, (port), (buf), (size)))
 115 #define itjc_write_multi_1(port, buf, size)                             \
 116         (bus_space_write_multi_1(t, h, (port), (buf), (size)))
 117
 118
 119 /*---------------------------------------------------------------------------*
 120  *      Glue data to register ourselves as a PCI device driver.
 121  *---------------------------------------------------------------------------*/
 122
 123 static device_method_t itjc_pci_methods[] =
 124 {
 125         /* Device interface */
 126         DEVMETHOD(device_probe,         itjc_probe),
 127         DEVMETHOD(device_attach,        itjc_attach),
 128         DEVMETHOD(device_shutdown,      itjc_shutdown),
 129
 130         /* bus interface */
 131         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 132         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 133
 134         { 0, 0 }
 135 };
 136
 137 static driver_t itjc_pci_driver =
 138 {
 139         "itjc",
 140         itjc_pci_methods,
 141         sizeof(struct l1_softc)
 142 };
 143
 144 static devclass_t itjc_pci_devclass;
 145
 146 DRIVER_MODULE(netjet, pci, itjc_pci_driver, itjc_pci_devclass, 0, 0);
 147
 148 /*
 149  * Jump table for multiplex routines.
 150  */
 151
 152 struct i4b_l1mux_func itjc_l1mux_func =
 153 {
 154         itjc_ret_linktab,
 155         itjc_set_linktab,
 156         itjc_mph_command_req,
 157         itjc_ph_data_req,
 158         itjc_ph_activate_req,
 159 };
 160
 161 struct l1_softc *itjc_scp[ITJC_MAXUNIT];
 162
 163
 164 /*---------------------------------------------------------------------------*
 165  *      Tiger300/320 PCI ASIC registers.
 166  *---------------------------------------------------------------------------*/
 167
 168 /*
 169  *      Register offsets from i/o base.
 170  */
 171 enum tiger_regs
 172 {
 173         TIGER_RESET_PIB_CL_TIME = 0x00,
 174         TIGER_DMA_OPER          = 0x01,
 175         TIGER_AUX_PORT_CNTL     = 0x02,
 176         TIGER_AUX_PORT_DATA     = 0x03,
 177         TIGER_INT0_MASK         = 0x04,
 178         TIGER_INT1_MASK         = 0x05,
 179         TIGER_INT0_STATUS       = 0x06,
 180         TIGER_INT1_STATUS       = 0x07,
 181         TIGER_DMA_WR_START_ADDR = 0x08,
 182         TIGER_DMA_WR_INT_ADDR   = 0x0C,
 183         TIGER_DMA_WR_END_ADDR   = 0x10,
 184         TIGER_DMA_WR_CURR_ADDR  = 0x14,
 185         TIGER_DMA_RD_START_ADDR = 0x18,
 186         TIGER_DMA_RD_INT_ADDR   = 0x1C,
 187         TIGER_DMA_RD_END_ADDR   = 0x20,
 188         TIGER_DMA_RD_CURR_ADDR  = 0x24,
 189         TIGER_PULSE_COUNTER     = 0x28,
 190 };
 191
 192 /*
 193  * Bits on the above registers.
 194  */
 195
 196 enum tiger_reg_bits
 197 {
 198 /* Reset and PIB Cycle Timing */
 199
 200         TIGER_DMA_OP_MODE_MASK          = 0x80,
 201                 TIGER_SELF_ADDR_DMA     = 0x00, /* Wrap around ending addr */
 202                 TIGER_NORMAL_DMA        = 0x80, /* Stop at ending addr */
 203
 204         TIGER_DMA_INT_MODE_MASK         = 0x40,
 205                 TIGER_DONT_LATCH_DMA_INT= 0x00, /* Bits on int0 status will be
 206                                                    set only while curr addr
 207                                                    equals int or end addr */
 208                 TIGER_LATCH_DMA_INT     = 0x40, /* Bits on int0 status remain
 209                                                    set until cleared by CPU */
 210
 211         TIGER_PIB_CYCLE_TIMING_MASK     = 0x30,
 212                 TIGER_PIB_3_CYCLES      = 0x00,
 213                 TIGER_PIB_5_CYCLES      = 0x01,
 214                 TIGER_PIB_12_CYCLES     = 0x10,
 215
 216         TIGER_RESET_MASK                = 0x0F,
 217                 TIGER_RESET_PULSE_COUNT = 0x08,
 218                 TIGER_RESET_SERIAL_PORT = 0x04,
 219                 TIGER_RESET_DMA_LOGIC   = 0x02,
 220                 TIGER_RESET_EXTERNAL    = 0x01,
 221                 TIGER_RESET_ALL         = 0x0F,
 222
 223 /* DMA Operation */
 224         TIGER_DMA_RESTART_MASK          = 0x02,
 225                 TIGER_HOLD_DMA          = 0x00,
 226                 TIGER_RESTART_DMA       = 0x00,
 227
 228         TIGER_DMA_ENABLE_MASK           = 0x01,
 229                 TIGER_ENABLE_DMA        = 0x01,
 230                 TIGER_DISABLE_DMA       = 0x00,
 231
 232 /* AUX Port Control & Data plus Interrupt 1 Mask & Status  */
 233         TIGER_AUX_7_MASK                = 0x80,
 234         TIGER_AUX_6_MASK                = 0x40,
 235         TIGER_AUX_5_MASK                = 0x20,
 236         TIGER_AUX_4_MASK                = 0x10,
 237         TIGER_ISAC_INT_MASK             = 0x10,
 238         TIGER_AUX_3_MASK                = 0x08,
 239         TIGER_AUX_2_MASK                = 0x04,
 240         TIGER_AUX_1_MASK                = 0x02,
 241         TIGER_AUX_0_MASK                = 0x01,
 242
 243 /* AUX Port Control */
 244                 TIGER_AUX_7_IS_INPUT    = 0x00,
 245                 TIGER_AUX_7_IS_OUTPUT   = 0x80,
 246                 TIGER_AUX_6_IS_INPUT    = 0x00,
 247                 TIGER_AUX_6_IS_OUTPUT   = 0x40,
 248                 TIGER_AUX_5_IS_INPUT    = 0x00,
 249                 TIGER_AUX_5_IS_OUTPUT   = 0x20,
 250                 TIGER_AUX_4_IS_INPUT    = 0x00,
 251                 TIGER_AUX_4_IS_OUTPUT   = 0x10,
 252                 TIGER_AUX_3_IS_INPUT    = 0x00,
 253                 TIGER_AUX_3_IS_OUTPUT   = 0x80,
 254                 TIGER_AUX_2_IS_INPUT    = 0x00,
 255                 TIGER_AUX_2_IS_OUTPUT   = 0x40,
 256                 TIGER_AUX_1_IS_INPUT    = 0x00,
 257                 TIGER_AUX_1_IS_OUTPUT   = 0x20,
 258                 TIGER_AUX_0_IS_INPUT    = 0x00,
 259                 TIGER_AUX_0_IS_OUTPUT   = 0x10,
 260                 TIGER_AUX_NJ_DEFAULT    = 0xEF, /* All but ISAC int is output */
 261
 262 /* Interrupt 0 Mask & Status */
 263         TIGER_PCI_TARGET_ABORT_INT_MASK = 0x20,
 264                 TIGER_NO_TGT_ABORT_INT  = 0x00,
 265                 TIGER_TARGET_ABORT_INT  = 0x20,
 266         TIGER_PCI_MASTER_ABORT_INT_MASK = 0x10,
 267                 TIGER_NO_MST_ABORT_INT  = 0x00,
 268                 TIGER_MASTER_ABORT_INT  = 0x10,
 269         TIGER_DMA_RD_END_INT_MASK       = 0x08,
 270                 TIGER_NO_RD_END_INT     = 0x00,
 271                 TIGER_RD_END_INT        = 0x08,
 272         TIGER_DMA_RD_INT_INT_MASK       = 0x04,
 273                 TIGER_NO_RD_INT_INT     = 0x00,
 274                 TIGER_RD_INT_INT        = 0x04,
 275         TIGER_DMA_WR_END_INT_MASK       = 0x02,
 276                 TIGER_NO_WR_END_INT     = 0x00,
 277                 TIGER_WR_END_INT        = 0x02,
 278         TIGER_DMA_WR_INT_INT_MASK       = 0x01,
 279                 TIGER_NO_WR_INT_INT     = 0x00,
 280                 TIGER_WR_INT_INT        = 0x01,
 281
 282 /* Interrupt 1 Mask & Status */
 283                 TIGER_NO_AUX_7_INT      = 0x00,
 284                 TIGER_AUX_7_INT         = 0x80,
 285                 TIGER_NO_AUX_6_INT      = 0x00,
 286                 TIGER_AUX_6_INT         = 0x40,
 287                 TIGER_NO_AUX_5_INT      = 0x00,
 288                 TIGER_AUX_5_INT         = 0x20,
 289                 TIGER_NO_AUX_4_INT      = 0x00,
 290                 TIGER_AUX_4_INT         = 0x10,
 291                 TIGER_NO_ISAC_INT       = 0x00,
 292                 TIGER_ISAC_INT          = 0x10,
 293                 TIGER_NO_AUX_3_INT      = 0x00,
 294                 TIGER_AUX_3_INT         = 0x08,
 295                 TIGER_NO_AUX_2_INT      = 0x00,
 296                 TIGER_AUX_2_INT         = 0x04,
 297                 TIGER_NO_AUX_1_INT      = 0x00,
 298                 TIGER_AUX_1_INT         = 0x02,
 299                 TIGER_NO_AUX_0_INT      = 0x00,
 300                 TIGER_AUX_0_INT         = 0x01
 301 };
 302
 303 /*
 304  * Peripheral Interface Bus definitions. This is an ISA like bus
 305  * created by the Tiger ASIC to keep ISA chips like the ISAC happy
 306  * on a PCI environment.
 307  *
 308  * Since the PIB only supplies 4 addressing lines, the 2 higher bits
 309  * (A4 & A5) of the ISAC register addresses are wired on the 2 lower
 310  * AUX lines. Another restriction is that all I/O to the PIB (8bit
 311  * wide) is mapped on the PCI side as 32bit data. So the PCI address
 312  * of a given ISAC register has to be multiplied by 4 before being
 313  * added to the PIB base offset.
 314  */
 315 enum tiger_pib_regs_defs
 316 {
 317         /* Offset from the I/O base to the ISAC registers. */
 318         PIB_OFFSET              = 0xC0,
 319         PIB_LO_ADDR_MASK        = 0x0F,
 320         PIB_HI_ADDR_MASK        = 0x30,
 321         PIB_LO_ADDR_SHIFT       = 2,    /* Align on dword boundary */
 322         PIB_HI_ADDR_SHIFT       = 4     /* Right shift to AUX_1 & AUX_0 */
 323 };
 324
 325
 326 #define itjc_set_pib_addr_msb(a)                                        \
 327 (                                                                       \
 328         itjc_write_1(TIGER_AUX_PORT_DATA,                               \
 329                 ((a) & PIB_HI_ADDR_MASK) >> PIB_HI_ADDR_SHIFT)          \
 330 )
 331
 332 #define itjc_pib_2_pci(a)                                               \
 333 (                                                                       \
 334         (((a) & PIB_LO_ADDR_MASK) << PIB_LO_ADDR_SHIFT) + PIB_OFFSET    \
 335 )
 336
 337 #define itjc_get_dma_offset(ctx,reg)                                    \
 338 (                                                                       \
 339         (u_int16_t)((bus_addr_t)itjc_read_4((reg)) - (ctx)->bus_addr)   \
 340 )
 341
 342
 343 /*
 344  * IOM-2 serial channel 0 DMA data ring buffers.
 345  *
 346  * The Tiger300/320 ASIC do not nothing more than transfer via DMA the
 347  * first 32 bits of every IOM-2 frame on the serial interface to the
 348  * ISAC. So we have no framing/deframing facilities like we would have
 349  * with an HSCX, having to do the job with CPU cycles. On the plus side
 350  * we are able to specify large rings which can limit the occurrence of
 351  * over/underruns.
 352  */
 353
 354 enum
 355 {
 356         ITJC_RING_SLOT_WORDS    = 64,
 357         ITJC_RING_WORDS         = 3 * ITJC_RING_SLOT_WORDS,
 358         ITJC_RING_SLOT_BYTES    = 4 * ITJC_RING_SLOT_WORDS,
 359         ITJC_RING_BYTES         = 4 * ITJC_RING_WORDS,
 360         ITJC_DMA_POOL_WORDS     = 2 * ITJC_RING_WORDS,
 361         ITJC_DMA_POOL_BYTES     = 4 * ITJC_DMA_POOL_WORDS
 362 };
 363
 364 #define itjc_ring_add(x, d)     (((x) + 4 * (d)) % ITJC_RING_BYTES)
 365 #define itjc_ring_sub(x, d)     (((x) + ITJC_RING_BYTES - 4 * (d))      \
 366                                         % ITJC_RING_BYTES)
 367
 368
 369 enum
 370 {
 371         TIGER_CH_A              = 0,
 372         TIGER_CH_B              = 1,
 373
 374         HSCX_CH_A               = 0,    /* For compatibility reasons. */
 375         HSCX_CH_B               = 1,
 376 };
 377
 378 enum
 379 {
 380         ITJC_TEL_SILENCE_BYTE   = 0x00,
 381         ITJC_HDLC_FLAG_BYTE     = 0x7E,
 382         ITJC_HDLC_ABORT_BYTE    = 0xFF
 383 };
 384
 385 /*
 386  * Hardware DMA control block (one per card).
 387  */
 388 typedef enum
 389 {
 390         ITJC_DS_LOAD_FAILED     = -1,
 391         ITJC_DS_FREE            =  0,
 392         ITJC_DS_LOADING,
 393         ITJC_DS_STOPPED,
 394         ITJC_DS_RUNNING
 395 }
 396         dma_state_t;
 397
 398 typedef struct
 399 {
 400         dma_state_t     state;
 401         u_int8_t        *pool;
 402         bus_addr_t      bus_addr;
 403         bus_dma_tag_t   tag;
 404         bus_dmamap_t    map;
 405         int             error;
 406 }
 407         dma_context_t;
 408
 409 dma_context_t
 410         dma_context     [ ITJC_MAXUNIT ];
 411
 412 /*
 413  * B-channel DMA control blocks (4 per card -- 1 RX & 1 TX per channel).
 414  */
 415 typedef enum
 416 {
 417         ITJC_RS_IDLE    = 0,
 418         ITJC_RS_ACTIVE
 419 }
 420         dma_rx_state_t;
 421
 422 typedef enum
 423 {
 424         ITJC_TS_IDLE    = 0,
 425         ITJC_TS_ACTIVE,
 426         ITJC_TS_AFTER_XDU
 427 }
 428         dma_tx_state_t;
 429
 430 typedef struct
 431 {
 432         u_int8_t        *ring;
 433         bus_addr_t      bus_addr;
 434         u_int16_t       next_read;
 435         u_int16_t       hdlc_len;
 436         u_int16_t       hdlc_tmp;
 437         u_int16_t       hdlc_crc;
 438         u_int16_t       hdlc_ib;
 439         u_int8_t        hdlc_blevel;
 440         u_int8_t        hdlc_flag;
 441         dma_rx_state_t  state;
 442 }
 443         dma_rx_context_t;
 444
 445 typedef struct
 446 {
 447         u_int8_t        *ring;
 448         bus_addr_t      bus_addr;
 449         u_int16_t       next_write;
 450         u_int32_t       hdlc_tmp;
 451         u_int16_t       hdlc_blevel;
 452         u_int16_t       hdlc_crc;
 453         u_int16_t       hdlc_ib;
 454         u_int16_t       next_frame;
 455         u_int16_t       filled;
 456         u_int8_t        hdlc_flag;
 457         dma_tx_state_t  state;
 458 }
 459         dma_tx_context_t;
 460
 461 dma_rx_context_t
 462         dma_rx_context  [ ITJC_MAXUNIT ] [ 2 ];
 463
 464 dma_tx_context_t
 465         dma_tx_context  [ ITJC_MAXUNIT ] [ 2 ];
 466
 467 /*
 468  * Used by the mbuf handling functions.
 469  */
 470 typedef enum
 471 {
 472         ITJC_MB_CURR = 0,
 473         ITJC_MB_NEXT = 1,
 474         ITJC_MB_NEW  = 2
 475 }
 476         which_mb_t;
 477
 478
 479 /*---------------------------------------------------------------------------*
 480  *      itjc_map_callback - get DMA bus address from resource mgr.
 481  *---------------------------------------------------------------------------*/
 482 static void
 483 itjc_map_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 484 {
 485         dma_context_t           *ctx = (dma_context_t *)arg;
 486
 487         if (error)
 488         {
 489                 ctx->error = error;
 490                 ctx->state = ITJC_DS_LOAD_FAILED;
 491                 return;
 492         }
 493
 494         ctx->bus_addr = segs->ds_addr;
 495         ctx->state = ITJC_DS_STOPPED;
 496 }
 497
 498
 499 /*---------------------------------------------------------------------------*
 500  *      itjc_dma_start - Complete DMA setup & start the Tiger DMA engine.
 501  *---------------------------------------------------------------------------*/
 502 static int
 503 itjc_dma_start(struct l1_softc *sc)
 504 {
 505         int                     unit    = sc->sc_unit;
 506         dma_context_t           *ctx    = &dma_context[unit];
 507         dma_rx_context_t        *rxc    = &dma_rx_context[unit][0];
 508         dma_tx_context_t        *txc    = &dma_tx_context[unit][0];
 509         bus_addr_t              ba;
 510         u_int8_t                i;
 511         u_int32_t               *pool_end,
 512                                 *ip;
 513
 514         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
 515         bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
 516
 517         /* See if it is already running. */
 518
 519         if (ctx->state == ITJC_DS_RUNNING)
 520                 return 0;
 521
 522         if (ctx->state == ITJC_DS_LOAD_FAILED)
 523         {
 524                 NDBGL1(L1_ERROR, "itjc%d: dma_start: DMA map loading "
 525                         "failed (error=%d).\n", unit, ctx->error);
 526                 return 1;
 527         }
 528
 529         if (ctx->state != ITJC_DS_STOPPED)
 530         {
 531                 NDBGL1(L1_ERROR, "itjc%d: dma_start: Unexpected DMA "
 532                         "state (%d).\n", unit, ctx->state);
 533                 return 1;
 534         }
 535
 536         /*
 537          * Initialize the DMA control structures (hardware & B-channel).
 538          */
 539         ba = ctx->bus_addr;
 540
 541         txc->ring = ctx->pool + TIGER_CH_A;
 542         rxc->ring = ctx->pool + TIGER_CH_A + ITJC_RING_BYTES;
 543
 544         txc->bus_addr = ba;
 545         rxc->bus_addr = ba + ITJC_RING_BYTES;
 546
 547         ++rxc; ++txc;
 548
 549         txc->ring = ctx->pool + TIGER_CH_B;
 550         rxc->ring = ctx->pool + TIGER_CH_B + ITJC_RING_BYTES;
 551
 552         txc->bus_addr = ba;
 553         rxc->bus_addr = ba + ITJC_RING_BYTES;
 554
 555         /*
 556          * Fill the DMA ring buffers with IOM-2 channel 0 frames made of
 557          * idle/abort sequences for the B & D channels and NOP for IOM-2
 558          * cmd/ind, monitor handshake & data.
 559          */
 560         pool_end = (u_int32_t *)ctx->pool + ITJC_DMA_POOL_WORDS;
 561         for (ip = (u_int32_t *)ctx->pool; ip < pool_end; ++ip)
 562                 *ip = 0xFFFFFFFF;
 563
 564         /*
 565          * Program the Tiger DMA gears.
 566          */
 567
 568         itjc_write_4(TIGER_DMA_WR_START_ADDR, ba);
 569         itjc_write_4(TIGER_DMA_WR_INT_ADDR, ba + ITJC_RING_SLOT_BYTES - 4);
 570         itjc_write_4(TIGER_DMA_WR_END_ADDR, ba + ITJC_RING_BYTES - 4);
 571
 572         ba += ITJC_RING_BYTES;
 573
 574         itjc_write_4(TIGER_DMA_RD_START_ADDR, ba);
 575         itjc_write_4(TIGER_DMA_RD_INT_ADDR, ba + ITJC_RING_SLOT_BYTES * 2 - 4);
 576         itjc_write_4(TIGER_DMA_RD_END_ADDR, ba + ITJC_RING_BYTES - 4);
 577
 578         itjc_write_1(TIGER_INT0_MASK,
 579                 TIGER_WR_END_INT | TIGER_WR_INT_INT | TIGER_RD_INT_INT);
 580
 581         itjc_write_1(TIGER_DMA_OPER, TIGER_ENABLE_DMA);
 582
 583         /*
 584          * See if it really started.
 585          */
 586         ba = itjc_read_4(TIGER_DMA_RD_CURR_ADDR);
 587         for (i = 0; i < 10; ++i)
 588         {
 589                 DELAY(SEC_DELAY/1000);
 590                 if (ba != itjc_read_4(TIGER_DMA_RD_CURR_ADDR))
 591                 {
 592                         ctx->state = ITJC_DS_RUNNING;
 593                         return 0;
 594                 }
 595         }
 596
 597         NDBGL1(L1_ERROR, "itjc%d: dma_start: DMA start failed.\n ", unit);
 598         return 1;
 599 }
 600
 601
 602 /*---------------------------------------------------------------------------*
 603  *      itjc_dma_stop - Stop the Tiger DMA engine.
 604  *---------------------------------------------------------------------------*/
 605 void
 606 itjc_dma_stop(struct l1_softc *sc)
 607 {
 608         dma_context_t           *ctx    = &dma_context[sc->sc_unit];
 609
 610         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
 611         bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
 612
 613         /* Only stop the DMA if it is running. */
 614
 615         if (ctx->state != ITJC_DS_RUNNING)
 616                 return;
 617
 618         itjc_write_1(TIGER_DMA_OPER, TIGER_DISABLE_DMA);
 619         DELAY(SEC_DELAY/1000);
 620
 621         ctx->state = ITJC_DS_STOPPED;
 622 }
 623
 624
 625 /*---------------------------------------------------------------------------*
 626  *      itjc_bchannel_dma_setup - The DMA side of itjc_bchannel_setup.
 627  *---------------------------------------------------------------------------*/
 628 static void
 629 itjc_bchannel_dma_setup(struct l1_softc *sc, int h_chan, int activate)
 630 {
 631         dma_rx_context_t        *rxc  = &dma_rx_context[sc->sc_unit][h_chan];
 632         dma_tx_context_t        *txc  = &dma_tx_context[sc->sc_unit][h_chan];
 633
 634         l1_bchan_state_t        *chan = &sc->sc_chan[h_chan];
 635
 636         u_int8_t                fill_byte,
 637                                 *ring_end,
 638                                 *cp;
 639         bus_space_handle_t h;
 640         bus_space_tag_t t;
 641
 642         crit_enter();
 643         h = rman_get_bushandle(sc->sc_resources.io_base[0]);
 644         t = rman_get_bustag(sc->sc_resources.io_base[0]);
 645
 646         if (activate)
 647         {
 648                 /*
 649                  * Get the DMA engine going if it's not running already.
 650                  */
 651                 itjc_dma_start(sc);
 652
 653                 rxc->hdlc_len   = rxc->hdlc_tmp    = rxc->hdlc_crc  = 0;
 654                 rxc->hdlc_ib    = rxc->hdlc_blevel = rxc->hdlc_flag = 0;
 655
 656                 txc->hdlc_tmp   = txc->hdlc_blevel = txc->hdlc_crc  = 0;
 657                 txc->hdlc_ib    = 0;
 658                 txc->hdlc_flag  = 2;
 659                 txc->filled     = 0;
 660
 661                 if (chan->bprot == BPROT_NONE)
 662                         fill_byte = ITJC_TEL_SILENCE_BYTE;
 663                 else
 664                         fill_byte = ITJC_HDLC_ABORT_BYTE;
 665
 666                 ring_end = rxc->ring + ITJC_RING_BYTES;
 667                 for (cp = rxc->ring; cp < ring_end; cp += 4)
 668                         *cp = fill_byte;
 669
 670                 ring_end = txc->ring + ITJC_RING_BYTES;
 671                 for (cp = txc->ring; cp < ring_end; cp += 4)
 672                         *cp = fill_byte;
 673
 674                 rxc->next_read  =
 675                         itjc_get_dma_offset(rxc, TIGER_DMA_RD_CURR_ADDR);
 676
 677                 txc->next_frame = txc->next_write =
 678                         itjc_get_dma_offset(txc, TIGER_DMA_WR_CURR_ADDR);
 679
 680                 rxc->state      = ITJC_RS_ACTIVE;
 681                 txc->state      = ITJC_TS_AFTER_XDU;
 682         }
 683         else
 684         {
 685                 dma_rx_context_t        *rxc2;
 686
 687                 txc->state      = ITJC_TS_IDLE;
 688                 rxc->state      = ITJC_RS_IDLE;
 689
 690                 rxc2 = &dma_rx_context[sc->sc_unit][0];
 691
 692                 if (rxc2->state == ITJC_RS_IDLE
 693                 && rxc2[1].state == ITJC_RS_IDLE)
 694                         itjc_dma_stop(sc);
 695         }
 696
 697         crit_exit();
 698 }
 699
 700
 701 /*---------------------------------------------------------------------------*
 702  *      Mbuf & if_queues management routines.
 703  *---------------------------------------------------------------------------*/
 704
 705 static u_int8_t *
 706 itjc_get_rx_mbuf(l1_bchan_state_t *chan, u_int8_t **dst_end_p,
 707 which_mb_t which)
 708 {
 709         struct mbuf     *mbuf = chan->in_mbuf;
 710
 711         if (mbuf == NULL && which == ITJC_MB_NEW)
 712         {
 713                 if ((mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 714                         panic("itjc_get_rx_mbuf: cannot allocate mbuf!");
 715
 716                 chan->in_mbuf  = mbuf;
 717                 chan->in_cbptr = (u_int8_t *)mbuf->m_data;
 718                 chan->in_len   = 0;
 719         }
 720
 721         if (dst_end_p != NULL)
 722         {
 723                 if (mbuf != NULL)
 724                         *dst_end_p = (u_int8_t *)(mbuf->m_data)
 725                                 + BCH_MAX_DATALEN;
 726                 else
 727                         *dst_end_p = NULL;
 728         }
 729
 730         return chan->in_cbptr;
 731 }
 732
 733
 734 static void
 735 itjc_save_rx_mbuf(l1_bchan_state_t *chan, u_int8_t * dst)
 736 {
 737         struct mbuf     *mbuf = chan->in_mbuf;
 738
 739         if (dst != NULL && mbuf != NULL)
 740         {
 741                 chan->in_cbptr = dst;
 742                 chan->in_len   = dst - (u_int8_t *)mbuf->m_data;
 743         }
 744         else if (dst == NULL && mbuf == NULL)
 745         {
 746                 chan->in_cbptr = NULL;
 747                 chan->in_len   = 0;
 748         }
 749         else
 750                 panic("itjc_save_rx_mbuf: stale pointer dst=%p mbuf=%p "
 751                         "in_cbptr=%p in_len=%d", dst, mbuf,
 752                         chan->in_cbptr, chan->in_len);
 753 }
 754
 755
 756 static void
 757 itjc_free_rx_mbuf(l1_bchan_state_t *chan)
 758 {
 759         struct mbuf     *mbuf = chan->in_mbuf;
 760
 761         if (mbuf != NULL)
 762                 i4b_Bfreembuf(mbuf);
 763
 764         chan->in_mbuf  = NULL;
 765         chan->in_cbptr = NULL;
 766         chan->in_len   = 0;
 767 }
 768
 769
 770 static void
 771 itjc_put_rx_mbuf(struct l1_softc *sc, l1_bchan_state_t *chan, u_int16_t len)
 772 {
 773         i4b_trace_hdr_t hdr;
 774         struct mbuf     *mbuf    = chan->in_mbuf;
 775         u_int8_t        *data    = mbuf->m_data;
 776         int             activity = 1;
 777
 778         mbuf->m_pkthdr.len = mbuf->m_len = len;
 779
 780         if (sc->sc_trace & TRACE_B_RX)
 781         {
 782                 hdr.unit = L0ITJCUNIT(sc->sc_unit);
 783                 hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 784                 hdr.dir = FROM_NT;
 785                 hdr.count = ++sc->sc_trace_bcount;
 786                 MICROTIME(hdr.time);
 787                 i4b_l1_trace_ind(&hdr, len, data);
 788         }
 789
 790         if (chan->bprot == BPROT_NONE)
 791         {
 792                 activity = ! i4b_l1_bchan_tel_silence(data, len);
 793
 794                 /* move rx'd data to rx queue */
 795
 796                 if (!IF_QFULL(&chan->rx_queue))
 797                 {
 798                         IF_ENQUEUE(&chan->rx_queue, mbuf);
 799                 }
 800                 else
 801                 {
 802                         i4b_Bfreembuf(mbuf);
 803                         len = 0;
 804                 }
 805         }
 806
 807         if (len != 0)
 808         {
 809                 chan->rxcount += len;
 810
 811                 (*chan->isic_drvr_linktab->bch_rx_data_ready)
 812                         (chan->isic_drvr_linktab->unit);
 813         }
 814
 815         if (activity)
 816                 (*chan->isic_drvr_linktab->bch_activity)
 817                         (chan->isic_drvr_linktab->unit, ACT_RX);
 818
 819         chan->in_mbuf  = NULL;
 820         chan->in_cbptr = NULL;
 821         chan->in_len   = 0;
 822 }
 823
 824
 825 #define itjc_free_tx_mbufs(chan)                                        \
 826 {                                                                       \
 827         i4b_Bfreembuf((chan)->out_mbuf_head);                           \
 828         (chan)->out_mbuf_cur = (chan)->out_mbuf_head = NULL;            \
 829         (chan)->out_mbuf_cur_ptr = NULL;                                \
 830         (chan)->out_mbuf_cur_len = 0;                                   \
 831 }
 832
 833
 834 static u_int16_t
 835 itjc_get_tx_mbuf(struct l1_softc *sc, l1_bchan_state_t *chan,
 836         u_int8_t **src_p, which_mb_t which)
 837 {
 838         i4b_trace_hdr_t hdr;
 839         struct mbuf     *mbuf = chan->out_mbuf_cur;
 840         u_int8_t        activity = 1;
 841         u_int16_t       len;
 842         void            *data;
 843
 844         switch (which)
 845         {
 846         case ITJC_MB_CURR:
 847                 if (mbuf != NULL)
 848                 {
 849                         *src_p = chan->out_mbuf_cur_ptr;
 850                         return   chan->out_mbuf_cur_len;
 851                 }
 852
 853                 break;
 854
 855         case ITJC_MB_NEXT:
 856                 if (mbuf != NULL)
 857                 {
 858                         chan->txcount += mbuf->m_len;
 859
 860                         mbuf = mbuf->m_next;
 861
 862                         if (mbuf != NULL)
 863                                 goto new_mbuf;
 864                 }
 865
 866                 chan->out_mbuf_cur_ptr = *src_p = NULL;
 867                 chan->out_mbuf_cur_len = 0;
 868
 869                 if (chan->out_mbuf_head != NULL)
 870                 {
 871                         i4b_Bfreembuf(chan->out_mbuf_head);
 872                         chan->out_mbuf_head = NULL;
 873                 }
 874
 875                 return 0;
 876
 877         case ITJC_MB_NEW:
 878                 if (mbuf != NULL)
 879                         chan->txcount += mbuf->m_len;
 880         }
 881
 882         if (chan->out_mbuf_head != NULL)
 883                 i4b_Bfreembuf(chan->out_mbuf_head);
 884
 885         IF_DEQUEUE(&chan->tx_queue, mbuf);
 886
 887         if (mbuf == NULL)
 888         {
 889                 chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
 890                 chan->out_mbuf_cur_ptr = *src_p = NULL;
 891                 chan->out_mbuf_cur_len = 0;
 892
 893                 chan->state &= ~(HSCX_TX_ACTIVE);
 894
 895                 (*chan->isic_drvr_linktab->bch_tx_queue_empty)
 896                         (chan->isic_drvr_linktab->unit);
 897
 898                 return 0;
 899         }
 900
 901         chan->out_mbuf_head = mbuf;
 902
 903 new_mbuf:
 904         chan->out_mbuf_cur      = mbuf;
 905         chan->out_mbuf_cur_ptr  = data = mbuf->m_data;
 906         chan->out_mbuf_cur_len  = len  = mbuf->m_len;
 907
 908         chan->state |= HSCX_TX_ACTIVE;
 909
 910         if (sc->sc_trace & TRACE_B_TX)
 911         {
 912                 hdr.unit = L0ITJCUNIT(sc->sc_unit);
 913                 hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 914                 hdr.dir = FROM_TE;
 915                 hdr.count = ++sc->sc_trace_bcount;
 916                 MICROTIME(hdr.time);
 917                 i4b_l1_trace_ind(&hdr, len, data);
 918         }
 919
 920         if (chan->bprot == BPROT_NONE)
 921                 activity = ! i4b_l1_bchan_tel_silence(data, len);
 922
 923         if (activity)
 924                 (*chan->isic_drvr_linktab->bch_activity)
 925                         (chan->isic_drvr_linktab->unit, ACT_TX);
 926
 927         *src_p = data;
 928         return len;
 929 }
 930
 931
 932 #define itjc_save_tx_mbuf(chan, src, dst)                               \
 933 (                                                                       \
 934         (chan)->out_mbuf_cur != NULL ?                                  \
 935         (                                                               \
 936                 (chan)->out_mbuf_cur_ptr = (src),                       \
 937                 (chan)->out_mbuf_cur_len = (len)                        \
 938         )                                                               \
 939         :                                                               \
 940                 0                                                       \
 941 )
 942
 943
 944 /*---------------------------------------------------------------------------*
 945  *      B-channel interrupt service routines.
 946  *---------------------------------------------------------------------------*/
 947
 948 /*
 949  * Since the Tiger ASIC doesn't produce a XMIT underflow indication,
 950  * we need to deduce it ourselves. This is somewhat tricky because we
 951  * are dealing with modulo m arithmetic. The idea here is to have a
 952  * "XDU zone" ahead of the writing pointer sized 1/3 of total ring
 953  * length (a ring slot). If the hardware DMA pointer is found there we
 954  * consider that a XDU has occurred. To complete the scheme, we never
 955  * let the ring have more than 2 slots of (unsent) data and adjust the
 956  * interrupt registers to cause an interrupt at every slot.
 957  */
 958 static u_int8_t
 959 itjc_xdu(struct l1_softc *sc, l1_bchan_state_t *chan, dma_tx_context_t *ctx,
 960 u_int16_t *dst_p, u_int16_t *dst_end_p, u_int8_t tx_restart)
 961 {
 962         u_int8_t        xdu;
 963
 964         u_int16_t       dst_end,
 965                         dst,
 966                         dma,
 967                         dma_l,
 968                         dma_h,
 969                         xdu_l,
 970                         xdu_h;
 971
 972         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
 973         bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
 974
 975         /*
 976          * Since the hardware is running, be conservative and assume
 977          * the pointer location has a `fuzy' error factor.
 978          */
 979         dma   = itjc_get_dma_offset(ctx, TIGER_DMA_WR_CURR_ADDR);
 980         dma_l = dma;
 981         dma_h = itjc_ring_add(dma, 1);
 982
 983         dst_end = itjc_ring_sub(dma_l, ITJC_RING_SLOT_WORDS);
 984
 985         if (ctx->state != ITJC_TS_ACTIVE)
 986         {
 987                 xdu = (ctx->state == ITJC_TS_AFTER_XDU);
 988                 dst = itjc_ring_add(dma_h, 4);
 989                 goto done;
 990         }
 991
 992         /*
 993          * Check for xmit underruns.
 994          */
 995         xdu_l = dst = ctx->next_write;
 996         xdu_h = itjc_ring_add(dst, ITJC_RING_SLOT_WORDS);
 997
 998         if (xdu_l < xdu_h)
 999                 xdu =      (xdu_l <= dma_l && dma_l < xdu_h)
1000                         || (xdu_l <= dma_h && dma_h < xdu_h);
1001         else
1002                 xdu =      (xdu_l <= dma_l || dma_l < xdu_h)
1003                         || (xdu_l <= dma_h || dma_h < xdu_h);
1004
1005         if (xdu)
1006         {
1007                 ctx->state = ITJC_TS_AFTER_XDU;
1008
1009                 dst = itjc_ring_add(dma_h, 4);
1010         }
1011         else if (tx_restart)
1012         {
1013                 /*
1014                  * See if we still can restart from immediately
1015                  * after the last frame sent. It's a XDU test but
1016                  * using the real data end on the comparsions. We
1017                  * don't consider XDU an error here because we were
1018                  * just trying to avoid send a filling gap between
1019                  * frames. If it's already sent no harm is done.
1020                  */
1021                 xdu_l = dst = ctx->next_frame;
1022                 xdu_h = itjc_ring_add(dst, ITJC_RING_SLOT_WORDS);
1023
1024                 if (xdu_l < xdu_h)
1025                         xdu =      (xdu_l <= dma_l && dma_l < xdu_h)
1026                                 || (xdu_l <= dma_h && dma_h < xdu_h);
1027                 else
1028                         xdu =      (xdu_l <= dma_l || dma_l < xdu_h)
1029                                 || (xdu_l <= dma_h || dma_h < xdu_h);
1030
1031                 if (xdu)
1032                         dst = itjc_ring_add(dma_h, 4);
1033
1034                 xdu = 0;
1035         }
1036
1037 done:
1038         if (dst_p != NULL)
1039                 *dst_p = dst;
1040
1041         if (dst_end_p != NULL)
1042                 *dst_end_p = dst_end;
1043
1044         ctx->next_write = dst_end;
1045
1046         return xdu;
1047 }
1048
1049
1050 #define itjc_rotate_hdlc_flag(blevel)                                   \
1051         ((u_int8_t)(0x7E7E >> (8 - (u_int8_t)((blevel) >> 8))))
1052
1053
1054 static void
1055 itjc_dma_rx_intr(struct l1_softc *sc, l1_bchan_state_t *chan,
1056 dma_rx_context_t *ctx)
1057 {
1058         u_int8_t        *ring,
1059                         *dst,
1060                         *dst_end,
1061                         flag,
1062                         blevel;
1063
1064         u_int16_t       dma,
1065                         src,
1066                         tmp2,
1067                         tmp,
1068                         len,
1069                         crc,
1070                         ib;
1071
1072         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1073         bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
1074
1075
1076         if (ctx->state == ITJC_RS_IDLE)
1077                 return;
1078
1079         ring = ctx->ring;
1080         dma = itjc_get_dma_offset(ctx, TIGER_DMA_RD_CURR_ADDR);
1081         dma = itjc_ring_sub(dma, 1);
1082         src = ctx->next_read;
1083
1084         if (chan->bprot == BPROT_NONE)
1085         {
1086                 dst = itjc_get_rx_mbuf(chan, &dst_end, ITJC_MB_CURR);
1087
1088                 while (src != dma)
1089                 {
1090                         if (dst == NULL)
1091                                 dst = itjc_get_rx_mbuf(chan, &dst_end,
1092                                         ITJC_MB_NEW);
1093
1094                         *dst++ = ring[src];
1095                         src = itjc_ring_add(src, 1);
1096
1097                         if (dst >= dst_end)
1098                         {
1099                                 itjc_put_rx_mbuf(sc, chan, BCH_MAX_DATALEN);
1100                                 dst = dst_end = NULL;
1101                         }
1102                 }
1103                 ctx->next_read = src;
1104                 itjc_save_rx_mbuf(chan, dst);
1105                 return;
1106         }
1107
1108         blevel = ctx->hdlc_blevel;
1109         flag   = ctx->hdlc_flag;
1110         len    = ctx->hdlc_len;
1111         tmp    = ctx->hdlc_tmp;
1112         crc    = ctx->hdlc_crc;
1113         ib     = ctx->hdlc_ib;
1114
1115         dst = itjc_get_rx_mbuf(chan, NULL, ITJC_MB_CURR);
1116
1117         while (src != dma)
1118         {
1119                 HDLC_DECODE(*dst++, len, tmp, tmp2, blevel, ib, crc, flag,
1120                 {/* rdd */
1121                         tmp2 = ring[src];
1122                         src = itjc_ring_add(src, 1);
1123                 },
1124                 {/* nfr */
1125                         if (dst != NULL)
1126                                 panic("itjc_dma_rx_intr: nfrcmd with "
1127                                         "valid current frame");
1128
1129                         dst = itjc_get_rx_mbuf(chan, &dst_end, ITJC_MB_NEW);
1130                         len = dst_end - dst;
1131                 },
1132                 {/* cfr */
1133                         len = BCH_MAX_DATALEN - len;
1134
1135                         if ((!len) || (len > BCH_MAX_DATALEN))
1136                         {
1137                                 /*
1138                                  * NOTE: frames without any data, only crc
1139                                  * field, should be silently discared.
1140                                  */
1141                                 NDBGL1(L1_S_MSG, "itjc_dma_rx_intr: "
1142                                         "bad frame (len=%d, unit=%d)",
1143                                         len, sc->sc_unit);
1144
1145                                 itjc_free_rx_mbuf(chan);
1146
1147                                 goto s0;
1148                         }
1149
1150                         if (crc)
1151                         {
1152                                 NDBGL1(L1_S_ERR,
1153                                         "CRC (crc=0x%04x, len=%d, unit=%d)",
1154                                         crc, len, sc->sc_unit);
1155
1156                                 itjc_free_rx_mbuf(chan);
1157
1158                                 goto s0;
1159                         }
1160
1161                         itjc_put_rx_mbuf(sc, chan, len);
1162
1163                 s0:
1164                         dst = NULL;
1165                         len = 0;
1166                 },
1167                 {/* rab */
1168                         NDBGL1(L1_S_ERR, "Read Abort (unit=%d)", sc->sc_unit);
1169
1170                         itjc_free_rx_mbuf(chan);
1171                         dst = NULL;
1172                         len = 0;
1173                 },
1174                 {/* rdo */
1175                         NDBGL1(L1_S_ERR, "RDO (unit=%d) dma=%d src=%d",
1176                                 sc->sc_unit, dma, src);
1177
1178                         itjc_free_rx_mbuf(chan);
1179                         dst = NULL;
1180                         len = 0;
1181                 },
1182                 continue,
1183                 d);
1184         }
1185
1186         itjc_save_rx_mbuf(chan, dst);
1187
1188         ctx->next_read  = src;
1189         ctx->hdlc_blevel= blevel;
1190         ctx->hdlc_flag  = flag;
1191         ctx->hdlc_len   = len;
1192         ctx->hdlc_tmp   = tmp;
1193         ctx->hdlc_crc   = crc;
1194         ctx->hdlc_ib    = ib;
1195 }
1196
1197
1198 /*
1199  * The HDLC side of itjc_dma_tx_intr. We made a separate function
1200  * to improve readability and (perhaps) help the compiler with
1201  * register allocation.
1202  */
1203 static void
1204 itjc_hdlc_encode(struct l1_softc *sc, l1_bchan_state_t *chan,
1205 dma_tx_context_t * ctx)
1206 {
1207         u_int8_t        *ring,
1208                         *src,
1209                         xdu,
1210                         flag,
1211                         flag_byte,
1212                         tx_restart;
1213
1214         u_int16_t       saved_len,
1215                         dst_end,
1216                         dst_end1,
1217                         dst,
1218                         filled,
1219                         blevel,
1220                         tmp2,
1221                         len,
1222                         crc,
1223                         ib;
1224
1225         u_int32_t       tmp;
1226
1227
1228         saved_len = len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_CURR);
1229
1230         filled = ctx->filled;
1231         flag   = ctx->hdlc_flag;
1232
1233         if (src == NULL && flag == 2 && filled >= ITJC_RING_WORDS)
1234                 return;
1235
1236         tx_restart = (flag == 2 && src != NULL);
1237         xdu = itjc_xdu(sc, chan, ctx, &dst, &dst_end, tx_restart);
1238
1239         ring   = ctx->ring;
1240
1241         ib     = ctx->hdlc_ib;
1242         crc    = ctx->hdlc_crc;
1243         tmp    = ctx->hdlc_tmp;
1244         blevel = ctx->hdlc_blevel;
1245
1246         if (xdu)
1247         {
1248                 if (flag != 2)
1249                 {
1250                         NDBGL1(L1_H_XFRERR, "XDU");
1251                         ++chan->stat_XDU;
1252
1253                         /*
1254                          * Abort the current frame and
1255                          * prepare for a full restart.
1256                          */
1257                         itjc_free_tx_mbufs(chan);
1258                         saved_len = len = filled = 0;
1259                         flag = (u_int8_t)-2;
1260                 }
1261                 else if (filled < ITJC_RING_SLOT_WORDS)
1262                 {
1263                         /*
1264                          * A little garbage may have been retransmitted.
1265                          * Send an abort before any new data.
1266                          */
1267                         filled = 0;
1268                         flag = (u_int8_t)-2;
1269                 }
1270         }
1271
1272         if (flag != 3)
1273                 len = 0;
1274
1275         while (dst != dst_end)
1276         {
1277                 HDLC_ENCODE(
1278                 *src++, len, tmp, tmp2, blevel, ib, crc, flag,
1279                 {/* gfr */
1280                         if ((len = saved_len) == 0)
1281                                 len = itjc_get_tx_mbuf(sc, chan, &src,
1282                                         ITJC_MB_NEW);
1283
1284                         if (len == 0)
1285                         {
1286                                 ctx->next_frame = dst;
1287
1288                                 flag_byte = itjc_rotate_hdlc_flag(blevel);
1289
1290                                 for (dst_end1 = itjc_ring_sub(dst_end, 1);
1291                                 dst != dst_end1;
1292                                 dst = itjc_ring_add(dst, 1))
1293                                 {
1294                                         ring[dst] = flag_byte;
1295                                         ++filled;
1296                                 }
1297                         }
1298                         else
1299                                 filled = 0;
1300
1301                         ctx->state = ITJC_TS_ACTIVE;
1302                 },
1303                 {/* nmb */
1304                         saved_len = 0;
1305                         len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_NEXT);
1306                 },
1307                 {/* wrd */
1308                         ring[dst] = (u_int8_t)tmp;
1309                         dst = itjc_ring_add(dst, 1);
1310                 },
1311                 d1);
1312         }
1313
1314         ctx->hdlc_blevel = blevel;
1315         ctx->hdlc_flag   = flag;
1316         ctx->hdlc_tmp    = tmp;
1317         ctx->hdlc_crc    = crc;
1318         ctx->hdlc_ib     = ib;
1319
1320         ctx->filled = filled;
1321         ctx->next_write = dst;
1322
1323         itjc_save_tx_mbuf(chan, src, len);
1324 }
1325
1326
1327 static void
1328 itjc_dma_tx_intr(struct l1_softc *sc, l1_bchan_state_t *chan,
1329 dma_tx_context_t * ctx)
1330 {
1331         u_int8_t        *data_end,
1332                         *ring,
1333                         *src,
1334                         xdu;
1335
1336         u_int16_t       dst,
1337                         dst_end,
1338                         filled,
1339                         len;
1340
1341
1342         if (ctx->state == ITJC_TS_IDLE)
1343                 goto done;
1344
1345         if (chan->bprot != BPROT_NONE)
1346         {
1347                 itjc_hdlc_encode(sc, chan, ctx);
1348                 goto done;
1349         }
1350
1351         ring   = ctx->ring;
1352         filled = ctx->filled;
1353
1354         len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_CURR);
1355
1356         if (len == 0 && filled >= ITJC_RING_WORDS)
1357                 goto done;
1358
1359         xdu = itjc_xdu(sc, chan, ctx, &dst, &dst_end, len != 0);
1360
1361         if (xdu && filled < ITJC_RING_WORDS)
1362         {
1363                 NDBGL1(L1_H_XFRERR, "XDU");
1364                 ++chan->stat_XDU;
1365                 filled = 0;
1366         }
1367
1368         if (len == 0)
1369                 goto fill_ring;
1370
1371         ctx->state = ITJC_TS_ACTIVE;
1372
1373         data_end = src + len;
1374         while (dst != dst_end)
1375         {
1376                 ring[dst] = *src++; --len;
1377
1378                 dst = itjc_ring_add(dst, 1);
1379
1380                 if (src >= data_end)
1381                 {
1382                         len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_NEXT);
1383                         if (len == 0)
1384                                 len = itjc_get_tx_mbuf(sc, chan,
1385                                          &src, ITJC_MB_NEW);
1386
1387                         if (len == 0)
1388                         {
1389                                 data_end = NULL;
1390                                 break;
1391                         }
1392                         data_end = src + len;
1393                 }
1394         }
1395
1396         itjc_save_tx_mbuf(chan, src, len);
1397
1398         filled = 0;
1399
1400 fill_ring:
1401         ctx->next_frame = dst;
1402
1403         for (; dst != dst_end; dst = itjc_ring_add(dst, 1))
1404         {
1405                 ring[dst] = ITJC_TEL_SILENCE_BYTE;
1406                 ++filled;
1407         }
1408
1409         ctx->next_write = dst;
1410         ctx->filled = filled;
1411
1412 done:
1413         ;
1414 }
1415
1416
1417 /*---------------------------------------------------------------------------*
1418  *      NetJet fifo read/write routines.
1419  *---------------------------------------------------------------------------*/
1420
1421 static void
1422 itjc_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
1423 {
1424         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1425         bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
1426
1427         if (what != ISIC_WHAT_ISAC)
1428                 panic("itjc_write_fifo: Trying to read from HSCX fifo.\n");
1429
1430         itjc_set_pib_addr_msb(0);
1431         itjc_read_multi_1(PIB_OFFSET, buf, size);
1432 }
1433
1434
1435 static void
1436 itjc_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
1437 {
1438         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1439         bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
1440
1441         if (what != ISIC_WHAT_ISAC)
1442                 panic("itjc_write_fifo: Trying to write to HSCX fifo.\n");
1443
1444         itjc_set_pib_addr_msb(0);
1445         itjc_write_multi_1(PIB_OFFSET, buf, size);
1446 }
1447
1448
1449 /*---------------------------------------------------------------------------*
1450  *      Read an ISAC register.
1451  *---------------------------------------------------------------------------*/
1452 static u_int8_t
1453 itjc_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
1454 {
1455         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1456         bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
1457
1458         if (what != ISIC_WHAT_ISAC)
1459         {
1460                 panic("itjc_read_reg: what(%d) != ISIC_WHAT_ISAC\n",
1461                         what);
1462                 return 0;
1463         }
1464
1465         itjc_set_pib_addr_msb(offs);
1466         return itjc_read_1(itjc_pib_2_pci(offs));
1467 }
1468
1469
1470 /*---------------------------------------------------------------------------*
1471  *      Write an ISAC register.
1472  *---------------------------------------------------------------------------*/
1473 static void
1474 itjc_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
1475 {
1476         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1477         bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
1478
1479         if (what != ISIC_WHAT_ISAC)
1480         {
1481                 panic("itjc_write_reg: what(%d) != ISIC_WHAT_ISAC\n",
1482                         what);
1483                 return;
1484         }
1485
1486         itjc_set_pib_addr_msb(offs);
1487         itjc_write_1(itjc_pib_2_pci(offs), data);
1488 }
1489
1490
1491 /*---------------------------------------------------------------------------*
1492  *      itjc_probe - probe for a card.
1493  *---------------------------------------------------------------------------*/
1494 static int
1495 itjc_probe(device_t dev)
1496 {
1497         u_int16_t       vid = pci_get_vendor(dev),
1498                         did = pci_get_device(dev);
1499
1500         if ((vid == PCI_TJNET_VID) && (did == PCI_TJ300_DID))
1501         {
1502                 device_set_desc(dev, "NetJet-S");
1503                 return 0;
1504         }
1505
1506         return ENXIO;
1507 }
1508
1509
1510 /*---------------------------------------------------------------------------*
1511  *      itjc_attach - attach a (previously probed) card.
1512  *---------------------------------------------------------------------------*/
1513 int
1514 itjc_attach(device_t dev)
1515 {
1516         bus_space_handle_t      h;
1517         bus_space_tag_t         t;
1518
1519         struct l1_softc         *sc = device_get_softc(dev);
1520
1521         u_int16_t               vid = pci_get_vendor(dev),
1522                                 did = pci_get_device(dev);
1523
1524         int                     unit = device_get_unit(dev),
1525                                 res_init_level = 0,
1526                                 error = 0;
1527
1528         void                    *ih = 0;
1529
1530         dma_context_t           *ctx = &dma_context[unit];
1531
1532         crit_enter();
1533         bzero(sc, sizeof(struct l1_softc));
1534
1535         /* Probably not really required. */
1536         if (unit > ITJC_MAXUNIT)
1537         {
1538                 kprintf("itjc%d: Error, unit > ITJC_MAXUNIT!\n", unit);
1539                 crit_exit();
1540                 return ENXIO;
1541         }
1542
1543         if (!(vid == PCI_TJNET_VID && did == PCI_TJ300_DID))
1544         {
1545                 kprintf("itjc%d: unknown device (%04X,%04X)!\n", unit, vid, did);
1546                 goto fail;
1547         }
1548
1549         itjc_scp[unit] = sc;
1550
1551         sc->sc_resources.io_rid[0] = PCIR_MAPS+0;
1552         sc->sc_resources.io_base[0] = bus_alloc_resource(dev, SYS_RES_IOPORT,
1553                 &sc->sc_resources.io_rid[0], 0, ~0, 1, RF_ACTIVE);
1554
1555         if (sc->sc_resources.io_base[0] == NULL)
1556         {
1557                 kprintf("itjc%d: couldn't map IO port\n", unit);
1558                 error = ENXIO;
1559                 goto fail;
1560         }
1561
1562         h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1563         t = rman_get_bustag(sc->sc_resources.io_base[0]);
1564
1565         ++res_init_level;
1566
1567         /* Allocate interrupt. */
1568         sc->sc_resources.irq_rid = 0;
1569         sc->sc_resources.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
1570                 &sc->sc_resources.irq_rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
1571
1572         if (sc->sc_resources.irq == NULL)
1573         {
1574                 kprintf("itjc%d: couldn't map interrupt\n", unit);
1575                 error = ENXIO;
1576                 goto fail;
1577         }
1578
1579         ++res_init_level;
1580
1581         error = bus_setup_intr(dev, sc->sc_resources.irq, 0,
1582                                itjc_intr, sc, &ih, NULL);
1583
1584         if (error)
1585         {
1586                 kprintf("itjc%d: couldn't set up irq handler\n", unit);
1587                 error = ENXIO;
1588                 goto fail;
1589         }
1590
1591         /*
1592          * Reset the ASIC & the ISAC.
1593          */
1594         itjc_write_1(TIGER_RESET_PIB_CL_TIME, TIGER_RESET_ALL);
1595
1596         DELAY(SEC_DELAY/100); /* Give it 10 ms to reset ...*/
1597
1598         itjc_write_1(TIGER_RESET_PIB_CL_TIME,
1599                 TIGER_SELF_ADDR_DMA | TIGER_PIB_3_CYCLES);
1600
1601         DELAY(SEC_DELAY/100); /* ... and more 10 to recover. */
1602
1603         /*
1604          * First part of DMA initialization. Create & map the memory
1605          * pool that will be used to bear the rx & tx ring buffers.
1606          */
1607         ctx->state = ITJC_DS_LOADING;
1608
1609         error = bus_dma_tag_create(
1610                 NULL,                                   /* parent */
1611                 4,                                      /* alignment*/
1612                 0,                                      /* boundary*/
1613                 BUS_SPACE_MAXADDR_32BIT,                /* lowaddr*/
1614                 BUS_SPACE_MAXADDR,                      /* highaddr*/
1615                 NULL,                                   /* filter*/
1616                 NULL,                                   /* filterarg*/
1617                 ITJC_DMA_POOL_BYTES,                    /* maxsize*/
1618                 1,                                      /* nsegments*/
1619                 ITJC_DMA_POOL_BYTES,                    /* maxsegsz*/
1620                 BUS_DMA_ALLOCNOW | BUS_DMA_COHERENT,    /* flags*/
1621                 &ctx->tag);
1622
1623         if (error)
1624         {
1625                 kprintf("itjc%d: couldn't create bus DMA tag.\n", unit);
1626                 goto fail;
1627         }
1628
1629         ++res_init_level;
1630
1631         error = bus_dmamem_alloc(
1632                 ctx->tag,                               /* DMA tag */
1633                 (void **)&ctx->pool,    /* KV addr of the allocated memory */
1634                 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,      /* flags */
1635                 &ctx->map);                             /* KV <-> PCI map */
1636
1637         if (error)
1638                 goto fail;
1639
1640         /*
1641          * Load the KV <-> PCI map so the device sees the same
1642          * memory segment as pointed by pool. Note: since the
1643          * load may happen assyncronously (completion indicated by
1644          * the execution of the callback function) we have to
1645          * delay the initialization of the DMA engine to a moment we
1646          * actually have the proper bus addresses to feed the Tiger
1647          * and our DMA control blocks. This will be done in
1648          * itjc_bchannel_setup via a call to itjc_dma_start.
1649          */
1650         bus_dmamap_load(
1651                 ctx->tag,               /* DMA tag */
1652                 ctx->map,               /* DMA map */
1653                 ctx->pool,              /* KV addr of buffer */
1654                 ITJC_DMA_POOL_BYTES,    /* buffer size */
1655                 itjc_map_callback,      /* this receive the bus addr/error */
1656                 ctx,                    /* callback aux arg */
1657                 0);                     /* flags */
1658
1659         ++res_init_level;
1660
1661         /*
1662          * Setup the AUX port so we can talk to the ISAC.
1663          */
1664         itjc_write_1(TIGER_AUX_PORT_CNTL, TIGER_AUX_NJ_DEFAULT);
1665         itjc_write_1(TIGER_INT1_MASK, TIGER_ISAC_INT);
1666
1667         /*
1668          * From now on, almost like a `normal' ISIC driver.
1669          */
1670
1671         sc->sc_unit = unit;
1672
1673         ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
1674
1675         HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
1676         HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
1677
1678         /* setup access routines */
1679
1680         sc->clearirq = NULL;
1681         sc->readreg = itjc_read_reg;
1682         sc->writereg = itjc_write_reg;
1683
1684         sc->readfifo = itjc_read_fifo;
1685         sc->writefifo = itjc_write_fifo;
1686
1687         /* setup card type */
1688
1689         sc->sc_cardtyp = CARD_TYPEP_NETJET_S;
1690
1691         /* setup IOM bus type */
1692
1693         sc->sc_bustyp = BUS_TYPE_IOM2;
1694
1695         /* set up some other miscellaneous things */
1696         sc->sc_ipac = 0;
1697         sc->sc_bfifolen = 2 * ITJC_RING_SLOT_WORDS;
1698
1699         kprintf("itjc%d: ISAC 2186 Version 1.1 (IOM-2)\n", unit);
1700
1701         /* init the ISAC */
1702         itjc_isac_init(sc);
1703
1704         /* init the "HSCX" */
1705         itjc_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
1706
1707         itjc_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
1708
1709         /* can't use the normal B-Channel stuff */
1710         itjc_init_linktab(sc);
1711
1712         /* set trace level */
1713
1714         sc->sc_trace = TRACE_OFF;
1715
1716         sc->sc_state = ISAC_IDLE;
1717
1718         sc->sc_ibuf = NULL;
1719         sc->sc_ib = NULL;
1720         sc->sc_ilen = 0;
1721
1722         sc->sc_obuf = NULL;
1723         sc->sc_op = NULL;
1724         sc->sc_ol = 0;
1725         sc->sc_freeflag = 0;
1726
1727         sc->sc_obuf2 = NULL;
1728         sc->sc_freeflag2 = 0;
1729
1730         callout_init(&sc->sc_T3_timeout);
1731         callout_init(&sc->sc_T4_timeout);
1732
1733         /* init higher protocol layers */
1734
1735         i4b_l1_mph_status_ind(L0ITJCUNIT(sc->sc_unit), STI_ATTACH,
1736                 sc->sc_cardtyp, &itjc_l1mux_func);
1737
1738         crit_exit();
1739         return 0;
1740
1741   fail:
1742         switch (res_init_level)
1743         {
1744         case 5:
1745                 bus_dmamap_unload(ctx->tag, ctx->map);
1746                 /* FALL TRHU */
1747
1748         case 4:
1749                 bus_dmamem_free(ctx->tag, ctx->pool, ctx->map);
1750                 bus_dmamap_destroy(ctx->tag, ctx->map);
1751                 /* FALL TRHU */
1752
1753         case 3:
1754                 bus_dma_tag_destroy(ctx->tag);
1755                 /* FALL TRHU */
1756
1757         case 2:
1758                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_resources.irq);
1759                 /* FALL TRHU */
1760
1761         case 1:
1762                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+0,
1763                         sc->sc_resources.io_base[0]);
1764                 /* FALL TRHU */
1765
1766         case 0:
1767                 break;
1768         }
1769
1770         itjc_scp[unit] = NULL;
1771
1772         crit_exit();
1773         return error;
1774 }
1775
1776
1777 /*---------------------------------------------------------------------------*
1778  *      itjc_intr - main interrupt service routine.
1779  *---------------------------------------------------------------------------*/
1780 static void
1781 itjc_intr(void *xsc)
1782 {
1783         struct l1_softc         *sc     = xsc;
1784         l1_bchan_state_t        *chan   = &sc->sc_chan[0];
1785         dma_context_t           *dma    = &dma_context[sc->sc_unit];
1786         dma_rx_context_t        *rxc    = &dma_rx_context[sc->sc_unit][0];
1787         dma_tx_context_t        *txc    = &dma_tx_context[sc->sc_unit][0];
1788
1789         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1790         bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
1791
1792         /* Honor interrupts from successfully configured cards only. */
1793         if (dma->state < ITJC_DS_STOPPED)
1794                 return;
1795
1796         /* First, we check the ISAC... */
1797         if (! (itjc_read_1(TIGER_AUX_PORT_DATA) & TIGER_ISAC_INT_MASK))
1798         {
1799                 itjc_write_1(TIGER_INT1_STATUS, TIGER_ISAC_INT);
1800                 NDBGL1(L1_H_IRQ, "ISAC");
1801                 itjc_isac_intr(sc);
1802         }
1803
1804         /* ... after what we always have a look at the DMA rings. */
1805
1806         NDBGL1(L1_H_IRQ, "Tiger");
1807
1808         itjc_read_1(TIGER_INT0_STATUS);
1809         itjc_write_1(TIGER_INT0_STATUS, TIGER_TARGET_ABORT_INT
1810                 | TIGER_MASTER_ABORT_INT | TIGER_RD_END_INT
1811                 | TIGER_RD_INT_INT       | TIGER_WR_END_INT | TIGER_WR_INT_INT);
1812
1813         itjc_dma_rx_intr(sc, chan, rxc);
1814         itjc_dma_tx_intr(sc, chan, txc);
1815
1816         ++chan; ++rxc; ++txc;
1817
1818         itjc_dma_rx_intr(sc, chan, rxc);
1819         itjc_dma_tx_intr(sc, chan, txc);
1820 }
1821
1822
1823 /*---------------------------------------------------------------------------*
1824  *      itjc_bchannel_setup - (Re)initialize and start/stop a Bchannel.
1825  *---------------------------------------------------------------------------*/
1826 static void
1827 itjc_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1828 {
1829         struct l1_softc         *sc     = itjc_scp[unit];
1830         l1_bchan_state_t        *chan   = &sc->sc_chan[h_chan];
1831
1832         crit_enter();
1833
1834         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1835                 unit, h_chan, activate ? "activate" : "deactivate");
1836
1837         /*
1838          * If we are deactivating the channel, we have to stop
1839          * the DMA before we reset the channel control structures.
1840          */
1841         if (! activate)
1842                 itjc_bchannel_dma_setup(sc, h_chan, activate);
1843
1844         /* general part */
1845
1846         chan->state = HSCX_IDLE;
1847
1848         chan->unit = sc->sc_unit;       /* unit number */
1849         chan->channel = h_chan;         /* B channel */
1850         chan->bprot = bprot;            /* B channel protocol */
1851
1852         /* receiver part */
1853
1854         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1855
1856         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1857
1858         chan->rxcount = 0;              /* reset rx counter */
1859
1860         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
1861
1862         chan->in_mbuf = NULL;           /* reset mbuf ptr */
1863         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
1864         chan->in_len = 0;               /* reset mbuf data len */
1865
1866         /* transmitter part */
1867
1868         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1869
1870         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1871
1872         chan->txcount = 0;              /* reset tx counter */
1873
1874         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
1875
1876         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
1877         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */
1878         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
1879         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
1880
1881         /*
1882          * Only setup & start the DMA after all other channel
1883          * control structures are in place.
1884          */
1885         if (activate)
1886                 itjc_bchannel_dma_setup(sc, h_chan, activate);
1887
1888         crit_exit();
1889 }
1890
1891
1892 /*---------------------------------------------------------------------------*
1893  *      itjc_bchannel_start - Signal us we have more data to send.
1894  *---------------------------------------------------------------------------*/
1895 static void
1896 itjc_bchannel_start(int unit, int h_chan)
1897 {
1898 #if Buggy_code
1899         /*
1900          * I disabled this routine because it was causing crashes when
1901          * this driver was used with the ISP (kernel SPPP) protocol driver.
1902          * The scenario is reproductible:
1903          *      Use the -link1 (dial on demand) ifconfig option.
1904          *      Start an interactive  TCP connection to somewhere.
1905          *      Wait until the PPP connection times out and is dropped.
1906          *      Try to send something on the TCP connection.
1907          *      The machine will print some garbage and halt or reboot
1908          *      (no panic messages).
1909          *
1910          * I've nailed down the problem to the fact that this routine
1911          * was being called before the B channel had been setup again.
1912          *
1913          * For now, I don't have a good solution other than this one.
1914          * But, don't despair. The impact of it is unnoticeable.
1915          */
1916
1917         struct l1_softc  *sc    = itjc_scp[unit];
1918         l1_bchan_state_t *chan  = &sc->sc_chan[h_chan];
1919         dma_tx_context_t *txc   = &dma_tx_context[unit][h_chan];
1920
1921         crit_enter();
1922
1923         if (chan->state & HSCX_TX_ACTIVE)
1924         {
1925                 crit_exit();
1926                 return;
1927         }
1928
1929         itjc_dma_tx_intr(sc, chan, txc);
1930
1931         crit_exit();
1932 #endif
1933 }
1934
1935
1936 /*---------------------------------------------------------------------------*
1937  *      itjc_shutdown - Stop the driver and reset the card.
1938  *---------------------------------------------------------------------------*/
1939 static void
1940 itjc_shutdown(device_t dev)
1941 {
1942         struct l1_softc *sc = device_get_softc(dev);
1943         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1944         bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
1945
1946         /*
1947          * Stop the DMA the nice and easy way.
1948          */
1949         itjc_bchannel_setup(sc->sc_unit, 0, BPROT_NONE, 0);
1950         itjc_bchannel_setup(sc->sc_unit, 1, BPROT_NONE, 0);
1951
1952         /*
1953          * Reset the card.
1954          */
1955         itjc_write_1(TIGER_RESET_PIB_CL_TIME, TIGER_RESET_ALL);
1956
1957         DELAY(SEC_DELAY/100); /* Give it 10 ms to reset ...*/
1958
1959         itjc_write_1(TIGER_RESET_PIB_CL_TIME,
1960                 TIGER_SELF_ADDR_DMA | TIGER_LATCH_DMA_INT | TIGER_PIB_3_CYCLES);
1961
1962         DELAY(SEC_DELAY/100); /* ... and more 10 to recover */
1963 }
1964
1965
1966 /*---------------------------------------------------------------------------*
1967  *      itjc_ret_linktab - Return the address of itjc drivers linktab.
1968  *---------------------------------------------------------------------------*/
1969 isdn_link_t *
1970 itjc_ret_linktab(int unit, int channel)
1971 {
1972         struct l1_softc         *sc = itjc_scp[unit];
1973         l1_bchan_state_t        *chan = &sc->sc_chan[channel];
1974
1975         return(&chan->isic_isdn_linktab);
1976 }
1977
1978 /*---------------------------------------------------------------------------*
1979  *      itjc_set_linktab - Set the driver linktab in the b channel softc.
1980  *---------------------------------------------------------------------------*/
1981 void
1982 itjc_set_linktab(int unit, int channel, drvr_link_t *dlt)
1983 {
1984         struct l1_softc *sc     = itjc_scp[unit];
1985         l1_bchan_state_t *chan  = &sc->sc_chan[channel];
1986
1987         chan->isic_drvr_linktab = dlt;
1988 }
1989
1990
1991 /*---------------------------------------------------------------------------*
1992  *      itjc_init_linktab - Initialize our local linktab.
1993  *---------------------------------------------------------------------------*/
1994 static void
1995 itjc_init_linktab(struct l1_softc *sc)
1996 {
1997         l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1998         isdn_link_t *lt = &chan->isic_isdn_linktab;
1999
2000         /* make sure the hardware driver is known to layer 4 */
2001         /* avoid overwriting if already set */
2002         if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
2003         {
2004                 ctrl_types[CTRL_PASSIVE].set_linktab = itjc_set_linktab;
2005                 ctrl_types[CTRL_PASSIVE].get_linktab = itjc_ret_linktab;
2006         }
2007
2008         /* local setup */
2009         lt->unit = sc->sc_unit;
2010         lt->channel = HSCX_CH_A;
2011         lt->bch_config = itjc_bchannel_setup;
2012         lt->bch_tx_start = itjc_bchannel_start;
2013         lt->bch_stat = itjc_bchannel_stat;
2014         lt->tx_queue = &chan->tx_queue;
2015
2016         /* used by non-HDLC data transfers, i.e. telephony drivers */
2017         lt->rx_queue = &chan->rx_queue;
2018
2019         /* used by HDLC data transfers, i.e. ipr and isp drivers */
2020         lt->rx_mbuf = &chan->in_mbuf;
2021
2022         chan = &sc->sc_chan[HSCX_CH_B];
2023         lt = &chan->isic_isdn_linktab;
2024
2025         lt->unit = sc->sc_unit;
2026         lt->channel = HSCX_CH_B;
2027         lt->bch_config = itjc_bchannel_setup;
2028         lt->bch_tx_start = itjc_bchannel_start;
2029         lt->bch_stat = itjc_bchannel_stat;
2030         lt->tx_queue = &chan->tx_queue;
2031
2032         /* used by non-HDLC data transfers, i.e. telephony drivers */
2033         lt->rx_queue = &chan->rx_queue;
2034
2035         /* used by HDLC data transfers, i.e. ipr and isp drivers */
2036         lt->rx_mbuf = &chan->in_mbuf;
2037 }
2038
2039
2040 /*---------------------------------------------------------------------------*
2041  *      itjc_bchannel_stat - Collect link statistics for a given B channel.
2042  *---------------------------------------------------------------------------*/
2043 static void
2044 itjc_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
2045 {
2046         struct l1_softc *sc = itjc_scp[unit];
2047         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
2048
2049         crit_enter();
2050
2051         bsp->outbytes = chan->txcount;
2052         bsp->inbytes = chan->rxcount;
2053
2054         chan->txcount = 0;
2055         chan->rxcount = 0;
2056
2057         crit_exit();
2058 }
2059
2060
2061 /*---------------------------------------------------------------------------*
2062  *      Netjet - ISAC interrupt routine.
2063  *---------------------------------------------------------------------------*/
2064 static void
2065 itjc_isac_intr(struct l1_softc *sc)
2066 {
2067         u_char irq_stat;
2068
2069         do
2070         {
2071                 /* get isac irq status */
2072                 irq_stat = ISAC_READ(I_ISTA);
2073
2074                 if(irq_stat)
2075                         itjc_isac_irq(sc, irq_stat); /* isac handler */
2076         }
2077         while(irq_stat);
2078
2079         ISAC_WRITE(I_MASK, 0xff);
2080
2081         DELAY(100);
2082
2083         ISAC_WRITE(I_MASK, ISAC_IMASK);
2084 }
2085
2086
2087 /*---------------------------------------------------------------------------*
2088  *      itjc_recover - Try to recover from ISAC irq lockup.
2089  *---------------------------------------------------------------------------*/
2090 void
2091 itjc_recover(struct l1_softc *sc)
2092 {
2093         u_char byte;
2094
2095         /* get isac irq status */
2096
2097         byte = ISAC_READ(I_ISTA);
2098
2099         NDBGL1(L1_ERROR, "  ISAC: ISTA = 0x%x", byte);
2100
2101         if(byte & ISAC_ISTA_EXI)
2102                 NDBGL1(L1_ERROR, "  ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
2103
2104         if(byte & ISAC_ISTA_CISQ)
2105         {
2106                 byte = ISAC_READ(I_CIRR);
2107
2108                 NDBGL1(L1_ERROR, "  ISAC: CISQ = 0x%x", byte);
2109
2110                 if(byte & ISAC_CIRR_SQC)
2111                         NDBGL1(L1_ERROR, "  ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
2112         }
2113
2114         NDBGL1(L1_ERROR, "  ISAC: IMASK = 0x%x", ISAC_IMASK);
2115
2116         ISAC_WRITE(I_MASK, 0xff);
2117         DELAY(100);
2118         ISAC_WRITE(I_MASK, ISAC_IMASK);
2119 }
2120
2121 #endif /* NITJC > 0 */