2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/kernel.h>
32 #include <sys/machintr.h>
33 #include <machine/globaldata.h>
34 #include <machine/smp.h>
35 #include <machine/cputypes.h>
36 #include <machine/specialreg.h>
37 #include <machine/md_var.h>
38 #include <machine/pmap.h>
39 #include <machine_base/apic/lapic.h>
40 #include <machine_base/apic/ioapic_abi.h>
41 #include <machine/segments.h>
42 #include <sys/thread2.h>
44 #include <machine/intr_machdep.h>
46 volatile lapic_t *lapic;
48 static void lapic_timer_calibrate(void);
49 static void lapic_timer_set_divisor(int);
50 static void lapic_timer_fixup_handler(void *);
51 static void lapic_timer_restart_handler(void *);
53 void lapic_timer_process(void);
54 void lapic_timer_process_frame(struct intrframe *);
56 static int lapic_timer_enable = 1;
57 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
59 static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
60 static void lapic_timer_intr_enable(struct cputimer_intr *);
61 static void lapic_timer_intr_restart(struct cputimer_intr *);
62 static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
64 static struct cputimer_intr lapic_cputimer_intr = {
66 .reload = lapic_timer_intr_reload,
67 .enable = lapic_timer_intr_enable,
68 .config = cputimer_intr_default_config,
69 .restart = lapic_timer_intr_restart,
70 .pmfixup = lapic_timer_intr_pmfixup,
71 .initclock = cputimer_intr_default_initclock,
72 .next = SLIST_ENTRY_INITIALIZER,
74 .type = CPUTIMER_INTR_LAPIC,
75 .prio = CPUTIMER_INTR_PRIO_LAPIC,
76 .caps = CPUTIMER_INTR_CAP_NONE
79 static int lapic_timer_divisor_idx = -1;
80 static const uint32_t lapic_timer_divisors[] = {
81 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
82 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
84 #define APIC_TIMER_NDIVISORS (int)(NELEM(lapic_timer_divisors))
87 * APIC ID <-> CPU ID mapping structures.
89 int cpu_id_to_apic_id[NAPICID];
90 int apic_id_to_cpu_id[NAPICID];
93 * Enable LAPIC, configure interrupts.
96 lapic_init(boolean_t bsp)
104 * Since IDT is shared between BSP and APs, these vectors
105 * only need to be installed once; we do it on BSP.
108 /* Install a 'Spurious INTerrupt' vector */
109 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
110 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
112 /* Install an inter-CPU IPI for TLB invalidation */
113 setidt(XINVLTLB_OFFSET, Xinvltlb,
114 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
116 /* Install an inter-CPU IPI for IPIQ messaging */
117 setidt(XIPIQ_OFFSET, Xipiq,
118 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
120 /* Install a timer vector */
121 setidt(XTIMER_OFFSET, Xtimer,
122 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
124 /* Install an inter-CPU IPI for CPU stop/restart */
125 setidt(XCPUSTOP_OFFSET, Xcpustop,
126 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
130 * Setup LINT0 as ExtINT on the BSP. This is theoretically an
131 * aggregate interrupt input from the 8259. The INTA cycle
132 * will be routed to the external controller (the 8259) which
133 * is expected to supply the vector.
135 * Must be setup edge triggered, active high.
137 * Disable LINT0 on BSP, if I/O APIC is enabled.
139 * Disable LINT0 on the APs. It doesn't matter what delivery
140 * mode we use because we leave it masked.
142 temp = lapic->lvt_lint0;
143 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
144 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
146 temp |= APIC_LVT_DM_EXTINT;
148 temp |= APIC_LVT_MASKED;
150 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
152 lapic->lvt_lint0 = temp;
155 * Setup LINT1 as NMI.
157 * Must be setup edge trigger, active high.
159 * Enable LINT1 on BSP, if I/O APIC is enabled.
161 * Disable LINT1 on the APs.
163 temp = lapic->lvt_lint1;
164 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
165 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
166 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
167 if (bsp && ioapic_enable)
168 temp &= ~APIC_LVT_MASKED;
169 lapic->lvt_lint1 = temp;
172 * Mask the LAPIC error interrupt, LAPIC performance counter
175 lapic->lvt_error = lapic->lvt_error | APIC_LVT_MASKED;
176 lapic->lvt_pcint = lapic->lvt_pcint | APIC_LVT_MASKED;
179 * Set LAPIC timer vector and mask the LAPIC timer interrupt.
181 timer = lapic->lvt_timer;
182 timer &= ~APIC_LVTT_VECTOR;
183 timer |= XTIMER_OFFSET;
184 timer |= APIC_LVTT_MASKED;
185 lapic->lvt_timer = timer;
188 * Set the Task Priority Register as needed. At the moment allow
189 * interrupts on all cpus (the APs will remain CLId until they are
193 temp &= ~APIC_TPR_PRIO; /* clear priority field */
200 temp |= APIC_SVR_ENABLE; /* enable the LAPIC */
201 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
204 * Set the spurious interrupt vector. The low 4 bits of the vector
207 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
208 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
209 temp &= ~APIC_SVR_VECTOR;
210 temp |= XSPURIOUSINT_OFFSET;
215 * Pump out a few EOIs to clean out interrupts that got through
216 * before we were able to set the TPR.
223 lapic_timer_calibrate();
224 if (lapic_timer_enable) {
225 cputimer_intr_register(&lapic_cputimer_intr);
226 cputimer_intr_select(&lapic_cputimer_intr, 0);
229 lapic_timer_set_divisor(lapic_timer_divisor_idx);
233 apic_dump("apic_initialize()");
237 lapic_timer_set_divisor(int divisor_idx)
239 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
240 lapic->dcr_timer = lapic_timer_divisors[divisor_idx];
244 lapic_timer_oneshot(u_int count)
248 value = lapic->lvt_timer;
249 value &= ~APIC_LVTT_PERIODIC;
250 lapic->lvt_timer = value;
251 lapic->icr_timer = count;
255 lapic_timer_oneshot_quick(u_int count)
257 lapic->icr_timer = count;
261 lapic_timer_calibrate(void)
265 /* Try to calibrate the local APIC timer. */
266 for (lapic_timer_divisor_idx = 0;
267 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
268 lapic_timer_divisor_idx++) {
269 lapic_timer_set_divisor(lapic_timer_divisor_idx);
270 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
272 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
273 if (value != APIC_TIMER_MAX_COUNT)
276 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
277 panic("lapic: no proper timer divisor?!\n");
278 lapic_cputimer_intr.freq = value / 2;
280 kprintf("lapic: divisor index %d, frequency %u Hz\n",
281 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
285 lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
289 gd->gd_timer_running = 0;
291 count = sys_cputimer->count();
292 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
293 systimer_intr(&count, 0, frame);
297 lapic_timer_process(void)
299 lapic_timer_process_oncpu(mycpu, NULL);
303 lapic_timer_process_frame(struct intrframe *frame)
305 lapic_timer_process_oncpu(mycpu, frame);
309 lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
311 struct globaldata *gd = mycpu;
313 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
317 if (gd->gd_timer_running) {
318 if (reload < lapic->ccr_timer)
319 lapic_timer_oneshot_quick(reload);
321 gd->gd_timer_running = 1;
322 lapic_timer_oneshot_quick(reload);
327 lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
331 timer = lapic->lvt_timer;
332 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
333 lapic->lvt_timer = timer;
335 lapic_timer_fixup_handler(NULL);
339 lapic_timer_fixup_handler(void *arg)
346 if (cpu_vendor_id == CPU_VENDOR_AMD) {
348 * Detect the presence of C1E capability mostly on latest
349 * dual-cores (or future) k8 family. This feature renders
350 * the local APIC timer dead, so we disable it by reading
351 * the Interrupt Pending Message register and clearing both
352 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
355 * "BIOS and Kernel Developer's Guide for AMD NPT
356 * Family 0Fh Processors"
357 * #32559 revision 3.00
359 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
360 (cpu_id & 0x0fff0000) >= 0x00040000) {
363 msr = rdmsr(0xc0010055);
364 if (msr & 0x18000000) {
365 struct globaldata *gd = mycpu;
367 kprintf("cpu%d: AMD C1E detected\n",
369 wrmsr(0xc0010055, msr & ~0x18000000ULL);
372 * We are kinda stalled;
375 gd->gd_timer_running = 1;
376 lapic_timer_oneshot_quick(2);
386 lapic_timer_restart_handler(void *dummy __unused)
390 lapic_timer_fixup_handler(&started);
392 struct globaldata *gd = mycpu;
394 gd->gd_timer_running = 1;
395 lapic_timer_oneshot_quick(2);
400 * This function is called only by ACPI-CA code currently:
401 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
402 * module controls PM. So once ACPI-CA is attached, we try
403 * to apply the fixup to prevent LAPIC timer from hanging.
406 lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
408 lwkt_send_ipiq_mask(smp_active_mask,
409 lapic_timer_fixup_handler, NULL);
413 lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
415 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
420 * dump contents of local APIC registers
425 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
426 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
427 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
431 * Inter Processor Interrupt functions.
435 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
437 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
438 * vector is any valid SYSTEM INT vector
439 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
441 * A backlog of requests can create a deadlock between cpus. To avoid this
442 * we have to be able to accept IPIs at the same time we are trying to send
443 * them. The critical section prevents us from attempting to send additional
444 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
445 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
446 * to occur but fortunately it does not happen too often.
449 apic_ipi(int dest_type, int vector, int delivery_mode)
454 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
455 unsigned int eflags = read_eflags();
457 DEBUG_PUSH_INFO("apic_ipi");
458 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
462 write_eflags(eflags);
465 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
466 delivery_mode | vector;
467 lapic->icr_lo = icr_lo;
473 single_apic_ipi(int cpu, int vector, int delivery_mode)
479 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
480 unsigned int eflags = read_eflags();
482 DEBUG_PUSH_INFO("single_apic_ipi");
483 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
487 write_eflags(eflags);
489 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
490 icr_hi |= (CPUID_TO_APICID(cpu) << 24);
491 lapic->icr_hi = icr_hi;
494 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK)
495 | APIC_DEST_DESTFLD | delivery_mode | vector;
498 lapic->icr_lo = icr_lo;
505 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
507 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
508 * to the target, and the scheduler does not 'poll' for IPI messages.
511 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
517 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
521 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
522 icr_hi |= (CPUID_TO_APICID(cpu) << 24);
523 lapic->icr_hi = icr_hi;
526 icr_lo = (lapic->icr_lo & APIC_RESV2_MASK)
527 | APIC_DEST_DESTFLD | delivery_mode | vector;
530 lapic->icr_lo = icr_lo;
538 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
540 * target is a bitmask of destination cpus. Vector is any
541 * valid system INT vector. Delivery mode may be either
542 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
545 selected_apic_ipi(cpumask_t target, int vector, int delivery_mode)
549 int n = BSFCPUMASK(target);
550 target &= ~CPUMASK(n);
551 single_apic_ipi(n, vector, delivery_mode);
557 * Timer code, in development...
558 * - suggested by rgrimes@gndrsh.aac.dev.com
561 get_apic_timer_frequency(void)
563 return(lapic_cputimer_intr.freq);
567 * Load a 'downcount time' in uSeconds.
570 set_apic_timer(int us)
575 * When we reach here, lapic timer's frequency
576 * must have been calculated as well as the
577 * divisor (lapic.dcr_timer is setup during the
578 * divisor calculation).
580 KKASSERT(lapic_cputimer_intr.freq != 0 &&
581 lapic_timer_divisor_idx >= 0);
583 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
584 lapic_timer_oneshot(count);
589 * Read remaining time in timer.
592 read_apic_timer(void)
595 /** XXX FIXME: we need to return the actual remaining time,
596 * for now we just return the remaining count.
599 return lapic->ccr_timer;
605 * Spin-style delay, set delay time in uS, spin till it drains.
610 set_apic_timer(count);
611 while (read_apic_timer())
616 lapic_unused_apic_id(int start)
620 for (i = start; i < NAPICID; ++i) {
621 if (APICID_TO_CPUID(i) == -1)
628 lapic_map(vm_offset_t lapic_addr)
630 lapic = pmap_mapdev_uncacheable(lapic_addr, sizeof(struct LAPIC));
632 kprintf("lapic: at %p\n", (void *)lapic_addr);
635 static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
636 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
641 struct lapic_enumerator *e;
642 int error, i, enable, ap_max;
644 for (i = 0; i < NAPICID; ++i)
645 APICID_TO_CPUID(i) = -1;
648 TUNABLE_INT_FETCH("hw.lapic_enable", &enable);
650 kprintf("LAPIC: Warning LAPIC is disabled\n");
654 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
655 error = e->lapic_probe(e);
660 kprintf("LAPIC: Can't find LAPIC\n");
664 e->lapic_enumerate(e);
667 TUNABLE_INT_FETCH("hw.ap_max", &ap_max);
668 if (ap_max > MAXCPU - 1)
671 if (mp_naps > ap_max) {
672 kprintf("LAPIC: Warning use only %d out of %d "
678 if ((cpu_feature2 & CPUID2_VMM) && mp_naps == 0) {
681 * Special hack for vmware. It looks like that
682 * if only one CPU is configured (mp_naps == 0)
683 * in vmware (cpu_feature2 & CPUID2_VMM),
684 * then LAPIC will not work at all.
686 kprintf("LAPIC: single CPU virtual machine detected, "
694 lapic_enumerator_register(struct lapic_enumerator *ne)
696 struct lapic_enumerator *e;
698 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
699 if (e->lapic_prio < ne->lapic_prio) {
700 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
704 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);
708 lapic_set_cpuid(int cpu_id, int apic_id)
710 CPUID_TO_APICID(cpu_id) = apic_id;
711 APICID_TO_CPUID(apic_id) = cpu_id;
715 lapic_fixup_noioapic(void)
719 /* Only allowed on BSP */
720 KKASSERT(mycpuid == 0);
721 KKASSERT(!ioapic_enable);
723 temp = lapic->lvt_lint0;
724 temp &= ~APIC_LVT_MASKED;
725 lapic->lvt_lint0 = temp;
727 temp = lapic->lvt_lint1;
728 temp |= APIC_LVT_MASKED;
729 lapic->lvt_lint1 = temp;