2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
40 #include <sys/mplock2.h>
43 #include <vm/vm_param.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
48 #include <vm/vm_map.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine_base/apic/mpapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
65 #include <machine/md_var.h> /* setidt() */
66 #include <machine_base/icu/icu.h> /* IPIs */
67 #include <machine_base/isa/intr_machdep.h> /* IPIs */
69 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
71 #define WARMBOOT_TARGET 0
72 #define WARMBOOT_OFF (KERNBASE + 0x0467)
73 #define WARMBOOT_SEG (KERNBASE + 0x0469)
75 #define BIOS_BASE (0xf0000)
76 #define BIOS_SIZE (0x10000)
77 #define BIOS_COUNT (BIOS_SIZE/4)
79 #define CMOS_REG (0x70)
80 #define CMOS_DATA (0x71)
81 #define BIOS_RESET (0x0f)
82 #define BIOS_WARM (0x0a)
84 #define PROCENTRY_FLAG_EN 0x01
85 #define PROCENTRY_FLAG_BP 0x02
86 #define IOAPICENTRY_FLAG_EN 0x01
89 /* MP Floating Pointer Structure */
90 typedef struct MPFPS {
103 /* MP Configuration Table Header */
104 typedef struct MPCTH {
106 u_short base_table_length;
110 u_char product_id[12];
111 u_int32_t oem_table_pointer;
112 u_short oem_table_size;
114 u_int32_t apic_address;
115 u_short extended_table_length;
116 u_char extended_table_checksum;
121 typedef struct PROCENTRY {
126 u_int32_t cpu_signature;
127 u_int32_t feature_flags;
132 typedef struct BUSENTRY {
138 typedef struct IOAPICENTRY {
143 u_int32_t apic_address;
144 } *io_apic_entry_ptr;
146 typedef struct INTENTRY {
156 /* descriptions of MP basetable entries */
157 typedef struct BASETABLE_ENTRY {
164 * this code MUST be enabled here and in mpboot.s.
165 * it follows the very early stages of AP boot by placing values in CMOS ram.
166 * it NORMALLY will never be needed and thus the primitive method for enabling.
169 #if defined(CHECK_POINTS)
170 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
171 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
173 #define CHECK_INIT(D); \
174 CHECK_WRITE(0x34, (D)); \
175 CHECK_WRITE(0x35, (D)); \
176 CHECK_WRITE(0x36, (D)); \
177 CHECK_WRITE(0x37, (D)); \
178 CHECK_WRITE(0x38, (D)); \
179 CHECK_WRITE(0x39, (D));
181 #define CHECK_PRINT(S); \
182 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
191 #else /* CHECK_POINTS */
193 #define CHECK_INIT(D)
194 #define CHECK_PRINT(S)
196 #endif /* CHECK_POINTS */
199 * Values to send to the POST hardware.
201 #define MP_BOOTADDRESS_POST 0x10
202 #define MP_PROBE_POST 0x11
203 #define MPTABLE_PASS1_POST 0x12
205 #define MP_START_POST 0x13
206 #define MP_ENABLE_POST 0x14
207 #define MPTABLE_PASS2_POST 0x15
209 #define START_ALL_APS_POST 0x16
210 #define INSTALL_AP_TRAMP_POST 0x17
211 #define START_AP_POST 0x18
213 #define MP_ANNOUNCE_POST 0x19
215 static int need_hyperthreading_fixup;
216 static u_int logical_cpus;
217 u_int logical_cpus_mask;
219 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
220 int current_postcode;
222 /** XXX FIXME: what system files declare these??? */
223 extern struct region_descriptor r_gdt, r_idt;
225 int bsp_apic_ready = 0; /* flags useability of BSP apic */
226 int mp_naps; /* # of Applications processors */
227 int mp_nbusses; /* # of busses */
229 int mp_napics; /* # of IO APICs */
231 int boot_cpu_id; /* designated BSP */
232 vm_offset_t cpu_apic_address;
234 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
235 u_int32_t *io_apic_versions;
239 u_int32_t cpu_apic_versions[MAXCPU];
241 extern int64_t tsc_offsets[];
244 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
248 * APIC ID logical/physical mapping structures.
249 * We oversize these to simplify boot-time config.
251 int cpu_num_to_apic_id[NAPICID];
253 int io_num_to_apic_id[NAPICID];
255 int apic_id_to_logical[NAPICID];
257 /* AP uses this during bootstrap. Do not staticize. */
262 * SMP page table page. Setup by locore to point to a page table
263 * page from which we allocate per-cpu privatespace areas io_apics,
267 #define IO_MAPPING_START_INDEX \
268 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
270 extern pt_entry_t *SMPpt;
272 struct pcb stoppcbs[MAXCPU];
274 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
277 * Local data and functions.
280 static int mp_capable;
281 static u_int boot_address;
282 static u_int base_memory;
283 static int mp_finish;
285 static mpfps_t mpfps;
286 static long search_for_sig(u_int32_t target, int count);
287 static void mp_enable(u_int boot_addr);
289 static void mptable_hyperthread_fixup(u_int id_mask);
290 static void mptable_pass1(void);
291 static int mptable_pass2(void);
292 static void default_mp_table(int type);
293 static void fix_mp_table(void);
295 static void setup_apic_irq_mapping(void);
296 static int apic_int_is_bus_type(int intr, int bus_type);
298 static int start_all_aps(u_int boot_addr);
300 static void install_ap_tramp(u_int boot_addr);
302 static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
304 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
305 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
306 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
307 static u_int bootMP_size;
310 * Calculate usable address in base memory for AP trampoline code.
313 mp_bootaddress(u_int basemem)
315 POSTCODE(MP_BOOTADDRESS_POST);
317 base_memory = basemem;
319 bootMP_size = mptramp_end - mptramp_start;
320 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
321 if (((basemem * 1024) - boot_address) < bootMP_size)
322 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
323 /* 3 levels of page table pages */
324 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
326 return mptramp_pagetables;
331 * Look for an Intel MP spec table (ie, SMP capable hardware).
341 * Make sure our SMPpt[] page table is big enough to hold all the
344 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
346 POSTCODE(MP_PROBE_POST);
348 /* see if EBDA exists */
349 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
350 /* search first 1K of EBDA */
351 target = (u_int32_t) (segment << 4);
352 if ((x = search_for_sig(target, 1024 / 4)) != -1L)
355 /* last 1K of base memory, effective 'top of base' passed in */
356 target = (u_int32_t) (base_memory - 0x400);
357 if ((x = search_for_sig(target, 1024 / 4)) != -1L)
361 /* search the BIOS */
362 target = (u_int32_t) BIOS_BASE;
363 if ((x = search_for_sig(target, BIOS_COUNT)) != -1L)
373 * Calculate needed resources. We can safely map physical
374 * memory into SMPpt after mptable_pass1() completes.
379 /* flag fact that we are running multiple processors */
386 * Startup the SMP processors.
391 POSTCODE(MP_START_POST);
393 /* look for MP capable motherboard */
395 mp_enable(boot_address);
397 panic("MP hardware not found!");
402 * Print various information about the SMP system hardware and setup.
409 POSTCODE(MP_ANNOUNCE_POST);
411 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
412 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
413 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
414 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
415 for (x = 1; x <= mp_naps; ++x) {
416 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
417 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
418 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
422 for (x = 0; x < mp_napics; ++x) {
423 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
424 kprintf(", version: 0x%08x", io_apic_versions[x]);
425 kprintf(", at 0x%08lx\n", io_apic_address[x]);
428 kprintf(" Warning: APIC I/O disabled\n");
433 * AP cpu's call this to sync up protected mode.
435 * WARNING! %gs is not set up on entry. This routine sets up %gs.
441 int x, myid = bootAP;
443 struct mdglobaldata *md;
444 struct privatespace *ps;
446 ps = &CPU_prvspace[myid];
448 gdt_segs[GPROC0_SEL].ssd_base =
449 (long) &ps->mdglobaldata.gd_common_tss;
450 ps->mdglobaldata.mi.gd_prvspace = ps;
452 /* We fill the 32-bit segment descriptors */
453 for (x = 0; x < NGDT; x++) {
454 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
455 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
457 /* And now a 64-bit one */
458 ssdtosyssd(&gdt_segs[GPROC0_SEL],
459 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
461 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
462 r_gdt.rd_base = (long) &gdt[myid * NGDT];
463 lgdt(&r_gdt); /* does magic intra-segment return */
465 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
466 wrmsr(MSR_FSBASE, 0); /* User value */
467 wrmsr(MSR_GSBASE, (u_int64_t)ps);
468 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
474 mdcpu->gd_currentldt = _default_ldt;
477 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
478 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
480 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
482 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
484 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
486 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
487 md->gd_common_tssd = *md->gd_tss_gdt;
489 md->gd_common_tss.tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
494 * Set to a known state:
495 * Set by mpboot.s: CR0_PG, CR0_PE
496 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
499 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
502 /* Set up the fast syscall stuff */
503 msr = rdmsr(MSR_EFER) | EFER_SCE;
504 wrmsr(MSR_EFER, msr);
505 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
506 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
507 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
508 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
509 wrmsr(MSR_STAR, msr);
510 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
512 pmap_set_opt(); /* PSE/4MB pages, etc */
514 /* Initialize the PAT MSR. */
518 /* set up CPU registers and state */
521 /* set up SSE/NX registers */
524 /* set up FPU state on the AP */
525 npxinit(__INITIAL_NPXCW__);
527 /* disable the APIC, just to be SURE */
528 lapic->svr &= ~APIC_SVR_ENABLE;
530 /* data returned to BSP */
531 cpu_apic_versions[0] = lapic->version;
534 /*******************************************************************
535 * local functions and data
539 * start the SMP system
542 mp_enable(u_int boot_addr)
550 POSTCODE(MP_ENABLE_POST);
553 /* turn on 4MB of V == P addressing so we can get to MP table */
554 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
558 /* examine the MP table for needed info, uses physical addresses */
566 /* can't process default configs till the CPU APIC is pmapped */
570 /* post scan cleanup */
575 setup_apic_irq_mapping();
577 /* fill the LOGICAL io_apic_versions table */
578 for (apic = 0; apic < mp_napics; ++apic) {
579 ux = io_apic_read(apic, IOAPIC_VER);
580 io_apic_versions[apic] = ux;
581 io_apic_set_id(apic, IO_TO_ID(apic));
584 /* program each IO APIC in the system */
585 for (apic = 0; apic < mp_napics; ++apic)
586 if (io_apic_setup(apic) < 0)
587 panic("IO APIC setup failure");
592 * These are required for SMP operation
595 /* install a 'Spurious INTerrupt' vector */
596 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
597 SDT_SYSIGT, SEL_KPL, 0);
599 /* install an inter-CPU IPI for TLB invalidation */
600 setidt(XINVLTLB_OFFSET, Xinvltlb,
601 SDT_SYSIGT, SEL_KPL, 0);
603 /* install an inter-CPU IPI for IPIQ messaging */
604 setidt(XIPIQ_OFFSET, Xipiq,
605 SDT_SYSIGT, SEL_KPL, 0);
607 /* install a timer vector */
608 setidt(XTIMER_OFFSET, Xtimer,
609 SDT_SYSIGT, SEL_KPL, 0);
611 /* install an inter-CPU IPI for CPU stop/restart */
612 setidt(XCPUSTOP_OFFSET, Xcpustop,
613 SDT_SYSIGT, SEL_KPL, 0);
615 /* start each Application Processor */
616 start_all_aps(boot_addr);
621 * look for the MP spec signature
624 /* string defined by the Intel MP Spec as identifying the MP table */
625 #define MP_SIG 0x5f504d5f /* _MP_ */
626 #define NEXT(X) ((X) += 4)
628 search_for_sig(u_int32_t target, int count)
631 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
633 for (x = 0; x < count; NEXT(x))
634 if (addr[x] == MP_SIG)
635 /* make array index a byte index */
636 return (long)(&addr[x]);
642 static basetable_entry basetable_entry_types[] =
644 {0, 20, "Processor"},
651 typedef struct BUSDATA {
653 enum busTypes bus_type;
656 typedef struct INTDATA {
666 typedef struct BUSTYPENAME {
671 static bus_type_name bus_type_table[] =
677 {UNKNOWN_BUSTYPE, "---"},
680 {UNKNOWN_BUSTYPE, "---"},
681 {UNKNOWN_BUSTYPE, "---"},
682 {UNKNOWN_BUSTYPE, "---"},
683 {UNKNOWN_BUSTYPE, "---"},
684 {UNKNOWN_BUSTYPE, "---"},
686 {UNKNOWN_BUSTYPE, "---"},
687 {UNKNOWN_BUSTYPE, "---"},
688 {UNKNOWN_BUSTYPE, "---"},
689 {UNKNOWN_BUSTYPE, "---"},
691 {UNKNOWN_BUSTYPE, "---"}
693 /* from MP spec v1.4, table 5-1 */
694 static int default_data[7][5] =
696 /* nbus, id0, type0, id1, type1 */
697 {1, 0, ISA, 255, 255},
698 {1, 0, EISA, 255, 255},
699 {1, 0, EISA, 255, 255},
700 {1, 0, MCA, 255, 255},
702 {2, 0, EISA, 1, PCI},
708 static bus_datum *bus_data;
711 /* the IO INT data, one entry per possible APIC INTerrupt */
712 static io_int *io_apic_ints;
716 static int processor_entry (proc_entry_ptr entry, int cpu);
717 static int bus_entry (bus_entry_ptr entry, int bus);
719 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
720 static int int_entry (int_entry_ptr entry, int intr);
722 static int lookup_bus_type (char *name);
726 * 1st pass on motherboard's Intel MP specification table.
732 * cpu_apic_address (common to all CPUs)
752 POSTCODE(MPTABLE_PASS1_POST);
755 /* clear various tables */
756 for (x = 0; x < NAPICID; ++x) {
757 io_apic_address[x] = ~0; /* IO APIC address table */
761 /* init everything to empty */
770 /* check for use of 'default' configuration */
771 if (mpfps->mpfb1 != 0) {
772 /* use default addresses */
773 cpu_apic_address = DEFAULT_APIC_BASE;
775 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
778 /* fill in with defaults */
779 mp_naps = 2; /* includes BSP */
780 mp_nbusses = default_data[mpfps->mpfb1 - 1][0];
788 panic("MP Configuration Table Header MISSING!");
789 cth = (void *)PHYS_TO_DMAP(mpfps->pap);
791 cpu_apic_address = (vm_offset_t) cth->apic_address;
793 /* walk the table, recording info of interest */
794 totalSize = cth->base_table_length - sizeof(struct MPCTH);
795 position = (u_char *) cth + sizeof(struct MPCTH);
796 count = cth->entry_count;
799 switch (type = *(u_char *) position) {
800 case 0: /* processor_entry */
801 if (((proc_entry_ptr)position)->cpu_flags
802 & PROCENTRY_FLAG_EN) {
805 ((proc_entry_ptr)position)->apic_id;
808 case 1: /* bus_entry */
811 case 2: /* io_apic_entry */
813 if (((io_apic_entry_ptr)position)->apic_flags
814 & IOAPICENTRY_FLAG_EN)
815 io_apic_address[mp_napics++] =
816 (vm_offset_t)((io_apic_entry_ptr)
817 position)->apic_address;
820 case 3: /* int_entry */
825 case 4: /* int_entry */
828 panic("mpfps Base Table HOSED!");
832 totalSize -= basetable_entry_types[type].length;
833 position = (uint8_t *)position +
834 basetable_entry_types[type].length;
838 /* qualify the numbers */
839 if (mp_naps > MAXCPU) {
840 kprintf("Warning: only using %d of %d available CPUs!\n",
845 /* See if we need to fixup HT logical CPUs. */
846 mptable_hyperthread_fixup(id_mask);
850 * This is also used as a counter while starting the APs.
854 --mp_naps; /* subtract the BSP */
859 * 2nd pass on motherboard's Intel MP specification table.
863 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
864 * CPU_TO_ID(N), logical CPU to APIC ID table
865 * IO_TO_ID(N), logical IO to APIC ID table
872 struct PROCENTRY proc;
879 int apic, bus, cpu, intr;
882 POSTCODE(MPTABLE_PASS2_POST);
884 /* Initialize fake proc entry for use with HT fixup. */
885 bzero(&proc, sizeof(proc));
887 proc.cpu_flags = PROCENTRY_FLAG_EN;
890 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
892 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
893 M_DEVBUF, M_WAITOK | M_ZERO);
894 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
897 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
901 for (i = 0; i < mp_napics; i++) {
902 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
906 /* clear various tables */
907 for (x = 0; x < NAPICID; ++x) {
908 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
910 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
911 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
915 /* clear bus data table */
916 for (x = 0; x < mp_nbusses; ++x)
917 bus_data[x].bus_id = 0xff;
920 /* clear IO APIC INT table */
921 for (x = 0; x < (nintrs + 1); ++x) {
922 io_apic_ints[x].int_type = 0xff;
923 io_apic_ints[x].int_vector = 0xff;
927 /* setup the cpu/apic mapping arrays */
930 /* record whether PIC or virtual-wire mode */
931 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, mpfps->mpfb2 & 0x80);
933 /* check for use of 'default' configuration */
934 if (mpfps->mpfb1 != 0)
935 return mpfps->mpfb1; /* return default configuration type */
938 panic("MP Configuration Table Header MISSING!");
940 cth = (void *)PHYS_TO_DMAP(mpfps->pap);
941 /* walk the table, recording info of interest */
942 totalSize = cth->base_table_length - sizeof(struct MPCTH);
943 position = (u_char *) cth + sizeof(struct MPCTH);
944 count = cth->entry_count;
945 apic = bus = intr = 0;
946 cpu = 1; /* pre-count the BSP */
949 switch (type = *(u_char *) position) {
951 if (processor_entry(position, cpu))
954 if (need_hyperthreading_fixup) {
956 * Create fake mptable processor entries
957 * and feed them to processor_entry() to
958 * enumerate the logical CPUs.
960 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
961 for (i = 1; i < logical_cpus; i++) {
963 processor_entry(&proc, cpu);
964 logical_cpus_mask |= (1 << cpu);
970 if (bus_entry(position, bus))
975 if (io_apic_entry(position, apic))
981 if (int_entry(position, intr))
986 /* int_entry(position); */
989 panic("mpfps Base Table HOSED!");
993 totalSize -= basetable_entry_types[type].length;
994 position = (uint8_t *)position + basetable_entry_types[type].length;
997 if (boot_cpu_id == -1)
998 panic("NO BSP found!");
1000 /* report fact that its NOT a default configuration */
1005 * Check if we should perform a hyperthreading "fix-up" to
1006 * enumerate any logical CPU's that aren't already listed
1009 * XXX: We assume that all of the physical CPUs in the
1010 * system have the same number of logical CPUs.
1012 * XXX: We assume that APIC ID's are allocated such that
1013 * the APIC ID's for a physical processor are aligned
1014 * with the number of logical CPU's in the processor.
1017 mptable_hyperthread_fixup(u_int id_mask)
1021 /* Nothing to do if there is no HTT support. */
1022 if ((cpu_feature & CPUID_HTT) == 0)
1024 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1025 if (logical_cpus <= 1)
1029 * For each APIC ID of a CPU that is set in the mask,
1030 * scan the other candidate APIC ID's for this
1031 * physical processor. If any of those ID's are
1032 * already in the table, then kill the fixup.
1034 for (id = 0; id <= MAXCPU; id++) {
1035 if ((id_mask & 1 << id) == 0)
1037 /* First, make sure we are on a logical_cpus boundary. */
1038 if (id % logical_cpus != 0)
1040 for (i = id + 1; i < id + logical_cpus; i++)
1041 if ((id_mask & 1 << i) != 0)
1046 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1047 * mp_naps right now.
1049 need_hyperthreading_fixup = 1;
1050 mp_naps *= logical_cpus;
1056 assign_apic_irq(int apic, int intpin, int irq)
1060 if (int_to_apicintpin[irq].ioapic != -1)
1061 panic("assign_apic_irq: inconsistent table");
1063 int_to_apicintpin[irq].ioapic = apic;
1064 int_to_apicintpin[irq].int_pin = intpin;
1065 int_to_apicintpin[irq].apic_address = ioapic[apic];
1066 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1068 for (x = 0; x < nintrs; x++) {
1069 if ((io_apic_ints[x].int_type == 0 ||
1070 io_apic_ints[x].int_type == 3) &&
1071 io_apic_ints[x].int_vector == 0xff &&
1072 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1073 io_apic_ints[x].dst_apic_int == intpin)
1074 io_apic_ints[x].int_vector = irq;
1079 revoke_apic_irq(int irq)
1085 if (int_to_apicintpin[irq].ioapic == -1)
1086 panic("revoke_apic_irq: inconsistent table");
1088 oldapic = int_to_apicintpin[irq].ioapic;
1089 oldintpin = int_to_apicintpin[irq].int_pin;
1091 int_to_apicintpin[irq].ioapic = -1;
1092 int_to_apicintpin[irq].int_pin = 0;
1093 int_to_apicintpin[irq].apic_address = NULL;
1094 int_to_apicintpin[irq].redirindex = 0;
1096 for (x = 0; x < nintrs; x++) {
1097 if ((io_apic_ints[x].int_type == 0 ||
1098 io_apic_ints[x].int_type == 3) &&
1099 io_apic_ints[x].int_vector != 0xff &&
1100 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1101 io_apic_ints[x].dst_apic_int == oldintpin)
1102 io_apic_ints[x].int_vector = 0xff;
1110 allocate_apic_irq(int intr)
1116 if (io_apic_ints[intr].int_vector != 0xff)
1117 return; /* Interrupt handler already assigned */
1119 if (io_apic_ints[intr].int_type != 0 &&
1120 (io_apic_ints[intr].int_type != 3 ||
1121 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1122 io_apic_ints[intr].dst_apic_int == 0)))
1123 return; /* Not INT or ExtInt on != (0, 0) */
1126 while (irq < APIC_INTMAPSIZE &&
1127 int_to_apicintpin[irq].ioapic != -1)
1130 if (irq >= APIC_INTMAPSIZE)
1131 return; /* No free interrupt handlers */
1133 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1134 intpin = io_apic_ints[intr].dst_apic_int;
1136 assign_apic_irq(apic, intpin, irq);
1141 swap_apic_id(int apic, int oldid, int newid)
1148 return; /* Nothing to do */
1150 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1151 apic, oldid, newid);
1153 /* Swap physical APIC IDs in interrupt entries */
1154 for (x = 0; x < nintrs; x++) {
1155 if (io_apic_ints[x].dst_apic_id == oldid)
1156 io_apic_ints[x].dst_apic_id = newid;
1157 else if (io_apic_ints[x].dst_apic_id == newid)
1158 io_apic_ints[x].dst_apic_id = oldid;
1161 /* Swap physical APIC IDs in IO_TO_ID mappings */
1162 for (oapic = 0; oapic < mp_napics; oapic++)
1163 if (IO_TO_ID(oapic) == newid)
1166 if (oapic < mp_napics) {
1167 kprintf("Changing APIC ID for IO APIC #%d from "
1168 "%d to %d in MP table\n",
1169 oapic, newid, oldid);
1170 IO_TO_ID(oapic) = oldid;
1172 IO_TO_ID(apic) = newid;
1177 fix_id_to_io_mapping(void)
1181 for (x = 0; x < NAPICID; x++)
1184 for (x = 0; x <= mp_naps; x++)
1185 if (CPU_TO_ID(x) < NAPICID)
1186 ID_TO_IO(CPU_TO_ID(x)) = x;
1188 for (x = 0; x < mp_napics; x++)
1189 if (IO_TO_ID(x) < NAPICID)
1190 ID_TO_IO(IO_TO_ID(x)) = x;
1195 first_free_apic_id(void)
1199 for (freeid = 0; freeid < NAPICID; freeid++) {
1200 for (x = 0; x <= mp_naps; x++)
1201 if (CPU_TO_ID(x) == freeid)
1205 for (x = 0; x < mp_napics; x++)
1206 if (IO_TO_ID(x) == freeid)
1217 io_apic_id_acceptable(int apic, int id)
1219 int cpu; /* Logical CPU number */
1220 int oapic; /* Logical IO APIC number for other IO APIC */
1223 return 0; /* Out of range */
1225 for (cpu = 0; cpu <= mp_naps; cpu++)
1226 if (CPU_TO_ID(cpu) == id)
1227 return 0; /* Conflict with CPU */
1229 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1230 if (IO_TO_ID(oapic) == id)
1231 return 0; /* Conflict with other APIC */
1233 return 1; /* ID is acceptable for IO APIC */
1238 io_apic_find_int_entry(int apic, int pin)
1242 /* search each of the possible INTerrupt sources */
1243 for (x = 0; x < nintrs; ++x) {
1244 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1245 (pin == io_apic_ints[x].dst_apic_int))
1246 return (&io_apic_ints[x]);
1254 * parse an Intel MP specification table
1262 int apic; /* IO APIC unit number */
1263 int freeid; /* Free physical APIC ID */
1264 int physid; /* Current physical IO APIC ID */
1267 int bus_0 = 0; /* Stop GCC warning */
1268 int bus_pci = 0; /* Stop GCC warning */
1272 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1273 * did it wrong. The MP spec says that when more than 1 PCI bus
1274 * exists the BIOS must begin with bus entries for the PCI bus and use
1275 * actual PCI bus numbering. This implies that when only 1 PCI bus
1276 * exists the BIOS can choose to ignore this ordering, and indeed many
1277 * MP motherboards do ignore it. This causes a problem when the PCI
1278 * sub-system makes requests of the MP sub-system based on PCI bus
1279 * numbers. So here we look for the situation and renumber the
1280 * busses and associated INTs in an effort to "make it right".
1283 /* find bus 0, PCI bus, count the number of PCI busses */
1284 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1285 if (bus_data[x].bus_id == 0) {
1288 if (bus_data[x].bus_type == PCI) {
1294 * bus_0 == slot of bus with ID of 0
1295 * bus_pci == slot of last PCI bus encountered
1298 /* check the 1 PCI bus case for sanity */
1299 /* if it is number 0 all is well */
1300 if (num_pci_bus == 1 &&
1301 bus_data[bus_pci].bus_id != 0) {
1303 /* mis-numbered, swap with whichever bus uses slot 0 */
1305 /* swap the bus entry types */
1306 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1307 bus_data[bus_0].bus_type = PCI;
1310 /* swap each relavant INTerrupt entry */
1311 id = bus_data[bus_pci].bus_id;
1312 for (x = 0; x < nintrs; ++x) {
1313 if (io_apic_ints[x].src_bus_id == id) {
1314 io_apic_ints[x].src_bus_id = 0;
1316 else if (io_apic_ints[x].src_bus_id == 0) {
1317 io_apic_ints[x].src_bus_id = id;
1324 /* Assign IO APIC IDs.
1326 * First try the existing ID. If a conflict is detected, try
1327 * the ID in the MP table. If a conflict is still detected, find
1330 * We cannot use the ID_TO_IO table before all conflicts has been
1331 * resolved and the table has been corrected.
1333 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1335 /* First try to use the value set by the BIOS */
1336 physid = io_apic_get_id(apic);
1337 if (io_apic_id_acceptable(apic, physid)) {
1338 if (IO_TO_ID(apic) != physid)
1339 swap_apic_id(apic, IO_TO_ID(apic), physid);
1343 /* Then check if the value in the MP table is acceptable */
1344 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1347 /* Last resort, find a free APIC ID and use it */
1348 freeid = first_free_apic_id();
1349 if (freeid >= NAPICID)
1350 panic("No free physical APIC IDs found");
1352 if (io_apic_id_acceptable(apic, freeid)) {
1353 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1356 panic("Free physical APIC ID not usable");
1358 fix_id_to_io_mapping();
1362 /* detect and fix broken Compaq MP table */
1363 if (apic_int_type(0, 0) == -1) {
1364 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1365 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1366 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1367 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1368 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1369 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1371 } else if (apic_int_type(0, 0) == 0) {
1372 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1373 for (x = 0; x < nintrs; ++x)
1374 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1375 (0 == io_apic_ints[x].dst_apic_int)) {
1376 io_apic_ints[x].int_type = 3;
1377 io_apic_ints[x].int_vector = 0xff;
1383 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1384 * controllers universally come in pairs. If IRQ 14 is specified
1385 * as an ISA interrupt, then IRQ 15 had better be too.
1387 * [ Shuttle XPC / AMD Athlon X2 ]
1388 * The MPTable is missing an entry for IRQ 15. Note that the
1389 * ACPI table has an entry for both 14 and 15.
1391 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1392 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1393 io14 = io_apic_find_int_entry(0, 14);
1394 io_apic_ints[nintrs] = *io14;
1395 io_apic_ints[nintrs].src_bus_irq = 15;
1396 io_apic_ints[nintrs].dst_apic_int = 15;
1404 /* Assign low level interrupt handlers */
1406 setup_apic_irq_mapping(void)
1412 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1413 int_to_apicintpin[x].ioapic = -1;
1414 int_to_apicintpin[x].int_pin = 0;
1415 int_to_apicintpin[x].apic_address = NULL;
1416 int_to_apicintpin[x].redirindex = 0;
1419 /* First assign ISA/EISA interrupts */
1420 for (x = 0; x < nintrs; x++) {
1421 int_vector = io_apic_ints[x].src_bus_irq;
1422 if (int_vector < APIC_INTMAPSIZE &&
1423 io_apic_ints[x].int_vector == 0xff &&
1424 int_to_apicintpin[int_vector].ioapic == -1 &&
1425 (apic_int_is_bus_type(x, ISA) ||
1426 apic_int_is_bus_type(x, EISA)) &&
1427 io_apic_ints[x].int_type == 0) {
1428 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1429 io_apic_ints[x].dst_apic_int,
1434 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1435 for (x = 0; x < nintrs; x++) {
1436 if (io_apic_ints[x].dst_apic_int == 0 &&
1437 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1438 io_apic_ints[x].int_vector == 0xff &&
1439 int_to_apicintpin[0].ioapic == -1 &&
1440 io_apic_ints[x].int_type == 3) {
1441 assign_apic_irq(0, 0, 0);
1446 /* Assign PCI interrupts */
1447 for (x = 0; x < nintrs; ++x) {
1448 if (io_apic_ints[x].int_type == 0 &&
1449 io_apic_ints[x].int_vector == 0xff &&
1450 apic_int_is_bus_type(x, PCI))
1451 allocate_apic_irq(x);
1458 processor_entry(proc_entry_ptr entry, int cpu)
1460 /* check for usability */
1461 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1464 if(entry->apic_id >= NAPICID)
1465 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1466 /* check for BSP flag */
1467 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1468 boot_cpu_id = entry->apic_id;
1469 CPU_TO_ID(0) = entry->apic_id;
1470 ID_TO_CPU(entry->apic_id) = 0;
1471 return 0; /* its already been counted */
1474 /* add another AP to list, if less than max number of CPUs */
1475 else if (cpu < MAXCPU) {
1476 CPU_TO_ID(cpu) = entry->apic_id;
1477 ID_TO_CPU(entry->apic_id) = cpu;
1486 bus_entry(bus_entry_ptr entry, int bus)
1491 /* encode the name into an index */
1492 for (x = 0; x < 6; ++x) {
1493 if ((c = entry->bus_type[x]) == ' ')
1499 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1500 panic("unknown bus type: '%s'", name);
1502 bus_data[bus].bus_id = entry->bus_id;
1503 bus_data[bus].bus_type = x;
1511 io_apic_entry(io_apic_entry_ptr entry, int apic)
1513 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1516 IO_TO_ID(apic) = entry->apic_id;
1517 if (entry->apic_id < NAPICID)
1518 ID_TO_IO(entry->apic_id) = apic;
1526 lookup_bus_type(char *name)
1530 for (x = 0; x < MAX_BUSTYPE; ++x)
1531 if (strcmp(bus_type_table[x].name, name) == 0)
1532 return bus_type_table[x].type;
1534 return UNKNOWN_BUSTYPE;
1540 int_entry(int_entry_ptr entry, int intr)
1544 io_apic_ints[intr].int_type = entry->int_type;
1545 io_apic_ints[intr].int_flags = entry->int_flags;
1546 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1547 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1548 if (entry->dst_apic_id == 255) {
1549 /* This signal goes to all IO APICS. Select an IO APIC
1550 with sufficient number of interrupt pins */
1551 for (apic = 0; apic < mp_napics; apic++)
1552 if (((io_apic_read(apic, IOAPIC_VER) &
1553 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1554 entry->dst_apic_int)
1556 if (apic < mp_napics)
1557 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1559 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1561 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1562 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1568 apic_int_is_bus_type(int intr, int bus_type)
1572 for (bus = 0; bus < mp_nbusses; ++bus)
1573 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1574 && ((int) bus_data[bus].bus_type == bus_type))
1581 * Given a traditional ISA INT mask, return an APIC mask.
1584 isa_apic_mask(u_int isa_mask)
1589 #if defined(SKIP_IRQ15_REDIRECT)
1590 if (isa_mask == (1 << 15)) {
1591 kprintf("skipping ISA IRQ15 redirect\n");
1594 #endif /* SKIP_IRQ15_REDIRECT */
1596 isa_irq = ffs(isa_mask); /* find its bit position */
1597 if (isa_irq == 0) /* doesn't exist */
1599 --isa_irq; /* make it zero based */
1601 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1605 return (1 << apic_pin); /* convert pin# to a mask */
1609 * Determine which APIC pin an ISA/EISA INT is attached to.
1611 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1612 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1613 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1614 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1616 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1618 isa_apic_irq(int isa_irq)
1622 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1623 if (INTTYPE(intr) == 0) { /* standard INT */
1624 if (SRCBUSIRQ(intr) == isa_irq) {
1625 if (apic_int_is_bus_type(intr, ISA) ||
1626 apic_int_is_bus_type(intr, EISA)) {
1627 if (INTIRQ(intr) == 0xff)
1628 return -1; /* unassigned */
1629 return INTIRQ(intr); /* found */
1634 return -1; /* NOT found */
1639 * Determine which APIC pin a PCI INT is attached to.
1641 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1642 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1643 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1645 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1649 --pciInt; /* zero based */
1651 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1652 if ((INTTYPE(intr) == 0) /* standard INT */
1653 && (SRCBUSID(intr) == pciBus)
1654 && (SRCBUSDEVICE(intr) == pciDevice)
1655 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1656 if (apic_int_is_bus_type(intr, PCI)) {
1657 if (INTIRQ(intr) == 0xff) {
1658 kprintf("IOAPIC: pci_apic_irq() "
1660 return -1; /* unassigned */
1662 return INTIRQ(intr); /* exact match */
1667 return -1; /* NOT found */
1671 next_apic_irq(int irq)
1678 for (intr = 0; intr < nintrs; intr++) {
1679 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1681 bus = SRCBUSID(intr);
1682 bustype = apic_bus_type(bus);
1683 if (bustype != ISA &&
1689 if (intr >= nintrs) {
1692 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1693 if (INTTYPE(ointr) != 0)
1695 if (bus != SRCBUSID(ointr))
1697 if (bustype == PCI) {
1698 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1700 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1703 if (bustype == ISA || bustype == EISA) {
1704 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1707 if (INTPIN(intr) == INTPIN(ointr))
1711 if (ointr >= nintrs) {
1714 return INTIRQ(ointr);
1729 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1732 * Exactly what this means is unclear at this point. It is a solution
1733 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1734 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1735 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1739 undirect_isa_irq(int rirq)
1743 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1744 /** FIXME: tickle the MB redirector chip */
1748 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1755 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1758 undirect_pci_irq(int rirq)
1762 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1764 /** FIXME: tickle the MB redirector chip */
1768 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1776 * given a bus ID, return:
1777 * the bus type if found
1781 apic_bus_type(int id)
1785 for (x = 0; x < mp_nbusses; ++x)
1786 if (bus_data[x].bus_id == id)
1787 return bus_data[x].bus_type;
1795 * given a LOGICAL APIC# and pin#, return:
1796 * the associated src bus ID if found
1800 apic_src_bus_id(int apic, int pin)
1804 /* search each of the possible INTerrupt sources */
1805 for (x = 0; x < nintrs; ++x)
1806 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1807 (pin == io_apic_ints[x].dst_apic_int))
1808 return (io_apic_ints[x].src_bus_id);
1810 return -1; /* NOT found */
1814 * given a LOGICAL APIC# and pin#, return:
1815 * the associated src bus IRQ if found
1819 apic_src_bus_irq(int apic, int pin)
1823 for (x = 0; x < nintrs; x++)
1824 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1825 (pin == io_apic_ints[x].dst_apic_int))
1826 return (io_apic_ints[x].src_bus_irq);
1828 return -1; /* NOT found */
1833 * given a LOGICAL APIC# and pin#, return:
1834 * the associated INTerrupt type if found
1838 apic_int_type(int apic, int pin)
1842 /* search each of the possible INTerrupt sources */
1843 for (x = 0; x < nintrs; ++x) {
1844 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1845 (pin == io_apic_ints[x].dst_apic_int))
1846 return (io_apic_ints[x].int_type);
1848 return -1; /* NOT found */
1852 * Return the IRQ associated with an APIC pin
1855 apic_irq(int apic, int pin)
1860 for (x = 0; x < nintrs; ++x) {
1861 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1862 (pin == io_apic_ints[x].dst_apic_int)) {
1863 res = io_apic_ints[x].int_vector;
1866 if (apic != int_to_apicintpin[res].ioapic)
1867 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1868 if (pin != int_to_apicintpin[res].int_pin)
1869 panic("apic_irq inconsistent table (2)");
1878 * given a LOGICAL APIC# and pin#, return:
1879 * the associated trigger mode if found
1883 apic_trigger(int apic, int pin)
1887 /* search each of the possible INTerrupt sources */
1888 for (x = 0; x < nintrs; ++x)
1889 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1890 (pin == io_apic_ints[x].dst_apic_int))
1891 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1893 return -1; /* NOT found */
1898 * given a LOGICAL APIC# and pin#, return:
1899 * the associated 'active' level if found
1903 apic_polarity(int apic, int pin)
1907 /* search each of the possible INTerrupt sources */
1908 for (x = 0; x < nintrs; ++x)
1909 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1910 (pin == io_apic_ints[x].dst_apic_int))
1911 return (io_apic_ints[x].int_flags & 0x03);
1913 return -1; /* NOT found */
1919 * set data according to MP defaults
1920 * FIXME: probably not complete yet...
1923 default_mp_table(int type)
1926 #if defined(APIC_IO)
1929 #endif /* APIC_IO */
1932 kprintf(" MP default config type: %d\n", type);
1935 kprintf(" bus: ISA, APIC: 82489DX\n");
1938 kprintf(" bus: EISA, APIC: 82489DX\n");
1941 kprintf(" bus: EISA, APIC: 82489DX\n");
1944 kprintf(" bus: MCA, APIC: 82489DX\n");
1947 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
1950 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
1953 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
1956 kprintf(" future type\n");
1962 boot_cpu_id = (lapic->id & APIC_ID_MASK) >> 24;
1963 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1966 CPU_TO_ID(0) = boot_cpu_id;
1967 ID_TO_CPU(boot_cpu_id) = 0;
1969 /* one and only AP */
1970 CPU_TO_ID(1) = ap_cpu_id;
1971 ID_TO_CPU(ap_cpu_id) = 1;
1973 #if defined(APIC_IO)
1974 /* one and only IO APIC */
1975 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1978 * sanity check, refer to MP spec section 3.6.6, last paragraph
1979 * necessary as some hardware isn't properly setting up the IO APIC
1981 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1982 if (io_apic_id != 2) {
1984 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1985 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1986 io_apic_set_id(0, 2);
1989 IO_TO_ID(0) = io_apic_id;
1990 ID_TO_IO(io_apic_id) = 0;
1991 #endif /* APIC_IO */
1993 /* fill out bus entries */
2002 bus_data[0].bus_id = default_data[type - 1][1];
2003 bus_data[0].bus_type = default_data[type - 1][2];
2004 bus_data[1].bus_id = default_data[type - 1][3];
2005 bus_data[1].bus_type = default_data[type - 1][4];
2008 /* case 4: case 7: MCA NOT supported */
2009 default: /* illegal/reserved */
2010 panic("BAD default MP config: %d", type);
2014 #if defined(APIC_IO)
2015 /* general cases from MP v1.4, table 5-2 */
2016 for (pin = 0; pin < 16; ++pin) {
2017 io_apic_ints[pin].int_type = 0;
2018 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2019 io_apic_ints[pin].src_bus_id = 0;
2020 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2021 io_apic_ints[pin].dst_apic_id = io_apic_id;
2022 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2025 /* special cases from MP v1.4, table 5-2 */
2027 io_apic_ints[2].int_type = 0xff; /* N/C */
2028 io_apic_ints[13].int_type = 0xff; /* N/C */
2029 #if !defined(APIC_MIXED_MODE)
2031 panic("sorry, can't support type 2 default yet");
2032 #endif /* APIC_MIXED_MODE */
2035 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2038 io_apic_ints[0].int_type = 0xff; /* N/C */
2040 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2041 #endif /* APIC_IO */
2045 * Map a physical memory address representing I/O into KVA. The I/O
2046 * block is assumed not to cross a page boundary.
2049 permanent_io_mapping(vm_paddr_t pa)
2051 KKASSERT(pa < 0x100000000LL);
2053 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
2057 * start each AP in our list
2060 start_all_aps(u_int boot_addr)
2062 vm_offset_t va = boot_address + KERNBASE;
2063 u_int64_t *pt4, *pt3, *pt2;
2066 u_char mpbiosreason;
2067 u_long mpbioswarmvec;
2068 struct mdglobaldata *gd;
2069 struct privatespace *ps;
2071 POSTCODE(START_ALL_APS_POST);
2073 /* Initialize BSP's local APIC */
2074 apic_initialize(TRUE);
2077 /* install the AP 1st level boot code */
2078 pmap_kenter(va, boot_address);
2079 cpu_invlpg((void *)va); /* JG XXX */
2080 bcopy(mptramp_start, (void *)va, bootMP_size);
2082 /* Locate the page tables, they'll be below the trampoline */
2083 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2084 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2085 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2087 /* Create the initial 1GB replicated page tables */
2088 for (i = 0; i < 512; i++) {
2089 /* Each slot of the level 4 pages points to the same level 3 page */
2090 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2091 pt4[i] |= PG_V | PG_RW | PG_U;
2093 /* Each slot of the level 3 pages points to the same level 2 page */
2094 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2095 pt3[i] |= PG_V | PG_RW | PG_U;
2097 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2098 pt2[i] = i * (2 * 1024 * 1024);
2099 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2102 /* save the current value of the warm-start vector */
2103 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2104 outb(CMOS_REG, BIOS_RESET);
2105 mpbiosreason = inb(CMOS_DATA);
2107 /* setup a vector to our boot code */
2108 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2109 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2110 outb(CMOS_REG, BIOS_RESET);
2111 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2114 for (x = 1; x <= mp_naps; ++x) {
2116 /* This is a bit verbose, it will go away soon. */
2118 /* first page of AP's private space */
2119 pg = x * x86_64_btop(sizeof(struct privatespace));
2121 /* allocate new private data page(s) */
2122 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2123 MDGLOBALDATA_BASEALLOC_SIZE);
2125 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2126 bzero(gd, sizeof(*gd));
2127 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2129 /* prime data page for it to use */
2130 mi_gdinit(&gd->mi, x);
2132 gd->gd_CMAP1 = &SMPpt[pg + 0];
2133 gd->gd_CMAP2 = &SMPpt[pg + 1];
2134 gd->gd_CMAP3 = &SMPpt[pg + 2];
2135 gd->gd_PMAP1 = &SMPpt[pg + 3];
2136 gd->gd_CADDR1 = ps->CPAGE1;
2137 gd->gd_CADDR2 = ps->CPAGE2;
2138 gd->gd_CADDR3 = ps->CPAGE3;
2139 gd->gd_PADDR1 = (pt_entry_t *)ps->PPAGE1;
2140 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2141 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2143 /* setup a vector to our boot code */
2144 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2145 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2146 outb(CMOS_REG, BIOS_RESET);
2147 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2150 * Setup the AP boot stack
2152 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2155 /* attempt to start the Application Processor */
2156 CHECK_INIT(99); /* setup checkpoints */
2157 if (!start_ap(gd, boot_addr)) {
2158 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2159 CHECK_PRINT("trace"); /* show checkpoints */
2160 /* better panic as the AP may be running loose */
2161 kprintf("panic y/n? [y] ");
2162 if (cngetc() != 'n')
2165 CHECK_PRINT("trace"); /* show checkpoints */
2167 /* record its version info */
2168 cpu_apic_versions[x] = cpu_apic_versions[0];
2171 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2174 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2175 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2178 ncpus2_shift = shift;
2179 ncpus2 = 1 << shift;
2180 ncpus2_mask = ncpus2 - 1;
2182 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2183 if ((1 << shift) < ncpus)
2185 ncpus_fit = 1 << shift;
2186 ncpus_fit_mask = ncpus_fit - 1;
2188 /* build our map of 'other' CPUs */
2189 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2190 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2191 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2193 /* fill in our (BSP) APIC version */
2194 cpu_apic_versions[0] = lapic->version;
2196 /* restore the warmstart vector */
2197 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2198 outb(CMOS_REG, BIOS_RESET);
2199 outb(CMOS_DATA, mpbiosreason);
2202 * NOTE! The idlestack for the BSP was setup by locore. Finish
2203 * up, clean out the P==V mapping we did earlier.
2206 for (x = 0; x < NKPT; x++)
2211 /* number of APs actually started */
2217 * load the 1st level AP boot code into base memory.
2220 /* targets for relocation */
2221 extern void bigJump(void);
2222 extern void bootCodeSeg(void);
2223 extern void bootDataSeg(void);
2224 extern void MPentry(void);
2225 extern u_int MP_GDT;
2226 extern u_int mp_gdtbase;
2231 install_ap_tramp(u_int boot_addr)
2234 int size = *(int *) ((u_long) & bootMP_size);
2235 u_char *src = (u_char *) ((u_long) bootMP);
2236 u_char *dst = (u_char *) boot_addr + KERNBASE;
2237 u_int boot_base = (u_int) bootMP;
2242 POSTCODE(INSTALL_AP_TRAMP_POST);
2244 for (x = 0; x < size; ++x)
2248 * modify addresses in code we just moved to basemem. unfortunately we
2249 * need fairly detailed info about mpboot.s for this to work. changes
2250 * to mpboot.s might require changes here.
2253 /* boot code is located in KERNEL space */
2254 dst = (u_char *) boot_addr + KERNBASE;
2256 /* modify the lgdt arg */
2257 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2258 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2260 /* modify the ljmp target for MPentry() */
2261 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2262 *dst32 = ((u_int) MPentry - KERNBASE);
2264 /* modify the target for boot code segment */
2265 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2266 dst8 = (u_int8_t *) (dst16 + 1);
2267 *dst16 = (u_int) boot_addr & 0xffff;
2268 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2270 /* modify the target for boot data segment */
2271 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2272 dst8 = (u_int8_t *) (dst16 + 1);
2273 *dst16 = (u_int) boot_addr & 0xffff;
2274 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2280 * this function starts the AP (application processor) identified
2281 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2282 * to accomplish this. This is necessary because of the nuances
2283 * of the different hardware we might encounter. It ain't pretty,
2284 * but it seems to work.
2286 * NOTE: eventually an AP gets to ap_init(), which is called just
2287 * before the AP goes into the LWKT scheduler's idle loop.
2290 start_ap(struct mdglobaldata *gd, u_int boot_addr)
2294 u_long icr_lo, icr_hi;
2296 POSTCODE(START_AP_POST);
2298 /* get the PHYSICAL APIC ID# */
2299 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2301 /* calculate the vector */
2302 vector = (boot_addr >> 12) & 0xff;
2304 /* Make sure the target cpu sees everything */
2308 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2309 * and running the target CPU. OR this INIT IPI might be latched (P5
2310 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2314 /* setup the address for the target AP */
2315 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2316 icr_hi |= (physical_cpu << 24);
2317 lapic->icr_hi = icr_hi;
2319 /* do an INIT IPI: assert RESET */
2320 icr_lo = lapic->icr_lo & 0xfff00000;
2321 lapic->icr_lo = icr_lo | 0x0000c500;
2323 /* wait for pending status end */
2324 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2327 /* do an INIT IPI: deassert RESET */
2328 lapic->icr_lo = icr_lo | 0x00008500;
2330 /* wait for pending status end */
2331 u_sleep(10000); /* wait ~10mS */
2332 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2336 * next we do a STARTUP IPI: the previous INIT IPI might still be
2337 * latched, (P5 bug) this 1st STARTUP would then terminate
2338 * immediately, and the previously started INIT IPI would continue. OR
2339 * the previous INIT IPI has already run. and this STARTUP IPI will
2340 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2344 /* do a STARTUP IPI */
2345 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2346 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2348 u_sleep(200); /* wait ~200uS */
2351 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2352 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2353 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2354 * recognized after hardware RESET or INIT IPI.
2357 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2358 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2360 u_sleep(200); /* wait ~200uS */
2362 /* wait for it to start, see ap_init() */
2363 set_apic_timer(5000000);/* == 5 seconds */
2364 while (read_apic_timer()) {
2365 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2366 return 1; /* return SUCCESS */
2368 return 0; /* return FAILURE */
2373 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2375 * If for some reason we were unable to start all cpus we cannot safely
2376 * use broadcast IPIs.
2382 if (smp_startup_mask == smp_active_mask) {
2383 all_but_self_ipi(XINVLTLB_OFFSET);
2385 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2386 APIC_DELMODE_FIXED);
2392 * When called the executing CPU will send an IPI to all other CPUs
2393 * requesting that they halt execution.
2395 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2397 * - Signals all CPUs in map to stop.
2398 * - Waits for each to stop.
2405 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2406 * from executing at same time.
2409 stop_cpus(u_int map)
2411 map &= smp_active_mask;
2413 /* send the Xcpustop IPI to all CPUs in map */
2414 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2416 while ((stopped_cpus & map) != map)
2424 * Called by a CPU to restart stopped CPUs.
2426 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2428 * - Signals all CPUs in map to restart.
2429 * - Waits for each to restart.
2437 restart_cpus(u_int map)
2439 /* signal other cpus to restart */
2440 started_cpus = map & smp_active_mask;
2442 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2449 * This is called once the mpboot code has gotten us properly relocated
2450 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2451 * and when it returns the scheduler will call the real cpu_idle() main
2452 * loop for the idlethread. Interrupts are disabled on entry and should
2453 * remain disabled at return.
2461 * Adjust smp_startup_mask to signal the BSP that we have started
2462 * up successfully. Note that we do not yet hold the BGL. The BSP
2463 * is waiting for our signal.
2465 * We can't set our bit in smp_active_mask yet because we are holding
2466 * interrupts physically disabled and remote cpus could deadlock
2467 * trying to send us an IPI.
2469 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2473 * Interlock for finalization. Wait until mp_finish is non-zero,
2474 * then get the MP lock.
2476 * Note: We are in a critical section.
2478 * Note: We have to synchronize td_mpcount to our desired MP state
2479 * before calling cpu_try_mplock().
2481 * Note: we are the idle thread, we can only spin.
2483 * Note: The load fence is memory volatile and prevents the compiler
2484 * from improperly caching mp_finish, and the cpu from improperly
2487 while (mp_finish == 0)
2489 ++curthread->td_mpcount;
2490 while (cpu_try_mplock() == 0)
2493 if (cpu_feature & CPUID_TSC) {
2495 * The BSP is constantly updating tsc0_offset, figure out the
2496 * relative difference to synchronize ktrdump.
2498 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2501 /* BSP may have changed PTD while we're waiting for the lock */
2504 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2508 /* Build our map of 'other' CPUs. */
2509 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2511 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2513 /* A quick check from sanity claus */
2514 apic_id = (apic_id_to_logical[(lapic->id & 0x0f000000) >> 24]);
2515 if (mycpu->gd_cpuid != apic_id) {
2516 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2517 kprintf("SMP: apic_id = %d\n", apic_id);
2519 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2521 panic("cpuid mismatch! boom!!");
2524 /* Initialize AP's local APIC for irq's */
2525 apic_initialize(FALSE);
2527 /* Set memory range attributes for this CPU to match the BSP */
2528 mem_range_AP_init();
2531 * Once we go active we must process any IPIQ messages that may
2532 * have been queued, because no actual IPI will occur until we
2533 * set our bit in the smp_active_mask. If we don't the IPI
2534 * message interlock could be left set which would also prevent
2537 * The idle loop doesn't expect the BGL to be held and while
2538 * lwkt_switch() normally cleans things up this is a special case
2539 * because we returning almost directly into the idle loop.
2541 * The idle thread is never placed on the runq, make sure
2542 * nothing we've done put it there.
2544 KKASSERT(curthread->td_mpcount == 1);
2545 smp_active_mask |= 1 << mycpu->gd_cpuid;
2548 * Enable interrupts here. idle_restore will also do it, but
2549 * doing it here lets us clean up any strays that got posted to
2550 * the CPU during the AP boot while we are still in a critical
2553 __asm __volatile("sti; pause; pause"::);
2554 mdcpu->gd_fpending = 0;
2556 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2557 lwkt_process_ipiq();
2560 * Releasing the mp lock lets the BSP finish up the SMP init
2563 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2567 * Get SMP fully working before we start initializing devices.
2575 kprintf("Finish MP startup\n");
2576 if (cpu_feature & CPUID_TSC)
2577 tsc0_offset = rdtsc();
2580 while (smp_active_mask != smp_startup_mask) {
2582 if (cpu_feature & CPUID_TSC)
2583 tsc0_offset = rdtsc();
2585 while (try_mplock() == 0)
2588 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2591 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2594 cpu_send_ipiq(int dcpu)
2596 if ((1 << dcpu) & smp_active_mask)
2597 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2600 #if 0 /* single_apic_ipi_passive() not working yet */
2602 * Returns 0 on failure, 1 on success
2605 cpu_send_ipiq_passive(int dcpu)
2608 if ((1 << dcpu) & smp_active_mask) {
2609 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2610 APIC_DELMODE_FIXED);