2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 #include "opt_ifpoll.h"
70 #include <sys/param.h>
72 #include <sys/endian.h>
73 #include <sys/interrupt.h>
74 #include <sys/kernel.h>
76 #include <sys/malloc.h>
80 #include <sys/serialize.h>
81 #include <sys/serialize2.h>
82 #include <sys/socket.h>
83 #include <sys/sockio.h>
84 #include <sys/sysctl.h>
85 #include <sys/systm.h>
88 #include <net/ethernet.h>
90 #include <net/if_arp.h>
91 #include <net/if_dl.h>
92 #include <net/if_media.h>
93 #include <net/ifq_var.h>
94 #include <net/toeplitz.h>
95 #include <net/toeplitz2.h>
96 #include <net/vlan/if_vlan_var.h>
97 #include <net/vlan/if_vlan_ether.h>
98 #include <net/if_poll.h>
100 #include <netinet/in_systm.h>
101 #include <netinet/in.h>
102 #include <netinet/ip.h>
103 #include <netinet/tcp.h>
104 #include <netinet/udp.h>
106 #include <bus/pci/pcivar.h>
107 #include <bus/pci/pcireg.h>
109 #include <dev/netif/ig_hal/e1000_api.h>
110 #include <dev/netif/ig_hal/e1000_82571.h>
111 #include <dev/netif/emx/if_emx.h>
116 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
118 if (sc->rss_debug >= lvl) \
119 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
121 #else /* !EMX_RSS_DEBUG */
122 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
123 #endif /* EMX_RSS_DEBUG */
125 #define EMX_NAME "Intel(R) PRO/1000 "
127 #define EMX_DEVICE(id) \
128 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
129 #define EMX_DEVICE_NULL { 0, 0, NULL }
131 static const struct emx_device {
136 EMX_DEVICE(82571EB_COPPER),
137 EMX_DEVICE(82571EB_FIBER),
138 EMX_DEVICE(82571EB_SERDES),
139 EMX_DEVICE(82571EB_SERDES_DUAL),
140 EMX_DEVICE(82571EB_SERDES_QUAD),
141 EMX_DEVICE(82571EB_QUAD_COPPER),
142 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
143 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
144 EMX_DEVICE(82571EB_QUAD_FIBER),
145 EMX_DEVICE(82571PT_QUAD_COPPER),
147 EMX_DEVICE(82572EI_COPPER),
148 EMX_DEVICE(82572EI_FIBER),
149 EMX_DEVICE(82572EI_SERDES),
153 EMX_DEVICE(82573E_IAMT),
156 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
157 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
158 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
159 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
164 EMX_DEVICE(PCH_LPT_I217_LM),
165 EMX_DEVICE(PCH_LPT_I217_V),
166 EMX_DEVICE(PCH_LPTLP_I218_LM),
167 EMX_DEVICE(PCH_LPTLP_I218_V),
169 /* required last entry */
173 static int emx_probe(device_t);
174 static int emx_attach(device_t);
175 static int emx_detach(device_t);
176 static int emx_shutdown(device_t);
177 static int emx_suspend(device_t);
178 static int emx_resume(device_t);
180 static void emx_init(void *);
181 static void emx_stop(struct emx_softc *);
182 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
183 static void emx_start(struct ifnet *, struct ifaltq_subque *);
185 static void emx_npoll(struct ifnet *, struct ifpoll_info *);
186 static void emx_npoll_status(struct ifnet *);
187 static void emx_npoll_tx(struct ifnet *, void *, int);
188 static void emx_npoll_rx(struct ifnet *, void *, int);
190 static void emx_watchdog(struct ifaltq_subque *);
191 static void emx_media_status(struct ifnet *, struct ifmediareq *);
192 static int emx_media_change(struct ifnet *);
193 static void emx_timer(void *);
194 static void emx_serialize(struct ifnet *, enum ifnet_serialize);
195 static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
196 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
198 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
202 static void emx_intr(void *);
203 static void emx_intr_mask(void *);
204 static void emx_intr_body(struct emx_softc *, boolean_t);
205 static void emx_rxeof(struct emx_rxdata *, int);
206 static void emx_txeof(struct emx_txdata *);
207 static void emx_tx_collect(struct emx_txdata *);
208 static void emx_tx_purge(struct emx_softc *);
209 static void emx_enable_intr(struct emx_softc *);
210 static void emx_disable_intr(struct emx_softc *);
212 static int emx_dma_alloc(struct emx_softc *);
213 static void emx_dma_free(struct emx_softc *);
214 static void emx_init_tx_ring(struct emx_txdata *);
215 static int emx_init_rx_ring(struct emx_rxdata *);
216 static void emx_free_tx_ring(struct emx_txdata *);
217 static void emx_free_rx_ring(struct emx_rxdata *);
218 static int emx_create_tx_ring(struct emx_txdata *);
219 static int emx_create_rx_ring(struct emx_rxdata *);
220 static void emx_destroy_tx_ring(struct emx_txdata *, int);
221 static void emx_destroy_rx_ring(struct emx_rxdata *, int);
222 static int emx_newbuf(struct emx_rxdata *, int, int);
223 static int emx_encap(struct emx_txdata *, struct mbuf **, int *, int *);
224 static int emx_txcsum(struct emx_txdata *, struct mbuf *,
225 uint32_t *, uint32_t *);
226 static int emx_tso_pullup(struct emx_txdata *, struct mbuf **);
227 static int emx_tso_setup(struct emx_txdata *, struct mbuf *,
228 uint32_t *, uint32_t *);
229 static int emx_get_txring_inuse(const struct emx_softc *, boolean_t);
231 static int emx_is_valid_eaddr(const uint8_t *);
232 static int emx_reset(struct emx_softc *);
233 static void emx_setup_ifp(struct emx_softc *);
234 static void emx_init_tx_unit(struct emx_softc *);
235 static void emx_init_rx_unit(struct emx_softc *);
236 static void emx_update_stats(struct emx_softc *);
237 static void emx_set_promisc(struct emx_softc *);
238 static void emx_disable_promisc(struct emx_softc *);
239 static void emx_set_multi(struct emx_softc *);
240 static void emx_update_link_status(struct emx_softc *);
241 static void emx_smartspeed(struct emx_softc *);
242 static void emx_set_itr(struct emx_softc *, uint32_t);
243 static void emx_disable_aspm(struct emx_softc *);
245 static void emx_print_debug_info(struct emx_softc *);
246 static void emx_print_nvm_info(struct emx_softc *);
247 static void emx_print_hw_stats(struct emx_softc *);
249 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
250 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
251 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
252 static int emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
253 static int emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
255 static int emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
256 static int emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
258 static void emx_add_sysctl(struct emx_softc *);
260 static void emx_serialize_skipmain(struct emx_softc *);
261 static void emx_deserialize_skipmain(struct emx_softc *);
263 /* Management and WOL Support */
264 static void emx_get_mgmt(struct emx_softc *);
265 static void emx_rel_mgmt(struct emx_softc *);
266 static void emx_get_hw_control(struct emx_softc *);
267 static void emx_rel_hw_control(struct emx_softc *);
268 static void emx_enable_wol(device_t);
270 static device_method_t emx_methods[] = {
271 /* Device interface */
272 DEVMETHOD(device_probe, emx_probe),
273 DEVMETHOD(device_attach, emx_attach),
274 DEVMETHOD(device_detach, emx_detach),
275 DEVMETHOD(device_shutdown, emx_shutdown),
276 DEVMETHOD(device_suspend, emx_suspend),
277 DEVMETHOD(device_resume, emx_resume),
281 static driver_t emx_driver = {
284 sizeof(struct emx_softc),
287 static devclass_t emx_devclass;
289 DECLARE_DUMMY_MODULE(if_emx);
290 MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
291 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
296 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
297 static int emx_rxd = EMX_DEFAULT_RXD;
298 static int emx_txd = EMX_DEFAULT_TXD;
299 static int emx_smart_pwr_down = 0;
300 static int emx_rxr = 0;
301 static int emx_txr = 1;
303 /* Controls whether promiscuous also shows bad packets */
304 static int emx_debug_sbp = 0;
306 static int emx_82573_workaround = 1;
307 static int emx_msi_enable = 1;
309 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
310 TUNABLE_INT("hw.emx.rxd", &emx_rxd);
311 TUNABLE_INT("hw.emx.rxr", &emx_rxr);
312 TUNABLE_INT("hw.emx.txd", &emx_txd);
313 TUNABLE_INT("hw.emx.txr", &emx_txr);
314 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
315 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
316 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
317 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
319 /* Global used in WOL setup with multiport cards */
320 static int emx_global_quad_port_a = 0;
322 /* Set this to one to display debug statistics */
323 static int emx_display_debug_stats = 0;
325 #if !defined(KTR_IF_EMX)
326 #define KTR_IF_EMX KTR_ALL
328 KTR_INFO_MASTER(if_emx);
329 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
330 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
331 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
332 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
333 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
334 #define logif(name) KTR_LOG(if_emx_ ## name)
337 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
339 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
340 /* DD bit must be cleared */
341 rxd->rxd_staterr = 0;
345 emx_rxcsum(uint32_t staterr, struct mbuf *mp)
347 /* Ignore Checksum bit is set */
348 if (staterr & E1000_RXD_STAT_IXSM)
351 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
353 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
355 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
356 E1000_RXD_STAT_TCPCS) {
357 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
359 CSUM_FRAG_NOT_CHECKED;
360 mp->m_pkthdr.csum_data = htons(0xffff);
364 static __inline struct pktinfo *
365 emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
366 uint32_t mrq, uint32_t hash, uint32_t staterr)
368 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
369 case EMX_RXDMRQ_IPV4_TCP:
370 pi->pi_netisr = NETISR_IP;
372 pi->pi_l3proto = IPPROTO_TCP;
375 case EMX_RXDMRQ_IPV6_TCP:
376 pi->pi_netisr = NETISR_IPV6;
378 pi->pi_l3proto = IPPROTO_TCP;
381 case EMX_RXDMRQ_IPV4:
382 if (staterr & E1000_RXD_STAT_IXSM)
386 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
387 E1000_RXD_STAT_TCPCS) {
388 pi->pi_netisr = NETISR_IP;
390 pi->pi_l3proto = IPPROTO_UDP;
398 m->m_flags |= M_HASH;
399 m->m_pkthdr.hash = toeplitz_hash(hash);
404 emx_probe(device_t dev)
406 const struct emx_device *d;
409 vid = pci_get_vendor(dev);
410 did = pci_get_device(dev);
412 for (d = emx_devices; d->desc != NULL; ++d) {
413 if (vid == d->vid && did == d->did) {
414 device_set_desc(dev, d->desc);
415 device_set_async_attach(dev, TRUE);
423 emx_attach(device_t dev)
425 struct emx_softc *sc = device_get_softc(dev);
426 int error = 0, i, throttle, msi_enable, tx_ring_max;
428 uint16_t eeprom_data, device_id, apme_mask;
429 driver_intr_t *intr_func;
431 int offset, offset_def;
437 for (i = 0; i < EMX_NRX_RING; ++i) {
438 sc->rx_data[i].sc = sc;
439 sc->rx_data[i].idx = i;
445 for (i = 0; i < EMX_NTX_RING; ++i) {
446 sc->tx_data[i].sc = sc;
447 sc->tx_data[i].idx = i;
451 * Initialize serializers
453 lwkt_serialize_init(&sc->main_serialize);
454 for (i = 0; i < EMX_NTX_RING; ++i)
455 lwkt_serialize_init(&sc->tx_data[i].tx_serialize);
456 for (i = 0; i < EMX_NRX_RING; ++i)
457 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
460 * Initialize serializer array
464 KKASSERT(i < EMX_NSERIALIZE);
465 sc->serializes[i++] = &sc->main_serialize;
467 KKASSERT(i < EMX_NSERIALIZE);
468 sc->serializes[i++] = &sc->tx_data[0].tx_serialize;
469 KKASSERT(i < EMX_NSERIALIZE);
470 sc->serializes[i++] = &sc->tx_data[1].tx_serialize;
472 KKASSERT(i < EMX_NSERIALIZE);
473 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
474 KKASSERT(i < EMX_NSERIALIZE);
475 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
477 KKASSERT(i == EMX_NSERIALIZE);
479 ifmedia_init(&sc->media, IFM_IMASK, emx_media_change, emx_media_status);
480 callout_init_mp(&sc->timer);
482 sc->dev = sc->osdep.dev = dev;
485 * Determine hardware and mac type
487 sc->hw.vendor_id = pci_get_vendor(dev);
488 sc->hw.device_id = pci_get_device(dev);
489 sc->hw.revision_id = pci_get_revid(dev);
490 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
491 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
493 if (e1000_set_mac_type(&sc->hw))
496 /* Enable bus mastering */
497 pci_enable_busmaster(dev);
502 sc->memory_rid = EMX_BAR_MEM;
503 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
504 &sc->memory_rid, RF_ACTIVE);
505 if (sc->memory == NULL) {
506 device_printf(dev, "Unable to allocate bus resource: memory\n");
510 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
511 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
513 /* XXX This is quite goofy, it is not actually used */
514 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
517 * Don't enable MSI-X on 82574, see:
518 * 82574 specification update errata #15
520 * Don't enable MSI on 82571/82572, see:
521 * 82571/82572 specification update errata #63
523 msi_enable = emx_msi_enable;
525 (sc->hw.mac.type == e1000_82571 ||
526 sc->hw.mac.type == e1000_82572))
532 sc->intr_type = pci_alloc_1intr(dev, msi_enable,
533 &sc->intr_rid, &intr_flags);
535 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
538 unshared = device_getenv_int(dev, "irq.unshared", 0);
540 sc->flags |= EMX_FLAG_SHARED_INTR;
542 device_printf(dev, "IRQ shared\n");
544 intr_flags &= ~RF_SHAREABLE;
546 device_printf(dev, "IRQ unshared\n");
550 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
552 if (sc->intr_res == NULL) {
553 device_printf(dev, "Unable to allocate bus resource: "
559 /* Save PCI command register for Shared Code */
560 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
561 sc->hw.back = &sc->osdep;
564 * For I217/I218, we need to map the flash memory and this
565 * must happen after the MAC is identified.
567 if (sc->hw.mac.type == e1000_pch_lpt) {
568 sc->flash_rid = EMX_BAR_FLASH;
570 sc->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
571 &sc->flash_rid, RF_ACTIVE);
572 if (sc->flash == NULL) {
573 device_printf(dev, "Mapping of Flash failed\n");
577 sc->osdep.flash_bus_space_tag = rman_get_bustag(sc->flash);
578 sc->osdep.flash_bus_space_handle =
579 rman_get_bushandle(sc->flash);
582 * This is used in the shared code
583 * XXX this goof is actually not used.
585 sc->hw.flash_address = (uint8_t *)sc->flash;
588 /* Do Shared Code initialization */
589 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
590 device_printf(dev, "Setup of Shared code failed\n");
594 e1000_get_bus_info(&sc->hw);
596 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
597 sc->hw.phy.autoneg_wait_to_complete = FALSE;
598 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
601 * Interrupt throttle rate
603 throttle = device_getenv_int(dev, "int_throttle_ceil",
604 emx_int_throttle_ceil);
606 sc->int_throttle_ceil = 0;
609 throttle = EMX_DEFAULT_ITR;
611 /* Recalculate the tunable value to get the exact frequency. */
612 throttle = 1000000000 / 256 / throttle;
614 /* Upper 16bits of ITR is reserved and should be zero */
615 if (throttle & 0xffff0000)
616 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
618 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
621 e1000_init_script_state_82541(&sc->hw, TRUE);
622 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
625 if (sc->hw.phy.media_type == e1000_media_type_copper) {
626 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
627 sc->hw.phy.disable_polarity_correction = FALSE;
628 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
631 /* Set the frame limits assuming standard ethernet sized frames. */
632 sc->hw.mac.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
634 /* This controls when hardware reports transmit completion status. */
635 sc->hw.mac.report_tx_early = 1;
637 /* Calculate # of RX rings */
638 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr);
639 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING);
642 * Calculate # of TX rings
645 * I217/I218 claims to have 2 TX queues
648 * Don't enable multiple TX queues on 82574; it always gives
649 * watchdog timeout on TX queue0, when multiple TCP streams are
650 * received. It was originally suspected that the hardware TX
651 * checksum offloading caused this watchdog timeout, since only
652 * TCP ACKs are sent during TCP receiving tests. However, even
653 * if the hardware TX checksum offloading is disable, TX queue0
654 * still will give watchdog.
657 if (sc->hw.mac.type == e1000_82571 ||
658 sc->hw.mac.type == e1000_82572 ||
659 sc->hw.mac.type == e1000_80003es2lan)
660 tx_ring_max = EMX_NTX_RING;
661 sc->tx_ring_cnt = device_getenv_int(dev, "txr", emx_txr);
662 sc->tx_ring_cnt = if_ring_count2(sc->tx_ring_cnt, tx_ring_max);
664 /* Allocate RX/TX rings' busdma(9) stuffs */
665 error = emx_dma_alloc(sc);
669 /* Allocate multicast array memory. */
670 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
673 /* Indicate SOL/IDER usage */
674 if (e1000_check_reset_block(&sc->hw)) {
676 "PHY reset is blocked due to SOL/IDER session.\n");
679 /* Disable EEE on I217/I218 */
680 sc->hw.dev_spec.ich8lan.eee_disable = 1;
683 * Start from a known state, this is important in reading the
684 * nvm and mac from that.
686 e1000_reset_hw(&sc->hw);
688 /* Make sure we have a good EEPROM before we read from it */
689 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
691 * Some PCI-E parts fail the first check due to
692 * the link being in sleep state, call it again,
693 * if it fails a second time its a real issue.
695 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
697 "The EEPROM Checksum Is Not Valid\n");
703 /* Copy the permanent MAC address out of the EEPROM */
704 if (e1000_read_mac_addr(&sc->hw) < 0) {
705 device_printf(dev, "EEPROM read error while reading MAC"
710 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
711 device_printf(dev, "Invalid MAC address\n");
716 /* Determine if we have to control management hardware */
717 if (e1000_enable_mng_pass_thru(&sc->hw))
718 sc->flags |= EMX_FLAG_HAS_MGMT;
723 apme_mask = EMX_EEPROM_APME;
725 switch (sc->hw.mac.type) {
727 sc->flags |= EMX_FLAG_HAS_AMT;
732 case e1000_80003es2lan:
733 if (sc->hw.bus.func == 1) {
734 e1000_read_nvm(&sc->hw,
735 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
737 e1000_read_nvm(&sc->hw,
738 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
743 e1000_read_nvm(&sc->hw,
744 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
747 if (eeprom_data & apme_mask)
748 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
751 * We have the eeprom settings, now apply the special cases
752 * where the eeprom may be wrong or the board won't support
753 * wake on lan on a particular port
755 device_id = pci_get_device(dev);
757 case E1000_DEV_ID_82571EB_FIBER:
759 * Wake events only supported on port A for dual fiber
760 * regardless of eeprom setting
762 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
767 case E1000_DEV_ID_82571EB_QUAD_COPPER:
768 case E1000_DEV_ID_82571EB_QUAD_FIBER:
769 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
770 /* if quad port sc, disable WoL on all but port A */
771 if (emx_global_quad_port_a != 0)
773 /* Reset for multiple quad port adapters */
774 if (++emx_global_quad_port_a == 4)
775 emx_global_quad_port_a = 0;
779 /* XXX disable wol */
784 * NPOLLING RX CPU offset
786 if (sc->rx_ring_cnt == ncpus2) {
789 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
790 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
791 if (offset >= ncpus2 ||
792 offset % sc->rx_ring_cnt != 0) {
793 device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
798 sc->rx_npoll_off = offset;
801 * NPOLLING TX CPU offset
803 if (sc->tx_ring_cnt == ncpus2) {
806 offset_def = (sc->tx_ring_cnt * device_get_unit(dev)) % ncpus2;
807 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
808 if (offset >= ncpus2 ||
809 offset % sc->tx_ring_cnt != 0) {
810 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
815 sc->tx_npoll_off = offset;
817 sc->tx_ring_inuse = emx_get_txring_inuse(sc, FALSE);
819 /* Setup OS specific network interface */
822 /* Add sysctl tree, must after em_setup_ifp() */
825 /* Reset the hardware */
826 error = emx_reset(sc);
829 * Some 82573 parts fail the first reset, call it again,
830 * if it fails a second time its a real issue.
832 error = emx_reset(sc);
834 device_printf(dev, "Unable to reset the hardware\n");
835 ether_ifdetach(&sc->arpcom.ac_if);
840 /* Initialize statistics */
841 emx_update_stats(sc);
843 sc->hw.mac.get_link_status = 1;
844 emx_update_link_status(sc);
846 /* Non-AMT based hardware can now take control from firmware */
847 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
849 emx_get_hw_control(sc);
852 * Missing Interrupt Following ICR read:
854 * 82571/82572 specification update errata #76
855 * 82573 specification update errata #31
856 * 82574 specification update errata #12
858 intr_func = emx_intr;
859 if ((sc->flags & EMX_FLAG_SHARED_INTR) &&
860 (sc->hw.mac.type == e1000_82571 ||
861 sc->hw.mac.type == e1000_82572 ||
862 sc->hw.mac.type == e1000_82573 ||
863 sc->hw.mac.type == e1000_82574))
864 intr_func = emx_intr_mask;
866 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc,
867 &sc->intr_tag, &sc->main_serialize);
869 device_printf(dev, "Failed to register interrupt handler");
870 ether_ifdetach(&sc->arpcom.ac_if);
880 emx_detach(device_t dev)
882 struct emx_softc *sc = device_get_softc(dev);
884 if (device_is_attached(dev)) {
885 struct ifnet *ifp = &sc->arpcom.ac_if;
887 ifnet_serialize_all(ifp);
891 e1000_phy_hw_reset(&sc->hw);
894 emx_rel_hw_control(sc);
897 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
898 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
902 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
904 ifnet_deserialize_all(ifp);
907 } else if (sc->memory != NULL) {
908 emx_rel_hw_control(sc);
911 ifmedia_removeall(&sc->media);
912 bus_generic_detach(dev);
914 if (sc->intr_res != NULL) {
915 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
919 if (sc->intr_type == PCI_INTR_TYPE_MSI)
920 pci_release_msi(dev);
922 if (sc->memory != NULL) {
923 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
927 if (sc->flash != NULL) {
928 bus_release_resource(dev, SYS_RES_MEMORY, sc->flash_rid,
934 /* Free sysctl tree */
935 if (sc->sysctl_tree != NULL)
936 sysctl_ctx_free(&sc->sysctl_ctx);
939 kfree(sc->mta, M_DEVBUF);
945 emx_shutdown(device_t dev)
947 return emx_suspend(dev);
951 emx_suspend(device_t dev)
953 struct emx_softc *sc = device_get_softc(dev);
954 struct ifnet *ifp = &sc->arpcom.ac_if;
956 ifnet_serialize_all(ifp);
961 emx_rel_hw_control(sc);
964 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
965 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
969 ifnet_deserialize_all(ifp);
971 return bus_generic_suspend(dev);
975 emx_resume(device_t dev)
977 struct emx_softc *sc = device_get_softc(dev);
978 struct ifnet *ifp = &sc->arpcom.ac_if;
981 ifnet_serialize_all(ifp);
985 for (i = 0; i < sc->tx_ring_inuse; ++i)
986 ifsq_devstart_sched(sc->tx_data[i].ifsq);
988 ifnet_deserialize_all(ifp);
990 return bus_generic_resume(dev);
994 emx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
996 struct emx_softc *sc = ifp->if_softc;
997 struct emx_txdata *tdata = ifsq_get_priv(ifsq);
999 int idx = -1, nsegs = 0;
1001 KKASSERT(tdata->ifsq == ifsq);
1002 ASSERT_SERIALIZED(&tdata->tx_serialize);
1004 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
1007 if (!sc->link_active || (tdata->tx_flags & EMX_TXFLAG_ENABLED) == 0) {
1012 while (!ifsq_is_empty(ifsq)) {
1013 /* Now do we at least have a minimal? */
1014 if (EMX_IS_OACTIVE(tdata)) {
1015 emx_tx_collect(tdata);
1016 if (EMX_IS_OACTIVE(tdata)) {
1017 ifsq_set_oactive(ifsq);
1023 m_head = ifsq_dequeue(ifsq);
1027 if (emx_encap(tdata, &m_head, &nsegs, &idx)) {
1028 IFNET_STAT_INC(ifp, oerrors, 1);
1029 emx_tx_collect(tdata);
1033 if (nsegs >= tdata->tx_wreg_nsegs) {
1034 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx);
1039 /* Send a copy of the frame to the BPF listener */
1040 ETHER_BPF_MTAP(ifp, m_head);
1042 /* Set timeout in case hardware has problems transmitting. */
1043 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT;
1046 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx);
1050 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1052 struct emx_softc *sc = ifp->if_softc;
1053 struct ifreq *ifr = (struct ifreq *)data;
1054 uint16_t eeprom_data = 0;
1055 int max_frame_size, mask, reinit;
1058 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1062 switch (sc->hw.mac.type) {
1065 * 82573 only supports jumbo frames
1066 * if ASPM is disabled.
1068 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
1070 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
1071 max_frame_size = ETHER_MAX_LEN;
1076 /* Limit Jumbo Frame size */
1081 case e1000_80003es2lan:
1082 max_frame_size = 9234;
1086 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1089 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1095 ifp->if_mtu = ifr->ifr_mtu;
1096 sc->hw.mac.max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
1099 if (ifp->if_flags & IFF_RUNNING)
1104 if (ifp->if_flags & IFF_UP) {
1105 if ((ifp->if_flags & IFF_RUNNING)) {
1106 if ((ifp->if_flags ^ sc->if_flags) &
1107 (IFF_PROMISC | IFF_ALLMULTI)) {
1108 emx_disable_promisc(sc);
1109 emx_set_promisc(sc);
1114 } else if (ifp->if_flags & IFF_RUNNING) {
1117 sc->if_flags = ifp->if_flags;
1122 if (ifp->if_flags & IFF_RUNNING) {
1123 emx_disable_intr(sc);
1125 #ifdef IFPOLL_ENABLE
1126 if (!(ifp->if_flags & IFF_NPOLLING))
1128 emx_enable_intr(sc);
1133 /* Check SOL/IDER usage */
1134 if (e1000_check_reset_block(&sc->hw)) {
1135 device_printf(sc->dev, "Media change is"
1136 " blocked due to SOL/IDER session.\n");
1142 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
1147 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1148 if (mask & IFCAP_RXCSUM) {
1149 ifp->if_capenable ^= IFCAP_RXCSUM;
1152 if (mask & IFCAP_VLAN_HWTAGGING) {
1153 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1156 if (mask & IFCAP_TXCSUM) {
1157 ifp->if_capenable ^= IFCAP_TXCSUM;
1158 if (ifp->if_capenable & IFCAP_TXCSUM)
1159 ifp->if_hwassist |= EMX_CSUM_FEATURES;
1161 ifp->if_hwassist &= ~EMX_CSUM_FEATURES;
1163 if (mask & IFCAP_TSO) {
1164 ifp->if_capenable ^= IFCAP_TSO;
1165 if (ifp->if_capenable & IFCAP_TSO)
1166 ifp->if_hwassist |= CSUM_TSO;
1168 ifp->if_hwassist &= ~CSUM_TSO;
1170 if (mask & IFCAP_RSS)
1171 ifp->if_capenable ^= IFCAP_RSS;
1172 if (reinit && (ifp->if_flags & IFF_RUNNING))
1177 error = ether_ioctl(ifp, command, data);
1184 emx_watchdog(struct ifaltq_subque *ifsq)
1186 struct emx_txdata *tdata = ifsq_get_priv(ifsq);
1187 struct ifnet *ifp = ifsq_get_ifp(ifsq);
1188 struct emx_softc *sc = ifp->if_softc;
1191 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1194 * The timer is set to 5 every time start queues a packet.
1195 * Then txeof keeps resetting it as long as it cleans at
1196 * least one descriptor.
1197 * Finally, anytime all descriptors are clean the timer is
1201 if (E1000_READ_REG(&sc->hw, E1000_TDT(tdata->idx)) ==
1202 E1000_READ_REG(&sc->hw, E1000_TDH(tdata->idx))) {
1204 * If we reach here, all TX jobs are completed and
1205 * the TX engine should have been idled for some time.
1206 * We don't need to call ifsq_devstart_sched() here.
1208 ifsq_clr_oactive(ifsq);
1209 tdata->tx_watchdog.wd_timer = 0;
1214 * If we are in this routine because of pause frames, then
1215 * don't reset the hardware.
1217 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1218 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT;
1222 if_printf(ifp, "TX %d watchdog timeout -- resetting\n", tdata->idx);
1224 IFNET_STAT_INC(ifp, oerrors, 1);
1227 for (i = 0; i < sc->tx_ring_inuse; ++i)
1228 ifsq_devstart_sched(sc->tx_data[i].ifsq);
1234 struct emx_softc *sc = xsc;
1235 struct ifnet *ifp = &sc->arpcom.ac_if;
1236 device_t dev = sc->dev;
1240 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1244 /* Get the latest mac address, User can use a LAA */
1245 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1247 /* Put the address into the Receive Address Array */
1248 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1251 * With the 82571 sc, RAR[0] may be overwritten
1252 * when the other port is reset, we make a duplicate
1253 * in RAR[14] for that eventuality, this assures
1254 * the interface continues to function.
1256 if (sc->hw.mac.type == e1000_82571) {
1257 e1000_set_laa_state_82571(&sc->hw, TRUE);
1258 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1259 E1000_RAR_ENTRIES - 1);
1262 /* Initialize the hardware */
1263 if (emx_reset(sc)) {
1264 device_printf(dev, "Unable to reset the hardware\n");
1265 /* XXX emx_stop()? */
1268 emx_update_link_status(sc);
1270 /* Setup VLAN support, basic and offload if available */
1271 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1273 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1276 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1277 ctrl |= E1000_CTRL_VME;
1278 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1281 /* Configure for OS presence */
1285 #ifdef IFPOLL_ENABLE
1286 if (ifp->if_flags & IFF_NPOLLING)
1289 sc->tx_ring_inuse = emx_get_txring_inuse(sc, polling);
1290 ifq_set_subq_mask(&ifp->if_snd, sc->tx_ring_inuse - 1);
1292 /* Prepare transmit descriptors and buffers */
1293 for (i = 0; i < sc->tx_ring_inuse; ++i)
1294 emx_init_tx_ring(&sc->tx_data[i]);
1295 emx_init_tx_unit(sc);
1297 /* Setup Multicast table */
1300 /* Prepare receive descriptors and buffers */
1301 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1302 if (emx_init_rx_ring(&sc->rx_data[i])) {
1304 "Could not setup receive structures\n");
1309 emx_init_rx_unit(sc);
1311 /* Don't lose promiscuous settings */
1312 emx_set_promisc(sc);
1314 ifp->if_flags |= IFF_RUNNING;
1315 for (i = 0; i < sc->tx_ring_inuse; ++i) {
1316 ifsq_clr_oactive(sc->tx_data[i].ifsq);
1317 ifsq_watchdog_start(&sc->tx_data[i].tx_watchdog);
1320 callout_reset(&sc->timer, hz, emx_timer, sc);
1321 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1323 /* MSI/X configuration for 82574 */
1324 if (sc->hw.mac.type == e1000_82574) {
1327 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1328 tmp |= E1000_CTRL_EXT_PBA_CLR;
1329 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1332 * Set the IVAR - interrupt vector routing.
1333 * Each nibble represents a vector, high bit
1334 * is enable, other 3 bits are the MSIX table
1335 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1336 * Link (other) to 2, hence the magic number.
1338 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1342 * Only enable interrupts if we are not polling, make sure
1343 * they are off otherwise.
1346 emx_disable_intr(sc);
1348 emx_enable_intr(sc);
1350 /* AMT based hardware can now take control from firmware */
1351 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
1352 (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT))
1353 emx_get_hw_control(sc);
1359 emx_intr_body(xsc, TRUE);
1363 emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted)
1365 struct ifnet *ifp = &sc->arpcom.ac_if;
1369 ASSERT_SERIALIZED(&sc->main_serialize);
1371 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1373 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1379 * XXX: some laptops trigger several spurious interrupts
1380 * on emx(4) when in the resume cycle. The ICR register
1381 * reports all-ones value in this case. Processing such
1382 * interrupts would lead to a freeze. I don't know why.
1384 if (reg_icr == 0xffffffff) {
1389 if (ifp->if_flags & IFF_RUNNING) {
1391 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1394 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1395 lwkt_serialize_enter(
1396 &sc->rx_data[i].rx_serialize);
1397 emx_rxeof(&sc->rx_data[i], -1);
1398 lwkt_serialize_exit(
1399 &sc->rx_data[i].rx_serialize);
1402 if (reg_icr & E1000_ICR_TXDW) {
1403 struct emx_txdata *tdata = &sc->tx_data[0];
1405 lwkt_serialize_enter(&tdata->tx_serialize);
1407 if (!ifsq_is_empty(tdata->ifsq))
1408 ifsq_devstart(tdata->ifsq);
1409 lwkt_serialize_exit(&tdata->tx_serialize);
1413 /* Link status change */
1414 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1415 emx_serialize_skipmain(sc);
1417 callout_stop(&sc->timer);
1418 sc->hw.mac.get_link_status = 1;
1419 emx_update_link_status(sc);
1421 /* Deal with TX cruft when link lost */
1424 callout_reset(&sc->timer, hz, emx_timer, sc);
1426 emx_deserialize_skipmain(sc);
1429 if (reg_icr & E1000_ICR_RXO)
1436 emx_intr_mask(void *xsc)
1438 struct emx_softc *sc = xsc;
1440 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
1443 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1444 * so don't check it.
1446 emx_intr_body(sc, FALSE);
1447 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
1451 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1453 struct emx_softc *sc = ifp->if_softc;
1455 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1457 emx_update_link_status(sc);
1459 ifmr->ifm_status = IFM_AVALID;
1460 ifmr->ifm_active = IFM_ETHER;
1462 if (!sc->link_active)
1465 ifmr->ifm_status |= IFM_ACTIVE;
1467 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1468 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1469 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1471 switch (sc->link_speed) {
1473 ifmr->ifm_active |= IFM_10_T;
1476 ifmr->ifm_active |= IFM_100_TX;
1480 ifmr->ifm_active |= IFM_1000_T;
1483 if (sc->link_duplex == FULL_DUPLEX)
1484 ifmr->ifm_active |= IFM_FDX;
1486 ifmr->ifm_active |= IFM_HDX;
1491 emx_media_change(struct ifnet *ifp)
1493 struct emx_softc *sc = ifp->if_softc;
1494 struct ifmedia *ifm = &sc->media;
1496 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1498 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1501 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1503 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1504 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1510 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1511 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1515 sc->hw.mac.autoneg = FALSE;
1516 sc->hw.phy.autoneg_advertised = 0;
1517 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1518 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1520 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1524 sc->hw.mac.autoneg = FALSE;
1525 sc->hw.phy.autoneg_advertised = 0;
1526 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1527 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1529 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1533 if_printf(ifp, "Unsupported media type\n");
1543 emx_encap(struct emx_txdata *tdata, struct mbuf **m_headp,
1544 int *segs_used, int *idx)
1546 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1548 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
1549 struct e1000_tx_desc *ctxd = NULL;
1550 struct mbuf *m_head = *m_headp;
1551 uint32_t txd_upper, txd_lower, cmd = 0;
1552 int maxsegs, nsegs, i, j, first, last = 0, error;
1554 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1555 error = emx_tso_pullup(tdata, m_headp);
1561 txd_upper = txd_lower = 0;
1564 * Capture the first descriptor index, this descriptor
1565 * will have the index of the EOP which is the only one
1566 * that now gets a DONE bit writeback.
1568 first = tdata->next_avail_tx_desc;
1569 tx_buffer = &tdata->tx_buf[first];
1570 tx_buffer_mapped = tx_buffer;
1571 map = tx_buffer->map;
1573 maxsegs = tdata->num_tx_desc_avail - EMX_TX_RESERVED;
1574 KASSERT(maxsegs >= tdata->spare_tx_desc, ("not enough spare TX desc"));
1575 if (maxsegs > EMX_MAX_SCATTER)
1576 maxsegs = EMX_MAX_SCATTER;
1578 error = bus_dmamap_load_mbuf_defrag(tdata->txtag, map, m_headp,
1579 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1585 bus_dmamap_sync(tdata->txtag, map, BUS_DMASYNC_PREWRITE);
1588 tdata->tx_nsegs += nsegs;
1589 *segs_used += nsegs;
1591 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1592 /* TSO will consume one TX desc */
1593 i = emx_tso_setup(tdata, m_head, &txd_upper, &txd_lower);
1594 tdata->tx_nsegs += i;
1596 } else if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1597 /* TX csum offloading will consume one TX desc */
1598 i = emx_txcsum(tdata, m_head, &txd_upper, &txd_lower);
1599 tdata->tx_nsegs += i;
1603 /* Handle VLAN tag */
1604 if (m_head->m_flags & M_VLANTAG) {
1605 /* Set the vlan id. */
1606 txd_upper |= (htole16(m_head->m_pkthdr.ether_vlantag) << 16);
1607 /* Tell hardware to add tag */
1608 txd_lower |= htole32(E1000_TXD_CMD_VLE);
1611 i = tdata->next_avail_tx_desc;
1613 /* Set up our transmit descriptors */
1614 for (j = 0; j < nsegs; j++) {
1615 tx_buffer = &tdata->tx_buf[i];
1616 ctxd = &tdata->tx_desc_base[i];
1618 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1619 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1620 txd_lower | segs[j].ds_len);
1621 ctxd->upper.data = htole32(txd_upper);
1624 if (++i == tdata->num_tx_desc)
1628 tdata->next_avail_tx_desc = i;
1630 KKASSERT(tdata->num_tx_desc_avail > nsegs);
1631 tdata->num_tx_desc_avail -= nsegs;
1633 tx_buffer->m_head = m_head;
1634 tx_buffer_mapped->map = tx_buffer->map;
1635 tx_buffer->map = map;
1637 if (tdata->tx_nsegs >= tdata->tx_intr_nsegs) {
1638 tdata->tx_nsegs = 0;
1641 * Report Status (RS) is turned on
1642 * every tx_intr_nsegs descriptors.
1644 cmd = E1000_TXD_CMD_RS;
1647 * Keep track of the descriptor, which will
1648 * be written back by hardware.
1650 tdata->tx_dd[tdata->tx_dd_tail] = last;
1651 EMX_INC_TXDD_IDX(tdata->tx_dd_tail);
1652 KKASSERT(tdata->tx_dd_tail != tdata->tx_dd_head);
1656 * Last Descriptor of Packet needs End Of Packet (EOP)
1658 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1661 * Defer TDT updating, until enough descriptors are setup
1665 #ifdef EMX_TSS_DEBUG
1673 emx_set_promisc(struct emx_softc *sc)
1675 struct ifnet *ifp = &sc->arpcom.ac_if;
1678 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1680 if (ifp->if_flags & IFF_PROMISC) {
1681 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1682 /* Turn this on if you want to see bad packets */
1684 reg_rctl |= E1000_RCTL_SBP;
1685 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1686 } else if (ifp->if_flags & IFF_ALLMULTI) {
1687 reg_rctl |= E1000_RCTL_MPE;
1688 reg_rctl &= ~E1000_RCTL_UPE;
1689 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1694 emx_disable_promisc(struct emx_softc *sc)
1698 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1700 reg_rctl &= ~E1000_RCTL_UPE;
1701 reg_rctl &= ~E1000_RCTL_MPE;
1702 reg_rctl &= ~E1000_RCTL_SBP;
1703 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1707 emx_set_multi(struct emx_softc *sc)
1709 struct ifnet *ifp = &sc->arpcom.ac_if;
1710 struct ifmultiaddr *ifma;
1711 uint32_t reg_rctl = 0;
1716 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1718 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1719 if (ifma->ifma_addr->sa_family != AF_LINK)
1722 if (mcnt == EMX_MCAST_ADDR_MAX)
1725 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1726 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1730 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1731 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1732 reg_rctl |= E1000_RCTL_MPE;
1733 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1735 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1740 * This routine checks for link status and updates statistics.
1743 emx_timer(void *xsc)
1745 struct emx_softc *sc = xsc;
1746 struct ifnet *ifp = &sc->arpcom.ac_if;
1748 lwkt_serialize_enter(&sc->main_serialize);
1750 emx_update_link_status(sc);
1751 emx_update_stats(sc);
1753 /* Reset LAA into RAR[0] on 82571 */
1754 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1755 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1757 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1758 emx_print_hw_stats(sc);
1762 callout_reset(&sc->timer, hz, emx_timer, sc);
1764 lwkt_serialize_exit(&sc->main_serialize);
1768 emx_update_link_status(struct emx_softc *sc)
1770 struct e1000_hw *hw = &sc->hw;
1771 struct ifnet *ifp = &sc->arpcom.ac_if;
1772 device_t dev = sc->dev;
1773 uint32_t link_check = 0;
1775 /* Get the cached link value or read phy for real */
1776 switch (hw->phy.media_type) {
1777 case e1000_media_type_copper:
1778 if (hw->mac.get_link_status) {
1779 /* Do the work to read phy */
1780 e1000_check_for_link(hw);
1781 link_check = !hw->mac.get_link_status;
1782 if (link_check) /* ESB2 fix */
1783 e1000_cfg_on_link_up(hw);
1789 case e1000_media_type_fiber:
1790 e1000_check_for_link(hw);
1791 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1794 case e1000_media_type_internal_serdes:
1795 e1000_check_for_link(hw);
1796 link_check = sc->hw.mac.serdes_has_link;
1799 case e1000_media_type_unknown:
1804 /* Now check for a transition */
1805 if (link_check && sc->link_active == 0) {
1806 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1810 * Check if we should enable/disable SPEED_MODE bit on
1813 if (sc->link_speed != SPEED_1000 &&
1814 (hw->mac.type == e1000_82571 ||
1815 hw->mac.type == e1000_82572)) {
1818 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1819 tarc0 &= ~EMX_TARC_SPEED_MODE;
1820 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1823 device_printf(dev, "Link is up %d Mbps %s\n",
1825 ((sc->link_duplex == FULL_DUPLEX) ?
1826 "Full Duplex" : "Half Duplex"));
1828 sc->link_active = 1;
1830 ifp->if_baudrate = sc->link_speed * 1000000;
1831 ifp->if_link_state = LINK_STATE_UP;
1832 if_link_state_change(ifp);
1833 } else if (!link_check && sc->link_active == 1) {
1834 ifp->if_baudrate = sc->link_speed = 0;
1835 sc->link_duplex = 0;
1837 device_printf(dev, "Link is Down\n");
1838 sc->link_active = 0;
1839 ifp->if_link_state = LINK_STATE_DOWN;
1840 if_link_state_change(ifp);
1845 emx_stop(struct emx_softc *sc)
1847 struct ifnet *ifp = &sc->arpcom.ac_if;
1850 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1852 emx_disable_intr(sc);
1854 callout_stop(&sc->timer);
1856 ifp->if_flags &= ~IFF_RUNNING;
1857 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1858 struct emx_txdata *tdata = &sc->tx_data[i];
1860 ifsq_clr_oactive(tdata->ifsq);
1861 ifsq_watchdog_stop(&tdata->tx_watchdog);
1862 tdata->tx_flags &= ~EMX_TXFLAG_ENABLED;
1866 * Disable multiple receive queues.
1869 * We should disable multiple receive queues before
1870 * resetting the hardware.
1872 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1874 e1000_reset_hw(&sc->hw);
1875 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1877 for (i = 0; i < sc->tx_ring_cnt; ++i)
1878 emx_free_tx_ring(&sc->tx_data[i]);
1879 for (i = 0; i < sc->rx_ring_cnt; ++i)
1880 emx_free_rx_ring(&sc->rx_data[i]);
1884 emx_reset(struct emx_softc *sc)
1886 device_t dev = sc->dev;
1887 uint16_t rx_buffer_size;
1890 /* Set up smart power down as default off on newer adapters. */
1891 if (!emx_smart_pwr_down &&
1892 (sc->hw.mac.type == e1000_82571 ||
1893 sc->hw.mac.type == e1000_82572)) {
1894 uint16_t phy_tmp = 0;
1896 /* Speed up time to link by disabling smart power down. */
1897 e1000_read_phy_reg(&sc->hw,
1898 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1899 phy_tmp &= ~IGP02E1000_PM_SPD;
1900 e1000_write_phy_reg(&sc->hw,
1901 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1905 * Packet Buffer Allocation (PBA)
1906 * Writing PBA sets the receive portion of the buffer
1907 * the remainder is used for the transmit buffer.
1909 switch (sc->hw.mac.type) {
1910 /* Total Packet Buffer on these is 48K */
1913 case e1000_80003es2lan:
1914 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1917 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1918 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1922 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1926 pba = E1000_PBA_26K;
1930 /* Devices before 82547 had a Packet Buffer of 64K. */
1931 if (sc->hw.mac.max_frame_size > 8192)
1932 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1934 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1936 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1939 * These parameters control the automatic generation (Tx) and
1940 * response (Rx) to Ethernet PAUSE frames.
1941 * - High water mark should allow for at least two frames to be
1942 * received after sending an XOFF.
1943 * - Low water mark works best when it is very near the high water mark.
1944 * This allows the receiver to restart by sending XON when it has
1945 * drained a bit. Here we use an arbitary value of 1500 which will
1946 * restart after one full frame is pulled from the buffer. There
1947 * could be several smaller frames in the buffer and if so they will
1948 * not trigger the XON until their total number reduces the buffer
1950 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1952 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1954 sc->hw.fc.high_water = rx_buffer_size -
1955 roundup2(sc->hw.mac.max_frame_size, 1024);
1956 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1958 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1959 sc->hw.fc.send_xon = TRUE;
1960 sc->hw.fc.requested_mode = e1000_fc_full;
1963 * Device specific overrides/settings
1965 if (sc->hw.mac.type == e1000_pch_lpt) {
1966 sc->hw.fc.high_water = 0x5C20;
1967 sc->hw.fc.low_water = 0x5048;
1968 sc->hw.fc.pause_time = 0x0650;
1969 sc->hw.fc.refresh_time = 0x0400;
1970 /* Jumbos need adjusted PBA */
1971 if (sc->arpcom.ac_if.if_mtu > ETHERMTU)
1972 E1000_WRITE_REG(&sc->hw, E1000_PBA, 12);
1974 E1000_WRITE_REG(&sc->hw, E1000_PBA, 26);
1975 } else if (sc->hw.mac.type == e1000_80003es2lan) {
1976 sc->hw.fc.pause_time = 0xFFFF;
1979 /* Issue a global reset */
1980 e1000_reset_hw(&sc->hw);
1981 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1982 emx_disable_aspm(sc);
1984 if (e1000_init_hw(&sc->hw) < 0) {
1985 device_printf(dev, "Hardware Initialization Failed\n");
1989 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1990 e1000_get_phy_info(&sc->hw);
1991 e1000_check_for_link(&sc->hw);
1997 emx_setup_ifp(struct emx_softc *sc)
1999 struct ifnet *ifp = &sc->arpcom.ac_if;
2002 if_initname(ifp, device_get_name(sc->dev),
2003 device_get_unit(sc->dev));
2005 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2006 ifp->if_init = emx_init;
2007 ifp->if_ioctl = emx_ioctl;
2008 ifp->if_start = emx_start;
2009 #ifdef IFPOLL_ENABLE
2010 ifp->if_npoll = emx_npoll;
2012 ifp->if_serialize = emx_serialize;
2013 ifp->if_deserialize = emx_deserialize;
2014 ifp->if_tryserialize = emx_tryserialize;
2016 ifp->if_serialize_assert = emx_serialize_assert;
2019 ifq_set_maxlen(&ifp->if_snd, sc->tx_data[0].num_tx_desc - 1);
2020 ifq_set_ready(&ifp->if_snd);
2021 ifq_set_subq_cnt(&ifp->if_snd, sc->tx_ring_cnt);
2023 ifp->if_mapsubq = ifq_mapsubq_mask;
2024 ifq_set_subq_mask(&ifp->if_snd, 0);
2026 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
2028 ifp->if_capabilities = IFCAP_HWCSUM |
2029 IFCAP_VLAN_HWTAGGING |
2032 if (sc->rx_ring_cnt > 1)
2033 ifp->if_capabilities |= IFCAP_RSS;
2034 ifp->if_capenable = ifp->if_capabilities;
2035 ifp->if_hwassist = EMX_CSUM_FEATURES | CSUM_TSO;
2038 * Tell the upper layer(s) we support long frames.
2040 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2042 for (i = 0; i < sc->tx_ring_cnt; ++i) {
2043 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i);
2044 struct emx_txdata *tdata = &sc->tx_data[i];
2046 ifsq_set_cpuid(ifsq, rman_get_cpuid(sc->intr_res));
2047 ifsq_set_priv(ifsq, tdata);
2048 ifsq_set_hw_serialize(ifsq, &tdata->tx_serialize);
2051 ifsq_watchdog_init(&tdata->tx_watchdog, ifsq, emx_watchdog);
2055 * Specify the media types supported by this sc and register
2056 * callbacks to update media and link information
2058 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2059 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
2060 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2062 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
2064 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
2065 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
2067 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2068 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
2070 if (sc->hw.phy.type != e1000_phy_ife) {
2071 ifmedia_add(&sc->media,
2072 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2073 ifmedia_add(&sc->media,
2074 IFM_ETHER | IFM_1000_T, 0, NULL);
2077 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2078 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
2082 * Workaround for SmartSpeed on 82541 and 82547 controllers
2085 emx_smartspeed(struct emx_softc *sc)
2089 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
2090 sc->hw.mac.autoneg == 0 ||
2091 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2094 if (sc->smartspeed == 0) {
2096 * If Master/Slave config fault is asserted twice,
2097 * we assume back-to-back
2099 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2100 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2102 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2103 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2104 e1000_read_phy_reg(&sc->hw,
2105 PHY_1000T_CTRL, &phy_tmp);
2106 if (phy_tmp & CR_1000T_MS_ENABLE) {
2107 phy_tmp &= ~CR_1000T_MS_ENABLE;
2108 e1000_write_phy_reg(&sc->hw,
2109 PHY_1000T_CTRL, phy_tmp);
2111 if (sc->hw.mac.autoneg &&
2112 !e1000_phy_setup_autoneg(&sc->hw) &&
2113 !e1000_read_phy_reg(&sc->hw,
2114 PHY_CONTROL, &phy_tmp)) {
2115 phy_tmp |= MII_CR_AUTO_NEG_EN |
2116 MII_CR_RESTART_AUTO_NEG;
2117 e1000_write_phy_reg(&sc->hw,
2118 PHY_CONTROL, phy_tmp);
2123 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
2124 /* If still no link, perhaps using 2/3 pair cable */
2125 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
2126 phy_tmp |= CR_1000T_MS_ENABLE;
2127 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
2128 if (sc->hw.mac.autoneg &&
2129 !e1000_phy_setup_autoneg(&sc->hw) &&
2130 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
2131 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2132 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
2136 /* Restart process after EMX_SMARTSPEED_MAX iterations */
2137 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
2142 emx_create_tx_ring(struct emx_txdata *tdata)
2144 device_t dev = tdata->sc->dev;
2145 struct emx_txbuf *tx_buffer;
2146 int error, i, tsize, ntxd;
2149 * Validate number of transmit descriptors. It must not exceed
2150 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2152 ntxd = device_getenv_int(dev, "txd", emx_txd);
2153 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
2154 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) {
2155 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
2156 EMX_DEFAULT_TXD, ntxd);
2157 tdata->num_tx_desc = EMX_DEFAULT_TXD;
2159 tdata->num_tx_desc = ntxd;
2163 * Allocate Transmit Descriptor ring
2165 tsize = roundup2(tdata->num_tx_desc * sizeof(struct e1000_tx_desc),
2167 tdata->tx_desc_base = bus_dmamem_coherent_any(tdata->sc->parent_dtag,
2168 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
2169 &tdata->tx_desc_dtag, &tdata->tx_desc_dmap,
2170 &tdata->tx_desc_paddr);
2171 if (tdata->tx_desc_base == NULL) {
2172 device_printf(dev, "Unable to allocate tx_desc memory\n");
2176 tsize = __VM_CACHELINE_ALIGN(
2177 sizeof(struct emx_txbuf) * tdata->num_tx_desc);
2178 tdata->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
2181 * Create DMA tags for tx buffers
2183 error = bus_dma_tag_create(tdata->sc->parent_dtag, /* parent */
2184 1, 0, /* alignment, bounds */
2185 BUS_SPACE_MAXADDR, /* lowaddr */
2186 BUS_SPACE_MAXADDR, /* highaddr */
2187 NULL, NULL, /* filter, filterarg */
2188 EMX_TSO_SIZE, /* maxsize */
2189 EMX_MAX_SCATTER, /* nsegments */
2190 EMX_MAX_SEGSIZE, /* maxsegsize */
2191 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2192 BUS_DMA_ONEBPAGE, /* flags */
2195 device_printf(dev, "Unable to allocate TX DMA tag\n");
2196 kfree(tdata->tx_buf, M_DEVBUF);
2197 tdata->tx_buf = NULL;
2202 * Create DMA maps for tx buffers
2204 for (i = 0; i < tdata->num_tx_desc; i++) {
2205 tx_buffer = &tdata->tx_buf[i];
2207 error = bus_dmamap_create(tdata->txtag,
2208 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2211 device_printf(dev, "Unable to create TX DMA map\n");
2212 emx_destroy_tx_ring(tdata, i);
2218 * Setup TX parameters
2220 tdata->spare_tx_desc = EMX_TX_SPARE;
2221 tdata->tx_wreg_nsegs = EMX_DEFAULT_TXWREG;
2224 * Keep following relationship between spare_tx_desc, oact_tx_desc
2225 * and tx_intr_nsegs:
2226 * (spare_tx_desc + EMX_TX_RESERVED) <=
2227 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_intr_nsegs
2229 tdata->oact_tx_desc = tdata->num_tx_desc / 8;
2230 if (tdata->oact_tx_desc > EMX_TX_OACTIVE_MAX)
2231 tdata->oact_tx_desc = EMX_TX_OACTIVE_MAX;
2232 if (tdata->oact_tx_desc < tdata->spare_tx_desc + EMX_TX_RESERVED)
2233 tdata->oact_tx_desc = tdata->spare_tx_desc + EMX_TX_RESERVED;
2235 tdata->tx_intr_nsegs = tdata->num_tx_desc / 16;
2236 if (tdata->tx_intr_nsegs < tdata->oact_tx_desc)
2237 tdata->tx_intr_nsegs = tdata->oact_tx_desc;
2240 * Pullup extra 4bytes into the first data segment, see:
2241 * 82571/82572 specification update errata #7
2244 * 4bytes instead of 2bytes, which are mentioned in the errata,
2245 * are pulled; mainly to keep rest of the data properly aligned.
2247 if (tdata->sc->hw.mac.type == e1000_82571 ||
2248 tdata->sc->hw.mac.type == e1000_82572)
2249 tdata->tx_flags |= EMX_TXFLAG_TSO_PULLEX;
2255 emx_init_tx_ring(struct emx_txdata *tdata)
2257 /* Clear the old ring contents */
2258 bzero(tdata->tx_desc_base,
2259 sizeof(struct e1000_tx_desc) * tdata->num_tx_desc);
2262 tdata->next_avail_tx_desc = 0;
2263 tdata->next_tx_to_clean = 0;
2264 tdata->num_tx_desc_avail = tdata->num_tx_desc;
2266 tdata->tx_flags |= EMX_TXFLAG_ENABLED;
2267 if (tdata->sc->tx_ring_inuse > 1) {
2268 tdata->tx_flags |= EMX_TXFLAG_FORCECTX;
2270 if_printf(&tdata->sc->arpcom.ac_if,
2271 "TX %d force ctx setup\n", tdata->idx);
2277 emx_init_tx_unit(struct emx_softc *sc)
2279 uint32_t tctl, tarc, tipg = 0;
2282 for (i = 0; i < sc->tx_ring_inuse; ++i) {
2283 struct emx_txdata *tdata = &sc->tx_data[i];
2286 /* Setup the Base and Length of the Tx Descriptor Ring */
2287 bus_addr = tdata->tx_desc_paddr;
2288 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(i),
2289 tdata->num_tx_desc * sizeof(struct e1000_tx_desc));
2290 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(i),
2291 (uint32_t)(bus_addr >> 32));
2292 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(i),
2293 (uint32_t)bus_addr);
2294 /* Setup the HW Tx Head and Tail descriptor pointers */
2295 E1000_WRITE_REG(&sc->hw, E1000_TDT(i), 0);
2296 E1000_WRITE_REG(&sc->hw, E1000_TDH(i), 0);
2299 /* Set the default values for the Tx Inter Packet Gap timer */
2300 switch (sc->hw.mac.type) {
2301 case e1000_80003es2lan:
2302 tipg = DEFAULT_82543_TIPG_IPGR1;
2303 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2304 E1000_TIPG_IPGR2_SHIFT;
2308 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2309 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2310 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2312 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2313 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2314 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2318 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2320 /* NOTE: 0 is not allowed for TIDV */
2321 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2322 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2324 if (sc->hw.mac.type == e1000_82571 ||
2325 sc->hw.mac.type == e1000_82572) {
2326 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2327 tarc |= EMX_TARC_SPEED_MODE;
2328 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2329 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2330 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2332 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2333 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2335 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2338 /* Program the Transmit Control Register */
2339 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2340 tctl &= ~E1000_TCTL_CT;
2341 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2342 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2343 tctl |= E1000_TCTL_MULR;
2345 /* This write will effectively turn on the transmit unit. */
2346 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2348 if (sc->hw.mac.type == e1000_82571 ||
2349 sc->hw.mac.type == e1000_82572 ||
2350 sc->hw.mac.type == e1000_80003es2lan) {
2351 /* Bit 28 of TARC1 must be cleared when MULR is enabled */
2352 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2354 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2357 if (sc->tx_ring_inuse > 1) {
2358 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2359 tarc &= ~EMX_TARC_COUNT_MASK;
2361 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2363 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2364 tarc &= ~EMX_TARC_COUNT_MASK;
2366 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2371 emx_destroy_tx_ring(struct emx_txdata *tdata, int ndesc)
2373 struct emx_txbuf *tx_buffer;
2376 /* Free Transmit Descriptor ring */
2377 if (tdata->tx_desc_base) {
2378 bus_dmamap_unload(tdata->tx_desc_dtag, tdata->tx_desc_dmap);
2379 bus_dmamem_free(tdata->tx_desc_dtag, tdata->tx_desc_base,
2380 tdata->tx_desc_dmap);
2381 bus_dma_tag_destroy(tdata->tx_desc_dtag);
2383 tdata->tx_desc_base = NULL;
2386 if (tdata->tx_buf == NULL)
2389 for (i = 0; i < ndesc; i++) {
2390 tx_buffer = &tdata->tx_buf[i];
2392 KKASSERT(tx_buffer->m_head == NULL);
2393 bus_dmamap_destroy(tdata->txtag, tx_buffer->map);
2395 bus_dma_tag_destroy(tdata->txtag);
2397 kfree(tdata->tx_buf, M_DEVBUF);
2398 tdata->tx_buf = NULL;
2402 * The offload context needs to be set when we transfer the first
2403 * packet of a particular protocol (TCP/UDP). This routine has been
2404 * enhanced to deal with inserted VLAN headers.
2406 * If the new packet's ether header length, ip header length and
2407 * csum offloading type are same as the previous packet, we should
2408 * avoid allocating a new csum context descriptor; mainly to take
2409 * advantage of the pipeline effect of the TX data read request.
2411 * This function returns number of TX descrptors allocated for
2415 emx_txcsum(struct emx_txdata *tdata, struct mbuf *mp,
2416 uint32_t *txd_upper, uint32_t *txd_lower)
2418 struct e1000_context_desc *TXD;
2419 int curr_txd, ehdrlen, csum_flags;
2420 uint32_t cmd, hdr_len, ip_hlen;
2422 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2423 ip_hlen = mp->m_pkthdr.csum_iphlen;
2424 ehdrlen = mp->m_pkthdr.csum_lhlen;
2426 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 &&
2427 tdata->csum_lhlen == ehdrlen && tdata->csum_iphlen == ip_hlen &&
2428 tdata->csum_flags == csum_flags) {
2430 * Same csum offload context as the previous packets;
2433 *txd_upper = tdata->csum_txd_upper;
2434 *txd_lower = tdata->csum_txd_lower;
2439 * Setup a new csum offload context.
2442 curr_txd = tdata->next_avail_tx_desc;
2443 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd];
2447 /* Setup of IP header checksum. */
2448 if (csum_flags & CSUM_IP) {
2450 * Start offset for header checksum calculation.
2451 * End offset for header checksum calculation.
2452 * Offset of place to put the checksum.
2454 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2455 TXD->lower_setup.ip_fields.ipcse =
2456 htole16(ehdrlen + ip_hlen - 1);
2457 TXD->lower_setup.ip_fields.ipcso =
2458 ehdrlen + offsetof(struct ip, ip_sum);
2459 cmd |= E1000_TXD_CMD_IP;
2460 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2462 hdr_len = ehdrlen + ip_hlen;
2464 if (csum_flags & CSUM_TCP) {
2466 * Start offset for payload checksum calculation.
2467 * End offset for payload checksum calculation.
2468 * Offset of place to put the checksum.
2470 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2471 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2472 TXD->upper_setup.tcp_fields.tucso =
2473 hdr_len + offsetof(struct tcphdr, th_sum);
2474 cmd |= E1000_TXD_CMD_TCP;
2475 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2476 } else if (csum_flags & CSUM_UDP) {
2478 * Start offset for header checksum calculation.
2479 * End offset for header checksum calculation.
2480 * Offset of place to put the checksum.
2482 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2483 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2484 TXD->upper_setup.tcp_fields.tucso =
2485 hdr_len + offsetof(struct udphdr, uh_sum);
2486 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2489 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2490 E1000_TXD_DTYP_D; /* Data descr */
2492 /* Save the information for this csum offloading context */
2493 tdata->csum_lhlen = ehdrlen;
2494 tdata->csum_iphlen = ip_hlen;
2495 tdata->csum_flags = csum_flags;
2496 tdata->csum_txd_upper = *txd_upper;
2497 tdata->csum_txd_lower = *txd_lower;
2499 TXD->tcp_seg_setup.data = htole32(0);
2500 TXD->cmd_and_length =
2501 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2503 if (++curr_txd == tdata->num_tx_desc)
2506 KKASSERT(tdata->num_tx_desc_avail > 0);
2507 tdata->num_tx_desc_avail--;
2509 tdata->next_avail_tx_desc = curr_txd;
2514 emx_txeof(struct emx_txdata *tdata)
2516 struct ifnet *ifp = &tdata->sc->arpcom.ac_if;
2517 struct emx_txbuf *tx_buffer;
2518 int first, num_avail;
2520 if (tdata->tx_dd_head == tdata->tx_dd_tail)
2523 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2526 num_avail = tdata->num_tx_desc_avail;
2527 first = tdata->next_tx_to_clean;
2529 while (tdata->tx_dd_head != tdata->tx_dd_tail) {
2530 int dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2531 struct e1000_tx_desc *tx_desc;
2533 tx_desc = &tdata->tx_desc_base[dd_idx];
2534 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2535 EMX_INC_TXDD_IDX(tdata->tx_dd_head);
2537 if (++dd_idx == tdata->num_tx_desc)
2540 while (first != dd_idx) {
2545 tx_buffer = &tdata->tx_buf[first];
2546 if (tx_buffer->m_head) {
2547 IFNET_STAT_INC(ifp, opackets, 1);
2548 bus_dmamap_unload(tdata->txtag,
2550 m_freem(tx_buffer->m_head);
2551 tx_buffer->m_head = NULL;
2554 if (++first == tdata->num_tx_desc)
2561 tdata->next_tx_to_clean = first;
2562 tdata->num_tx_desc_avail = num_avail;
2564 if (tdata->tx_dd_head == tdata->tx_dd_tail) {
2565 tdata->tx_dd_head = 0;
2566 tdata->tx_dd_tail = 0;
2569 if (!EMX_IS_OACTIVE(tdata)) {
2570 ifsq_clr_oactive(tdata->ifsq);
2572 /* All clean, turn off the timer */
2573 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2574 tdata->tx_watchdog.wd_timer = 0;
2579 emx_tx_collect(struct emx_txdata *tdata)
2581 struct ifnet *ifp = &tdata->sc->arpcom.ac_if;
2582 struct emx_txbuf *tx_buffer;
2583 int tdh, first, num_avail, dd_idx = -1;
2585 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2588 tdh = E1000_READ_REG(&tdata->sc->hw, E1000_TDH(tdata->idx));
2589 if (tdh == tdata->next_tx_to_clean)
2592 if (tdata->tx_dd_head != tdata->tx_dd_tail)
2593 dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2595 num_avail = tdata->num_tx_desc_avail;
2596 first = tdata->next_tx_to_clean;
2598 while (first != tdh) {
2603 tx_buffer = &tdata->tx_buf[first];
2604 if (tx_buffer->m_head) {
2605 IFNET_STAT_INC(ifp, opackets, 1);
2606 bus_dmamap_unload(tdata->txtag,
2608 m_freem(tx_buffer->m_head);
2609 tx_buffer->m_head = NULL;
2612 if (first == dd_idx) {
2613 EMX_INC_TXDD_IDX(tdata->tx_dd_head);
2614 if (tdata->tx_dd_head == tdata->tx_dd_tail) {
2615 tdata->tx_dd_head = 0;
2616 tdata->tx_dd_tail = 0;
2619 dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2623 if (++first == tdata->num_tx_desc)
2626 tdata->next_tx_to_clean = first;
2627 tdata->num_tx_desc_avail = num_avail;
2629 if (!EMX_IS_OACTIVE(tdata)) {
2630 ifsq_clr_oactive(tdata->ifsq);
2632 /* All clean, turn off the timer */
2633 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2634 tdata->tx_watchdog.wd_timer = 0;
2639 * When Link is lost sometimes there is work still in the TX ring
2640 * which will result in a watchdog, rather than allow that do an
2641 * attempted cleanup and then reinit here. Note that this has been
2642 * seens mostly with fiber adapters.
2645 emx_tx_purge(struct emx_softc *sc)
2649 if (sc->link_active)
2652 for (i = 0; i < sc->tx_ring_inuse; ++i) {
2653 struct emx_txdata *tdata = &sc->tx_data[i];
2655 if (tdata->tx_watchdog.wd_timer) {
2656 emx_tx_collect(tdata);
2657 if (tdata->tx_watchdog.wd_timer) {
2658 if_printf(&sc->arpcom.ac_if,
2659 "Link lost, TX pending, reinit\n");
2668 emx_newbuf(struct emx_rxdata *rdata, int i, int init)
2671 bus_dma_segment_t seg;
2673 struct emx_rxbuf *rx_buffer;
2676 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2679 if_printf(&rdata->sc->arpcom.ac_if,
2680 "Unable to allocate RX mbuf\n");
2684 m->m_len = m->m_pkthdr.len = MCLBYTES;
2686 if (rdata->sc->hw.mac.max_frame_size <= MCLBYTES - ETHER_ALIGN)
2687 m_adj(m, ETHER_ALIGN);
2689 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2690 rdata->rx_sparemap, m,
2691 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2695 if_printf(&rdata->sc->arpcom.ac_if,
2696 "Unable to load RX mbuf\n");
2701 rx_buffer = &rdata->rx_buf[i];
2702 if (rx_buffer->m_head != NULL)
2703 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2705 map = rx_buffer->map;
2706 rx_buffer->map = rdata->rx_sparemap;
2707 rdata->rx_sparemap = map;
2709 rx_buffer->m_head = m;
2710 rx_buffer->paddr = seg.ds_addr;
2712 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
2717 emx_create_rx_ring(struct emx_rxdata *rdata)
2719 device_t dev = rdata->sc->dev;
2720 struct emx_rxbuf *rx_buffer;
2721 int i, error, rsize, nrxd;
2724 * Validate number of receive descriptors. It must not exceed
2725 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2727 nrxd = device_getenv_int(dev, "rxd", emx_rxd);
2728 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2729 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) {
2730 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2731 EMX_DEFAULT_RXD, nrxd);
2732 rdata->num_rx_desc = EMX_DEFAULT_RXD;
2734 rdata->num_rx_desc = nrxd;
2738 * Allocate Receive Descriptor ring
2740 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
2742 rdata->rx_desc = bus_dmamem_coherent_any(rdata->sc->parent_dtag,
2743 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2744 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2745 &rdata->rx_desc_paddr);
2746 if (rdata->rx_desc == NULL) {
2747 device_printf(dev, "Unable to allocate rx_desc memory\n");
2751 rsize = __VM_CACHELINE_ALIGN(
2752 sizeof(struct emx_rxbuf) * rdata->num_rx_desc);
2753 rdata->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2756 * Create DMA tag for rx buffers
2758 error = bus_dma_tag_create(rdata->sc->parent_dtag, /* parent */
2759 1, 0, /* alignment, bounds */
2760 BUS_SPACE_MAXADDR, /* lowaddr */
2761 BUS_SPACE_MAXADDR, /* highaddr */
2762 NULL, NULL, /* filter, filterarg */
2763 MCLBYTES, /* maxsize */
2765 MCLBYTES, /* maxsegsize */
2766 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2769 device_printf(dev, "Unable to allocate RX DMA tag\n");
2770 kfree(rdata->rx_buf, M_DEVBUF);
2771 rdata->rx_buf = NULL;
2776 * Create spare DMA map for rx buffers
2778 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2779 &rdata->rx_sparemap);
2781 device_printf(dev, "Unable to create spare RX DMA map\n");
2782 bus_dma_tag_destroy(rdata->rxtag);
2783 kfree(rdata->rx_buf, M_DEVBUF);
2784 rdata->rx_buf = NULL;
2789 * Create DMA maps for rx buffers
2791 for (i = 0; i < rdata->num_rx_desc; i++) {
2792 rx_buffer = &rdata->rx_buf[i];
2794 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2797 device_printf(dev, "Unable to create RX DMA map\n");
2798 emx_destroy_rx_ring(rdata, i);
2806 emx_free_rx_ring(struct emx_rxdata *rdata)
2810 for (i = 0; i < rdata->num_rx_desc; i++) {
2811 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
2813 if (rx_buffer->m_head != NULL) {
2814 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2815 m_freem(rx_buffer->m_head);
2816 rx_buffer->m_head = NULL;
2820 if (rdata->fmp != NULL)
2821 m_freem(rdata->fmp);
2827 emx_free_tx_ring(struct emx_txdata *tdata)
2831 for (i = 0; i < tdata->num_tx_desc; i++) {
2832 struct emx_txbuf *tx_buffer = &tdata->tx_buf[i];
2834 if (tx_buffer->m_head != NULL) {
2835 bus_dmamap_unload(tdata->txtag, tx_buffer->map);
2836 m_freem(tx_buffer->m_head);
2837 tx_buffer->m_head = NULL;
2841 tdata->tx_flags &= ~EMX_TXFLAG_FORCECTX;
2843 tdata->csum_flags = 0;
2844 tdata->csum_lhlen = 0;
2845 tdata->csum_iphlen = 0;
2846 tdata->csum_thlen = 0;
2847 tdata->csum_mss = 0;
2848 tdata->csum_pktlen = 0;
2850 tdata->tx_dd_head = 0;
2851 tdata->tx_dd_tail = 0;
2852 tdata->tx_nsegs = 0;
2856 emx_init_rx_ring(struct emx_rxdata *rdata)
2860 /* Reset descriptor ring */
2861 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
2863 /* Allocate new ones. */
2864 for (i = 0; i < rdata->num_rx_desc; i++) {
2865 error = emx_newbuf(rdata, i, 1);
2870 /* Setup our descriptor pointers */
2871 rdata->next_rx_desc_to_check = 0;
2877 emx_init_rx_unit(struct emx_softc *sc)
2879 struct ifnet *ifp = &sc->arpcom.ac_if;
2881 uint32_t rctl, itr, rfctl;
2885 * Make sure receives are disabled while setting
2886 * up the descriptor ring
2888 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2889 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2892 * Set the interrupt throttling rate. Value is calculated
2893 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2895 if (sc->int_throttle_ceil)
2896 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2899 emx_set_itr(sc, itr);
2901 /* Use extended RX descriptor */
2902 rfctl = E1000_RFCTL_EXTEN;
2904 /* Disable accelerated ackknowledge */
2905 if (sc->hw.mac.type == e1000_82574)
2906 rfctl |= E1000_RFCTL_ACK_DIS;
2908 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
2911 * Receive Checksum Offload for TCP and UDP
2913 * Checksum offloading is also enabled if multiple receive
2914 * queue is to be supported, since we need it to figure out
2917 if ((ifp->if_capenable & IFCAP_RXCSUM) ||
2918 sc->rx_ring_cnt > 1) {
2921 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2925 * PCSD must be enabled to enable multiple
2928 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2930 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2934 * Configure multiple receive queue (RSS)
2936 if (sc->rx_ring_cnt > 1) {
2937 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2940 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING,
2941 ("invalid number of RX ring (%d)", sc->rx_ring_cnt));
2945 * When we reach here, RSS has already been disabled
2946 * in emx_stop(), so we could safely configure RSS key
2947 * and redirect table.
2953 toeplitz_get_key(key, sizeof(key));
2954 for (i = 0; i < EMX_NRSSRK; ++i) {
2957 rssrk = EMX_RSSRK_VAL(key, i);
2958 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2960 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2964 * Configure RSS redirect table in following fashion:
2965 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2968 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2971 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT;
2972 reta |= q << (8 * i);
2974 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2976 for (i = 0; i < EMX_NRETA; ++i)
2977 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
2980 * Enable multiple receive queues.
2981 * Enable IPv4 RSS standard hash functions.
2982 * Disable RSS interrupt.
2984 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2985 E1000_MRQC_ENABLE_RSS_2Q |
2986 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2987 E1000_MRQC_RSS_FIELD_IPV4);
2991 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2992 * long latencies are observed, like Lenovo X60. This
2993 * change eliminates the problem, but since having positive
2994 * values in RDTR is a known source of problems on other
2995 * platforms another solution is being sought.
2997 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
2998 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
2999 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
3002 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3003 struct emx_rxdata *rdata = &sc->rx_data[i];
3006 * Setup the Base and Length of the Rx Descriptor Ring
3008 bus_addr = rdata->rx_desc_paddr;
3009 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
3010 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
3011 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
3012 (uint32_t)(bus_addr >> 32));
3013 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
3014 (uint32_t)bus_addr);
3017 * Setup the HW Rx Head and Tail Descriptor Pointers
3019 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
3020 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
3021 sc->rx_data[i].num_rx_desc - 1);
3024 if (sc->hw.mac.type >= e1000_pch2lan) {
3025 if (ifp->if_mtu > ETHERMTU)
3026 e1000_lv_jumbo_workaround_ich8lan(&sc->hw, TRUE);
3028 e1000_lv_jumbo_workaround_ich8lan(&sc->hw, FALSE);
3031 /* Setup the Receive Control Register */
3032 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3033 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
3034 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
3035 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3037 /* Make sure VLAN Filters are off */
3038 rctl &= ~E1000_RCTL_VFE;
3040 /* Don't store bad paket */
3041 rctl &= ~E1000_RCTL_SBP;
3044 rctl |= E1000_RCTL_SZ_2048;
3046 if (ifp->if_mtu > ETHERMTU)
3047 rctl |= E1000_RCTL_LPE;
3049 rctl &= ~E1000_RCTL_LPE;
3051 /* Enable Receives */
3052 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
3056 emx_destroy_rx_ring(struct emx_rxdata *rdata, int ndesc)
3058 struct emx_rxbuf *rx_buffer;
3061 /* Free Receive Descriptor ring */
3062 if (rdata->rx_desc) {
3063 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
3064 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
3065 rdata->rx_desc_dmap);
3066 bus_dma_tag_destroy(rdata->rx_desc_dtag);
3068 rdata->rx_desc = NULL;
3071 if (rdata->rx_buf == NULL)
3074 for (i = 0; i < ndesc; i++) {
3075 rx_buffer = &rdata->rx_buf[i];
3077 KKASSERT(rx_buffer->m_head == NULL);
3078 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
3080 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
3081 bus_dma_tag_destroy(rdata->rxtag);
3083 kfree(rdata->rx_buf, M_DEVBUF);
3084 rdata->rx_buf = NULL;
3088 emx_rxeof(struct emx_rxdata *rdata, int count)
3090 struct ifnet *ifp = &rdata->sc->arpcom.ac_if;
3092 emx_rxdesc_t *current_desc;
3094 int i, cpuid = mycpuid;
3096 i = rdata->next_rx_desc_to_check;
3097 current_desc = &rdata->rx_desc[i];
3098 staterr = le32toh(current_desc->rxd_staterr);
3100 if (!(staterr & E1000_RXD_STAT_DD))
3103 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
3104 struct pktinfo *pi = NULL, pi0;
3105 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
3106 struct mbuf *m = NULL;
3111 mp = rx_buf->m_head;
3114 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
3115 * needs to access the last received byte in the mbuf.
3117 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
3118 BUS_DMASYNC_POSTREAD);
3120 len = le16toh(current_desc->rxd_length);
3121 if (staterr & E1000_RXD_STAT_EOP) {
3128 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
3130 uint32_t mrq, rss_hash;
3133 * Save several necessary information,
3134 * before emx_newbuf() destroy it.
3136 if ((staterr & E1000_RXD_STAT_VP) && eop)
3137 vlan = le16toh(current_desc->rxd_vlan);
3139 mrq = le32toh(current_desc->rxd_mrq);
3140 rss_hash = le32toh(current_desc->rxd_rss);
3142 EMX_RSS_DPRINTF(rdata->sc, 10,
3143 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
3144 rdata->idx, mrq, rss_hash);
3146 if (emx_newbuf(rdata, i, 0) != 0) {
3147 IFNET_STAT_INC(ifp, iqdrops, 1);
3151 /* Assign correct length to the current fragment */
3154 if (rdata->fmp == NULL) {
3155 mp->m_pkthdr.len = len;
3156 rdata->fmp = mp; /* Store the first mbuf */
3160 * Chain mbuf's together
3162 rdata->lmp->m_next = mp;
3163 rdata->lmp = rdata->lmp->m_next;
3164 rdata->fmp->m_pkthdr.len += len;
3168 rdata->fmp->m_pkthdr.rcvif = ifp;
3169 IFNET_STAT_INC(ifp, ipackets, 1);
3171 if (ifp->if_capenable & IFCAP_RXCSUM)
3172 emx_rxcsum(staterr, rdata->fmp);
3174 if (staterr & E1000_RXD_STAT_VP) {
3175 rdata->fmp->m_pkthdr.ether_vlantag =
3177 rdata->fmp->m_flags |= M_VLANTAG;
3183 if (ifp->if_capenable & IFCAP_RSS) {
3184 pi = emx_rssinfo(m, &pi0, mrq,
3187 #ifdef EMX_RSS_DEBUG
3192 IFNET_STAT_INC(ifp, ierrors, 1);
3194 emx_setup_rxdesc(current_desc, rx_buf);
3195 if (rdata->fmp != NULL) {
3196 m_freem(rdata->fmp);
3204 ifp->if_input(ifp, m, pi, cpuid);
3206 /* Advance our pointers to the next descriptor. */
3207 if (++i == rdata->num_rx_desc)
3210 current_desc = &rdata->rx_desc[i];
3211 staterr = le32toh(current_desc->rxd_staterr);
3213 rdata->next_rx_desc_to_check = i;
3215 /* Advance the E1000's Receive Queue "Tail Pointer". */
3217 i = rdata->num_rx_desc - 1;
3218 E1000_WRITE_REG(&rdata->sc->hw, E1000_RDT(rdata->idx), i);
3222 emx_enable_intr(struct emx_softc *sc)
3224 uint32_t ims_mask = IMS_ENABLE_MASK;
3226 lwkt_serialize_handler_enable(&sc->main_serialize);
3229 if (sc->hw.mac.type == e1000_82574) {
3230 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
3231 ims_mask |= EM_MSIX_MASK;
3234 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
3238 emx_disable_intr(struct emx_softc *sc)
3240 if (sc->hw.mac.type == e1000_82574)
3241 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
3242 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
3244 lwkt_serialize_handler_disable(&sc->main_serialize);
3248 * Bit of a misnomer, what this really means is
3249 * to enable OS management of the system... aka
3250 * to disable special hardware management features
3253 emx_get_mgmt(struct emx_softc *sc)
3255 /* A shared code workaround */
3256 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3257 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3258 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3260 /* disable hardware interception of ARP */
3261 manc &= ~(E1000_MANC_ARP_EN);
3263 /* enable receiving management packets to the host */
3264 manc |= E1000_MANC_EN_MNG2HOST;
3265 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3266 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3267 manc2h |= E1000_MNG2HOST_PORT_623;
3268 manc2h |= E1000_MNG2HOST_PORT_664;
3269 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3271 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3276 * Give control back to hardware management
3277 * controller if there is one.
3280 emx_rel_mgmt(struct emx_softc *sc)
3282 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3283 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3285 /* re-enable hardware interception of ARP */
3286 manc |= E1000_MANC_ARP_EN;
3287 manc &= ~E1000_MANC_EN_MNG2HOST;
3289 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3294 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3295 * For ASF and Pass Through versions of f/w this means that
3296 * the driver is loaded. For AMT version (only with 82573)
3297 * of the f/w this means that the network i/f is open.
3300 emx_get_hw_control(struct emx_softc *sc)
3302 /* Let firmware know the driver has taken over */
3303 if (sc->hw.mac.type == e1000_82573) {
3306 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3307 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3308 swsm | E1000_SWSM_DRV_LOAD);
3312 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3313 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3314 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3316 sc->flags |= EMX_FLAG_HW_CTRL;
3320 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3321 * For ASF and Pass Through versions of f/w this means that the
3322 * driver is no longer loaded. For AMT version (only with 82573)
3323 * of the f/w this means that the network i/f is closed.
3326 emx_rel_hw_control(struct emx_softc *sc)
3328 if ((sc->flags & EMX_FLAG_HW_CTRL) == 0)
3330 sc->flags &= ~EMX_FLAG_HW_CTRL;
3332 /* Let firmware taken over control of h/w */
3333 if (sc->hw.mac.type == e1000_82573) {
3336 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3337 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3338 swsm & ~E1000_SWSM_DRV_LOAD);
3342 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3343 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3344 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3349 emx_is_valid_eaddr(const uint8_t *addr)
3351 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3353 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3360 * Enable PCI Wake On Lan capability
3363 emx_enable_wol(device_t dev)
3365 uint16_t cap, status;
3368 /* First find the capabilities pointer*/
3369 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3371 /* Read the PM Capabilities */
3372 id = pci_read_config(dev, cap, 1);
3373 if (id != PCIY_PMG) /* Something wrong */
3377 * OK, we have the power capabilities,
3378 * so now get the status register
3380 cap += PCIR_POWER_STATUS;
3381 status = pci_read_config(dev, cap, 2);
3382 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3383 pci_write_config(dev, cap, status, 2);
3387 emx_update_stats(struct emx_softc *sc)
3389 struct ifnet *ifp = &sc->arpcom.ac_if;
3391 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3392 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3393 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3394 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3396 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3397 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3398 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3399 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3401 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3402 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3403 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3404 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3405 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3406 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3407 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3408 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3409 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3410 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3411 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3412 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3413 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3414 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3415 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3416 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3417 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3418 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3419 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3420 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3422 /* For the 64-bit byte counters the low dword must be read first. */
3423 /* Both registers clear on the read of the high dword */
3425 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3426 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3428 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3429 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3430 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3431 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3432 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3434 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3435 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3437 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3438 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3439 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3440 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3441 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3442 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3443 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3444 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3445 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3446 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3448 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3449 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3450 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3451 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3452 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3453 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3455 IFNET_STAT_SET(ifp, collisions, sc->stats.colc);
3458 IFNET_STAT_SET(ifp, ierrors,
3459 sc->stats.rxerrc + sc->stats.crcerrs + sc->stats.algnerrc +
3460 sc->stats.ruc + sc->stats.roc + sc->stats.mpc + sc->stats.cexterr);
3463 IFNET_STAT_SET(ifp, oerrors, sc->stats.ecol + sc->stats.latecol);
3467 emx_print_debug_info(struct emx_softc *sc)
3469 device_t dev = sc->dev;
3470 uint8_t *hw_addr = sc->hw.hw_addr;
3473 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3474 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3475 E1000_READ_REG(&sc->hw, E1000_CTRL),
3476 E1000_READ_REG(&sc->hw, E1000_RCTL));
3477 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3478 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3479 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3480 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3481 sc->hw.fc.high_water, sc->hw.fc.low_water);
3482 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3483 E1000_READ_REG(&sc->hw, E1000_TIDV),
3484 E1000_READ_REG(&sc->hw, E1000_TADV));
3485 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3486 E1000_READ_REG(&sc->hw, E1000_RDTR),
3487 E1000_READ_REG(&sc->hw, E1000_RADV));
3489 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3490 device_printf(dev, "hw %d tdh = %d, hw tdt = %d\n", i,
3491 E1000_READ_REG(&sc->hw, E1000_TDH(i)),
3492 E1000_READ_REG(&sc->hw, E1000_TDT(i)));
3494 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3495 device_printf(dev, "hw %d rdh = %d, hw rdt = %d\n", i,
3496 E1000_READ_REG(&sc->hw, E1000_RDH(i)),
3497 E1000_READ_REG(&sc->hw, E1000_RDT(i)));
3500 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3501 device_printf(dev, "TX %d Tx descriptors avail = %d\n", i,
3502 sc->tx_data[i].num_tx_desc_avail);
3503 device_printf(dev, "TX %d TSO segments = %lu\n", i,
3504 sc->tx_data[i].tso_segments);
3505 device_printf(dev, "TX %d TSO ctx reused = %lu\n", i,
3506 sc->tx_data[i].tso_ctx_reused);
3511 emx_print_hw_stats(struct emx_softc *sc)
3513 device_t dev = sc->dev;
3515 device_printf(dev, "Excessive collisions = %lld\n",
3516 (long long)sc->stats.ecol);
3517 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3518 device_printf(dev, "Symbol errors = %lld\n",
3519 (long long)sc->stats.symerrs);
3521 device_printf(dev, "Sequence errors = %lld\n",
3522 (long long)sc->stats.sec);
3523 device_printf(dev, "Defer count = %lld\n",
3524 (long long)sc->stats.dc);
3525 device_printf(dev, "Missed Packets = %lld\n",
3526 (long long)sc->stats.mpc);
3527 device_printf(dev, "Receive No Buffers = %lld\n",
3528 (long long)sc->stats.rnbc);
3529 /* RLEC is inaccurate on some hardware, calculate our own. */
3530 device_printf(dev, "Receive Length Errors = %lld\n",
3531 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3532 device_printf(dev, "Receive errors = %lld\n",
3533 (long long)sc->stats.rxerrc);
3534 device_printf(dev, "Crc errors = %lld\n",
3535 (long long)sc->stats.crcerrs);
3536 device_printf(dev, "Alignment errors = %lld\n",
3537 (long long)sc->stats.algnerrc);
3538 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3539 (long long)sc->stats.cexterr);
3540 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3541 device_printf(dev, "XON Rcvd = %lld\n",
3542 (long long)sc->stats.xonrxc);
3543 device_printf(dev, "XON Xmtd = %lld\n",
3544 (long long)sc->stats.xontxc);
3545 device_printf(dev, "XOFF Rcvd = %lld\n",
3546 (long long)sc->stats.xoffrxc);
3547 device_printf(dev, "XOFF Xmtd = %lld\n",
3548 (long long)sc->stats.xofftxc);
3549 device_printf(dev, "Good Packets Rcvd = %lld\n",
3550 (long long)sc->stats.gprc);
3551 device_printf(dev, "Good Packets Xmtd = %lld\n",
3552 (long long)sc->stats.gptc);
3556 emx_print_nvm_info(struct emx_softc *sc)
3558 uint16_t eeprom_data;
3561 /* Its a bit crude, but it gets the job done */
3562 kprintf("\nInterface EEPROM Dump:\n");
3563 kprintf("Offset\n0x0000 ");
3564 for (i = 0, j = 0; i < 32; i++, j++) {
3565 if (j == 8) { /* Make the offset block */
3567 kprintf("\n0x00%x0 ",row);
3569 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3570 kprintf("%04x ", eeprom_data);
3576 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3578 struct emx_softc *sc;
3583 error = sysctl_handle_int(oidp, &result, 0, req);
3584 if (error || !req->newptr)
3587 sc = (struct emx_softc *)arg1;
3588 ifp = &sc->arpcom.ac_if;
3590 ifnet_serialize_all(ifp);
3593 emx_print_debug_info(sc);
3596 * This value will cause a hex dump of the
3597 * first 32 16-bit words of the EEPROM to
3601 emx_print_nvm_info(sc);
3603 ifnet_deserialize_all(ifp);
3609 emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3614 error = sysctl_handle_int(oidp, &result, 0, req);
3615 if (error || !req->newptr)
3619 struct emx_softc *sc = (struct emx_softc *)arg1;
3620 struct ifnet *ifp = &sc->arpcom.ac_if;
3622 ifnet_serialize_all(ifp);
3623 emx_print_hw_stats(sc);
3624 ifnet_deserialize_all(ifp);
3630 emx_add_sysctl(struct emx_softc *sc)
3632 #if defined(EMX_RSS_DEBUG) || defined(EMX_TSS_DEBUG)
3637 sysctl_ctx_init(&sc->sysctl_ctx);
3638 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
3639 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
3640 device_get_nameunit(sc->dev),
3642 if (sc->sysctl_tree == NULL) {
3643 device_printf(sc->dev, "can't add sysctl node\n");
3647 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3648 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3649 emx_sysctl_debug_info, "I", "Debug Information");
3651 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3652 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3653 emx_sysctl_stats, "I", "Statistics");
3655 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3656 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_data[0].num_rx_desc, 0,
3658 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3659 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_data[0].num_tx_desc, 0,
3662 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3663 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3664 emx_sysctl_int_throttle, "I", "interrupt throttling rate");
3665 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3666 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3667 emx_sysctl_tx_intr_nsegs, "I", "# segments per TX interrupt");
3668 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3669 OID_AUTO, "tx_wreg_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3670 emx_sysctl_tx_wreg_nsegs, "I",
3671 "# segments sent before write to hardware register");
3673 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3674 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD, &sc->rx_ring_cnt, 0,
3676 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3677 OID_AUTO, "tx_ring_cnt", CTLFLAG_RD, &sc->tx_ring_cnt, 0,
3679 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3680 OID_AUTO, "tx_ring_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0,
3681 "# of TX rings used");
3683 #ifdef IFPOLL_ENABLE
3684 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3685 OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
3686 sc, 0, emx_sysctl_npoll_rxoff, "I",
3687 "NPOLLING RX cpu offset");
3688 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3689 OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
3690 sc, 0, emx_sysctl_npoll_txoff, "I",
3691 "NPOLLING TX cpu offset");
3694 #ifdef EMX_RSS_DEBUG
3695 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3696 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3697 0, "RSS debug level");
3698 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3699 ksnprintf(pkt_desc, sizeof(pkt_desc), "rx%d_pkt", i);
3700 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
3701 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
3702 pkt_desc, CTLFLAG_RW, &sc->rx_data[i].rx_pkts,
3706 #ifdef EMX_TSS_DEBUG
3707 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3708 ksnprintf(pkt_desc, sizeof(pkt_desc), "tx%d_pkt", i);
3709 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
3710 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
3711 pkt_desc, CTLFLAG_RW, &sc->tx_data[i].tx_pkts,
3718 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3720 struct emx_softc *sc = (void *)arg1;
3721 struct ifnet *ifp = &sc->arpcom.ac_if;
3722 int error, throttle;
3724 throttle = sc->int_throttle_ceil;
3725 error = sysctl_handle_int(oidp, &throttle, 0, req);
3726 if (error || req->newptr == NULL)
3728 if (throttle < 0 || throttle > 1000000000 / 256)
3733 * Set the interrupt throttling rate in 256ns increments,
3734 * recalculate sysctl value assignment to get exact frequency.
3736 throttle = 1000000000 / 256 / throttle;
3738 /* Upper 16bits of ITR is reserved and should be zero */
3739 if (throttle & 0xffff0000)
3743 ifnet_serialize_all(ifp);
3746 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3748 sc->int_throttle_ceil = 0;
3750 if (ifp->if_flags & IFF_RUNNING)
3751 emx_set_itr(sc, throttle);
3753 ifnet_deserialize_all(ifp);
3756 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3757 sc->int_throttle_ceil);
3763 emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3765 struct emx_softc *sc = (void *)arg1;
3766 struct ifnet *ifp = &sc->arpcom.ac_if;
3767 struct emx_txdata *tdata = &sc->tx_data[0];
3770 segs = tdata->tx_intr_nsegs;
3771 error = sysctl_handle_int(oidp, &segs, 0, req);
3772 if (error || req->newptr == NULL)
3777 ifnet_serialize_all(ifp);
3780 * Don't allow tx_intr_nsegs to become:
3781 * o Less the oact_tx_desc
3782 * o Too large that no TX desc will cause TX interrupt to
3783 * be generated (OACTIVE will never recover)
3784 * o Too small that will cause tx_dd[] overflow
3786 if (segs < tdata->oact_tx_desc ||
3787 segs >= tdata->num_tx_desc - tdata->oact_tx_desc ||
3788 segs < tdata->num_tx_desc / EMX_TXDD_SAFE) {
3794 for (i = 0; i < sc->tx_ring_cnt; ++i)
3795 sc->tx_data[i].tx_intr_nsegs = segs;
3798 ifnet_deserialize_all(ifp);
3804 emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3806 struct emx_softc *sc = (void *)arg1;
3807 struct ifnet *ifp = &sc->arpcom.ac_if;
3808 int error, nsegs, i;
3810 nsegs = sc->tx_data[0].tx_wreg_nsegs;
3811 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3812 if (error || req->newptr == NULL)
3815 ifnet_serialize_all(ifp);
3816 for (i = 0; i < sc->tx_ring_cnt; ++i)
3817 sc->tx_data[i].tx_wreg_nsegs =nsegs;
3818 ifnet_deserialize_all(ifp);
3823 #ifdef IFPOLL_ENABLE
3826 emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3828 struct emx_softc *sc = (void *)arg1;
3829 struct ifnet *ifp = &sc->arpcom.ac_if;
3832 off = sc->rx_npoll_off;
3833 error = sysctl_handle_int(oidp, &off, 0, req);
3834 if (error || req->newptr == NULL)
3839 ifnet_serialize_all(ifp);
3840 if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3844 sc->rx_npoll_off = off;
3846 ifnet_deserialize_all(ifp);
3852 emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3854 struct emx_softc *sc = (void *)arg1;
3855 struct ifnet *ifp = &sc->arpcom.ac_if;
3858 off = sc->tx_npoll_off;
3859 error = sysctl_handle_int(oidp, &off, 0, req);
3860 if (error || req->newptr == NULL)
3865 ifnet_serialize_all(ifp);
3866 if (off >= ncpus2 || off % sc->tx_ring_cnt != 0) {
3870 sc->tx_npoll_off = off;
3872 ifnet_deserialize_all(ifp);
3877 #endif /* IFPOLL_ENABLE */
3880 emx_dma_alloc(struct emx_softc *sc)
3885 * Create top level busdma tag
3887 error = bus_dma_tag_create(NULL, 1, 0,
3888 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3890 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3891 0, &sc->parent_dtag);
3893 device_printf(sc->dev, "could not create top level DMA tag\n");
3898 * Allocate transmit descriptors ring and buffers
3900 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3901 error = emx_create_tx_ring(&sc->tx_data[i]);
3903 device_printf(sc->dev,
3904 "Could not setup transmit structures\n");
3910 * Allocate receive descriptors ring and buffers
3912 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3913 error = emx_create_rx_ring(&sc->rx_data[i]);
3915 device_printf(sc->dev,
3916 "Could not setup receive structures\n");
3924 emx_dma_free(struct emx_softc *sc)
3928 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3929 emx_destroy_tx_ring(&sc->tx_data[i],
3930 sc->tx_data[i].num_tx_desc);
3933 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3934 emx_destroy_rx_ring(&sc->rx_data[i],
3935 sc->rx_data[i].num_rx_desc);
3938 /* Free top level busdma tag */
3939 if (sc->parent_dtag != NULL)
3940 bus_dma_tag_destroy(sc->parent_dtag);
3944 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3946 struct emx_softc *sc = ifp->if_softc;
3948 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, slz);
3952 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3954 struct emx_softc *sc = ifp->if_softc;
3956 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, slz);
3960 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3962 struct emx_softc *sc = ifp->if_softc;
3964 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE, slz);
3968 emx_serialize_skipmain(struct emx_softc *sc)
3970 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3974 emx_deserialize_skipmain(struct emx_softc *sc)
3976 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3982 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3983 boolean_t serialized)
3985 struct emx_softc *sc = ifp->if_softc;
3987 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE,
3991 #endif /* INVARIANTS */
3993 #ifdef IFPOLL_ENABLE
3996 emx_npoll_status(struct ifnet *ifp)
3998 struct emx_softc *sc = ifp->if_softc;
4001 ASSERT_SERIALIZED(&sc->main_serialize);
4003 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
4004 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4005 callout_stop(&sc->timer);
4006 sc->hw.mac.get_link_status = 1;
4007 emx_update_link_status(sc);
4008 callout_reset(&sc->timer, hz, emx_timer, sc);
4013 emx_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
4015 struct emx_txdata *tdata = arg;
4017 ASSERT_SERIALIZED(&tdata->tx_serialize);
4020 if (!ifsq_is_empty(tdata->ifsq))
4021 ifsq_devstart(tdata->ifsq);
4025 emx_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
4027 struct emx_rxdata *rdata = arg;
4029 ASSERT_SERIALIZED(&rdata->rx_serialize);
4031 emx_rxeof(rdata, cycle);
4035 emx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
4037 struct emx_softc *sc = ifp->if_softc;
4040 ASSERT_IFNET_SERIALIZED_ALL(ifp);
4045 info->ifpi_status.status_func = emx_npoll_status;
4046 info->ifpi_status.serializer = &sc->main_serialize;
4048 txr_cnt = emx_get_txring_inuse(sc, TRUE);
4049 off = sc->tx_npoll_off;
4050 for (i = 0; i < txr_cnt; ++i) {
4051 struct emx_txdata *tdata = &sc->tx_data[i];
4054 KKASSERT(idx < ncpus2);
4055 info->ifpi_tx[idx].poll_func = emx_npoll_tx;
4056 info->ifpi_tx[idx].arg = tdata;
4057 info->ifpi_tx[idx].serializer = &tdata->tx_serialize;
4058 ifsq_set_cpuid(tdata->ifsq, idx);
4061 off = sc->rx_npoll_off;
4062 for (i = 0; i < sc->rx_ring_cnt; ++i) {
4063 struct emx_rxdata *rdata = &sc->rx_data[i];
4066 KKASSERT(idx < ncpus2);
4067 info->ifpi_rx[idx].poll_func = emx_npoll_rx;
4068 info->ifpi_rx[idx].arg = rdata;
4069 info->ifpi_rx[idx].serializer = &rdata->rx_serialize;
4072 if (ifp->if_flags & IFF_RUNNING) {
4073 if (txr_cnt == sc->tx_ring_inuse)
4074 emx_disable_intr(sc);
4079 for (i = 0; i < sc->tx_ring_cnt; ++i) {
4080 struct emx_txdata *tdata = &sc->tx_data[i];
4082 ifsq_set_cpuid(tdata->ifsq,
4083 rman_get_cpuid(sc->intr_res));
4086 if (ifp->if_flags & IFF_RUNNING) {
4087 txr_cnt = emx_get_txring_inuse(sc, FALSE);
4088 if (txr_cnt == sc->tx_ring_inuse)
4089 emx_enable_intr(sc);
4096 #endif /* IFPOLL_ENABLE */
4099 emx_set_itr(struct emx_softc *sc, uint32_t itr)
4101 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr);
4102 if (sc->hw.mac.type == e1000_82574) {
4106 * When using MSIX interrupts we need to
4107 * throttle using the EITR register
4109 for (i = 0; i < 4; ++i)
4110 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr);
4115 * Disable the L0s, 82574L Errata #20
4118 emx_disable_aspm(struct emx_softc *sc)
4120 uint16_t link_cap, link_ctrl, disable;
4121 uint8_t pcie_ptr, reg;
4122 device_t dev = sc->dev;
4124 switch (sc->hw.mac.type) {
4129 * 82573 specification update
4130 * errata #8 disable L0s
4131 * errata #41 disable L1
4133 * 82571/82572 specification update
4134 # errata #13 disable L1
4135 * errata #68 disable L0s
4137 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1;
4142 * 82574 specification update errata #20
4144 * There is no need to disable L1
4146 disable = PCIEM_LNKCTL_ASPM_L0S;
4153 pcie_ptr = pci_get_pciecap_ptr(dev);
4157 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2);
4158 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0)
4162 if_printf(&sc->arpcom.ac_if, "disable ASPM %#02x\n", disable);
4164 reg = pcie_ptr + PCIER_LINKCTRL;
4165 link_ctrl = pci_read_config(dev, reg, 2);
4166 link_ctrl &= ~disable;
4167 pci_write_config(dev, reg, link_ctrl, 2);
4171 emx_tso_pullup(struct emx_txdata *tdata, struct mbuf **mp)
4173 int iphlen, hoff, thoff, ex = 0;
4178 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4180 iphlen = m->m_pkthdr.csum_iphlen;
4181 thoff = m->m_pkthdr.csum_thlen;
4182 hoff = m->m_pkthdr.csum_lhlen;
4184 KASSERT(iphlen > 0, ("invalid ip hlen"));
4185 KASSERT(thoff > 0, ("invalid tcp hlen"));
4186 KASSERT(hoff > 0, ("invalid ether hlen"));
4188 if (tdata->tx_flags & EMX_TXFLAG_TSO_PULLEX)
4191 if (m->m_len < hoff + iphlen + thoff + ex) {
4192 m = m_pullup(m, hoff + iphlen + thoff + ex);
4199 ip = mtodoff(m, struct ip *, hoff);
4206 emx_tso_setup(struct emx_txdata *tdata, struct mbuf *mp,
4207 uint32_t *txd_upper, uint32_t *txd_lower)
4209 struct e1000_context_desc *TXD;
4210 int hoff, iphlen, thoff, hlen;
4211 int mss, pktlen, curr_txd;
4213 #ifdef EMX_TSO_DEBUG
4214 tdata->tso_segments++;
4217 iphlen = mp->m_pkthdr.csum_iphlen;
4218 thoff = mp->m_pkthdr.csum_thlen;
4219 hoff = mp->m_pkthdr.csum_lhlen;
4220 mss = mp->m_pkthdr.tso_segsz;
4221 pktlen = mp->m_pkthdr.len;
4223 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 &&
4224 tdata->csum_flags == CSUM_TSO &&
4225 tdata->csum_iphlen == iphlen &&
4226 tdata->csum_lhlen == hoff &&
4227 tdata->csum_thlen == thoff &&
4228 tdata->csum_mss == mss &&
4229 tdata->csum_pktlen == pktlen) {
4230 *txd_upper = tdata->csum_txd_upper;
4231 *txd_lower = tdata->csum_txd_lower;
4232 #ifdef EMX_TSO_DEBUG
4233 tdata->tso_ctx_reused++;
4237 hlen = hoff + iphlen + thoff;
4240 * Setup a new TSO context.
4243 curr_txd = tdata->next_avail_tx_desc;
4244 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd];
4246 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
4247 E1000_TXD_DTYP_D | /* Data descr type */
4248 E1000_TXD_CMD_TSE; /* Do TSE on this packet */
4250 /* IP and/or TCP header checksum calculation and insertion. */
4251 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8;
4254 * Start offset for header checksum calculation.
4255 * End offset for header checksum calculation.
4256 * Offset of place put the checksum.
4258 TXD->lower_setup.ip_fields.ipcss = hoff;
4259 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1);
4260 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum);
4263 * Start offset for payload checksum calculation.
4264 * End offset for payload checksum calculation.
4265 * Offset of place to put the checksum.
4267 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen;
4268 TXD->upper_setup.tcp_fields.tucse = 0;
4269 TXD->upper_setup.tcp_fields.tucso =
4270 hoff + iphlen + offsetof(struct tcphdr, th_sum);
4273 * Payload size per packet w/o any headers.
4274 * Length of all headers up to payload.
4276 TXD->tcp_seg_setup.fields.mss = htole16(mss);
4277 TXD->tcp_seg_setup.fields.hdr_len = hlen;
4278 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS |
4279 E1000_TXD_CMD_DEXT | /* Extended descr */
4280 E1000_TXD_CMD_TSE | /* TSE context */
4281 E1000_TXD_CMD_IP | /* Do IP csum */
4282 E1000_TXD_CMD_TCP | /* Do TCP checksum */
4283 (pktlen - hlen)); /* Total len */
4285 /* Save the information for this TSO context */
4286 tdata->csum_flags = CSUM_TSO;
4287 tdata->csum_lhlen = hoff;
4288 tdata->csum_iphlen = iphlen;
4289 tdata->csum_thlen = thoff;
4290 tdata->csum_mss = mss;
4291 tdata->csum_pktlen = pktlen;
4292 tdata->csum_txd_upper = *txd_upper;
4293 tdata->csum_txd_lower = *txd_lower;
4295 if (++curr_txd == tdata->num_tx_desc)
4298 KKASSERT(tdata->num_tx_desc_avail > 0);
4299 tdata->num_tx_desc_avail--;
4301 tdata->next_avail_tx_desc = curr_txd;
4306 emx_get_txring_inuse(const struct emx_softc *sc, boolean_t polling)
4309 return sc->tx_ring_cnt;