igb: Use kmalloc_cachealign to allocate rx ring, tx ring and msix data
[dragonfly.git] / sys / dev / netif / igb / if_igb.c
1 /*
2  * Copyright (c) 2001-2011, Intel Corporation 
3  * All rights reserved.
4  * 
5  * Redistribution and use in source and binary forms, with or without 
6  * modification, are permitted provided that the following conditions are met:
7  * 
8  *  1. Redistributions of source code must retain the above copyright notice, 
9  *     this list of conditions and the following disclaimer.
10  * 
11  *  2. Redistributions in binary form must reproduce the above copyright 
12  *     notice, this list of conditions and the following disclaimer in the 
13  *     documentation and/or other materials provided with the distribution.
14  * 
15  *  3. Neither the name of the Intel Corporation nor the names of its 
16  *     contributors may be used to endorse or promote products derived from 
17  *     this software without specific prior written permission.
18  * 
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31
32 #include "opt_ifpoll.h"
33 #include "opt_igb.h"
34
35 #include <sys/param.h>
36 #include <sys/bus.h>
37 #include <sys/endian.h>
38 #include <sys/interrupt.h>
39 #include <sys/kernel.h>
40 #include <sys/malloc.h>
41 #include <sys/mbuf.h>
42 #include <sys/proc.h>
43 #include <sys/rman.h>
44 #include <sys/serialize.h>
45 #include <sys/serialize2.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
49 #include <sys/systm.h>
50
51 #include <net/bpf.h>
52 #include <net/ethernet.h>
53 #include <net/if.h>
54 #include <net/if_arp.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/ifq_var.h>
58 #include <net/toeplitz.h>
59 #include <net/toeplitz2.h>
60 #include <net/vlan/if_vlan_var.h>
61 #include <net/vlan/if_vlan_ether.h>
62 #include <net/if_poll.h>
63
64 #include <netinet/in_systm.h>
65 #include <netinet/in.h>
66 #include <netinet/ip.h>
67 #include <netinet/tcp.h>
68 #include <netinet/udp.h>
69
70 #include <bus/pci/pcivar.h>
71 #include <bus/pci/pcireg.h>
72
73 #include <dev/netif/ig_hal/e1000_api.h>
74 #include <dev/netif/ig_hal/e1000_82575.h>
75 #include <dev/netif/igb/if_igb.h>
76
77 #ifdef IGB_RSS_DEBUG
78 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
79 do { \
80         if (sc->rss_debug >= lvl) \
81                 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
82 } while (0)
83 #else   /* !IGB_RSS_DEBUG */
84 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
85 #endif  /* IGB_RSS_DEBUG */
86
87 #define IGB_NAME        "Intel(R) PRO/1000 "
88 #define IGB_DEVICE(id)  \
89         { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
90 #define IGB_DEVICE_NULL { 0, 0, NULL }
91
92 static struct igb_device {
93         uint16_t        vid;
94         uint16_t        did;
95         const char      *desc;
96 } igb_devices[] = {
97         IGB_DEVICE(82575EB_COPPER),
98         IGB_DEVICE(82575EB_FIBER_SERDES),
99         IGB_DEVICE(82575GB_QUAD_COPPER),
100         IGB_DEVICE(82576),
101         IGB_DEVICE(82576_NS),
102         IGB_DEVICE(82576_NS_SERDES),
103         IGB_DEVICE(82576_FIBER),
104         IGB_DEVICE(82576_SERDES),
105         IGB_DEVICE(82576_SERDES_QUAD),
106         IGB_DEVICE(82576_QUAD_COPPER),
107         IGB_DEVICE(82576_QUAD_COPPER_ET2),
108         IGB_DEVICE(82576_VF),
109         IGB_DEVICE(82580_COPPER),
110         IGB_DEVICE(82580_FIBER),
111         IGB_DEVICE(82580_SERDES),
112         IGB_DEVICE(82580_SGMII),
113         IGB_DEVICE(82580_COPPER_DUAL),
114         IGB_DEVICE(82580_QUAD_FIBER),
115         IGB_DEVICE(DH89XXCC_SERDES),
116         IGB_DEVICE(DH89XXCC_SGMII),
117         IGB_DEVICE(DH89XXCC_SFP),
118         IGB_DEVICE(DH89XXCC_BACKPLANE),
119         IGB_DEVICE(I350_COPPER),
120         IGB_DEVICE(I350_FIBER),
121         IGB_DEVICE(I350_SERDES),
122         IGB_DEVICE(I350_SGMII),
123         IGB_DEVICE(I350_VF),
124
125         /* required last entry */
126         IGB_DEVICE_NULL
127 };
128
129 static int      igb_probe(device_t);
130 static int      igb_attach(device_t);
131 static int      igb_detach(device_t);
132 static int      igb_shutdown(device_t);
133 static int      igb_suspend(device_t);
134 static int      igb_resume(device_t);
135
136 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
137 static void     igb_setup_ifp(struct igb_softc *);
138 static boolean_t igb_txcsum_ctx(struct igb_tx_ring *, struct mbuf *);
139 static int      igb_tso_pullup(struct igb_tx_ring *, struct mbuf **);
140 static void     igb_tso_ctx(struct igb_tx_ring *, struct mbuf *, uint32_t *);
141 static void     igb_add_sysctl(struct igb_softc *);
142 static int      igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
143 static int      igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
144 static int      igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
145 static void     igb_set_ring_inuse(struct igb_softc *, boolean_t);
146 #ifdef IFPOLL_ENABLE
147 static int      igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
148 static int      igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
149 #endif
150
151 static void     igb_vf_init_stats(struct igb_softc *);
152 static void     igb_reset(struct igb_softc *);
153 static void     igb_update_stats_counters(struct igb_softc *);
154 static void     igb_update_vf_stats_counters(struct igb_softc *);
155 static void     igb_update_link_status(struct igb_softc *);
156 static void     igb_init_tx_unit(struct igb_softc *);
157 static void     igb_init_rx_unit(struct igb_softc *);
158
159 static void     igb_set_vlan(struct igb_softc *);
160 static void     igb_set_multi(struct igb_softc *);
161 static void     igb_set_promisc(struct igb_softc *);
162 static void     igb_disable_promisc(struct igb_softc *);
163
164 static int      igb_alloc_rings(struct igb_softc *);
165 static void     igb_free_rings(struct igb_softc *);
166 static int      igb_create_tx_ring(struct igb_tx_ring *);
167 static int      igb_create_rx_ring(struct igb_rx_ring *);
168 static void     igb_free_tx_ring(struct igb_tx_ring *);
169 static void     igb_free_rx_ring(struct igb_rx_ring *);
170 static void     igb_destroy_tx_ring(struct igb_tx_ring *, int);
171 static void     igb_destroy_rx_ring(struct igb_rx_ring *, int);
172 static void     igb_init_tx_ring(struct igb_tx_ring *);
173 static int      igb_init_rx_ring(struct igb_rx_ring *);
174 static int      igb_newbuf(struct igb_rx_ring *, int, boolean_t);
175 static int      igb_encap(struct igb_tx_ring *, struct mbuf **);
176
177 static void     igb_stop(struct igb_softc *);
178 static void     igb_init(void *);
179 static int      igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
180 static void     igb_media_status(struct ifnet *, struct ifmediareq *);
181 static int      igb_media_change(struct ifnet *);
182 static void     igb_timer(void *);
183 static void     igb_watchdog(struct ifnet *);
184 static void     igb_start(struct ifnet *);
185 #ifdef IFPOLL_ENABLE
186 static void     igb_npoll(struct ifnet *, struct ifpoll_info *);
187 static void     igb_npoll_rx(struct ifnet *, void *, int);
188 static void     igb_npoll_tx(struct ifnet *, void *, int);
189 static void     igb_npoll_status(struct ifnet *, int);
190 #endif
191 static void     igb_serialize(struct ifnet *, enum ifnet_serialize);
192 static void     igb_deserialize(struct ifnet *, enum ifnet_serialize);
193 static int      igb_tryserialize(struct ifnet *, enum ifnet_serialize);
194 #ifdef INVARIANTS
195 static void     igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
196                     boolean_t);
197 #endif
198
199 static void     igb_intr(void *);
200 static void     igb_intr_shared(void *);
201 static void     igb_rxeof(struct igb_rx_ring *, int);
202 static void     igb_txeof(struct igb_tx_ring *);
203 static void     igb_set_eitr(struct igb_softc *, int, int);
204 static void     igb_enable_intr(struct igb_softc *);
205 static void     igb_disable_intr(struct igb_softc *);
206 static void     igb_init_unshared_intr(struct igb_softc *);
207 static void     igb_init_intr(struct igb_softc *);
208 static int      igb_setup_intr(struct igb_softc *);
209 static void     igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
210 static void     igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
211 static void     igb_set_intr_mask(struct igb_softc *);
212 static int      igb_alloc_intr(struct igb_softc *);
213 static void     igb_free_intr(struct igb_softc *);
214 static void     igb_teardown_intr(struct igb_softc *);
215 static void     igb_msix_try_alloc(struct igb_softc *);
216 static void     igb_msix_free(struct igb_softc *, boolean_t);
217 static int      igb_msix_setup(struct igb_softc *);
218 static void     igb_msix_teardown(struct igb_softc *, int);
219 static void     igb_msix_rx(void *);
220 static void     igb_msix_tx(void *);
221 static void     igb_msix_status(void *);
222
223 /* Management and WOL Support */
224 static void     igb_get_mgmt(struct igb_softc *);
225 static void     igb_rel_mgmt(struct igb_softc *);
226 static void     igb_get_hw_control(struct igb_softc *);
227 static void     igb_rel_hw_control(struct igb_softc *);
228 static void     igb_enable_wol(device_t);
229
230 static device_method_t igb_methods[] = {
231         /* Device interface */
232         DEVMETHOD(device_probe,         igb_probe),
233         DEVMETHOD(device_attach,        igb_attach),
234         DEVMETHOD(device_detach,        igb_detach),
235         DEVMETHOD(device_shutdown,      igb_shutdown),
236         DEVMETHOD(device_suspend,       igb_suspend),
237         DEVMETHOD(device_resume,        igb_resume),
238         { 0, 0 }
239 };
240
241 static driver_t igb_driver = {
242         "igb",
243         igb_methods,
244         sizeof(struct igb_softc),
245 };
246
247 static devclass_t igb_devclass;
248
249 DECLARE_DUMMY_MODULE(if_igb);
250 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
251 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
252
253 static int      igb_rxd = IGB_DEFAULT_RXD;
254 static int      igb_txd = IGB_DEFAULT_TXD;
255 static int      igb_rxr = 0;
256 static int      igb_msi_enable = 1;
257 static int      igb_msix_enable = 1;
258 static int      igb_eee_disabled = 1;   /* Energy Efficient Ethernet */
259 static int      igb_fc_setting = e1000_fc_full;
260
261 /*
262  * DMA Coalescing, only for i350 - default to off,
263  * this feature is for power savings
264  */
265 static int      igb_dma_coalesce = 0;
266
267 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
268 TUNABLE_INT("hw.igb.txd", &igb_txd);
269 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
270 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
271 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
272 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
273
274 /* i350 specific */
275 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
276 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
277
278 static __inline void
279 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
280 {
281         /* Ignore Checksum bit is set */
282         if (staterr & E1000_RXD_STAT_IXSM)
283                 return;
284
285         if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
286             E1000_RXD_STAT_IPCS)
287                 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
288
289         if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
290                 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
291                         mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
292                             CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
293                         mp->m_pkthdr.csum_data = htons(0xffff);
294                 }
295         }
296 }
297
298 static __inline struct pktinfo *
299 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
300     uint32_t hash, uint32_t hashtype, uint32_t staterr)
301 {
302         switch (hashtype) {
303         case E1000_RXDADV_RSSTYPE_IPV4_TCP:
304                 pi->pi_netisr = NETISR_IP;
305                 pi->pi_flags = 0;
306                 pi->pi_l3proto = IPPROTO_TCP;
307                 break;
308
309         case E1000_RXDADV_RSSTYPE_IPV4:
310                 if (staterr & E1000_RXD_STAT_IXSM)
311                         return NULL;
312
313                 if ((staterr &
314                      (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
315                     E1000_RXD_STAT_TCPCS) {
316                         pi->pi_netisr = NETISR_IP;
317                         pi->pi_flags = 0;
318                         pi->pi_l3proto = IPPROTO_UDP;
319                         break;
320                 }
321                 /* FALL THROUGH */
322         default:
323                 return NULL;
324         }
325
326         m->m_flags |= M_HASH;
327         m->m_pkthdr.hash = toeplitz_hash(hash);
328         return pi;
329 }
330
331 static int
332 igb_probe(device_t dev)
333 {
334         const struct igb_device *d;
335         uint16_t vid, did;
336
337         vid = pci_get_vendor(dev);
338         did = pci_get_device(dev);
339
340         for (d = igb_devices; d->desc != NULL; ++d) {
341                 if (vid == d->vid && did == d->did) {
342                         device_set_desc(dev, d->desc);
343                         return 0;
344                 }
345         }
346         return ENXIO;
347 }
348
349 static int
350 igb_attach(device_t dev)
351 {
352         struct igb_softc *sc = device_get_softc(dev);
353         uint16_t eeprom_data;
354         int error = 0, i, j, ring_max;
355 #ifdef IFPOLL_ENABLE
356         int offset, offset_def;
357 #endif
358
359 #ifdef notyet
360         /* SYSCTL stuff */
361         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
362             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
363             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
364             igb_sysctl_nvm_info, "I", "NVM Information");
365         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
366             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
367             OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
368             adapter, 0, igb_set_flowcntl, "I", "Flow Control");
369 #endif
370
371         callout_init_mp(&sc->timer);
372         lwkt_serialize_init(&sc->main_serialize);
373
374         if_initname(&sc->arpcom.ac_if, device_get_name(dev),
375             device_get_unit(dev));
376         sc->dev = sc->osdep.dev = dev;
377
378         /*
379          * Determine hardware and mac type
380          */
381         sc->hw.vendor_id = pci_get_vendor(dev);
382         sc->hw.device_id = pci_get_device(dev);
383         sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
384         sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
385         sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
386
387         if (e1000_set_mac_type(&sc->hw))
388                 return ENXIO;
389
390         /* Are we a VF device? */
391         if (sc->hw.mac.type == e1000_vfadapt ||
392             sc->hw.mac.type == e1000_vfadapt_i350)
393                 sc->vf_ifp = 1;
394         else
395                 sc->vf_ifp = 0;
396
397         /*
398          * Configure total supported RX/TX ring count
399          */
400         switch (sc->hw.mac.type) {
401         case e1000_82575:
402                 ring_max = IGB_MAX_RING_82575;
403                 break;
404         case e1000_82580:
405                 ring_max = IGB_MAX_RING_82580;
406                 break;
407         case e1000_i350:
408                 ring_max = IGB_MAX_RING_I350;
409                 break;
410         case e1000_82576:
411                 ring_max = IGB_MAX_RING_82576;
412                 break;
413         default:
414                 ring_max = IGB_MIN_RING;
415                 break;
416         }
417         sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
418         sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
419 #ifdef IGB_RSS_DEBUG
420         sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
421 #endif
422         sc->rx_ring_inuse = sc->rx_ring_cnt;
423         sc->tx_ring_cnt = 1; /* XXX */
424
425         if (sc->hw.mac.type == e1000_82575)
426                 sc->flags |= IGB_FLAG_TSO_IPLEN0;
427
428         /* Enable bus mastering */
429         pci_enable_busmaster(dev);
430
431         /*
432          * Allocate IO memory
433          */
434         sc->mem_rid = PCIR_BAR(0);
435         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
436             RF_ACTIVE);
437         if (sc->mem_res == NULL) {
438                 device_printf(dev, "Unable to allocate bus resource: memory\n");
439                 error = ENXIO;
440                 goto failed;
441         }
442         sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
443         sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
444
445         sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
446
447         /* Save PCI command register for Shared Code */
448         sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
449         sc->hw.back = &sc->osdep;
450
451         /* Do Shared Code initialization */
452         if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
453                 device_printf(dev, "Setup of Shared code failed\n");
454                 error = ENXIO;
455                 goto failed;
456         }
457
458         e1000_get_bus_info(&sc->hw);
459
460         sc->hw.mac.autoneg = DO_AUTO_NEG;
461         sc->hw.phy.autoneg_wait_to_complete = FALSE;
462         sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
463
464         /* Copper options */
465         if (sc->hw.phy.media_type == e1000_media_type_copper) {
466                 sc->hw.phy.mdix = AUTO_ALL_MODES;
467                 sc->hw.phy.disable_polarity_correction = FALSE;
468                 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
469         }
470
471         /* Set the frame limits assuming  standard ethernet sized frames. */
472         sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
473
474         /* Allocate RX/TX rings */
475         error = igb_alloc_rings(sc);
476         if (error)
477                 goto failed;
478
479 #ifdef IFPOLL_ENABLE
480         /*
481          * NPOLLING RX CPU offset
482          */
483         if (sc->rx_ring_cnt == ncpus2) {
484                 offset = 0;
485         } else {
486                 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
487                 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
488                 if (offset >= ncpus2 ||
489                     offset % sc->rx_ring_cnt != 0) {
490                         device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
491                             offset, offset_def);
492                         offset = offset_def;
493                 }
494         }
495         sc->rx_npoll_off = offset;
496
497         /*
498          * NPOLLING TX CPU offset
499          */
500         offset_def = sc->rx_npoll_off;
501         offset = device_getenv_int(dev, "npoll.txoff", offset_def);
502         if (offset >= ncpus2) {
503                 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
504                     offset, offset_def);
505                 offset = offset_def;
506         }
507         sc->tx_npoll_off = offset;
508 #endif
509
510         /* Allocate interrupt */
511         error = igb_alloc_intr(sc);
512         if (error)
513                 goto failed;
514
515         /*
516          * Setup serializers
517          */
518         i = 0;
519         sc->serializes[i++] = &sc->main_serialize;
520
521         sc->tx_serialize = i;
522         for (j = 0; j < sc->tx_ring_cnt; ++j)
523                 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
524
525         sc->rx_serialize = i;
526         for (j = 0; j < sc->rx_ring_cnt; ++j)
527                 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
528
529         sc->serialize_cnt = i;
530         KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
531
532         /* Allocate the appropriate stats memory */
533         if (sc->vf_ifp) {
534                 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
535                     M_WAITOK | M_ZERO);
536                 igb_vf_init_stats(sc);
537         } else {
538                 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
539                     M_WAITOK | M_ZERO);
540         }
541
542         /* Allocate multicast array memory. */
543         sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
544             M_DEVBUF, M_WAITOK);
545
546         /* Some adapter-specific advanced features */
547         if (sc->hw.mac.type >= e1000_i350) {
548 #ifdef notyet
549                 igb_set_sysctl_value(adapter, "dma_coalesce",
550                     "configure dma coalesce",
551                     &adapter->dma_coalesce, igb_dma_coalesce);
552                 igb_set_sysctl_value(adapter, "eee_disabled",
553                     "enable Energy Efficient Ethernet",
554                     &adapter->hw.dev_spec._82575.eee_disable,
555                     igb_eee_disabled);
556 #else
557                 sc->dma_coalesce = igb_dma_coalesce;
558                 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
559 #endif
560                 e1000_set_eee_i350(&sc->hw);
561         }
562
563         /*
564          * Start from a known state, this is important in reading the nvm and
565          * mac from that.
566          */
567         e1000_reset_hw(&sc->hw);
568
569         /* Make sure we have a good EEPROM before we read from it */
570         if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
571                 /*
572                  * Some PCI-E parts fail the first check due to
573                  * the link being in sleep state, call it again,
574                  * if it fails a second time its a real issue.
575                  */
576                 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
577                         device_printf(dev,
578                             "The EEPROM Checksum Is Not Valid\n");
579                         error = EIO;
580                         goto failed;
581                 }
582         }
583
584         /* Copy the permanent MAC address out of the EEPROM */
585         if (e1000_read_mac_addr(&sc->hw) < 0) {
586                 device_printf(dev, "EEPROM read error while reading MAC"
587                     " address\n");
588                 error = EIO;
589                 goto failed;
590         }
591         if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
592                 device_printf(dev, "Invalid MAC address\n");
593                 error = EIO;
594                 goto failed;
595         }
596
597         /* Setup OS specific network interface */
598         igb_setup_ifp(sc);
599
600         /* Add sysctl tree, must after igb_setup_ifp() */
601         igb_add_sysctl(sc);
602
603         /* Now get a good starting state */
604         igb_reset(sc);
605
606         /* Initialize statistics */
607         igb_update_stats_counters(sc);
608
609         sc->hw.mac.get_link_status = 1;
610         igb_update_link_status(sc);
611
612         /* Indicate SOL/IDER usage */
613         if (e1000_check_reset_block(&sc->hw)) {
614                 device_printf(dev,
615                     "PHY reset is blocked due to SOL/IDER session.\n");
616         }
617
618         /* Determine if we have to control management hardware */
619         if (e1000_enable_mng_pass_thru(&sc->hw))
620                 sc->flags |= IGB_FLAG_HAS_MGMT;
621
622         /*
623          * Setup Wake-on-Lan
624          */
625         /* APME bit in EEPROM is mapped to WUC.APME */
626         eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
627         if (eeprom_data)
628                 sc->wol = E1000_WUFC_MAG;
629         /* XXX disable WOL */
630         sc->wol = 0; 
631
632 #ifdef notyet
633         /* Register for VLAN events */
634         adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
635              igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
636         adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
637              igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
638 #endif
639
640 #ifdef notyet
641         igb_add_hw_stats(adapter);
642 #endif
643
644         error = igb_setup_intr(sc);
645         if (error) {
646                 ether_ifdetach(&sc->arpcom.ac_if);
647                 goto failed;
648         }
649         return 0;
650
651 failed:
652         igb_detach(dev);
653         return error;
654 }
655
656 static int
657 igb_detach(device_t dev)
658 {
659         struct igb_softc *sc = device_get_softc(dev);
660
661         if (device_is_attached(dev)) {
662                 struct ifnet *ifp = &sc->arpcom.ac_if;
663
664                 ifnet_serialize_all(ifp);
665
666                 igb_stop(sc);
667
668                 e1000_phy_hw_reset(&sc->hw);
669
670                 /* Give control back to firmware */
671                 igb_rel_mgmt(sc);
672                 igb_rel_hw_control(sc);
673
674                 if (sc->wol) {
675                         E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
676                         E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
677                         igb_enable_wol(dev);
678                 }
679
680                 igb_teardown_intr(sc);
681
682                 ifnet_deserialize_all(ifp);
683
684                 ether_ifdetach(ifp);
685         } else if (sc->mem_res != NULL) {
686                 igb_rel_hw_control(sc);
687         }
688         bus_generic_detach(dev);
689
690         if (sc->sysctl_tree != NULL)
691                 sysctl_ctx_free(&sc->sysctl_ctx);
692
693         igb_free_intr(sc);
694
695         if (sc->msix_mem_res != NULL) {
696                 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
697                     sc->msix_mem_res);
698         }
699         if (sc->mem_res != NULL) {
700                 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
701                     sc->mem_res);
702         }
703
704         igb_free_rings(sc);
705
706         if (sc->mta != NULL)
707                 kfree(sc->mta, M_DEVBUF);
708         if (sc->stats != NULL)
709                 kfree(sc->stats, M_DEVBUF);
710
711         return 0;
712 }
713
714 static int
715 igb_shutdown(device_t dev)
716 {
717         return igb_suspend(dev);
718 }
719
720 static int
721 igb_suspend(device_t dev)
722 {
723         struct igb_softc *sc = device_get_softc(dev);
724         struct ifnet *ifp = &sc->arpcom.ac_if;
725
726         ifnet_serialize_all(ifp);
727
728         igb_stop(sc);
729
730         igb_rel_mgmt(sc);
731         igb_rel_hw_control(sc);
732
733         if (sc->wol) {
734                 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
735                 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
736                 igb_enable_wol(dev);
737         }
738
739         ifnet_deserialize_all(ifp);
740
741         return bus_generic_suspend(dev);
742 }
743
744 static int
745 igb_resume(device_t dev)
746 {
747         struct igb_softc *sc = device_get_softc(dev);
748         struct ifnet *ifp = &sc->arpcom.ac_if;
749
750         ifnet_serialize_all(ifp);
751
752         igb_init(sc);
753         igb_get_mgmt(sc);
754
755         if_devstart(ifp);
756
757         ifnet_deserialize_all(ifp);
758
759         return bus_generic_resume(dev);
760 }
761
762 static int
763 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
764 {
765         struct igb_softc *sc = ifp->if_softc;
766         struct ifreq *ifr = (struct ifreq *)data;
767         int max_frame_size, mask, reinit;
768         int error = 0;
769
770         ASSERT_IFNET_SERIALIZED_ALL(ifp);
771
772         switch (command) {
773         case SIOCSIFMTU:
774                 max_frame_size = 9234;
775                 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
776                     ETHER_CRC_LEN) {
777                         error = EINVAL;
778                         break;
779                 }
780
781                 ifp->if_mtu = ifr->ifr_mtu;
782                 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
783                     ETHER_CRC_LEN;
784
785                 if (ifp->if_flags & IFF_RUNNING)
786                         igb_init(sc);
787                 break;
788
789         case SIOCSIFFLAGS:
790                 if (ifp->if_flags & IFF_UP) {
791                         if (ifp->if_flags & IFF_RUNNING) {
792                                 if ((ifp->if_flags ^ sc->if_flags) &
793                                     (IFF_PROMISC | IFF_ALLMULTI)) {
794                                         igb_disable_promisc(sc);
795                                         igb_set_promisc(sc);
796                                 }
797                         } else {
798                                 igb_init(sc);
799                         }
800                 } else if (ifp->if_flags & IFF_RUNNING) {
801                         igb_stop(sc);
802                 }
803                 sc->if_flags = ifp->if_flags;
804                 break;
805
806         case SIOCADDMULTI:
807         case SIOCDELMULTI:
808                 if (ifp->if_flags & IFF_RUNNING) {
809                         igb_disable_intr(sc);
810                         igb_set_multi(sc);
811 #ifdef IFPOLL_ENABLE
812                         if (!(ifp->if_flags & IFF_NPOLLING))
813 #endif
814                                 igb_enable_intr(sc);
815                 }
816                 break;
817
818         case SIOCSIFMEDIA:
819                 /*
820                  * As the speed/duplex settings are being
821                  * changed, we need toreset the PHY.
822                  */
823                 sc->hw.phy.reset_disable = FALSE;
824
825                 /* Check SOL/IDER usage */
826                 if (e1000_check_reset_block(&sc->hw)) {
827                         if_printf(ifp, "Media change is "
828                             "blocked due to SOL/IDER session.\n");
829                         break;
830                 }
831                 /* FALL THROUGH */
832
833         case SIOCGIFMEDIA:
834                 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
835                 break;
836
837         case SIOCSIFCAP:
838                 reinit = 0;
839                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
840                 if (mask & IFCAP_RXCSUM) {
841                         ifp->if_capenable ^= IFCAP_RXCSUM;
842                         reinit = 1;
843                 }
844                 if (mask & IFCAP_VLAN_HWTAGGING) {
845                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
846                         reinit = 1;
847                 }
848                 if (mask & IFCAP_TXCSUM) {
849                         ifp->if_capenable ^= IFCAP_TXCSUM;
850                         if (ifp->if_capenable & IFCAP_TXCSUM)
851                                 ifp->if_hwassist |= IGB_CSUM_FEATURES;
852                         else
853                                 ifp->if_hwassist &= ~IGB_CSUM_FEATURES;
854                 }
855                 if (mask & IFCAP_TSO) {
856                         ifp->if_capenable ^= IFCAP_TSO;
857                         if (ifp->if_capenable & IFCAP_TSO)
858                                 ifp->if_hwassist |= CSUM_TSO;
859                         else
860                                 ifp->if_hwassist &= ~CSUM_TSO;
861                 }
862                 if (mask & IFCAP_RSS)
863                         ifp->if_capenable ^= IFCAP_RSS;
864                 if (reinit && (ifp->if_flags & IFF_RUNNING))
865                         igb_init(sc);
866                 break;
867
868         default:
869                 error = ether_ioctl(ifp, command, data);
870                 break;
871         }
872         return error;
873 }
874
875 static void
876 igb_init(void *xsc)
877 {
878         struct igb_softc *sc = xsc;
879         struct ifnet *ifp = &sc->arpcom.ac_if;
880         boolean_t polling;
881         int i;
882
883         ASSERT_IFNET_SERIALIZED_ALL(ifp);
884
885         igb_stop(sc);
886
887         /* Get the latest mac address, User can use a LAA */
888         bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
889
890         /* Put the address into the Receive Address Array */
891         e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
892
893         igb_reset(sc);
894         igb_update_link_status(sc);
895
896         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
897
898         /* Configure for OS presence */
899         igb_get_mgmt(sc);
900
901         polling = FALSE;
902 #ifdef IFPOLL_ENABLE
903         if (ifp->if_flags & IFF_NPOLLING)
904                 polling = TRUE;
905 #endif
906
907         /* Configured used RX/TX rings */
908         igb_set_ring_inuse(sc, polling);
909
910         /* Initialize interrupt */
911         igb_init_intr(sc);
912
913         /* Prepare transmit descriptors and buffers */
914         for (i = 0; i < sc->tx_ring_cnt; ++i)
915                 igb_init_tx_ring(&sc->tx_rings[i]);
916         igb_init_tx_unit(sc);
917
918         /* Setup Multicast table */
919         igb_set_multi(sc);
920
921 #if 0
922         /*
923          * Figure out the desired mbuf pool
924          * for doing jumbo/packetsplit
925          */
926         if (adapter->max_frame_size <= 2048)
927                 adapter->rx_mbuf_sz = MCLBYTES;
928         else if (adapter->max_frame_size <= 4096)
929                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
930         else
931                 adapter->rx_mbuf_sz = MJUM9BYTES;
932 #endif
933
934         /* Prepare receive descriptors and buffers */
935         for (i = 0; i < sc->rx_ring_inuse; ++i) {
936                 int error;
937
938                 error = igb_init_rx_ring(&sc->rx_rings[i]);
939                 if (error) {
940                         if_printf(ifp, "Could not setup receive structures\n");
941                         igb_stop(sc);
942                         return;
943                 }
944         }
945         igb_init_rx_unit(sc);
946
947         /* Enable VLAN support */
948         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
949                 igb_set_vlan(sc);
950
951         /* Don't lose promiscuous settings */
952         igb_set_promisc(sc);
953
954         ifp->if_flags |= IFF_RUNNING;
955         ifp->if_flags &= ~IFF_OACTIVE;
956
957         callout_reset(&sc->timer, hz, igb_timer, sc);
958         e1000_clear_hw_cntrs_base_generic(&sc->hw);
959
960         /* This clears any pending interrupts */
961         E1000_READ_REG(&sc->hw, E1000_ICR);
962
963         /*
964          * Only enable interrupts if we are not polling, make sure
965          * they are off otherwise.
966          */
967         if (polling) {
968                 igb_disable_intr(sc);
969         } else {
970                 igb_enable_intr(sc);
971                 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
972         }
973
974         /* Set Energy Efficient Ethernet */
975         e1000_set_eee_i350(&sc->hw);
976
977         /* Don't reset the phy next time init gets called */
978         sc->hw.phy.reset_disable = TRUE;
979 }
980
981 static void
982 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
983 {
984         struct igb_softc *sc = ifp->if_softc;
985         u_char fiber_type = IFM_1000_SX;
986
987         ASSERT_IFNET_SERIALIZED_ALL(ifp);
988
989         igb_update_link_status(sc);
990
991         ifmr->ifm_status = IFM_AVALID;
992         ifmr->ifm_active = IFM_ETHER;
993
994         if (!sc->link_active)
995                 return;
996
997         ifmr->ifm_status |= IFM_ACTIVE;
998
999         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1000             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1001                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1002         } else {
1003                 switch (sc->link_speed) {
1004                 case 10:
1005                         ifmr->ifm_active |= IFM_10_T;
1006                         break;
1007
1008                 case 100:
1009                         ifmr->ifm_active |= IFM_100_TX;
1010                         break;
1011
1012                 case 1000:
1013                         ifmr->ifm_active |= IFM_1000_T;
1014                         break;
1015                 }
1016                 if (sc->link_duplex == FULL_DUPLEX)
1017                         ifmr->ifm_active |= IFM_FDX;
1018                 else
1019                         ifmr->ifm_active |= IFM_HDX;
1020         }
1021 }
1022
1023 static int
1024 igb_media_change(struct ifnet *ifp)
1025 {
1026         struct igb_softc *sc = ifp->if_softc;
1027         struct ifmedia *ifm = &sc->media;
1028
1029         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1030
1031         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1032                 return EINVAL;
1033
1034         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1035         case IFM_AUTO:
1036                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1037                 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1038                 break;
1039
1040         case IFM_1000_LX:
1041         case IFM_1000_SX:
1042         case IFM_1000_T:
1043                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1044                 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1045                 break;
1046
1047         case IFM_100_TX:
1048                 sc->hw.mac.autoneg = FALSE;
1049                 sc->hw.phy.autoneg_advertised = 0;
1050                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1051                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1052                 else
1053                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1054                 break;
1055
1056         case IFM_10_T:
1057                 sc->hw.mac.autoneg = FALSE;
1058                 sc->hw.phy.autoneg_advertised = 0;
1059                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1060                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1061                 else
1062                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1063                 break;
1064
1065         default:
1066                 if_printf(ifp, "Unsupported media type\n");
1067                 break;
1068         }
1069
1070         igb_init(sc);
1071
1072         return 0;
1073 }
1074
1075 static void
1076 igb_set_promisc(struct igb_softc *sc)
1077 {
1078         struct ifnet *ifp = &sc->arpcom.ac_if;
1079         struct e1000_hw *hw = &sc->hw;
1080         uint32_t reg;
1081
1082         if (sc->vf_ifp) {
1083                 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1084                 return;
1085         }
1086
1087         reg = E1000_READ_REG(hw, E1000_RCTL);
1088         if (ifp->if_flags & IFF_PROMISC) {
1089                 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1090                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1091         } else if (ifp->if_flags & IFF_ALLMULTI) {
1092                 reg |= E1000_RCTL_MPE;
1093                 reg &= ~E1000_RCTL_UPE;
1094                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1095         }
1096 }
1097
1098 static void
1099 igb_disable_promisc(struct igb_softc *sc)
1100 {
1101         struct e1000_hw *hw = &sc->hw;
1102         uint32_t reg;
1103
1104         if (sc->vf_ifp) {
1105                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1106                 return;
1107         }
1108         reg = E1000_READ_REG(hw, E1000_RCTL);
1109         reg &= ~E1000_RCTL_UPE;
1110         reg &= ~E1000_RCTL_MPE;
1111         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1112 }
1113
1114 static void
1115 igb_set_multi(struct igb_softc *sc)
1116 {
1117         struct ifnet *ifp = &sc->arpcom.ac_if;
1118         struct ifmultiaddr *ifma;
1119         uint32_t reg_rctl = 0;
1120         uint8_t *mta;
1121         int mcnt = 0;
1122
1123         mta = sc->mta;
1124         bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1125
1126         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1127                 if (ifma->ifma_addr->sa_family != AF_LINK)
1128                         continue;
1129
1130                 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1131                         break;
1132
1133                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1134                     &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1135                 mcnt++;
1136         }
1137
1138         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1139                 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1140                 reg_rctl |= E1000_RCTL_MPE;
1141                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1142         } else {
1143                 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1144         }
1145 }
1146
1147 static void
1148 igb_timer(void *xsc)
1149 {
1150         struct igb_softc *sc = xsc;
1151
1152         lwkt_serialize_enter(&sc->main_serialize);
1153
1154         igb_update_link_status(sc);
1155         igb_update_stats_counters(sc);
1156
1157         callout_reset(&sc->timer, hz, igb_timer, sc);
1158
1159         lwkt_serialize_exit(&sc->main_serialize);
1160 }
1161
1162 static void
1163 igb_update_link_status(struct igb_softc *sc)
1164 {
1165         struct ifnet *ifp = &sc->arpcom.ac_if;
1166         struct e1000_hw *hw = &sc->hw;
1167         uint32_t link_check, thstat, ctrl;
1168
1169         link_check = thstat = ctrl = 0;
1170
1171         /* Get the cached link value or read for real */
1172         switch (hw->phy.media_type) {
1173         case e1000_media_type_copper:
1174                 if (hw->mac.get_link_status) {
1175                         /* Do the work to read phy */
1176                         e1000_check_for_link(hw);
1177                         link_check = !hw->mac.get_link_status;
1178                 } else {
1179                         link_check = TRUE;
1180                 }
1181                 break;
1182
1183         case e1000_media_type_fiber:
1184                 e1000_check_for_link(hw);
1185                 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1186                 break;
1187
1188         case e1000_media_type_internal_serdes:
1189                 e1000_check_for_link(hw);
1190                 link_check = hw->mac.serdes_has_link;
1191                 break;
1192
1193         /* VF device is type_unknown */
1194         case e1000_media_type_unknown:
1195                 e1000_check_for_link(hw);
1196                 link_check = !hw->mac.get_link_status;
1197                 /* Fall thru */
1198         default:
1199                 break;
1200         }
1201
1202         /* Check for thermal downshift or shutdown */
1203         if (hw->mac.type == e1000_i350) {
1204                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1205                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1206         }
1207
1208         /* Now we check if a transition has happened */
1209         if (link_check && sc->link_active == 0) {
1210                 e1000_get_speed_and_duplex(hw, 
1211                     &sc->link_speed, &sc->link_duplex);
1212                 if (bootverbose) {
1213                         if_printf(ifp, "Link is up %d Mbps %s\n",
1214                             sc->link_speed,
1215                             sc->link_duplex == FULL_DUPLEX ?
1216                             "Full Duplex" : "Half Duplex");
1217                 }
1218                 sc->link_active = 1;
1219
1220                 ifp->if_baudrate = sc->link_speed * 1000000;
1221                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1222                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1223                         if_printf(ifp, "Link: thermal downshift\n");
1224                 /* This can sleep */
1225                 ifp->if_link_state = LINK_STATE_UP;
1226                 if_link_state_change(ifp);
1227         } else if (!link_check && sc->link_active == 1) {
1228                 ifp->if_baudrate = sc->link_speed = 0;
1229                 sc->link_duplex = 0;
1230                 if (bootverbose)
1231                         if_printf(ifp, "Link is Down\n");
1232                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1233                     (thstat & E1000_THSTAT_PWR_DOWN))
1234                         if_printf(ifp, "Link: thermal shutdown\n");
1235                 sc->link_active = 0;
1236                 /* This can sleep */
1237                 ifp->if_link_state = LINK_STATE_DOWN;
1238                 if_link_state_change(ifp);
1239         }
1240 }
1241
1242 static void
1243 igb_stop(struct igb_softc *sc)
1244 {
1245         struct ifnet *ifp = &sc->arpcom.ac_if;
1246         int i;
1247
1248         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1249
1250         igb_disable_intr(sc);
1251
1252         callout_stop(&sc->timer);
1253
1254         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1255         ifp->if_timer = 0;
1256
1257         e1000_reset_hw(&sc->hw);
1258         E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1259
1260         e1000_led_off(&sc->hw);
1261         e1000_cleanup_led(&sc->hw);
1262
1263         for (i = 0; i < sc->tx_ring_cnt; ++i)
1264                 igb_free_tx_ring(&sc->tx_rings[i]);
1265         for (i = 0; i < sc->rx_ring_cnt; ++i)
1266                 igb_free_rx_ring(&sc->rx_rings[i]);
1267 }
1268
1269 static void
1270 igb_reset(struct igb_softc *sc)
1271 {
1272         struct ifnet *ifp = &sc->arpcom.ac_if;
1273         struct e1000_hw *hw = &sc->hw;
1274         struct e1000_fc_info *fc = &hw->fc;
1275         uint32_t pba = 0;
1276         uint16_t hwm;
1277
1278         /* Let the firmware know the OS is in control */
1279         igb_get_hw_control(sc);
1280
1281         /*
1282          * Packet Buffer Allocation (PBA)
1283          * Writing PBA sets the receive portion of the buffer
1284          * the remainder is used for the transmit buffer.
1285          */
1286         switch (hw->mac.type) {
1287         case e1000_82575:
1288                 pba = E1000_PBA_32K;
1289                 break;
1290
1291         case e1000_82576:
1292         case e1000_vfadapt:
1293                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1294                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1295                 break;
1296
1297         case e1000_82580:
1298         case e1000_i350:
1299         case e1000_vfadapt_i350:
1300                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1301                 pba = e1000_rxpbs_adjust_82580(pba);
1302                 break;
1303                 /* XXX pba = E1000_PBA_35K; */
1304
1305         default:
1306                 break;
1307         }
1308
1309         /* Special needs in case of Jumbo frames */
1310         if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1311                 uint32_t tx_space, min_tx, min_rx;
1312
1313                 pba = E1000_READ_REG(hw, E1000_PBA);
1314                 tx_space = pba >> 16;
1315                 pba &= 0xffff;
1316
1317                 min_tx = (sc->max_frame_size +
1318                     sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1319                 min_tx = roundup2(min_tx, 1024);
1320                 min_tx >>= 10;
1321                 min_rx = sc->max_frame_size;
1322                 min_rx = roundup2(min_rx, 1024);
1323                 min_rx >>= 10;
1324                 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1325                         pba = pba - (min_tx - tx_space);
1326                         /*
1327                          * if short on rx space, rx wins
1328                          * and must trump tx adjustment
1329                          */
1330                         if (pba < min_rx)
1331                                 pba = min_rx;
1332                 }
1333                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1334         }
1335
1336         /*
1337          * These parameters control the automatic generation (Tx) and
1338          * response (Rx) to Ethernet PAUSE frames.
1339          * - High water mark should allow for at least two frames to be
1340          *   received after sending an XOFF.
1341          * - Low water mark works best when it is very near the high water mark.
1342          *   This allows the receiver to restart by sending XON when it has
1343          *   drained a bit.
1344          */
1345         hwm = min(((pba << 10) * 9 / 10),
1346             ((pba << 10) - 2 * sc->max_frame_size));
1347
1348         if (hw->mac.type < e1000_82576) {
1349                 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1350                 fc->low_water = fc->high_water - 8;
1351         } else {
1352                 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1353                 fc->low_water = fc->high_water - 16;
1354         }
1355         fc->pause_time = IGB_FC_PAUSE_TIME;
1356         fc->send_xon = TRUE;
1357
1358         /* Issue a global reset */
1359         e1000_reset_hw(hw);
1360         E1000_WRITE_REG(hw, E1000_WUC, 0);
1361
1362         if (e1000_init_hw(hw) < 0)
1363                 if_printf(ifp, "Hardware Initialization Failed\n");
1364
1365         /* Setup DMA Coalescing */
1366         if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1367                 uint32_t reg;
1368
1369                 hwm = (pba - 4) << 10;
1370                 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1371                     & E1000_DMACR_DMACTHR_MASK;
1372
1373                 /* transition to L0x or L1 if available..*/
1374                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1375
1376                 /* timer = +-1000 usec in 32usec intervals */
1377                 reg |= (1000 >> 5);
1378                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1379
1380                 /* No lower threshold */
1381                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1382
1383                 /* set hwm to PBA -  2 * max frame size */
1384                 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1385
1386                 /* Set the interval before transition */
1387                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1388                 reg |= 0x800000FF; /* 255 usec */
1389                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1390
1391                 /* free space in tx packet buffer to wake from DMA coal */
1392                 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1393                     (20480 - (2 * sc->max_frame_size)) >> 6);
1394
1395                 /* make low power state decision controlled by DMA coal */
1396                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1397                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1398                     reg | E1000_PCIEMISC_LX_DECISION);
1399                 if_printf(ifp, "DMA Coalescing enabled\n");
1400         }
1401
1402         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1403         e1000_get_phy_info(hw);
1404         e1000_check_for_link(hw);
1405 }
1406
1407 static void
1408 igb_setup_ifp(struct igb_softc *sc)
1409 {
1410         struct ifnet *ifp = &sc->arpcom.ac_if;
1411
1412         ifp->if_softc = sc;
1413         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1414         ifp->if_init = igb_init;
1415         ifp->if_ioctl = igb_ioctl;
1416         ifp->if_start = igb_start;
1417         ifp->if_serialize = igb_serialize;
1418         ifp->if_deserialize = igb_deserialize;
1419         ifp->if_tryserialize = igb_tryserialize;
1420 #ifdef INVARIANTS
1421         ifp->if_serialize_assert = igb_serialize_assert;
1422 #endif
1423 #ifdef IFPOLL_ENABLE
1424         ifp->if_npoll = igb_npoll;
1425 #endif
1426         ifp->if_watchdog = igb_watchdog;
1427
1428         ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1429         ifq_set_ready(&ifp->if_snd);
1430
1431         ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1432
1433         ifp->if_capabilities =
1434             IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_TSO;
1435         if (IGB_ENABLE_HWRSS(sc))
1436                 ifp->if_capabilities |= IFCAP_RSS;
1437         ifp->if_capenable = ifp->if_capabilities;
1438         ifp->if_hwassist = IGB_CSUM_FEATURES | CSUM_TSO;
1439
1440         /*
1441          * Tell the upper layer(s) we support long frames
1442          */
1443         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1444
1445         /*
1446          * Specify the media types supported by this adapter and register
1447          * callbacks to update media and link information
1448          */
1449         ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1450         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1451             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1452                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1453                     0, NULL);
1454                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1455         } else {
1456                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1457                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1458                     0, NULL);
1459                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1460                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1461                     0, NULL);
1462                 if (sc->hw.phy.type != e1000_phy_ife) {
1463                         ifmedia_add(&sc->media,
1464                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1465                         ifmedia_add(&sc->media,
1466                             IFM_ETHER | IFM_1000_T, 0, NULL);
1467                 }
1468         }
1469         ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1470         ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1471 }
1472
1473 static void
1474 igb_add_sysctl(struct igb_softc *sc)
1475 {
1476         char node[32];
1477         int i;
1478
1479         sysctl_ctx_init(&sc->sysctl_ctx);
1480         sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1481             SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1482             device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1483         if (sc->sysctl_tree == NULL) {
1484                 device_printf(sc->dev, "can't add sysctl node\n");
1485                 return;
1486         }
1487
1488         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1489             OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1490         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1491             OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1492             "# of RX rings used");
1493         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1494             OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1495             "# of RX descs");
1496         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1497             OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1498             "# of TX descs");
1499
1500         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1501                 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1502                     SYSCTL_CHILDREN(sc->sysctl_tree),
1503                     OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1504                     sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1505         } else {
1506                 for (i = 0; i < sc->msix_cnt; ++i) {
1507                         struct igb_msix_data *msix = &sc->msix_data[i];
1508
1509                         ksnprintf(node, sizeof(node), "msix%d_rate", i);
1510                         SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1511                             SYSCTL_CHILDREN(sc->sysctl_tree),
1512                             OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1513                             msix, 0, igb_sysctl_msix_rate, "I",
1514                             msix->msix_rate_desc);
1515                 }
1516         }
1517
1518         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1519             OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1520             sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1521             "# of segments per TX interrupt");
1522
1523 #ifdef IFPOLL_ENABLE
1524         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1525             OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
1526             sc, 0, igb_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset");
1527         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1528             OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
1529             sc, 0, igb_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset");
1530 #endif
1531
1532 #ifdef IGB_RSS_DEBUG
1533         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1534             OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1535             "RSS debug level");
1536         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1537                 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
1538                 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1539                     SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1540                     CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1541         }
1542 #endif
1543 }
1544
1545 static int
1546 igb_alloc_rings(struct igb_softc *sc)
1547 {
1548         int error, i;
1549
1550         /*
1551          * Create top level busdma tag
1552          */
1553         error = bus_dma_tag_create(NULL, 1, 0,
1554             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1555             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1556             &sc->parent_tag);
1557         if (error) {
1558                 device_printf(sc->dev, "could not create top level DMA tag\n");
1559                 return error;
1560         }
1561
1562         /*
1563          * Allocate TX descriptor rings and buffers
1564          */
1565         sc->tx_rings = kmalloc_cachealign(
1566             sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1567             M_DEVBUF, M_WAITOK | M_ZERO);
1568         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1569                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1570
1571                 /* Set up some basics */
1572                 txr->sc = sc;
1573                 txr->me = i;
1574                 lwkt_serialize_init(&txr->tx_serialize);
1575
1576                 error = igb_create_tx_ring(txr);
1577                 if (error)
1578                         return error;
1579         }
1580
1581         /*
1582          * Allocate RX descriptor rings and buffers
1583          */ 
1584         sc->rx_rings = kmalloc_cachealign(
1585             sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1586             M_DEVBUF, M_WAITOK | M_ZERO);
1587         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1588                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1589
1590                 /* Set up some basics */
1591                 rxr->sc = sc;
1592                 rxr->me = i;
1593                 lwkt_serialize_init(&rxr->rx_serialize);
1594
1595                 error = igb_create_rx_ring(rxr);
1596                 if (error)
1597                         return error;
1598         }
1599
1600         return 0;
1601 }
1602
1603 static void
1604 igb_free_rings(struct igb_softc *sc)
1605 {
1606         int i;
1607
1608         if (sc->tx_rings != NULL) {
1609                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1610                         struct igb_tx_ring *txr = &sc->tx_rings[i];
1611
1612                         igb_destroy_tx_ring(txr, txr->num_tx_desc);
1613                 }
1614                 kfree(sc->tx_rings, M_DEVBUF);
1615         }
1616
1617         if (sc->rx_rings != NULL) {
1618                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1619                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
1620
1621                         igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1622                 }
1623                 kfree(sc->rx_rings, M_DEVBUF);
1624         }
1625 }
1626
1627 static int
1628 igb_create_tx_ring(struct igb_tx_ring *txr)
1629 {
1630         int tsize, error, i;
1631
1632         /*
1633          * Validate number of transmit descriptors. It must not exceed
1634          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1635          */
1636         if (((igb_txd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN) != 0 ||
1637             (igb_txd > IGB_MAX_TXD) || (igb_txd < IGB_MIN_TXD)) {
1638                 device_printf(txr->sc->dev,
1639                     "Using %d TX descriptors instead of %d!\n",
1640                     IGB_DEFAULT_TXD, igb_txd);
1641                 txr->num_tx_desc = IGB_DEFAULT_TXD;
1642         } else {
1643                 txr->num_tx_desc = igb_txd;
1644         }
1645
1646         /*
1647          * Allocate TX descriptor ring
1648          */
1649         tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1650             IGB_DBA_ALIGN);
1651         txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1652             IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1653             &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1654         if (txr->txdma.dma_vaddr == NULL) {
1655                 device_printf(txr->sc->dev,
1656                     "Unable to allocate TX Descriptor memory\n");
1657                 return ENOMEM;
1658         }
1659         txr->tx_base = txr->txdma.dma_vaddr;
1660         bzero(txr->tx_base, tsize);
1661
1662         txr->tx_buf = kmalloc(sizeof(struct igb_tx_buf) * txr->num_tx_desc,
1663             M_DEVBUF, M_WAITOK | M_ZERO);
1664
1665         /*
1666          * Allocate TX head write-back buffer
1667          */
1668         txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1669             __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1670             &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1671         if (txr->tx_hdr == NULL) {
1672                 device_printf(txr->sc->dev,
1673                     "Unable to allocate TX head write-back buffer\n");
1674                 return ENOMEM;
1675         }
1676
1677         /*
1678          * Create DMA tag for TX buffers
1679          */
1680         error = bus_dma_tag_create(txr->sc->parent_tag,
1681             1, 0,               /* alignment, bounds */
1682             BUS_SPACE_MAXADDR,  /* lowaddr */
1683             BUS_SPACE_MAXADDR,  /* highaddr */
1684             NULL, NULL,         /* filter, filterarg */
1685             IGB_TSO_SIZE,       /* maxsize */
1686             IGB_MAX_SCATTER,    /* nsegments */
1687             PAGE_SIZE,          /* maxsegsize */
1688             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1689             BUS_DMA_ONEBPAGE,   /* flags */
1690             &txr->tx_tag);
1691         if (error) {
1692                 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1693                 kfree(txr->tx_buf, M_DEVBUF);
1694                 txr->tx_buf = NULL;
1695                 return error;
1696         }
1697
1698         /*
1699          * Create DMA maps for TX buffers
1700          */
1701         for (i = 0; i < txr->num_tx_desc; ++i) {
1702                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1703
1704                 error = bus_dmamap_create(txr->tx_tag,
1705                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1706                 if (error) {
1707                         device_printf(txr->sc->dev,
1708                             "Unable to create TX DMA map\n");
1709                         igb_destroy_tx_ring(txr, i);
1710                         return error;
1711                 }
1712         }
1713
1714         /*
1715          * Initialize various watermark
1716          */
1717         txr->spare_desc = IGB_TX_SPARE;
1718         txr->intr_nsegs = txr->num_tx_desc / 16;
1719         txr->oact_hi_desc = txr->num_tx_desc / 2;
1720         txr->oact_lo_desc = txr->num_tx_desc / 8;
1721         if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1722                 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1723         if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1724                 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1725
1726         return 0;
1727 }
1728
1729 static void
1730 igb_free_tx_ring(struct igb_tx_ring *txr)
1731 {
1732         int i;
1733
1734         for (i = 0; i < txr->num_tx_desc; ++i) {
1735                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1736
1737                 if (txbuf->m_head != NULL) {
1738                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1739                         m_freem(txbuf->m_head);
1740                         txbuf->m_head = NULL;
1741                 }
1742         }
1743 }
1744
1745 static void
1746 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1747 {
1748         int i;
1749
1750         if (txr->txdma.dma_vaddr != NULL) {
1751                 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1752                 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1753                     txr->txdma.dma_map);
1754                 bus_dma_tag_destroy(txr->txdma.dma_tag);
1755                 txr->txdma.dma_vaddr = NULL;
1756         }
1757
1758         if (txr->tx_hdr != NULL) {
1759                 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1760                 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1761                     txr->tx_hdr_dmap);
1762                 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1763                 txr->tx_hdr = NULL;
1764         }
1765
1766         if (txr->tx_buf == NULL)
1767                 return;
1768
1769         for (i = 0; i < ndesc; ++i) {
1770                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1771
1772                 KKASSERT(txbuf->m_head == NULL);
1773                 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1774         }
1775         bus_dma_tag_destroy(txr->tx_tag);
1776
1777         kfree(txr->tx_buf, M_DEVBUF);
1778         txr->tx_buf = NULL;
1779 }
1780
1781 static void
1782 igb_init_tx_ring(struct igb_tx_ring *txr)
1783 {
1784         /* Clear the old descriptor contents */
1785         bzero(txr->tx_base,
1786             sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1787
1788         /* Clear TX head write-back buffer */
1789         *(txr->tx_hdr) = 0;
1790
1791         /* Reset indices */
1792         txr->next_avail_desc = 0;
1793         txr->next_to_clean = 0;
1794         txr->tx_nsegs = 0;
1795
1796         /* Set number of descriptors available */
1797         txr->tx_avail = txr->num_tx_desc;
1798 }
1799
1800 static void
1801 igb_init_tx_unit(struct igb_softc *sc)
1802 {
1803         struct e1000_hw *hw = &sc->hw;
1804         uint32_t tctl;
1805         int i;
1806
1807         /* Setup the Tx Descriptor Rings */
1808         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1809                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1810                 uint64_t bus_addr = txr->txdma.dma_paddr;
1811                 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1812                 uint32_t txdctl = 0;
1813                 uint32_t dca_txctrl;
1814
1815                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1816                     txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1817                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1818                     (uint32_t)(bus_addr >> 32));
1819                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1820                     (uint32_t)bus_addr);
1821
1822                 /* Setup the HW Tx Head and Tail descriptor pointers */
1823                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1824                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1825
1826                 /*
1827                  * WTHRESH is ignored by the hardware, since header
1828                  * write back mode is used.
1829                  */
1830                 txdctl |= IGB_TX_PTHRESH;
1831                 txdctl |= IGB_TX_HTHRESH << 8;
1832                 txdctl |= IGB_TX_WTHRESH << 16;
1833                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1834                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1835
1836                 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1837                 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1838                 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1839
1840                 /*
1841                  * Don't set WB_on_EITR:
1842                  * - 82575 does not have it
1843                  * - It almost has no effect on 82576, see:
1844                  *   82576 specification update errata #26
1845                  * - It causes unnecessary bus traffic
1846                  */
1847                 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1848                     (uint32_t)(hdr_paddr >> 32));
1849                 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1850                     ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1851         }
1852
1853         if (sc->vf_ifp)
1854                 return;
1855
1856         e1000_config_collision_dist(hw);
1857
1858         /* Program the Transmit Control Register */
1859         tctl = E1000_READ_REG(hw, E1000_TCTL);
1860         tctl &= ~E1000_TCTL_CT;
1861         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1862             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1863
1864         /* This write will effectively turn on the transmit unit. */
1865         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1866 }
1867
1868 static boolean_t
1869 igb_txcsum_ctx(struct igb_tx_ring *txr, struct mbuf *mp)
1870 {
1871         struct e1000_adv_tx_context_desc *TXD;
1872         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1873         int ehdrlen, ctxd, ip_hlen = 0;
1874         boolean_t offload = TRUE;
1875
1876         if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1877                 offload = FALSE;
1878
1879         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1880
1881         ctxd = txr->next_avail_desc;
1882         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1883
1884         /*
1885          * In advanced descriptors the vlan tag must 
1886          * be placed into the context descriptor, thus
1887          * we need to be here just for that setup.
1888          */
1889         if (mp->m_flags & M_VLANTAG) {
1890                 uint16_t vlantag;
1891
1892                 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1893                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1894         } else if (!offload) {
1895                 return FALSE;
1896         }
1897
1898         ehdrlen = mp->m_pkthdr.csum_lhlen;
1899         KASSERT(ehdrlen > 0, ("invalid ether hlen"));
1900
1901         /* Set the ether header length */
1902         vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1903         if (mp->m_pkthdr.csum_flags & CSUM_IP) {
1904                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1905                 ip_hlen = mp->m_pkthdr.csum_iphlen;
1906                 KASSERT(ip_hlen > 0, ("invalid ip hlen"));
1907         }
1908         vlan_macip_lens |= ip_hlen;
1909
1910         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1911         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1912                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1913         else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1914                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1915
1916         /* 82575 needs the queue index added */
1917         if (txr->sc->hw.mac.type == e1000_82575)
1918                 mss_l4len_idx = txr->me << 4;
1919
1920         /* Now copy bits into descriptor */
1921         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1922         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1923         TXD->seqnum_seed = htole32(0);
1924         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1925
1926         /* We've consumed the first desc, adjust counters */
1927         if (++ctxd == txr->num_tx_desc)
1928                 ctxd = 0;
1929         txr->next_avail_desc = ctxd;
1930         --txr->tx_avail;
1931
1932         return offload;
1933 }
1934
1935 static void
1936 igb_txeof(struct igb_tx_ring *txr)
1937 {
1938         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
1939         int first, hdr, avail;
1940
1941         if (txr->tx_avail == txr->num_tx_desc)
1942                 return;
1943
1944         first = txr->next_to_clean;
1945         hdr = *(txr->tx_hdr);
1946
1947         if (first == hdr)
1948                 return;
1949
1950         avail = txr->tx_avail;
1951         while (first != hdr) {
1952                 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1953
1954                 ++avail;
1955                 if (txbuf->m_head) {
1956                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1957                         m_freem(txbuf->m_head);
1958                         txbuf->m_head = NULL;
1959                         ++ifp->if_opackets;
1960                 }
1961                 if (++first == txr->num_tx_desc)
1962                         first = 0;
1963         }
1964         txr->next_to_clean = first;
1965         txr->tx_avail = avail;
1966
1967         /*
1968          * If we have a minimum free, clear IFF_OACTIVE
1969          * to tell the stack that it is OK to send packets.
1970          */
1971         if (IGB_IS_NOT_OACTIVE(txr)) {
1972                 ifp->if_flags &= ~IFF_OACTIVE;
1973
1974                 /*
1975                  * We have enough TX descriptors, turn off
1976                  * the watchdog.  We allow small amount of
1977                  * packets (roughly intr_nsegs) pending on
1978                  * the transmit ring.
1979                  */
1980                 ifp->if_timer = 0;
1981         }
1982 }
1983
1984 static int
1985 igb_create_rx_ring(struct igb_rx_ring *rxr)
1986 {
1987         int rsize, i, error;
1988
1989         /*
1990          * Validate number of receive descriptors. It must not exceed
1991          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1992          */
1993         if (((igb_rxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN) != 0 ||
1994             (igb_rxd > IGB_MAX_RXD) || (igb_rxd < IGB_MIN_RXD)) {
1995                 device_printf(rxr->sc->dev,
1996                     "Using %d RX descriptors instead of %d!\n",
1997                     IGB_DEFAULT_RXD, igb_rxd);
1998                 rxr->num_rx_desc = IGB_DEFAULT_RXD;
1999         } else {
2000                 rxr->num_rx_desc = igb_rxd;
2001         }
2002
2003         /*
2004          * Allocate RX descriptor ring
2005          */
2006         rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
2007             IGB_DBA_ALIGN);
2008         rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
2009             IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2010             &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
2011             &rxr->rxdma.dma_paddr);
2012         if (rxr->rxdma.dma_vaddr == NULL) {
2013                 device_printf(rxr->sc->dev,
2014                     "Unable to allocate RxDescriptor memory\n");
2015                 return ENOMEM;
2016         }
2017         rxr->rx_base = rxr->rxdma.dma_vaddr;
2018         bzero(rxr->rx_base, rsize);
2019
2020         rxr->rx_buf = kmalloc(sizeof(struct igb_rx_buf) * rxr->num_rx_desc,
2021             M_DEVBUF, M_WAITOK | M_ZERO);
2022
2023         /*
2024          * Create DMA tag for RX buffers
2025          */
2026         error = bus_dma_tag_create(rxr->sc->parent_tag,
2027             1, 0,               /* alignment, bounds */
2028             BUS_SPACE_MAXADDR,  /* lowaddr */
2029             BUS_SPACE_MAXADDR,  /* highaddr */
2030             NULL, NULL,         /* filter, filterarg */
2031             MCLBYTES,           /* maxsize */
2032             1,                  /* nsegments */
2033             MCLBYTES,           /* maxsegsize */
2034             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2035             &rxr->rx_tag);
2036         if (error) {
2037                 device_printf(rxr->sc->dev,
2038                     "Unable to create RX payload DMA tag\n");
2039                 kfree(rxr->rx_buf, M_DEVBUF);
2040                 rxr->rx_buf = NULL;
2041                 return error;
2042         }
2043
2044         /*
2045          * Create spare DMA map for RX buffers
2046          */
2047         error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2048             &rxr->rx_sparemap);
2049         if (error) {
2050                 device_printf(rxr->sc->dev,
2051                     "Unable to create spare RX DMA maps\n");
2052                 bus_dma_tag_destroy(rxr->rx_tag);
2053                 kfree(rxr->rx_buf, M_DEVBUF);
2054                 rxr->rx_buf = NULL;
2055                 return error;
2056         }
2057
2058         /*
2059          * Create DMA maps for RX buffers
2060          */
2061         for (i = 0; i < rxr->num_rx_desc; i++) {
2062                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2063
2064                 error = bus_dmamap_create(rxr->rx_tag,
2065                     BUS_DMA_WAITOK, &rxbuf->map);
2066                 if (error) {
2067                         device_printf(rxr->sc->dev,
2068                             "Unable to create RX DMA maps\n");
2069                         igb_destroy_rx_ring(rxr, i);
2070                         return error;
2071                 }
2072         }
2073         return 0;
2074 }
2075
2076 static void
2077 igb_free_rx_ring(struct igb_rx_ring *rxr)
2078 {
2079         int i;
2080
2081         for (i = 0; i < rxr->num_rx_desc; ++i) {
2082                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2083
2084                 if (rxbuf->m_head != NULL) {
2085                         bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2086                         m_freem(rxbuf->m_head);
2087                         rxbuf->m_head = NULL;
2088                 }
2089         }
2090
2091         if (rxr->fmp != NULL)
2092                 m_freem(rxr->fmp);
2093         rxr->fmp = NULL;
2094         rxr->lmp = NULL;
2095 }
2096
2097 static void
2098 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2099 {
2100         int i;
2101
2102         if (rxr->rxdma.dma_vaddr != NULL) {
2103                 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2104                 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2105                     rxr->rxdma.dma_map);
2106                 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2107                 rxr->rxdma.dma_vaddr = NULL;
2108         }
2109
2110         if (rxr->rx_buf == NULL)
2111                 return;
2112
2113         for (i = 0; i < ndesc; ++i) {
2114                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2115
2116                 KKASSERT(rxbuf->m_head == NULL);
2117                 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2118         }
2119         bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2120         bus_dma_tag_destroy(rxr->rx_tag);
2121
2122         kfree(rxr->rx_buf, M_DEVBUF);
2123         rxr->rx_buf = NULL;
2124 }
2125
2126 static void
2127 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2128 {
2129         rxd->read.pkt_addr = htole64(rxbuf->paddr);
2130         rxd->wb.upper.status_error = 0;
2131 }
2132
2133 static int
2134 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2135 {
2136         struct mbuf *m;
2137         bus_dma_segment_t seg;
2138         bus_dmamap_t map;
2139         struct igb_rx_buf *rxbuf;
2140         int error, nseg;
2141
2142         m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2143         if (m == NULL) {
2144                 if (wait) {
2145                         if_printf(&rxr->sc->arpcom.ac_if,
2146                             "Unable to allocate RX mbuf\n");
2147                 }
2148                 return ENOBUFS;
2149         }
2150         m->m_len = m->m_pkthdr.len = MCLBYTES;
2151
2152         if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2153                 m_adj(m, ETHER_ALIGN);
2154
2155         error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2156             rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2157         if (error) {
2158                 m_freem(m);
2159                 if (wait) {
2160                         if_printf(&rxr->sc->arpcom.ac_if,
2161                             "Unable to load RX mbuf\n");
2162                 }
2163                 return error;
2164         }
2165
2166         rxbuf = &rxr->rx_buf[i];
2167         if (rxbuf->m_head != NULL)
2168                 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2169
2170         map = rxbuf->map;
2171         rxbuf->map = rxr->rx_sparemap;
2172         rxr->rx_sparemap = map;
2173
2174         rxbuf->m_head = m;
2175         rxbuf->paddr = seg.ds_addr;
2176
2177         igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2178         return 0;
2179 }
2180
2181 static int
2182 igb_init_rx_ring(struct igb_rx_ring *rxr)
2183 {
2184         int i;
2185
2186         /* Clear the ring contents */
2187         bzero(rxr->rx_base,
2188             rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2189
2190         /* Now replenish the ring mbufs */
2191         for (i = 0; i < rxr->num_rx_desc; ++i) {
2192                 int error;
2193
2194                 error = igb_newbuf(rxr, i, TRUE);
2195                 if (error)
2196                         return error;
2197         }
2198
2199         /* Setup our descriptor indices */
2200         rxr->next_to_check = 0;
2201
2202         rxr->fmp = NULL;
2203         rxr->lmp = NULL;
2204         rxr->discard = FALSE;
2205
2206         return 0;
2207 }
2208
2209 static void
2210 igb_init_rx_unit(struct igb_softc *sc)
2211 {
2212         struct ifnet *ifp = &sc->arpcom.ac_if;
2213         struct e1000_hw *hw = &sc->hw;
2214         uint32_t rctl, rxcsum, srrctl = 0;
2215         int i;
2216
2217         /*
2218          * Make sure receives are disabled while setting
2219          * up the descriptor ring
2220          */
2221         rctl = E1000_READ_REG(hw, E1000_RCTL);
2222         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2223
2224 #if 0
2225         /*
2226         ** Set up for header split
2227         */
2228         if (igb_header_split) {
2229                 /* Use a standard mbuf for the header */
2230                 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2231                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2232         } else
2233 #endif
2234                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2235
2236         /*
2237         ** Set up for jumbo frames
2238         */
2239         if (ifp->if_mtu > ETHERMTU) {
2240                 rctl |= E1000_RCTL_LPE;
2241 #if 0
2242                 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2243                         srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2244                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2245                 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2246                         srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2247                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2248                 }
2249                 /* Set maximum packet len */
2250                 psize = adapter->max_frame_size;
2251                 /* are we on a vlan? */
2252                 if (adapter->ifp->if_vlantrunk != NULL)
2253                         psize += VLAN_TAG_SIZE;
2254                 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2255 #else
2256                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2257                 rctl |= E1000_RCTL_SZ_2048;
2258 #endif
2259         } else {
2260                 rctl &= ~E1000_RCTL_LPE;
2261                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2262                 rctl |= E1000_RCTL_SZ_2048;
2263         }
2264
2265         /* Setup the Base and Length of the Rx Descriptor Rings */
2266         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2267                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2268                 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2269                 uint32_t rxdctl;
2270
2271                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2272                     rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2273                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2274                     (uint32_t)(bus_addr >> 32));
2275                 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2276                     (uint32_t)bus_addr);
2277                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2278                 /* Enable this Queue */
2279                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2280                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2281                 rxdctl &= 0xFFF00000;
2282                 rxdctl |= IGB_RX_PTHRESH;
2283                 rxdctl |= IGB_RX_HTHRESH << 8;
2284                 /*
2285                  * Don't set WTHRESH to a value above 1 on 82576, see:
2286                  * 82576 specification update errata #26
2287                  */
2288                 rxdctl |= IGB_RX_WTHRESH << 16;
2289                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2290         }
2291
2292         rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2293         rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2294
2295         /*
2296          * Receive Checksum Offload for TCP and UDP
2297          *
2298          * Checksum offloading is also enabled if multiple receive
2299          * queue is to be supported, since we need it to figure out
2300          * fragments.
2301          */
2302         if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2303                 /*
2304                  * NOTE:
2305                  * PCSD must be enabled to enable multiple
2306                  * receive queues.
2307                  */
2308                 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2309                     E1000_RXCSUM_PCSD;
2310         } else {
2311                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2312                     E1000_RXCSUM_PCSD);
2313         }
2314         E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2315
2316         if (IGB_ENABLE_HWRSS(sc)) {
2317                 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2318                 uint32_t reta_shift;
2319                 int j, r;
2320
2321                 /*
2322                  * NOTE:
2323                  * When we reach here, RSS has already been disabled
2324                  * in igb_stop(), so we could safely configure RSS key
2325                  * and redirect table.
2326                  */
2327
2328                 /*
2329                  * Configure RSS key
2330                  */
2331                 toeplitz_get_key(key, sizeof(key));
2332                 for (i = 0; i < IGB_NRSSRK; ++i) {
2333                         uint32_t rssrk;
2334
2335                         rssrk = IGB_RSSRK_VAL(key, i);
2336                         IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2337
2338                         E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2339                 }
2340
2341                 /*
2342                  * Configure RSS redirect table in following fashion:
2343                  * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2344                  */
2345                 reta_shift = IGB_RETA_SHIFT;
2346                 if (hw->mac.type == e1000_82575)
2347                         reta_shift = IGB_RETA_SHIFT_82575;
2348
2349                 r = 0;
2350                 for (j = 0; j < IGB_NRETA; ++j) {
2351                         uint32_t reta = 0;
2352
2353                         for (i = 0; i < IGB_RETA_SIZE; ++i) {
2354                                 uint32_t q;
2355
2356                                 q = (r % sc->rx_ring_inuse) << reta_shift;
2357                                 reta |= q << (8 * i);
2358                                 ++r;
2359                         }
2360                         IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2361                         E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2362                 }
2363
2364                 /*
2365                  * Enable multiple receive queues.
2366                  * Enable IPv4 RSS standard hash functions.
2367                  * Disable RSS interrupt on 82575
2368                  */
2369                 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2370                                 E1000_MRQC_ENABLE_RSS_4Q |
2371                                 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2372                                 E1000_MRQC_RSS_FIELD_IPV4);
2373         }
2374
2375         /* Setup the Receive Control Register */
2376         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2377         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2378             E1000_RCTL_RDMTS_HALF |
2379             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2380         /* Strip CRC bytes. */
2381         rctl |= E1000_RCTL_SECRC;
2382         /* Make sure VLAN Filters are off */
2383         rctl &= ~E1000_RCTL_VFE;
2384         /* Don't store bad packets */
2385         rctl &= ~E1000_RCTL_SBP;
2386
2387         /* Enable Receives */
2388         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2389
2390         /*
2391          * Setup the HW Rx Head and Tail Descriptor Pointers
2392          *   - needs to be after enable
2393          */
2394         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2395                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2396
2397                 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2398                 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2399         }
2400 }
2401
2402 static void
2403 igb_rxeof(struct igb_rx_ring *rxr, int count)
2404 {
2405         struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2406         union e1000_adv_rx_desc *cur;
2407         uint32_t staterr;
2408         int i;
2409
2410         i = rxr->next_to_check;
2411         cur = &rxr->rx_base[i];
2412         staterr = le32toh(cur->wb.upper.status_error);
2413
2414         if ((staterr & E1000_RXD_STAT_DD) == 0)
2415                 return;
2416
2417         while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2418                 struct pktinfo *pi = NULL, pi0;
2419                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2420                 struct mbuf *m = NULL;
2421                 boolean_t eop;
2422
2423                 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2424                 if (eop)
2425                         --count;
2426
2427                 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2428                     !rxr->discard) {
2429                         struct mbuf *mp = rxbuf->m_head;
2430                         uint32_t hash, hashtype;
2431                         uint16_t vlan;
2432                         int len;
2433
2434                         len = le16toh(cur->wb.upper.length);
2435                         if (rxr->sc->hw.mac.type == e1000_i350 &&
2436                             (staterr & E1000_RXDEXT_STATERR_LB))
2437                                 vlan = be16toh(cur->wb.upper.vlan);
2438                         else
2439                                 vlan = le16toh(cur->wb.upper.vlan);
2440
2441                         hash = le32toh(cur->wb.lower.hi_dword.rss);
2442                         hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2443                             E1000_RXDADV_RSSTYPE_MASK;
2444
2445                         IGB_RSS_DPRINTF(rxr->sc, 10,
2446                             "ring%d, hash 0x%08x, hashtype %u\n",
2447                             rxr->me, hash, hashtype);
2448
2449                         bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2450                             BUS_DMASYNC_POSTREAD);
2451
2452                         if (igb_newbuf(rxr, i, FALSE) != 0) {
2453                                 ifp->if_iqdrops++;
2454                                 goto discard;
2455                         }
2456
2457                         mp->m_len = len;
2458                         if (rxr->fmp == NULL) {
2459                                 mp->m_pkthdr.len = len;
2460                                 rxr->fmp = mp;
2461                                 rxr->lmp = mp;
2462                         } else {
2463                                 rxr->lmp->m_next = mp;
2464                                 rxr->lmp = rxr->lmp->m_next;
2465                                 rxr->fmp->m_pkthdr.len += len;
2466                         }
2467
2468                         if (eop) {
2469                                 m = rxr->fmp;
2470                                 rxr->fmp = NULL;
2471                                 rxr->lmp = NULL;
2472
2473                                 m->m_pkthdr.rcvif = ifp;
2474                                 ifp->if_ipackets++;
2475
2476                                 if (ifp->if_capenable & IFCAP_RXCSUM)
2477                                         igb_rxcsum(staterr, m);
2478
2479                                 if (staterr & E1000_RXD_STAT_VP) {
2480                                         m->m_pkthdr.ether_vlantag = vlan;
2481                                         m->m_flags |= M_VLANTAG;
2482                                 }
2483
2484                                 if (ifp->if_capenable & IFCAP_RSS) {
2485                                         pi = igb_rssinfo(m, &pi0,
2486                                             hash, hashtype, staterr);
2487                                 }
2488 #ifdef IGB_RSS_DEBUG
2489                                 rxr->rx_packets++;
2490 #endif
2491                         }
2492                 } else {
2493                         ifp->if_ierrors++;
2494 discard:
2495                         igb_setup_rxdesc(cur, rxbuf);
2496                         if (!eop)
2497                                 rxr->discard = TRUE;
2498                         else
2499                                 rxr->discard = FALSE;
2500                         if (rxr->fmp != NULL) {
2501                                 m_freem(rxr->fmp);
2502                                 rxr->fmp = NULL;
2503                                 rxr->lmp = NULL;
2504                         }
2505                         m = NULL;
2506                 }
2507
2508                 if (m != NULL)
2509                         ether_input_pkt(ifp, m, pi);
2510
2511                 /* Advance our pointers to the next descriptor. */
2512                 if (++i == rxr->num_rx_desc)
2513                         i = 0;
2514
2515                 cur = &rxr->rx_base[i];
2516                 staterr = le32toh(cur->wb.upper.status_error);
2517         }
2518         rxr->next_to_check = i;
2519
2520         if (--i < 0)
2521                 i = rxr->num_rx_desc - 1;
2522         E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2523 }
2524
2525
2526 static void
2527 igb_set_vlan(struct igb_softc *sc)
2528 {
2529         struct e1000_hw *hw = &sc->hw;
2530         uint32_t reg;
2531 #if 0
2532         struct ifnet *ifp = sc->arpcom.ac_if;
2533 #endif
2534
2535         if (sc->vf_ifp) {
2536                 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2537                 return;
2538         }
2539
2540         reg = E1000_READ_REG(hw, E1000_CTRL);
2541         reg |= E1000_CTRL_VME;
2542         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2543
2544 #if 0
2545         /* Enable the Filter Table */
2546         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2547                 reg = E1000_READ_REG(hw, E1000_RCTL);
2548                 reg &= ~E1000_RCTL_CFIEN;
2549                 reg |= E1000_RCTL_VFE;
2550                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2551         }
2552 #endif
2553
2554         /* Update the frame size */
2555         E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2556             sc->max_frame_size + VLAN_TAG_SIZE);
2557
2558 #if 0
2559         /* Don't bother with table if no vlans */
2560         if ((adapter->num_vlans == 0) ||
2561             ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2562                 return;
2563         /*
2564         ** A soft reset zero's out the VFTA, so
2565         ** we need to repopulate it now.
2566         */
2567         for (int i = 0; i < IGB_VFTA_SIZE; i++)
2568                 if (adapter->shadow_vfta[i] != 0) {
2569                         if (adapter->vf_ifp)
2570                                 e1000_vfta_set_vf(hw,
2571                                     adapter->shadow_vfta[i], TRUE);
2572                         else
2573                                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2574                                  i, adapter->shadow_vfta[i]);
2575                 }
2576 #endif
2577 }
2578
2579 static void
2580 igb_enable_intr(struct igb_softc *sc)
2581 {
2582         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2583                 lwkt_serialize_handler_enable(&sc->main_serialize);
2584         } else {
2585                 int i;
2586
2587                 for (i = 0; i < sc->msix_cnt; ++i) {
2588                         lwkt_serialize_handler_enable(
2589                             sc->msix_data[i].msix_serialize);
2590                 }
2591         }
2592
2593         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2594                 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2595                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2596                 else
2597                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2598                 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2599                 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2600                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2601         } else {
2602                 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2603         }
2604         E1000_WRITE_FLUSH(&sc->hw);
2605 }
2606
2607 static void
2608 igb_disable_intr(struct igb_softc *sc)
2609 {
2610         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2611                 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2612                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2613         }
2614         E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2615         E1000_WRITE_FLUSH(&sc->hw);
2616
2617         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2618                 lwkt_serialize_handler_disable(&sc->main_serialize);
2619         } else {
2620                 int i;
2621
2622                 for (i = 0; i < sc->msix_cnt; ++i) {
2623                         lwkt_serialize_handler_disable(
2624                             sc->msix_data[i].msix_serialize);
2625                 }
2626         }
2627 }
2628
2629 /*
2630  * Bit of a misnomer, what this really means is
2631  * to enable OS management of the system... aka
2632  * to disable special hardware management features 
2633  */
2634 static void
2635 igb_get_mgmt(struct igb_softc *sc)
2636 {
2637         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2638                 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2639                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2640
2641                 /* disable hardware interception of ARP */
2642                 manc &= ~E1000_MANC_ARP_EN;
2643
2644                 /* enable receiving management packets to the host */
2645                 manc |= E1000_MANC_EN_MNG2HOST;
2646                 manc2h |= 1 << 5; /* Mng Port 623 */
2647                 manc2h |= 1 << 6; /* Mng Port 664 */
2648                 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2649                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2650         }
2651 }
2652
2653 /*
2654  * Give control back to hardware management controller
2655  * if there is one.
2656  */
2657 static void
2658 igb_rel_mgmt(struct igb_softc *sc)
2659 {
2660         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2661                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2662
2663                 /* Re-enable hardware interception of ARP */
2664                 manc |= E1000_MANC_ARP_EN;
2665                 manc &= ~E1000_MANC_EN_MNG2HOST;
2666
2667                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2668         }
2669 }
2670
2671 /*
2672  * Sets CTRL_EXT:DRV_LOAD bit.
2673  *
2674  * For ASF and Pass Through versions of f/w this means that
2675  * the driver is loaded. 
2676  */
2677 static void
2678 igb_get_hw_control(struct igb_softc *sc)
2679 {
2680         uint32_t ctrl_ext;
2681
2682         if (sc->vf_ifp)
2683                 return;
2684
2685         /* Let firmware know the driver has taken over */
2686         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2687         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2688             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2689 }
2690
2691 /*
2692  * Resets CTRL_EXT:DRV_LOAD bit.
2693  *
2694  * For ASF and Pass Through versions of f/w this means that the
2695  * driver is no longer loaded.
2696  */
2697 static void
2698 igb_rel_hw_control(struct igb_softc *sc)
2699 {
2700         uint32_t ctrl_ext;
2701
2702         if (sc->vf_ifp)
2703                 return;
2704
2705         /* Let firmware taken over control of h/w */
2706         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2707         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2708             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2709 }
2710
2711 static int
2712 igb_is_valid_ether_addr(const uint8_t *addr)
2713 {
2714         uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2715
2716         if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2717                 return FALSE;
2718         return TRUE;
2719 }
2720
2721 /*
2722  * Enable PCI Wake On Lan capability
2723  */
2724 static void
2725 igb_enable_wol(device_t dev)
2726 {
2727         uint16_t cap, status;
2728         uint8_t id;
2729
2730         /* First find the capabilities pointer*/
2731         cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2732
2733         /* Read the PM Capabilities */
2734         id = pci_read_config(dev, cap, 1);
2735         if (id != PCIY_PMG)     /* Something wrong */
2736                 return;
2737
2738         /*
2739          * OK, we have the power capabilities,
2740          * so now get the status register
2741          */
2742         cap += PCIR_POWER_STATUS;
2743         status = pci_read_config(dev, cap, 2);
2744         status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2745         pci_write_config(dev, cap, status, 2);
2746 }
2747
2748 static void
2749 igb_update_stats_counters(struct igb_softc *sc)
2750 {
2751         struct e1000_hw *hw = &sc->hw;
2752         struct e1000_hw_stats *stats;
2753         struct ifnet *ifp = &sc->arpcom.ac_if;
2754
2755         /* 
2756          * The virtual function adapter has only a
2757          * small controlled set of stats, do only 
2758          * those and return.
2759          */
2760         if (sc->vf_ifp) {
2761                 igb_update_vf_stats_counters(sc);
2762                 return;
2763         }
2764         stats = sc->stats;
2765
2766         if (sc->hw.phy.media_type == e1000_media_type_copper ||
2767             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2768                 stats->symerrs +=
2769                     E1000_READ_REG(hw,E1000_SYMERRS);
2770                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2771         }
2772
2773         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2774         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2775         stats->scc += E1000_READ_REG(hw, E1000_SCC);
2776         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2777
2778         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2779         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2780         stats->colc += E1000_READ_REG(hw, E1000_COLC);
2781         stats->dc += E1000_READ_REG(hw, E1000_DC);
2782         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2783         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2784         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2785
2786         /*
2787          * For watchdog management we need to know if we have been
2788          * paused during the last interval, so capture that here.
2789          */ 
2790         sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2791         stats->xoffrxc += sc->pause_frames;
2792         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2793         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2794         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2795         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2796         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2797         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2798         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2799         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2800         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2801         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2802         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2803         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2804
2805         /* For the 64-bit byte counters the low dword must be read first. */
2806         /* Both registers clear on the read of the high dword */
2807
2808         stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2809             ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2810         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2811             ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2812
2813         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2814         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2815         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2816         stats->roc += E1000_READ_REG(hw, E1000_ROC);
2817         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2818
2819         stats->tor += E1000_READ_REG(hw, E1000_TORH);
2820         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2821
2822         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2823         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2824         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2825         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2826         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2827         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2828         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2829         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2830         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2831         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2832
2833         /* Interrupt Counts */
2834
2835         stats->iac += E1000_READ_REG(hw, E1000_IAC);
2836         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2837         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2838         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2839         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2840         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2841         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2842         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2843         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2844
2845         /* Host to Card Statistics */
2846
2847         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2848         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2849         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2850         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2851         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2852         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2853         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2854         stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2855             ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2856         stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2857             ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2858         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2859         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2860         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2861
2862         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2863         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2864         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2865         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2866         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2867         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2868
2869         ifp->if_collisions = stats->colc;
2870
2871         /* Rx Errors */
2872         ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2873             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2874
2875         /* Tx Errors */
2876         ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2877
2878         /* Driver specific counters */
2879         sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2880         sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2881         sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2882         sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2883         sc->packet_buf_alloc_tx =
2884             ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2885         sc->packet_buf_alloc_rx =
2886             (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2887 }
2888
2889 static void
2890 igb_vf_init_stats(struct igb_softc *sc)
2891 {
2892         struct e1000_hw *hw = &sc->hw;
2893         struct e1000_vf_stats *stats;
2894
2895         stats = sc->stats;
2896         stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2897         stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2898         stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2899         stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2900         stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2901 }
2902  
2903 static void
2904 igb_update_vf_stats_counters(struct igb_softc *sc)
2905 {
2906         struct e1000_hw *hw = &sc->hw;
2907         struct e1000_vf_stats *stats;
2908
2909         if (sc->link_speed == 0)
2910                 return;
2911
2912         stats = sc->stats;
2913         UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2914         UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2915         UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2916         UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2917         UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
2918 }
2919
2920 #ifdef IFPOLL_ENABLE
2921
2922 static void
2923 igb_npoll_status(struct ifnet *ifp, int pollhz __unused)
2924 {
2925         struct igb_softc *sc = ifp->if_softc;
2926         uint32_t reg_icr;
2927
2928         ASSERT_SERIALIZED(&sc->main_serialize);
2929
2930         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2931         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2932                 sc->hw.mac.get_link_status = 1;
2933                 igb_update_link_status(sc);
2934         }
2935 }
2936
2937 static void
2938 igb_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
2939 {
2940         struct igb_tx_ring *txr = arg;
2941
2942         ASSERT_SERIALIZED(&txr->tx_serialize);
2943
2944         igb_txeof(txr);
2945         if (!ifq_is_empty(&ifp->if_snd))
2946                 if_devstart(ifp);
2947 }
2948
2949 static void
2950 igb_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
2951 {
2952         struct igb_rx_ring *rxr = arg;
2953
2954         ASSERT_SERIALIZED(&rxr->rx_serialize);
2955
2956         igb_rxeof(rxr, cycle);
2957 }
2958
2959 static void
2960 igb_npoll(struct ifnet *ifp, struct ifpoll_info *info)
2961 {
2962         struct igb_softc *sc = ifp->if_softc;
2963
2964         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2965
2966         if (info) {
2967                 struct igb_tx_ring *txr;
2968                 int i, off;
2969
2970                 info->ifpi_status.status_func = igb_npoll_status;
2971                 info->ifpi_status.serializer = &sc->main_serialize;
2972
2973                 off = sc->tx_npoll_off;
2974                 KKASSERT(off < ncpus2);
2975                 txr = &sc->tx_rings[0];
2976                 info->ifpi_tx[off].poll_func = igb_npoll_tx;
2977                 info->ifpi_tx[off].arg = txr;
2978                 info->ifpi_tx[off].serializer = &txr->tx_serialize;
2979
2980                 off = sc->rx_npoll_off;
2981                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
2982                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
2983                         int idx = i + off;
2984
2985                         KKASSERT(idx < ncpus2);
2986                         info->ifpi_rx[idx].poll_func = igb_npoll_rx;
2987                         info->ifpi_rx[idx].arg = rxr;
2988                         info->ifpi_rx[idx].serializer = &rxr->rx_serialize;
2989                 }
2990
2991                 if (ifp->if_flags & IFF_RUNNING) {
2992                         if (sc->rx_ring_inuse == sc->rx_ring_cnt)
2993                                 igb_disable_intr(sc);
2994                         else
2995                                 igb_init(sc);
2996                 }
2997                 ifp->if_npoll_cpuid = sc->tx_npoll_off;
2998         } else {
2999                 if (ifp->if_flags & IFF_RUNNING) {
3000                         if (sc->rx_ring_inuse == sc->rx_ring_cnt)
3001                                 igb_enable_intr(sc);
3002                         else
3003                                 igb_init(sc);
3004                 }
3005                 ifp->if_npoll_cpuid = -1;
3006         }
3007 }
3008
3009 #endif /* IFPOLL_ENABLE */
3010
3011 static void
3012 igb_intr(void *xsc)
3013 {
3014         struct igb_softc *sc = xsc;
3015         struct ifnet *ifp = &sc->arpcom.ac_if;
3016         uint32_t eicr;
3017
3018         ASSERT_SERIALIZED(&sc->main_serialize);
3019
3020         eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
3021
3022         if (eicr == 0)
3023                 return;
3024
3025         if (ifp->if_flags & IFF_RUNNING) {
3026                 struct igb_tx_ring *txr;
3027                 int i;
3028
3029                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3030                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
3031
3032                         if (eicr & rxr->rx_intr_mask) {
3033                                 lwkt_serialize_enter(&rxr->rx_serialize);
3034                                 igb_rxeof(rxr, -1);
3035                                 lwkt_serialize_exit(&rxr->rx_serialize);
3036                         }
3037                 }
3038
3039                 txr = &sc->tx_rings[0];
3040                 if (eicr & txr->tx_intr_mask) {
3041                         lwkt_serialize_enter(&txr->tx_serialize);
3042                         igb_txeof(txr);
3043                         if (!ifq_is_empty(&ifp->if_snd))
3044                                 if_devstart(ifp);
3045                         lwkt_serialize_exit(&txr->tx_serialize);
3046                 }
3047         }
3048
3049         if (eicr & E1000_EICR_OTHER) {
3050                 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3051
3052                 /* Link status change */
3053                 if (icr & E1000_ICR_LSC) {
3054                         sc->hw.mac.get_link_status = 1;
3055                         igb_update_link_status(sc);
3056                 }
3057         }
3058
3059         /*
3060          * Reading EICR has the side effect to clear interrupt mask,
3061          * so all interrupts need to be enabled here.
3062          */
3063         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
3064 }
3065
3066 static void
3067 igb_intr_shared(void *xsc)
3068 {
3069         struct igb_softc *sc = xsc;
3070         struct ifnet *ifp = &sc->arpcom.ac_if;
3071         uint32_t reg_icr;
3072
3073         ASSERT_SERIALIZED(&sc->main_serialize);
3074
3075         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3076
3077         /* Hot eject?  */
3078         if (reg_icr == 0xffffffff)
3079                 return;
3080
3081         /* Definitely not our interrupt.  */
3082         if (reg_icr == 0x0)
3083                 return;
3084
3085         if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3086                 return;
3087
3088         if (ifp->if_flags & IFF_RUNNING) {
3089                 if (reg_icr &
3090                     (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3091                         int i;
3092
3093                         for (i = 0; i < sc->rx_ring_inuse; ++i) {
3094                                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3095
3096                                 lwkt_serialize_enter(&rxr->rx_serialize);
3097                                 igb_rxeof(rxr, -1);
3098                                 lwkt_serialize_exit(&rxr->rx_serialize);
3099                         }
3100                 }
3101
3102                 if (reg_icr & E1000_ICR_TXDW) {
3103                         struct igb_tx_ring *txr = &sc->tx_rings[0];
3104
3105                         lwkt_serialize_enter(&txr->tx_serialize);
3106                         igb_txeof(txr);
3107                         if (!ifq_is_empty(&ifp->if_snd))
3108                                 if_devstart(ifp);
3109                         lwkt_serialize_exit(&txr->tx_serialize);
3110                 }
3111         }
3112
3113         /* Link status change */
3114         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3115                 sc->hw.mac.get_link_status = 1;
3116                 igb_update_link_status(sc);
3117         }
3118
3119         if (reg_icr & E1000_ICR_RXO)
3120                 sc->rx_overruns++;
3121 }
3122
3123 static int
3124 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp)
3125 {
3126         bus_dma_segment_t segs[IGB_MAX_SCATTER];
3127         bus_dmamap_t map;
3128         struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3129         union e1000_adv_tx_desc *txd = NULL;
3130         struct mbuf *m_head = *m_headp;
3131         uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3132         int maxsegs, nsegs, i, j, error, last = 0;
3133         uint32_t hdrlen = 0;
3134
3135         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3136                 error = igb_tso_pullup(txr, m_headp);
3137                 if (error)
3138                         return error;
3139                 m_head = *m_headp;
3140         }
3141
3142         /* Set basic descriptor constants */
3143         cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3144         cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3145         if (m_head->m_flags & M_VLANTAG)
3146                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3147
3148         /*
3149          * Map the packet for DMA.
3150          */
3151         tx_buf = &txr->tx_buf[txr->next_avail_desc];
3152         tx_buf_mapped = tx_buf;
3153         map = tx_buf->map;
3154
3155         maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3156         KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3157         if (maxsegs > IGB_MAX_SCATTER)
3158                 maxsegs = IGB_MAX_SCATTER;
3159
3160         error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3161             segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3162         if (error) {
3163                 if (error == ENOBUFS)
3164                         txr->sc->mbuf_defrag_failed++;
3165                 else
3166                         txr->sc->no_tx_dma_setup++;
3167
3168                 m_freem(*m_headp);
3169                 *m_headp = NULL;
3170                 return error;
3171         }
3172         bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3173
3174         m_head = *m_headp;
3175
3176         /*
3177          * Set up the TX context descriptor, if any hardware offloading is
3178          * needed.  This includes CSUM, VLAN, and TSO.  It will consume one
3179          * TX descriptor.
3180          *
3181          * Unlike these chips' predecessors (em/emx), TX context descriptor
3182          * will _not_ interfere TX data fetching pipelining.
3183          */
3184         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3185                 igb_tso_ctx(txr, m_head, &hdrlen);
3186                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3187                 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3188                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3189                 txr->tx_nsegs++;
3190         } else if (igb_txcsum_ctx(txr, m_head)) {
3191                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3192                         olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3193                 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3194                         olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3195                 txr->tx_nsegs++;
3196         }
3197
3198         txr->tx_nsegs += nsegs;
3199         if (txr->tx_nsegs >= txr->intr_nsegs) {
3200                 /*
3201                  * Report Status (RS) is turned on every intr_nsegs
3202                  * descriptors (roughly).
3203                  */
3204                 txr->tx_nsegs = 0;
3205                 cmd_rs = E1000_ADVTXD_DCMD_RS;
3206         }
3207
3208         /* Calculate payload length */
3209         olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3210             << E1000_ADVTXD_PAYLEN_SHIFT);
3211
3212         /* 82575 needs the queue index added */
3213         if (txr->sc->hw.mac.type == e1000_82575)
3214                 olinfo_status |= txr->me << 4;
3215
3216         /* Set up our transmit descriptors */
3217         i = txr->next_avail_desc;
3218         for (j = 0; j < nsegs; j++) {
3219                 bus_size_t seg_len;
3220                 bus_addr_t seg_addr;
3221
3222                 tx_buf = &txr->tx_buf[i];
3223                 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3224                 seg_addr = segs[j].ds_addr;
3225                 seg_len = segs[j].ds_len;
3226
3227                 txd->read.buffer_addr = htole64(seg_addr);
3228                 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3229                 txd->read.olinfo_status = htole32(olinfo_status);
3230                 last = i;
3231                 if (++i == txr->num_tx_desc)
3232                         i = 0;
3233                 tx_buf->m_head = NULL;
3234         }
3235
3236         KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3237         txr->next_avail_desc = i;
3238         txr->tx_avail -= nsegs;
3239
3240         tx_buf->m_head = m_head;
3241         tx_buf_mapped->map = tx_buf->map;
3242         tx_buf->map = map;
3243
3244         /*
3245          * Last Descriptor of Packet needs End Of Packet (EOP)
3246          */
3247         txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3248
3249         /*
3250          * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
3251          * that this frame is available to transmit.
3252          */
3253         E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), i);
3254         ++txr->tx_packets;
3255
3256         return 0;
3257 }
3258
3259 static void
3260 igb_start(struct ifnet *ifp)
3261 {
3262         struct igb_softc *sc = ifp->if_softc;
3263         struct igb_tx_ring *txr = &sc->tx_rings[0];
3264         struct mbuf *m_head;
3265
3266         ASSERT_SERIALIZED(&txr->tx_serialize);
3267
3268         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
3269                 return;
3270
3271         if (!sc->link_active) {
3272                 ifq_purge(&ifp->if_snd);
3273                 return;
3274         }
3275
3276         if (!IGB_IS_NOT_OACTIVE(txr))
3277                 igb_txeof(txr);
3278
3279         while (!ifq_is_empty(&ifp->if_snd)) {
3280                 if (IGB_IS_OACTIVE(txr)) {
3281                         ifp->if_flags |= IFF_OACTIVE;
3282                         /* Set watchdog on */
3283                         ifp->if_timer = 5;
3284                         break;
3285                 }
3286
3287                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3288                 if (m_head == NULL)
3289                         break;
3290
3291                 if (igb_encap(txr, &m_head)) {
3292                         ifp->if_oerrors++;
3293                         continue;
3294                 }
3295
3296                 /* Send a copy of the frame to the BPF listener */
3297                 ETHER_BPF_MTAP(ifp, m_head);
3298         }
3299 }
3300
3301 static void
3302 igb_watchdog(struct ifnet *ifp)
3303 {
3304         struct igb_softc *sc = ifp->if_softc;
3305         struct igb_tx_ring *txr = &sc->tx_rings[0];
3306
3307         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3308
3309         /* 
3310          * If flow control has paused us since last checking
3311          * it invalidates the watchdog timing, so dont run it.
3312          */
3313         if (sc->pause_frames) {
3314                 sc->pause_frames = 0;
3315                 ifp->if_timer = 5;
3316                 return;
3317         }
3318
3319         if_printf(ifp, "Watchdog timeout -- resetting\n");
3320         if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3321             E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3322             E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3323         if_printf(ifp, "TX(%d) desc avail = %d, "
3324             "Next TX to Clean = %d\n",
3325             txr->me, txr->tx_avail, txr->next_to_clean);
3326
3327         ifp->if_oerrors++;
3328         sc->watchdog_events++;
3329
3330         igb_init(sc);
3331         if (!ifq_is_empty(&ifp->if_snd))
3332                 if_devstart(ifp);
3333 }
3334
3335 static void
3336 igb_set_eitr(struct igb_softc *sc, int idx, int rate)
3337 {
3338         uint32_t eitr = 0;
3339
3340         if (rate > 0) {
3341                 if (sc->hw.mac.type == e1000_82575) {
3342                         eitr = 1000000000 / 256 / rate;
3343                         /*
3344                          * NOTE:
3345                          * Document is wrong on the 2 bits left shift
3346                          */
3347                 } else {
3348                         eitr = 1000000 / rate;
3349                         eitr <<= IGB_EITR_INTVL_SHIFT;
3350                 }
3351
3352                 if (eitr == 0) {
3353                         /* Don't disable it */
3354                         eitr = 1 << IGB_EITR_INTVL_SHIFT;
3355                 } else if (eitr > IGB_EITR_INTVL_MASK) {
3356                         /* Don't allow it to be too large */
3357                         eitr = IGB_EITR_INTVL_MASK;
3358                 }
3359         }
3360         if (sc->hw.mac.type == e1000_82575)
3361                 eitr |= eitr << 16;
3362         else
3363                 eitr |= E1000_EITR_CNT_IGNR;
3364         E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
3365 }
3366
3367 static int
3368 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3369 {
3370         struct igb_softc *sc = (void *)arg1;
3371         struct ifnet *ifp = &sc->arpcom.ac_if;
3372         int error, intr_rate;
3373
3374         intr_rate = sc->intr_rate;
3375         error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3376         if (error || req->newptr == NULL)
3377                 return error;
3378         if (intr_rate < 0)
3379                 return EINVAL;
3380
3381         ifnet_serialize_all(ifp);
3382
3383         sc->intr_rate = intr_rate;
3384         if (ifp->if_flags & IFF_RUNNING)
3385                 igb_set_eitr(sc, 0, sc->intr_rate);
3386
3387         if (bootverbose)
3388                 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
3389
3390         ifnet_deserialize_all(ifp);
3391
3392         return 0;
3393 }
3394
3395 static int
3396 igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3397 {
3398         struct igb_msix_data *msix = (void *)arg1;
3399         struct igb_softc *sc = msix->msix_sc;
3400         struct ifnet *ifp = &sc->arpcom.ac_if;
3401         int error, msix_rate;
3402
3403         msix_rate = msix->msix_rate;
3404         error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3405         if (error || req->newptr == NULL)
3406                 return error;
3407         if (msix_rate < 0)
3408                 return EINVAL;
3409
3410         lwkt_serialize_enter(msix->msix_serialize);
3411
3412         msix->msix_rate = msix_rate;
3413         if (ifp->if_flags & IFF_RUNNING)
3414                 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3415
3416         if (bootverbose) {
3417                 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3418                     msix->msix_rate);
3419         }
3420
3421         lwkt_serialize_exit(msix->msix_serialize);
3422
3423         return 0;
3424 }
3425
3426 static int
3427 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3428 {
3429         struct igb_softc *sc = (void *)arg1;
3430         struct ifnet *ifp = &sc->arpcom.ac_if;
3431         struct igb_tx_ring *txr = &sc->tx_rings[0];
3432         int error, nsegs;
3433
3434         nsegs = txr->intr_nsegs;
3435         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3436         if (error || req->newptr == NULL)
3437                 return error;
3438         if (nsegs <= 0)
3439                 return EINVAL;
3440
3441         ifnet_serialize_all(ifp);
3442
3443         if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3444             nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3445                 error = EINVAL;
3446         } else {
3447                 error = 0;
3448                 txr->intr_nsegs = nsegs;
3449         }
3450
3451         ifnet_deserialize_all(ifp);
3452
3453         return error;
3454 }
3455
3456 #ifdef IFPOLL_ENABLE
3457
3458 static int
3459 igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3460 {
3461         struct igb_softc *sc = (void *)arg1;
3462         struct ifnet *ifp = &sc->arpcom.ac_if;
3463         int error, off;
3464
3465         off = sc->rx_npoll_off;
3466         error = sysctl_handle_int(oidp, &off, 0, req);
3467         if (error || req->newptr == NULL)
3468                 return error;
3469         if (off < 0)
3470                 return EINVAL;
3471
3472         ifnet_serialize_all(ifp);
3473         if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3474                 error = EINVAL;
3475         } else {
3476                 error = 0;
3477                 sc->rx_npoll_off = off;
3478         }
3479         ifnet_deserialize_all(ifp);
3480
3481         return error;
3482 }
3483
3484 static int
3485 igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3486 {
3487         struct igb_softc *sc = (void *)arg1;
3488         struct ifnet *ifp = &sc->arpcom.ac_if;
3489         int error, off;
3490
3491         off = sc->tx_npoll_off;
3492         error = sysctl_handle_int(oidp, &off, 0, req);
3493         if (error || req->newptr == NULL)
3494                 return error;
3495         if (off < 0)
3496                 return EINVAL;
3497
3498         ifnet_serialize_all(ifp);
3499         if (off >= ncpus2) {
3500                 error = EINVAL;
3501         } else {
3502                 error = 0;
3503                 sc->tx_npoll_off = off;
3504         }
3505         ifnet_deserialize_all(ifp);
3506
3507         return error;
3508 }
3509
3510 #endif  /* IFPOLL_ENABLE */
3511
3512 static void
3513 igb_init_intr(struct igb_softc *sc)
3514 {
3515         igb_set_intr_mask(sc);
3516
3517         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
3518                 igb_init_unshared_intr(sc);
3519
3520         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3521                 igb_set_eitr(sc, 0, sc->intr_rate);
3522         } else {
3523                 int i;
3524
3525                 for (i = 0; i < sc->msix_cnt; ++i)
3526                         igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3527         }
3528 }
3529
3530 static void
3531 igb_init_unshared_intr(struct igb_softc *sc)
3532 {
3533         struct e1000_hw *hw = &sc->hw;
3534         const struct igb_rx_ring *rxr;
3535         const struct igb_tx_ring *txr;
3536         uint32_t ivar, index;
3537         int i;
3538
3539         /*
3540          * Enable extended mode
3541          */
3542         if (sc->hw.mac.type != e1000_82575) {
3543                 uint32_t gpie;
3544                 int ivar_max;
3545
3546                 gpie = E1000_GPIE_NSICR;
3547                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3548                         gpie |= E1000_GPIE_MSIX_MODE |
3549                             E1000_GPIE_EIAME |
3550                             E1000_GPIE_PBA;
3551                 }
3552                 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3553
3554                 /*
3555                  * Clear IVARs
3556                  */
3557                 switch (sc->hw.mac.type) {
3558                 case e1000_82580:
3559                         ivar_max = IGB_MAX_IVAR_82580;
3560                         break;
3561
3562                 case e1000_i350:
3563                         ivar_max = IGB_MAX_IVAR_I350;
3564                         break;
3565
3566                 case e1000_vfadapt:
3567                 case e1000_vfadapt_i350:
3568                         ivar_max = IGB_MAX_IVAR_VF;
3569                         break;
3570
3571                 case e1000_82576:
3572                         ivar_max = IGB_MAX_IVAR_82576;
3573                         break;
3574
3575                 default:
3576                         panic("unknown mac type %d\n", sc->hw.mac.type);
3577                 }
3578                 for (i = 0; i < ivar_max; ++i)
3579                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3580                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3581         } else {
3582                 uint32_t tmp;
3583
3584                 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3585                     ("82575 w/ MSI-X"));
3586                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3587                 tmp |= E1000_CTRL_EXT_IRCA;
3588                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3589         }
3590
3591         /*
3592          * Map TX/RX interrupts to EICR
3593          */
3594         switch (sc->hw.mac.type) {
3595         case e1000_82580:
3596         case e1000_i350:
3597         case e1000_vfadapt:
3598         case e1000_vfadapt_i350:
3599                 /* RX entries */
3600                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3601                         rxr = &sc->rx_rings[i];
3602
3603                         index = i >> 1;
3604                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3605
3606                         if (i & 1) {
3607                                 ivar &= 0xff00ffff;
3608                                 ivar |=
3609                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3610                         } else {
3611                                 ivar &= 0xffffff00;
3612                                 ivar |=
3613                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3614                         }
3615                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3616                 }
3617                 /* TX entries */
3618                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3619                         txr = &sc->tx_rings[i];
3620
3621                         index = i >> 1;
3622                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3623
3624                         if (i & 1) {
3625                                 ivar &= 0x00ffffff;
3626                                 ivar |=
3627                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3628                         } else {
3629                                 ivar &= 0xffff00ff;
3630                                 ivar |=
3631                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3632                         }
3633                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3634                 }
3635                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3636                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3637                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3638                 }
3639                 break;
3640
3641         case e1000_82576:
3642                 /* RX entries */
3643                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3644                         rxr = &sc->rx_rings[i];
3645
3646                         index = i & 0x7; /* Each IVAR has two entries */
3647                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3648
3649                         if (i < 8) {
3650                                 ivar &= 0xffffff00;
3651                                 ivar |=
3652                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3653                         } else {
3654                                 ivar &= 0xff00ffff;
3655                                 ivar |=
3656                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3657                         }
3658                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3659                 }
3660                 /* TX entries */
3661                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3662                         txr = &sc->tx_rings[i];
3663
3664                         index = i & 0x7; /* Each IVAR has two entries */
3665                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3666
3667                         if (i < 8) {
3668                                 ivar &= 0xffff00ff;
3669                                 ivar |=
3670                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3671                         } else {
3672                                 ivar &= 0x00ffffff;
3673                                 ivar |=
3674                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3675                         }
3676                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3677                 }
3678                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3679                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3680                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3681                 }
3682                 break;
3683
3684         case e1000_82575:
3685                 /*
3686                  * Enable necessary interrupt bits.
3687                  *
3688                  * The name of the register is confusing; in addition to
3689                  * configuring the first vector of MSI-X, it also configures
3690                  * which bits of EICR could be set by the hardware even when
3691                  * MSI or line interrupt is used; it thus controls interrupt
3692                  * generation.  It MUST be configured explicitly; the default
3693                  * value mentioned in the datasheet is wrong: RX queue0 and
3694                  * TX queue0 are NOT enabled by default.
3695                  */
3696                 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3697                 break;
3698
3699         default:
3700                 panic("unknown mac type %d\n", sc->hw.mac.type);
3701         }
3702 }
3703
3704 static int
3705 igb_setup_intr(struct igb_softc *sc)
3706 {
3707         struct ifnet *ifp = &sc->arpcom.ac_if;
3708         int error;
3709
3710         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3711                 return igb_msix_setup(sc);
3712
3713         error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
3714             (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_intr_shared : igb_intr,
3715             sc, &sc->intr_tag, &sc->main_serialize);
3716         if (error) {
3717                 device_printf(sc->dev, "Failed to register interrupt handler");
3718                 return error;
3719         }
3720
3721         ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
3722         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3723
3724         return 0;
3725 }
3726
3727 static void
3728 igb_set_txintr_mask(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
3729 {
3730         if (txr->sc->hw.mac.type == e1000_82575) {
3731                 txr->tx_intr_bit = 0;   /* unused */
3732                 switch (txr->me) {
3733                 case 0:
3734                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3735                         break;
3736                 case 1:
3737                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3738                         break;
3739                 case 2:
3740                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3741                         break;
3742                 case 3:
3743                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3744                         break;
3745                 default:
3746                         panic("unsupported # of TX ring, %d\n", txr->me);
3747                 }
3748         } else {
3749                 int intr_bit = *intr_bit0;
3750
3751                 txr->tx_intr_bit = intr_bit % intr_bitmax;
3752                 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
3753
3754                 *intr_bit0 = intr_bit + 1;
3755         }
3756 }
3757
3758 static void
3759 igb_set_rxintr_mask(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
3760 {
3761         if (rxr->sc->hw.mac.type == e1000_82575) {
3762                 rxr->rx_intr_bit = 0;   /* unused */
3763                 switch (rxr->me) {
3764                 case 0:
3765                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3766                         break;
3767                 case 1:
3768                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3769                         break;
3770                 case 2:
3771                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3772                         break;
3773                 case 3:
3774                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3775                         break;
3776                 default:
3777                         panic("unsupported # of RX ring, %d\n", rxr->me);
3778                 }
3779         } else {
3780                 int intr_bit = *intr_bit0;
3781
3782                 rxr->rx_intr_bit = intr_bit % intr_bitmax;
3783                 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
3784
3785                 *intr_bit0 = intr_bit + 1;
3786         }
3787 }
3788
3789 static void
3790 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3791 {
3792         struct igb_softc *sc = ifp->if_softc;
3793
3794         ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
3795             sc->tx_serialize, sc->rx_serialize, slz);
3796 }
3797
3798 static void
3799 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3800 {
3801         struct igb_softc *sc = ifp->if_softc;
3802
3803         ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
3804             sc->tx_serialize, sc->rx_serialize, slz);
3805 }
3806
3807 static int
3808 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3809 {
3810         struct igb_softc *sc = ifp->if_softc;
3811
3812         return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
3813             sc->tx_serialize, sc->rx_serialize, slz);
3814 }
3815
3816 #ifdef INVARIANTS
3817
3818 static void
3819 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3820     boolean_t serialized)
3821 {
3822         struct igb_softc *sc = ifp->if_softc;
3823
3824         ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
3825             sc->tx_serialize, sc->rx_serialize, slz, serialized);
3826 }
3827
3828 #endif  /* INVARIANTS */
3829
3830 static void
3831 igb_set_intr_mask(struct igb_softc *sc)
3832 {
3833         int i;
3834
3835         sc->intr_mask = sc->sts_intr_mask;
3836         for (i = 0; i < sc->rx_ring_inuse; ++i)
3837                 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
3838         for (i = 0; i < sc->tx_ring_cnt; ++i)
3839                 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
3840         if (bootverbose) {
3841                 if_printf(&sc->arpcom.ac_if, "intr mask 0x%08x\n",
3842                     sc->intr_mask);
3843         }
3844 }
3845
3846 static int
3847 igb_alloc_intr(struct igb_softc *sc)
3848 {
3849         int i, intr_bit, intr_bitmax;
3850         u_int intr_flags;
3851
3852         igb_msix_try_alloc(sc);
3853         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3854                 goto done;
3855
3856         /*
3857          * Allocate MSI/legacy interrupt resource
3858          */
3859         sc->intr_type = pci_alloc_1intr(sc->dev, igb_msi_enable,
3860             &sc->intr_rid, &intr_flags);
3861
3862         if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
3863                 int unshared;
3864
3865                 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
3866                 if (!unshared) {
3867                         sc->flags |= IGB_FLAG_SHARED_INTR;
3868                         if (bootverbose)
3869                                 device_printf(sc->dev, "IRQ shared\n");
3870                 } else {
3871                         intr_flags &= ~RF_SHAREABLE;
3872                         if (bootverbose)
3873                                 device_printf(sc->dev, "IRQ unshared\n");
3874                 }
3875         }
3876
3877         sc->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
3878             &sc->intr_rid, intr_flags);
3879         if (sc->intr_res == NULL) {
3880                 device_printf(sc->dev, "Unable to allocate bus resource: "
3881                     "interrupt\n");
3882                 return ENXIO;
3883         }
3884
3885         /*
3886          * Setup MSI/legacy interrupt mask
3887          */
3888         switch (sc->hw.mac.type) {
3889         case e1000_82575:
3890                 intr_bitmax = IGB_MAX_TXRXINT_82575;
3891                 break;
3892         case e1000_82580:
3893                 intr_bitmax = IGB_MAX_TXRXINT_82580;
3894                 break;
3895         case e1000_i350:
3896                 intr_bitmax = IGB_MAX_TXRXINT_I350;
3897                 break;
3898         case e1000_82576:
3899                 intr_bitmax = IGB_MAX_TXRXINT_82576;
3900                 break;
3901         default:
3902                 intr_bitmax = IGB_MIN_TXRXINT;
3903                 break;
3904         }
3905         intr_bit = 0;
3906         for (i = 0; i < sc->tx_ring_cnt; ++i)
3907                 igb_set_txintr_mask(&sc->tx_rings[i], &intr_bit, intr_bitmax);
3908         for (i = 0; i < sc->rx_ring_cnt; ++i)
3909                 igb_set_rxintr_mask(&sc->rx_rings[i], &intr_bit, intr_bitmax);
3910         sc->sts_intr_bit = 0;
3911         sc->sts_intr_mask = E1000_EICR_OTHER;
3912
3913         /* Initialize interrupt rate */
3914         sc->intr_rate = IGB_INTR_RATE;
3915 done:
3916         igb_set_ring_inuse(sc, FALSE);
3917         igb_set_intr_mask(sc);
3918         return 0;
3919 }
3920
3921 static void
3922 igb_free_intr(struct igb_softc *sc)
3923 {
3924         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3925                 if (sc->intr_res != NULL) {
3926                         bus_release_resource(sc->dev, SYS_RES_IRQ, sc->intr_rid,
3927                             sc->intr_res);
3928                 }
3929                 if (sc->intr_type == PCI_INTR_TYPE_MSI)
3930                         pci_release_msi(sc->dev);
3931         } else {
3932                 igb_msix_free(sc, TRUE);
3933         }
3934 }
3935
3936 static void
3937 igb_teardown_intr(struct igb_softc *sc)
3938 {
3939         if (sc->intr_type != PCI_INTR_TYPE_MSIX)
3940                 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_tag);
3941         else
3942                 igb_msix_teardown(sc, sc->msix_cnt);
3943 }
3944
3945 static void
3946 igb_msix_try_alloc(struct igb_softc *sc)
3947 {
3948         int msix_enable, msix_cnt, msix_cnt2, alloc_cnt;
3949         int i, x, error;
3950         struct igb_msix_data *msix;
3951         boolean_t aggregate, setup = FALSE;
3952
3953         /*
3954          * Don't enable MSI-X on 82575, see:
3955          * 82575 specification update errata #25
3956          */
3957         if (sc->hw.mac.type == e1000_82575)
3958                 return;
3959
3960         /* Don't enable MSI-X on VF */
3961         if (sc->vf_ifp)
3962                 return;
3963
3964         msix_enable = device_getenv_int(sc->dev, "msix.enable",
3965             igb_msix_enable);
3966         if (!msix_enable)
3967                 return;
3968
3969         msix_cnt = pci_msix_count(sc->dev);
3970 #ifdef IGB_MSIX_DEBUG
3971         msix_cnt = device_getenv_int(sc->dev, "msix.count", msix_cnt);
3972 #endif
3973         if (msix_cnt <= 1) {
3974                 /* One MSI-X model does not make sense */
3975                 return;
3976         }
3977
3978         i = 0;
3979         while ((1 << (i + 1)) <= msix_cnt)
3980                 ++i;
3981         msix_cnt2 = 1 << i;
3982
3983         if (bootverbose) {
3984                 device_printf(sc->dev, "MSI-X count %d/%d\n",
3985                     msix_cnt2, msix_cnt);
3986         }
3987
3988         KKASSERT(msix_cnt2 <= msix_cnt);
3989         if (msix_cnt == msix_cnt2) {
3990                 /* We need at least one MSI-X for link status */
3991                 msix_cnt2 >>= 1;
3992                 if (msix_cnt2 <= 1) {
3993                         /* One MSI-X for RX/TX does not make sense */
3994                         device_printf(sc->dev, "not enough MSI-X for TX/RX, "
3995                             "MSI-X count %d/%d\n", msix_cnt2, msix_cnt);
3996                         return;
3997                 }
3998                 KKASSERT(msix_cnt > msix_cnt2);
3999
4000                 if (bootverbose) {
4001                         device_printf(sc->dev, "MSI-X count fixup %d/%d\n",
4002                             msix_cnt2, msix_cnt);
4003                 }
4004         }
4005
4006         sc->rx_ring_msix = sc->rx_ring_cnt;
4007         if (sc->rx_ring_msix > msix_cnt2)
4008                 sc->rx_ring_msix = msix_cnt2;
4009
4010         if (msix_cnt >= sc->tx_ring_cnt + sc->rx_ring_msix + 1) {
4011                 /*
4012                  * Independent TX/RX MSI-X
4013                  */
4014                 aggregate = FALSE;
4015                 if (bootverbose)
4016                         device_printf(sc->dev, "independent TX/RX MSI-X\n");
4017                 alloc_cnt = sc->tx_ring_cnt + sc->rx_ring_msix;
4018         } else {
4019                 /*
4020                  * Aggregate TX/RX MSI-X
4021                  */
4022                 aggregate = TRUE;
4023                 if (bootverbose)
4024                         device_printf(sc->dev, "aggregate TX/RX MSI-X\n");
4025                 alloc_cnt = msix_cnt2;
4026                 if (alloc_cnt > ncpus2)
4027                         alloc_cnt = ncpus2;
4028                 if (sc->rx_ring_msix > alloc_cnt)
4029                         sc->rx_ring_msix = alloc_cnt;
4030         }
4031         ++alloc_cnt;    /* For link status */
4032
4033         if (bootverbose) {
4034                 device_printf(sc->dev, "MSI-X alloc %d, RX ring %d\n",
4035                     alloc_cnt, sc->rx_ring_msix);
4036         }
4037
4038         sc->msix_mem_rid = PCIR_BAR(IGB_MSIX_BAR);
4039         sc->msix_mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4040             &sc->msix_mem_rid, RF_ACTIVE);
4041         if (sc->msix_mem_res == NULL) {
4042                 device_printf(sc->dev, "Unable to map MSI-X table\n");
4043                 return;
4044         }
4045
4046         sc->msix_cnt = alloc_cnt;
4047         sc->msix_data = kmalloc_cachealign(
4048             sizeof(struct igb_msix_data) * sc->msix_cnt,
4049             M_DEVBUF, M_WAITOK | M_ZERO);
4050         for (x = 0; x < sc->msix_cnt; ++x) {
4051                 msix = &sc->msix_data[x];
4052
4053                 lwkt_serialize_init(&msix->msix_serialize0);
4054                 msix->msix_sc = sc;
4055                 msix->msix_rid = -1;
4056                 msix->msix_vector = x;
4057                 msix->msix_mask = 1 << msix->msix_vector;
4058                 msix->msix_rate = IGB_INTR_RATE;
4059         }
4060
4061         x = 0;
4062         if (!aggregate) {
4063                 int offset, offset_def;
4064
4065                 if (sc->rx_ring_msix == ncpus2) {
4066                         offset = 0;
4067                 } else {
4068                         offset_def = (sc->rx_ring_msix *
4069                             device_get_unit(sc->dev)) % ncpus2;
4070
4071                         offset = device_getenv_int(sc->dev,
4072                             "msix.rxoff", offset_def);
4073                         if (offset >= ncpus2 ||
4074