1 /* $NetBSD: i82365.c,v 1.25 1999/10/15 06:07:27 haya Exp $ */
2 /* $FreeBSD: src/sys/dev/pcic/i82365.c,v 1.16.2.1 2000/05/23 03:57:02 imp Exp $ */
3 /* $DragonFly: src/sys/dev/misc/pcic/Attic/i82365.c,v 1.4 2003/07/19 21:14:25 dillon Exp $ */
6 * Copyright (c) 1997 Marc Horowitz. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Marc Horowitz.
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/kernel.h>
39 #include <sys/queue.h>
40 #include <sys/types.h>
43 #include <machine/bus.h>
45 #include <machine/resource.h>
47 #include <machine/clock.h>
51 #include <sys/kthread.h>
54 /* We shouldn't need to include the following, but sadly we do for now */
56 #include <dev/pccard/pccardreg.h>
57 #include <dev/pccard/pccardvar.h>
59 #include <dev/pcic/i82365reg.h>
60 #include <dev/pcic/i82365var.h>
68 #define DPRINTF(arg) if (pcic_debug) printf arg;
69 #define DEVPRINTF(arg) if (pcic_debug) device_printf arg;
72 #define DEVPRINTF(arg)
75 #define DETACH_FORCE 0x1
77 #define PCIC_VENDOR_UNKNOWN 0
78 #define PCIC_VENDOR_I82365SLR0 1
79 #define PCIC_VENDOR_I82365SLR1 2
80 #define PCIC_VENDOR_CIRRUS_PD6710 3
81 #define PCIC_VENDOR_CIRRUS_PD672X 4
84 * Individual drivers will allocate their own memory and io regions. Memory
85 * regions must be a multiple of 4k, aligned on a 4k boundary.
88 #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE
90 static void pcic_init_socket(struct pcic_handle *);
92 static void pcic_intr_socket(struct pcic_handle *);
94 static void pcic_deactivate(device_t dev);
95 static int pcic_activate(device_t dev);
96 static void pcic_intr(void *arg);
98 static void pcic_attach_card(struct pcic_handle *);
99 static void pcic_detach_card(struct pcic_handle *, int);
101 static void pcic_chip_do_mem_map(struct pcic_handle *, int);
102 static void pcic_chip_do_io_map(struct pcic_handle *, int);
104 void pcic_create_event_thread(void *);
105 void pcic_event_thread(void *);
107 void pcic_queue_event(struct pcic_handle *, int);
109 static void pcic_wait_ready(struct pcic_handle *);
111 static u_int8_t st_pcic_read(struct pcic_handle *, int);
112 static void st_pcic_write(struct pcic_handle *, int, u_int8_t);
114 /* XXX Should really be dynamic XXX */
115 static struct pcic_handle *handles[20];
116 static struct pcic_handle **lasthandle = handles;
118 static struct pcic_handle *
119 pcic_get_handle(device_t dev, device_t child)
123 while (child && device_get_parent(child) != dev)
124 child = device_get_parent(child);
127 return ((struct pcic_handle *) device_get_ivars(child));
131 pcic_ident_ok(int ident)
133 /* this is very empirical and heuristic */
135 if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO))
138 if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) {
140 printf("pcic: does not support memory and I/O cards, "
141 "ignored (ident=%0x)\n", ident);
149 pcic_vendor(struct pcic_handle *h)
154 * the chip_id of the cirrus toggles between 11 and 00 after a write.
158 pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0);
159 reg = pcic_read(h, -1);
161 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) ==
162 PCIC_CIRRUS_CHIP_INFO_CHIP_ID) {
163 reg = pcic_read(h, -1);
164 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) {
165 if (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS)
166 return (PCIC_VENDOR_CIRRUS_PD672X);
168 return (PCIC_VENDOR_CIRRUS_PD6710);
172 reg = pcic_read(h, PCIC_IDENT);
174 if ((reg & PCIC_IDENT_REV_MASK) == PCIC_IDENT_REV_I82365SLR0)
175 return (PCIC_VENDOR_I82365SLR0);
177 return (PCIC_VENDOR_I82365SLR1);
179 return (PCIC_VENDOR_UNKNOWN);
183 pcic_vendor_to_string(int vendor)
186 case PCIC_VENDOR_I82365SLR0:
187 return ("Intel 82365SL Revision 0");
188 case PCIC_VENDOR_I82365SLR1:
189 return ("Intel 82365SL Revision 1");
190 case PCIC_VENDOR_CIRRUS_PD6710:
191 return ("Cirrus PD6710");
192 case PCIC_VENDOR_CIRRUS_PD672X:
193 return ("Cirrus PD672X");
196 return ("Unknown controller");
200 pcic_activate(device_t dev)
202 struct pcic_softc *sc = (struct pcic_softc *)
203 device_get_softc(dev);
207 sc->port_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->port_rid,
208 0, ~0, PCIC_IOSIZE, RF_ACTIVE);
211 device_printf(dev, "Cannot allocate ioport\n");
217 sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irq_rid,
218 0, ~0, 1, RF_ACTIVE);
221 device_printf(dev, "Cannot allocate irq\n");
223 pcic_deactivate(dev);
226 sc->irq = rman_get_start(sc->irq_res);
227 if ((err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET, pcic_intr,
228 sc, &sc->intrhand)) != 0) {
229 pcic_deactivate(dev);
233 /* XXX This might not be needed in future, get it directly from
236 sc->mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->mem_rid,
237 0, ~0, 1 << 13, RF_ACTIVE);
240 device_printf(dev, "Cannot allocate mem\n");
242 pcic_deactivate(dev);
246 sc->iot = rman_get_bustag(sc->port_res);
247 sc->ioh = rman_get_bushandle(sc->port_res);;
248 sc->memt = rman_get_bustag(sc->mem_res);
249 sc->memh = rman_get_bushandle(sc->mem_res);;
255 pcic_deactivate(device_t dev)
257 struct pcic_softc *sc = device_get_softc(dev);
260 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
263 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid,
267 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
271 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
278 pcic_attach(device_t dev)
280 struct pcic_softc *sc = (struct pcic_softc *)
281 device_get_softc(dev);
282 struct pcic_handle *h;
283 int vendor, count, i, reg, error;
287 /* Activate our resources */
288 if ((error = pcic_activate(dev)) != 0)
291 /* now check for each controller/socket */
294 * this could be done with a loop, but it would violate the
295 * abstraction... so? --imp
300 DPRINTF(("pcic ident regs:"));
302 sc->handle[0].sc = sc;
303 sc->handle[0].sock = C0SA;
304 /* initialise pcic_read and pcic_write functions */
305 sc->handle[0].ph_read = st_pcic_read;
306 sc->handle[0].ph_write = st_pcic_write;
307 sc->handle[0].ph_bus_t = sc->iot;
308 sc->handle[0].ph_bus_h = sc->ioh;
309 if (pcic_ident_ok(reg = pcic_read(&sc->handle[0], PCIC_IDENT))) {
310 sc->handle[0].flags = PCIC_FLAG_SOCKETP;
313 sc->handle[0].flags = 0;
315 sc->handle[0].laststate = PCIC_LASTSTATE_EMPTY;
317 DPRINTF((" 0x%02x", reg));
319 sc->handle[1].sc = sc;
320 sc->handle[1].sock = C0SB;
321 /* initialise pcic_read and pcic_write functions */
322 sc->handle[1].ph_read = st_pcic_read;
323 sc->handle[1].ph_write = st_pcic_write;
324 sc->handle[1].ph_bus_t = sc->iot;
325 sc->handle[1].ph_bus_h = sc->ioh;
326 if (pcic_ident_ok(reg = pcic_read(&sc->handle[1], PCIC_IDENT))) {
327 sc->handle[1].flags = PCIC_FLAG_SOCKETP;
330 sc->handle[1].flags = 0;
332 sc->handle[1].laststate = PCIC_LASTSTATE_EMPTY;
334 DPRINTF((" 0x%02x", reg));
337 * The CL-PD6729 has only one controller and always returns 0
338 * if you try to read from the second one. Maybe pcic_ident_ok
339 * shouldn't accept 0?
341 sc->handle[2].sc = sc;
342 sc->handle[2].sock = C1SA;
343 /* initialise pcic_read and pcic_write functions */
344 sc->handle[2].ph_read = st_pcic_read;
345 sc->handle[2].ph_write = st_pcic_write;
346 sc->handle[2].ph_bus_t = sc->iot;
347 sc->handle[2].ph_bus_h = sc->ioh;
348 if (pcic_vendor(&sc->handle[0]) != PCIC_VENDOR_CIRRUS_PD672X ||
349 pcic_read(&sc->handle[2], PCIC_IDENT) != 0) {
350 if (pcic_ident_ok(reg = pcic_read(&sc->handle[2],
352 sc->handle[2].flags = PCIC_FLAG_SOCKETP;
355 sc->handle[2].flags = 0;
357 sc->handle[2].laststate = PCIC_LASTSTATE_EMPTY;
359 DPRINTF((" 0x%02x", reg));
361 sc->handle[3].sc = sc;
362 sc->handle[3].sock = C1SB;
363 /* initialise pcic_read and pcic_write functions */
364 sc->handle[3].ph_read = st_pcic_read;
365 sc->handle[3].ph_write = st_pcic_write;
366 sc->handle[3].ph_bus_t = sc->iot;
367 sc->handle[3].ph_bus_h = sc->ioh;
368 if (pcic_ident_ok(reg = pcic_read(&sc->handle[3],
370 sc->handle[3].flags = PCIC_FLAG_SOCKETP;
373 sc->handle[3].flags = 0;
375 sc->handle[3].laststate = PCIC_LASTSTATE_EMPTY;
377 DPRINTF((" 0x%02x\n", reg));
379 sc->handle[2].flags = 0;
380 sc->handle[3].flags = 0;
384 panic("pcic_attach: attach found no sockets");
386 /* establish the interrupt */
388 /* XXX block interrupts? */
390 for (i = 0; i < PCIC_NSLOTS; i++) {
392 * this should work, but w/o it, setting tty flags hangs at
395 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP)
397 STAILQ_INIT(&sc->handle[i].events);
398 pcic_write(&sc->handle[i], PCIC_CSC_INTR, 0);
399 pcic_read(&sc->handle[i], PCIC_CSC);
403 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) ||
404 (sc->handle[1].flags & PCIC_FLAG_SOCKETP)) {
405 vendor = pcic_vendor(&sc->handle[0]);
407 device_printf(dev, "controller 0 (%s) has ",
408 pcic_vendor_to_string(vendor));
410 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) &&
411 (sc->handle[1].flags & PCIC_FLAG_SOCKETP))
412 printf("sockets A and B\n");
413 else if (sc->handle[0].flags & PCIC_FLAG_SOCKETP)
414 printf("socket A only\n");
416 printf("socket B only\n");
418 if (sc->handle[0].flags & PCIC_FLAG_SOCKETP)
419 sc->handle[0].vendor = vendor;
420 if (sc->handle[1].flags & PCIC_FLAG_SOCKETP)
421 sc->handle[1].vendor = vendor;
423 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) ||
424 (sc->handle[3].flags & PCIC_FLAG_SOCKETP)) {
425 vendor = pcic_vendor(&sc->handle[2]);
427 device_printf(dev, "controller 1 (%s) has ",
428 pcic_vendor_to_string(vendor));
430 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) &&
431 (sc->handle[3].flags & PCIC_FLAG_SOCKETP))
432 printf("sockets A and B\n");
433 else if (sc->handle[2].flags & PCIC_FLAG_SOCKETP)
434 printf("socket A only\n");
436 printf("socket B only\n");
438 if (sc->handle[2].flags & PCIC_FLAG_SOCKETP)
439 sc->handle[2].vendor = vendor;
440 if (sc->handle[3].flags & PCIC_FLAG_SOCKETP)
441 sc->handle[3].vendor = vendor;
444 for (i = 0; i < PCIC_NSLOTS; i++) {
445 if ((sc->handle[i].flags & PCIC_FLAG_SOCKETP) == 0)
448 /* initialize the rest of the handle */
454 h->dev = device_add_child(dev, "pccard", -1);
455 device_set_ivars(h->dev, h);
460 * Probe and attach any children as were configured above.
462 error = bus_generic_attach(dev);
464 pcic_deactivate(dev);
469 pcic_create_event_thread(void *arg)
471 struct pcic_handle *h = arg;
488 panic("pcic_create_event_thread: unknown pcic socket");
491 if (kthread_create(pcic_event_thread, h, &h->event_thread,
492 "%s,%s", device_get_name(h->sc->dev), cs)) {
493 device_printf(h->sc->dev,
494 "cannot create event thread for sock 0x%02x\n", h->sock);
495 panic("pcic_create_event_thread");
500 pcic_event_thread(void *arg)
502 struct pcic_handle *h = arg;
503 struct pcic_event *pe;
505 struct pcic_softc *sc = h->sc;
507 while (h->shutdown == 0) {
509 if ((pe = STAILQ_FIRST(&h->events)) == NULL) {
511 (void) tsleep(&h->events, 0, "pcicev", 0);
515 /* sleep .25s to be enqueued chatterling interrupts */
516 (void) tsleep((caddr_t)pcic_event_thread, 0, "pcicss", hz/4);
519 STAILQ_REMOVE_HEAD_UNTIL(&h->events, pe, pe_q);
522 switch (pe->pe_type) {
523 case PCIC_EVENT_INSERTION:
526 struct pcic_event *pe1, *pe2;
528 if ((pe1 = STAILQ_FIRST(&h->events)) == NULL)
530 if (pe1->pe_type != PCIC_EVENT_REMOVAL)
532 if ((pe2 = STAILQ_NEXT(pe1, pe_q)) == NULL)
534 if (pe2->pe_type == PCIC_EVENT_INSERTION) {
535 STAILQ_REMOVE_HEAD_UNTIL(&h->events, pe1, pe_q);
537 STAILQ_REMOVE_HEAD_UNTIL(&h->events, pe2, pe_q);
543 DEVPRINTF((h->dev, "insertion event\n"));
547 case PCIC_EVENT_REMOVAL:
550 struct pcic_event *pe1, *pe2;
552 if ((pe1 = STAILQ_FIRST(&h->events)) == NULL)
554 if (pe1->pe_type != PCIC_EVENT_INSERTION)
556 if ((pe2 = STAILQ_NEXT(pe1, pe_q)) == NULL)
558 if (pe2->pe_type == PCIC_EVENT_REMOVAL) {
559 STAILQ_REMOVE_HEAD_UNTIL(&h->events, pe1, pe_q);
561 STAILQ_REMOVE_HEAD_UNTIL(&h->events, pe2, pe_q);
567 DEVPRINTF((h->dev, "removal event\n"));
568 pcic_detach_card(h, DETACH_FORCE);
572 panic("pcic_event_thread: unknown event %d",
578 h->event_thread = NULL;
580 /* In case parent is waiting for us to exit. */
587 pcic_init_socket(struct pcic_handle *h)
590 struct pcic_softc *sc = h->sc;
593 * queue creation of a kernel thread to handle insert/removal events.
597 /* set up the card to interrupt on card detect */
599 pcic_write(h, PCIC_CSC_INTR, (sc->irq << PCIC_CSC_INTR_IRQ_SHIFT) |
600 PCIC_CSC_INTR_CD_ENABLE);
601 pcic_write(h, PCIC_INTR, 0);
602 pcic_read(h, PCIC_CSC);
604 /* unsleep the cirrus controller */
606 if ((h->vendor == PCIC_VENDOR_CIRRUS_PD6710) ||
607 (h->vendor == PCIC_VENDOR_CIRRUS_PD672X)) {
608 reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2);
609 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) {
610 DEVPRINTF((sc->dev, "socket %02x was suspended\n",
612 reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND;
613 pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg);
616 h->laststate = PCIC_LASTSTATE_EMPTY;
620 /* Should do this later */
621 /* maybe as part of interrupt routing verification */
622 if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) ==
623 PCIC_IF_STATUS_CARDDETECT_PRESENT) {
625 h->laststate = PCIC_LASTSTATE_PRESENT;
627 h->laststate = PCIC_LASTSTATE_EMPTY;
635 struct pcic_softc *sc = arg;
638 DEVPRINTF((sc->dev, "intr\n"));
640 for (i = 0; i < PCIC_NSLOTS; i++)
641 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP)
642 pcic_intr_socket(&sc->handle[i]);
646 pcic_intr_socket(struct pcic_handle *h)
650 cscreg = pcic_read(h, PCIC_CSC);
652 cscreg &= (PCIC_CSC_GPI | PCIC_CSC_CD | PCIC_CSC_READY |
653 PCIC_CSC_BATTWARN | PCIC_CSC_BATTDEAD);
655 if (cscreg & PCIC_CSC_GPI) {
656 DEVPRINTF((h->dev, "%02x GPI\n", h->sock));
658 if (cscreg & PCIC_CSC_CD) {
661 statreg = pcic_read(h, PCIC_IF_STATUS);
663 DEVPRINTF((h->dev, "%02x CD %x\n", h->sock, statreg));
665 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) ==
666 PCIC_IF_STATUS_CARDDETECT_PRESENT) {
667 if (h->laststate != PCIC_LASTSTATE_PRESENT) {
669 "enqueing INSERTION event\n"));
670 pcic_queue_event(h, PCIC_EVENT_INSERTION);
672 h->laststate = PCIC_LASTSTATE_PRESENT;
674 if (h->laststate == PCIC_LASTSTATE_PRESENT) {
675 /* Deactivate the card now. */
676 DEVPRINTF((h->dev, "detaching card\n"));
677 pcic_detach_card(h, DETACH_FORCE);
680 "enqueing REMOVAL event\n"));
681 pcic_queue_event(h, PCIC_EVENT_REMOVAL);
683 h->laststate = ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 0)
684 ? PCIC_LASTSTATE_EMPTY : PCIC_LASTSTATE_HALF;
687 if (cscreg & PCIC_CSC_READY) {
688 DEVPRINTF((h->dev, "%02x READY\n", h->sock));
689 /* shouldn't happen */
691 if (cscreg & PCIC_CSC_BATTWARN) {
692 DEVPRINTF((h->dev, "%02x BATTWARN\n", h->sock));
694 if (cscreg & PCIC_CSC_BATTDEAD) {
695 DEVPRINTF((h->dev, "%02x BATTDEAD\n", h->sock));
700 pcic_queue_event(struct pcic_handle *h, int event)
702 struct pcic_event *pe;
705 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT);
707 panic("pcic_queue_event: can't allocate event");
711 STAILQ_INSERT_TAIL(&h->events, pe, pe_q);
717 pcic_attach_card(struct pcic_handle *h)
719 DPRINTF(("pcic_attach_card h %p h->dev %p %s %s\n", h, h->dev,
720 device_get_name(h->dev), device_get_name(device_get_parent(h->dev))));
721 if (!(h->flags & PCIC_FLAG_CARDP)) {
722 /* call the MI attach function */
723 CARD_ATTACH_CARD(h->dev);
725 h->flags |= PCIC_FLAG_CARDP;
727 DPRINTF(("pcic_attach_card: already attached"));
732 pcic_detach_card(struct pcic_handle *h, int flags)
735 if (h->flags & PCIC_FLAG_CARDP) {
736 h->flags &= ~PCIC_FLAG_CARDP;
738 /* call the MI detach function */
739 CARD_DETACH_CARD(h->dev, flags);
741 DPRINTF(("pcic_detach_card: already detached"));
746 pcic_chip_mem_alloc(struct pcic_handle *h, struct resource *r, bus_size_t size,
747 struct pccard_mem_handle *pcmhp)
749 bus_space_handle_t memh;
753 struct pcic_softc *sc = h->sc;
755 /* out of sc->memh, allocate as many pages as necessary */
757 /* convert size to PCIC pages */
758 sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN;
759 if (sizepg > PCIC_MAX_MEM_PAGES)
762 mask = (1 << sizepg) - 1;
764 addr = rman_get_start(r);
766 pcmhp->memt = sc->memt;
770 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE;
775 pcic_chip_mem_free(struct pcic_handle *h, struct pccard_mem_handle *pcmhp)
779 static struct mem_map_index_st {
780 int sysmem_start_lsb;
781 int sysmem_start_msb;
787 } mem_map_index[] = {
789 PCIC_SYSMEM_ADDR0_START_LSB,
790 PCIC_SYSMEM_ADDR0_START_MSB,
791 PCIC_SYSMEM_ADDR0_STOP_LSB,
792 PCIC_SYSMEM_ADDR0_STOP_MSB,
793 PCIC_CARDMEM_ADDR0_LSB,
794 PCIC_CARDMEM_ADDR0_MSB,
795 PCIC_ADDRWIN_ENABLE_MEM0,
798 PCIC_SYSMEM_ADDR1_START_LSB,
799 PCIC_SYSMEM_ADDR1_START_MSB,
800 PCIC_SYSMEM_ADDR1_STOP_LSB,
801 PCIC_SYSMEM_ADDR1_STOP_MSB,
802 PCIC_CARDMEM_ADDR1_LSB,
803 PCIC_CARDMEM_ADDR1_MSB,
804 PCIC_ADDRWIN_ENABLE_MEM1,
807 PCIC_SYSMEM_ADDR2_START_LSB,
808 PCIC_SYSMEM_ADDR2_START_MSB,
809 PCIC_SYSMEM_ADDR2_STOP_LSB,
810 PCIC_SYSMEM_ADDR2_STOP_MSB,
811 PCIC_CARDMEM_ADDR2_LSB,
812 PCIC_CARDMEM_ADDR2_MSB,
813 PCIC_ADDRWIN_ENABLE_MEM2,
816 PCIC_SYSMEM_ADDR3_START_LSB,
817 PCIC_SYSMEM_ADDR3_START_MSB,
818 PCIC_SYSMEM_ADDR3_STOP_LSB,
819 PCIC_SYSMEM_ADDR3_STOP_MSB,
820 PCIC_CARDMEM_ADDR3_LSB,
821 PCIC_CARDMEM_ADDR3_MSB,
822 PCIC_ADDRWIN_ENABLE_MEM3,
825 PCIC_SYSMEM_ADDR4_START_LSB,
826 PCIC_SYSMEM_ADDR4_START_MSB,
827 PCIC_SYSMEM_ADDR4_STOP_LSB,
828 PCIC_SYSMEM_ADDR4_STOP_MSB,
829 PCIC_CARDMEM_ADDR4_LSB,
830 PCIC_CARDMEM_ADDR4_MSB,
831 PCIC_ADDRWIN_ENABLE_MEM4,
836 pcic_chip_do_mem_map(struct pcic_handle *h, int win)
840 pcic_write(h, mem_map_index[win].sysmem_start_lsb,
841 (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff);
842 pcic_write(h, mem_map_index[win].sysmem_start_msb,
843 ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) &
844 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK));
847 /* XXX do I want 16 bit all the time? */
848 PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT;
851 pcic_write(h, mem_map_index[win].sysmem_stop_lsb,
852 ((h->mem[win].addr + h->mem[win].size) >>
853 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff);
854 pcic_write(h, mem_map_index[win].sysmem_stop_msb,
855 (((h->mem[win].addr + h->mem[win].size) >>
856 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) &
857 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) |
858 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2);
860 pcic_write(h, mem_map_index[win].cardmem_lsb,
861 (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff);
862 pcic_write(h, mem_map_index[win].cardmem_msb,
863 ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) &
864 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) |
865 ((h->mem[win].kind == PCCARD_MEM_ATTR) ?
866 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0));
868 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
869 reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16);
870 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
876 int r1, r2, r3, r4, r5, r6;
878 r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb);
879 r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb);
880 r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb);
881 r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb);
882 r5 = pcic_read(h, mem_map_index[win].cardmem_msb);
883 r6 = pcic_read(h, mem_map_index[win].cardmem_lsb);
885 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x "
886 "%02x%02x\n", win, r1, r2, r3, r4, r5, r6));
892 pcic_chip_mem_map(struct pcic_handle *h, int kind, bus_addr_t card_addr,
893 bus_size_t size, struct pccard_mem_handle *pcmhp, bus_addr_t *offsetp,
901 for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0]));
903 if ((h->memalloc & (1 << i)) == 0) {
905 h->memalloc |= (1 << i);
914 busaddr = pcmhp->addr;
917 * compute the address offset to the pccard address space for the
918 * pcic. this is intentionally signed. The masks and shifts below
919 * will cause TRT to happen in the pcic registers. Deal with making
920 * sure the address is aligned, and return the alignment offset.
923 *offsetp = card_addr % PCIC_MEM_ALIGN;
924 card_addr -= *offsetp;
926 DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr "
927 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size,
928 (u_long) card_addr));
931 * include the offset in the size, and decrement size by one, since
932 * the hw wants start/stop
934 size += *offsetp - 1;
936 card_offset = (((long) card_addr) - ((long) busaddr));
938 h->mem[win].addr = busaddr;
939 h->mem[win].size = size;
940 h->mem[win].offset = card_offset;
941 h->mem[win].kind = kind;
943 pcic_chip_do_mem_map(h, win);
949 pcic_chip_mem_unmap(struct pcic_handle *h, int window)
953 if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0])))
954 panic("pcic_chip_mem_unmap: window out of range");
956 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
957 reg &= ~mem_map_index[window].memenable;
958 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
960 h->memalloc &= ~(1 << window);
964 pcic_chip_io_alloc(struct pcic_handle *h, bus_addr_t start, bus_size_t size,
965 bus_size_t align, struct pccard_io_handle *pcihp)
968 bus_space_handle_t ioh;
971 struct pcic_softc *sc = h->sc;
974 * Allocate some arbitrary I/O space.
982 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n",
983 (u_long) ioaddr, (u_long) size));
985 flags |= PCCARD_IO_ALLOCATED;
987 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n",
988 (u_long) ioaddr, (u_long) size));
993 pcihp->addr = ioaddr;
995 pcihp->flags = flags;
1001 pcic_chip_io_free(struct pcic_handle *h, struct pccard_io_handle *pcihp)
1006 static struct io_map_index_st {
1013 int ioctlbits[3]; /* indexed by PCCARD_WIDTH_* */
1014 } io_map_index[] = {
1016 PCIC_IOADDR0_START_LSB,
1017 PCIC_IOADDR0_START_MSB,
1018 PCIC_IOADDR0_STOP_LSB,
1019 PCIC_IOADDR0_STOP_MSB,
1020 PCIC_ADDRWIN_ENABLE_IO0,
1021 PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT |
1022 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK,
1024 PCIC_IOCTL_IO0_IOCS16SRC_CARD,
1025 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE |
1026 PCIC_IOCTL_IO0_DATASIZE_8BIT,
1027 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE |
1028 PCIC_IOCTL_IO0_DATASIZE_16BIT,
1032 PCIC_IOADDR1_START_LSB,
1033 PCIC_IOADDR1_START_MSB,
1034 PCIC_IOADDR1_STOP_LSB,
1035 PCIC_IOADDR1_STOP_MSB,
1036 PCIC_ADDRWIN_ENABLE_IO1,
1037 PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT |
1038 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK,
1040 PCIC_IOCTL_IO1_IOCS16SRC_CARD,
1041 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE |
1042 PCIC_IOCTL_IO1_DATASIZE_8BIT,
1043 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE |
1044 PCIC_IOCTL_IO1_DATASIZE_16BIT,
1050 pcic_chip_do_io_map(struct pcic_handle *h, int win)
1054 DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n",
1055 win, (long) h->io[win].addr, (long) h->io[win].size,
1056 h->io[win].width * 8));
1058 pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff);
1059 pcic_write(h, io_map_index[win].start_msb,
1060 (h->io[win].addr >> 8) & 0xff);
1062 pcic_write(h, io_map_index[win].stop_lsb,
1063 (h->io[win].addr + h->io[win].size - 1) & 0xff);
1064 pcic_write(h, io_map_index[win].stop_msb,
1065 ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff);
1067 reg = pcic_read(h, PCIC_IOCTL);
1068 reg &= ~io_map_index[win].ioctlmask;
1069 reg |= io_map_index[win].ioctlbits[h->io[win].width];
1070 pcic_write(h, PCIC_IOCTL, reg);
1072 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
1073 reg |= io_map_index[win].ioenable;
1074 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
1078 pcic_chip_io_map(struct pcic_handle *h, int width, bus_addr_t offset,
1079 bus_size_t size, struct pccard_io_handle *pcihp, int *windowp)
1081 bus_addr_t ioaddr = pcihp->addr + offset;
1084 static char *width_names[] = { "auto", "io8", "io16" };
1087 struct pcic_softc *sc = h->sc;
1090 /* XXX Sanity check offset/size. */
1093 for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) {
1094 if ((h->ioalloc & (1 << i)) == 0) {
1096 h->ioalloc |= (1 << i);
1107 /* XXX this is pretty gross */
1108 if (sc->iot != pcihp->iot)
1109 panic("pcic_chip_io_map iot is bogus");
1112 DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n",
1113 win, width_names[width], (u_long) ioaddr, (u_long) size));
1115 /* XXX wtf is this doing here? */
1117 printf(" port 0x%lx", (u_long) ioaddr);
1119 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1);
1121 h->io[win].addr = ioaddr;
1122 h->io[win].size = size;
1123 h->io[win].width = width;
1125 pcic_chip_do_io_map(h, win);
1131 pcic_chip_io_unmap(struct pcic_handle *h, int window)
1135 if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0])))
1136 panic("pcic_chip_io_unmap: window out of range");
1138 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
1139 reg &= ~io_map_index[window].ioenable;
1140 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
1142 h->ioalloc &= ~(1 << window);
1146 pcic_wait_ready(struct pcic_handle *h)
1150 for (i = 0; i < 10000; i++) {
1151 if (pcic_read(h, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY)
1156 if ((i>5000) && (i%100 == 99))
1163 printf("pcic_wait_ready: ready never happened, status = %02x\n",
1164 pcic_read(h, PCIC_IF_STATUS));
1169 pcic_enable_socket(device_t dev, device_t child)
1171 struct pcic_handle *h = pcic_get_handle(dev, child);
1172 int cardtype, reg, win;
1174 /* this bit is mostly stolen from pcic_attach_card */
1176 /* power down the socket to reset it, clear the card reset pin */
1178 pcic_write(h, PCIC_PWRCTL, 0);
1181 * wait 300ms until power fails (Tpf). Then, wait 100ms since
1182 * we are changing Vcc (Toff).
1184 DELAY((300 + 100) * 1000);
1186 #ifdef VADEM_POWER_HACK
1187 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x0e);
1188 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x37);
1189 printf("prcr = %02x\n", pcic_read(h, 0x02));
1190 printf("cvsr = %02x\n", pcic_read(h, 0x2f));
1191 printf("DANGER WILL ROBINSON! Changing voltage select!\n");
1192 pcic_write(h, 0x2f, pcic_read(h, 0x2f) & ~0x03);
1193 printf("cvsr = %02x\n", pcic_read(h, 0x2f));
1196 /* power up the socket */
1198 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV
1199 | PCIC_PWRCTL_PWR_ENABLE);
1202 * wait 100ms until power raise (Tpr) and 20ms to become
1203 * stable (Tsu(Vcc)).
1205 * some machines require some more time to be settled
1206 * (300ms is added here).
1208 DELAY((100 + 20 + 300) * 1000);
1210 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV | PCIC_PWRCTL_OE
1211 | PCIC_PWRCTL_PWR_ENABLE);
1212 pcic_write(h, PCIC_INTR, 0);
1215 * hold RESET at least 10us.
1219 /* clear the reset flag */
1221 pcic_write(h, PCIC_INTR, PCIC_INTR_RESET);
1223 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */
1227 /* wait for the chip to finish initializing */
1230 reg = pcic_read(h, PCIC_IF_STATUS);
1231 if (!(reg & PCIC_IF_STATUS_POWERACTIVE)) {
1232 printf("pcic_chip_socket_enable: status %x", reg);
1238 /* zero out the address windows */
1239 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0);
1241 /* set the card type */
1242 CARD_GET_TYPE(h->dev, &cardtype);
1244 reg = pcic_read(h, PCIC_INTR);
1245 reg &= ~(PCIC_INTR_CARDTYPE_MASK | PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE);
1246 reg |= ((cardtype == PCCARD_IFTYPE_IO) ?
1247 PCIC_INTR_CARDTYPE_IO :
1248 PCIC_INTR_CARDTYPE_MEM);
1250 pcic_write(h, PCIC_INTR, reg);
1252 DEVPRINTF((h->dev, "pcic_chip_socket_enable cardtype %s %02x\n",
1253 ((cardtype == PCCARD_IFTYPE_IO) ? "io" : "mem"), reg));
1255 /* reinstall all the memory and io mappings */
1257 for (win = 0; win < PCIC_MEM_WINS; win++)
1258 if (h->memalloc & (1 << win))
1259 pcic_chip_do_mem_map(h, win);
1261 for (win = 0; win < PCIC_IO_WINS; win++)
1262 if (h->ioalloc & (1 << win))
1263 pcic_chip_do_io_map(h, win);
1269 pcic_disable_socket(device_t dev, device_t child)
1271 struct pcic_handle *h = pcic_get_handle(dev, child);
1272 DPRINTF(("pcic_chip_socket_disable\n"));
1274 /* power down the socket */
1276 pcic_write(h, PCIC_PWRCTL, 0);
1279 * wait 300ms until power fails (Tpf).
1287 st_pcic_read(struct pcic_handle *h, int idx)
1290 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX,
1293 return bus_space_read_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA);
1297 st_pcic_write(struct pcic_handle *h, int idx, u_int8_t data)
1300 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX,
1304 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA, data);
1308 pcic_activate_resource(device_t dev, device_t child, int type, int rid,
1315 struct pcic_handle *h = pcic_get_handle(dev, child);
1317 sz = rman_get_end(r) - rman_get_start(r) + 1;
1319 case SYS_RES_IOPORT:
1321 err = pcic_chip_io_map(h, 0, 0, sz, &h->io[rid], &win);
1323 pcic_chip_io_free(h, &h->io[rid]);
1327 case SYS_RES_MEMORY:
1328 err = pcic_chip_mem_map(h, 0, 0, sz, &h->mem[rid], &off, &win);
1330 pcic_chip_mem_free(h, &h->mem[rid]);
1337 err = bus_generic_activate_resource(device_get_parent(dev), child,
1343 pcic_deactivate_resource(device_t dev, device_t child, int type, int rid,
1346 struct pcic_handle *h = pcic_get_handle(dev, child);
1350 case SYS_RES_IOPORT:
1351 pcic_chip_io_unmap(h, rid);
1353 case SYS_RES_MEMORY:
1354 pcic_chip_mem_unmap(h, rid);
1358 err = bus_generic_deactivate_resource(device_get_parent(dev), child,
1364 pcic_setup_intr(device_t dev, device_t child, struct resource *irqres,
1365 int flags, driver_intr_t intr, void *arg, void **cookiep)
1367 struct pcic_handle *h = pcic_get_handle(dev, child);
1372 err = bus_generic_setup_intr(device_get_parent(dev), child, irqres,
1373 flags, intr, arg, cookiep);
1377 irq = rman_get_start(irqres);
1378 reg = pcic_read(h, PCIC_INTR);
1379 reg &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE);
1381 pcic_write(h, PCIC_INTR, reg);
1385 device_printf(dev, "card irq %d\n", irq);
1391 pcic_teardown_intr(device_t dev, device_t child, struct resource *irq,
1395 struct pcic_handle *h = pcic_get_handle(dev, child);
1399 reg = pcic_read(h, PCIC_INTR);
1400 reg &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE);
1401 pcic_write(h, PCIC_INTR, reg);
1403 return (bus_generic_teardown_intr(device_get_parent(dev), child, irq,
1408 pcic_alloc_resource(device_t dev, device_t child, int type, int *rid,
1409 u_long start, u_long end, u_long count, u_int flags)
1414 struct pcic_handle *h = pcic_get_handle(dev, child);
1416 /* Nearly default */
1417 if (type == SYS_RES_MEMORY && start == 0 && end == ~0 && count != 1) {
1418 start = 0xd0000; /* XXX */
1422 r = bus_generic_alloc_resource(dev, child, type, rid, start, end,
1426 sz = rman_get_end(r) - rman_get_start(r) + 1;
1428 case SYS_RES_IOPORT:
1429 err = pcic_chip_io_alloc(h, rman_get_start(r), sz, 0,
1432 bus_generic_release_resource(dev, child, type, *rid,
1437 case SYS_RES_MEMORY:
1438 err = pcic_chip_mem_alloc(h, r, sz, &h->mem[*rid]);
1440 bus_generic_release_resource(dev, child, type, *rid,
1452 pcic_release_resource(device_t dev, device_t child, int type, int rid,
1455 struct pcic_handle *h = pcic_get_handle(dev, child);
1458 case SYS_RES_IOPORT:
1459 pcic_chip_io_free(h, &h->io[rid]);
1461 case SYS_RES_MEMORY:
1462 pcic_chip_mem_free(h, &h->mem[rid]);
1466 return bus_generic_release_resource(dev, child, type, rid, r);
1470 pcic_suspend(device_t dev)
1473 * Do nothing for now, maybe in time do what FreeBSD's current
1474 * pccard code does and detach my children. That's the safest thing
1475 * to do since we don't want to wake up and have different hardware
1483 pcic_resume(device_t dev)
1485 /* Need to port pcic_power from newer netbsd versions of this file */
1491 pcic_set_res_flags(device_t dev, device_t child, int type, int rid,
1494 struct pcic_handle *h = pcic_get_handle(dev, child);
1496 DPRINTF(("%p %p %d %d %#x\n", dev, child, type, rid, flags));
1497 if (type != SYS_RES_MEMORY)
1499 h->mem[rid].kind = PCCARD_MEM_ATTR;
1500 pcic_chip_do_mem_map(h, rid);
1506 pcic_set_memory_offset(device_t dev, device_t child, int rid, u_int32_t offset)
1512 pcic_start_threads(void *arg)
1514 struct pcic_handle **walker;
1517 pcic_create_event_thread(*walker++);
1521 SYSINIT(pcic, SI_SUB_KTHREAD_IDLE, SI_ORDER_ANY, pcic_start_threads, 0);