7ba41879682ec6563746f99842213b3ecf050865
[dragonfly.git] / sys / dev / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2  */
3 /*-
4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5  * All Rights Reserved.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a
8  * copy of this software and associated documentation files (the
9  * "Software"), to deal in the Software without restriction, including
10  * without limitation the rights to use, copy, modify, merge, publish,
11  * distribute, sub license, and/or sell copies of the Software, and to
12  * permit persons to whom the Software is furnished to do so, subject to
13  * the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the
16  * next paragraph) shall be included in all copies or substantial portions
17  * of the Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26  *
27  */
28
29 #include "dev/drm/drmP.h"
30 #include "dev/drm/drm.h"
31 #include "dev/drm/i915_drm.h"
32 #include "i915_drv.h"
33
34 #define MAX_NOPID ((u32)~0)
35
36 /**
37  * Interrupts that are always left unmasked.
38  *
39  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
40  * we leave them always unmasked in IMR and then control enabling them through
41  * PIPESTAT alone.
42  */
43 #define I915_INTERRUPT_ENABLE_FIX       (I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
44                                          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
45
46 /** Interrupts that we mask and unmask at runtime. */
47 #define I915_INTERRUPT_ENABLE_VAR       (I915_USER_INTERRUPT)
48
49 /** These are all of the interrupts used by the driver */
50 #define I915_INTERRUPT_ENABLE_MASK      (I915_INTERRUPT_ENABLE_FIX | \
51                                          I915_INTERRUPT_ENABLE_VAR)
52
53 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
54                                          DRM_I915_VBLANK_PIPE_B)
55
56 static inline void
57 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
58 {
59         mask &= I915_INTERRUPT_ENABLE_VAR;
60         if ((dev_priv->irq_mask_reg & mask) != 0) {
61                 dev_priv->irq_mask_reg &= ~mask;
62                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
63                 (void) I915_READ(IMR);
64         }
65 }
66
67 static inline void
68 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
69 {
70         mask &= I915_INTERRUPT_ENABLE_VAR;
71         if ((dev_priv->irq_mask_reg & mask) != mask) {
72                 dev_priv->irq_mask_reg |= mask;
73                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
74                 (void) I915_READ(IMR);
75         }
76 }
77
78 static inline u32
79 i915_pipestat(int pipe)
80 {
81         if (pipe == 0)
82             return PIPEASTAT;
83         if (pipe == 1)
84             return PIPEBSTAT;
85         return -EINVAL;
86 }
87
88 void
89 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
90 {
91         if ((dev_priv->pipestat[pipe] & mask) != mask) {
92                 u32 reg = i915_pipestat(pipe);
93
94                 dev_priv->pipestat[pipe] |= mask;
95                 /* Enable the interrupt, clear any pending status */
96                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
97                 (void) I915_READ(reg);
98         }
99 }
100
101 void
102 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
103 {
104         if ((dev_priv->pipestat[pipe] & mask) != 0) {
105                 u32 reg = i915_pipestat(pipe);
106
107                 dev_priv->pipestat[pipe] &= ~mask;
108                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
109                 (void) I915_READ(reg);
110         }
111 }
112
113 /**
114  * i915_pipe_enabled - check if a pipe is enabled
115  * @dev: DRM device
116  * @pipe: pipe to check
117  *
118  * Reading certain registers when the pipe is disabled can hang the chip.
119  * Use this routine to make sure the PLL is running and the pipe is active
120  * before reading such registers if unsure.
121  */
122 static int
123 i915_pipe_enabled(struct drm_device *dev, int pipe)
124 {
125         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
126         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
127
128         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
129                 return 1;
130
131         return 0;
132 }
133
134 /* Called from drm generic code, passed a 'crtc', which
135  * we use as a pipe index
136  */
137 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
138 {
139         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
140         unsigned long high_frame;
141         unsigned long low_frame;
142         u32 high1, high2, low, count;
143
144         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
145         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
146
147         if (!i915_pipe_enabled(dev, pipe)) {
148                 DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe);
149                 return 0;
150         }
151
152         /*
153          * High & low register fields aren't synchronized, so make sure
154          * we get a low value that's stable across two reads of the high
155          * register.
156          */
157         do {
158                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
159                          PIPE_FRAME_HIGH_SHIFT);
160                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
161                         PIPE_FRAME_LOW_SHIFT);
162                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
163                          PIPE_FRAME_HIGH_SHIFT);
164         } while (high1 != high2);
165
166         count = (high1 << 8) | low;
167
168         return count;
169 }
170
171 u32 g45_get_vblank_counter(struct drm_device *dev, int pipe)
172 {
173         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
174         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
175
176         if (!i915_pipe_enabled(dev, pipe)) {
177                 DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe);
178                 return 0;
179         }
180
181         return I915_READ(reg);
182 }
183
184 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
185 {
186         struct drm_device *dev = (struct drm_device *) arg;
187         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
188         u32 iir, new_iir;
189         u32 pipea_stats, pipeb_stats;
190         u32 vblank_status;
191         u32 vblank_enable;
192         int irq_received;
193
194         iir = I915_READ(IIR);
195
196         if (IS_I965G(dev)) {
197                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
198                 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
199         } else {
200                 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
201                 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
202         }
203
204         for (;;) {
205                 irq_received = iir != 0;
206
207                 /* Can't rely on pipestat interrupt bit in iir as it might
208                  * have been cleared after the pipestat interrupt was received.
209                  * It doesn't set the bit in iir again, but it still produces
210                  * interrupts (for non-MSI).
211                  */
212                 DRM_SPINLOCK(&dev_priv->user_irq_lock);
213                 pipea_stats = I915_READ(PIPEASTAT);
214                 pipeb_stats = I915_READ(PIPEBSTAT);
215
216                 /*
217                  * Clear the PIPE(A|B)STAT regs before the IIR
218                  */
219                 if (pipea_stats & 0x8000ffff) {
220                         I915_WRITE(PIPEASTAT, pipea_stats);
221                         irq_received = 1;
222                 }
223
224                 if (pipeb_stats & 0x8000ffff) {
225                         I915_WRITE(PIPEBSTAT, pipeb_stats);
226                         irq_received = 1;
227                 }
228                 DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
229
230                 if (!irq_received)
231                         break;
232
233                 I915_WRITE(IIR, iir);
234                 new_iir = I915_READ(IIR); /* Flush posted writes */
235
236                 if (dev_priv->sarea_priv)
237                         dev_priv->sarea_priv->last_dispatch =
238                             READ_BREADCRUMB(dev_priv);
239
240                 if (iir & I915_USER_INTERRUPT) {
241                         DRM_WAKEUP(&dev_priv->irq_queue);
242                 }
243
244                 if (pipea_stats & vblank_status)
245                         drm_handle_vblank(dev, 0);
246
247                 if (pipeb_stats & vblank_status)
248                         drm_handle_vblank(dev, 1);
249
250                 /* With MSI, interrupts are only generated when iir
251                  * transitions from zero to nonzero.  If another bit got
252                  * set while we were handling the existing iir bits, then
253                  * we would never get another interrupt.
254                  *
255                  * This is fine on non-MSI as well, as if we hit this path
256                  * we avoid exiting the interrupt handler only to generate
257                  * another one.
258                  *
259                  * Note that for MSI this could cause a stray interrupt report
260                  * if an interrupt landed in the time between writing IIR and
261                  * the posting read.  This should be rare enough to never
262                  * trigger the 99% of 100,000 interrupts test for disabling
263                  * stray interrupts.
264                  */
265                 iir = new_iir;
266         }
267 }
268
269 static int i915_emit_irq(struct drm_device * dev)
270 {
271         drm_i915_private_t *dev_priv = dev->dev_private;
272         RING_LOCALS;
273
274         i915_kernel_lost_context(dev);
275
276         if (++dev_priv->counter > 0x7FFFFFFFUL)
277                 dev_priv->counter = 0;
278         if (dev_priv->sarea_priv)
279                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
280
281         DRM_DEBUG("emitting: %d\n", dev_priv->counter);
282
283         BEGIN_LP_RING(4);
284         OUT_RING(MI_STORE_DWORD_INDEX);
285         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
286         OUT_RING(dev_priv->counter);
287         OUT_RING(MI_USER_INTERRUPT);
288         ADVANCE_LP_RING();
289
290         return dev_priv->counter;
291 }
292
293 void i915_user_irq_get(struct drm_device *dev)
294 {
295         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
296
297         if (dev->irq_enabled == 0)
298                 return;
299
300         DRM_DEBUG("\n");
301         DRM_SPINLOCK(&dev_priv->user_irq_lock);
302         if (++dev_priv->user_irq_refcount == 1)
303                 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
304         DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
305 }
306
307 void i915_user_irq_put(struct drm_device *dev)
308 {
309         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
310
311         if (dev->irq_enabled == 0)
312                 return;
313
314         DRM_SPINLOCK(&dev_priv->user_irq_lock);
315         KASSERT(dev_priv->user_irq_refcount > 0, ("invalid refcount"));
316         if (--dev_priv->user_irq_refcount == 0)
317                 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
318         DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
319 }
320
321 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
322 {
323         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
324         int ret = 0;
325
326         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
327                 if (dev_priv->sarea_priv) {
328                         dev_priv->sarea_priv->last_dispatch =
329                                 READ_BREADCRUMB(dev_priv);
330                 }
331                 return 0;
332         }
333
334         if (dev_priv->sarea_priv)
335                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
336
337         DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
338                   READ_BREADCRUMB(dev_priv));
339
340         i915_user_irq_get(dev);
341         DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
342                     READ_BREADCRUMB(dev_priv) >= irq_nr);
343         i915_user_irq_put(dev);
344
345         if (ret == -ERESTART)
346                 DRM_DEBUG("restarting syscall\n");
347
348         if (ret == -EBUSY) {
349                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
350                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
351         }
352
353         return ret;
354 }
355
356 /* Needs the lock as it touches the ring.
357  */
358 int i915_irq_emit(struct drm_device *dev, void *data,
359                          struct drm_file *file_priv)
360 {
361         drm_i915_private_t *dev_priv = dev->dev_private;
362         drm_i915_irq_emit_t *emit = data;
363         int result;
364
365         if (!dev_priv) {
366                 DRM_ERROR("called with no initialization\n");
367                 return -EINVAL;
368         }
369
370         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
371
372         result = i915_emit_irq(dev);
373
374         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
375                 DRM_ERROR("copy_to_user\n");
376                 return -EFAULT;
377         }
378
379         return 0;
380 }
381
382 /* Doesn't need the hardware lock.
383  */
384 int i915_irq_wait(struct drm_device *dev, void *data,
385                          struct drm_file *file_priv)
386 {
387         drm_i915_private_t *dev_priv = dev->dev_private;
388         drm_i915_irq_wait_t *irqwait = data;
389
390         if (!dev_priv) {
391                 DRM_ERROR("called with no initialization\n");
392                 return -EINVAL;
393         }
394
395         return i915_wait_irq(dev, irqwait->irq_seq);
396 }
397
398 /* Called from drm generic code, passed 'crtc' which
399  * we use as a pipe index
400  */
401 int i915_enable_vblank(struct drm_device *dev, int pipe)
402 {
403         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
404
405         if (!i915_pipe_enabled(dev, pipe))
406                 return -EINVAL;
407
408         DRM_SPINLOCK(&dev_priv->user_irq_lock);
409         if (IS_I965G(dev))
410                 i915_enable_pipestat(dev_priv, pipe,
411                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
412         else
413                 i915_enable_pipestat(dev_priv, pipe,
414                                      PIPE_VBLANK_INTERRUPT_ENABLE);
415         DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
416         return 0;
417 }
418
419 /* Called from drm generic code, passed 'crtc' which
420  * we use as a pipe index
421  */
422 void i915_disable_vblank(struct drm_device *dev, int pipe)
423 {
424         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
425
426         DRM_SPINLOCK(&dev_priv->user_irq_lock);
427         i915_disable_pipestat(dev_priv, pipe,
428                               PIPE_VBLANK_INTERRUPT_ENABLE |
429                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
430         DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
431 }
432
433 /* Set the vblank monitor pipe
434  */
435 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
436                          struct drm_file *file_priv)
437 {
438         drm_i915_private_t *dev_priv = dev->dev_private;
439
440         if (!dev_priv) {
441                 DRM_ERROR("called with no initialization\n");
442                 return -EINVAL;
443         }
444
445         return 0;
446 }
447
448 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
449                          struct drm_file *file_priv)
450 {
451         drm_i915_private_t *dev_priv = dev->dev_private;
452         drm_i915_vblank_pipe_t *pipe = data;
453
454         if (!dev_priv) {
455                 DRM_ERROR("called with no initialization\n");
456                 return -EINVAL;
457         }
458
459         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
460
461         return 0;
462 }
463
464 /**
465  * Schedule buffer swap at given vertical blank.
466  */
467 int i915_vblank_swap(struct drm_device *dev, void *data,
468                      struct drm_file *file_priv)
469 {
470         /* The delayed swap mechanism was fundamentally racy, and has been
471          * removed.  The model was that the client requested a delayed flip/swap
472          * from the kernel, then waited for vblank before continuing to perform
473          * rendering.  The problem was that the kernel might wake the client
474          * up before it dispatched the vblank swap (since the lock has to be
475          * held while touching the ringbuffer), in which case the client would
476          * clear and start the next frame before the swap occurred, and
477          * flicker would occur in addition to likely missing the vblank.
478          *
479          * In the absence of this ioctl, userland falls back to a correct path
480          * of waiting for a vblank, then dispatching the swap on its own.
481          * Context switching to userland and back is plenty fast enough for
482          * meeting the requirements of vblank swapping.
483          */
484         return -EINVAL;
485 }
486
487 /* drm_dma.h hooks
488 */
489 void i915_driver_irq_preinstall(struct drm_device * dev)
490 {
491         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
492
493         I915_WRITE(HWSTAM, 0xeffe);
494         I915_WRITE(PIPEASTAT, 0);
495         I915_WRITE(PIPEBSTAT, 0);
496         I915_WRITE(IMR, 0xffffffff);
497         I915_WRITE(IER, 0x0);
498         (void) I915_READ(IER);
499 }
500
501 int i915_driver_irq_postinstall(struct drm_device *dev)
502 {
503         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
504
505         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
506
507         /* Unmask the interrupts that we always want on. */
508         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
509
510         /* Disable pipe interrupt enables, clear pending pipe status */
511         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
512         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
513
514         /* Clear pending interrupt status */
515         I915_WRITE(IIR, I915_READ(IIR));
516
517         I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK);
518         I915_WRITE(IMR, dev_priv->irq_mask_reg);
519         I915_WRITE(PIPEASTAT, dev_priv->pipestat[0] |
520             (dev_priv->pipestat[0] >> 16));
521         I915_WRITE(PIPEBSTAT, dev_priv->pipestat[1] |
522             (dev_priv->pipestat[1] >> 16));
523         (void) I915_READ(IER);
524
525         return 0;
526 }
527
528 void i915_driver_irq_uninstall(struct drm_device * dev)
529 {
530         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
531
532         if (!dev_priv)
533                 return;
534
535         dev_priv->vblank_pipe = 0;
536
537         I915_WRITE(HWSTAM, 0xffffffff);
538         I915_WRITE(PIPEASTAT, 0);
539         I915_WRITE(PIPEBSTAT, 0);
540         I915_WRITE(IMR, 0xffffffff);
541         I915_WRITE(IER, 0x0);
542
543         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
544         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
545         I915_WRITE(IIR, I915_READ(IIR));
546 }