2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/kernel.h>
32 #include <sys/machintr.h>
33 #include <machine/globaldata.h>
34 #include <machine/smp.h>
35 #include <machine/md_var.h>
36 #include <machine/pmap.h>
37 #include <machine_base/apic/mpapic.h>
38 #include <machine_base/apic/ioapic_abi.h>
39 #include <machine/segments.h>
40 #include <sys/thread2.h>
42 #include <machine/intr_machdep.h>
46 /* EISA Edge/Level trigger control registers */
47 #define ELCR0 0x4d0 /* eisa irq 0-7 */
48 #define ELCR1 0x4d1 /* eisa irq 8-15 */
57 TAILQ_ENTRY(ioapic_info) io_link;
59 TAILQ_HEAD(ioapic_info_list, ioapic_info);
62 struct ioapic_info_list ioc_list;
63 int ioc_intsrc[16]; /* XXX magic number */
66 volatile lapic_t *lapic;
68 static void lapic_timer_calibrate(void);
69 static void lapic_timer_set_divisor(int);
70 static void lapic_timer_fixup_handler(void *);
71 static void lapic_timer_restart_handler(void *);
73 void lapic_timer_process(void);
74 void lapic_timer_process_frame(struct intrframe *);
75 void lapic_timer_always(struct intrframe *);
77 static int lapic_timer_enable = 1;
78 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
80 static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
81 static void lapic_timer_intr_enable(struct cputimer_intr *);
82 static void lapic_timer_intr_restart(struct cputimer_intr *);
83 static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
85 static void ioapic_setup(const struct ioapic_info *);
86 static void ioapic_set_apic_id(const struct ioapic_info *);
87 static void ioapic_gsi_setup(int);
88 static const struct ioapic_info *
89 ioapic_gsi_search(int);
90 static void ioapic_pin_prog(void *, int, int,
91 enum intr_trigger, enum intr_polarity, uint32_t);
93 static struct cputimer_intr lapic_cputimer_intr = {
95 .reload = lapic_timer_intr_reload,
96 .enable = lapic_timer_intr_enable,
97 .config = cputimer_intr_default_config,
98 .restart = lapic_timer_intr_restart,
99 .pmfixup = lapic_timer_intr_pmfixup,
100 .initclock = cputimer_intr_default_initclock,
101 .next = SLIST_ENTRY_INITIALIZER,
103 .type = CPUTIMER_INTR_LAPIC,
104 .prio = CPUTIMER_INTR_PRIO_LAPIC,
105 .caps = CPUTIMER_INTR_CAP_NONE
109 * pointers to pmapped apic hardware.
112 volatile ioapic_t **ioapic;
114 static int lapic_timer_divisor_idx = -1;
115 static const uint32_t lapic_timer_divisors[] = {
116 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
117 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
119 #define APIC_TIMER_NDIVISORS (int)(NELEM(lapic_timer_divisors))
122 static struct ioapic_conf ioapic_conf;
132 * Enable LAPIC, configure interrupts.
135 lapic_init(boolean_t bsp)
143 * Since IDT is shared between BSP and APs, these vectors
144 * only need to be installed once; we do it on BSP.
147 /* Install a 'Spurious INTerrupt' vector */
148 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
149 SDT_SYSIGT, SEL_KPL, 0);
151 /* Install an inter-CPU IPI for TLB invalidation */
152 setidt(XINVLTLB_OFFSET, Xinvltlb,
153 SDT_SYSIGT, SEL_KPL, 0);
155 /* Install an inter-CPU IPI for IPIQ messaging */
156 setidt(XIPIQ_OFFSET, Xipiq,
157 SDT_SYSIGT, SEL_KPL, 0);
159 /* Install a timer vector */
160 setidt(XTIMER_OFFSET, Xtimer,
161 SDT_SYSIGT, SEL_KPL, 0);
163 /* Install an inter-CPU IPI for CPU stop/restart */
164 setidt(XCPUSTOP_OFFSET, Xcpustop,
165 SDT_SYSIGT, SEL_KPL, 0);
169 * Setup LINT0 as ExtINT on the BSP. This is theoretically an
170 * aggregate interrupt input from the 8259. The INTA cycle
171 * will be routed to the external controller (the 8259) which
172 * is expected to supply the vector.
174 * Must be setup edge triggered, active high.
176 * Disable LINT0 on BSP, if I/O APIC is enabled.
178 * Disable LINT0 on the APs. It doesn't matter what delivery
179 * mode we use because we leave it masked.
181 temp = lapic->lvt_lint0;
182 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
183 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
185 temp |= APIC_LVT_DM_EXTINT;
187 temp |= APIC_LVT_MASKED;
189 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
191 lapic->lvt_lint0 = temp;
194 * Setup LINT1 as NMI.
196 * Must be setup edge trigger, active high.
198 * Enable LINT1 on BSP, if I/O APIC is enabled.
200 * Disable LINT1 on the APs.
202 temp = lapic->lvt_lint1;
203 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
204 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
205 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
206 if (bsp && apic_io_enable)
207 temp &= ~APIC_LVT_MASKED;
208 lapic->lvt_lint1 = temp;
211 * Mask the LAPIC error interrupt, LAPIC performance counter
214 lapic->lvt_error = lapic->lvt_error | APIC_LVT_MASKED;
215 lapic->lvt_pcint = lapic->lvt_pcint | APIC_LVT_MASKED;
218 * Set LAPIC timer vector and mask the LAPIC timer interrupt.
220 timer = lapic->lvt_timer;
221 timer &= ~APIC_LVTT_VECTOR;
222 timer |= XTIMER_OFFSET;
223 timer |= APIC_LVTT_MASKED;
224 lapic->lvt_timer = timer;
227 * Set the Task Priority Register as needed. At the moment allow
228 * interrupts on all cpus (the APs will remain CLId until they are
229 * ready to deal). We could disable all but IPIs by setting
230 * temp |= TPR_IPI for cpu != 0.
233 temp &= ~APIC_TPR_PRIO; /* clear priority field */
234 #ifdef SMP /* APIC-IO */
235 if (!apic_io_enable) {
238 * If we are NOT running the IO APICs, the LAPIC will only be used
239 * for IPIs. Set the TPR to prevent any unintentional interrupts.
242 #ifdef SMP /* APIC-IO */
251 temp |= APIC_SVR_ENABLE; /* enable the LAPIC */
252 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
255 * Set the spurious interrupt vector. The low 4 bits of the vector
258 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
259 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
260 temp &= ~APIC_SVR_VECTOR;
261 temp |= XSPURIOUSINT_OFFSET;
266 * Pump out a few EOIs to clean out interrupts that got through
267 * before we were able to set the TPR.
274 lapic_timer_calibrate();
275 if (lapic_timer_enable) {
276 cputimer_intr_register(&lapic_cputimer_intr);
277 cputimer_intr_select(&lapic_cputimer_intr, 0);
280 lapic_timer_set_divisor(lapic_timer_divisor_idx);
284 apic_dump("apic_initialize()");
288 lapic_timer_set_divisor(int divisor_idx)
290 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
291 lapic->dcr_timer = lapic_timer_divisors[divisor_idx];
295 lapic_timer_oneshot(u_int count)
299 value = lapic->lvt_timer;
300 value &= ~APIC_LVTT_PERIODIC;
301 lapic->lvt_timer = value;
302 lapic->icr_timer = count;
306 lapic_timer_oneshot_quick(u_int count)
308 lapic->icr_timer = count;
312 lapic_timer_calibrate(void)
316 /* Try to calibrate the local APIC timer. */
317 for (lapic_timer_divisor_idx = 0;
318 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
319 lapic_timer_divisor_idx++) {
320 lapic_timer_set_divisor(lapic_timer_divisor_idx);
321 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
323 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
324 if (value != APIC_TIMER_MAX_COUNT)
327 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
328 panic("lapic: no proper timer divisor?!\n");
329 lapic_cputimer_intr.freq = value / 2;
331 kprintf("lapic: divisor index %d, frequency %u Hz\n",
332 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
336 lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
340 gd->gd_timer_running = 0;
342 count = sys_cputimer->count();
343 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
344 systimer_intr(&count, 0, frame);
348 lapic_timer_process(void)
350 lapic_timer_process_oncpu(mycpu, NULL);
354 lapic_timer_process_frame(struct intrframe *frame)
356 lapic_timer_process_oncpu(mycpu, frame);
360 * This manual debugging code is called unconditionally from Xtimer
361 * (the lapic timer interrupt) whether the current thread is in a
362 * critical section or not) and can be useful in tracking down lockups.
364 * NOTE: MANUAL DEBUG CODE
367 static int saveticks[SMP_MAXCPU];
368 static int savecounts[SMP_MAXCPU];
372 lapic_timer_always(struct intrframe *frame)
375 globaldata_t gd = mycpu;
376 int cpu = gd->gd_cpuid;
382 gptr = (short *)0xFFFFFFFF800b8000 + 80 * cpu;
383 *gptr = ((*gptr + 1) & 0x00FF) | 0x0700;
386 ksnprintf(buf, sizeof(buf), " %p %16s %d %16s ",
387 (void *)frame->if_rip, gd->gd_curthread->td_comm, ticks,
389 for (i = 0; buf[i]; ++i) {
390 gptr[i] = 0x0700 | (unsigned char)buf[i];
394 if (saveticks[gd->gd_cpuid] != ticks) {
395 saveticks[gd->gd_cpuid] = ticks;
396 savecounts[gd->gd_cpuid] = 0;
398 ++savecounts[gd->gd_cpuid];
399 if (savecounts[gd->gd_cpuid] > 2000 && panicstr == NULL) {
400 panic("cpud %d panicing on ticks failure",
403 for (i = 0; i < ncpus; ++i) {
405 if (saveticks[i] && panicstr == NULL) {
406 delta = saveticks[i] - ticks;
407 if (delta < -10 || delta > 10) {
408 panic("cpu %d panicing on cpu %d watchdog",
418 lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
420 struct globaldata *gd = mycpu;
422 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
426 if (gd->gd_timer_running) {
427 if (reload < lapic->ccr_timer)
428 lapic_timer_oneshot_quick(reload);
430 gd->gd_timer_running = 1;
431 lapic_timer_oneshot_quick(reload);
436 lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
440 timer = lapic->lvt_timer;
441 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
442 lapic->lvt_timer = timer;
444 lapic_timer_fixup_handler(NULL);
448 lapic_timer_fixup_handler(void *arg)
455 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
457 * Detect the presence of C1E capability mostly on latest
458 * dual-cores (or future) k8 family. This feature renders
459 * the local APIC timer dead, so we disable it by reading
460 * the Interrupt Pending Message register and clearing both
461 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
464 * "BIOS and Kernel Developer's Guide for AMD NPT
465 * Family 0Fh Processors"
466 * #32559 revision 3.00
468 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
469 (cpu_id & 0x0fff0000) >= 0x00040000) {
472 msr = rdmsr(0xc0010055);
473 if (msr & 0x18000000) {
474 struct globaldata *gd = mycpu;
476 kprintf("cpu%d: AMD C1E detected\n",
478 wrmsr(0xc0010055, msr & ~0x18000000ULL);
481 * We are kinda stalled;
484 gd->gd_timer_running = 1;
485 lapic_timer_oneshot_quick(2);
495 lapic_timer_restart_handler(void *dummy __unused)
499 lapic_timer_fixup_handler(&started);
501 struct globaldata *gd = mycpu;
503 gd->gd_timer_running = 1;
504 lapic_timer_oneshot_quick(2);
509 * This function is called only by ACPI-CA code currently:
510 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
511 * module controls PM. So once ACPI-CA is attached, we try
512 * to apply the fixup to prevent LAPIC timer from hanging.
515 lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
517 lwkt_send_ipiq_mask(smp_active_mask,
518 lapic_timer_fixup_handler, NULL);
522 lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
524 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
529 * dump contents of local APIC registers
534 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
535 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
536 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
540 #ifdef SMP /* APIC-IO */
546 #define IOAPIC_ISA_INTS 16
547 #define REDIRCNT_IOAPIC(A) \
548 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
550 static int trigger (int apic, int pin, u_int32_t * flags);
551 static void polarity (int apic, int pin, u_int32_t * flags, int level);
553 #define DEFAULT_FLAGS \
559 #define DEFAULT_ISA_FLAGS \
568 io_apic_set_id(int apic, int id)
572 ux = ioapic_read(ioapic[apic], IOAPIC_ID); /* get current contents */
573 if (((ux & APIC_ID_MASK) >> 24) != id) {
574 kprintf("Changing APIC ID for IO APIC #%d"
575 " from %d to %d on chip\n",
576 apic, ((ux & APIC_ID_MASK) >> 24), id);
577 ux &= ~APIC_ID_MASK; /* clear the ID field */
579 ioapic_write(ioapic[apic], IOAPIC_ID, ux); /* write new value */
580 ux = ioapic_read(ioapic[apic], IOAPIC_ID); /* re-read && test */
581 if (((ux & APIC_ID_MASK) >> 24) != id)
582 panic("can't control IO APIC #%d ID, reg: 0x%08x",
589 io_apic_get_id(int apic)
591 return (ioapic_read(ioapic[apic], IOAPIC_ID) & APIC_ID_MASK) >> 24;
600 io_apic_setup_intpin(int apic, int pin)
602 int bus, bustype, irq;
603 u_char select; /* the select register is 8 bits */
604 u_int32_t flags; /* the window register is 32 bits */
605 u_int32_t target; /* the window register is 32 bits */
606 u_int32_t vector; /* the window register is 32 bits */
611 select = pin * 2 + IOAPIC_REDTBL0; /* register */
614 * Always clear an IO APIC pin before [re]programming it. This is
615 * particularly important if the pin is set up for a level interrupt
616 * as the IOART_REM_IRR bit might be set. When we reprogram the
617 * vector any EOI from pending ints on this pin could be lost and
618 * IRR might never get reset.
620 * To fix this problem, clear the vector and make sure it is
621 * programmed as an edge interrupt. This should theoretically
622 * clear IRR so we can later, safely program it as a level
627 flags = ioapic_read(ioapic[apic], select) & IOART_RESV;
628 flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
629 flags |= IOART_DESTPHY | IOART_DELFIXED;
631 target = ioapic_read(ioapic[apic], select + 1) & IOART_HI_DEST_RESV;
632 target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
636 ioapic_write(ioapic[apic], select, flags | vector);
637 ioapic_write(ioapic[apic], select + 1, target);
642 * We only deal with vectored interrupts here. ? documentation is
643 * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
646 * This test also catches unconfigured pins.
648 if (apic_int_type(apic, pin) != 0)
652 * Leave the pin unprogrammed if it does not correspond to
655 irq = apic_irq(apic, pin);
659 /* determine the bus type for this pin */
660 bus = apic_src_bus_id(apic, pin);
663 bustype = apic_bus_type(bus);
665 if ((bustype == ISA) &&
666 (pin < IOAPIC_ISA_INTS) &&
668 (apic_polarity(apic, pin) == 0x1) &&
669 (apic_trigger(apic, pin) == 0x3)) {
671 * A broken BIOS might describe some ISA
672 * interrupts as active-high level-triggered.
673 * Use default ISA flags for those interrupts.
675 flags = DEFAULT_ISA_FLAGS;
678 * Program polarity and trigger mode according to
681 flags = DEFAULT_FLAGS;
682 level = trigger(apic, pin, &flags);
684 int_to_apicintpin[irq].flags |= IOAPIC_IM_FLAG_LEVEL;
685 polarity(apic, pin, &flags, level);
689 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", irq);
690 kgetenv_int(envpath, &cpuid);
692 /* ncpus may not be available yet */
697 kprintf("IOAPIC #%d intpin %d -> irq %d (CPU%d)\n",
698 apic, pin, irq, cpuid);
702 * Program the appropriate registers. This routing may be
703 * overridden when an interrupt handler for a device is
704 * actually added (see register_int(), which calls through
705 * the MACHINTR ABI to set up an interrupt handler/vector).
707 * The order in which we must program the two registers for
708 * safety is unclear! XXX
712 vector = IDT_OFFSET + irq; /* IDT vec */
713 target = ioapic_read(ioapic[apic], select + 1) & IOART_HI_DEST_RESV;
714 /* Deliver all interrupts to CPU0 (BSP) */
715 target |= (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
717 flags |= ioapic_read(ioapic[apic], select) & IOART_RESV;
718 ioapic_write(ioapic[apic], select, flags | vector);
719 ioapic_write(ioapic[apic], select + 1, target);
725 io_apic_setup(int apic)
730 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
731 kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
733 for (pin = 0; pin < maxpin; ++pin) {
734 io_apic_setup_intpin(apic, pin);
737 if (apic_int_type(apic, pin) >= 0) {
738 kprintf("Warning: IOAPIC #%d pin %d does not exist,"
739 " cannot program!\n", apic, pin);
744 /* return GOOD status */
747 #undef DEFAULT_ISA_FLAGS
751 #define DEFAULT_EXTINT_FLAGS \
760 * XXX this function is only used by 8254 setup
761 * Setup the source of External INTerrupts.
764 ext_int_setup(int apic, int intr)
766 u_char select; /* the select register is 8 bits */
767 u_int32_t flags; /* the window register is 32 bits */
768 u_int32_t target; /* the window register is 32 bits */
769 u_int32_t vector; /* the window register is 32 bits */
773 if (apic_int_type(apic, intr) != 3)
777 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", intr);
778 kgetenv_int(envpath, &cpuid);
780 /* ncpus may not be available yet */
784 /* Deliver interrupts to CPU0 (BSP) */
785 target = (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
787 select = IOAPIC_REDTBL0 + (2 * intr);
788 vector = IDT_OFFSET + intr;
789 flags = DEFAULT_EXTINT_FLAGS;
791 ioapic_write(ioapic[apic], select, flags | vector);
792 ioapic_write(ioapic[apic], select + 1, target);
796 #undef DEFAULT_EXTINT_FLAGS
800 * Set the trigger level for an IO APIC pin.
803 trigger(int apic, int pin, u_int32_t * flags)
808 static int intcontrol = -1;
810 switch (apic_trigger(apic, pin)) {
816 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
820 *flags |= IOART_TRGRLVL;
828 if ((id = apic_src_bus_id(apic, pin)) == -1)
831 switch (apic_bus_type(id)) {
833 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
837 eirq = apic_src_bus_irq(apic, pin);
839 if (eirq < 0 || eirq > 15) {
840 kprintf("EISA IRQ %d?!?!\n", eirq);
844 if (intcontrol == -1) {
845 intcontrol = inb(ELCR1) << 8;
846 intcontrol |= inb(ELCR0);
847 kprintf("EISA INTCONTROL = %08x\n", intcontrol);
850 /* Use ELCR settings to determine level or edge mode */
851 level = (intcontrol >> eirq) & 1;
854 * Note that on older Neptune chipset based systems, any
855 * pci interrupts often show up here and in the ELCR as well
856 * as level sensitive interrupts attributed to the EISA bus.
860 *flags |= IOART_TRGRLVL;
862 *flags &= ~IOART_TRGRLVL;
867 *flags |= IOART_TRGRLVL;
876 panic("bad APIC IO INT flags");
881 * Set the polarity value for an IO APIC pin.
884 polarity(int apic, int pin, u_int32_t * flags, int level)
888 switch (apic_polarity(apic, pin)) {
894 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
898 *flags |= IOART_INTALO;
906 if ((id = apic_src_bus_id(apic, pin)) == -1)
909 switch (apic_bus_type(id)) {
911 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
915 /* polarity converter always gives active high */
916 *flags &= ~IOART_INTALO;
920 *flags |= IOART_INTALO;
929 panic("bad APIC IO INT flags");
934 * Print contents of unmasked IRQs.
941 kprintf("SMP: enabled INTs: ");
942 for (x = 0; x < APIC_INTMAPSIZE; ++x) {
943 if ((int_to_apicintpin[x].flags & IOAPIC_IM_FLAG_MASKED) == 0)
951 * Inter Processor Interrupt functions.
954 #endif /* SMP APIC-IO */
957 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
959 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
960 * vector is any valid SYSTEM INT vector
961 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
963 * A backlog of requests can create a deadlock between cpus. To avoid this
964 * we have to be able to accept IPIs at the same time we are trying to send
965 * them. The critical section prevents us from attempting to send additional
966 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
967 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
968 * to occur but fortunately it does not happen too often.
971 apic_ipi(int dest_type, int vector, int delivery_mode)
976 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
977 unsigned long rflags = read_rflags();
979 DEBUG_PUSH_INFO("apic_ipi");
980 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
984 write_rflags(rflags);
987 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
988 delivery_mode | vector;
989 lapic->icr_lo = icr_lo;
995 single_apic_ipi(int cpu, int vector, int delivery_mode)
1001 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
1002 unsigned long rflags = read_rflags();
1004 DEBUG_PUSH_INFO("single_apic_ipi");
1005 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
1006 lwkt_process_ipiq();
1009 write_rflags(rflags);
1011 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
1012 icr_hi |= (CPU_TO_ID(cpu) << 24);
1013 lapic->icr_hi = icr_hi;
1016 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK)
1017 | APIC_DEST_DESTFLD | delivery_mode | vector;
1019 /* write APIC ICR */
1020 lapic->icr_lo = icr_lo;
1027 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
1029 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
1030 * to the target, and the scheduler does not 'poll' for IPI messages.
1033 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
1039 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
1043 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
1044 icr_hi |= (CPU_TO_ID(cpu) << 24);
1045 lapic->icr_hi = icr_hi;
1048 icr_lo = (lapic->icr_lo & APIC_RESV2_MASK)
1049 | APIC_DEST_DESTFLD | delivery_mode | vector;
1051 /* write APIC ICR */
1052 lapic->icr_lo = icr_lo;
1060 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
1062 * target is a bitmask of destination cpus. Vector is any
1063 * valid system INT vector. Delivery mode may be either
1064 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
1067 selected_apic_ipi(cpumask_t target, int vector, int delivery_mode)
1071 int n = BSFCPUMASK(target);
1072 target &= ~CPUMASK(n);
1073 single_apic_ipi(n, vector, delivery_mode);
1079 * Timer code, in development...
1080 * - suggested by rgrimes@gndrsh.aac.dev.com
1083 get_apic_timer_frequency(void)
1085 return(lapic_cputimer_intr.freq);
1089 * Load a 'downcount time' in uSeconds.
1092 set_apic_timer(int us)
1097 * When we reach here, lapic timer's frequency
1098 * must have been calculated as well as the
1099 * divisor (lapic->dcr_timer is setup during the
1100 * divisor calculation).
1102 KKASSERT(lapic_cputimer_intr.freq != 0 &&
1103 lapic_timer_divisor_idx >= 0);
1105 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
1106 lapic_timer_oneshot(count);
1111 * Read remaining time in timer.
1114 read_apic_timer(void)
1117 /** XXX FIXME: we need to return the actual remaining time,
1118 * for now we just return the remaining count.
1121 return lapic->ccr_timer;
1127 * Spin-style delay, set delay time in uS, spin till it drains.
1132 set_apic_timer(count);
1133 while (read_apic_timer())
1138 lapic_map(vm_offset_t lapic_addr)
1140 lapic = pmap_mapdev_uncacheable(lapic_addr, sizeof(struct LAPIC));
1142 kprintf("lapic: at 0x%08lx\n", lapic_addr);
1145 static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
1146 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
1151 struct lapic_enumerator *e;
1154 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1155 error = e->lapic_probe(e);
1160 panic("can't config lapic\n");
1162 e->lapic_enumerate(e);
1166 lapic_enumerator_register(struct lapic_enumerator *ne)
1168 struct lapic_enumerator *e;
1170 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1171 if (e->lapic_prio < ne->lapic_prio) {
1172 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
1176 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);
1179 static TAILQ_HEAD(, ioapic_enumerator) ioapic_enumerators =
1180 TAILQ_HEAD_INITIALIZER(ioapic_enumerators);
1185 struct ioapic_enumerator *e;
1189 TAILQ_INIT(&ioapic_conf.ioc_list);
1190 /* XXX magic number */
1191 for (i = 0; i < 16; ++i)
1192 ioapic_conf.ioc_intsrc[i] = -1;
1194 TAILQ_FOREACH(e, &ioapic_enumerators, ioapic_link) {
1195 error = e->ioapic_probe(e);
1201 panic("can't config I/O APIC\n");
1203 kprintf("no I/O APIC\n");
1208 if (!ioapic_use_old) {
1215 * Switch to I/O APIC MachIntrABI and reconfigure
1216 * the default IDT entries.
1218 MachIntrABI = MachIntrABI_IOAPIC;
1219 MachIntrABI.setdefault();
1222 e->ioapic_enumerate(e);
1224 if (!ioapic_use_old) {
1225 struct ioapic_info *info;
1228 * Fixup the rest of the fields of ioapic_info
1231 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
1232 const struct ioapic_info *prev_info;
1235 info->io_apic_id = info->io_idx + lapic_id_max + 1;
1238 kprintf("IOAPIC: idx %d, apic id %d, "
1239 "gsi base %d, npin %d\n",
1246 /* Warning about possible GSI hole */
1247 prev_info = TAILQ_PREV(info, ioapic_info_list, io_link);
1248 if (prev_info != NULL) {
1249 if (info->io_gsi_base !=
1250 prev_info->io_gsi_base + prev_info->io_npin) {
1251 kprintf("IOAPIC: warning gsi hole "
1253 prev_info->io_gsi_base +
1255 info->io_gsi_base - 1);
1261 * Setup all I/O APIC
1263 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
1268 MachIntrABI.cleanup();
1272 panic("ioapic_config: new ioapic not working yet\n");
1277 ioapic_enumerator_register(struct ioapic_enumerator *ne)
1279 struct ioapic_enumerator *e;
1281 TAILQ_FOREACH(e, &ioapic_enumerators, ioapic_link) {
1282 if (e->ioapic_prio < ne->ioapic_prio) {
1283 TAILQ_INSERT_BEFORE(e, ne, ioapic_link);
1287 TAILQ_INSERT_TAIL(&ioapic_enumerators, ne, ioapic_link);
1291 ioapic_add(void *addr, int gsi_base, int npin)
1293 struct ioapic_info *info, *ninfo;
1296 gsi_end = gsi_base + npin - 1;
1297 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
1298 if ((gsi_base >= info->io_gsi_base &&
1299 gsi_base < info->io_gsi_base + info->io_npin) ||
1300 (gsi_end >= info->io_gsi_base &&
1301 gsi_end < info->io_gsi_base + info->io_npin)) {
1302 panic("ioapic_add: overlapped gsi, base %d npin %d, "
1303 "hit base %d, npin %d\n", gsi_base, npin,
1304 info->io_gsi_base, info->io_npin);
1306 if (info->io_addr == addr)
1307 panic("ioapic_add: duplicated addr %p\n", addr);
1310 ninfo = kmalloc(sizeof(*ninfo), M_DEVBUF, M_WAITOK | M_ZERO);
1311 ninfo->io_addr = addr;
1312 ninfo->io_npin = npin;
1313 ninfo->io_gsi_base = gsi_base;
1316 * Create IOAPIC list in ascending order of GSI base
1318 TAILQ_FOREACH_REVERSE(info, &ioapic_conf.ioc_list,
1319 ioapic_info_list, io_link) {
1320 if (ninfo->io_gsi_base > info->io_gsi_base) {
1321 TAILQ_INSERT_AFTER(&ioapic_conf.ioc_list,
1322 info, ninfo, io_link);
1327 TAILQ_INSERT_HEAD(&ioapic_conf.ioc_list, ninfo, io_link);
1331 ioapic_intsrc(int irq, int gsi)
1334 if (ioapic_conf.ioc_intsrc[irq] != -1 &&
1335 ioapic_conf.ioc_intsrc[irq] != gsi) {
1336 kprintf("IOAPIC: warning intsrc irq %d, gsi %d -> gsi %d\n",
1337 irq, ioapic_conf.ioc_intsrc[irq], gsi);
1339 ioapic_conf.ioc_intsrc[irq] = gsi;
1343 ioapic_set_apic_id(const struct ioapic_info *info)
1347 id = ioapic_read(info->io_addr, IOAPIC_ID);
1349 id &= ~APIC_ID_MASK;
1350 id |= (info->io_apic_id << 24);
1352 ioapic_write(info->io_addr, IOAPIC_ID, id);
1357 id = ioapic_read(info->io_addr, IOAPIC_ID);
1358 if (((id & APIC_ID_MASK) >> 24) != info->io_apic_id) {
1359 panic("ioapic_set_apic_id: can't set apic id to %d\n",
1365 ioapic_gsi_setup(int gsi)
1367 enum intr_trigger trig;
1368 enum intr_polarity pola;
1374 ioapic_extpin_setup(ioapic_gsi_ioaddr(gsi),
1375 ioapic_gsi_pin(gsi), 0);
1380 for (irq = 0; irq < 16; ++irq) {
1381 if (gsi == ioapic_conf.ioc_intsrc[irq]) {
1382 trig = INTR_TRIGGER_EDGE;
1383 pola = INTR_POLARITY_HIGH;
1390 trig = INTR_TRIGGER_EDGE;
1391 pola = INTR_POLARITY_HIGH;
1393 trig = INTR_TRIGGER_LEVEL;
1394 pola = INTR_POLARITY_LOW;
1399 ioapic_abi_set_irqmap(irq, gsi, trig, pola);
1403 ioapic_gsi_ioaddr(int gsi)
1405 const struct ioapic_info *info;
1407 info = ioapic_gsi_search(gsi);
1408 return info->io_addr;
1412 ioapic_gsi_pin(int gsi)
1414 const struct ioapic_info *info;
1416 info = ioapic_gsi_search(gsi);
1417 return gsi - info->io_gsi_base;
1420 static const struct ioapic_info *
1421 ioapic_gsi_search(int gsi)
1423 const struct ioapic_info *info;
1425 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
1426 if (gsi >= info->io_gsi_base &&
1427 gsi < info->io_gsi_base + info->io_npin)
1430 panic("ioapic_gsi_search: no I/O APIC\n");
1434 ioapic_extpin_setup(void *addr, int pin, int vec)
1436 ioapic_pin_prog(addr, pin, vec,
1437 INTR_TRIGGER_CONFORM, INTR_POLARITY_CONFORM, IOART_DELEXINT);
1441 ioapic_pin_setup(void *addr, int pin, int vec,
1442 enum intr_trigger trig, enum intr_polarity pola)
1445 * Always clear an I/O APIC pin before [re]programming it. This is
1446 * particularly important if the pin is set up for a level interrupt
1447 * as the IOART_REM_IRR bit might be set. When we reprogram the
1448 * vector any EOI from pending ints on this pin could be lost and
1449 * IRR might never get reset.
1451 * To fix this problem, clear the vector and make sure it is
1452 * programmed as an edge interrupt. This should theoretically
1453 * clear IRR so we can later, safely program it as a level
1456 ioapic_pin_prog(addr, pin, vec, INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH,
1458 ioapic_pin_prog(addr, pin, vec, trig, pola, IOART_DELFIXED);
1462 ioapic_pin_prog(void *addr, int pin, int vec,
1463 enum intr_trigger trig, enum intr_polarity pola, uint32_t del_mode)
1465 uint32_t flags, target;
1468 KKASSERT(del_mode == IOART_DELEXINT || del_mode == IOART_DELFIXED);
1470 select = IOAPIC_REDTBL0 + (2 * pin);
1472 flags = ioapic_read(addr, select) & IOART_RESV;
1473 flags |= IOART_INTMSET | IOART_DESTPHY | del_mode;
1475 if (del_mode == IOART_DELEXINT) {
1476 KKASSERT(trig == INTR_TRIGGER_CONFORM &&
1477 pola == INTR_POLARITY_CONFORM);
1478 flags |= IOART_TRGREDG | IOART_INTAHI;
1481 case INTR_TRIGGER_EDGE:
1482 flags |= IOART_TRGREDG;
1485 case INTR_TRIGGER_LEVEL:
1486 flags |= IOART_TRGRLVL;
1489 case INTR_TRIGGER_CONFORM:
1490 panic("ioapic_pin_prog: trig conform is not "
1494 case INTR_POLARITY_HIGH:
1495 flags |= IOART_INTAHI;
1498 case INTR_POLARITY_LOW:
1499 flags |= IOART_INTALO;
1502 case INTR_POLARITY_CONFORM:
1503 panic("ioapic_pin_prog: pola conform is not "
1508 target = ioapic_read(addr, select + 1) & IOART_HI_DEST_RESV;
1511 ioapic_write(addr, select, flags | vec);
1512 ioapic_write(addr, select + 1, target);
1516 ioapic_setup(const struct ioapic_info *info)
1520 ioapic_set_apic_id(info);
1522 for (i = 0; i < info->io_npin; ++i)
1523 ioapic_gsi_setup(info->io_gsi_base + i);