2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <sys/mplock2.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine/cputypes.h>
59 #include <machine_base/apic/mpapic.h>
60 #include <machine/psl.h>
61 #include <machine/segments.h>
62 #include <machine/tss.h>
63 #include <machine/specialreg.h>
64 #include <machine/globaldata.h>
65 #include <machine/pmap_inval.h>
67 #include <machine/md_var.h> /* setidt() */
68 #include <machine_base/icu/icu.h> /* IPIs */
69 #include <machine/intr_machdep.h> /* IPIs */
71 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
73 #define WARMBOOT_TARGET 0
74 #define WARMBOOT_OFF (KERNBASE + 0x0467)
75 #define WARMBOOT_SEG (KERNBASE + 0x0469)
77 #define BIOS_BASE (0xf0000)
78 #define BIOS_BASE2 (0xe0000)
79 #define BIOS_SIZE (0x10000)
80 #define BIOS_COUNT (BIOS_SIZE/4)
82 #define CMOS_REG (0x70)
83 #define CMOS_DATA (0x71)
84 #define BIOS_RESET (0x0f)
85 #define BIOS_WARM (0x0a)
87 #define PROCENTRY_FLAG_EN 0x01
88 #define PROCENTRY_FLAG_BP 0x02
89 #define IOAPICENTRY_FLAG_EN 0x01
92 /* MP Floating Pointer Structure */
93 typedef struct MPFPS {
106 /* MP Configuration Table Header */
107 typedef struct MPCTH {
109 u_short base_table_length;
113 u_char product_id[12];
114 void *oem_table_pointer;
115 u_short oem_table_size;
118 u_short extended_table_length;
119 u_char extended_table_checksum;
124 typedef struct PROCENTRY {
129 u_long cpu_signature;
130 u_long feature_flags;
135 typedef struct BUSENTRY {
141 typedef struct IOAPICENTRY {
147 } *io_apic_entry_ptr;
149 typedef struct INTENTRY {
159 /* descriptions of MP basetable entries */
160 typedef struct BASETABLE_ENTRY {
169 vm_size_t mp_cth_mapsz;
172 typedef int (*mptable_iter_func)(void *, const void *, int);
175 * this code MUST be enabled here and in mpboot.s.
176 * it follows the very early stages of AP boot by placing values in CMOS ram.
177 * it NORMALLY will never be needed and thus the primitive method for enabling.
180 #if defined(CHECK_POINTS)
181 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
182 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
184 #define CHECK_INIT(D); \
185 CHECK_WRITE(0x34, (D)); \
186 CHECK_WRITE(0x35, (D)); \
187 CHECK_WRITE(0x36, (D)); \
188 CHECK_WRITE(0x37, (D)); \
189 CHECK_WRITE(0x38, (D)); \
190 CHECK_WRITE(0x39, (D));
192 #define CHECK_PRINT(S); \
193 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
202 #else /* CHECK_POINTS */
204 #define CHECK_INIT(D)
205 #define CHECK_PRINT(S)
207 #endif /* CHECK_POINTS */
210 * Values to send to the POST hardware.
212 #define MP_BOOTADDRESS_POST 0x10
213 #define MP_PROBE_POST 0x11
214 #define MPTABLE_PASS1_POST 0x12
216 #define MP_START_POST 0x13
217 #define MP_ENABLE_POST 0x14
218 #define MPTABLE_PASS2_POST 0x15
220 #define START_ALL_APS_POST 0x16
221 #define INSTALL_AP_TRAMP_POST 0x17
222 #define START_AP_POST 0x18
224 #define MP_ANNOUNCE_POST 0x19
226 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
227 int current_postcode;
229 /** XXX FIXME: what system files declare these??? */
230 extern struct region_descriptor r_gdt, r_idt;
232 int mp_naps; /* # of Applications processors */
233 #ifdef SMP /* APIC-IO */
234 static int mp_nbusses; /* # of busses */
235 int mp_napics; /* # of IO APICs */
236 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
237 u_int32_t *io_apic_versions;
241 u_int32_t cpu_apic_versions[MAXCPU];
243 extern int64_t tsc_offsets[];
245 extern u_long ebda_addr;
247 #ifdef SMP /* APIC-IO */
248 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
252 * APIC ID logical/physical mapping structures.
253 * We oversize these to simplify boot-time config.
255 int cpu_num_to_apic_id[NAPICID];
256 #ifdef SMP /* APIC-IO */
257 int io_num_to_apic_id[NAPICID];
259 int apic_id_to_logical[NAPICID];
261 /* AP uses this during bootstrap. Do not staticize. */
265 /* Hotwire a 0->4MB V==P mapping */
266 extern pt_entry_t *KPTphys;
269 * SMP page table page. Setup by locore to point to a page table
270 * page from which we allocate per-cpu privatespace areas io_apics,
274 #define IO_MAPPING_START_INDEX \
275 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
277 extern pt_entry_t *SMPpt;
278 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
280 struct pcb stoppcbs[MAXCPU];
282 static basetable_entry basetable_entry_types[] =
284 {0, 20, "Processor"},
292 * Local data and functions.
295 static u_int boot_address;
296 static u_int base_memory;
297 static int mp_finish;
299 static void mp_enable(u_int boot_addr);
301 static int mptable_iterate_entries(const mpcth_t,
302 mptable_iter_func, void *);
303 static int mptable_probe(void);
304 static int mptable_search(void);
305 static int mptable_check(vm_paddr_t);
306 static int mptable_search_sig(u_int32_t target, int count);
307 static int mptable_hyperthread_fixup(cpumask_t, int);
308 #ifdef SMP /* APIC-IO */
309 static void mptable_pass1(struct mptable_pos *);
310 static void mptable_pass2(struct mptable_pos *);
311 static void mptable_default(int type);
312 static void mptable_fix(void);
314 static int mptable_map(struct mptable_pos *, vm_paddr_t);
315 static void mptable_unmap(struct mptable_pos *);
316 static void mptable_imcr(struct mptable_pos *);
318 static int mptable_lapic_probe(struct lapic_enumerator *);
319 static void mptable_lapic_enumerate(struct lapic_enumerator *);
320 static void mptable_lapic_default(void);
322 #ifdef SMP /* APIC-IO */
323 static void setup_apic_irq_mapping(void);
324 static int apic_int_is_bus_type(int intr, int bus_type);
326 static int start_all_aps(u_int boot_addr);
327 static void install_ap_tramp(u_int boot_addr);
328 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
329 static int smitest(void);
331 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
332 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
333 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
336 * Calculate usable address in base memory for AP trampoline code.
339 mp_bootaddress(u_int basemem)
341 POSTCODE(MP_BOOTADDRESS_POST);
343 base_memory = basemem;
345 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
346 if ((base_memory - boot_address) < bootMP_size)
347 boot_address -= 4096; /* not enough, lower by 4k */
358 mpfps_paddr = mptable_search();
359 if (mptable_check(mpfps_paddr))
366 * Look for an Intel MP spec table (ie, SMP capable hardware).
375 * Make sure our SMPpt[] page table is big enough to hold all the
378 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
380 POSTCODE(MP_PROBE_POST);
382 /* see if EBDA exists */
383 if (ebda_addr != 0) {
384 /* search first 1K of EBDA */
385 target = (u_int32_t)ebda_addr;
386 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
389 /* last 1K of base memory, effective 'top of base' passed in */
390 target = (u_int32_t)(base_memory - 0x400);
391 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
395 /* search the BIOS */
396 target = (u_int32_t)BIOS_BASE;
397 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
400 /* search the extended BIOS */
401 target = (u_int32_t)BIOS_BASE2;
402 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
409 struct mptable_check_cbarg {
415 mptable_check_callback(void *xarg, const void *pos, int type)
417 const struct PROCENTRY *ent;
418 struct mptable_check_cbarg *arg = xarg;
424 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
428 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
429 if (arg->found_bsp) {
430 kprintf("more than one BSP in base MP table\n");
439 mptable_check(vm_paddr_t mpfps_paddr)
441 struct mptable_pos mpt;
442 struct mptable_check_cbarg arg;
446 if (mpfps_paddr == 0)
449 error = mptable_map(&mpt, mpfps_paddr);
453 if (mpt.mp_fps->mpfb1 != 0)
461 if (cth->apic_address == 0)
464 bzero(&arg, sizeof(arg));
465 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
467 if (arg.cpu_count == 0) {
468 kprintf("MP table contains no processor entries\n");
470 } else if (!arg.found_bsp) {
471 kprintf("MP table does not contains BSP entry\n");
481 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
483 int count, total_size;
484 const void *position;
486 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
487 total_size = cth->base_table_length - sizeof(struct MPCTH);
488 position = (const uint8_t *)cth + sizeof(struct MPCTH);
489 count = cth->entry_count;
494 KKASSERT(total_size >= 0);
495 if (total_size == 0) {
496 kprintf("invalid base MP table, "
497 "entry count and length mismatch\n");
501 type = *(const uint8_t *)position;
503 case 0: /* processor_entry */
504 case 1: /* bus_entry */
505 case 2: /* io_apic_entry */
506 case 3: /* int_entry */
507 case 4: /* int_entry */
510 kprintf("unknown base MP table entry type %d\n", type);
514 if (total_size < basetable_entry_types[type].length) {
515 kprintf("invalid base MP table length, "
516 "does not contain all entries\n");
519 total_size -= basetable_entry_types[type].length;
521 error = func(arg, position, type);
525 position = (const uint8_t *)position +
526 basetable_entry_types[type].length;
533 * Startup the SMP processors.
538 POSTCODE(MP_START_POST);
539 mp_enable(boot_address);
544 * Print various information about the SMP system hardware and setup.
551 POSTCODE(MP_ANNOUNCE_POST);
553 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
554 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
555 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
556 for (x = 1; x <= mp_naps; ++x) {
557 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
558 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
561 if (apic_io_enable) {
562 for (x = 0; x < mp_napics; ++x) {
563 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
564 kprintf(", version: 0x%08x", io_apic_versions[x]);
565 kprintf(", at 0x%08lx\n", io_apic_address[x]);
568 kprintf(" Warning: APIC I/O disabled\n");
573 * AP cpu's call this to sync up protected mode.
575 * WARNING! We must ensure that the cpu is sufficiently initialized to
576 * be able to use to the FP for our optimized bzero/bcopy code before
577 * we enter more mainstream C code.
579 * WARNING! %fs is not set up on entry. This routine sets up %fs.
585 int x, myid = bootAP;
587 struct mdglobaldata *md;
588 struct privatespace *ps;
590 ps = &CPU_prvspace[myid];
592 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
593 gdt_segs[GPROC0_SEL].ssd_base =
594 (int) &ps->mdglobaldata.gd_common_tss;
595 ps->mdglobaldata.mi.gd_prvspace = ps;
597 for (x = 0; x < NGDT; x++) {
598 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
601 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
602 r_gdt.rd_base = (int) &gdt[myid * NGDT];
603 lgdt(&r_gdt); /* does magic intra-segment return */
608 mdcpu->gd_currentldt = _default_ldt;
610 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
611 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
613 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
615 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
616 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
617 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
618 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
619 md->gd_common_tssd = *md->gd_tss_gdt;
623 * Set to a known state:
624 * Set by mpboot.s: CR0_PG, CR0_PE
625 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
628 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
630 pmap_set_opt(); /* PSE/4MB pages, etc */
632 /* set up CPU registers and state */
635 /* set up FPU state on the AP */
636 npxinit(__INITIAL_NPXCW__);
638 /* set up SSE registers */
642 /*******************************************************************
643 * local functions and data
647 * start the SMP system
650 mp_enable(u_int boot_addr)
654 vm_paddr_t mpfps_paddr;
655 struct mptable_pos mpt;
657 POSTCODE(MP_ENABLE_POST);
661 mpfps_paddr = mptable_probe();
663 mptable_map(&mpt, mpfps_paddr);
667 if (apic_io_enable) {
670 panic("no MP table, disable APIC_IO! (set hw.apic_io_enable=0)\n");
672 mptable_map(&mpt, mpfps_paddr);
675 * Examine the MP table for needed info
682 /* Post scan cleanup */
685 setup_apic_irq_mapping();
687 /* fill the LOGICAL io_apic_versions table */
688 for (apic = 0; apic < mp_napics; ++apic) {
689 ux = ioapic_read(apic, IOAPIC_VER);
690 io_apic_versions[apic] = ux;
691 io_apic_set_id(apic, IO_TO_ID(apic));
694 /* program each IO APIC in the system */
695 for (apic = 0; apic < mp_napics; ++apic)
696 if (io_apic_setup(apic) < 0)
697 panic("IO APIC setup failure");
702 * These are required for SMP operation
705 /* install a 'Spurious INTerrupt' vector */
706 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
707 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
709 /* install an inter-CPU IPI for TLB invalidation */
710 setidt(XINVLTLB_OFFSET, Xinvltlb,
711 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
713 /* install an inter-CPU IPI for IPIQ messaging */
714 setidt(XIPIQ_OFFSET, Xipiq,
715 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
717 /* install a timer vector */
718 setidt(XTIMER_OFFSET, Xtimer,
719 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
721 /* install an inter-CPU IPI for CPU stop/restart */
722 setidt(XCPUSTOP_OFFSET, Xcpustop,
723 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
725 /* start each Application Processor */
726 start_all_aps(boot_addr);
731 * look for the MP spec signature
734 /* string defined by the Intel MP Spec as identifying the MP table */
735 #define MP_SIG 0x5f504d5f /* _MP_ */
736 #define NEXT(X) ((X) += 4)
738 mptable_search_sig(u_int32_t target, int count)
744 KKASSERT(target != 0);
746 map_size = count * sizeof(u_int32_t);
747 addr = pmap_mapdev((vm_paddr_t)target, map_size);
750 for (x = 0; x < count; NEXT(x)) {
751 if (addr[x] == MP_SIG) {
752 /* make array index a byte index */
753 ret = target + (x * sizeof(u_int32_t));
758 pmap_unmapdev((vm_offset_t)addr, map_size);
763 typedef struct BUSDATA {
765 enum busTypes bus_type;
768 typedef struct INTDATA {
778 typedef struct BUSTYPENAME {
783 static bus_type_name bus_type_table[] =
789 {UNKNOWN_BUSTYPE, "---"},
792 {UNKNOWN_BUSTYPE, "---"},
793 {UNKNOWN_BUSTYPE, "---"},
794 {UNKNOWN_BUSTYPE, "---"},
795 {UNKNOWN_BUSTYPE, "---"},
796 {UNKNOWN_BUSTYPE, "---"},
798 {UNKNOWN_BUSTYPE, "---"},
799 {UNKNOWN_BUSTYPE, "---"},
800 {UNKNOWN_BUSTYPE, "---"},
801 {UNKNOWN_BUSTYPE, "---"},
803 {UNKNOWN_BUSTYPE, "---"}
805 /* from MP spec v1.4, table 5-1 */
806 static int default_data[7][5] =
808 /* nbus, id0, type0, id1, type1 */
809 {1, 0, ISA, 255, 255},
810 {1, 0, EISA, 255, 255},
811 {1, 0, EISA, 255, 255},
812 {1, 0, MCA, 255, 255},
814 {2, 0, EISA, 1, PCI},
820 static bus_datum *bus_data;
822 /* the IO INT data, one entry per possible APIC INTerrupt */
823 static io_int *io_apic_ints;
826 static int processor_entry (const struct PROCENTRY *entry, int cpu);
827 static int bus_entry (const struct BUSENTRY *entry, int bus);
828 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
829 static int int_entry (const struct INTENTRY *entry, int intr);
830 static int lookup_bus_type (char *name);
833 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
835 const struct IOAPICENTRY *ioapic_ent;
838 case 1: /* bus_entry */
842 case 2: /* io_apic_entry */
844 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
845 io_apic_address[mp_napics++] =
846 (vm_offset_t)ioapic_ent->apic_address;
850 case 3: /* int_entry */
858 * 1st pass on motherboard's Intel MP specification table.
867 mptable_pass1(struct mptable_pos *mpt)
872 POSTCODE(MPTABLE_PASS1_POST);
875 KKASSERT(fps != NULL);
877 /* clear various tables */
878 for (x = 0; x < NAPICID; ++x)
879 io_apic_address[x] = ~0; /* IO APIC address table */
885 /* check for use of 'default' configuration */
886 if (fps->mpfb1 != 0) {
887 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
888 mp_nbusses = default_data[fps->mpfb1 - 1][0];
894 error = mptable_iterate_entries(mpt->mp_cth,
895 mptable_ioapic_pass1_callback, NULL);
897 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
901 struct mptable_ioapic2_cbarg {
908 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
910 struct mptable_ioapic2_cbarg *arg = xarg;
914 if (bus_entry(pos, arg->bus))
919 if (io_apic_entry(pos, arg->apic))
924 if (int_entry(pos, arg->intr))
932 * 2nd pass on motherboard's Intel MP specification table.
935 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
936 * IO_TO_ID(N), logical IO to APIC ID table
941 mptable_pass2(struct mptable_pos *mpt)
943 struct mptable_ioapic2_cbarg arg;
947 POSTCODE(MPTABLE_PASS2_POST);
950 KKASSERT(fps != NULL);
952 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
954 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
955 M_DEVBUF, M_WAITOK | M_ZERO);
956 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
958 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
961 for (x = 0; x < mp_napics; x++)
962 ioapic[x] = permanent_io_mapping(io_apic_address[x]);
964 /* clear various tables */
965 for (x = 0; x < NAPICID; ++x) {
966 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
967 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
970 /* clear bus data table */
971 for (x = 0; x < mp_nbusses; ++x)
972 bus_data[x].bus_id = 0xff;
974 /* clear IO APIC INT table */
975 for (x = 0; x < nintrs + FIXUP_EXTRA_APIC_INTS; ++x) {
976 io_apic_ints[x].int_type = 0xff;
977 io_apic_ints[x].int_vector = 0xff;
980 /* check for use of 'default' configuration */
981 if (fps->mpfb1 != 0) {
982 mptable_default(fps->mpfb1);
986 bzero(&arg, sizeof(arg));
987 error = mptable_iterate_entries(mpt->mp_cth,
988 mptable_ioapic_pass2_callback, &arg);
990 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
994 * Check if we should perform a hyperthreading "fix-up" to
995 * enumerate any logical CPU's that aren't already listed
998 * XXX: We assume that all of the physical CPUs in the
999 * system have the same number of logical CPUs.
1001 * XXX: We assume that APIC ID's are allocated such that
1002 * the APIC ID's for a physical processor are aligned
1003 * with the number of logical CPU's in the processor.
1006 mptable_hyperthread_fixup(cpumask_t id_mask, int cpu_count)
1008 int i, id, lcpus_max, logical_cpus;
1010 if ((cpu_feature & CPUID_HTT) == 0)
1013 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1017 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
1019 * INSTRUCTION SET REFERENCE, A-M (#253666)
1020 * Page 3-181, Table 3-20
1021 * "The nearest power-of-2 integer that is not smaller
1022 * than EBX[23:16] is the number of unique initial APIC
1023 * IDs reserved for addressing different logical
1024 * processors in a physical package."
1026 for (i = 0; ; ++i) {
1027 if ((1 << i) >= lcpus_max) {
1034 KKASSERT(cpu_count != 0);
1035 if (cpu_count == lcpus_max) {
1036 /* We have nothing to fix */
1038 } else if (cpu_count == 1) {
1039 /* XXX this may be incorrect */
1040 logical_cpus = lcpus_max;
1042 int cur, prev, dist;
1045 * Calculate the distances between two nearest
1046 * APIC IDs. If all such distances are same,
1047 * then it is the number of missing cpus that
1048 * we are going to fill later.
1050 dist = cur = prev = -1;
1051 for (id = 0; id < MAXCPU; ++id) {
1052 if ((id_mask & CPUMASK(id)) == 0)
1057 int new_dist = cur - prev;
1063 * Make sure that all distances
1064 * between two nearest APIC IDs
1067 if (dist != new_dist)
1075 /* Must be power of 2 */
1076 if (dist & (dist - 1))
1079 /* Can't exceed CPU package capacity */
1080 if (dist > lcpus_max)
1081 logical_cpus = lcpus_max;
1083 logical_cpus = dist;
1087 * For each APIC ID of a CPU that is set in the mask,
1088 * scan the other candidate APIC ID's for this
1089 * physical processor. If any of those ID's are
1090 * already in the table, then kill the fixup.
1092 for (id = 0; id < MAXCPU; id++) {
1093 if ((id_mask & CPUMASK(id)) == 0)
1095 /* First, make sure we are on a logical_cpus boundary. */
1096 if (id % logical_cpus != 0)
1098 for (i = id + 1; i < id + logical_cpus; i++)
1099 if ((id_mask & CPUMASK(i)) != 0)
1102 return logical_cpus;
1106 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1110 vm_size_t cth_mapsz = 0;
1112 bzero(mpt, sizeof(*mpt));
1114 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1115 if (fps->pap != 0) {
1117 * Map configuration table header to get
1118 * the base table size
1120 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1121 cth_mapsz = cth->base_table_length;
1122 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1124 if (cth_mapsz < sizeof(*cth)) {
1125 kprintf("invalid base MP table length %d\n",
1127 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1132 * Map the base table
1134 cth = pmap_mapdev(fps->pap, cth_mapsz);
1139 mpt->mp_cth_mapsz = cth_mapsz;
1145 mptable_unmap(struct mptable_pos *mpt)
1147 if (mpt->mp_cth != NULL) {
1148 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1150 mpt->mp_cth_mapsz = 0;
1152 if (mpt->mp_fps != NULL) {
1153 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1159 assign_apic_irq(int apic, int intpin, int irq)
1163 if (int_to_apicintpin[irq].ioapic != -1)
1164 panic("assign_apic_irq: inconsistent table");
1166 int_to_apicintpin[irq].ioapic = apic;
1167 int_to_apicintpin[irq].int_pin = intpin;
1168 int_to_apicintpin[irq].apic_address = ioapic[apic];
1169 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1171 for (x = 0; x < nintrs; x++) {
1172 if ((io_apic_ints[x].int_type == 0 ||
1173 io_apic_ints[x].int_type == 3) &&
1174 io_apic_ints[x].int_vector == 0xff &&
1175 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1176 io_apic_ints[x].dst_apic_int == intpin)
1177 io_apic_ints[x].int_vector = irq;
1182 revoke_apic_irq(int irq)
1188 if (int_to_apicintpin[irq].ioapic == -1)
1189 panic("revoke_apic_irq: inconsistent table");
1191 oldapic = int_to_apicintpin[irq].ioapic;
1192 oldintpin = int_to_apicintpin[irq].int_pin;
1194 int_to_apicintpin[irq].ioapic = -1;
1195 int_to_apicintpin[irq].int_pin = 0;
1196 int_to_apicintpin[irq].apic_address = NULL;
1197 int_to_apicintpin[irq].redirindex = 0;
1199 for (x = 0; x < nintrs; x++) {
1200 if ((io_apic_ints[x].int_type == 0 ||
1201 io_apic_ints[x].int_type == 3) &&
1202 io_apic_ints[x].int_vector != 0xff &&
1203 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1204 io_apic_ints[x].dst_apic_int == oldintpin)
1205 io_apic_ints[x].int_vector = 0xff;
1213 allocate_apic_irq(int intr)
1219 if (io_apic_ints[intr].int_vector != 0xff)
1220 return; /* Interrupt handler already assigned */
1222 if (io_apic_ints[intr].int_type != 0 &&
1223 (io_apic_ints[intr].int_type != 3 ||
1224 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1225 io_apic_ints[intr].dst_apic_int == 0)))
1226 return; /* Not INT or ExtInt on != (0, 0) */
1229 while (irq < APIC_INTMAPSIZE &&
1230 int_to_apicintpin[irq].ioapic != -1)
1233 if (irq >= APIC_INTMAPSIZE)
1234 return; /* No free interrupt handlers */
1236 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1237 intpin = io_apic_ints[intr].dst_apic_int;
1239 assign_apic_irq(apic, intpin, irq);
1244 swap_apic_id(int apic, int oldid, int newid)
1251 return; /* Nothing to do */
1253 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1254 apic, oldid, newid);
1256 /* Swap physical APIC IDs in interrupt entries */
1257 for (x = 0; x < nintrs; x++) {
1258 if (io_apic_ints[x].dst_apic_id == oldid)
1259 io_apic_ints[x].dst_apic_id = newid;
1260 else if (io_apic_ints[x].dst_apic_id == newid)
1261 io_apic_ints[x].dst_apic_id = oldid;
1264 /* Swap physical APIC IDs in IO_TO_ID mappings */
1265 for (oapic = 0; oapic < mp_napics; oapic++)
1266 if (IO_TO_ID(oapic) == newid)
1269 if (oapic < mp_napics) {
1270 kprintf("Changing APIC ID for IO APIC #%d from "
1271 "%d to %d in MP table\n",
1272 oapic, newid, oldid);
1273 IO_TO_ID(oapic) = oldid;
1275 IO_TO_ID(apic) = newid;
1280 fix_id_to_io_mapping(void)
1284 for (x = 0; x < NAPICID; x++)
1287 for (x = 0; x <= mp_naps; x++)
1288 if (CPU_TO_ID(x) < NAPICID)
1289 ID_TO_IO(CPU_TO_ID(x)) = x;
1291 for (x = 0; x < mp_napics; x++)
1292 if (IO_TO_ID(x) < NAPICID)
1293 ID_TO_IO(IO_TO_ID(x)) = x;
1298 first_free_apic_id(void)
1302 for (freeid = 0; freeid < NAPICID; freeid++) {
1303 for (x = 0; x <= mp_naps; x++)
1304 if (CPU_TO_ID(x) == freeid)
1308 for (x = 0; x < mp_napics; x++)
1309 if (IO_TO_ID(x) == freeid)
1320 io_apic_id_acceptable(int apic, int id)
1322 int cpu; /* Logical CPU number */
1323 int oapic; /* Logical IO APIC number for other IO APIC */
1326 return 0; /* Out of range */
1328 for (cpu = 0; cpu <= mp_naps; cpu++)
1329 if (CPU_TO_ID(cpu) == id)
1330 return 0; /* Conflict with CPU */
1332 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1333 if (IO_TO_ID(oapic) == id)
1334 return 0; /* Conflict with other APIC */
1336 return 1; /* ID is acceptable for IO APIC */
1341 io_apic_find_int_entry(int apic, int pin)
1345 /* search each of the possible INTerrupt sources */
1346 for (x = 0; x < nintrs; ++x) {
1347 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1348 (pin == io_apic_ints[x].dst_apic_int))
1349 return (&io_apic_ints[x]);
1355 * parse an Intel MP specification table
1362 int apic; /* IO APIC unit number */
1363 int freeid; /* Free physical APIC ID */
1364 int physid; /* Current physical IO APIC ID */
1366 int bus_0 = 0; /* Stop GCC warning */
1367 int bus_pci = 0; /* Stop GCC warning */
1371 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1372 * did it wrong. The MP spec says that when more than 1 PCI bus
1373 * exists the BIOS must begin with bus entries for the PCI bus and use
1374 * actual PCI bus numbering. This implies that when only 1 PCI bus
1375 * exists the BIOS can choose to ignore this ordering, and indeed many
1376 * MP motherboards do ignore it. This causes a problem when the PCI
1377 * sub-system makes requests of the MP sub-system based on PCI bus
1378 * numbers. So here we look for the situation and renumber the
1379 * busses and associated INTs in an effort to "make it right".
1382 /* find bus 0, PCI bus, count the number of PCI busses */
1383 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1384 if (bus_data[x].bus_id == 0) {
1387 if (bus_data[x].bus_type == PCI) {
1393 * bus_0 == slot of bus with ID of 0
1394 * bus_pci == slot of last PCI bus encountered
1397 /* check the 1 PCI bus case for sanity */
1398 /* if it is number 0 all is well */
1399 if (num_pci_bus == 1 &&
1400 bus_data[bus_pci].bus_id != 0) {
1402 /* mis-numbered, swap with whichever bus uses slot 0 */
1404 /* swap the bus entry types */
1405 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1406 bus_data[bus_0].bus_type = PCI;
1408 /* swap each relavant INTerrupt entry */
1409 id = bus_data[bus_pci].bus_id;
1410 for (x = 0; x < nintrs; ++x) {
1411 if (io_apic_ints[x].src_bus_id == id) {
1412 io_apic_ints[x].src_bus_id = 0;
1414 else if (io_apic_ints[x].src_bus_id == 0) {
1415 io_apic_ints[x].src_bus_id = id;
1420 /* Assign IO APIC IDs.
1422 * First try the existing ID. If a conflict is detected, try
1423 * the ID in the MP table. If a conflict is still detected, find
1426 * We cannot use the ID_TO_IO table before all conflicts has been
1427 * resolved and the table has been corrected.
1429 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1431 /* First try to use the value set by the BIOS */
1432 physid = io_apic_get_id(apic);
1433 if (io_apic_id_acceptable(apic, physid)) {
1434 if (IO_TO_ID(apic) != physid)
1435 swap_apic_id(apic, IO_TO_ID(apic), physid);
1439 /* Then check if the value in the MP table is acceptable */
1440 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1443 /* Last resort, find a free APIC ID and use it */
1444 freeid = first_free_apic_id();
1445 if (freeid >= NAPICID)
1446 panic("No free physical APIC IDs found");
1448 if (io_apic_id_acceptable(apic, freeid)) {
1449 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1452 panic("Free physical APIC ID not usable");
1454 fix_id_to_io_mapping();
1456 /* detect and fix broken Compaq MP table */
1457 if (apic_int_type(0, 0) == -1) {
1458 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1459 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1460 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1461 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1462 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1463 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1465 } else if (apic_int_type(0, 0) == 0) {
1466 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1467 for (x = 0; x < nintrs; ++x)
1468 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1469 (0 == io_apic_ints[x].dst_apic_int)) {
1470 io_apic_ints[x].int_type = 3;
1471 io_apic_ints[x].int_vector = 0xff;
1477 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1478 * controllers universally come in pairs. If IRQ 14 is specified
1479 * as an ISA interrupt, then IRQ 15 had better be too.
1481 * [ Shuttle XPC / AMD Athlon X2 ]
1482 * The MPTable is missing an entry for IRQ 15. Note that the
1483 * ACPI table has an entry for both 14 and 15.
1485 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1486 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1487 io14 = io_apic_find_int_entry(0, 14);
1488 io_apic_ints[nintrs] = *io14;
1489 io_apic_ints[nintrs].src_bus_irq = 15;
1490 io_apic_ints[nintrs].dst_apic_int = 15;
1495 /* Assign low level interrupt handlers */
1497 setup_apic_irq_mapping(void)
1503 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1504 int_to_apicintpin[x].ioapic = -1;
1505 int_to_apicintpin[x].int_pin = 0;
1506 int_to_apicintpin[x].apic_address = NULL;
1507 int_to_apicintpin[x].redirindex = 0;
1509 /* Default to masked */
1510 int_to_apicintpin[x].flags = IOAPIC_IM_FLAG_MASKED;
1513 /* First assign ISA/EISA interrupts */
1514 for (x = 0; x < nintrs; x++) {
1515 int_vector = io_apic_ints[x].src_bus_irq;
1516 if (int_vector < APIC_INTMAPSIZE &&
1517 io_apic_ints[x].int_vector == 0xff &&
1518 int_to_apicintpin[int_vector].ioapic == -1 &&
1519 (apic_int_is_bus_type(x, ISA) ||
1520 apic_int_is_bus_type(x, EISA)) &&
1521 io_apic_ints[x].int_type == 0) {
1522 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1523 io_apic_ints[x].dst_apic_int,
1528 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1529 for (x = 0; x < nintrs; x++) {
1530 if (io_apic_ints[x].dst_apic_int == 0 &&
1531 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1532 io_apic_ints[x].int_vector == 0xff &&
1533 int_to_apicintpin[0].ioapic == -1 &&
1534 io_apic_ints[x].int_type == 3) {
1535 assign_apic_irq(0, 0, 0);
1540 /* Assign PCI interrupts */
1541 for (x = 0; x < nintrs; ++x) {
1542 if (io_apic_ints[x].int_type == 0 &&
1543 io_apic_ints[x].int_vector == 0xff &&
1544 apic_int_is_bus_type(x, PCI))
1545 allocate_apic_irq(x);
1550 mp_set_cpuids(int cpu_id, int apic_id)
1552 CPU_TO_ID(cpu_id) = apic_id;
1553 ID_TO_CPU(apic_id) = cpu_id;
1557 processor_entry(const struct PROCENTRY *entry, int cpu)
1561 /* check for usability */
1562 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1565 /* check for BSP flag */
1566 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1567 mp_set_cpuids(0, entry->apic_id);
1568 return 0; /* its already been counted */
1571 /* add another AP to list, if less than max number of CPUs */
1572 else if (cpu < MAXCPU) {
1573 mp_set_cpuids(cpu, entry->apic_id);
1581 bus_entry(const struct BUSENTRY *entry, int bus)
1586 /* encode the name into an index */
1587 for (x = 0; x < 6; ++x) {
1588 if ((c = entry->bus_type[x]) == ' ')
1594 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1595 panic("unknown bus type: '%s'", name);
1597 bus_data[bus].bus_id = entry->bus_id;
1598 bus_data[bus].bus_type = x;
1604 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1606 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1609 IO_TO_ID(apic) = entry->apic_id;
1610 ID_TO_IO(entry->apic_id) = apic;
1616 lookup_bus_type(char *name)
1620 for (x = 0; x < MAX_BUSTYPE; ++x)
1621 if (strcmp(bus_type_table[x].name, name) == 0)
1622 return bus_type_table[x].type;
1624 return UNKNOWN_BUSTYPE;
1628 int_entry(const struct INTENTRY *entry, int intr)
1632 io_apic_ints[intr].int_type = entry->int_type;
1633 io_apic_ints[intr].int_flags = entry->int_flags;
1634 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1635 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1636 if (entry->dst_apic_id == 255) {
1637 /* This signal goes to all IO APICS. Select an IO APIC
1638 with sufficient number of interrupt pins */
1639 for (apic = 0; apic < mp_napics; apic++)
1640 if (((ioapic_read(apic, IOAPIC_VER) &
1641 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1642 entry->dst_apic_int)
1644 if (apic < mp_napics)
1645 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1647 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1649 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1650 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1656 apic_int_is_bus_type(int intr, int bus_type)
1660 for (bus = 0; bus < mp_nbusses; ++bus)
1661 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1662 && ((int) bus_data[bus].bus_type == bus_type))
1669 * Given a traditional ISA INT mask, return an APIC mask.
1672 isa_apic_mask(u_int isa_mask)
1677 #if defined(SKIP_IRQ15_REDIRECT)
1678 if (isa_mask == (1 << 15)) {
1679 kprintf("skipping ISA IRQ15 redirect\n");
1682 #endif /* SKIP_IRQ15_REDIRECT */
1684 isa_irq = ffs(isa_mask); /* find its bit position */
1685 if (isa_irq == 0) /* doesn't exist */
1687 --isa_irq; /* make it zero based */
1689 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1693 return (1 << apic_pin); /* convert pin# to a mask */
1697 * Determine which APIC pin an ISA/EISA INT is attached to.
1699 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1700 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1701 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1702 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1704 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1706 isa_apic_irq(int isa_irq)
1710 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1711 if (INTTYPE(intr) == 0) { /* standard INT */
1712 if (SRCBUSIRQ(intr) == isa_irq) {
1713 if (apic_int_is_bus_type(intr, ISA) ||
1714 apic_int_is_bus_type(intr, EISA)) {
1715 if (INTIRQ(intr) == 0xff)
1716 return -1; /* unassigned */
1717 return INTIRQ(intr); /* found */
1722 return -1; /* NOT found */
1727 * Determine which APIC pin a PCI INT is attached to.
1729 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1730 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1731 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1733 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1737 --pciInt; /* zero based */
1739 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1740 if ((INTTYPE(intr) == 0) /* standard INT */
1741 && (SRCBUSID(intr) == pciBus)
1742 && (SRCBUSDEVICE(intr) == pciDevice)
1743 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1744 if (apic_int_is_bus_type(intr, PCI)) {
1745 if (INTIRQ(intr) == 0xff) {
1746 kprintf("IOAPIC: pci_apic_irq() "
1748 return -1; /* unassigned */
1750 return INTIRQ(intr); /* exact match */
1755 return -1; /* NOT found */
1759 next_apic_irq(int irq)
1766 for (intr = 0; intr < nintrs; intr++) {
1767 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1769 bus = SRCBUSID(intr);
1770 bustype = apic_bus_type(bus);
1771 if (bustype != ISA &&
1777 if (intr >= nintrs) {
1780 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1781 if (INTTYPE(ointr) != 0)
1783 if (bus != SRCBUSID(ointr))
1785 if (bustype == PCI) {
1786 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1788 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1791 if (bustype == ISA || bustype == EISA) {
1792 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1795 if (INTPIN(intr) == INTPIN(ointr))
1799 if (ointr >= nintrs) {
1802 return INTIRQ(ointr);
1815 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1818 * Exactly what this means is unclear at this point. It is a solution
1819 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1820 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1821 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1825 undirect_isa_irq(int rirq)
1829 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1830 /** FIXME: tickle the MB redirector chip */
1834 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1841 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1844 undirect_pci_irq(int rirq)
1848 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1850 /** FIXME: tickle the MB redirector chip */
1854 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1862 * given a bus ID, return:
1863 * the bus type if found
1867 apic_bus_type(int id)
1871 for (x = 0; x < mp_nbusses; ++x)
1872 if (bus_data[x].bus_id == id)
1873 return bus_data[x].bus_type;
1879 * given a LOGICAL APIC# and pin#, return:
1880 * the associated src bus ID if found
1884 apic_src_bus_id(int apic, int pin)
1888 /* search each of the possible INTerrupt sources */
1889 for (x = 0; x < nintrs; ++x)
1890 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1891 (pin == io_apic_ints[x].dst_apic_int))
1892 return (io_apic_ints[x].src_bus_id);
1894 return -1; /* NOT found */
1898 * given a LOGICAL APIC# and pin#, return:
1899 * the associated src bus IRQ if found
1903 apic_src_bus_irq(int apic, int pin)
1907 for (x = 0; x < nintrs; x++)
1908 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1909 (pin == io_apic_ints[x].dst_apic_int))
1910 return (io_apic_ints[x].src_bus_irq);
1912 return -1; /* NOT found */
1917 * given a LOGICAL APIC# and pin#, return:
1918 * the associated INTerrupt type if found
1922 apic_int_type(int apic, int pin)
1926 /* search each of the possible INTerrupt sources */
1927 for (x = 0; x < nintrs; ++x) {
1928 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1929 (pin == io_apic_ints[x].dst_apic_int))
1930 return (io_apic_ints[x].int_type);
1932 return -1; /* NOT found */
1936 * Return the IRQ associated with an APIC pin
1939 apic_irq(int apic, int pin)
1944 for (x = 0; x < nintrs; ++x) {
1945 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1946 (pin == io_apic_ints[x].dst_apic_int)) {
1947 res = io_apic_ints[x].int_vector;
1950 if (apic != int_to_apicintpin[res].ioapic)
1951 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1952 if (pin != int_to_apicintpin[res].int_pin)
1953 panic("apic_irq inconsistent table (2)");
1962 * given a LOGICAL APIC# and pin#, return:
1963 * the associated trigger mode if found
1967 apic_trigger(int apic, int pin)
1971 /* search each of the possible INTerrupt sources */
1972 for (x = 0; x < nintrs; ++x)
1973 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1974 (pin == io_apic_ints[x].dst_apic_int))
1975 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1977 return -1; /* NOT found */
1982 * given a LOGICAL APIC# and pin#, return:
1983 * the associated 'active' level if found
1987 apic_polarity(int apic, int pin)
1991 /* search each of the possible INTerrupt sources */
1992 for (x = 0; x < nintrs; ++x)
1993 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1994 (pin == io_apic_ints[x].dst_apic_int))
1995 return (io_apic_ints[x].int_flags & 0x03);
1997 return -1; /* NOT found */
2001 * set data according to MP defaults
2002 * FIXME: probably not complete yet...
2005 mptable_default(int type)
2011 kprintf(" MP default config type: %d\n", type);
2014 kprintf(" bus: ISA, APIC: 82489DX\n");
2017 kprintf(" bus: EISA, APIC: 82489DX\n");
2020 kprintf(" bus: EISA, APIC: 82489DX\n");
2023 kprintf(" bus: MCA, APIC: 82489DX\n");
2026 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2029 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2032 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2035 kprintf(" future type\n");
2041 /* one and only IO APIC */
2042 io_apic_id = (ioapic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2045 * sanity check, refer to MP spec section 3.6.6, last paragraph
2046 * necessary as some hardware isn't properly setting up the IO APIC
2048 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2049 if (io_apic_id != 2) {
2051 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2052 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2053 io_apic_set_id(0, 2);
2056 IO_TO_ID(0) = io_apic_id;
2057 ID_TO_IO(io_apic_id) = 0;
2059 /* fill out bus entries */
2068 bus_data[0].bus_id = default_data[type - 1][1];
2069 bus_data[0].bus_type = default_data[type - 1][2];
2070 bus_data[1].bus_id = default_data[type - 1][3];
2071 bus_data[1].bus_type = default_data[type - 1][4];
2074 /* case 4: case 7: MCA NOT supported */
2075 default: /* illegal/reserved */
2076 panic("BAD default MP config: %d", type);
2080 /* general cases from MP v1.4, table 5-2 */
2081 for (pin = 0; pin < 16; ++pin) {
2082 io_apic_ints[pin].int_type = 0;
2083 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2084 io_apic_ints[pin].src_bus_id = 0;
2085 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2086 io_apic_ints[pin].dst_apic_id = io_apic_id;
2087 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2090 /* special cases from MP v1.4, table 5-2 */
2092 io_apic_ints[2].int_type = 0xff; /* N/C */
2093 io_apic_ints[13].int_type = 0xff; /* N/C */
2094 #if !defined(APIC_MIXED_MODE)
2096 panic("sorry, can't support type 2 default yet");
2097 #endif /* APIC_MIXED_MODE */
2100 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2103 io_apic_ints[0].int_type = 0xff; /* N/C */
2105 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2109 * Map a physical memory address representing I/O into KVA. The I/O
2110 * block is assumed not to cross a page boundary.
2113 permanent_io_mapping(vm_paddr_t pa)
2119 KKASSERT(pa < 0x100000000LL);
2121 pgeflag = 0; /* not used for SMP yet */
2124 * If the requested physical address has already been incidently
2125 * mapped, just use the existing mapping. Otherwise create a new
2128 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2129 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2130 ((vm_offset_t)pa & PG_FRAME)) {
2134 if (i == SMPpt_alloc_index) {
2135 if (i == NPTEPG - 2) {
2136 panic("permanent_io_mapping: We ran out of space"
2139 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | PG_N | pgeflag |
2140 ((vm_offset_t)pa & PG_FRAME));
2141 ++SMPpt_alloc_index;
2143 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2144 ((vm_offset_t)pa & PAGE_MASK);
2145 return ((void *)vaddr);
2149 * start each AP in our list
2152 start_all_aps(u_int boot_addr)
2159 u_char mpbiosreason;
2160 u_long mpbioswarmvec;
2161 struct mdglobaldata *gd;
2162 struct privatespace *ps;
2166 POSTCODE(START_ALL_APS_POST);
2168 /* Initialize BSP's local APIC */
2169 apic_initialize(TRUE);
2172 MachIntrABI.finalize();
2174 /* install the AP 1st level boot code */
2175 install_ap_tramp(boot_addr);
2178 /* save the current value of the warm-start vector */
2179 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2180 outb(CMOS_REG, BIOS_RESET);
2181 mpbiosreason = inb(CMOS_DATA);
2183 /* setup a vector to our boot code */
2184 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2185 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2186 outb(CMOS_REG, BIOS_RESET);
2187 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2190 * If we have a TSC we can figure out the SMI interrupt rate.
2191 * The SMI does not necessarily use a constant rate. Spend
2192 * up to 250ms trying to figure it out.
2195 if (cpu_feature & CPUID_TSC) {
2196 set_apic_timer(275000);
2197 smilast = read_apic_timer();
2198 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2199 smicount = smitest();
2200 if (smibest == 0 || smilast - smicount < smibest)
2201 smibest = smilast - smicount;
2204 if (smibest > 250000)
2207 smibest = smibest * (int64_t)1000000 /
2208 get_apic_timer_frequency();
2212 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2213 1000000 / smibest, smibest);
2216 /* set up temporary P==V mapping for AP boot */
2217 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2218 kptbase = (uintptr_t)(void *)KPTphys;
2219 for (x = 0; x < NKPT; x++) {
2220 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2221 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2226 for (x = 1; x <= mp_naps; ++x) {
2228 /* This is a bit verbose, it will go away soon. */
2230 /* first page of AP's private space */
2231 pg = x * i386_btop(sizeof(struct privatespace));
2233 /* allocate new private data page(s) */
2234 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2235 MDGLOBALDATA_BASEALLOC_SIZE);
2236 /* wire it into the private page table page */
2237 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2238 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2239 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2241 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2243 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2244 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2245 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2246 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2248 /* allocate and set up an idle stack data page */
2249 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2250 for (i = 0; i < UPAGES; i++) {
2251 SMPpt[pg + 4 + i] = (pt_entry_t)
2252 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2255 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2256 bzero(gd, sizeof(*gd));
2257 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2259 /* prime data page for it to use */
2260 mi_gdinit(&gd->mi, x);
2262 gd->gd_CMAP1 = &SMPpt[pg + 0];
2263 gd->gd_CMAP2 = &SMPpt[pg + 1];
2264 gd->gd_CMAP3 = &SMPpt[pg + 2];
2265 gd->gd_PMAP1 = &SMPpt[pg + 3];
2266 gd->gd_CADDR1 = ps->CPAGE1;
2267 gd->gd_CADDR2 = ps->CPAGE2;
2268 gd->gd_CADDR3 = ps->CPAGE3;
2269 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2272 * Per-cpu pmap for get_ptbase().
2274 gd->gd_GDADDR1= (unsigned *)
2275 kmem_alloc_nofault(&kernel_map, SEG_SIZE, SEG_SIZE);
2276 gd->gd_GDMAP1 = &PTD[(vm_offset_t)gd->gd_GDADDR1 >> PDRSHIFT];
2278 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2279 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2282 * Setup the AP boot stack
2284 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2287 /* attempt to start the Application Processor */
2288 CHECK_INIT(99); /* setup checkpoints */
2289 if (!start_ap(gd, boot_addr, smibest)) {
2290 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2291 CHECK_PRINT("trace"); /* show checkpoints */
2292 /* better panic as the AP may be running loose */
2293 kprintf("panic y/n? [y] ");
2294 if (cngetc() != 'n')
2297 CHECK_PRINT("trace"); /* show checkpoints */
2299 /* record its version info */
2300 cpu_apic_versions[x] = cpu_apic_versions[0];
2303 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2306 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2307 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2310 ncpus2_shift = shift;
2311 ncpus2 = 1 << shift;
2312 ncpus2_mask = ncpus2 - 1;
2314 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2315 if ((1 << shift) < ncpus)
2317 ncpus_fit = 1 << shift;
2318 ncpus_fit_mask = ncpus_fit - 1;
2320 /* build our map of 'other' CPUs */
2321 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2322 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2323 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2325 /* fill in our (BSP) APIC version */
2326 cpu_apic_versions[0] = lapic.version;
2328 /* restore the warmstart vector */
2329 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2330 outb(CMOS_REG, BIOS_RESET);
2331 outb(CMOS_DATA, mpbiosreason);
2334 * NOTE! The idlestack for the BSP was setup by locore. Finish
2335 * up, clean out the P==V mapping we did earlier.
2337 for (x = 0; x < NKPT; x++)
2341 /* number of APs actually started */
2346 * load the 1st level AP boot code into base memory.
2349 /* targets for relocation */
2350 extern void bigJump(void);
2351 extern void bootCodeSeg(void);
2352 extern void bootDataSeg(void);
2353 extern void MPentry(void);
2354 extern u_int MP_GDT;
2355 extern u_int mp_gdtbase;
2358 install_ap_tramp(u_int boot_addr)
2361 int size = *(int *) ((u_long) & bootMP_size);
2362 u_char *src = (u_char *) ((u_long) bootMP);
2363 u_char *dst = (u_char *) boot_addr + KERNBASE;
2364 u_int boot_base = (u_int) bootMP;
2369 POSTCODE(INSTALL_AP_TRAMP_POST);
2371 for (x = 0; x < size; ++x)
2375 * modify addresses in code we just moved to basemem. unfortunately we
2376 * need fairly detailed info about mpboot.s for this to work. changes
2377 * to mpboot.s might require changes here.
2380 /* boot code is located in KERNEL space */
2381 dst = (u_char *) boot_addr + KERNBASE;
2383 /* modify the lgdt arg */
2384 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2385 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2387 /* modify the ljmp target for MPentry() */
2388 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2389 *dst32 = ((u_int) MPentry - KERNBASE);
2391 /* modify the target for boot code segment */
2392 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2393 dst8 = (u_int8_t *) (dst16 + 1);
2394 *dst16 = (u_int) boot_addr & 0xffff;
2395 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2397 /* modify the target for boot data segment */
2398 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2399 dst8 = (u_int8_t *) (dst16 + 1);
2400 *dst16 = (u_int) boot_addr & 0xffff;
2401 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2406 * This function starts the AP (application processor) identified
2407 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2408 * to accomplish this. This is necessary because of the nuances
2409 * of the different hardware we might encounter. It ain't pretty,
2410 * but it seems to work.
2412 * NOTE: eventually an AP gets to ap_init(), which is called just
2413 * before the AP goes into the LWKT scheduler's idle loop.
2416 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2420 u_long icr_lo, icr_hi;
2422 POSTCODE(START_AP_POST);
2424 /* get the PHYSICAL APIC ID# */
2425 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2427 /* calculate the vector */
2428 vector = (boot_addr >> 12) & 0xff;
2430 /* We don't want anything interfering */
2433 /* Make sure the target cpu sees everything */
2437 * Try to detect when a SMI has occurred, wait up to 200ms.
2439 * If a SMI occurs during an AP reset but before we issue
2440 * the STARTUP command, the AP may brick. To work around
2441 * this problem we hold off doing the AP startup until
2442 * after we have detected the SMI. Hopefully another SMI
2443 * will not occur before we finish the AP startup.
2445 * Retries don't seem to help. SMIs have a window of opportunity
2446 * and if USB->legacy keyboard emulation is enabled in the BIOS
2447 * the interrupt rate can be quite high.
2449 * NOTE: Don't worry about the L1 cache load, it might bloat
2450 * ldelta a little but ndelta will be so huge when the SMI
2451 * occurs the detection logic will still work fine.
2454 set_apic_timer(200000);
2459 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2460 * and running the target CPU. OR this INIT IPI might be latched (P5
2461 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2464 * see apic/apicreg.h for icr bit definitions.
2466 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2470 * Setup the address for the target AP. We can setup
2471 * icr_hi once and then just trigger operations with
2474 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2475 icr_hi |= (physical_cpu << 24);
2476 icr_lo = lapic.icr_lo & 0xfff00000;
2477 lapic.icr_hi = icr_hi;
2480 * Do an INIT IPI: assert RESET
2482 * Use edge triggered mode to assert INIT
2484 lapic.icr_lo = icr_lo | 0x0000c500;
2485 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2489 * The spec calls for a 10ms delay but we may have to use a
2490 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2491 * interrupt. We have other loops here too and dividing by 2
2492 * doesn't seem to be enough even after subtracting 350us,
2493 * so we divide by 4.
2495 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2496 * interrupt was detected we use the full 10ms.
2500 else if (smibest < 150 * 4 + 350)
2502 else if ((smibest - 350) / 4 < 10000)
2503 u_sleep((smibest - 350) / 4);
2508 * Do an INIT IPI: deassert RESET
2510 * Use level triggered mode to deassert. It is unclear
2511 * why we need to do this.
2513 lapic.icr_lo = icr_lo | 0x00008500;
2514 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2516 u_sleep(150); /* wait 150us */
2519 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2520 * latched, (P5 bug) this 1st STARTUP would then terminate
2521 * immediately, and the previously started INIT IPI would continue. OR
2522 * the previous INIT IPI has already run. and this STARTUP IPI will
2523 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2526 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2527 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2529 u_sleep(200); /* wait ~200uS */
2532 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2533 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2534 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2535 * recognized after hardware RESET or INIT IPI.
2537 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2538 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2541 /* Resume normal operation */
2544 /* wait for it to start, see ap_init() */
2545 set_apic_timer(5000000);/* == 5 seconds */
2546 while (read_apic_timer()) {
2547 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
2548 return 1; /* return SUCCESS */
2551 return 0; /* return FAILURE */
2566 while (read_apic_timer()) {
2568 for (count = 0; count < 100; ++count)
2569 ntsc = rdtsc(); /* force loop to occur */
2571 ndelta = ntsc - ltsc;
2572 if (ldelta > ndelta)
2574 if (ndelta > ldelta * 2)
2577 ldelta = ntsc - ltsc;
2580 return(read_apic_timer());
2584 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2586 * If for some reason we were unable to start all cpus we cannot safely
2587 * use broadcast IPIs.
2590 static cpumask_t smp_invltlb_req;
2591 #define SMP_INVLTLB_DEBUG
2597 struct mdglobaldata *md = mdcpu;
2598 #ifdef SMP_INVLTLB_DEBUG
2603 crit_enter_gd(&md->mi);
2604 md->gd_invltlb_ret = 0;
2605 ++md->mi.gd_cnt.v_smpinvltlb;
2606 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2607 #ifdef SMP_INVLTLB_DEBUG
2610 if (smp_startup_mask == smp_active_mask) {
2611 all_but_self_ipi(XINVLTLB_OFFSET);
2613 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
2614 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
2617 #ifdef SMP_INVLTLB_DEBUG
2619 kprintf("smp_invltlb: ipi sent\n");
2621 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
2622 (smp_active_mask & ~md->mi.gd_cpumask)) {
2625 #ifdef SMP_INVLTLB_DEBUG
2627 if (++count == 400000000) {
2628 print_backtrace(-1);
2629 kprintf("smp_invltlb: endless loop %08lx %08lx, "
2630 "rflags %016lx retry",
2631 (long)md->gd_invltlb_ret,
2632 (long)smp_invltlb_req,
2633 (long)read_eflags());
2634 __asm __volatile ("sti");
2637 lwkt_process_ipiq();
2639 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
2640 ~md->mi.gd_cpumask &
2643 kprintf("bcpu %d\n", bcpu);
2644 xgd = globaldata_find(bcpu);
2645 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
2654 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2655 crit_exit_gd(&md->mi);
2662 * Called from Xinvltlb assembly with interrupts disabled. We didn't
2663 * bother to bump the critical section count or nested interrupt count
2664 * so only do very low level operations here.
2667 smp_invltlb_intr(void)
2669 struct mdglobaldata *md = mdcpu;
2670 struct mdglobaldata *omd;
2674 mask = smp_invltlb_req;
2678 cpu = BSFCPUMASK(mask);
2679 mask &= ~CPUMASK(cpu);
2680 omd = (struct mdglobaldata *)globaldata_find(cpu);
2681 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
2688 * When called the executing CPU will send an IPI to all other CPUs
2689 * requesting that they halt execution.
2691 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2693 * - Signals all CPUs in map to stop.
2694 * - Waits for each to stop.
2701 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2702 * from executing at same time.
2705 stop_cpus(cpumask_t map)
2707 map &= smp_active_mask;
2709 /* send the Xcpustop IPI to all CPUs in map */
2710 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2712 while ((stopped_cpus & map) != map)
2720 * Called by a CPU to restart stopped CPUs.
2722 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2724 * - Signals all CPUs in map to restart.
2725 * - Waits for each to restart.
2733 restart_cpus(cpumask_t map)
2735 /* signal other cpus to restart */
2736 started_cpus = map & smp_active_mask;
2738 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2745 * This is called once the mpboot code has gotten us properly relocated
2746 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2747 * and when it returns the scheduler will call the real cpu_idle() main
2748 * loop for the idlethread. Interrupts are disabled on entry and should
2749 * remain disabled at return.
2757 * Adjust smp_startup_mask to signal the BSP that we have started
2758 * up successfully. Note that we do not yet hold the BGL. The BSP
2759 * is waiting for our signal.
2761 * We can't set our bit in smp_active_mask yet because we are holding
2762 * interrupts physically disabled and remote cpus could deadlock
2763 * trying to send us an IPI.
2765 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
2769 * Interlock for finalization. Wait until mp_finish is non-zero,
2770 * then get the MP lock.
2772 * Note: We are in a critical section.
2774 * Note: we are the idle thread, we can only spin.
2776 * Note: The load fence is memory volatile and prevents the compiler
2777 * from improperly caching mp_finish, and the cpu from improperly
2780 while (mp_finish == 0)
2782 while (try_mplock() == 0)
2785 if (cpu_feature & CPUID_TSC) {
2787 * The BSP is constantly updating tsc0_offset, figure out
2788 * the relative difference to synchronize ktrdump.
2790 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2793 /* BSP may have changed PTD while we're waiting for the lock */
2796 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2800 /* Build our map of 'other' CPUs. */
2801 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2803 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2805 /* A quick check from sanity claus */
2806 apic_id = (apic_id_to_logical[(lapic.id & 0xff000000) >> 24]);
2807 if (mycpu->gd_cpuid != apic_id) {
2808 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2809 kprintf("SMP: apic_id = %d\n", apic_id);
2810 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2811 panic("cpuid mismatch! boom!!");
2814 /* Initialize AP's local APIC for irq's */
2815 apic_initialize(FALSE);
2817 /* Set memory range attributes for this CPU to match the BSP */
2818 mem_range_AP_init();
2821 * Once we go active we must process any IPIQ messages that may
2822 * have been queued, because no actual IPI will occur until we
2823 * set our bit in the smp_active_mask. If we don't the IPI
2824 * message interlock could be left set which would also prevent
2827 * The idle loop doesn't expect the BGL to be held and while
2828 * lwkt_switch() normally cleans things up this is a special case
2829 * because we returning almost directly into the idle loop.
2831 * The idle thread is never placed on the runq, make sure
2832 * nothing we've done put it there.
2834 KKASSERT(get_mplock_count(curthread) == 1);
2835 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
2838 * Enable interrupts here. idle_restore will also do it, but
2839 * doing it here lets us clean up any strays that got posted to
2840 * the CPU during the AP boot while we are still in a critical
2843 __asm __volatile("sti; pause; pause"::);
2844 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
2846 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2847 lwkt_process_ipiq();
2850 * Releasing the mp lock lets the BSP finish up the SMP init
2853 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2857 * Get SMP fully working before we start initializing devices.
2865 kprintf("Finish MP startup\n");
2866 if (cpu_feature & CPUID_TSC)
2867 tsc0_offset = rdtsc();
2870 while (smp_active_mask != smp_startup_mask) {
2872 if (cpu_feature & CPUID_TSC)
2873 tsc0_offset = rdtsc();
2875 while (try_mplock() == 0)
2878 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2881 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2884 cpu_send_ipiq(int dcpu)
2886 if (CPUMASK(dcpu) & smp_active_mask)
2887 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2890 #if 0 /* single_apic_ipi_passive() not working yet */
2892 * Returns 0 on failure, 1 on success
2895 cpu_send_ipiq_passive(int dcpu)
2898 if (CPUMASK(dcpu) & smp_active_mask) {
2899 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2900 APIC_DELMODE_FIXED);
2906 struct mptable_lapic_cbarg1 {
2909 u_int ht_apicid_mask;
2913 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2915 const struct PROCENTRY *ent;
2916 struct mptable_lapic_cbarg1 *arg = xarg;
2922 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2926 if (ent->apic_id < 32) {
2927 arg->ht_apicid_mask |= 1 << ent->apic_id;
2928 } else if (arg->ht_fixup) {
2929 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2935 struct mptable_lapic_cbarg2 {
2942 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2944 const struct PROCENTRY *ent;
2945 struct mptable_lapic_cbarg2 *arg = xarg;
2951 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2952 KKASSERT(!arg->found_bsp);
2956 if (processor_entry(ent, arg->cpu))
2959 if (arg->logical_cpus) {
2960 struct PROCENTRY proc;
2964 * Create fake mptable processor entries
2965 * and feed them to processor_entry() to
2966 * enumerate the logical CPUs.
2968 bzero(&proc, sizeof(proc));
2970 proc.cpu_flags = PROCENTRY_FLAG_EN;
2971 proc.apic_id = ent->apic_id;
2973 for (i = 1; i < arg->logical_cpus; i++) {
2975 processor_entry(&proc, arg->cpu);
2983 mptable_imcr(struct mptable_pos *mpt)
2985 /* record whether PIC or virtual-wire mode */
2986 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
2987 mpt->mp_fps->mpfb2 & 0x80);
2990 struct mptable_lapic_enumerator {
2991 struct lapic_enumerator enumerator;
2992 vm_paddr_t mpfps_paddr;
2996 mptable_lapic_default(void)
2998 int ap_apicid, bsp_apicid;
3000 mp_naps = 1; /* exclude BSP */
3002 /* Map local apic before the id field is accessed */
3003 lapic_map(DEFAULT_APIC_BASE);
3005 bsp_apicid = APIC_ID(lapic.id);
3006 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
3009 mp_set_cpuids(0, bsp_apicid);
3010 /* one and only AP */
3011 mp_set_cpuids(1, ap_apicid);
3017 * ID_TO_CPU(N), APIC ID to logical CPU table
3018 * CPU_TO_ID(N), logical CPU to APIC ID table
3021 mptable_lapic_enumerate(struct lapic_enumerator *e)
3023 struct mptable_pos mpt;
3024 struct mptable_lapic_cbarg1 arg1;
3025 struct mptable_lapic_cbarg2 arg2;
3027 int error, logical_cpus = 0;
3028 vm_offset_t lapic_addr;
3029 vm_paddr_t mpfps_paddr;
3031 mpfps_paddr = ((struct mptable_lapic_enumerator *)e)->mpfps_paddr;
3032 KKASSERT(mpfps_paddr != 0);
3034 error = mptable_map(&mpt, mpfps_paddr);
3036 panic("mptable_lapic_enumerate mptable_map failed\n");
3038 KKASSERT(mpt.mp_fps != NULL);
3041 * Check for use of 'default' configuration
3043 if (mpt.mp_fps->mpfb1 != 0) {
3044 mptable_lapic_default();
3045 mptable_unmap(&mpt);
3050 KKASSERT(cth != NULL);
3052 /* Save local apic address */
3053 lapic_addr = (vm_offset_t)cth->apic_address;
3054 KKASSERT(lapic_addr != 0);
3057 * Find out how many CPUs do we have
3059 bzero(&arg1, sizeof(arg1));
3060 arg1.ht_fixup = 1; /* Apply ht fixup by default */
3062 error = mptable_iterate_entries(cth,
3063 mptable_lapic_pass1_callback, &arg1);
3065 panic("mptable_iterate_entries(lapic_pass1) failed\n");
3066 KKASSERT(arg1.cpu_count != 0);
3068 /* See if we need to fixup HT logical CPUs. */
3069 if (arg1.ht_fixup) {
3070 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
3072 if (logical_cpus != 0)
3073 arg1.cpu_count *= logical_cpus;
3075 mp_naps = arg1.cpu_count;
3077 /* Qualify the numbers again, after possible HT fixup */
3078 if (mp_naps > MAXCPU) {
3079 kprintf("Warning: only using %d of %d available CPUs!\n",
3084 --mp_naps; /* subtract the BSP */
3087 * Link logical CPU id to local apic id
3089 bzero(&arg2, sizeof(arg2));
3091 arg2.logical_cpus = logical_cpus;
3093 error = mptable_iterate_entries(cth,
3094 mptable_lapic_pass2_callback, &arg2);
3096 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3097 KKASSERT(arg2.found_bsp);
3099 /* Map local apic */
3100 lapic_map(lapic_addr);
3102 mptable_unmap(&mpt);
3106 mptable_lapic_probe(struct lapic_enumerator *e)
3108 vm_paddr_t mpfps_paddr;
3110 mpfps_paddr = mptable_probe();
3111 if (mpfps_paddr == 0)
3114 ((struct mptable_lapic_enumerator *)e)->mpfps_paddr = mpfps_paddr;
3118 static struct mptable_lapic_enumerator mptable_lapic_enumerator = {
3120 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
3121 .lapic_probe = mptable_lapic_probe,
3122 .lapic_enumerate = mptable_lapic_enumerate
3127 mptable_apic_register(void)
3129 lapic_enumerator_register(&mptable_lapic_enumerator.enumerator);
3131 SYSINIT(madt, SI_BOOT2_PRESMP, SI_ORDER_ANY, mptable_apic_register, 0);