2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/pci/pci.c,v 1.355.2.9.2.1 2009/04/15 03:14:26 kensmith Exp $
33 #include "opt_compat_oldpci.h"
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
39 #include <sys/linker.h>
40 #include <sys/fcntl.h>
42 #include <sys/kernel.h>
43 #include <sys/queue.h>
44 #include <sys/sysctl.h>
45 #include <sys/endian.h>
46 #include <sys/machintr.h>
48 #include <machine/msi_machdep.h>
52 #include <vm/vm_extern.h>
56 #include <sys/device.h>
58 #include <sys/pciio.h>
59 #include <bus/pci/pcireg.h>
60 #include <bus/pci/pcivar.h>
61 #include <bus/pci/pci_private.h>
67 #include <contrib/dev/acpica/acpi.h>
70 #define ACPI_PWR_FOR_SLEEP(x, y, z)
73 extern struct dev_ops pcic_ops; /* XXX */
75 typedef void (*pci_read_cap_t)(device_t, int, int, pcicfgregs *);
77 static uint32_t pci_mapbase(unsigned mapreg);
78 static const char *pci_maptype(unsigned mapreg);
79 static int pci_mapsize(unsigned testval);
80 static int pci_maprange(unsigned mapreg);
81 static void pci_fixancient(pcicfgregs *cfg);
83 static int pci_porten(device_t pcib, int b, int s, int f);
84 static int pci_memen(device_t pcib, int b, int s, int f);
85 static void pci_assign_interrupt(device_t bus, device_t dev,
87 static int pci_add_map(device_t pcib, device_t bus, device_t dev,
88 int b, int s, int f, int reg,
89 struct resource_list *rl, int force, int prefetch);
90 static int pci_probe(device_t dev);
91 static int pci_attach(device_t dev);
92 static void pci_child_detached(device_t, device_t);
93 static void pci_load_vendor_data(void);
94 static int pci_describe_parse_line(char **ptr, int *vendor,
95 int *device, char **desc);
96 static char *pci_describe_device(device_t dev);
97 static int pci_modevent(module_t mod, int what, void *arg);
98 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
100 static void pci_read_capabilities(device_t pcib, pcicfgregs *cfg);
101 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
102 int reg, uint32_t *data);
104 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
105 int reg, uint32_t data);
107 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
108 static void pci_disable_msi(device_t dev);
109 static void pci_enable_msi(device_t dev, uint64_t address,
111 static void pci_setup_msix_vector(device_t dev, u_int index,
112 uint64_t address, uint32_t data);
113 static void pci_mask_msix_vector(device_t dev, u_int index);
114 static void pci_unmask_msix_vector(device_t dev, u_int index);
115 static void pci_mask_msix_allvectors(device_t dev);
116 static int pci_msi_blacklisted(void);
117 static void pci_resume_msi(device_t dev);
118 static void pci_resume_msix(device_t dev);
119 static int pcie_slotimpl(const pcicfgregs *);
120 static void pci_print_verbose_expr(const pcicfgregs *);
122 static void pci_read_cap_pmgt(device_t, int, int, pcicfgregs *);
123 static void pci_read_cap_ht(device_t, int, int, pcicfgregs *);
124 static void pci_read_cap_msi(device_t, int, int, pcicfgregs *);
125 static void pci_read_cap_msix(device_t, int, int, pcicfgregs *);
126 static void pci_read_cap_vpd(device_t, int, int, pcicfgregs *);
127 static void pci_read_cap_subvendor(device_t, int, int,
129 static void pci_read_cap_pcix(device_t, int, int, pcicfgregs *);
130 static void pci_read_cap_express(device_t, int, int, pcicfgregs *);
132 static device_method_t pci_methods[] = {
133 /* Device interface */
134 DEVMETHOD(device_probe, pci_probe),
135 DEVMETHOD(device_attach, pci_attach),
136 DEVMETHOD(device_detach, bus_generic_detach),
137 DEVMETHOD(device_shutdown, bus_generic_shutdown),
138 DEVMETHOD(device_suspend, pci_suspend),
139 DEVMETHOD(device_resume, pci_resume),
142 DEVMETHOD(bus_print_child, pci_print_child),
143 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
144 DEVMETHOD(bus_read_ivar, pci_read_ivar),
145 DEVMETHOD(bus_write_ivar, pci_write_ivar),
146 DEVMETHOD(bus_driver_added, pci_driver_added),
147 DEVMETHOD(bus_child_detached, pci_child_detached),
148 DEVMETHOD(bus_setup_intr, pci_setup_intr),
149 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
151 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
152 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
153 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
154 DEVMETHOD(bus_delete_resource, pci_delete_resource),
155 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
156 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
157 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
158 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
159 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
160 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
163 DEVMETHOD(pci_read_config, pci_read_config_method),
164 DEVMETHOD(pci_write_config, pci_write_config_method),
165 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
166 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
167 DEVMETHOD(pci_enable_io, pci_enable_io_method),
168 DEVMETHOD(pci_disable_io, pci_disable_io_method),
169 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
170 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
171 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
172 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
173 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
174 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
175 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
176 DEVMETHOD(pci_alloc_msix_vector, pci_alloc_msix_vector_method),
177 DEVMETHOD(pci_release_msi, pci_release_msi_method),
178 DEVMETHOD(pci_msi_count, pci_msi_count_method),
179 DEVMETHOD(pci_msix_count, pci_msix_count_method),
184 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
186 static devclass_t pci_devclass;
187 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL);
188 MODULE_VERSION(pci, 1);
190 static char *pci_vendordata;
191 static size_t pci_vendordata_size;
194 static const struct pci_read_cap {
196 pci_read_cap_t read_cap;
197 } pci_read_caps[] = {
198 { PCIY_PMG, pci_read_cap_pmgt },
199 { PCIY_HT, pci_read_cap_ht },
200 { PCIY_MSI, pci_read_cap_msi },
201 { PCIY_MSIX, pci_read_cap_msix },
202 { PCIY_VPD, pci_read_cap_vpd },
203 { PCIY_SUBVENDOR, pci_read_cap_subvendor },
204 { PCIY_PCIX, pci_read_cap_pcix },
205 { PCIY_EXPRESS, pci_read_cap_express },
206 { 0, NULL } /* required last entry */
210 uint32_t devid; /* Vendor/device of the card */
212 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
213 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
218 struct pci_quirk pci_quirks[] = {
219 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
220 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
221 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
222 /* As does the Serverworks OSB4 (the SMBus mapping register) */
223 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
226 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
227 * or the CMIC-SL (AKA ServerWorks GC_LE).
229 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
230 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
233 * MSI doesn't work on earlier Intel chipsets including
234 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
236 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
237 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
238 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
239 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
240 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
241 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
242 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
245 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
248 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
253 /* map register information */
254 #define PCI_MAPMEM 0x01 /* memory map */
255 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
256 #define PCI_MAPPORT 0x04 /* port map */
258 struct devlist pci_devq;
259 uint32_t pci_generation;
260 uint32_t pci_numdevs = 0;
261 static int pcie_chipset, pcix_chipset;
264 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
266 static int pci_enable_io_modes = 1;
267 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
268 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
269 &pci_enable_io_modes, 1,
270 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
271 enable these bits correctly. We'd like to do this all the time, but there\n\
272 are some peripherals that this causes problems with.");
274 static int pci_do_power_nodriver = 0;
275 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
276 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
277 &pci_do_power_nodriver, 0,
278 "Place a function into D3 state when no driver attaches to it. 0 means\n\
279 disable. 1 means conservatively place devices into D3 state. 2 means\n\
280 aggressively place devices into D3 state. 3 means put absolutely everything\n\
283 static int pci_do_power_resume = 1;
284 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
285 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
286 &pci_do_power_resume, 1,
287 "Transition from D3 -> D0 on resume.");
289 static int pci_do_msi = 1;
290 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
291 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
292 "Enable support for MSI interrupts");
294 static int pci_do_msix = 0;
296 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
297 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
298 "Enable support for MSI-X interrupts");
301 static int pci_honor_msi_blacklist = 1;
302 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
303 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
304 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
306 static int pci_msi_cpuid;
308 /* Find a device_t by bus/slot/function in domain 0 */
311 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
314 return (pci_find_dbsf(0, bus, slot, func));
317 /* Find a device_t by domain/bus/slot/function */
320 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
322 struct pci_devinfo *dinfo;
324 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
325 if ((dinfo->cfg.domain == domain) &&
326 (dinfo->cfg.bus == bus) &&
327 (dinfo->cfg.slot == slot) &&
328 (dinfo->cfg.func == func)) {
329 return (dinfo->cfg.dev);
336 /* Find a device_t by vendor/device ID */
339 pci_find_device(uint16_t vendor, uint16_t device)
341 struct pci_devinfo *dinfo;
343 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
344 if ((dinfo->cfg.vendor == vendor) &&
345 (dinfo->cfg.device == device)) {
346 return (dinfo->cfg.dev);
353 /* return base address of memory or port map */
356 pci_mapbase(uint32_t mapreg)
359 if (PCI_BAR_MEM(mapreg))
360 return (mapreg & PCIM_BAR_MEM_BASE);
362 return (mapreg & PCIM_BAR_IO_BASE);
365 /* return map type of memory or port map */
368 pci_maptype(unsigned mapreg)
371 if (PCI_BAR_IO(mapreg))
373 if (mapreg & PCIM_BAR_MEM_PREFETCH)
374 return ("Prefetchable Memory");
378 /* return log2 of map size decoded for memory or port map */
381 pci_mapsize(uint32_t testval)
385 testval = pci_mapbase(testval);
388 while ((testval & 1) == 0)
397 /* return log2 of address range supported by map register */
400 pci_maprange(unsigned mapreg)
404 if (PCI_BAR_IO(mapreg))
407 switch (mapreg & PCIM_BAR_MEM_TYPE) {
408 case PCIM_BAR_MEM_32:
411 case PCIM_BAR_MEM_1MB:
414 case PCIM_BAR_MEM_64:
421 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
424 pci_fixancient(pcicfgregs *cfg)
426 if (cfg->hdrtype != 0)
429 /* PCI to PCI bridges use header type 1 */
430 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
434 /* extract header type specific config data */
437 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
439 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
440 switch (cfg->hdrtype) {
442 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
443 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
444 cfg->nummaps = PCI_MAXMAPS_0;
447 cfg->nummaps = PCI_MAXMAPS_1;
449 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
453 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
454 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
455 cfg->nummaps = PCI_MAXMAPS_2;
457 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
464 /* read configuration header into pcicfgregs structure */
466 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
468 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
469 pcicfgregs *cfg = NULL;
470 struct pci_devinfo *devlist_entry;
471 struct devlist *devlist_head;
473 devlist_head = &pci_devq;
475 devlist_entry = NULL;
477 if (REG(PCIR_DEVVENDOR, 4) != -1) {
478 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
480 cfg = &devlist_entry->cfg;
486 cfg->vendor = REG(PCIR_VENDOR, 2);
487 cfg->device = REG(PCIR_DEVICE, 2);
488 cfg->cmdreg = REG(PCIR_COMMAND, 2);
489 cfg->statreg = REG(PCIR_STATUS, 2);
490 cfg->baseclass = REG(PCIR_CLASS, 1);
491 cfg->subclass = REG(PCIR_SUBCLASS, 1);
492 cfg->progif = REG(PCIR_PROGIF, 1);
493 cfg->revid = REG(PCIR_REVID, 1);
494 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
495 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
496 cfg->lattimer = REG(PCIR_LATTIMER, 1);
497 cfg->intpin = REG(PCIR_INTPIN, 1);
498 cfg->intline = REG(PCIR_INTLINE, 1);
500 cfg->mingnt = REG(PCIR_MINGNT, 1);
501 cfg->maxlat = REG(PCIR_MAXLAT, 1);
503 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
504 cfg->hdrtype &= ~PCIM_MFDEV;
507 pci_hdrtypedata(pcib, b, s, f, cfg);
509 pci_read_capabilities(pcib, cfg);
511 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
513 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
514 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
515 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
516 devlist_entry->conf.pc_sel.pc_func = cfg->func;
517 devlist_entry->conf.pc_hdr = cfg->hdrtype;
519 devlist_entry->conf.pc_subvendor = cfg->subvendor;
520 devlist_entry->conf.pc_subdevice = cfg->subdevice;
521 devlist_entry->conf.pc_vendor = cfg->vendor;
522 devlist_entry->conf.pc_device = cfg->device;
524 devlist_entry->conf.pc_class = cfg->baseclass;
525 devlist_entry->conf.pc_subclass = cfg->subclass;
526 devlist_entry->conf.pc_progif = cfg->progif;
527 devlist_entry->conf.pc_revid = cfg->revid;
532 return (devlist_entry);
537 pci_fixup_nextptr(int *nextptr0)
539 int nextptr = *nextptr0;
541 /* "Next pointer" is only one byte */
542 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
546 * PCI local bus spec 3.0:
548 * "... The bottom two bits of all pointers are reserved
549 * and must be implemented as 00b although software must
550 * mask them to allow for future uses of these bits ..."
553 kprintf("Illegal PCI extended capability "
554 "offset, fixup 0x%02x -> 0x%02x\n",
555 nextptr, nextptr & ~0x3);
561 if (nextptr < 0x40) {
563 kprintf("Illegal PCI extended capability "
564 "offset 0x%02x", nextptr);
572 pci_read_cap_pmgt(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
575 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
577 struct pcicfg_pp *pp = &cfg->pp;
582 pp->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
583 pp->pp_status = ptr + PCIR_POWER_STATUS;
584 pp->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
586 if ((nextptr - ptr) > PCIR_POWER_DATA) {
589 * We should write to data_select and read back from
590 * data_scale to determine whether data register is
594 pp->pp_data = ptr + PCIR_POWER_DATA;
604 pci_read_cap_ht(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
606 #if defined(__i386__) || defined(__x86_64__)
609 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
611 struct pcicfg_ht *ht = &cfg->ht;
615 /* Determine HT-specific capability type. */
616 val = REG(ptr + PCIR_HT_COMMAND, 2);
618 if ((val & 0xe000) == PCIM_HTCAP_SLAVE)
619 cfg->ht.ht_slave = ptr;
621 if ((val & PCIM_HTCMD_CAP_MASK) != PCIM_HTCAP_MSI_MAPPING)
624 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
625 /* Sanity check the mapping window. */
626 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 4);
628 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 4);
629 if (addr != MSI_X86_ADDR_BASE) {
630 device_printf(pcib, "HT Bridge at pci%d:%d:%d:%d "
631 "has non-default MSI window 0x%llx\n",
632 cfg->domain, cfg->bus, cfg->slot, cfg->func,
636 addr = MSI_X86_ADDR_BASE;
640 ht->ht_msictrl = val;
641 ht->ht_msiaddr = addr;
645 #endif /* __i386__ || __x86_64__ */
649 pci_read_cap_msi(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
652 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
654 struct pcicfg_msi *msi = &cfg->msi;
656 msi->msi_location = ptr;
657 msi->msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
658 msi->msi_msgnum = 1 << ((msi->msi_ctrl & PCIM_MSICTRL_MMC_MASK) >> 1);
664 pci_read_cap_msix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
667 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
669 struct pcicfg_msix *msix = &cfg->msix;
672 msix->msix_location = ptr;
673 msix->msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
674 msix->msix_msgnum = (msix->msix_ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
676 val = REG(ptr + PCIR_MSIX_TABLE, 4);
677 msix->msix_table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
678 msix->msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
680 val = REG(ptr + PCIR_MSIX_PBA, 4);
681 msix->msix_pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
682 msix->msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
688 pci_read_cap_vpd(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
690 cfg->vpd.vpd_reg = ptr;
694 pci_read_cap_subvendor(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
697 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
699 /* Should always be true. */
700 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
703 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
704 cfg->subvendor = val & 0xffff;
705 cfg->subdevice = val >> 16;
712 pci_read_cap_pcix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
715 * Assume we have a PCI-X chipset if we have
716 * at least one PCI-PCI bridge with a PCI-X
717 * capability. Note that some systems with
718 * PCI-express or HT chipsets might match on
719 * this check as well.
721 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
724 cfg->pcix.pcix_ptr = ptr;
728 pcie_slotimpl(const pcicfgregs *cfg)
730 const struct pcicfg_expr *expr = &cfg->expr;
734 * Only version 1 can be parsed currently
736 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
740 * - Slot implemented bit is meaningful iff current port is
741 * root port or down stream port.
742 * - Testing for root port or down stream port is meanningful
743 * iff PCI configure has type 1 header.
746 if (cfg->hdrtype != 1)
749 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
750 if (port_type != PCIE_ROOT_PORT && port_type != PCIE_DOWN_STREAM_PORT)
753 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
760 pci_read_cap_express(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
763 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
765 struct pcicfg_expr *expr = &cfg->expr;
768 * Assume we have a PCI-express chipset if we have
769 * at least one PCI-express device.
773 expr->expr_ptr = ptr;
774 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2);
777 * Only version 1 can be parsed currently
779 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
783 * Read slot capabilities. Slot capabilities exists iff
784 * current port's slot is implemented
786 if (pcie_slotimpl(cfg))
787 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4);
793 pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
795 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
796 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
801 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
802 /* No capabilities */
806 switch (cfg->hdrtype & PCIM_HDRTYPE) {
809 ptrptr = PCIR_CAP_PTR;
812 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
815 return; /* no capabilities support */
817 nextptr = REG(ptrptr, 1); /* sanity check? */
820 * Read capability entries.
822 while (pci_fixup_nextptr(&nextptr)) {
823 const struct pci_read_cap *rc;
826 /* Find the next entry */
827 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
829 /* Process this entry */
830 val = REG(ptr + PCICAP_ID, 1);
831 for (rc = pci_read_caps; rc->read_cap != NULL; ++rc) {
832 if (rc->cap == val) {
833 rc->read_cap(pcib, ptr, nextptr, cfg);
839 #if defined(__i386__) || defined(__x86_64__)
841 * Enable the MSI mapping window for all HyperTransport
842 * slaves. PCI-PCI bridges have their windows enabled via
845 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 &&
846 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
848 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n",
849 cfg->domain, cfg->bus, cfg->slot, cfg->func);
850 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
851 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl,
856 /* REG and WREG use carry through to next functions */
860 * PCI Vital Product Data
863 #define PCI_VPD_TIMEOUT 1000000
866 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
868 int count = PCI_VPD_TIMEOUT;
870 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
872 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
874 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
877 DELAY(1); /* limit looping */
879 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
886 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
888 int count = PCI_VPD_TIMEOUT;
890 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
892 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
893 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
894 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
897 DELAY(1); /* limit looping */
904 #undef PCI_VPD_TIMEOUT
906 struct vpd_readstate {
916 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
921 if (vrs->bytesinval == 0) {
922 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
924 vrs->val = le32toh(reg);
926 byte = vrs->val & 0xff;
929 vrs->val = vrs->val >> 8;
930 byte = vrs->val & 0xff;
940 pcie_slot_implemented(device_t dev)
942 struct pci_devinfo *dinfo = device_get_ivars(dev);
944 return pcie_slotimpl(&dinfo->cfg);
948 pcie_set_max_readrq(device_t dev, uint16_t rqsize)
953 rqsize &= PCIEM_DEVCTL_MAX_READRQ_MASK;
954 if (rqsize > PCIEM_DEVCTL_MAX_READRQ_4096) {
955 panic("%s: invalid max read request size 0x%02x\n",
956 device_get_nameunit(dev), rqsize);
959 expr_ptr = pci_get_pciecap_ptr(dev);
961 panic("%s: not PCIe device\n", device_get_nameunit(dev));
963 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
964 if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) != rqsize) {
966 device_printf(dev, "adjust device control 0x%04x", val);
968 val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK;
970 pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2);
973 kprintf(" -> 0x%04x\n", val);
978 pcie_get_max_readrq(device_t dev)
983 expr_ptr = pci_get_pciecap_ptr(dev);
985 panic("%s: not PCIe device\n", device_get_nameunit(dev));
987 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
988 return (val & PCIEM_DEVCTL_MAX_READRQ_MASK);
992 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
994 struct vpd_readstate vrs;
999 int alloc, off; /* alloc/off for RO/W arrays */
1005 /* init vpd reader */
1013 name = remain = i = 0; /* shut up stupid gcc */
1014 alloc = off = 0; /* shut up stupid gcc */
1015 dflen = 0; /* shut up stupid gcc */
1017 while (state >= 0) {
1018 if (vpd_nextbyte(&vrs, &byte)) {
1023 kprintf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
1024 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
1025 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
1028 case 0: /* item name */
1030 if (vpd_nextbyte(&vrs, &byte2)) {
1035 if (vpd_nextbyte(&vrs, &byte2)) {
1039 remain |= byte2 << 8;
1040 if (remain > (0x7f*4 - vrs.off)) {
1043 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
1044 cfg->domain, cfg->bus, cfg->slot,
1049 remain = byte & 0x7;
1050 name = (byte >> 3) & 0xf;
1053 case 0x2: /* String */
1054 cfg->vpd.vpd_ident = kmalloc(remain + 1,
1055 M_DEVBUF, M_WAITOK);
1062 case 0x10: /* VPD-R */
1065 cfg->vpd.vpd_ros = kmalloc(alloc *
1066 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
1070 case 0x11: /* VPD-W */
1073 cfg->vpd.vpd_w = kmalloc(alloc *
1074 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
1078 default: /* Invalid data, abort */
1084 case 1: /* Identifier String */
1085 cfg->vpd.vpd_ident[i++] = byte;
1088 cfg->vpd.vpd_ident[i] = '\0';
1093 case 2: /* VPD-R Keyword Header */
1095 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1096 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
1097 M_DEVBUF, M_WAITOK | M_ZERO);
1099 cfg->vpd.vpd_ros[off].keyword[0] = byte;
1100 if (vpd_nextbyte(&vrs, &byte2)) {
1104 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
1105 if (vpd_nextbyte(&vrs, &byte2)) {
1111 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
1114 * if this happens, we can't trust the rest
1118 "pci%d:%d:%d:%d: bad keyword length: %d\n",
1119 cfg->domain, cfg->bus, cfg->slot,
1124 } else if (dflen == 0) {
1125 cfg->vpd.vpd_ros[off].value = kmalloc(1 *
1126 sizeof(*cfg->vpd.vpd_ros[off].value),
1127 M_DEVBUF, M_WAITOK);
1128 cfg->vpd.vpd_ros[off].value[0] = '\x00';
1130 cfg->vpd.vpd_ros[off].value = kmalloc(
1132 sizeof(*cfg->vpd.vpd_ros[off].value),
1133 M_DEVBUF, M_WAITOK);
1136 /* keep in sync w/ state 3's transistions */
1137 if (dflen == 0 && remain == 0)
1139 else if (dflen == 0)
1145 case 3: /* VPD-R Keyword Value */
1146 cfg->vpd.vpd_ros[off].value[i++] = byte;
1147 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1148 "RV", 2) == 0 && cksumvalid == -1) {
1154 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
1155 cfg->domain, cfg->bus,
1156 cfg->slot, cfg->func,
1165 /* keep in sync w/ state 2's transistions */
1167 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1168 if (dflen == 0 && remain == 0) {
1169 cfg->vpd.vpd_rocnt = off;
1170 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1171 off * sizeof(*cfg->vpd.vpd_ros),
1172 M_DEVBUF, M_WAITOK | M_ZERO);
1174 } else if (dflen == 0)
1184 case 5: /* VPD-W Keyword Header */
1186 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1187 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1188 M_DEVBUF, M_WAITOK | M_ZERO);
1190 cfg->vpd.vpd_w[off].keyword[0] = byte;
1191 if (vpd_nextbyte(&vrs, &byte2)) {
1195 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1196 if (vpd_nextbyte(&vrs, &byte2)) {
1200 cfg->vpd.vpd_w[off].len = dflen = byte2;
1201 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1202 cfg->vpd.vpd_w[off].value = kmalloc((dflen + 1) *
1203 sizeof(*cfg->vpd.vpd_w[off].value),
1204 M_DEVBUF, M_WAITOK);
1207 /* keep in sync w/ state 6's transistions */
1208 if (dflen == 0 && remain == 0)
1210 else if (dflen == 0)
1216 case 6: /* VPD-W Keyword Value */
1217 cfg->vpd.vpd_w[off].value[i++] = byte;
1220 /* keep in sync w/ state 5's transistions */
1222 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1223 if (dflen == 0 && remain == 0) {
1224 cfg->vpd.vpd_wcnt = off;
1225 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1226 off * sizeof(*cfg->vpd.vpd_w),
1227 M_DEVBUF, M_WAITOK | M_ZERO);
1229 } else if (dflen == 0)
1234 kprintf("pci%d:%d:%d:%d: invalid state: %d\n",
1235 cfg->domain, cfg->bus, cfg->slot, cfg->func,
1242 if (cksumvalid == 0 || state < -1) {
1243 /* read-only data bad, clean up */
1244 if (cfg->vpd.vpd_ros != NULL) {
1245 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1246 kfree(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1247 kfree(cfg->vpd.vpd_ros, M_DEVBUF);
1248 cfg->vpd.vpd_ros = NULL;
1252 /* I/O error, clean up */
1253 kprintf("pci%d:%d:%d:%d: failed to read VPD data.\n",
1254 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1255 if (cfg->vpd.vpd_ident != NULL) {
1256 kfree(cfg->vpd.vpd_ident, M_DEVBUF);
1257 cfg->vpd.vpd_ident = NULL;
1259 if (cfg->vpd.vpd_w != NULL) {
1260 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1261 kfree(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1262 kfree(cfg->vpd.vpd_w, M_DEVBUF);
1263 cfg->vpd.vpd_w = NULL;
1266 cfg->vpd.vpd_cached = 1;
1272 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1274 struct pci_devinfo *dinfo = device_get_ivars(child);
1275 pcicfgregs *cfg = &dinfo->cfg;
1277 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1278 pci_read_vpd(device_get_parent(dev), cfg);
1280 *identptr = cfg->vpd.vpd_ident;
1282 if (*identptr == NULL)
1289 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1292 struct pci_devinfo *dinfo = device_get_ivars(child);
1293 pcicfgregs *cfg = &dinfo->cfg;
1296 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1297 pci_read_vpd(device_get_parent(dev), cfg);
1299 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1300 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1301 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1302 *vptr = cfg->vpd.vpd_ros[i].value;
1305 if (i != cfg->vpd.vpd_rocnt)
1313 * Return the offset in configuration space of the requested extended
1314 * capability entry or 0 if the specified capability was not found.
1317 pci_find_extcap_method(device_t dev, device_t child, int capability,
1320 struct pci_devinfo *dinfo = device_get_ivars(child);
1321 pcicfgregs *cfg = &dinfo->cfg;
1326 * Check the CAP_LIST bit of the PCI status register first.
1328 status = pci_read_config(child, PCIR_STATUS, 2);
1329 if (!(status & PCIM_STATUS_CAPPRESENT))
1333 * Determine the start pointer of the capabilities list.
1335 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1341 ptr = PCIR_CAP_PTR_2;
1345 return (ENXIO); /* no extended capabilities support */
1347 ptr = pci_read_config(child, ptr, 1);
1350 * Traverse the capabilities list.
1353 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1358 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1365 * Support for MSI-X message interrupts.
1368 pci_setup_msix_vector(device_t dev, u_int index, uint64_t address,
1371 struct pci_devinfo *dinfo = device_get_ivars(dev);
1372 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1375 KASSERT(msix->msix_table_len > index, ("bogus index"));
1376 offset = msix->msix_table_offset + index * 16;
1377 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1378 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1379 bus_write_4(msix->msix_table_res, offset + 8, data);
1381 /* Enable MSI -> HT mapping. */
1382 pci_ht_map_msi(dev, address);
1386 pci_mask_msix_vector(device_t dev, u_int index)
1388 struct pci_devinfo *dinfo = device_get_ivars(dev);
1389 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1390 uint32_t offset, val;
1392 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1393 offset = msix->msix_table_offset + index * 16 + 12;
1394 val = bus_read_4(msix->msix_table_res, offset);
1395 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1396 val |= PCIM_MSIX_VCTRL_MASK;
1397 bus_write_4(msix->msix_table_res, offset, val);
1402 pci_unmask_msix_vector(device_t dev, u_int index)
1404 struct pci_devinfo *dinfo = device_get_ivars(dev);
1405 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1406 uint32_t offset, val;
1408 KASSERT(msix->msix_table_len > index, ("bogus index"));
1409 offset = msix->msix_table_offset + index * 16 + 12;
1410 val = bus_read_4(msix->msix_table_res, offset);
1411 if (val & PCIM_MSIX_VCTRL_MASK) {
1412 val &= ~PCIM_MSIX_VCTRL_MASK;
1413 bus_write_4(msix->msix_table_res, offset, val);
1418 pci_pending_msix_vector(device_t dev, u_int index)
1420 struct pci_devinfo *dinfo = device_get_ivars(dev);
1421 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1422 uint32_t offset, bit;
1424 KASSERT(msix->msix_table_res != NULL && msix->msix_pba_res != NULL,
1425 ("MSI-X is not setup yet\n"));
1427 KASSERT(msix->msix_table_len > index, ("bogus index"));
1428 offset = msix->msix_pba_offset + (index / 32) * 4;
1429 bit = 1 << index % 32;
1430 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1434 * Restore MSI-X registers and table during resume. If MSI-X is
1435 * enabled then walk the virtual table to restore the actual MSI-X
1439 pci_resume_msix(device_t dev)
1441 struct pci_devinfo *dinfo = device_get_ivars(dev);
1442 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1443 struct msix_table_entry *mte;
1444 struct msix_vector *mv;
1447 if (msix->msix_alloc > 0) {
1448 pci_mask_msix_allvectors(dev);
1450 /* Program any messages with at least one handler. */
1451 for (i = 0; i < msix->msix_table_len; i++) {
1452 mte = &msix->msix_table[i];
1453 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1455 mv = &msix->msix_vectors[mte->mte_vector - 1];
1456 pci_setup_msix_vector(dev, i, mv->mv_address,
1458 pci_unmask_msix_vector(dev, i);
1461 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1462 msix->msix_ctrl, 2);
1466 * Attempt to allocate one MSI-X message at the specified vector on cpuid.
1468 * After this function returns, the MSI-X's rid will be saved in rid0.
1471 pci_alloc_msix_vector_method(device_t dev, device_t child, u_int vector,
1472 int *rid0, int cpuid)
1474 struct pci_devinfo *dinfo = device_get_ivars(child);
1475 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1476 struct resource_list_entry *rle;
1477 int error, irq, rid;
1479 KASSERT(msix->msix_table_res != NULL &&
1480 msix->msix_pba_res != NULL, ("MSI-X is not setup yet\n"));
1481 KASSERT(cpuid >= 0 && cpuid < ncpus, ("invalid cpuid %d\n", cpuid));
1482 KASSERT(vector < msix->msix_msgnum,
1483 ("invalid MSI-X vector %u, total %d\n", vector, msix->msix_msgnum));
1486 device_printf(child,
1487 "attempting to allocate MSI-X #%u vector (%d supported)\n",
1488 vector, msix->msix_msgnum);
1491 /* Set rid according to vector number */
1494 /* Allocate a message. */
1495 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq, cpuid);
1498 resource_list_add(&dinfo->resources, SYS_RES_IRQ, rid,
1499 irq, irq, 1, cpuid);
1502 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
1503 device_printf(child, "using IRQ %lu for MSI-X on cpu%d\n",
1507 /* Update counts of alloc'd messages. */
1516 pci_release_msix(device_t dev, device_t child)
1518 struct pci_devinfo *dinfo = device_get_ivars(child);
1519 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1520 struct resource_list_entry *rle;
1523 /* Do we have any messages to release? */
1524 if (msix->msix_alloc == 0)
1527 /* Make sure none of the resources are allocated. */
1528 for (i = 0; i < msix->msix_table_len; i++) {
1529 if (msix->msix_table[i].mte_vector == 0)
1531 if (msix->msix_table[i].mte_handlers > 0)
1533 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1534 KASSERT(rle != NULL, ("missing resource"));
1535 if (rle->res != NULL)
1539 /* Update control register to disable MSI-X. */
1540 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1541 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1542 msix->msix_ctrl, 2);
1544 /* Free the resource list entries. */
1545 for (i = 0; i < msix->msix_table_len; i++) {
1546 if (msix->msix_table[i].mte_vector == 0)
1548 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1550 kfree(msix->msix_table, M_DEVBUF);
1551 msix->msix_table_len = 0;
1553 /* Release the IRQs. */
1554 for (i = 0; i < msix->msix_alloc; i++)
1555 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1556 msix->msix_vectors[i].mv_irq, -1 /* XXX */);
1557 kfree(msix->msix_vectors, M_DEVBUF);
1558 msix->msix_alloc = 0;
1564 * Return the max supported MSI-X messages this device supports.
1565 * Basically, assuming the MD code can alloc messages, this function
1566 * should return the maximum value that pci_alloc_msix() can return.
1567 * Thus, it is subject to the tunables, etc.
1570 pci_msix_count_method(device_t dev, device_t child)
1572 struct pci_devinfo *dinfo = device_get_ivars(child);
1573 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1575 if (pci_do_msix && msix->msix_location != 0)
1576 return (msix->msix_msgnum);
1581 pci_setup_msix(device_t dev)
1583 struct pci_devinfo *dinfo = device_get_ivars(dev);
1584 pcicfgregs *cfg = &dinfo->cfg;
1585 struct resource_list_entry *rle;
1586 struct resource *table_res, *pba_res;
1588 KASSERT(cfg->msix.msix_table_res == NULL &&
1589 cfg->msix.msix_pba_res == NULL, ("MSI-X has been setup yet\n"));
1591 /* If rid 0 is allocated, then fail. */
1592 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1593 if (rle != NULL && rle->res != NULL)
1596 /* Already have allocated MSIs? */
1597 if (cfg->msi.msi_alloc != 0)
1600 /* If MSI is blacklisted for this system, fail. */
1601 if (pci_msi_blacklisted())
1604 /* MSI-X capability present? */
1605 if (cfg->msix.msix_location == 0 || cfg->msix.msix_msgnum == 0 ||
1609 /* Make sure the appropriate BARs are mapped. */
1610 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1611 cfg->msix.msix_table_bar);
1612 if (rle == NULL || rle->res == NULL ||
1613 !(rman_get_flags(rle->res) & RF_ACTIVE))
1615 table_res = rle->res;
1616 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1617 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1618 cfg->msix.msix_pba_bar);
1619 if (rle == NULL || rle->res == NULL ||
1620 !(rman_get_flags(rle->res) & RF_ACTIVE))
1625 cfg->msix.msix_table_res = table_res;
1626 cfg->msix.msix_pba_res = pba_res;
1628 pci_mask_msix_allvectors(dev);
1634 pci_teardown_msix(device_t dev)
1636 struct pci_devinfo *dinfo = device_get_ivars(dev);
1637 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1639 KASSERT(msix->msix_table_res != NULL &&
1640 msix->msix_pba_res != NULL, ("MSI-X is not setup yet\n"));
1642 pci_mask_msix_allvectors(dev);
1644 msix->msix_table_res = NULL;
1645 msix->msix_pba_res = NULL;
1649 pci_enable_msix(device_t dev)
1651 struct pci_devinfo *dinfo = device_get_ivars(dev);
1652 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1654 KASSERT(msix->msix_table_res != NULL &&
1655 msix->msix_pba_res != NULL, ("MSI-X is not setup yet\n"));
1657 /* Update control register to enable MSI-X. */
1658 msix->msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1659 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1660 msix->msix_ctrl, 2);
1664 pci_disable_msix(device_t dev)
1666 struct pci_devinfo *dinfo = device_get_ivars(dev);
1667 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1669 KASSERT(msix->msix_table_res != NULL &&
1670 msix->msix_pba_res != NULL, ("MSI-X is not setup yet\n"));
1672 /* Disable MSI -> HT mapping. */
1673 pci_ht_map_msi(dev, 0);
1675 /* Update control register to disable MSI-X. */
1676 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1677 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1678 msix->msix_ctrl, 2);
1682 pci_mask_msix_allvectors(device_t dev)
1684 struct pci_devinfo *dinfo = device_get_ivars(dev);
1687 for (i = 0; i < dinfo->cfg.msix.msix_msgnum; ++i)
1688 pci_mask_msix_vector(dev, i);
1692 * HyperTransport MSI mapping control
1695 pci_ht_map_msi(device_t dev, uint64_t addr)
1697 struct pci_devinfo *dinfo = device_get_ivars(dev);
1698 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1703 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1704 ht->ht_msiaddr >> 20 == addr >> 20) {
1705 /* Enable MSI -> HT mapping. */
1706 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1707 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1711 if (!addr && (ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
1712 /* Disable MSI -> HT mapping. */
1713 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1714 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1720 * Support for MSI message signalled interrupts.
1723 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1725 struct pci_devinfo *dinfo = device_get_ivars(dev);
1726 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1728 /* Write data and address values. */
1729 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1730 address & 0xffffffff, 4);
1731 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1732 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1734 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1737 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1740 /* Enable MSI in the control register. */
1741 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1742 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1745 /* Enable MSI -> HT mapping. */
1746 pci_ht_map_msi(dev, address);
1750 pci_disable_msi(device_t dev)
1752 struct pci_devinfo *dinfo = device_get_ivars(dev);
1753 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1755 /* Disable MSI -> HT mapping. */
1756 pci_ht_map_msi(dev, 0);
1758 /* Disable MSI in the control register. */
1759 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1760 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1765 * Restore MSI registers during resume. If MSI is enabled then
1766 * restore the data and address registers in addition to the control
1770 pci_resume_msi(device_t dev)
1772 struct pci_devinfo *dinfo = device_get_ivars(dev);
1773 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1777 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1778 address = msi->msi_addr;
1779 data = msi->msi_data;
1780 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1781 address & 0xffffffff, 4);
1782 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1783 pci_write_config(dev, msi->msi_location +
1784 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1785 pci_write_config(dev, msi->msi_location +
1786 PCIR_MSI_DATA_64BIT, data, 2);
1788 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1791 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1796 * Returns true if the specified device is blacklisted because MSI
1800 pci_msi_device_blacklisted(device_t dev)
1802 struct pci_quirk *q;
1804 if (!pci_honor_msi_blacklist)
1807 for (q = &pci_quirks[0]; q->devid; q++) {
1808 if (q->devid == pci_get_devid(dev) &&
1809 q->type == PCI_QUIRK_DISABLE_MSI)
1816 * Determine if MSI is blacklisted globally on this sytem. Currently,
1817 * we just check for blacklisted chipsets as represented by the
1818 * host-PCI bridge at device 0:0:0. In the future, it may become
1819 * necessary to check other system attributes, such as the kenv values
1820 * that give the motherboard manufacturer and model number.
1823 pci_msi_blacklisted(void)
1827 if (!pci_honor_msi_blacklist)
1830 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
1831 if (!(pcie_chipset || pcix_chipset))
1834 dev = pci_find_bsf(0, 0, 0);
1836 return (pci_msi_device_blacklisted(dev));
1841 * Attempt to allocate count MSI messages on start_cpuid.
1843 * If start_cpuid < 0, then the MSI messages' target CPU will be
1844 * selected automaticly.
1846 * If the caller explicitly specified the MSI messages' target CPU,
1847 * i.e. start_cpuid >= 0, then we will try to allocate the count MSI
1848 * messages on the specified CPU, if the allocation fails due to MD
1849 * does not have enough vectors (EMSGSIZE), then we will try next
1850 * available CPU, until the allocation fails on all CPUs.
1852 * EMSGSIZE will be returned, if all available CPUs does not have
1853 * enough vectors for the requested amount of MSI messages. Caller
1854 * should either reduce the amount of MSI messages to be requested,
1855 * or simply giving up using MSI.
1857 * The available SYS_RES_IRQ resources' rids, which are >= 1, are
1858 * returned in 'rid' array, if the allocation succeeds.
1861 pci_alloc_msi_method(device_t dev, device_t child, int *rid, int count,
1864 struct pci_devinfo *dinfo = device_get_ivars(child);
1865 pcicfgregs *cfg = &dinfo->cfg;
1866 struct resource_list_entry *rle;
1867 int error, i, irqs[32], cpuid = 0;
1870 KASSERT(count != 0 && count <= 32 && powerof2(count),
1871 ("invalid MSI count %d\n", count));
1872 KASSERT(start_cpuid < ncpus, ("invalid cpuid %d\n", start_cpuid));
1874 /* If rid 0 is allocated, then fail. */
1875 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1876 if (rle != NULL && rle->res != NULL)
1879 /* Already have allocated messages? */
1880 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1883 /* If MSI is blacklisted for this system, fail. */
1884 if (pci_msi_blacklisted())
1887 /* MSI capability present? */
1888 if (cfg->msi.msi_location == 0 || cfg->msi.msi_msgnum == 0 ||
1892 KASSERT(count <= cfg->msi.msi_msgnum, ("large MSI count %d, max %d\n",
1893 count, cfg->msi.msi_msgnum));
1896 device_printf(child,
1897 "attempting to allocate %d MSI vectors (%d supported)\n",
1898 count, cfg->msi.msi_msgnum);
1901 if (start_cpuid < 0)
1902 start_cpuid = atomic_fetchadd_int(&pci_msi_cpuid, 1) % ncpus;
1905 for (i = 0; i < ncpus; ++i) {
1906 cpuid = (start_cpuid + i) % ncpus;
1908 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, count,
1909 cfg->msi.msi_msgnum, irqs, cpuid);
1912 else if (error != EMSGSIZE)
1919 * We now have N messages mapped onto SYS_RES_IRQ resources in
1920 * the irqs[] array, so add new resources starting at rid 1.
1922 for (i = 0; i < count; i++) {
1924 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
1925 irqs[i], irqs[i], 1, cpuid);
1930 device_printf(child, "using IRQ %d on cpu%d for MSI\n",
1936 * Be fancy and try to print contiguous runs
1937 * of IRQ values as ranges. 'run' is true if
1938 * we are in a range.
1940 device_printf(child, "using IRQs %d", irqs[0]);
1942 for (i = 1; i < count; i++) {
1944 /* Still in a run? */
1945 if (irqs[i] == irqs[i - 1] + 1) {
1950 /* Finish previous range. */
1952 kprintf("-%d", irqs[i - 1]);
1956 /* Start new range. */
1957 kprintf(",%d", irqs[i]);
1960 /* Unfinished range? */
1962 kprintf("-%d", irqs[count - 1]);
1963 kprintf(" for MSI on cpu%d\n", cpuid);
1967 /* Update control register with count. */
1968 ctrl = cfg->msi.msi_ctrl;
1969 ctrl &= ~PCIM_MSICTRL_MME_MASK;
1970 ctrl |= (ffs(count) - 1) << 4;
1971 cfg->msi.msi_ctrl = ctrl;
1972 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
1974 /* Update counts of alloc'd messages. */
1975 cfg->msi.msi_alloc = count;
1976 cfg->msi.msi_handlers = 0;
1980 /* Release the MSI messages associated with this device. */
1982 pci_release_msi_method(device_t dev, device_t child)
1984 struct pci_devinfo *dinfo = device_get_ivars(child);
1985 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1986 struct resource_list_entry *rle;
1987 int i, irqs[32], cpuid = -1;
1989 /* Do we have any messages to release? */
1990 if (msi->msi_alloc == 0)
1992 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
1994 /* Make sure none of the resources are allocated. */
1995 if (msi->msi_handlers > 0)
1997 for (i = 0; i < msi->msi_alloc; i++) {
1998 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1999 KASSERT(rle != NULL, ("missing MSI resource"));
2000 if (rle->res != NULL)
2004 KASSERT(cpuid >= 0 && cpuid < ncpus,
2005 ("invalid MSI target cpuid %d\n", cpuid));
2007 KASSERT(rle->cpuid == cpuid,
2008 ("MSI targets different cpus, "
2009 "was cpu%d, now cpu%d", cpuid, rle->cpuid));
2011 irqs[i] = rle->start;
2014 /* Update control register with 0 count. */
2015 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2016 ("%s: MSI still enabled", __func__));
2017 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2018 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2021 /* Release the messages. */
2022 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs,
2024 for (i = 0; i < msi->msi_alloc; i++)
2025 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2027 /* Update alloc count. */
2035 * Return the max supported MSI messages this device supports.
2036 * Basically, assuming the MD code can alloc messages, this function
2037 * should return the maximum value that pci_alloc_msi() can return.
2038 * Thus, it is subject to the tunables, etc.
2041 pci_msi_count_method(device_t dev, device_t child)
2043 struct pci_devinfo *dinfo = device_get_ivars(child);
2044 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2046 if (pci_do_msi && msi->msi_location != 0)
2047 return (msi->msi_msgnum);
2051 /* kfree pcicfgregs structure and all depending data structures */
2054 pci_freecfg(struct pci_devinfo *dinfo)
2056 struct devlist *devlist_head;
2059 devlist_head = &pci_devq;
2061 if (dinfo->cfg.vpd.vpd_reg) {
2062 kfree(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2063 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2064 kfree(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2065 kfree(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2066 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2067 kfree(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2068 kfree(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2070 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2071 kfree(dinfo, M_DEVBUF);
2073 /* increment the generation count */
2076 /* we're losing one device */
2082 * PCI power manangement
2085 pci_set_powerstate_method(device_t dev, device_t child, int state)
2087 struct pci_devinfo *dinfo = device_get_ivars(child);
2088 pcicfgregs *cfg = &dinfo->cfg;
2090 int result, oldstate, highest, delay;
2092 if (cfg->pp.pp_cap == 0)
2093 return (EOPNOTSUPP);
2096 * Optimize a no state change request away. While it would be OK to
2097 * write to the hardware in theory, some devices have shown odd
2098 * behavior when going from D3 -> D3.
2100 oldstate = pci_get_powerstate(child);
2101 if (oldstate == state)
2105 * The PCI power management specification states that after a state
2106 * transition between PCI power states, system software must
2107 * guarantee a minimal delay before the function accesses the device.
2108 * Compute the worst case delay that we need to guarantee before we
2109 * access the device. Many devices will be responsive much more
2110 * quickly than this delay, but there are some that don't respond
2111 * instantly to state changes. Transitions to/from D3 state require
2112 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2113 * is done below with DELAY rather than a sleeper function because
2114 * this function can be called from contexts where we cannot sleep.
2116 highest = (oldstate > state) ? oldstate : state;
2117 if (highest == PCI_POWERSTATE_D3)
2119 else if (highest == PCI_POWERSTATE_D2)
2123 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2124 & ~PCIM_PSTAT_DMASK;
2127 case PCI_POWERSTATE_D0:
2128 status |= PCIM_PSTAT_D0;
2130 case PCI_POWERSTATE_D1:
2131 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2132 return (EOPNOTSUPP);
2133 status |= PCIM_PSTAT_D1;
2135 case PCI_POWERSTATE_D2:
2136 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2137 return (EOPNOTSUPP);
2138 status |= PCIM_PSTAT_D2;
2140 case PCI_POWERSTATE_D3:
2141 status |= PCIM_PSTAT_D3;
2149 "pci%d:%d:%d:%d: Transition from D%d to D%d\n",
2150 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2151 dinfo->cfg.func, oldstate, state);
2153 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2160 pci_get_powerstate_method(device_t dev, device_t child)
2162 struct pci_devinfo *dinfo = device_get_ivars(child);
2163 pcicfgregs *cfg = &dinfo->cfg;
2167 if (cfg->pp.pp_cap != 0) {
2168 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2169 switch (status & PCIM_PSTAT_DMASK) {
2171 result = PCI_POWERSTATE_D0;
2174 result = PCI_POWERSTATE_D1;
2177 result = PCI_POWERSTATE_D2;
2180 result = PCI_POWERSTATE_D3;
2183 result = PCI_POWERSTATE_UNKNOWN;
2187 /* No support, device is always at D0 */
2188 result = PCI_POWERSTATE_D0;
2194 * Some convenience functions for PCI device drivers.
2197 static __inline void
2198 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2202 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2204 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2207 static __inline void
2208 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2212 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2214 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2218 pci_enable_busmaster_method(device_t dev, device_t child)
2220 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2225 pci_disable_busmaster_method(device_t dev, device_t child)
2227 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2232 pci_enable_io_method(device_t dev, device_t child, int space)
2242 case SYS_RES_IOPORT:
2243 bit = PCIM_CMD_PORTEN;
2246 case SYS_RES_MEMORY:
2247 bit = PCIM_CMD_MEMEN;
2253 pci_set_command_bit(dev, child, bit);
2254 /* Some devices seem to need a brief stall here, what do to? */
2255 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2258 device_printf(child, "failed to enable %s mapping!\n", error);
2263 pci_disable_io_method(device_t dev, device_t child, int space)
2273 case SYS_RES_IOPORT:
2274 bit = PCIM_CMD_PORTEN;
2277 case SYS_RES_MEMORY:
2278 bit = PCIM_CMD_MEMEN;
2284 pci_clear_command_bit(dev, child, bit);
2285 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2286 if (command & bit) {
2287 device_printf(child, "failed to disable %s mapping!\n", error);
2294 * New style pci driver. Parent device is either a pci-host-bridge or a
2295 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2299 pci_print_verbose(struct pci_devinfo *dinfo)
2303 pcicfgregs *cfg = &dinfo->cfg;
2305 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2306 cfg->vendor, cfg->device, cfg->revid);
2307 kprintf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2308 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2309 kprintf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2310 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2312 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2313 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2314 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2315 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2316 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2317 if (cfg->intpin > 0)
2318 kprintf("\tintpin=%c, irq=%d\n",
2319 cfg->intpin +'a' -1, cfg->intline);
2320 if (cfg->pp.pp_cap) {
2323 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2324 kprintf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2325 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2326 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2327 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2328 status & PCIM_PSTAT_DMASK);
2330 if (cfg->msi.msi_location) {
2333 ctrl = cfg->msi.msi_ctrl;
2334 kprintf("\tMSI supports %d message%s%s%s\n",
2335 cfg->msi.msi_msgnum,
2336 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2337 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2338 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2340 if (cfg->msix.msix_location) {
2341 kprintf("\tMSI-X supports %d message%s ",
2342 cfg->msix.msix_msgnum,
2343 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2344 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2345 kprintf("in map 0x%x\n",
2346 cfg->msix.msix_table_bar);
2348 kprintf("in maps 0x%x and 0x%x\n",
2349 cfg->msix.msix_table_bar,
2350 cfg->msix.msix_pba_bar);
2352 pci_print_verbose_expr(cfg);
2357 pci_print_verbose_expr(const pcicfgregs *cfg)
2359 const struct pcicfg_expr *expr = &cfg->expr;
2360 const char *port_name;
2366 if (expr->expr_ptr == 0) /* No PCI Express capability */
2369 kprintf("\tPCI Express ver.%d cap=0x%04x",
2370 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap);
2371 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
2374 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
2376 switch (port_type) {
2377 case PCIE_END_POINT:
2378 port_name = "DEVICE";
2380 case PCIE_LEG_END_POINT:
2381 port_name = "LEGDEV";
2383 case PCIE_ROOT_PORT:
2386 case PCIE_UP_STREAM_PORT:
2387 port_name = "UPSTREAM";
2389 case PCIE_DOWN_STREAM_PORT:
2390 port_name = "DOWNSTRM";
2392 case PCIE_PCIE2PCI_BRIDGE:
2393 port_name = "PCIE2PCI";
2395 case PCIE_PCI2PCIE_BRIDGE:
2396 port_name = "PCI2PCIE";
2402 if ((port_type == PCIE_ROOT_PORT ||
2403 port_type == PCIE_DOWN_STREAM_PORT) &&
2404 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
2406 if (port_name != NULL)
2407 kprintf("[%s]", port_name);
2409 if (pcie_slotimpl(cfg)) {
2410 kprintf(", slotcap=0x%08x", expr->expr_slotcap);
2411 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP)
2412 kprintf("[HOTPLUG]");
2419 pci_porten(device_t pcib, int b, int s, int f)
2421 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2422 & PCIM_CMD_PORTEN) != 0;
2426 pci_memen(device_t pcib, int b, int s, int f)
2428 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2429 & PCIM_CMD_MEMEN) != 0;
2433 * Add a resource based on a pci map register. Return 1 if the map
2434 * register is a 32bit map register or 2 if it is a 64bit register.
2437 pci_add_map(device_t pcib, device_t bus, device_t dev,
2438 int b, int s, int f, int reg, struct resource_list *rl, int force,
2443 pci_addr_t start, end, count;
2450 struct resource *res;
2452 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2453 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
2454 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2455 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
2457 if (PCI_BAR_MEM(map)) {
2458 type = SYS_RES_MEMORY;
2459 if (map & PCIM_BAR_MEM_PREFETCH)
2462 type = SYS_RES_IOPORT;
2463 ln2size = pci_mapsize(testval);
2464 ln2range = pci_maprange(testval);
2465 base = pci_mapbase(map);
2466 barlen = ln2range == 64 ? 2 : 1;
2469 * For I/O registers, if bottom bit is set, and the next bit up
2470 * isn't clear, we know we have a BAR that doesn't conform to the
2471 * spec, so ignore it. Also, sanity check the size of the data
2472 * areas to the type of memory involved. Memory must be at least
2473 * 16 bytes in size, while I/O ranges must be at least 4.
2475 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2477 if ((type == SYS_RES_MEMORY && ln2size < 4) ||
2478 (type == SYS_RES_IOPORT && ln2size < 2))
2482 /* Read the other half of a 64bit map register */
2483 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
2485 kprintf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2486 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
2487 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2488 kprintf(", port disabled\n");
2489 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2490 kprintf(", memory disabled\n");
2492 kprintf(", enabled\n");
2496 * If base is 0, then we have problems. It is best to ignore
2497 * such entries for the moment. These will be allocated later if
2498 * the driver specifically requests them. However, some
2499 * removable busses look better when all resources are allocated,
2500 * so allow '0' to be overriden.
2502 * Similarly treat maps whose values is the same as the test value
2503 * read back. These maps have had all f's written to them by the
2504 * BIOS in an attempt to disable the resources.
2506 if (!force && (base == 0 || map == testval))
2508 if ((u_long)base != base) {
2510 "pci%d:%d:%d:%d bar %#x too many address bits",
2511 pci_get_domain(dev), b, s, f, reg);
2516 * This code theoretically does the right thing, but has
2517 * undesirable side effects in some cases where peripherals
2518 * respond oddly to having these bits enabled. Let the user
2519 * be able to turn them off (since pci_enable_io_modes is 1 by
2522 if (pci_enable_io_modes) {
2523 /* Turn on resources that have been left off by a lazy BIOS */
2524 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
2525 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2526 cmd |= PCIM_CMD_PORTEN;
2527 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2529 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
2530 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2531 cmd |= PCIM_CMD_MEMEN;
2532 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2535 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2537 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2541 count = 1 << ln2size;
2542 if (base == 0 || base == pci_mapbase(testval)) {
2543 start = 0; /* Let the parent decide. */
2547 end = base + (1 << ln2size) - 1;
2549 resource_list_add(rl, type, reg, start, end, count, -1);
2552 * Try to allocate the resource for this BAR from our parent
2553 * so that this resource range is already reserved. The
2554 * driver for this device will later inherit this resource in
2555 * pci_alloc_resource().
2557 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
2558 prefetch ? RF_PREFETCHABLE : 0, -1);
2561 * If the allocation fails, delete the resource list
2562 * entry to force pci_alloc_resource() to allocate
2563 * resources from the parent.
2565 resource_list_delete(rl, type, reg);
2566 #ifdef PCI_BAR_CLEAR
2569 #else /* !PCI_BAR_CLEAR */
2571 * Don't clear BAR here. Some BIOS lists HPET as a
2572 * PCI function, clearing the BAR causes HPET timer
2576 kprintf("pci:%d:%d:%d: resource reservation failed "
2577 "%#jx - %#jx\n", b, s, f,
2578 (intmax_t)start, (intmax_t)end);
2581 #endif /* PCI_BAR_CLEAR */
2583 start = rman_get_start(res);
2585 pci_write_config(dev, reg, start, 4);
2587 pci_write_config(dev, reg + 4, start >> 32, 4);
2592 * For ATA devices we need to decide early what addressing mode to use.
2593 * Legacy demands that the primary and secondary ATA ports sits on the
2594 * same addresses that old ISA hardware did. This dictates that we use
2595 * those addresses and ignore the BAR's if we cannot set PCI native
2599 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
2600 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask)
2602 int rid, type, progif;
2604 /* if this device supports PCI native addressing use it */
2605 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2606 if ((progif & 0x8a) == 0x8a) {
2607 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2608 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2609 kprintf("Trying ATA native PCI addressing mode\n");
2610 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2614 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2615 type = SYS_RES_IOPORT;
2616 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2617 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force,
2618 prefetchmask & (1 << 0));
2619 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force,
2620 prefetchmask & (1 << 1));
2623 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8, -1);
2624 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
2627 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1, -1);
2628 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
2631 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2632 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force,
2633 prefetchmask & (1 << 2));
2634 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force,
2635 prefetchmask & (1 << 3));
2638 resource_list_add(rl, type, rid, 0x170, 0x177, 8, -1);
2639 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
2642 resource_list_add(rl, type, rid, 0x376, 0x376, 1, -1);
2643 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
2646 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force,
2647 prefetchmask & (1 << 4));
2648 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force,
2649 prefetchmask & (1 << 5));
2653 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2655 struct pci_devinfo *dinfo = device_get_ivars(dev);
2656 pcicfgregs *cfg = &dinfo->cfg;
2657 char tunable_name[64];
2660 /* Has to have an intpin to have an interrupt. */
2661 if (cfg->intpin == 0)
2664 /* Let the user override the IRQ with a tunable. */
2665 irq = PCI_INVALID_IRQ;
2666 ksnprintf(tunable_name, sizeof(tunable_name),
2667 "hw.pci%d.%d.%d.INT%c.irq",
2668 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2669 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2670 irq = PCI_INVALID_IRQ;
2673 * If we didn't get an IRQ via the tunable, then we either use the
2674 * IRQ value in the intline register or we ask the bus to route an
2675 * interrupt for us. If force_route is true, then we only use the
2676 * value in the intline register if the bus was unable to assign an
2679 if (!PCI_INTERRUPT_VALID(irq)) {
2680 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2681 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2682 if (!PCI_INTERRUPT_VALID(irq))
2686 /* If after all that we don't have an IRQ, just bail. */
2687 if (!PCI_INTERRUPT_VALID(irq))
2690 /* Update the config register if it changed. */
2691 if (irq != cfg->intline) {
2693 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2696 /* Add this IRQ as rid 0 interrupt resource. */
2697 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1,
2698 machintr_legacy_intr_cpuid(irq));
2702 pci_add_resources(device_t pcib, device_t bus, device_t dev, int force, uint32_t prefetchmask)
2704 struct pci_devinfo *dinfo = device_get_ivars(dev);
2705 pcicfgregs *cfg = &dinfo->cfg;
2706 struct resource_list *rl = &dinfo->resources;
2707 struct pci_quirk *q;
2714 /* ATA devices needs special map treatment */
2715 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2716 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
2717 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2718 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2719 !pci_read_config(dev, PCIR_BAR(2), 4))) )
2720 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask);
2722 for (i = 0; i < cfg->nummaps;)
2723 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
2724 rl, force, prefetchmask & (1 << i));
2727 * Add additional, quirked resources.
2729 for (q = &pci_quirks[0]; q->devid; q++) {
2730 if (q->devid == ((cfg->device << 16) | cfg->vendor)
2731 && q->type == PCI_QUIRK_MAP_REG)
2732 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl,
2736 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2738 * Try to re-route interrupts. Sometimes the BIOS or
2739 * firmware may leave bogus values in these registers.
2740 * If the re-route fails, then just stick with what we
2743 pci_assign_interrupt(bus, dev, 1);
2748 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
2750 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
2751 device_t pcib = device_get_parent(dev);
2752 struct pci_devinfo *dinfo;
2754 int s, f, pcifunchigh;
2757 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2758 ("dinfo_size too small"));
2759 maxslots = PCIB_MAXSLOTS(pcib);
2760 for (s = 0; s <= maxslots; s++) {
2764 hdrtype = REG(PCIR_HDRTYPE, 1);
2765 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2767 if (hdrtype & PCIM_MFDEV)
2768 pcifunchigh = PCI_FUNCMAX;
2769 for (f = 0; f <= pcifunchigh; f++) {
2770 dinfo = pci_read_device(pcib, domain, busno, s, f,
2772 if (dinfo != NULL) {
2773 pci_add_child(dev, dinfo);
2781 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2785 pcib = device_get_parent(bus);
2786 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2787 device_set_ivars(dinfo->cfg.dev, dinfo);
2788 resource_list_init(&dinfo->resources);
2789 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2790 pci_cfg_restore(dinfo->cfg.dev, dinfo);
2791 pci_print_verbose(dinfo);
2792 pci_add_resources(pcib, bus, dinfo->cfg.dev, 0, 0);
2796 pci_probe(device_t dev)
2798 device_set_desc(dev, "PCI bus");
2800 /* Allow other subclasses to override this driver. */
2805 pci_attach(device_t dev)
2810 * Since there can be multiple independantly numbered PCI
2811 * busses on systems with multiple PCI domains, we can't use
2812 * the unit number to decide which bus we are probing. We ask
2813 * the parent pcib what our domain and bus numbers are.
2815 domain = pcib_get_domain(dev);
2816 busno = pcib_get_bus(dev);
2818 device_printf(dev, "domain=%d, physical bus=%d\n",
2821 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
2823 return (bus_generic_attach(dev));
2827 pci_suspend(device_t dev)
2829 int dstate, error, i, numdevs;
2830 device_t acpi_dev, child, *devlist;
2831 struct pci_devinfo *dinfo;
2834 * Save the PCI configuration space for each child and set the
2835 * device in the appropriate power state for this sleep state.
2838 if (pci_do_power_resume)
2839 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2840 device_get_children(dev, &devlist, &numdevs);
2841 for (i = 0; i < numdevs; i++) {
2843 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2844 pci_cfg_save(child, dinfo, 0);
2847 /* Suspend devices before potentially powering them down. */
2848 error = bus_generic_suspend(dev);
2850 kfree(devlist, M_TEMP);
2855 * Always set the device to D3. If ACPI suggests a different
2856 * power state, use it instead. If ACPI is not present, the
2857 * firmware is responsible for managing device power. Skip
2858 * children who aren't attached since they are powered down
2859 * separately. Only manage type 0 devices for now.
2861 for (i = 0; acpi_dev && i < numdevs; i++) {
2863 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2864 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
2865 dstate = PCI_POWERSTATE_D3;
2866 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
2867 pci_set_powerstate(child, dstate);
2870 kfree(devlist, M_TEMP);
2875 pci_resume(device_t dev)
2878 device_t acpi_dev, child, *devlist;
2879 struct pci_devinfo *dinfo;
2882 * Set each child to D0 and restore its PCI configuration space.
2885 if (pci_do_power_resume)
2886 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2887 device_get_children(dev, &devlist, &numdevs);
2888 for (i = 0; i < numdevs; i++) {
2890 * Notify ACPI we're going to D0 but ignore the result. If
2891 * ACPI is not present, the firmware is responsible for
2892 * managing device power. Only manage type 0 devices for now.
2895 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2896 if (acpi_dev && device_is_attached(child) &&
2897 dinfo->cfg.hdrtype == 0) {
2898 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
2899 pci_set_powerstate(child, PCI_POWERSTATE_D0);
2902 /* Now the device is powered up, restore its config space. */
2903 pci_cfg_restore(child, dinfo);
2905 kfree(devlist, M_TEMP);
2906 return (bus_generic_resume(dev));
2910 pci_load_vendor_data(void)
2912 caddr_t vendordata, info;
2914 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
2915 info = preload_search_info(vendordata, MODINFO_ADDR);
2916 pci_vendordata = *(char **)info;
2917 info = preload_search_info(vendordata, MODINFO_SIZE);
2918 pci_vendordata_size = *(size_t *)info;
2919 /* terminate the database */
2920 pci_vendordata[pci_vendordata_size] = '\n';
2925 pci_driver_added(device_t dev, driver_t *driver)
2930 struct pci_devinfo *dinfo;
2934 device_printf(dev, "driver added\n");
2935 DEVICE_IDENTIFY(driver, dev);
2936 device_get_children(dev, &devlist, &numdevs);
2937 for (i = 0; i < numdevs; i++) {
2939 if (device_get_state(child) != DS_NOTPRESENT)
2941 dinfo = device_get_ivars(child);
2942 pci_print_verbose(dinfo);
2944 kprintf("pci%d:%d:%d:%d: reprobing on driver added\n",
2945 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2947 pci_cfg_restore(child, dinfo);
2948 if (device_probe_and_attach(child) != 0)
2949 pci_cfg_save(child, dinfo, 1);
2951 kfree(devlist, M_TEMP);
2955 pci_child_detached(device_t parent __unused, device_t child)
2957 /* Turn child's power off */
2958 pci_cfg_save(child, device_get_ivars(child), 1);
2962 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
2963 driver_intr_t *intr, void *arg, void **cookiep, lwkt_serialize_t serializer)
2965 struct pci_devinfo *dinfo;
2966 struct msix_table_entry *mte;
2967 struct msix_vector *mv;
2973 error = bus_generic_setup_intr(dev, child, irq, flags, intr,
2974 arg, &cookie, serializer);
2978 /* If this is not a direct child, just bail out. */
2979 if (device_get_parent(child) != dev) {
2984 rid = rman_get_rid(irq);
2986 /* Make sure that INTx is enabled */
2987 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
2990 * Check to see if the interrupt is MSI or MSI-X.
2991 * Ask our parent to map the MSI and give
2992 * us the address and data register values.
2993 * If we fail for some reason, teardown the
2994 * interrupt handler.
2996 dinfo = device_get_ivars(child);
2997 if (dinfo->cfg.msi.msi_alloc > 0) {
2998 if (dinfo->cfg.msi.msi_addr == 0) {
2999 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
3000 ("MSI has handlers, but vectors not mapped"));
3001 error = PCIB_MAP_MSI(device_get_parent(dev),
3002 child, rman_get_start(irq), &addr, &data,
3003 rman_get_cpuid(irq));
3006 dinfo->cfg.msi.msi_addr = addr;
3007 dinfo->cfg.msi.msi_data = data;
3008 pci_enable_msi(child, addr, data);
3010 dinfo->cfg.msi.msi_handlers++;
3012 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3013 ("No MSI or MSI-X interrupts allocated"));
3014 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3015 ("MSI-X index too high"));
3016 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3017 KASSERT(mte->mte_vector != 0, ("no message vector"));
3018 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
3019 KASSERT(mv->mv_irq == rman_get_start(irq),
3021 if (mv->mv_address == 0) {
3022 KASSERT(mte->mte_handlers == 0,
3023 ("MSI-X table entry has handlers, but vector not mapped"));
3024 error = PCIB_MAP_MSI(device_get_parent(dev),
3025 child, rman_get_start(irq), &addr, &data,
3026 rman_get_cpuid(irq));
3029 mv->mv_address = addr;
3032 if (mte->mte_handlers == 0) {
3033 pci_setup_msix_vector(child, rid - 1,
3034 mv->mv_address, mv->mv_data);
3035 pci_unmask_msix_vector(child, rid - 1);
3037 mte->mte_handlers++;
3040 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3041 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3044 (void)bus_generic_teardown_intr(dev, child, irq,
3054 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3057 struct msix_table_entry *mte;
3058 struct resource_list_entry *rle;
3059 struct pci_devinfo *dinfo;
3062 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3065 /* If this isn't a direct child, just bail out */
3066 if (device_get_parent(child) != dev)
3067 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3069 rid = rman_get_rid(irq);
3072 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3075 * Check to see if the interrupt is MSI or MSI-X. If so,
3076 * decrement the appropriate handlers count and mask the
3077 * MSI-X message, or disable MSI messages if the count
3080 dinfo = device_get_ivars(child);
3081 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
3082 if (rle->res != irq)
3084 if (dinfo->cfg.msi.msi_alloc > 0) {
3085 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
3086 ("MSI-X index too high"));
3087 if (dinfo->cfg.msi.msi_handlers == 0)
3089 dinfo->cfg.msi.msi_handlers--;
3090 if (dinfo->cfg.msi.msi_handlers == 0)
3091 pci_disable_msi(child);
3093 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3094 ("No MSI or MSI-X interrupts allocated"));
3095 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3096 ("MSI-X index too high"));
3097 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3098 if (mte->mte_handlers == 0)
3100 mte->mte_handlers--;
3101 if (mte->mte_handlers == 0)
3102 pci_mask_msix_vector(child, rid - 1);
3105 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3108 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3113 pci_print_child(device_t dev, device_t child)
3115 struct pci_devinfo *dinfo;
3116 struct resource_list *rl;
3119 dinfo = device_get_ivars(child);
3120 rl = &dinfo->resources;
3122 retval += bus_print_child_header(dev, child);
3124 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3125 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3126 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3127 if (device_get_flags(dev))
3128 retval += kprintf(" flags %#x", device_get_flags(dev));
3130 retval += kprintf(" at device %d.%d", pci_get_slot(child),
3131 pci_get_function(child));
3133 retval += bus_print_child_footer(dev, child);
3143 } pci_nomatch_tab[] = {
3144 {PCIC_OLD, -1, "old"},
3145 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3146 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3147 {PCIC_STORAGE, -1, "mass storage"},
3148 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3149 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3150 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3151 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3152 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3153 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3154 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3155 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3156 {PCIC_NETWORK, -1, "network"},
3157 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3158 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3159 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3160 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3161 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3162 {PCIC_DISPLAY, -1, "display"},
3163 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3164 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3165 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3166 {PCIC_MULTIMEDIA, -1, "multimedia"},
3167 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3168 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3169 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3170 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3171 {PCIC_MEMORY, -1, "memory"},
3172 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3173 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3174 {PCIC_BRIDGE, -1, "bridge"},
3175 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3176 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3177 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3178 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3179 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3180 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3181 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3182 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3183 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3184 {PCIC_SIMPLECOMM, -1, "simple comms"},
3185 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3186 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3187 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3188 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3189 {PCIC_BASEPERIPH, -1, "base peripheral"},
3190 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3191 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3192 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3193 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3194 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3195 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3196 {PCIC_INPUTDEV, -1, "input device"},
3197 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3198 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3199 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3200 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3201 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3202 {PCIC_DOCKING, -1, "docking station"},
3203 {PCIC_PROCESSOR, -1, "processor"},
3204 {PCIC_SERIALBUS, -1, "serial bus"},
3205 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3206 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3207 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3208 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3209 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3210 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3211 {PCIC_WIRELESS, -1, "wireless controller"},
3212 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3213 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3214 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3215 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3216 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3217 {PCIC_SATCOM, -1, "satellite communication"},
3218 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3219 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3220 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3221 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3222 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3223 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3224 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3225 {PCIC_DASP, -1, "dasp"},
3226 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3231 pci_probe_nomatch(device_t dev, device_t child)
3234 char *cp, *scp, *device;
3237 * Look for a listing for this device in a loaded device database.
3239 if ((device = pci_describe_device(child)) != NULL) {
3240 device_printf(dev, "<%s>", device);
3241 kfree(device, M_DEVBUF);
3244 * Scan the class/subclass descriptions for a general
3249 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3250 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3251 if (pci_nomatch_tab[i].subclass == -1) {
3252 cp = pci_nomatch_tab[i].desc;
3253 } else if (pci_nomatch_tab[i].subclass ==
3254 pci_get_subclass(child)) {
3255 scp = pci_nomatch_tab[i].desc;
3259 device_printf(dev, "<%s%s%s>",
3261 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3264 kprintf(" (vendor 0x%04x, dev 0x%04x) at device %d.%d",
3265 pci_get_vendor(child), pci_get_device(child),
3266 pci_get_slot(child), pci_get_function(child));
3267 if (pci_get_intpin(child) > 0) {
3270 irq = pci_get_irq(child);
3271 if (PCI_INTERRUPT_VALID(irq))
3272 kprintf(" irq %d", irq);
3276 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
3280 * Parse the PCI device database, if loaded, and return a pointer to a
3281 * description of the device.
3283 * The database is flat text formatted as follows:
3285 * Any line not in a valid format is ignored.
3286 * Lines are terminated with newline '\n' characters.
3288 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3291 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3292 * - devices cannot be listed without a corresponding VENDOR line.
3293 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3294 * another TAB, then the device name.
3298 * Assuming (ptr) points to the beginning of a line in the database,
3299 * return the vendor or device and description of the next entry.
3300 * The value of (vendor) or (device) inappropriate for the entry type
3301 * is set to -1. Returns nonzero at the end of the database.
3303 * Note that this is slightly unrobust in the face of corrupt data;
3304 * we attempt to safeguard against this by spamming the end of the
3305 * database with a newline when we initialise.
3308 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3317 left = pci_vendordata_size - (cp - pci_vendordata);
3325 ksscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3329 ksscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3332 /* skip to next line */
3333 while (*cp != '\n' && left > 0) {
3342 /* skip to next line */
3343 while (*cp != '\n' && left > 0) {
3347 if (*cp == '\n' && left > 0)
3354 pci_describe_device(device_t dev)
3357 char *desc, *vp, *dp, *line;
3359 desc = vp = dp = NULL;
3362 * If we have no vendor data, we can't do anything.
3364 if (pci_vendordata == NULL)
3368 * Scan the vendor data looking for this device
3370 line = pci_vendordata;
3371 if ((vp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3374 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3376 if (vendor == pci_get_vendor(dev))
3379 if ((dp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3382 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3390 if (device == pci_get_device(dev))
3394 ksnprintf(dp, 80, "0x%x", pci_get_device(dev));
3395 if ((desc = kmalloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3397 ksprintf(desc, "%s, %s", vp, dp);
3400 kfree(vp, M_DEVBUF);
3402 kfree(dp, M_DEVBUF);
3407 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3409 struct pci_devinfo *dinfo;
3412 dinfo = device_get_ivars(child);
3416 case PCI_IVAR_ETHADDR:
3418 * The generic accessor doesn't deal with failure, so
3419 * we set the return value, then return an error.
3421 *((uint8_t **) result) = NULL;
3423 case PCI_IVAR_SUBVENDOR:
3424 *result = cfg->subvendor;
3426 case PCI_IVAR_SUBDEVICE:
3427 *result = cfg->subdevice;
3429 case PCI_IVAR_VENDOR:
3430 *result = cfg->vendor;
3432 case PCI_IVAR_DEVICE:
3433 *result = cfg->device;
3435 case PCI_IVAR_DEVID:
3436 *result = (cfg->device << 16) | cfg->vendor;
3438 case PCI_IVAR_CLASS:
3439 *result = cfg->baseclass;
3441 case PCI_IVAR_SUBCLASS:
3442 *result = cfg->subclass;
3444 case PCI_IVAR_PROGIF:
3445 *result = cfg->progif;
3447 case PCI_IVAR_REVID:
3448 *result = cfg->revid;
3450 case PCI_IVAR_INTPIN:
3451 *result = cfg->intpin;
3454 *result = cfg->intline;
3456 case PCI_IVAR_DOMAIN:
3457 *result = cfg->domain;
3463 *result = cfg->slot;
3465 case PCI_IVAR_FUNCTION:
3466 *result = cfg->func;
3468 case PCI_IVAR_CMDREG:
3469 *result = cfg->cmdreg;
3471 case PCI_IVAR_CACHELNSZ:
3472 *result = cfg->cachelnsz;
3474 case PCI_IVAR_MINGNT:
3475 *result = cfg->mingnt;
3477 case PCI_IVAR_MAXLAT:
3478 *result = cfg->maxlat;
3480 case PCI_IVAR_LATTIMER:
3481 *result = cfg->lattimer;
3483 case PCI_IVAR_PCIXCAP_PTR:
3484 *result = cfg->pcix.pcix_ptr;
3486 case PCI_IVAR_PCIECAP_PTR:
3487 *result = cfg->expr.expr_ptr;
3489 case PCI_IVAR_VPDCAP_PTR:
3490 *result = cfg->vpd.vpd_reg;
3499 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3501 struct pci_devinfo *dinfo;
3503 dinfo = device_get_ivars(child);
3506 case PCI_IVAR_INTPIN:
3507 dinfo->cfg.intpin = value;
3509 case PCI_IVAR_ETHADDR:
3510 case PCI_IVAR_SUBVENDOR:
3511 case PCI_IVAR_SUBDEVICE:
3512 case PCI_IVAR_VENDOR:
3513 case PCI_IVAR_DEVICE:
3514 case PCI_IVAR_DEVID:
3515 case PCI_IVAR_CLASS:
3516 case PCI_IVAR_SUBCLASS:
3517 case PCI_IVAR_PROGIF:
3518 case PCI_IVAR_REVID:
3520 case PCI_IVAR_DOMAIN:
3523 case PCI_IVAR_FUNCTION:
3524 return (EINVAL); /* disallow for now */
3531 #include "opt_ddb.h"
3533 #include <ddb/ddb.h>
3534 #include <sys/cons.h>
3537 * List resources based on pci map registers, used for within ddb
3540 DB_SHOW_COMMAND(pciregs, db_pci_dump)
3542 struct pci_devinfo *dinfo;
3543 struct devlist *devlist_head;
3546 int i, error, none_count;
3549 /* get the head of the device queue */
3550 devlist_head = &pci_devq;
3553 * Go through the list of devices and print out devices
3555 for (error = 0, i = 0,
3556 dinfo = STAILQ_FIRST(devlist_head);
3557 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3558 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3560 /* Populate pd_name and pd_unit */
3563 name = device_get_name(dinfo->cfg.dev);
3566 db_kprintf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3567 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3568 (name && *name) ? name : "none",
3569 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3571 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3572 p->pc_sel.pc_func, (p->pc_class << 16) |
3573 (p->pc_subclass << 8) | p->pc_progif,
3574 (p->pc_subdevice << 16) | p->pc_subvendor,
3575 (p->pc_device << 16) | p->pc_vendor,
3576 p->pc_revid, p->pc_hdr);
3582 static struct resource *
3583 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3584 u_long start, u_long end, u_long count, u_int flags)
3586 struct pci_devinfo *dinfo = device_get_ivars(child);
3587 struct resource_list *rl = &dinfo->resources;
3588 struct resource_list_entry *rle;
3589 struct resource *res;
3590 pci_addr_t map, testval;
3594 * Weed out the bogons, and figure out how large the BAR/map
3595 * is. Bars that read back 0 here are bogus and unimplemented.
3596 * Note: atapci in legacy mode are special and handled elsewhere
3597 * in the code. If you have a atapci device in legacy mode and
3598 * it fails here, that other code is broken.
3601 map = pci_read_config(child, *rid, 4);
3602 pci_write_config(child, *rid, 0xffffffff, 4);
3603 testval = pci_read_config(child, *rid, 4);
3604 if (pci_maprange(testval) == 64)
3605 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
3606 if (pci_mapbase(testval) == 0)
3610 * Restore the original value of the BAR. We may have reprogrammed
3611 * the BAR of the low-level console device and when booting verbose,
3612 * we need the console device addressable.
3614 pci_write_config(child, *rid, map, 4);
3616 if (PCI_BAR_MEM(testval)) {
3617 if (type != SYS_RES_MEMORY) {
3620 "child %s requested type %d for rid %#x,"
3621 " but the BAR says it is an memio\n",
3622 device_get_nameunit(child), type, *rid);
3626 if (type != SYS_RES_IOPORT) {
3629 "child %s requested type %d for rid %#x,"
3630 " but the BAR says it is an ioport\n",
3631 device_get_nameunit(child), type, *rid);
3636 * For real BARs, we need to override the size that
3637 * the driver requests, because that's what the BAR
3638 * actually uses and we would otherwise have a
3639 * situation where we might allocate the excess to
3640 * another driver, which won't work.
3642 mapsize = pci_mapsize(testval);
3643 count = 1UL << mapsize;
3644 if (RF_ALIGNMENT(flags) < mapsize)
3645 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3646 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3647 flags |= RF_PREFETCHABLE;
3650 * Allocate enough resource, and then write back the
3651 * appropriate bar for that resource.
3653 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
3654 start, end, count, flags, -1);
3656 device_printf(child,
3657 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3658 count, *rid, type, start, end);
3661 resource_list_add(rl, type, *rid, start, end, count, -1);
3662 rle = resource_list_find(rl, type, *rid);
3664 panic("pci_alloc_map: unexpectedly can't find resource.");
3666 rle->start = rman_get_start(res);
3667 rle->end = rman_get_end(res);
3670 device_printf(child,
3671 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3672 count, *rid, type, rman_get_start(res));
3673 map = rman_get_start(res);
3675 pci_write_config(child, *rid, map, 4);
3676 if (pci_maprange(testval) == 64)
3677 pci_write_config(child, *rid + 4, map >> 32, 4);
3683 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
3684 u_long start, u_long end, u_long count, u_int flags, int cpuid)
3686 struct pci_devinfo *dinfo = device_get_ivars(child);
3687 struct resource_list *rl = &dinfo->resources;
3688 struct resource_list_entry *rle;
3689 pcicfgregs *cfg = &dinfo->cfg;
3692 * Perform lazy resource allocation
3694 if (device_get_parent(child) == dev) {
3698 * Can't alloc legacy interrupt once MSI messages
3699 * have been allocated.
3701 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3702 cfg->msix.msix_alloc > 0))
3705 * If the child device doesn't have an
3706 * interrupt routed and is deserving of an
3707 * interrupt, try to assign it one.
3709 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3711 pci_assign_interrupt(dev, child, 0);
3713 case SYS_RES_IOPORT:
3714 case SYS_RES_MEMORY:
3715 if (*rid < PCIR_BAR(cfg->nummaps)) {
3717 * Enable the I/O mode. We should
3718 * also be assigning resources too
3719 * when none are present. The
3720 * resource_list_alloc kind of sorta does
3723 if (PCI_ENABLE_IO(dev, child, type))
3726 rle = resource_list_find(rl, type, *rid);
3728 return (pci_alloc_map(dev, child, type, rid,
3729 start, end, count, flags));
3733 * If we've already allocated the resource, then
3734 * return it now. But first we may need to activate
3735 * it, since we don't allocate the resource as active
3736 * above. Normally this would be done down in the
3737 * nexus, but since we short-circuit that path we have
3738 * to do its job here. Not sure if we should kfree the
3739 * resource if it fails to activate.
3741 rle = resource_list_find(rl, type, *rid);
3742 if (rle != NULL && rle->res != NULL) {
3744 device_printf(child,
3745 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
3746 rman_get_size(rle->res), *rid, type,
3747 rman_get_start(rle->res));
3748 if ((flags & RF_ACTIVE) &&
3749 bus_generic_activate_resource(dev, child, type,
3750 *rid, rle->res) != 0)
3755 return (resource_list_alloc(rl, dev, child, type, rid,
3756 start, end, count, flags, cpuid));
3760 pci_delete_resource(device_t dev, device_t child, int type, int rid)
3762 struct pci_devinfo *dinfo;
3763 struct resource_list *rl;
3764 struct resource_list_entry *rle;
3766 if (device_get_parent(child) != dev)
3769 dinfo = device_get_ivars(child);
3770 rl = &dinfo->resources;
3771 rle = resource_list_find(rl, type, rid);
3774 if (rman_get_device(rle->res) != dev ||
3775 rman_get_flags(rle->res) & RF_ACTIVE) {
3776 device_printf(dev, "delete_resource: "
3777 "Resource still owned by child, oops. "
3778 "(type=%d, rid=%d, addr=%lx)\n",
3779 rle->type, rle->rid,
3780 rman_get_start(rle->res));
3783 bus_release_resource(dev, type, rid, rle->res);
3785 resource_list_delete(rl, type, rid);
3788 * Why do we turn off the PCI configuration BAR when we delete a
3791 pci_write_config(child, rid, 0, 4);
3792 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
3795 struct resource_list *
3796 pci_get_resource_list (device_t dev, device_t child)
3798 struct pci_devinfo *dinfo = device_get_ivars(child);
3803 return (&dinfo->resources);
3807 pci_read_config_method(device_t dev, device_t child, int reg, int width)
3809 struct pci_devinfo *dinfo = device_get_ivars(child);
3810 pcicfgregs *cfg = &dinfo->cfg;
3812 return (PCIB_READ_CONFIG(device_get_parent(dev),
3813 cfg->bus, cfg->slot, cfg->func, reg, width));
3817 pci_write_config_method(device_t dev, device_t child, int reg,
3818 uint32_t val, int width)
3820 struct pci_devinfo *dinfo = device_get_ivars(child);
3821 pcicfgregs *cfg = &dinfo->cfg;
3823 PCIB_WRITE_CONFIG(device_get_parent(dev),
3824 cfg->bus, cfg->slot, cfg->func, reg, val, width);
3828 pci_child_location_str_method(device_t dev, device_t child, char *buf,
3832 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
3833 pci_get_function(child));
3838 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
3841 struct pci_devinfo *dinfo;
3844 dinfo = device_get_ivars(child);
3846 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
3847 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
3848 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
3854 pci_assign_interrupt_method(device_t dev, device_t child)
3856 struct pci_devinfo *dinfo = device_get_ivars(child);
3857 pcicfgregs *cfg = &dinfo->cfg;
3859 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
3864 pci_modevent(module_t mod, int what, void *arg)
3866 static struct cdev *pci_cdev;
3870 STAILQ_INIT(&pci_devq);
3872 pci_cdev = make_dev(&pcic_ops, 0, UID_ROOT, GID_WHEEL, 0644,
3874 pci_load_vendor_data();
3878 destroy_dev(pci_cdev);
3886 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
3891 * Only do header type 0 devices. Type 1 devices are bridges,
3892 * which we know need special treatment. Type 2 devices are
3893 * cardbus bridges which also require special treatment.
3894 * Other types are unknown, and we err on the side of safety
3897 if (dinfo->cfg.hdrtype != 0)
3901 * Restore the device to full power mode. We must do this
3902 * before we restore the registers because moving from D3 to
3903 * D0 will cause the chip's BARs and some other registers to
3904 * be reset to some unknown power on reset values. Cut down
3905 * the noise on boot by doing nothing if we are already in
3908 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
3909 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
3911 for (i = 0; i < dinfo->cfg.nummaps; i++)
3912 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
3913 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
3914 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
3915 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
3916 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
3917 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
3918 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
3919 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
3920 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
3921 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
3922 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
3924 /* Restore MSI and MSI-X configurations if they are present. */
3925 if (dinfo->cfg.msi.msi_location != 0)
3926 pci_resume_msi(dev);
3927 if (dinfo->cfg.msix.msix_location != 0)
3928 pci_resume_msix(dev);
3932 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
3939 * Only do header type 0 devices. Type 1 devices are bridges, which
3940 * we know need special treatment. Type 2 devices are cardbus bridges
3941 * which also require special treatment. Other types are unknown, and
3942 * we err on the side of safety by ignoring them. Powering down
3943 * bridges should not be undertaken lightly.
3945 if (dinfo->cfg.hdrtype != 0)
3947 for (i = 0; i < dinfo->cfg.nummaps; i++)
3948 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
3949 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
3952 * Some drivers apparently write to these registers w/o updating our
3953 * cached copy. No harm happens if we update the copy, so do so here
3954 * so we can restore them. The COMMAND register is modified by the
3955 * bus w/o updating the cache. This should represent the normally
3956 * writable portion of the 'defined' part of type 0 headers. In
3957 * theory we also need to save/restore the PCI capability structures
3958 * we know about, but apart from power we don't know any that are
3961 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
3962 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
3963 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
3964 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
3965 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
3966 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
3967 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
3968 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
3969 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
3970 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3971 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3972 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
3973 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
3974 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
3975 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
3978 * don't set the state for display devices, base peripherals and
3979 * memory devices since bad things happen when they are powered down.
3980 * We should (a) have drivers that can easily detach and (b) use
3981 * generic drivers for these devices so that some device actually
3982 * attaches. We need to make sure that when we implement (a) we don't
3983 * power the device down on a reattach.
3985 cls = pci_get_class(dev);
3988 switch (pci_do_power_nodriver)
3990 case 0: /* NO powerdown at all */
3992 case 1: /* Conservative about what to power down */
3993 if (cls == PCIC_STORAGE)
3996 case 2: /* Agressive about what to power down */
3997 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
3998 cls == PCIC_BASEPERIPH)
4001 case 3: /* Power down everything */
4005 * PCI spec says we can only go into D3 state from D0 state.
4006 * Transition from D[12] into D0 before going to D3 state.
4008 ps = pci_get_powerstate(dev);
4009 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
4010 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4011 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
4012 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
4015 #ifdef COMPAT_OLDPCI
4018 * Locate the parent of a PCI device by scanning the PCI devlist
4019 * and return the entry for the parent.
4020 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
4021 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
4024 pci_devlist_get_parent(pcicfgregs *cfg)
4026 struct devlist *devlist_head;
4027 struct pci_devinfo *dinfo;
4028 pcicfgregs *bridge_cfg;
4031 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
4033 /* If the device is on PCI bus 0, look for the host */
4034 if (cfg->bus == 0) {
4035 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
4036 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4037 bridge_cfg = &dinfo->cfg;
4038 if (bridge_cfg->baseclass == PCIC_BRIDGE
4039 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
4040 && bridge_cfg->bus == cfg->bus) {
4046 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
4048 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
4049 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4050 bridge_cfg = &dinfo->cfg;
4051 if (bridge_cfg->baseclass == PCIC_BRIDGE
4052 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
4053 && bridge_cfg->secondarybus == cfg->bus) {
4062 #endif /* COMPAT_OLDPCI */
4065 pci_alloc_1intr(device_t dev, int msi_enable, int *rid0, u_int *flags0)
4072 type = PCI_INTR_TYPE_LEGACY;
4073 flags = RF_SHAREABLE | RF_ACTIVE;
4075 ksnprintf(env, sizeof(env), "hw.%s.msi.enable",
4076 device_get_nameunit(dev));
4077 kgetenv_int(env, &msi_enable);
4082 ksnprintf(env, sizeof(env), "hw.%s.msi.cpu",
4083 device_get_nameunit(dev));
4084 kgetenv_int(env, &cpu);
4088 if (pci_alloc_msi(dev, &rid, 1, cpu) == 0) {
4089 flags &= ~RF_SHAREABLE;
4090 type = PCI_INTR_TYPE_MSI;