sys/platform/pc32/apic/ioapic_abi.c

   1 /*
   2  * Copyright (c) 2005 The DragonFly Project.  All rights reserved.
   3  * Copyright (c) 1996, by Steve Passe.  All rights reserved.
   4  * Copyright (c) 1991 The Regents of the University of California.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The DragonFly Project
   8  * by Matthew Dillon <dillon@backplane.com>
   9  *
  10  * This code is derived from software contributed to Berkeley by
  11  * William Jolitz.
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  *
  17  * 1. Redistributions of source code must retain the above copyright
  18  *    notice, this list of conditions and the following disclaimer.
  19  * 2. Redistributions in binary form must reproduce the above copyright
  20  *    notice, this list of conditions and the following disclaimer in
  21  *    the documentation and/or other materials provided with the
  22  *    distribution.
  23  * 3. Neither the name of The DragonFly Project nor the names of its
  24  *    contributors may be used to endorse or promote products derived
  25  *    from this software without specific, prior written permission.
  26  *
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  30  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  31  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  32  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
  33  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  34  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  35  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  36  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  37  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  38  * SUCH DAMAGE.
  39  *
  40  * $DragonFly: src/sys/platform/pc32/apic/apic_abi.c,v 1.12 2007/04/30 16:45:55 dillon Exp $
  41  */
  42
  43 #include <sys/param.h>
  44 #include <sys/systm.h>
  45 #include <sys/kernel.h>
  46 #include <sys/machintr.h>
  47 #include <sys/interrupt.h>
  48 #include <sys/bus.h>
  49 #include <sys/rman.h>
  50 #include <sys/thread2.h>
  51
  52 #include <machine/smp.h>
  53 #include <machine/segments.h>
  54 #include <machine/md_var.h>
  55 #include <machine/intr_machdep.h>
  56 #include <machine/globaldata.h>
  57 #include <machine/msi_var.h>
  58
  59 #include <machine_base/isa/isa_intr.h>
  60 #include <machine_base/icu/icu.h>
  61 #include <machine_base/icu/icu_var.h>
  62 #include <machine_base/apic/ioapic.h>
  63 #include <machine_base/apic/ioapic_abi.h>
  64 #include <machine_base/apic/ioapic_ipl.h>
  65 #include <machine_base/apic/apicreg.h>
  66
  67 #include <dev/acpica5/acpi_sci_var.h>
  68
  69 #define IOAPIC_HWI_VECTORS      IDT_HWI_VECTORS
  70
  71 extern inthand_t
  72         IDTVEC(ioapic_intr0),
  73         IDTVEC(ioapic_intr1),
  74         IDTVEC(ioapic_intr2),
  75         IDTVEC(ioapic_intr3),
  76         IDTVEC(ioapic_intr4),
  77         IDTVEC(ioapic_intr5),
  78         IDTVEC(ioapic_intr6),
  79         IDTVEC(ioapic_intr7),
  80         IDTVEC(ioapic_intr8),
  81         IDTVEC(ioapic_intr9),
  82         IDTVEC(ioapic_intr10),
  83         IDTVEC(ioapic_intr11),
  84         IDTVEC(ioapic_intr12),
  85         IDTVEC(ioapic_intr13),
  86         IDTVEC(ioapic_intr14),
  87         IDTVEC(ioapic_intr15),
  88         IDTVEC(ioapic_intr16),
  89         IDTVEC(ioapic_intr17),
  90         IDTVEC(ioapic_intr18),
  91         IDTVEC(ioapic_intr19),
  92         IDTVEC(ioapic_intr20),
  93         IDTVEC(ioapic_intr21),
  94         IDTVEC(ioapic_intr22),
  95         IDTVEC(ioapic_intr23),
  96         IDTVEC(ioapic_intr24),
  97         IDTVEC(ioapic_intr25),
  98         IDTVEC(ioapic_intr26),
  99         IDTVEC(ioapic_intr27),
 100         IDTVEC(ioapic_intr28),
 101         IDTVEC(ioapic_intr29),
 102         IDTVEC(ioapic_intr30),
 103         IDTVEC(ioapic_intr31),
 104         IDTVEC(ioapic_intr32),
 105         IDTVEC(ioapic_intr33),
 106         IDTVEC(ioapic_intr34),
 107         IDTVEC(ioapic_intr35),
 108         IDTVEC(ioapic_intr36),
 109         IDTVEC(ioapic_intr37),
 110         IDTVEC(ioapic_intr38),
 111         IDTVEC(ioapic_intr39),
 112         IDTVEC(ioapic_intr40),
 113         IDTVEC(ioapic_intr41),
 114         IDTVEC(ioapic_intr42),
 115         IDTVEC(ioapic_intr43),
 116         IDTVEC(ioapic_intr44),
 117         IDTVEC(ioapic_intr45),
 118         IDTVEC(ioapic_intr46),
 119         IDTVEC(ioapic_intr47),
 120         IDTVEC(ioapic_intr48),
 121         IDTVEC(ioapic_intr49),
 122         IDTVEC(ioapic_intr50),
 123         IDTVEC(ioapic_intr51),
 124         IDTVEC(ioapic_intr52),
 125         IDTVEC(ioapic_intr53),
 126         IDTVEC(ioapic_intr54),
 127         IDTVEC(ioapic_intr55),
 128         IDTVEC(ioapic_intr56),
 129         IDTVEC(ioapic_intr57),
 130         IDTVEC(ioapic_intr58),
 131         IDTVEC(ioapic_intr59),
 132         IDTVEC(ioapic_intr60),
 133         IDTVEC(ioapic_intr61),
 134         IDTVEC(ioapic_intr62),
 135         IDTVEC(ioapic_intr63),
 136         IDTVEC(ioapic_intr64),
 137         IDTVEC(ioapic_intr65),
 138         IDTVEC(ioapic_intr66),
 139         IDTVEC(ioapic_intr67),
 140         IDTVEC(ioapic_intr68),
 141         IDTVEC(ioapic_intr69),
 142         IDTVEC(ioapic_intr70),
 143         IDTVEC(ioapic_intr71),
 144         IDTVEC(ioapic_intr72),
 145         IDTVEC(ioapic_intr73),
 146         IDTVEC(ioapic_intr74),
 147         IDTVEC(ioapic_intr75),
 148         IDTVEC(ioapic_intr76),
 149         IDTVEC(ioapic_intr77),
 150         IDTVEC(ioapic_intr78),
 151         IDTVEC(ioapic_intr79),
 152         IDTVEC(ioapic_intr80),
 153         IDTVEC(ioapic_intr81),
 154         IDTVEC(ioapic_intr82),
 155         IDTVEC(ioapic_intr83),
 156         IDTVEC(ioapic_intr84),
 157         IDTVEC(ioapic_intr85),
 158         IDTVEC(ioapic_intr86),
 159         IDTVEC(ioapic_intr87),
 160         IDTVEC(ioapic_intr88),
 161         IDTVEC(ioapic_intr89),
 162         IDTVEC(ioapic_intr90),
 163         IDTVEC(ioapic_intr91),
 164         IDTVEC(ioapic_intr92),
 165         IDTVEC(ioapic_intr93),
 166         IDTVEC(ioapic_intr94),
 167         IDTVEC(ioapic_intr95),
 168         IDTVEC(ioapic_intr96),
 169         IDTVEC(ioapic_intr97),
 170         IDTVEC(ioapic_intr98),
 171         IDTVEC(ioapic_intr99),
 172         IDTVEC(ioapic_intr100),
 173         IDTVEC(ioapic_intr101),
 174         IDTVEC(ioapic_intr102),
 175         IDTVEC(ioapic_intr103),
 176         IDTVEC(ioapic_intr104),
 177         IDTVEC(ioapic_intr105),
 178         IDTVEC(ioapic_intr106),
 179         IDTVEC(ioapic_intr107),
 180         IDTVEC(ioapic_intr108),
 181         IDTVEC(ioapic_intr109),
 182         IDTVEC(ioapic_intr110),
 183         IDTVEC(ioapic_intr111),
 184         IDTVEC(ioapic_intr112),
 185         IDTVEC(ioapic_intr113),
 186         IDTVEC(ioapic_intr114),
 187         IDTVEC(ioapic_intr115),
 188         IDTVEC(ioapic_intr116),
 189         IDTVEC(ioapic_intr117),
 190         IDTVEC(ioapic_intr118),
 191         IDTVEC(ioapic_intr119),
 192         IDTVEC(ioapic_intr120),
 193         IDTVEC(ioapic_intr121),
 194         IDTVEC(ioapic_intr122),
 195         IDTVEC(ioapic_intr123),
 196         IDTVEC(ioapic_intr124),
 197         IDTVEC(ioapic_intr125),
 198         IDTVEC(ioapic_intr126),
 199         IDTVEC(ioapic_intr127),
 200         IDTVEC(ioapic_intr128),
 201         IDTVEC(ioapic_intr129),
 202         IDTVEC(ioapic_intr130),
 203         IDTVEC(ioapic_intr131),
 204         IDTVEC(ioapic_intr132),
 205         IDTVEC(ioapic_intr133),
 206         IDTVEC(ioapic_intr134),
 207         IDTVEC(ioapic_intr135),
 208         IDTVEC(ioapic_intr136),
 209         IDTVEC(ioapic_intr137),
 210         IDTVEC(ioapic_intr138),
 211         IDTVEC(ioapic_intr139),
 212         IDTVEC(ioapic_intr140),
 213         IDTVEC(ioapic_intr141),
 214         IDTVEC(ioapic_intr142),
 215         IDTVEC(ioapic_intr143),
 216         IDTVEC(ioapic_intr144),
 217         IDTVEC(ioapic_intr145),
 218         IDTVEC(ioapic_intr146),
 219         IDTVEC(ioapic_intr147),
 220         IDTVEC(ioapic_intr148),
 221         IDTVEC(ioapic_intr149),
 222         IDTVEC(ioapic_intr150),
 223         IDTVEC(ioapic_intr151),
 224         IDTVEC(ioapic_intr152),
 225         IDTVEC(ioapic_intr153),
 226         IDTVEC(ioapic_intr154),
 227         IDTVEC(ioapic_intr155),
 228         IDTVEC(ioapic_intr156),
 229         IDTVEC(ioapic_intr157),
 230         IDTVEC(ioapic_intr158),
 231         IDTVEC(ioapic_intr159),
 232         IDTVEC(ioapic_intr160),
 233         IDTVEC(ioapic_intr161),
 234         IDTVEC(ioapic_intr162),
 235         IDTVEC(ioapic_intr163),
 236         IDTVEC(ioapic_intr164),
 237         IDTVEC(ioapic_intr165),
 238         IDTVEC(ioapic_intr166),
 239         IDTVEC(ioapic_intr167),
 240         IDTVEC(ioapic_intr168),
 241         IDTVEC(ioapic_intr169),
 242         IDTVEC(ioapic_intr170),
 243         IDTVEC(ioapic_intr171),
 244         IDTVEC(ioapic_intr172),
 245         IDTVEC(ioapic_intr173),
 246         IDTVEC(ioapic_intr174),
 247         IDTVEC(ioapic_intr175),
 248         IDTVEC(ioapic_intr176),
 249         IDTVEC(ioapic_intr177),
 250         IDTVEC(ioapic_intr178),
 251         IDTVEC(ioapic_intr179),
 252         IDTVEC(ioapic_intr180),
 253         IDTVEC(ioapic_intr181),
 254         IDTVEC(ioapic_intr182),
 255         IDTVEC(ioapic_intr183),
 256         IDTVEC(ioapic_intr184),
 257         IDTVEC(ioapic_intr185),
 258         IDTVEC(ioapic_intr186),
 259         IDTVEC(ioapic_intr187),
 260         IDTVEC(ioapic_intr188),
 261         IDTVEC(ioapic_intr189),
 262         IDTVEC(ioapic_intr190),
 263         IDTVEC(ioapic_intr191);
 264
 265 static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = {
 266         &IDTVEC(ioapic_intr0),
 267         &IDTVEC(ioapic_intr1),
 268         &IDTVEC(ioapic_intr2),
 269         &IDTVEC(ioapic_intr3),
 270         &IDTVEC(ioapic_intr4),
 271         &IDTVEC(ioapic_intr5),
 272         &IDTVEC(ioapic_intr6),
 273         &IDTVEC(ioapic_intr7),
 274         &IDTVEC(ioapic_intr8),
 275         &IDTVEC(ioapic_intr9),
 276         &IDTVEC(ioapic_intr10),
 277         &IDTVEC(ioapic_intr11),
 278         &IDTVEC(ioapic_intr12),
 279         &IDTVEC(ioapic_intr13),
 280         &IDTVEC(ioapic_intr14),
 281         &IDTVEC(ioapic_intr15),
 282         &IDTVEC(ioapic_intr16),
 283         &IDTVEC(ioapic_intr17),
 284         &IDTVEC(ioapic_intr18),
 285         &IDTVEC(ioapic_intr19),
 286         &IDTVEC(ioapic_intr20),
 287         &IDTVEC(ioapic_intr21),
 288         &IDTVEC(ioapic_intr22),
 289         &IDTVEC(ioapic_intr23),
 290         &IDTVEC(ioapic_intr24),
 291         &IDTVEC(ioapic_intr25),
 292         &IDTVEC(ioapic_intr26),
 293         &IDTVEC(ioapic_intr27),
 294         &IDTVEC(ioapic_intr28),
 295         &IDTVEC(ioapic_intr29),
 296         &IDTVEC(ioapic_intr30),
 297         &IDTVEC(ioapic_intr31),
 298         &IDTVEC(ioapic_intr32),
 299         &IDTVEC(ioapic_intr33),
 300         &IDTVEC(ioapic_intr34),
 301         &IDTVEC(ioapic_intr35),
 302         &IDTVEC(ioapic_intr36),
 303         &IDTVEC(ioapic_intr37),
 304         &IDTVEC(ioapic_intr38),
 305         &IDTVEC(ioapic_intr39),
 306         &IDTVEC(ioapic_intr40),
 307         &IDTVEC(ioapic_intr41),
 308         &IDTVEC(ioapic_intr42),
 309         &IDTVEC(ioapic_intr43),
 310         &IDTVEC(ioapic_intr44),
 311         &IDTVEC(ioapic_intr45),
 312         &IDTVEC(ioapic_intr46),
 313         &IDTVEC(ioapic_intr47),
 314         &IDTVEC(ioapic_intr48),
 315         &IDTVEC(ioapic_intr49),
 316         &IDTVEC(ioapic_intr50),
 317         &IDTVEC(ioapic_intr51),
 318         &IDTVEC(ioapic_intr52),
 319         &IDTVEC(ioapic_intr53),
 320         &IDTVEC(ioapic_intr54),
 321         &IDTVEC(ioapic_intr55),
 322         &IDTVEC(ioapic_intr56),
 323         &IDTVEC(ioapic_intr57),
 324         &IDTVEC(ioapic_intr58),
 325         &IDTVEC(ioapic_intr59),
 326         &IDTVEC(ioapic_intr60),
 327         &IDTVEC(ioapic_intr61),
 328         &IDTVEC(ioapic_intr62),
 329         &IDTVEC(ioapic_intr63),
 330         &IDTVEC(ioapic_intr64),
 331         &IDTVEC(ioapic_intr65),
 332         &IDTVEC(ioapic_intr66),
 333         &IDTVEC(ioapic_intr67),
 334         &IDTVEC(ioapic_intr68),
 335         &IDTVEC(ioapic_intr69),
 336         &IDTVEC(ioapic_intr70),
 337         &IDTVEC(ioapic_intr71),
 338         &IDTVEC(ioapic_intr72),
 339         &IDTVEC(ioapic_intr73),
 340         &IDTVEC(ioapic_intr74),
 341         &IDTVEC(ioapic_intr75),
 342         &IDTVEC(ioapic_intr76),
 343         &IDTVEC(ioapic_intr77),
 344         &IDTVEC(ioapic_intr78),
 345         &IDTVEC(ioapic_intr79),
 346         &IDTVEC(ioapic_intr80),
 347         &IDTVEC(ioapic_intr81),
 348         &IDTVEC(ioapic_intr82),
 349         &IDTVEC(ioapic_intr83),
 350         &IDTVEC(ioapic_intr84),
 351         &IDTVEC(ioapic_intr85),
 352         &IDTVEC(ioapic_intr86),
 353         &IDTVEC(ioapic_intr87),
 354         &IDTVEC(ioapic_intr88),
 355         &IDTVEC(ioapic_intr89),
 356         &IDTVEC(ioapic_intr90),
 357         &IDTVEC(ioapic_intr91),
 358         &IDTVEC(ioapic_intr92),
 359         &IDTVEC(ioapic_intr93),
 360         &IDTVEC(ioapic_intr94),
 361         &IDTVEC(ioapic_intr95),
 362         &IDTVEC(ioapic_intr96),
 363         &IDTVEC(ioapic_intr97),
 364         &IDTVEC(ioapic_intr98),
 365         &IDTVEC(ioapic_intr99),
 366         &IDTVEC(ioapic_intr100),
 367         &IDTVEC(ioapic_intr101),
 368         &IDTVEC(ioapic_intr102),
 369         &IDTVEC(ioapic_intr103),
 370         &IDTVEC(ioapic_intr104),
 371         &IDTVEC(ioapic_intr105),
 372         &IDTVEC(ioapic_intr106),
 373         &IDTVEC(ioapic_intr107),
 374         &IDTVEC(ioapic_intr108),
 375         &IDTVEC(ioapic_intr109),
 376         &IDTVEC(ioapic_intr110),
 377         &IDTVEC(ioapic_intr111),
 378         &IDTVEC(ioapic_intr112),
 379         &IDTVEC(ioapic_intr113),
 380         &IDTVEC(ioapic_intr114),
 381         &IDTVEC(ioapic_intr115),
 382         &IDTVEC(ioapic_intr116),
 383         &IDTVEC(ioapic_intr117),
 384         &IDTVEC(ioapic_intr118),
 385         &IDTVEC(ioapic_intr119),
 386         &IDTVEC(ioapic_intr120),
 387         &IDTVEC(ioapic_intr121),
 388         &IDTVEC(ioapic_intr122),
 389         &IDTVEC(ioapic_intr123),
 390         &IDTVEC(ioapic_intr124),
 391         &IDTVEC(ioapic_intr125),
 392         &IDTVEC(ioapic_intr126),
 393         &IDTVEC(ioapic_intr127),
 394         &IDTVEC(ioapic_intr128),
 395         &IDTVEC(ioapic_intr129),
 396         &IDTVEC(ioapic_intr130),
 397         &IDTVEC(ioapic_intr131),
 398         &IDTVEC(ioapic_intr132),
 399         &IDTVEC(ioapic_intr133),
 400         &IDTVEC(ioapic_intr134),
 401         &IDTVEC(ioapic_intr135),
 402         &IDTVEC(ioapic_intr136),
 403         &IDTVEC(ioapic_intr137),
 404         &IDTVEC(ioapic_intr138),
 405         &IDTVEC(ioapic_intr139),
 406         &IDTVEC(ioapic_intr140),
 407         &IDTVEC(ioapic_intr141),
 408         &IDTVEC(ioapic_intr142),
 409         &IDTVEC(ioapic_intr143),
 410         &IDTVEC(ioapic_intr144),
 411         &IDTVEC(ioapic_intr145),
 412         &IDTVEC(ioapic_intr146),
 413         &IDTVEC(ioapic_intr147),
 414         &IDTVEC(ioapic_intr148),
 415         &IDTVEC(ioapic_intr149),
 416         &IDTVEC(ioapic_intr150),
 417         &IDTVEC(ioapic_intr151),
 418         &IDTVEC(ioapic_intr152),
 419         &IDTVEC(ioapic_intr153),
 420         &IDTVEC(ioapic_intr154),
 421         &IDTVEC(ioapic_intr155),
 422         &IDTVEC(ioapic_intr156),
 423         &IDTVEC(ioapic_intr157),
 424         &IDTVEC(ioapic_intr158),
 425         &IDTVEC(ioapic_intr159),
 426         &IDTVEC(ioapic_intr160),
 427         &IDTVEC(ioapic_intr161),
 428         &IDTVEC(ioapic_intr162),
 429         &IDTVEC(ioapic_intr163),
 430         &IDTVEC(ioapic_intr164),
 431         &IDTVEC(ioapic_intr165),
 432         &IDTVEC(ioapic_intr166),
 433         &IDTVEC(ioapic_intr167),
 434         &IDTVEC(ioapic_intr168),
 435         &IDTVEC(ioapic_intr169),
 436         &IDTVEC(ioapic_intr170),
 437         &IDTVEC(ioapic_intr171),
 438         &IDTVEC(ioapic_intr172),
 439         &IDTVEC(ioapic_intr173),
 440         &IDTVEC(ioapic_intr174),
 441         &IDTVEC(ioapic_intr175),
 442         &IDTVEC(ioapic_intr176),
 443         &IDTVEC(ioapic_intr177),
 444         &IDTVEC(ioapic_intr178),
 445         &IDTVEC(ioapic_intr179),
 446         &IDTVEC(ioapic_intr180),
 447         &IDTVEC(ioapic_intr181),
 448         &IDTVEC(ioapic_intr182),
 449         &IDTVEC(ioapic_intr183),
 450         &IDTVEC(ioapic_intr184),
 451         &IDTVEC(ioapic_intr185),
 452         &IDTVEC(ioapic_intr186),
 453         &IDTVEC(ioapic_intr187),
 454         &IDTVEC(ioapic_intr188),
 455         &IDTVEC(ioapic_intr189),
 456         &IDTVEC(ioapic_intr190),
 457         &IDTVEC(ioapic_intr191)
 458 };
 459
 460 #define IOAPIC_HWI_SYSCALL      (IDT_OFFSET_SYSCALL - IDT_OFFSET)
 461
 462 static struct ioapic_irqmap {
 463         int                     im_type;        /* IOAPIC_IMT_ */
 464         enum intr_trigger       im_trig;
 465         enum intr_polarity      im_pola;
 466         int                     im_gsi;
 467         int                     im_msi_base;
 468         uint32_t                im_flags;       /* IOAPIC_IMF_ */
 469 } ioapic_irqmaps[MAXCPU][IOAPIC_HWI_VECTORS];
 470
 471 static struct lwkt_token ioapic_irqmap_tok =
 472         LWKT_TOKEN_INITIALIZER(ioapic_irqmap_token);
 473
 474 #define IOAPIC_IMT_UNUSED       0
 475 #define IOAPIC_IMT_RESERVED     1
 476 #define IOAPIC_IMT_LEGACY       2
 477 #define IOAPIC_IMT_SYSCALL      3
 478 #define IOAPIC_IMT_SHADOW       4
 479 #define IOAPIC_IMT_MSI          5
 480
 481 #define IOAPIC_IMT_ISHWI(map)   ((map)->im_type != IOAPIC_IMT_RESERVED && \
 482                                  (map)->im_type != IOAPIC_IMT_SYSCALL && \
 483                                  (map)->im_type != IOAPIC_IMT_SHADOW)
 484
 485 #define IOAPIC_IMF_CONF         0x1
 486
 487 extern void     IOAPIC_INTREN(int);
 488 extern void     IOAPIC_INTRDIS(int);
 489
 490 extern int      imcr_present;
 491
 492 static void     ioapic_abi_intr_enable(int);
 493 static void     ioapic_abi_intr_disable(int);
 494 static void     ioapic_abi_intr_setup(int, int);
 495 static void     ioapic_abi_intr_teardown(int);
 496
 497 static void     ioapic_abi_legacy_intr_config(int,
 498                     enum intr_trigger, enum intr_polarity);
 499 static int      ioapic_abi_legacy_intr_cpuid(int);
 500
 501 static int      ioapic_abi_msi_alloc(int [], int, int);
 502 static void     ioapic_abi_msi_release(const int [], int, int);
 503 static void     ioapic_abi_msi_map(int, uint64_t *, uint32_t *, int);
 504
 505 static void     ioapic_abi_finalize(void);
 506 static void     ioapic_abi_cleanup(void);
 507 static void     ioapic_abi_setdefault(void);
 508 static void     ioapic_abi_stabilize(void);
 509 static void     ioapic_abi_initmap(void);
 510 static void     ioapic_abi_rman_setup(struct rman *);
 511
 512 static int      ioapic_abi_gsi_cpuid(int, int);
 513
 514 struct machintr_abi MachIntrABI_IOAPIC = {
 515         MACHINTR_IOAPIC,
 516
 517         .intr_disable   = ioapic_abi_intr_disable,
 518         .intr_enable    = ioapic_abi_intr_enable,
 519         .intr_setup     = ioapic_abi_intr_setup,
 520         .intr_teardown  = ioapic_abi_intr_teardown,
 521
 522         .legacy_intr_config = ioapic_abi_legacy_intr_config,
 523         .legacy_intr_cpuid = ioapic_abi_legacy_intr_cpuid,
 524
 525         .msi_alloc      = ioapic_abi_msi_alloc,
 526         .msi_release    = ioapic_abi_msi_release,
 527         .msi_map        = ioapic_abi_msi_map,
 528
 529         .finalize       = ioapic_abi_finalize,
 530         .cleanup        = ioapic_abi_cleanup,
 531         .setdefault     = ioapic_abi_setdefault,
 532         .stabilize      = ioapic_abi_stabilize,
 533         .initmap        = ioapic_abi_initmap,
 534         .rman_setup     = ioapic_abi_rman_setup
 535 };
 536
 537 static int      ioapic_abi_extint_irq = -1;
 538 static int      ioapic_abi_legacy_irq_max;
 539 static int      ioapic_abi_gsi_balance;
 540 static int      ioapic_abi_msi_start;   /* NOTE: for testing only */
 541
 542 struct ioapic_irqinfo   ioapic_irqs[IOAPIC_HWI_VECTORS];
 543
 544 static void
 545 ioapic_abi_intr_enable(int irq)
 546 {
 547         const struct ioapic_irqmap *map;
 548
 549         KASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS,
 550             ("ioapic enable, invalid irq %d\n", irq));
 551
 552         map = &ioapic_irqmaps[mycpuid][irq];
 553         KASSERT(IOAPIC_IMT_ISHWI(map),
 554             ("ioapic enable, not hwi irq %d, type %d, cpu%d\n",
 555              irq, map->im_type, mycpuid));
 556         if (map->im_type != IOAPIC_IMT_LEGACY)
 557                 return;
 558
 559         IOAPIC_INTREN(irq);
 560 }
 561
 562 static void
 563 ioapic_abi_intr_disable(int irq)
 564 {
 565         const struct ioapic_irqmap *map;
 566
 567         KASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS,
 568             ("ioapic disable, invalid irq %d\n", irq));
 569
 570         map = &ioapic_irqmaps[mycpuid][irq];
 571         KASSERT(IOAPIC_IMT_ISHWI(map),
 572             ("ioapic disable, not hwi irq %d, type %d, cpu%d\n",
 573              irq, map->im_type, mycpuid));
 574         if (map->im_type != IOAPIC_IMT_LEGACY)
 575                 return;
 576
 577         IOAPIC_INTRDIS(irq);
 578 }
 579
 580 static void
 581 ioapic_abi_finalize(void)
 582 {
 583         KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC);
 584         KKASSERT(ioapic_enable);
 585
 586         /*
 587          * If an IMCR is present, program bit 0 to disconnect the 8259
 588          * from the BSP.
 589          */
 590         if (imcr_present) {
 591                 outb(0x22, 0x70);       /* select IMCR */
 592                 outb(0x23, 0x01);       /* disconnect 8259 */
 593         }
 594 }
 595
 596 /*
 597  * This routine is called after physical interrupts are enabled but before
 598  * the critical section is released.  We need to clean out any interrupts
 599  * that had already been posted to the cpu.
 600  */
 601 static void
 602 ioapic_abi_cleanup(void)
 603 {
 604         bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
 605 }
 606
 607 /* Must never be called */
 608 static void
 609 ioapic_abi_stabilize(void)
 610 {
 611         panic("ioapic_stabilize() is called\n");
 612 }
 613
 614 static void
 615 ioapic_abi_intr_setup(int intr, int flags)
 616 {
 617         const struct ioapic_irqmap *map;
 618         int vector, select;
 619         uint32_t value;
 620         u_long ef;
 621
 622         KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
 623             ("ioapic setup, invalid irq %d\n", intr));
 624
 625         map = &ioapic_irqmaps[mycpuid][intr];
 626         KASSERT(IOAPIC_IMT_ISHWI(map),
 627             ("ioapic setup, not hwi irq %d, type %d, cpu%d",
 628              intr, map->im_type, mycpuid));
 629         if (map->im_type != IOAPIC_IMT_LEGACY)
 630                 return;
 631
 632         KASSERT(ioapic_irqs[intr].io_addr != NULL,
 633             ("ioapic setup, no GSI information, irq %d\n", intr));
 634
 635         ef = read_eflags();
 636         cpu_disable_intr();
 637
 638         vector = IDT_OFFSET + intr;
 639
 640         /*
 641          * Now reprogram the vector in the IO APIC.  In order to avoid
 642          * losing an EOI for a level interrupt, which is vector based,
 643          * make sure that the IO APIC is programmed for edge-triggering
 644          * first, then reprogrammed with the new vector.  This should
 645          * clear the IRR bit.
 646          */
 647         imen_lock();
 648
 649         select = ioapic_irqs[intr].io_idx;
 650         value = ioapic_read(ioapic_irqs[intr].io_addr, select);
 651         value |= IOART_INTMSET;
 652
 653         ioapic_write(ioapic_irqs[intr].io_addr, select,
 654             (value & ~APIC_TRIGMOD_MASK));
 655         ioapic_write(ioapic_irqs[intr].io_addr, select,
 656             (value & ~IOART_INTVEC) | vector);
 657
 658         imen_unlock();
 659
 660         IOAPIC_INTREN(intr);
 661
 662         write_eflags(ef);
 663 }
 664
 665 static void
 666 ioapic_abi_intr_teardown(int intr)
 667 {
 668         const struct ioapic_irqmap *map;
 669         int vector, select;
 670         uint32_t value;
 671         u_long ef;
 672
 673         KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
 674             ("ioapic teardown, invalid irq %d\n", intr));
 675
 676         map = &ioapic_irqmaps[mycpuid][intr];
 677         KASSERT(IOAPIC_IMT_ISHWI(map),
 678             ("ioapic teardown, not hwi irq %d, type %d, cpu%d",
 679              intr, map->im_type, mycpuid));
 680         if (map->im_type != IOAPIC_IMT_LEGACY)
 681                 return;
 682
 683         KASSERT(ioapic_irqs[intr].io_addr != NULL,
 684             ("ioapic teardown, no GSI information, irq %d\n", intr));
 685
 686         ef = read_eflags();
 687         cpu_disable_intr();
 688
 689         /*
 690          * Teardown an interrupt vector.  The vector should already be
 691          * installed in the cpu's IDT, but make sure.
 692          */
 693         IOAPIC_INTRDIS(intr);
 694
 695         vector = IDT_OFFSET + intr;
 696
 697         /*
 698          * In order to avoid losing an EOI for a level interrupt, which
 699          * is vector based, make sure that the IO APIC is programmed for
 700          * edge-triggering first, then reprogrammed with the new vector.
 701          * This should clear the IRR bit.
 702          */
 703         imen_lock();
 704
 705         select = ioapic_irqs[intr].io_idx;
 706         value = ioapic_read(ioapic_irqs[intr].io_addr, select);
 707
 708         ioapic_write(ioapic_irqs[intr].io_addr, select,
 709             (value & ~APIC_TRIGMOD_MASK));
 710         ioapic_write(ioapic_irqs[intr].io_addr, select,
 711             (value & ~IOART_INTVEC) | vector);
 712
 713         imen_unlock();
 714
 715         write_eflags(ef);
 716 }
 717
 718 static void
 719 ioapic_abi_setdefault(void)
 720 {
 721         int intr;
 722
 723         for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) {
 724                 if (intr == IOAPIC_HWI_SYSCALL)
 725                         continue;
 726                 setidt(IDT_OFFSET + intr, ioapic_intr[intr], SDT_SYS386IGT,
 727                        SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
 728         }
 729 }
 730
 731 static void
 732 ioapic_abi_initmap(void)
 733 {
 734         int cpu;
 735
 736         kgetenv_int("hw.ioapic.gsi.balance", &ioapic_abi_gsi_balance);
 737
 738         kgetenv_int("hw.ioapic.msi_start", &ioapic_abi_msi_start);
 739         ioapic_abi_msi_start &= ~0x1f;  /* MUST be 32 aligned */
 740
 741         /*
 742          * NOTE: ncpus is not ready yet
 743          */
 744         for (cpu = 0; cpu < MAXCPU; ++cpu) {
 745                 int i;
 746
 747                 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i) {
 748                         ioapic_irqmaps[cpu][i].im_gsi = -1;
 749                         ioapic_irqmaps[cpu][i].im_msi_base = -1;
 750                 }
 751                 ioapic_irqmaps[cpu][IOAPIC_HWI_SYSCALL].im_type =
 752                     IOAPIC_IMT_SYSCALL;
 753         }
 754 }
 755
 756 void
 757 ioapic_set_legacy_irqmap(int irq, int gsi, enum intr_trigger trig,
 758     enum intr_polarity pola)
 759 {
 760         struct ioapic_irqinfo *info;
 761         struct ioapic_irqmap *map;
 762         void *ioaddr;
 763         int pin, cpuid;
 764
 765         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
 766         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
 767
 768         KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
 769         if (irq > ioapic_abi_legacy_irq_max)
 770                 ioapic_abi_legacy_irq_max = irq;
 771
 772         cpuid = ioapic_abi_gsi_cpuid(irq, gsi);
 773
 774         map = &ioapic_irqmaps[cpuid][irq];
 775
 776         KKASSERT(map->im_type == IOAPIC_IMT_UNUSED);
 777         map->im_type = IOAPIC_IMT_LEGACY;
 778
 779         map->im_gsi = gsi;
 780         map->im_trig = trig;
 781         map->im_pola = pola;
 782
 783         if (bootverbose) {
 784                 kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n",
 785                         irq, map->im_gsi,
 786                         intr_str_trigger(map->im_trig),
 787                         intr_str_polarity(map->im_pola));
 788         }
 789
 790         pin = ioapic_gsi_pin(map->im_gsi);
 791         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
 792
 793         info = &ioapic_irqs[irq];
 794
 795         imen_lock();
 796
 797         info->io_addr = ioaddr;
 798         info->io_idx = IOAPIC_REDTBL + (2 * pin);
 799         info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
 800         if (map->im_trig == INTR_TRIGGER_LEVEL)
 801                 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
 802
 803         ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
 804             map->im_trig, map->im_pola, cpuid);
 805
 806         imen_unlock();
 807 }
 808
 809 void
 810 ioapic_fixup_legacy_irqmaps(void)
 811 {
 812         int cpu;
 813
 814         ioapic_abi_legacy_irq_max += 1;
 815         if (bootverbose) {
 816                 kprintf("IOAPIC: legacy irq max %d\n",
 817                     ioapic_abi_legacy_irq_max);
 818         }
 819
 820         for (cpu = 0; cpu < ncpus; ++cpu) {
 821                 int i;
 822
 823                 for (i = 0; i < ioapic_abi_legacy_irq_max; ++i) {
 824                         struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][i];
 825
 826                         if (map->im_type == IOAPIC_IMT_UNUSED) {
 827                                 map->im_type = IOAPIC_IMT_RESERVED;
 828                                 if (bootverbose) {
 829                                         kprintf("IOAPIC: "
 830                                             "cpu%d irq %d reserved\n", cpu, i);
 831                                 }
 832                         }
 833                 }
 834         }
 835 }
 836
 837 int
 838 ioapic_find_legacy_by_gsi(int gsi, enum intr_trigger trig,
 839     enum intr_polarity pola)
 840 {
 841         int cpu;
 842
 843         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
 844         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
 845
 846         for (cpu = 0; cpu < ncpus; ++cpu) {
 847                 int irq;
 848
 849                 for (irq = 0; irq < ioapic_abi_legacy_irq_max; ++irq) {
 850                         const struct ioapic_irqmap *map =
 851                             &ioapic_irqmaps[cpu][irq];
 852
 853                         if (map->im_gsi == gsi) {
 854                                 KKASSERT(map->im_type == IOAPIC_IMT_LEGACY);
 855
 856                                 if (map->im_flags & IOAPIC_IMF_CONF) {
 857                                         if (map->im_trig != trig ||
 858                                             map->im_pola != pola)
 859                                                 return -1;
 860                                 }
 861                                 return irq;
 862                         }
 863                 }
 864         }
 865         return -1;
 866 }
 867
 868 int
 869 ioapic_find_legacy_by_irq(int irq, enum intr_trigger trig,
 870     enum intr_polarity pola)
 871 {
 872         int cpu;
 873
 874         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
 875         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
 876
 877         if (irq < 0 || irq >= ioapic_abi_legacy_irq_max)
 878                 return -1;
 879
 880         for (cpu = 0; cpu < ncpus; ++cpu) {
 881                 const struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][irq];
 882
 883                 if (map->im_type == IOAPIC_IMT_LEGACY) {
 884                         if (map->im_flags & IOAPIC_IMF_CONF) {
 885                                 if (map->im_trig != trig ||
 886                                     map->im_pola != pola)
 887                                         return -1;
 888                         }
 889                         return irq;
 890                 }
 891         }
 892         return -1;
 893 }
 894
 895 static void
 896 ioapic_abi_legacy_intr_config(int irq, enum intr_trigger trig,
 897     enum intr_polarity pola)
 898 {
 899         struct ioapic_irqinfo *info;
 900         struct ioapic_irqmap *map = NULL;
 901         void *ioaddr;
 902         int pin, cpuid;
 903
 904         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
 905         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
 906
 907         KKASSERT(irq >= 0 && irq < ioapic_abi_legacy_irq_max);
 908         for (cpuid = 0; cpuid < ncpus; ++cpuid) {
 909                 map = &ioapic_irqmaps[cpuid][irq];
 910                 if (map->im_type == IOAPIC_IMT_LEGACY)
 911                         break;
 912         }
 913         KKASSERT(cpuid < ncpus);
 914
 915 #ifdef notyet
 916         if (map->im_flags & IOAPIC_IMF_CONF) {
 917                 if (trig != map->im_trig) {
 918                         panic("ioapic_intr_config: trig %s -> %s\n",
 919                               intr_str_trigger(map->im_trig),
 920                               intr_str_trigger(trig));
 921                 }
 922                 if (pola != map->im_pola) {
 923                         panic("ioapic_intr_config: pola %s -> %s\n",
 924                               intr_str_polarity(map->im_pola),
 925                               intr_str_polarity(pola));
 926                 }
 927                 return;
 928         }
 929 #endif
 930         map->im_flags |= IOAPIC_IMF_CONF;
 931
 932         if (trig == map->im_trig && pola == map->im_pola)
 933                 return;
 934
 935         if (bootverbose) {
 936                 kprintf("IOAPIC: irq %d, gsi %d %s/%s -> %s/%s\n",
 937                         irq, map->im_gsi,
 938                         intr_str_trigger(map->im_trig),
 939                         intr_str_polarity(map->im_pola),
 940                         intr_str_trigger(trig),
 941                         intr_str_polarity(pola));
 942         }
 943         map->im_trig = trig;
 944         map->im_pola = pola;
 945
 946         pin = ioapic_gsi_pin(map->im_gsi);
 947         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
 948
 949         info = &ioapic_irqs[irq];
 950
 951         imen_lock();
 952
 953         info->io_flags &= ~IOAPIC_IRQI_FLAG_LEVEL;
 954         if (map->im_trig == INTR_TRIGGER_LEVEL)
 955                 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
 956
 957         ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
 958             map->im_trig, map->im_pola, cpuid);
 959
 960         imen_unlock();
 961 }
 962
 963 int
 964 ioapic_conf_legacy_extint(int irq)
 965 {
 966         struct ioapic_irqinfo *info;
 967         struct ioapic_irqmap *map;
 968         void *ioaddr;
 969         int pin, error, vec;
 970
 971         /* XXX only irq0 is allowed */
 972         KKASSERT(irq == 0);
 973
 974         vec = IDT_OFFSET + irq;
 975
 976         if (ioapic_abi_extint_irq == irq)
 977                 return 0;
 978         else if (ioapic_abi_extint_irq >= 0)
 979                 return EEXIST;
 980
 981         error = icu_ioapic_extint(irq, vec);
 982         if (error)
 983                 return error;
 984
 985         /* ExtINT is always targeted to cpu0 */
 986         map = &ioapic_irqmaps[0][irq];
 987
 988         KKASSERT(map->im_type == IOAPIC_IMT_RESERVED ||
 989                  map->im_type == IOAPIC_IMT_LEGACY);
 990         if (map->im_type == IOAPIC_IMT_LEGACY) {
 991                 if (map->im_flags & IOAPIC_IMF_CONF)
 992                         return EEXIST;
 993         }
 994         ioapic_abi_extint_irq = irq;
 995
 996         map->im_type = IOAPIC_IMT_LEGACY;
 997         map->im_trig = INTR_TRIGGER_EDGE;
 998         map->im_pola = INTR_POLARITY_HIGH;
 999         map->im_flags = IOAPIC_IMF_CONF;
1000
1001         map->im_gsi = ioapic_extpin_gsi();
1002         KKASSERT(map->im_gsi >= 0);
1003
1004         if (bootverbose) {
1005                 kprintf("IOAPIC: irq %d -> extint gsi %d %s/%s\n",
1006                         irq, map->im_gsi,
1007                         intr_str_trigger(map->im_trig),
1008                         intr_str_polarity(map->im_pola));
1009         }
1010
1011         pin = ioapic_gsi_pin(map->im_gsi);
1012         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
1013
1014         info = &ioapic_irqs[irq];
1015
1016         imen_lock();
1017
1018         info->io_addr = ioaddr;
1019         info->io_idx = IOAPIC_REDTBL + (2 * pin);
1020         info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
1021
1022         ioapic_extpin_setup(ioaddr, pin, vec);
1023
1024         imen_unlock();
1025
1026         return 0;
1027 }
1028
1029 static int
1030 ioapic_abi_legacy_intr_cpuid(int irq)
1031 {
1032         const struct ioapic_irqmap *map = NULL;
1033         int cpuid;
1034
1035         KKASSERT(irq >= 0 && irq < ioapic_abi_legacy_irq_max);
1036
1037         for (cpuid = 0; cpuid < ncpus; ++cpuid) {
1038                 map = &ioapic_irqmaps[cpuid][irq];
1039                 if (map->im_type == IOAPIC_IMT_LEGACY)
1040                         return cpuid;
1041         }
1042
1043         /* XXX some drivers tries to peek at reserved IRQs */
1044         for (cpuid = 0; cpuid < ncpus; ++cpuid) {
1045                 map = &ioapic_irqmaps[cpuid][irq];
1046                 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED);
1047         }
1048         return 0;
1049 }
1050
1051 static int
1052 ioapic_abi_gsi_cpuid(int irq, int gsi)
1053 {
1054         char envpath[32];
1055         int cpuid = -1;
1056
1057         KKASSERT(gsi >= 0);
1058
1059         if (irq == 0 || gsi == 0) {
1060                 if (bootverbose) {
1061                         kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (0)\n",
1062                             irq, gsi);
1063                 }
1064                 return 0;
1065         }
1066
1067         if (irq == acpi_sci_irqno()) {
1068                 if (bootverbose) {
1069                         kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (sci)\n",
1070                             irq, gsi);
1071                 }
1072                 return 0;
1073         }
1074
1075         ksnprintf(envpath, sizeof(envpath), "hw.ioapic.gsi.%d.cpu", gsi);
1076         kgetenv_int(envpath, &cpuid);
1077
1078         if (cpuid < 0) {
1079                 if (!ioapic_abi_gsi_balance) {
1080                         if (bootverbose) {
1081                                 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 "
1082                                     "(fixed)\n", irq, gsi);
1083                         }
1084                         return 0;
1085                 }
1086
1087                 cpuid = gsi % ncpus;
1088                 if (bootverbose) {
1089                         kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (auto)\n",
1090                             irq, gsi, cpuid);
1091                 }
1092         } else if (cpuid >= ncpus) {
1093                 cpuid = ncpus - 1;
1094                 if (bootverbose) {
1095                         kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (fixup)\n",
1096                             irq, gsi, cpuid);
1097                 }
1098         } else {
1099                 if (bootverbose) {
1100                         kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (user)\n",
1101                             irq, gsi, cpuid);
1102                 }
1103         }
1104         return cpuid;
1105 }
1106
1107 static void
1108 ioapic_abi_rman_setup(struct rman *rm)
1109 {
1110         int start, end, i;
1111
1112         KASSERT(rm->rm_cpuid >= 0 && rm->rm_cpuid < MAXCPU,
1113             ("invalid rman cpuid %d", rm->rm_cpuid));
1114
1115         start = end = -1;
1116         for (i = 0; i < IOAPIC_HWI_VECTORS; ++i) {
1117                 const struct ioapic_irqmap *map =
1118                     &ioapic_irqmaps[rm->rm_cpuid][i];
1119
1120                 if (start < 0) {
1121                         if (IOAPIC_IMT_ISHWI(map))
1122                                 start = end = i;
1123                 } else {
1124                         if (IOAPIC_IMT_ISHWI(map)) {
1125                                 end = i;
1126                         } else {
1127                                 KKASSERT(end >= 0);
1128                                 if (bootverbose) {
1129                                         kprintf("IOAPIC: rman cpu%d %d - %d\n",
1130                                             rm->rm_cpuid, start, end);
1131                                 }
1132                                 if (rman_manage_region(rm, start, end)) {
1133                                         panic("rman_manage_region"
1134                                             "(cpu%d %d - %d)", rm->rm_cpuid,
1135                                             start, end);
1136                                 }
1137                                 start = end = -1;
1138                         }
1139                 }
1140         }
1141         if (start >= 0) {
1142                 KKASSERT(end >= 0);
1143                 if (bootverbose) {
1144                         kprintf("IOAPIC: rman cpu%d %d - %d\n",
1145                             rm->rm_cpuid, start, end);
1146                 }
1147                 if (rman_manage_region(rm, start, end)) {
1148                         panic("rman_manage_region(cpu%d %d - %d)",
1149                             rm->rm_cpuid, start, end);
1150                 }
1151         }
1152 }
1153
1154 static int
1155 ioapic_abi_msi_alloc(int intrs[], int count, int cpuid)
1156 {
1157         int i, error;
1158
1159         KASSERT(cpuid >= 0 && cpuid < ncpus,
1160             ("invalid cpuid %d", cpuid));
1161
1162         KASSERT(count > 0 && count <= 32, ("invalid count %d\n", count));
1163         KASSERT((count & (count - 1)) == 0,
1164             ("count %d is not power of 2\n", count));
1165
1166         lwkt_gettoken(&ioapic_irqmap_tok);
1167
1168         /*
1169          * NOTE:
1170          * Since IDT_OFFSET is 32, which is the maximum valid 'count',
1171          * we do not need to find out the first properly aligned
1172          * interrupt vector.
1173          */
1174
1175         error = EMSGSIZE;
1176         for (i = ioapic_abi_msi_start; i < IOAPIC_HWI_VECTORS; i += count) {
1177                 int j;
1178
1179                 if (ioapic_irqmaps[cpuid][i].im_type != IOAPIC_IMT_UNUSED)
1180                         continue;
1181
1182                 for (j = 1; j < count; ++j) {
1183                         if (ioapic_irqmaps[cpuid][i + j].im_type !=
1184                             IOAPIC_IMT_UNUSED)
1185                                 break;
1186                 }
1187                 if (j != count)
1188                         continue;
1189
1190                 for (j = 0; j < count; ++j) {
1191                         int intr = i + j, cpu;
1192
1193                         for (cpu = 0; cpu < ncpus; ++cpu) {
1194                                 struct ioapic_irqmap *map;
1195
1196                                 map = &ioapic_irqmaps[cpu][intr];
1197                                 KASSERT(map->im_msi_base < 0,
1198                                     ("intr %d cpu%d, stale MSI-base %d\n",
1199                                      intr, cpu, map->im_msi_base));
1200                                 KASSERT(map->im_type == IOAPIC_IMT_UNUSED,
1201                                     ("intr %d cpu%d, already allocated\n",
1202                                      intr, cpu));
1203
1204                                 if (cpu == cpuid) {
1205                                         map->im_type = IOAPIC_IMT_MSI;
1206                                         map->im_msi_base = i;
1207                                 } else {
1208                                         map->im_type = IOAPIC_IMT_SHADOW;
1209                                 }
1210                         }
1211
1212                         intrs[j] = intr;
1213                         msi_setup(intr);
1214
1215                         if (bootverbose) {
1216                                 kprintf("alloc MSI intr %d on cpu%d\n",
1217                                     intr, cpuid);
1218                         }
1219                 }
1220                 error = 0;
1221                 break;
1222         }
1223
1224         lwkt_reltoken(&ioapic_irqmap_tok);
1225
1226         return error;
1227 }
1228
1229 static void
1230 ioapic_abi_msi_release(const int intrs[], int count, int cpuid)
1231 {
1232         int i, msi_base = -1, intr_next = -1, mask;
1233
1234         KASSERT(cpuid >= 0 && cpuid < ncpus,
1235             ("invalid cpuid %d", cpuid));
1236
1237         KASSERT(count > 0 && count <= 32, ("invalid count %d\n", count));
1238
1239         mask = count - 1;
1240         KASSERT((count & mask) == 0, ("count %d is not power of 2\n", count));
1241
1242         lwkt_gettoken(&ioapic_irqmap_tok);
1243
1244         for (i = 0; i < count; ++i) {
1245                 int intr = intrs[i], cpu;
1246
1247                 KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
1248                     ("invalid intr %d\n", intr));
1249
1250                 for (cpu = 0; cpu < ncpus; ++cpu) {
1251                         struct ioapic_irqmap *map;
1252
1253                         map = &ioapic_irqmaps[cpu][intr];
1254
1255                         if (cpu == cpuid) {
1256                                 KASSERT(map->im_type == IOAPIC_IMT_MSI,
1257                                     ("try release non-MSI intr %d cpu%d, "
1258                                      "type %d\n", intr, cpu, map->im_type));
1259                                 KASSERT(map->im_msi_base >= 0 &&
1260                                     map->im_msi_base <= intr,
1261                                     ("intr %d cpu%d, invalid MSI-base %d\n",
1262                                      intr, cpu, map->im_msi_base));
1263                                 KASSERT((map->im_msi_base & mask) == 0,
1264                                     ("intr %d cpu%d, MSI-base %d is "
1265                                      "not proper aligned %d\n",
1266                                      intr, cpu, map->im_msi_base, count));
1267
1268                                 if (msi_base < 0) {
1269                                         msi_base = map->im_msi_base;
1270                                 } else {
1271                                         KASSERT(map->im_msi_base == msi_base,
1272                                             ("intr %d cpu%d, "
1273                                              "inconsistent MSI-base, "
1274                                              "was %d, now %d\n",
1275                                              intr, cpu,
1276                                              msi_base, map->im_msi_base));
1277                                 }
1278                                 map->im_msi_base = -1;
1279                         } else {
1280                                 KASSERT(map->im_type == IOAPIC_IMT_SHADOW,
1281                                     ("try release non-MSIsh intr %d cpu%d, "
1282                                      "type %d\n", intr, cpu, map->im_type));
1283                                 KASSERT(map->im_msi_base < 0,
1284                                     ("intr %d cpu%d, invalid MSIsh-base %d\n",
1285                                      intr, cpu, map->im_msi_base));
1286                         }
1287                         map->im_type = IOAPIC_IMT_UNUSED;
1288                 }
1289
1290                 if (intr_next < intr)
1291                         intr_next = intr;
1292
1293                 if (bootverbose)
1294                         kprintf("release MSI intr %d on cpu%d\n", intr, cpuid);
1295         }
1296
1297         KKASSERT(intr_next > 0);
1298         KKASSERT(msi_base >= 0);
1299
1300         ++intr_next;
1301         if (intr_next < IOAPIC_HWI_VECTORS) {
1302                 int cpu;
1303
1304                 for (cpu = 0; cpu < ncpus; ++cpu) {
1305                         const struct ioapic_irqmap *map =
1306                             &ioapic_irqmaps[cpu][intr_next];
1307
1308                         if (map->im_type == IOAPIC_IMT_MSI) {
1309                                 KASSERT(map->im_msi_base != msi_base,
1310                                     ("more than %d MSI was allocated\n", count));
1311                         }
1312                 }
1313         }
1314
1315         lwkt_reltoken(&ioapic_irqmap_tok);
1316 }
1317
1318 static void
1319 ioapic_abi_msi_map(int intr, uint64_t *addr, uint32_t *data, int cpuid)
1320 {
1321         const struct ioapic_irqmap *map;
1322
1323         KASSERT(cpuid >= 0 && cpuid < ncpus,
1324             ("invalid cpuid %d", cpuid));
1325
1326         KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
1327             ("invalid intr %d\n", intr));
1328
1329         lwkt_gettoken(&ioapic_irqmap_tok);
1330
1331         map = &ioapic_irqmaps[cpuid][intr];
1332         KASSERT(map->im_type == IOAPIC_IMT_MSI,
1333             ("try map non-MSI intr %d, type %d\n", intr, map->im_type));
1334         KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr,
1335             ("intr %d, invalid MSI-base %d\n", intr, map->im_msi_base));
1336
1337         msi_map(map->im_msi_base, addr, data, cpuid);
1338
1339         if (bootverbose)
1340                 kprintf("map MSI intr %d on cpu%d\n", intr, cpuid);
1341
1342         lwkt_reltoken(&ioapic_irqmap_tok);
1343 }