2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
3 * and Duncan Barclay<dmlb@dmlb.org>
4 * Modifications for FreeBSD-stable by Edwin Groothuis
5 * <edwin at mavetju.org
6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v
32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.40 2008/09/17 08:51:29 sephe Exp $
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sockio.h>
39 #include <sys/malloc.h>
40 #include <sys/interrupt.h>
41 #include <sys/kernel.h>
42 #include <sys/socket.h>
43 #include <sys/queue.h>
46 #include <sys/thread2.h>
49 #include <net/ifq_var.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
57 #include <net/if_types.h>
58 #include <net/vlan/if_vlan_var.h>
60 #include <netinet/in_systm.h>
61 #include <netinet/in.h>
62 #include <netinet/ip.h>
64 #include <bus/pci/pcireg.h>
65 #include <bus/pci/pcivar.h>
66 #include <bus/pci/pcidevs.h>
68 #include <dev/netif/mii_layer/mii.h>
69 #include <dev/netif/mii_layer/miivar.h>
71 #include <dev/netif/bfe/if_bfereg.h>
73 MODULE_DEPEND(bfe, pci, 1, 1, 1);
74 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
76 /* "controller miibus0" required. See GENERIC if you get errors here. */
77 #include "miibus_if.h"
79 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */
81 static struct bfe_type bfe_devs[] = {
82 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401,
83 "Broadcom BCM4401 Fast Ethernet" },
84 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0,
85 "Broadcom BCM4401-B0 Fast Ethernet" },
86 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4402,
87 "Broadcom BCM4402 Fast Ethernet" },
91 static int bfe_probe(device_t);
92 static int bfe_attach(device_t);
93 static int bfe_detach(device_t);
94 static void bfe_intr(void *);
95 static void bfe_start(struct ifnet *);
96 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
97 static void bfe_init(void *);
98 static void bfe_stop(struct bfe_softc *);
99 static void bfe_watchdog(struct ifnet *);
100 static void bfe_shutdown(device_t);
101 static void bfe_tick(void *);
102 static void bfe_txeof(struct bfe_softc *);
103 static void bfe_rxeof(struct bfe_softc *);
104 static void bfe_set_rx_mode(struct bfe_softc *);
105 static int bfe_list_rx_init(struct bfe_softc *);
106 static int bfe_newbuf(struct bfe_softc *, int, int);
107 static void bfe_setup_rxdesc(struct bfe_softc *, int);
108 static void bfe_rx_ring_free(struct bfe_softc *);
110 static void bfe_pci_setup(struct bfe_softc *, uint32_t);
111 static int bfe_ifmedia_upd(struct ifnet *);
112 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
113 static int bfe_miibus_readreg(device_t, int, int);
114 static int bfe_miibus_writereg(device_t, int, int, int);
115 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t,
117 static void bfe_get_config(struct bfe_softc *sc);
118 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *);
119 static void bfe_stats_update(struct bfe_softc *);
120 static void bfe_clear_stats (struct bfe_softc *);
121 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*);
122 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t);
123 static int bfe_resetphy(struct bfe_softc *);
124 static int bfe_setupphy(struct bfe_softc *);
125 static void bfe_chip_reset(struct bfe_softc *);
126 static void bfe_chip_halt(struct bfe_softc *);
127 static void bfe_core_reset(struct bfe_softc *);
128 static void bfe_core_disable(struct bfe_softc *);
129 static int bfe_dma_alloc(device_t);
130 static void bfe_dma_free(struct bfe_softc *);
131 static void bfe_cam_write(struct bfe_softc *, u_char *, int);
133 static device_method_t bfe_methods[] = {
134 /* Device interface */
135 DEVMETHOD(device_probe, bfe_probe),
136 DEVMETHOD(device_attach, bfe_attach),
137 DEVMETHOD(device_detach, bfe_detach),
138 DEVMETHOD(device_shutdown, bfe_shutdown),
141 DEVMETHOD(bus_print_child, bus_generic_print_child),
142 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
145 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
146 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
151 static driver_t bfe_driver = {
154 sizeof(struct bfe_softc)
157 static devclass_t bfe_devclass;
159 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
160 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
163 * Probe for a Broadcom 4401 chip.
166 bfe_probe(device_t dev)
169 uint16_t vendor, product;
171 vendor = pci_get_vendor(dev);
172 product = pci_get_device(dev);
174 for (t = bfe_devs; t->bfe_name != NULL; t++) {
175 if (vendor == t->bfe_vid && product == t->bfe_did) {
176 device_set_desc(dev, t->bfe_name);
185 bfe_dma_alloc(device_t dev)
187 struct bfe_softc *sc = device_get_softc(dev);
189 int error, i, tx_pos = 0, rx_pos = 0;
192 * Parent tag. Apparently the chip cannot handle any DMA address
193 * greater than BFE_BUS_SPACE_MAXADDR (1GB).
195 error = bus_dma_tag_create(NULL, /* parent */
196 1, 0, /* alignment, boundary */
197 BFE_BUS_SPACE_MAXADDR, /* lowaddr */
198 BUS_SPACE_MAXADDR, /* highaddr */
199 NULL, NULL, /* filter, filterarg */
200 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
201 0, /* num of segments */
202 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */
204 &sc->bfe_parent_tag);
206 device_printf(dev, "could not allocate parent dma tag\n");
210 /* Allocate TX ring */
211 error = bus_dmamem_coherent(sc->bfe_parent_tag, PAGE_SIZE, 0,
212 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
214 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
216 device_printf(dev, "could not allocate TX list\n");
219 sc->bfe_tx_tag = dmem.dmem_tag;
220 sc->bfe_tx_map = dmem.dmem_map;
221 sc->bfe_tx_list = dmem.dmem_addr;
222 sc->bfe_tx_dma = dmem.dmem_busaddr;
224 /* Allocate RX ring */
225 error = bus_dmamem_coherent(sc->bfe_parent_tag, PAGE_SIZE, 0,
226 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
228 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
230 device_printf(dev, "could not allocate RX list\n");
233 sc->bfe_rx_tag = dmem.dmem_tag;
234 sc->bfe_rx_map = dmem.dmem_map;
235 sc->bfe_rx_list = dmem.dmem_addr;
236 sc->bfe_rx_dma = dmem.dmem_busaddr;
238 /* Tag for RX mbufs */
239 error = bus_dma_tag_create(sc->bfe_parent_tag, 1, 0,
240 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
242 MCLBYTES, 1, MCLBYTES,
243 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
246 device_printf(dev, "could not allocate dma tag for RX mbufs\n");
250 error = bus_dmamap_create(sc->bfe_rxbuf_tag, BUS_DMA_WAITOK,
253 device_printf(dev, "could not create RX mbuf tmp map\n");
254 bus_dma_tag_destroy(sc->bfe_rxbuf_tag);
255 sc->bfe_rxbuf_tag = NULL;
259 /* Allocate dma maps for RX list */
260 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
261 error = bus_dmamap_create(sc->bfe_rxbuf_tag, BUS_DMA_WAITOK,
262 &sc->bfe_rx_ring[i].bfe_map);
265 device_printf(dev, "cannot create DMA map for RX\n");
269 rx_pos = BFE_RX_LIST_CNT;
271 /* Tag for TX mbufs */
272 error = bus_dma_tag_create(sc->bfe_parent_tag, 1, 0,
273 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
275 MCLBYTES, BFE_MAXSEGS, MCLBYTES,
276 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
279 device_printf(dev, "could not allocate dma tag for TX mbufs\n");
283 /* Allocate dmamaps for TX list */
284 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
285 error = bus_dmamap_create(sc->bfe_txbuf_tag, BUS_DMA_WAITOK,
286 &sc->bfe_tx_ring[i].bfe_map);
289 device_printf(dev, "cannot create DMA map for TX\n");
297 if (sc->bfe_rxbuf_tag != NULL) {
298 for (i = 0; i < rx_pos; ++i) {
299 bus_dmamap_destroy(sc->bfe_rxbuf_tag,
300 sc->bfe_rx_ring[i].bfe_map);
302 bus_dmamap_destroy(sc->bfe_rxbuf_tag, sc->bfe_rx_tmpmap);
303 bus_dma_tag_destroy(sc->bfe_rxbuf_tag);
304 sc->bfe_rxbuf_tag = NULL;
307 if (sc->bfe_txbuf_tag != NULL) {
308 for (i = 0; i < tx_pos; ++i) {
309 bus_dmamap_destroy(sc->bfe_txbuf_tag,
310 sc->bfe_tx_ring[i].bfe_map);
312 bus_dma_tag_destroy(sc->bfe_txbuf_tag);
313 sc->bfe_txbuf_tag = NULL;
319 bfe_attach(device_t dev)
322 struct bfe_softc *sc;
325 sc = device_get_softc(dev);
328 callout_init(&sc->bfe_stat_timer);
332 * Handle power management nonsense.
334 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
335 uint32_t membase, irq;
337 /* Save important PCI config data. */
338 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4);
339 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4);
341 /* Reset the power state. */
342 device_printf(dev, "chip is in D%d power mode"
343 " -- setting to D0\n", pci_get_powerstate(dev));
345 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
347 /* Restore PCI config data. */
348 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4);
349 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4);
351 #endif /* !BURN_BRIDGE */
354 * Map control/status registers.
356 pci_enable_busmaster(dev);
359 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
361 if (sc->bfe_res == NULL) {
362 device_printf(dev, "couldn't map memory\n");
366 sc->bfe_btag = rman_get_bustag(sc->bfe_res);
367 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res);
369 /* Allocate interrupt */
372 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
373 RF_SHAREABLE | RF_ACTIVE);
374 if (sc->bfe_irq == NULL) {
375 device_printf(dev, "couldn't map interrupt\n");
380 error = bfe_dma_alloc(dev);
382 device_printf(dev, "failed to allocate DMA resources\n");
386 /* Set up ifnet structure */
387 ifp = &sc->arpcom.ac_if;
389 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
390 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
391 ifp->if_ioctl = bfe_ioctl;
392 ifp->if_start = bfe_start;
393 ifp->if_watchdog = bfe_watchdog;
394 ifp->if_init = bfe_init;
395 ifp->if_mtu = ETHERMTU;
396 ifp->if_baudrate = 100000000;
397 ifp->if_capabilities |= IFCAP_VLAN_MTU;
398 ifp->if_capenable |= IFCAP_VLAN_MTU;
399 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
400 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN);
401 ifq_set_ready(&ifp->if_snd);
405 /* Reset the chip and turn on the PHY */
408 if (mii_phy_probe(dev, &sc->bfe_miibus,
409 bfe_ifmedia_upd, bfe_ifmedia_sts)) {
410 device_printf(dev, "MII without any PHY!\n");
415 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
418 * Hook interrupt last to avoid having to lock softc
420 error = bus_setup_intr(dev, sc->bfe_irq, INTR_MPSAFE,
421 bfe_intr, sc, &sc->bfe_intrhand,
422 sc->arpcom.ac_if.if_serializer);
426 device_printf(dev, "couldn't set up irq\n");
430 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bfe_irq));
431 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
439 bfe_detach(device_t dev)
441 struct bfe_softc *sc = device_get_softc(dev);
442 struct ifnet *ifp = &sc->arpcom.ac_if;
444 if (device_is_attached(dev)) {
445 lwkt_serialize_enter(ifp->if_serializer);
448 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand);
449 lwkt_serialize_exit(ifp->if_serializer);
453 if (sc->bfe_miibus != NULL)
454 device_delete_child(dev, sc->bfe_miibus);
455 bus_generic_detach(dev);
457 if (sc->bfe_irq != NULL)
458 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq);
460 if (sc->bfe_res != NULL) {
461 bus_release_resource(dev, SYS_RES_MEMORY, BFE_PCI_MEMLO,
470 * Stop all chip I/O so that the kernel's probe routines don't
471 * get confused by errant DMAs when rebooting.
474 bfe_shutdown(device_t dev)
476 struct bfe_softc *sc = device_get_softc(dev);
477 struct ifnet *ifp = &sc->arpcom.ac_if;
479 lwkt_serialize_enter(ifp->if_serializer);
481 lwkt_serialize_exit(ifp->if_serializer);
485 bfe_miibus_readreg(device_t dev, int phy, int reg)
487 struct bfe_softc *sc;
490 sc = device_get_softc(dev);
491 if (phy != sc->bfe_phyaddr)
493 bfe_readphy(sc, reg, &ret);
499 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
501 struct bfe_softc *sc;
503 sc = device_get_softc(dev);
504 if (phy != sc->bfe_phyaddr)
506 bfe_writephy(sc, reg, val);
512 bfe_tx_ring_free(struct bfe_softc *sc)
516 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
517 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
518 bus_dmamap_unload(sc->bfe_txbuf_tag,
519 sc->bfe_tx_ring[i].bfe_map);
520 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
521 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
524 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
525 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE);
529 bfe_rx_ring_free(struct bfe_softc *sc)
533 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
534 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
535 bus_dmamap_unload(sc->bfe_rxbuf_tag,
536 sc->bfe_rx_ring[i].bfe_map);
537 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
538 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
541 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
542 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
546 bfe_list_rx_init(struct bfe_softc *sc)
550 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
551 error = bfe_newbuf(sc, i, 1);
556 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
557 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
565 bfe_newbuf(struct bfe_softc *sc, int c, int init)
569 bus_dma_segment_t seg;
573 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
576 m->m_len = m->m_pkthdr.len = MCLBYTES;
578 error = bus_dmamap_load_mbuf_segment(sc->bfe_rxbuf_tag,
579 sc->bfe_rx_tmpmap, m,
580 &seg, 1, &nsegs, BUS_DMA_NOWAIT);
584 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
588 KKASSERT(c >= 0 && c < BFE_RX_LIST_CNT);
589 r = &sc->bfe_rx_ring[c];
591 if (r->bfe_mbuf != NULL)
592 bus_dmamap_unload(sc->bfe_rxbuf_tag, r->bfe_map);
595 r->bfe_map = sc->bfe_rx_tmpmap;
596 sc->bfe_rx_tmpmap = map;
599 r->bfe_paddr = seg.ds_addr;
601 bfe_setup_rxdesc(sc, c);
606 bfe_setup_rxdesc(struct bfe_softc *sc, int c)
608 struct bfe_rxheader *rx_header;
614 KKASSERT(c >= 0 && c < BFE_RX_LIST_CNT);
615 r = &sc->bfe_rx_ring[c];
616 d = &sc->bfe_rx_list[c];
618 KKASSERT(r->bfe_mbuf != NULL && r->bfe_paddr != 0);
621 rx_header = mtod(m, struct bfe_rxheader *);
623 rx_header->flags = 0;
624 bus_dmamap_sync(sc->bfe_rxbuf_tag, r->bfe_map, BUS_DMASYNC_PREWRITE);
626 ctrl = ETHER_MAX_LEN + 32;
627 if (c == BFE_RX_LIST_CNT - 1)
628 ctrl |= BFE_DESC_EOT;
630 d->bfe_addr = r->bfe_paddr + BFE_PCI_DMA;
632 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
636 bfe_get_config(struct bfe_softc *sc)
640 bfe_read_eeprom(sc, eeprom);
642 sc->arpcom.ac_enaddr[0] = eeprom[79];
643 sc->arpcom.ac_enaddr[1] = eeprom[78];
644 sc->arpcom.ac_enaddr[2] = eeprom[81];
645 sc->arpcom.ac_enaddr[3] = eeprom[80];
646 sc->arpcom.ac_enaddr[4] = eeprom[83];
647 sc->arpcom.ac_enaddr[5] = eeprom[82];
649 sc->bfe_phyaddr = eeprom[90] & 0x1f;
650 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
652 sc->bfe_core_unit = 0;
653 sc->bfe_dma_offset = BFE_PCI_DMA;
657 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores)
659 uint32_t bar_orig, pci_rev, val;
661 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
662 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
663 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
665 val = CSR_READ_4(sc, BFE_SBINTVEC);
667 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
669 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
670 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
671 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
673 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
677 bfe_clear_stats(struct bfe_softc *sc)
681 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
682 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
684 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
689 bfe_resetphy(struct bfe_softc *sc)
693 bfe_writephy(sc, 0, BMCR_RESET);
695 bfe_readphy(sc, 0, &val);
696 if (val & BMCR_RESET) {
697 if_printf(&sc->arpcom.ac_if,
698 "PHY Reset would not complete.\n");
705 bfe_chip_halt(struct bfe_softc *sc)
707 /* disable interrupts - not that it actually does..*/
708 CSR_WRITE_4(sc, BFE_IMASK, 0);
709 CSR_READ_4(sc, BFE_IMASK);
711 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
712 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
714 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
715 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
720 bfe_chip_reset(struct bfe_softc *sc)
724 /* Set the interrupt vector for the enet core */
725 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
728 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK);
729 if (val == BFE_CLOCK) {
730 /* It is, so shut it down */
731 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
732 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
733 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
734 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
735 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
736 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
737 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0);
738 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
746 * We want the phy registers to be accessible even when
747 * the driver is "downed" so initialize MDC preamble, frequency,
748 * and whether internal or external phy here.
751 /* 4402 has 62.5Mhz SB clock and internal phy */
752 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
754 /* Internal or external PHY? */
755 val = CSR_READ_4(sc, BFE_DEVCTRL);
756 if (!(val & BFE_IPP))
757 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
758 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
759 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
763 /* Enable CRC32 generation and set proper LED modes */
764 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
766 /* Reset or clear powerdown control bit */
767 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
769 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
773 * We don't want lazy interrupts, so just send them at the end of a
776 BFE_OR(sc, BFE_RCV_LAZY, 0);
778 /* Set max lengths, accounting for VLAN tags */
779 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
780 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
782 /* Set watermark XXX - magic */
783 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
786 * Initialise DMA channels - not forgetting dma addresses need to be
787 * added to BFE_PCI_DMA
789 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
790 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
792 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
794 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
801 bfe_core_disable(struct bfe_softc *sc)
803 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
807 * Set reject, wait for it set, then wait for the core to stop being busy
808 * Then set reset and reject and enable the clocks
810 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
811 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
812 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
813 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
815 CSR_READ_4(sc, BFE_SBTMSLOW);
817 /* Leave reset and reject set */
818 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
823 bfe_core_reset(struct bfe_softc *sc)
827 /* Disable the core */
828 bfe_core_disable(sc);
830 /* and bring it back up */
831 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
832 CSR_READ_4(sc, BFE_SBTMSLOW);
835 /* Chip bug, clear SERR, IB and TO if they are set. */
836 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
837 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
838 val = CSR_READ_4(sc, BFE_SBIMSTATE);
839 if (val & (BFE_IBE | BFE_TO))
840 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
842 /* Clear reset and allow it to move through the core */
843 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
844 CSR_READ_4(sc, BFE_SBTMSLOW);
847 /* Leave the clock set */
848 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
849 CSR_READ_4(sc, BFE_SBTMSLOW);
854 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
858 val = ((uint32_t) data[2]) << 24;
859 val |= ((uint32_t) data[3]) << 16;
860 val |= ((uint32_t) data[4]) << 8;
861 val |= ((uint32_t) data[5]);
862 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
863 val = (BFE_CAM_HI_VALID |
864 (((uint32_t) data[0]) << 8) |
865 (((uint32_t) data[1])));
866 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
867 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
868 ((uint32_t)index << BFE_CAM_INDEX_SHIFT)));
869 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
873 bfe_set_rx_mode(struct bfe_softc *sc)
875 struct ifnet *ifp = &sc->arpcom.ac_if;
876 struct ifmultiaddr *ifma;
880 val = CSR_READ_4(sc, BFE_RXCONF);
882 if (ifp->if_flags & IFF_PROMISC)
883 val |= BFE_RXCONF_PROMISC;
885 val &= ~BFE_RXCONF_PROMISC;
887 if (ifp->if_flags & IFF_BROADCAST)
888 val &= ~BFE_RXCONF_DBCAST;
890 val |= BFE_RXCONF_DBCAST;
893 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
894 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++);
896 if (ifp->if_flags & IFF_ALLMULTI) {
897 val |= BFE_RXCONF_ALLMULTI;
899 val &= ~BFE_RXCONF_ALLMULTI;
900 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
901 if (ifma->ifma_addr->sa_family != AF_LINK)
904 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++);
908 CSR_WRITE_4(sc, BFE_RXCONF, val);
909 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
913 bfe_dma_free(struct bfe_softc *sc)
917 if (sc->bfe_tx_tag != NULL) {
918 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
919 if (sc->bfe_tx_list != NULL) {
920 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
922 sc->bfe_tx_list = NULL;
924 bus_dma_tag_destroy(sc->bfe_tx_tag);
925 sc->bfe_tx_tag = NULL;
928 if (sc->bfe_rx_tag != NULL) {
929 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
930 if (sc->bfe_rx_list != NULL) {
931 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
933 sc->bfe_rx_list = NULL;
935 bus_dma_tag_destroy(sc->bfe_rx_tag);
936 sc->bfe_rx_tag = NULL;
939 if (sc->bfe_txbuf_tag != NULL) {
940 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
941 bus_dmamap_destroy(sc->bfe_txbuf_tag,
942 sc->bfe_tx_ring[i].bfe_map);
944 bus_dma_tag_destroy(sc->bfe_txbuf_tag);
945 sc->bfe_txbuf_tag = NULL;
948 if (sc->bfe_rxbuf_tag != NULL) {
949 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
950 bus_dmamap_destroy(sc->bfe_rxbuf_tag,
951 sc->bfe_rx_ring[i].bfe_map);
953 bus_dmamap_destroy(sc->bfe_rxbuf_tag, sc->bfe_rx_tmpmap);
954 bus_dma_tag_destroy(sc->bfe_rxbuf_tag);
955 sc->bfe_rxbuf_tag = NULL;
958 if (sc->bfe_parent_tag != NULL) {
959 bus_dma_tag_destroy(sc->bfe_parent_tag);
960 sc->bfe_parent_tag = NULL;
965 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data)
968 uint16_t *ptr = (uint16_t *)data;
970 for (i = 0; i < 128; i += 2)
971 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
975 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit,
976 u_long timeout, const int clear)
980 for (i = 0; i < timeout; i++) {
981 uint32_t val = CSR_READ_4(sc, reg);
983 if (clear && !(val & bit))
985 if (!clear && (val & bit))
990 if_printf(&sc->arpcom.ac_if,
991 "BUG! Timeout waiting for bit %08x of register "
992 "%x to %s.\n", bit, reg,
993 (clear ? "clear" : "set"));
1000 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val)
1005 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1006 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1007 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
1008 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1009 (reg << BFE_MDIO_RA_SHIFT) |
1010 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
1011 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1012 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
1017 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val)
1021 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1022 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1023 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1024 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1025 (reg << BFE_MDIO_RA_SHIFT) |
1026 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1027 (val & BFE_MDIO_DATA_DATA)));
1028 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1034 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1038 bfe_setupphy(struct bfe_softc *sc)
1042 /* Enable activity LED */
1043 bfe_readphy(sc, 26, &val);
1044 bfe_writephy(sc, 26, val & 0x7fff);
1045 bfe_readphy(sc, 26, &val);
1047 /* Enable traffic meter LED mode */
1048 bfe_readphy(sc, 27, &val);
1049 bfe_writephy(sc, 27, val | (1 << 6));
1055 bfe_stats_update(struct bfe_softc *sc)
1060 val = &sc->bfe_hwstats.tx_good_octets;
1061 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1062 *val++ += CSR_READ_4(sc, reg);
1063 val = &sc->bfe_hwstats.rx_good_octets;
1064 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1065 *val++ += CSR_READ_4(sc, reg);
1069 bfe_txeof(struct bfe_softc *sc)
1071 struct ifnet *ifp = &sc->arpcom.ac_if;
1072 uint32_t i, chipidx;
1074 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1075 chipidx /= sizeof(struct bfe_desc);
1077 i = sc->bfe_tx_cons;
1079 /* Go through the mbufs and free those that have been transmitted */
1080 while (i != chipidx) {
1081 struct bfe_data *r = &sc->bfe_tx_ring[i];
1083 if (r->bfe_mbuf != NULL) {
1085 bus_dmamap_unload(sc->bfe_txbuf_tag, r->bfe_map);
1086 m_freem(r->bfe_mbuf);
1090 KKASSERT(sc->bfe_tx_cnt > 0);
1092 BFE_INC(i, BFE_TX_LIST_CNT);
1095 if (i != sc->bfe_tx_cons) {
1096 sc->bfe_tx_cons = i;
1098 if (sc->bfe_tx_cnt + BFE_SPARE_TXDESC < BFE_TX_LIST_CNT)
1099 ifp->if_flags &= ~IFF_OACTIVE;
1101 if (sc->bfe_tx_cnt == 0)
1105 /* Pass a received packet up the stack */
1107 bfe_rxeof(struct bfe_softc *sc)
1109 struct ifnet *ifp = &sc->arpcom.ac_if;
1111 struct bfe_rxheader *rxheader;
1113 uint32_t cons, status, current, len, flags;
1114 struct mbuf_chain chain[MAXCPU];
1116 cons = sc->bfe_rx_cons;
1117 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1118 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1120 ether_input_chain_init(chain);
1122 while (current != cons) {
1123 r = &sc->bfe_rx_ring[cons];
1124 bus_dmamap_sync(sc->bfe_rxbuf_tag, r->bfe_map,
1125 BUS_DMASYNC_POSTREAD);
1127 KKASSERT(r->bfe_mbuf != NULL);
1129 rxheader = mtod(m, struct bfe_rxheader*);
1130 len = rxheader->len - ETHER_CRC_LEN;
1131 flags = rxheader->flags;
1133 /* flag an error and try again */
1134 if (len > ETHER_MAX_LEN + 32 || (flags & BFE_RX_FLAG_ERRORS)) {
1136 if (flags & BFE_RX_FLAG_SERR)
1137 ifp->if_collisions++;
1139 bfe_setup_rxdesc(sc, cons);
1140 BFE_INC(cons, BFE_RX_LIST_CNT);
1144 /* Go past the rx header */
1145 if (bfe_newbuf(sc, cons, 0) != 0) {
1146 bfe_setup_rxdesc(sc, cons);
1148 BFE_INC(cons, BFE_RX_LIST_CNT);
1152 m_adj(m, BFE_RX_OFFSET);
1153 m->m_len = m->m_pkthdr.len = len;
1156 m->m_pkthdr.rcvif = ifp;
1158 ether_input_chain(ifp, m, chain);
1159 BFE_INC(cons, BFE_RX_LIST_CNT);
1162 ether_input_dispatch(chain);
1164 sc->bfe_rx_cons = cons;
1170 struct bfe_softc *sc = xsc;
1171 struct ifnet *ifp = &sc->arpcom.ac_if;
1172 uint32_t istat, imask, flag;
1174 istat = CSR_READ_4(sc, BFE_ISTAT);
1175 imask = CSR_READ_4(sc, BFE_IMASK);
1178 * Defer unsolicited interrupts - This is necessary because setting the
1179 * chips interrupt mask register to 0 doesn't actually stop the
1183 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1184 CSR_READ_4(sc, BFE_ISTAT);
1186 /* not expecting this interrupt, disregard it */
1191 if (istat & BFE_ISTAT_ERRORS) {
1192 flag = CSR_READ_4(sc, BFE_DMATX_STAT);
1193 if (flag & BFE_STAT_EMASK)
1196 flag = CSR_READ_4(sc, BFE_DMARX_STAT);
1197 if (flag & BFE_RX_FLAG_ERRORS)
1200 ifp->if_flags &= ~IFF_RUNNING;
1204 /* A packet was received */
1205 if (istat & BFE_ISTAT_RX)
1208 /* A packet was sent */
1209 if (istat & BFE_ISTAT_TX)
1212 /* We have packets pending, fire them out */
1213 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
1218 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, uint32_t *txidx)
1220 struct mbuf *m = *m_head;
1221 bus_dma_segment_t segs[BFE_MAXSEGS];
1223 int i, first_idx, last_idx, cur, error, maxsegs, nsegs;
1225 KKASSERT(sc->bfe_tx_cnt + BFE_SPARE_TXDESC < BFE_TX_LIST_CNT);
1226 maxsegs = BFE_TX_LIST_CNT - sc->bfe_tx_cnt - BFE_SPARE_TXDESC;
1227 if (maxsegs > BFE_MAXSEGS)
1228 maxsegs = BFE_MAXSEGS;
1231 map = sc->bfe_tx_ring[first_idx].bfe_map;
1233 error = bus_dmamap_load_mbuf_segment(sc->bfe_txbuf_tag, map, m,
1234 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1235 if (error && error != EFBIG)
1237 if (error) { /* error == EFBIG */
1240 m_new = m_defrag(m, MB_DONTWAIT);
1241 if (m_new == NULL) {
1245 *m_head = m = m_new;
1248 error = bus_dmamap_load_mbuf_segment(sc->bfe_txbuf_tag, map, m,
1249 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1253 bus_dmamap_sync(sc->bfe_txbuf_tag, map, BUS_DMASYNC_PREWRITE);
1257 for (i = 0; i < nsegs; ++i) {
1261 ctrl = BFE_DESC_LEN & segs[i].ds_len;
1262 ctrl |= BFE_DESC_IOC; /* always interrupt */
1263 if (cur == BFE_TX_LIST_CNT - 1) {
1265 * Tell the chip to wrap to the
1266 * start of the descriptor list.
1268 ctrl |= BFE_DESC_EOT;
1271 d = &sc->bfe_tx_list[cur];
1272 d->bfe_addr = segs[i].ds_addr + BFE_PCI_DMA;
1276 BFE_INC(cur, BFE_TX_LIST_CNT);
1278 KKASSERT(last_idx >= 0);
1280 /* End of the frame */
1281 sc->bfe_tx_list[last_idx].bfe_ctrl |= BFE_DESC_EOF;
1284 * Set start of the frame on the first fragment,
1285 * _after_ all of the fragments are setup.
1287 sc->bfe_tx_list[first_idx].bfe_ctrl |= BFE_DESC_SOF;
1289 sc->bfe_tx_ring[first_idx].bfe_map = sc->bfe_tx_ring[last_idx].bfe_map;
1290 sc->bfe_tx_ring[last_idx].bfe_map = map;
1291 sc->bfe_tx_ring[last_idx].bfe_mbuf = m;
1293 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE);
1296 sc->bfe_tx_cnt += nsegs;
1305 * Set up to transmit a packet
1308 bfe_start(struct ifnet *ifp)
1310 struct bfe_softc *sc = ifp->if_softc;
1311 struct mbuf *m_head = NULL;
1312 int idx, need_trans;
1314 ASSERT_SERIALIZED(ifp->if_serializer);
1317 * Not much point trying to send if the link is down
1318 * or we have nothing to send.
1320 if (!sc->bfe_link) {
1321 ifq_purge(&ifp->if_snd);
1325 if (ifp->if_flags & IFF_OACTIVE)
1328 idx = sc->bfe_tx_prod;
1331 while (!ifq_is_empty(&ifp->if_snd)) {
1332 if (sc->bfe_tx_cnt + BFE_SPARE_TXDESC >= BFE_TX_LIST_CNT) {
1333 ifp->if_flags |= IFF_OACTIVE;
1337 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1342 * Pack the data into the tx ring. If we don't have
1343 * enough room, let the chip drain the ring.
1345 if (bfe_encap(sc, &m_head, &idx)) {
1346 /* m_head is freed by re_encap(), if we reach here */
1349 if (sc->bfe_tx_cnt > 0) {
1350 ifp->if_flags |= IFF_OACTIVE;
1354 * IFF_OACTIVE could not be set under
1355 * this situation, since except up/down,
1356 * nothing will clear IFF_OACTIVE.
1358 * Let's just keep draining the ifq ...
1366 * If there's a BPF listener, bounce a copy of this frame
1369 BPF_MTAP(ifp, m_head);
1375 sc->bfe_tx_prod = idx;
1377 /* Transmit - twice due to apparent hardware bug */
1378 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1379 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1382 * Set a timeout in case the chip goes out to lunch.
1390 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1391 struct ifnet *ifp = &sc->arpcom.ac_if;
1393 ASSERT_SERIALIZED(ifp->if_serializer);
1395 if (ifp->if_flags & IFF_RUNNING)
1401 if (bfe_list_rx_init(sc) == ENOBUFS) {
1402 if_printf(ifp, "bfe_init failed. "
1403 " Not enough memory for list buffers\n");
1408 bfe_set_rx_mode(sc);
1410 /* Enable the chip and core */
1411 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1412 /* Enable interrupts */
1413 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1415 bfe_ifmedia_upd(ifp);
1416 ifp->if_flags |= IFF_RUNNING;
1417 ifp->if_flags &= ~IFF_OACTIVE;
1419 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1423 * Set media options.
1426 bfe_ifmedia_upd(struct ifnet *ifp)
1428 struct bfe_softc *sc = ifp->if_softc;
1429 struct mii_data *mii;
1431 ASSERT_SERIALIZED(ifp->if_serializer);
1433 mii = device_get_softc(sc->bfe_miibus);
1435 if (mii->mii_instance) {
1436 struct mii_softc *miisc;
1437 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1438 miisc = LIST_NEXT(miisc, mii_list))
1439 mii_phy_reset(miisc);
1449 * Report current media status.
1452 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1454 struct bfe_softc *sc = ifp->if_softc;
1455 struct mii_data *mii;
1457 ASSERT_SERIALIZED(ifp->if_serializer);
1459 mii = device_get_softc(sc->bfe_miibus);
1461 ifmr->ifm_active = mii->mii_media_active;
1462 ifmr->ifm_status = mii->mii_media_status;
1466 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1468 struct bfe_softc *sc = ifp->if_softc;
1469 struct ifreq *ifr = (struct ifreq *) data;
1470 struct mii_data *mii;
1473 ASSERT_SERIALIZED(ifp->if_serializer);
1477 if (ifp->if_flags & IFF_UP)
1478 if (ifp->if_flags & IFF_RUNNING)
1479 bfe_set_rx_mode(sc);
1482 else if (ifp->if_flags & IFF_RUNNING)
1487 if (ifp->if_flags & IFF_RUNNING)
1488 bfe_set_rx_mode(sc);
1492 mii = device_get_softc(sc->bfe_miibus);
1493 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1497 error = ether_ioctl(ifp, command, data);
1504 bfe_watchdog(struct ifnet *ifp)
1506 struct bfe_softc *sc = ifp->if_softc;
1508 ASSERT_SERIALIZED(ifp->if_serializer);
1510 if_printf(ifp, "watchdog timeout -- resetting\n");
1512 ifp->if_flags &= ~IFF_RUNNING;
1521 struct bfe_softc *sc = xsc;
1522 struct mii_data *mii;
1523 struct ifnet *ifp = &sc->arpcom.ac_if;
1525 mii = device_get_softc(sc->bfe_miibus);
1527 lwkt_serialize_enter(ifp->if_serializer);
1529 bfe_stats_update(sc);
1530 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1532 if (sc->bfe_link == 0) {
1534 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE &&
1535 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1541 lwkt_serialize_exit(ifp->if_serializer);
1545 * Stop the adapter and free any mbufs allocated to the
1549 bfe_stop(struct bfe_softc *sc)
1551 struct ifnet *ifp = &sc->arpcom.ac_if;
1553 ASSERT_SERIALIZED(ifp->if_serializer);
1555 callout_stop(&sc->bfe_stat_timer);
1558 bfe_tx_ring_free(sc);
1559 bfe_rx_ring_free(sc);
1561 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);