2 * Copyright (c) 1995 - 2001 John Hay. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. Neither the name of the author nor the names of any co-contributors
13 * may be used to endorse or promote products derived from this software
14 * without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY John Hay ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL John Hay BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * $FreeBSD: src/sys/dev/ar/if_ar.c,v 1.66 2005/01/06 01:42:28 imp Exp $
29 * $DragonFly: src/sys/dev/netif/ar/if_ar.c,v 1.18 2005/11/28 17:13:39 dillon Exp $
33 * Programming assumptions and other issues.
35 * The descriptors of a DMA channel will fit in a 16K memory window.
37 * The buffers of a transmit DMA channel will fit in a 16K memory window.
39 * Only the ISA bus cards with X.21 and V.35 is tested.
41 * When interface is going up, handshaking is set and it is only cleared
42 * when the interface is down'ed.
44 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE,
45 * internal/external clock, etc.....
48 #include "opt_netgraph.h"
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
53 #include <sys/malloc.h>
55 #include <sys/socket.h>
56 #include <sys/sockio.h>
57 #include <sys/module.h>
59 #include <sys/serialize.h>
60 #include <machine/bus.h>
61 #include <machine/resource.h>
62 #include <machine/bus_pio.h>
63 #include <machine/bus_memio.h>
66 #include <sys/thread2.h>
70 #include <netgraph/ng_message.h>
71 #include <netgraph/netgraph.h>
72 #include <sys/syslog.h>
73 #include <dev/netif/ar/if_ar.h>
75 #include <net/sppp/if_sppp.h>
79 #include <machine/md_var.h>
81 #include <dev/netif/ic_layer/hd64570.h>
82 #include <dev/netif/ar/if_arregs.h>
92 #define PPP_HEADER_LEN 4
94 devclass_t ar_devclass;
100 int unit; /* With regards to all ar devices */
101 int subunit; /* With regards to this card */
105 u_int txdesc; /* On card address */
106 u_int txstart; /* On card address */
107 u_int txend; /* On card address */
108 u_int txtail; /* Index of first unused buffer */
109 u_int txmax; /* number of usable buffers/descriptors */
110 u_int txeda; /* Error descriptor addresses */
111 }block[AR_TX_BLOCKS];
113 char xmit_busy; /* Transmitter is busy */
114 char txb_inuse; /* Number of tx blocks currently in use */
115 u_char txb_new; /* Index to where new buffer will be added */
116 u_char txb_next_tx; /* Index to next block ready to tx */
118 u_int rxdesc; /* On card address */
119 u_int rxstart; /* On card address */
120 u_int rxend; /* On card address */
121 u_int rxhind; /* Index to the head of the rx buffers. */
122 u_int rxmax; /* number of usable buffers/descriptors */
128 int running; /* something is attached so we are running */
129 int dcd; /* do we have dcd? */
130 /* ---netgraph bits --- */
131 char nodename[NG_NODELEN + 1]; /* store our node name */
132 int datahooks; /* number of data hooks attached */
133 node_p node; /* netgraph node */
134 hook_p hook; /* data hook */
136 struct ifqueue xmitq_hipri; /* hi-priority transmit queue */
137 struct ifqueue xmitq; /* transmit queue */
138 int flags; /* state */
139 #define SCF_RUNNING 0x01 /* board is active */
140 #define SCF_OACTIVE 0x02 /* output is active */
141 int out_dog; /* watchdog cycles output count-down */
142 struct callout timer; /* watchdog timer */
143 u_long inbytes, outbytes; /* stats */
144 u_long lastinbytes, lastoutbytes; /* a second ago */
145 u_long inrate, outrate; /* highest rate seen */
146 u_long inlast; /* last input N secs ago */
147 u_long out_deficit; /* output since last input */
148 u_long oerrors, ierrors[6];
149 u_long opackets, ipackets;
150 #endif /* NETGRAPH */
153 static int next_ar_unit = 0;
154 static struct lwkt_serialize ar_serializer;
157 #define DOG_HOLDOFF 6 /* dog holds off for 6 secs */
158 #define QUITE_A_WHILE 300 /* 5 MINUTES */
159 #define LOTS_OF_PACKETS 100
160 #endif /* NETGRAPH */
163 * This translate from irq numbers to
164 * the value that the arnet card needs
165 * in the lower part of the AR_INT_SEL
168 static int irqtable[16] = {
188 DECLARE_DUMMY_MODULE(if_ar);
189 MODULE_DEPEND(if_ar, sppp, 1, 1, 1);
191 MODULE_DEPEND(ng_sync_ar, netgraph, 1, 1, 1);
194 static void arintr(void *arg);
195 static void ar_xmit(struct ar_softc *sc);
197 static void arstart(struct ifnet *ifp);
198 static int arioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *);
199 static void arwatchdog(struct ifnet *ifp);
201 static void arstart(struct ar_softc *sc);
202 static void arwatchdog(struct ar_softc *sc);
203 #endif /* NETGRAPH */
204 static int ar_packet_avail(struct ar_softc *sc, int *len, u_char *rxstat);
205 static void ar_copy_rxbuf(struct mbuf *m, struct ar_softc *sc, int len);
206 static void ar_eat_packet(struct ar_softc *sc, int single);
207 static void ar_get_packets(struct ar_softc *sc);
209 static int ar_read_pim_iface(volatile struct ar_hardc *hc, int channel);
210 static void ar_up(struct ar_softc *sc);
211 static void ar_down(struct ar_softc *sc);
212 static void arc_init(struct ar_hardc *hc);
213 static void ar_init_sca(struct ar_hardc *hc, int scano);
214 static void ar_init_msci(struct ar_softc *sc);
215 static void ar_init_rx_dmac(struct ar_softc *sc);
216 static void ar_init_tx_dmac(struct ar_softc *sc);
217 static void ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr);
218 static void ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr);
219 static void ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr);
222 static void ngar_watchdog_frame(void * arg);
223 static void ngar_init(void* ignored);
225 static ng_constructor_t ngar_constructor;
226 static ng_rcvmsg_t ngar_rcvmsg;
227 static ng_shutdown_t ngar_shutdown;
228 static ng_newhook_t ngar_newhook;
229 /*static ng_findhook_t ngar_findhook; */
230 static ng_connect_t ngar_connect;
231 static ng_rcvdata_t ngar_rcvdata;
232 static ng_disconnect_t ngar_disconnect;
234 static struct ng_type typestruct = {
250 static int ngar_done_init = 0;
251 #endif /* NETGRAPH */
254 ar_attach(device_t device)
261 #endif /* NETGRAPH */
265 hc = (struct ar_hardc *)device_get_softc(device);
266 lwkt_serialize_init(&ar_serializer);
268 printf("arc%d: %uK RAM, %u ports, rev %u.\n",
276 error = BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq,
278 &hc->intr_cookie, &ar_serializer);
284 for(unit=0;unit<hc->numports;unit+=NCHAN)
285 ar_init_sca(hc, unit / NCHAN);
288 * Now configure each port on the card.
290 for(unit=0;unit<hc->numports;sc++,unit++) {
293 sc->unit = next_ar_unit;
295 sc->scano = unit / NCHAN;
296 sc->scachan = unit%NCHAN;
303 ifp = &sc->ifsppp.pp_if;
306 if_initname(ifp, device_get_name(device), sc->unit);
307 ifp->if_mtu = PP_MTU;
308 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST;
309 ifp->if_ioctl = arioctl;
310 ifp->if_start = arstart;
311 ifp->if_watchdog = arwatchdog;
313 sc->ifsppp.pp_flags = PP_KEEPALIVE;
315 switch(hc->interface[unit]) {
316 default: iface = "UNKNOWN"; break;
317 case AR_IFACE_EIA_232: iface = "EIA-232"; break;
318 case AR_IFACE_V_35: iface = "EIA-232 or V.35"; break;
319 case AR_IFACE_EIA_530: iface = "EIA-530"; break;
320 case AR_IFACE_X_21: iface = "X.21"; break;
321 case AR_IFACE_COMBO: iface = "COMBO X.21 / EIA-530"; break;
324 printf("ar%d: Adapter %d, port %d, interface %s.\n",
330 sppp_attach((struct ifnet *)&sc->ifsppp);
331 if_attach(ifp, &ar_serializer);
333 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN);
336 * we have found a node, make sure our 'type' is availabe.
338 if (ngar_done_init == 0) ngar_init(NULL);
339 if (ng_make_node_common(&typestruct, &sc->node) != 0)
341 sprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit);
342 if (ng_name_node(sc->node, sc->nodename)) {
343 NG_NODE_UNREF(sc->node); /* drop it again */
346 NG_NODE_SET_PRIVATE(sc->node, sc);
347 callout_init(&sc->timer);
348 sc->xmitq.ifq_maxlen = IFQ_MAXLEN;
349 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN;
351 #endif /* NETGRAPH */
354 if(hc->bustype == AR_BUS_ISA)
361 ar_detach(device_t device)
363 device_t parent = device_get_parent(device);
364 struct ar_hardc *hc = device_get_softc(device);
367 lwkt_serialize_enter(&ar_serializer);
369 if (hc->intr_cookie != NULL) {
370 if (BUS_TEARDOWN_INTR(parent, device,
371 hc->res_irq, hc->intr_cookie) != 0) {
372 printf("intr teardown failed.. continuing\n");
374 hc->intr_cookie = NULL;
378 * deallocate any system resources we may have
379 * allocated on behalf of this driver.
381 FREE(hc->sc, M_DEVBUF);
383 hc->mem_start = NULL;
384 error = ar_deallocate_resources(device);
385 lwkt_serialize_exit(&ar_serializer);
391 ar_allocate_ioport(device_t device, int rid, u_long size)
393 struct ar_hardc *hc = device_get_softc(device);
395 hc->rid_ioport = rid;
396 hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT,
397 &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE);
398 if (hc->res_ioport == NULL) {
401 hc->bt = rman_get_bustag(hc->res_ioport);
402 hc->bh = rman_get_bushandle(hc->res_ioport);
407 ar_deallocate_resources(device);
412 ar_allocate_irq(device_t device, int rid, u_long size)
414 struct ar_hardc *hc = device_get_softc(device);
417 hc->res_irq = bus_alloc_resource_any(device, SYS_RES_IRQ,
418 &hc->rid_irq, RF_SHAREABLE|RF_ACTIVE);
419 if (hc->res_irq == NULL) {
425 ar_deallocate_resources(device);
430 ar_allocate_memory(device_t device, int rid, u_long size)
432 struct ar_hardc *hc = device_get_softc(device);
434 hc->rid_memory = rid;
435 hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
436 &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE);
437 if (hc->res_memory == NULL) {
443 ar_deallocate_resources(device);
448 ar_allocate_plx_memory(device_t device, int rid, u_long size)
450 struct ar_hardc *hc = device_get_softc(device);
452 hc->rid_plx_memory = rid;
453 hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
454 &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE);
455 if (hc->res_plx_memory == NULL) {
461 ar_deallocate_resources(device);
466 ar_deallocate_resources(device_t device)
468 struct ar_hardc *hc = device_get_softc(device);
470 if (hc->res_irq != 0) {
471 bus_deactivate_resource(device, SYS_RES_IRQ,
472 hc->rid_irq, hc->res_irq);
473 bus_release_resource(device, SYS_RES_IRQ,
474 hc->rid_irq, hc->res_irq);
477 if (hc->res_ioport != 0) {
478 bus_deactivate_resource(device, SYS_RES_IOPORT,
479 hc->rid_ioport, hc->res_ioport);
480 bus_release_resource(device, SYS_RES_IOPORT,
481 hc->rid_ioport, hc->res_ioport);
484 if (hc->res_memory != 0) {
485 bus_deactivate_resource(device, SYS_RES_MEMORY,
486 hc->rid_memory, hc->res_memory);
487 bus_release_resource(device, SYS_RES_MEMORY,
488 hc->rid_memory, hc->res_memory);
491 if (hc->res_plx_memory != 0) {
492 bus_deactivate_resource(device, SYS_RES_MEMORY,
493 hc->rid_plx_memory, hc->res_plx_memory);
494 bus_release_resource(device, SYS_RES_MEMORY,
495 hc->rid_plx_memory, hc->res_plx_memory);
496 hc->res_plx_memory = 0;
502 * First figure out which SCA gave the interrupt.
504 * See if there is other interrupts pending.
505 * Repeat until there is no more interrupts.
510 struct ar_hardc *hc = (struct ar_hardc *)arg;
512 u_char isr0, isr1, isr2, arisr;
515 /* XXX Use the PCI interrupt score board register later */
516 if(hc->bustype == AR_BUS_PCI)
517 arisr = hc->orbase[AR_ISTAT * 4];
519 arisr = ar_inb(hc, AR_ISTAT);
521 while(arisr & AR_BD_INT) {
522 TRC(printf("arisr = %x\n", arisr));
525 else if(arisr & AR_INT_1)
528 /* XXX Oops this shouldn't happen. */
529 printf("arc%d: Interrupted with no interrupt.\n",
533 sca = hc->sca[scano];
535 if(hc->bustype == AR_BUS_ISA)
536 ARC_SET_SCA(hc, scano);
542 TRC(printf("arc%d: ARINTR isr0 %x, isr1 %x, isr2 %x\n",
548 ar_msci_intr(hc, scano, isr0);
551 ar_dmac_intr(hc, scano, isr1);
554 ar_timer_intr(hc, scano, isr2);
557 * Proccess the second sca's interrupt if available.
558 * Else see if there are any new interrupts.
560 if((arisr & AR_INT_0) && (arisr & AR_INT_1))
563 if(hc->bustype == AR_BUS_PCI)
564 arisr = hc->orbase[AR_ISTAT * 4];
566 arisr = ar_inb(hc, AR_ISTAT);
570 if(hc->bustype == AR_BUS_ISA)
576 * This will only start the transmitter. It is assumed that the data
577 * is already there. It is normally called from arstart() or ar_dmac_intr().
581 ar_xmit(struct ar_softc *sc)
585 #endif /* NETGRAPH */
589 ifp = &sc->ifsppp.pp_if;
590 #endif /* NETGRAPH */
591 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)];
593 if(sc->hc->bustype == AR_BUS_ISA)
594 ARC_SET_SCA(sc->hc, sc->scano);
595 dmac->cda = (u_short)(sc->block[sc->txb_next_tx].txdesc & 0xffff);
597 dmac->eda = (u_short)(sc->block[sc->txb_next_tx].txeda & 0xffff);
598 dmac->dsr = SCA_DSR_DE;
603 if(sc->txb_next_tx == AR_TX_BLOCKS)
607 ifp->if_timer = 2; /* Value in seconds. */
609 sc->out_dog = DOG_HOLDOFF; /* give ourself some breathing space*/
610 #endif /* NETGRAPH */
611 if(sc->hc->bustype == AR_BUS_ISA)
616 * This function will be called from the upper level when a user add a
617 * packet to be send, and from the interrupt handler after a finished
620 * This function only place the data in the oncard buffers. It does not
621 * start the transmition. ar_xmit() does that.
623 * Transmitter idle state is indicated by the IFF_OACTIVE flag. The function
624 * that clears that should ensure that the transmitter and its DMA is
625 * in a "good" idle state.
629 arstart(struct ifnet *ifp)
631 struct ar_softc *sc = ifp->if_softc;
634 arstart(struct ar_softc *sc)
636 #endif /* NETGRAPH */
640 sca_descriptor *txdesc;
641 struct buf_block *blkp;
644 if(!(ifp->if_flags & IFF_RUNNING))
648 #endif /* NETGRAPH */
653 * See if we have space for more packets.
655 if(sc->txb_inuse == AR_TX_BLOCKS) {
657 ifp->if_flags |= IFF_OACTIVE; /* yes, mark active */
659 /*XXX*/ /*ifp->if_flags |= IFF_OACTIVE;*/ /* yes, mark active */
660 #endif /* NETGRAPH */
665 mtx = sppp_dequeue(ifp);
667 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
669 IF_DEQUEUE(&sc->xmitq, mtx);
671 #endif /* NETGRAPH */
676 * It is OK to set the memory window outside the loop because
677 * all tx buffers and descriptors are assumed to be in the same
680 if(sc->hc->bustype == AR_BUS_ISA)
681 ARC_SET_MEM(sc->hc, sc->block[0].txdesc);
684 * We stay in this loop until there is nothing in the
685 * TX queue left or the tx buffer is full.
688 blkp = &sc->block[sc->txb_new];
689 txdesc = (sca_descriptor *)
690 (sc->hc->mem_start + (blkp->txdesc & sc->hc->winmsk));
691 txdata = (u_char *)(sc->hc->mem_start + (blkp->txstart & sc->hc->winmsk));
693 len = mtx->m_pkthdr.len;
695 TRC(printf("ar%d: ARstart len %u\n", sc->unit, len));
698 * We can do this because the tx buffers don't wrap.
700 m_copydata(mtx, 0, len, txdata);
702 while(tlen > AR_BUF_SIZ) {
704 txdesc->len = AR_BUF_SIZ;
707 txdata += AR_BUF_SIZ;
710 /* XXX Move into the loop? */
711 txdesc->stat = SCA_DESC_EOM;
714 txdata += AR_BUF_SIZ;
720 ++sc->ifsppp.pp_if.if_opackets;
725 #endif /* NETGRAPH */
728 * Check if we have space for another mbuf.
729 * XXX This is hardcoded. A packet won't be larger
730 * than 3 buffers (3 x 512).
732 if((i + 3) >= blkp->txmax)
736 mtx = sppp_dequeue(ifp);
738 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
740 IF_DEQUEUE(&sc->xmitq, mtx);
742 #endif /* NETGRAPH */
750 * Mark the last descriptor, so that the SCA know where
754 txdesc->stat |= SCA_DESC_EOT;
756 txdesc = (sca_descriptor *)blkp->txdesc;
757 blkp->txeda = (u_short)((u_int)&txdesc[i]);
760 printf("ARstart: %p desc->cp %x\n", &txdesc->cp, txdesc->cp);
761 printf("ARstart: %p desc->bp %x\n", &txdesc->bp, txdesc->bp);
762 printf("ARstart: %p desc->bpb %x\n", &txdesc->bpb, txdesc->bpb);
763 printf("ARstart: %p desc->len %x\n", &txdesc->len, txdesc->len);
764 printf("ARstart: %p desc->stat %x\n", &txdesc->stat, txdesc->stat);
769 if(sc->txb_new == AR_TX_BLOCKS)
772 if(sc->xmit_busy == 0)
775 if(sc->hc->bustype == AR_BUS_ISA)
783 arioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
786 int was_up, should_be_up;
787 struct ar_softc *sc = ifp->if_softc;
789 TRC(if_printf(ifp, "arioctl.\n");)
791 was_up = ifp->if_flags & IFF_RUNNING;
793 error = sppp_ioctl(ifp, cmd, data);
794 TRC(if_printf(ifp, "ioctl: ifsppp.pp_flags = %x, if_flags %x.\n",
795 ((struct sppp *)ifp)->pp_flags, ifp->if_flags);)
799 if((cmd != SIOCSIFFLAGS) && cmd != (SIOCSIFADDR))
802 TRC(if_printf(ifp, "arioctl %s.\n",
803 (cmd == SIOCSIFFLAGS) ? "SIOCSIFFLAGS" : "SIOCSIFADDR");)
805 should_be_up = ifp->if_flags & IFF_RUNNING;
807 if(!was_up && should_be_up) {
808 /* Interface should be up -- start it. */
811 /* XXX Maybe clear the IFF_UP flag so that the link
812 * will only go up after sppp lcp and ipcp negotiation.
814 } else if(was_up && !should_be_up) {
815 /* Interface should be down -- stop it. */
821 #endif /* NETGRAPH */
824 * This is to catch lost tx interrupts.
828 arwatchdog(struct ifnet *ifp)
830 struct ar_softc *sc = ifp->if_softc;
832 arwatchdog(struct ar_softc *sc)
834 #endif /* NETGRAPH */
835 msci_channel *msci = &sc->sca->msci[sc->scachan];
838 if(!(ifp->if_flags & IFF_RUNNING))
840 #endif /* NETGRAPH */
842 if(sc->hc->bustype == AR_BUS_ISA)
843 ARC_SET_SCA(sc->hc, sc->scano);
845 /* XXX if(sc->ifsppp.pp_if.if_flags & IFF_DEBUG) */
846 printf("ar%d: transmit failed, "
847 "ST0 %x, ST1 %x, ST3 %x, DSR %x.\n",
852 sc->sca->dmac[DMAC_TXCH(sc->scachan)].dsr);
854 if(msci->st1 & SCA_ST1_UDRN) {
855 msci->cmd = SCA_CMD_TXABORT;
856 msci->cmd = SCA_CMD_TXENABLE;
857 msci->st1 = SCA_ST1_UDRN;
862 ifp->if_flags &= ~IFF_OACTIVE;
864 /* XXX ifp->if_flags &= ~IFF_OACTIVE; */
865 #endif /* NETGRAPH */
867 if(sc->txb_inuse && --sc->txb_inuse)
874 #endif /* NETGRAPH */
878 ar_up(struct ar_softc *sc)
884 msci = &sca->msci[sc->scachan];
886 TRC(printf("ar%d: sca %p, msci %p, ch %d\n",
887 sc->unit, sca, msci, sc->scachan));
890 * Enable transmitter and receiver.
894 if(sc->hc->bustype == AR_BUS_ISA)
895 ARC_SET_SCA(sc->hc, sc->scano);
898 * What about using AUTO mode in msci->md0 ???
899 * And what about CTS/DCD etc... ?
901 if(sc->hc->handshake & AR_SHSK_RTS)
902 msci->ctl &= ~SCA_CTL_RTS;
903 if(sc->hc->handshake & AR_SHSK_DTR) {
904 sc->hc->txc_dtr[sc->scano] &= sc->scachan ?
905 ~AR_TXC_DTR_DTR1 : ~AR_TXC_DTR_DTR0;
906 if(sc->hc->bustype == AR_BUS_PCI)
907 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] =
908 sc->hc->txc_dtr[sc->scano];
910 ar_outb(sc->hc, sc->hc->txc_dtr_off[sc->scano],
911 sc->hc->txc_dtr[sc->scano]);
914 if(sc->scachan == 0) {
922 msci->cmd = SCA_CMD_RXENABLE;
923 if(sc->hc->bustype == AR_BUS_ISA)
924 ar_inb(sc->hc, AR_ID_5); /* XXX slow it down a bit. */
925 msci->cmd = SCA_CMD_TXENABLE;
927 if(sc->hc->bustype == AR_BUS_ISA)
930 callout_reset(&sc->timer, hz, ngar_watchdog_frame, sc);
932 #endif /* NETGRAPH */
936 ar_down(struct ar_softc *sc)
942 msci = &sca->msci[sc->scachan];
945 callout_stop(&sc->timer);
947 #endif /* NETGRAPH */
949 * Disable transmitter and receiver.
951 * Disable interrupts.
953 if(sc->hc->bustype == AR_BUS_ISA)
954 ARC_SET_SCA(sc->hc, sc->scano);
955 msci->cmd = SCA_CMD_RXDISABLE;
956 if(sc->hc->bustype == AR_BUS_ISA)
957 ar_inb(sc->hc, AR_ID_5); /* XXX slow it down a bit. */
958 msci->cmd = SCA_CMD_TXDISABLE;
960 if(sc->hc->handshake & AR_SHSK_RTS)
961 msci->ctl |= SCA_CTL_RTS;
962 if(sc->hc->handshake & AR_SHSK_DTR) {
963 sc->hc->txc_dtr[sc->scano] |= sc->scachan ?
964 AR_TXC_DTR_DTR1 : AR_TXC_DTR_DTR0;
965 if(sc->hc->bustype == AR_BUS_PCI)
966 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] =
967 sc->hc->txc_dtr[sc->scano];
969 ar_outb(sc->hc, sc->hc->txc_dtr_off[sc->scano],
970 sc->hc->txc_dtr[sc->scano]);
973 if(sc->scachan == 0) {
981 if(sc->hc->bustype == AR_BUS_ISA)
986 ar_read_pim_iface(volatile struct ar_hardc *hc, int channel)
988 int ctype, i, val, x;
989 volatile u_char *pimctrl;
994 pimctrl = hc->orbase + AR_PIMCTRL;
998 *pimctrl = AR_PIM_STROBE;
1000 /* Check if there is a PIM */
1002 *pimctrl = AR_PIM_READ;
1004 TRC(printf("x = %x", x));
1005 if(x & AR_PIM_DATA) {
1006 printf("No PIM installed\n");
1007 return (AR_IFACE_UNKNOWN);
1010 x = (x >> 1) & 0x01;
1013 /* Now read the next 15 bits */
1014 for(i = 1; i < 16; i++) {
1015 *pimctrl = AR_PIM_READ;
1016 *pimctrl = AR_PIM_READ | AR_PIM_STROBE;
1018 TRC(printf(" %x ", x));
1019 x = (x >> 1) & 0x01;
1021 if(i == 8 && (val & 0x000f) == 0x0004) {
1025 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1026 *pimctrl = AR_PIM_A2D_DOUT;
1029 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1030 *pimctrl = AR_PIM_A2D_DOUT;
1033 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1034 *pimctrl = AR_PIM_A2D_DOUT;
1036 /* Select channel */
1037 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 2) << 2);
1038 *pimctrl = ((channel & 2) << 2);
1039 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 1) << 3);
1040 *pimctrl = ((channel & 1) << 3);
1042 *pimctrl = AR_PIM_A2D_STROBE;
1046 printf("\nOops A2D start bit not zero (%X)\n", x);
1048 for(ii = 7; ii >= 0; ii--) {
1050 *pimctrl = AR_PIM_A2D_STROBE;
1057 TRC(printf("\nPIM val %x, ctype %x, %d\n", val, ctype, ctype));
1058 *pimctrl = AR_PIM_MODEG;
1059 *pimctrl = AR_PIM_MODEG | AR_PIM_AUTO_LED;
1061 return (AR_IFACE_UNKNOWN);
1063 return (AR_IFACE_V_35);
1065 return (AR_IFACE_EIA_232);
1067 return (AR_IFACE_X_21);
1069 return (AR_IFACE_EIA_530);
1071 return (AR_IFACE_UNKNOWN);
1073 return (AR_IFACE_LOOPBACK);
1074 return (AR_IFACE_UNKNOWN);
1078 * Initialize the card, allocate memory for the ar_softc structures
1079 * and fill in the pointers.
1082 arc_init(struct ar_hardc *hc)
1084 struct ar_softc *sc;
1093 MALLOC(sc, struct ar_softc *, hc->numports * sizeof(struct ar_softc),
1094 M_DEVBUF, M_WAITOK | M_ZERO);
1099 hc->txc_dtr[0] = AR_TXC_DTR_NOTRESET |
1100 AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1;
1101 hc->txc_dtr[1] = AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1;
1102 hc->txc_dtr_off[0] = AR_TXC_DTR0;
1103 hc->txc_dtr_off[1] = AR_TXC_DTR2;
1104 if(hc->bustype == AR_BUS_PCI) {
1105 hc->txc_dtr_off[0] *= 4;
1106 hc->txc_dtr_off[1] *= 4;
1110 * reset the card and wait at least 1uS.
1112 if(hc->bustype == AR_BUS_PCI)
1113 hc->orbase[AR_TXC_DTR0 * 4] = ~AR_TXC_DTR_NOTRESET &
1116 ar_outb(hc, AR_TXC_DTR0, ~AR_TXC_DTR_NOTRESET &
1119 if(hc->bustype == AR_BUS_PCI)
1120 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0];
1122 ar_outb(hc, AR_TXC_DTR0, hc->txc_dtr[0]);
1124 if(hc->bustype == AR_BUS_ISA) {
1126 * Configure the card.
1129 memst = rman_get_start(hc->res_memory);
1131 isr = irqtable[hc->isa_irq] << 1;
1133 printf("ar%d: Warning illegal interrupt %d\n",
1134 hc->cunit, hc->isa_irq);
1135 isr = isr | ((memst & 0xc000) >> 10);
1137 hc->sca[0] = (sca_regs *)hc->mem_start;
1138 hc->sca[1] = (sca_regs *)hc->mem_start;
1140 ar_outb(hc, AR_MEM_SEL, mar);
1141 ar_outb(hc, AR_INT_SEL, isr | AR_INTS_CEN);
1144 if(hc->bustype == AR_BUS_PCI && hc->interface[0] == AR_IFACE_PIM)
1145 for(x = 0; x < hc->numports; x++)
1146 hc->interface[x] = ar_read_pim_iface(hc, x);
1149 * Set the TX clock direction and enable TX.
1151 for(x=0;x<hc->numports;x++) {
1152 switch(hc->interface[x]) {
1154 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1155 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1;
1156 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1157 AR_TXC_DTR_TXCS0 : AR_TXC_DTR_TXCS1;
1159 case AR_IFACE_EIA_530:
1160 case AR_IFACE_COMBO:
1162 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1163 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1;
1168 if(hc->bustype == AR_BUS_PCI)
1169 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0];
1171 ar_outb(hc, AR_TXC_DTR0, hc->txc_dtr[0]);
1172 if(hc->numports > NCHAN) {
1173 if(hc->bustype == AR_BUS_PCI)
1174 hc->orbase[AR_TXC_DTR2 * 4] = hc->txc_dtr[1];
1176 ar_outb(hc, AR_TXC_DTR2, hc->txc_dtr[1]);
1179 chanmem = hc->memsize / hc->numports;
1182 for(x=0;x<hc->numports;x++, sc++) {
1185 sc->sca = hc->sca[x / NCHAN];
1187 for(blk = 0; blk < AR_TX_BLOCKS; blk++) {
1188 sc->block[blk].txdesc = next;
1189 bufmem = (16 * 1024) / AR_TX_BLOCKS;
1190 descneeded = bufmem / AR_BUF_SIZ;
1191 sc->block[blk].txstart = sc->block[blk].txdesc +
1192 ((((descneeded * sizeof(sca_descriptor)) /
1193 AR_BUF_SIZ) + 1) * AR_BUF_SIZ);
1194 sc->block[blk].txend = next + bufmem;
1195 sc->block[blk].txmax =
1196 (sc->block[blk].txend - sc->block[blk].txstart)
1200 TRC(printf("ar%d: blk %d: txdesc %x, txstart %x, "
1201 "txend %x, txmax %d\n",
1204 sc->block[blk].txdesc,
1205 sc->block[blk].txstart,
1206 sc->block[blk].txend,
1207 sc->block[blk].txmax));
1211 bufmem = chanmem - (bufmem * AR_TX_BLOCKS);
1212 descneeded = bufmem / AR_BUF_SIZ;
1213 sc->rxstart = sc->rxdesc +
1214 ((((descneeded * sizeof(sca_descriptor)) /
1215 AR_BUF_SIZ) + 1) * AR_BUF_SIZ);
1216 sc->rxend = next + bufmem;
1217 sc->rxmax = (sc->rxend - sc->rxstart) / AR_BUF_SIZ;
1219 TRC(printf("ar%d: rxdesc %x, rxstart %x, "
1220 "rxend %x, rxmax %d\n",
1221 x, sc->rxdesc, sc->rxstart, sc->rxend, sc->rxmax));
1224 if(hc->bustype == AR_BUS_PCI)
1225 hc->orbase[AR_PIMCTRL] = AR_PIM_MODEG | AR_PIM_AUTO_LED;
1230 * The things done here are channel independent.
1232 * Configure the sca waitstates.
1233 * Configure the global interrupt registers.
1234 * Enable master dma enable.
1237 ar_init_sca(struct ar_hardc *hc, int scano)
1241 sca = hc->sca[scano];
1242 if(hc->bustype == AR_BUS_ISA)
1243 ARC_SET_SCA(hc, scano);
1246 * Do the wait registers.
1247 * Set everything to 0 wait states.
1256 * Configure the interrupt registers.
1257 * Most are cleared until the interface is configured.
1259 sca->ier0 = 0x00; /* MSCI interrupts... Not used with dma. */
1260 sca->ier1 = 0x00; /* DMAC interrupts */
1261 sca->ier2 = 0x00; /* TIMER interrupts... Not used yet. */
1262 sca->itcr = 0x00; /* Use ivr and no intr ack */
1263 sca->ivr = 0x40; /* Fill in the interrupt vector. */
1267 * Configure the timers.
1273 * Set the DMA channel priority to rotate between
1274 * all four channels.
1276 * Enable all dma channels.
1278 if(hc->bustype == AR_BUS_PCI) {
1282 * Stupid problem with the PCI interface chip that break
1287 t[AR_PCI_SCA_PCR] = SCA_PCR_PR2;
1288 t[AR_PCI_SCA_DMER] = SCA_DMER_EN;
1290 sca->pcr = SCA_PCR_PR2;
1291 sca->dmer = SCA_DMER_EN;
1297 * Configure the msci
1299 * NOTE: The serial port configuration is hardcoded at the moment.
1302 ar_init_msci(struct ar_softc *sc)
1306 msci = &sc->sca->msci[sc->scachan];
1308 if(sc->hc->bustype == AR_BUS_ISA)
1309 ARC_SET_SCA(sc->hc, sc->scano);
1311 msci->cmd = SCA_CMD_RESET;
1313 msci->md0 = SCA_MD0_CRC_1 |
1315 SCA_MD0_CRC_ENABLE |
1317 msci->md1 = SCA_MD1_NOADDRCHK;
1318 msci->md2 = SCA_MD2_DUPLEX | SCA_MD2_NRZ;
1321 * Acording to the manual I should give a reset after changing the
1324 msci->cmd = SCA_CMD_RXRESET;
1325 msci->ctl = SCA_CTL_IDLPAT | SCA_CTL_UDRNC | SCA_CTL_RTS;
1328 * For now all interfaces are programmed to use the RX clock for
1331 switch(sc->hc->interface[sc->subunit]) {
1333 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1;
1334 msci->txs = SCA_TXS_CLK_TXC | SCA_TXS_DIV1;
1337 case AR_IFACE_EIA_530:
1338 case AR_IFACE_COMBO:
1339 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1;
1340 msci->txs = SCA_TXS_CLK_RX | SCA_TXS_DIV1;
1343 msci->tmc = 153; /* This give 64k for loopback */
1346 * Disable all interrupts for now. I think if you are using
1347 * the dmac you don't use these interrupts.
1350 msci->ie1 = 0x0C; /* XXX CTS and DCD (DSR on 570I) level change. */
1357 msci->idl = 0x7E; /* XXX This is what cisco does. */
1360 * This is what the ARNET diags use.
1368 * Configure the rx dma controller.
1371 ar_init_rx_dmac(struct ar_softc *sc)
1374 sca_descriptor *rxd;
1380 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1382 if(sc->hc->bustype == AR_BUS_ISA)
1383 ARC_SET_MEM(sc->hc, sc->rxdesc);
1385 rxd = (sca_descriptor *)(sc->hc->mem_start + (sc->rxdesc&sc->hc->winmsk));
1386 rxda_d = (u_int)sc->hc->mem_start - (sc->rxdesc & ~sc->hc->winmsk);
1388 for(rxbuf=sc->rxstart;rxbuf<sc->rxend;rxbuf += AR_BUF_SIZ, rxd++) {
1389 rxda = (u_int)&rxd[1] - rxda_d;
1390 rxd->cp = (u_short)(rxda & 0xfffful);
1394 TRC(printf("Descrp %p, data pt %x, data %x, ",
1397 rxd->bp = (u_short)(rxbuf & 0xfffful);
1398 rxd->bpb = (u_char)((rxbuf >> 16) & 0xff);
1400 rxd->stat = 0xff; /* The sca write here when it is finished. */
1403 TRC(printf("bpb %x, bp %x.\n", rxd->bpb, rxd->bp));
1406 rxd->cp = (u_short)(sc->rxdesc & 0xfffful);
1410 if(sc->hc->bustype == AR_BUS_ISA)
1411 ARC_SET_SCA(sc->hc, sc->scano);
1413 dmac->dsr = 0; /* Disable DMA transfer */
1414 dmac->dcr = SCA_DCR_ABRT;
1416 /* XXX maybe also SCA_DMR_CNTE */
1417 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF;
1418 dmac->bfl = AR_BUF_SIZ;
1420 dmac->cda = (u_short)(sc->rxdesc & 0xffff);
1421 dmac->sarb = (u_char)((sc->rxdesc >> 16) & 0xff);
1423 rxd = (sca_descriptor *)sc->rxstart;
1424 dmac->eda = (u_short)((u_int)&rxd[sc->rxmax - 1] & 0xffff);
1428 dmac->dsr = SCA_DSR_DE;
1432 * Configure the TX DMA descriptors.
1433 * Initialize the needed values and chain the descriptors.
1436 ar_init_tx_dmac(struct ar_softc *sc)
1439 struct buf_block *blkp;
1441 sca_descriptor *txd;
1446 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)];
1448 if(sc->hc->bustype == AR_BUS_ISA)
1449 ARC_SET_MEM(sc->hc, sc->block[0].txdesc);
1451 for(blk = 0; blk < AR_TX_BLOCKS; blk++) {
1452 blkp = &sc->block[blk];
1453 txd = (sca_descriptor *)(sc->hc->mem_start +
1454 (blkp->txdesc&sc->hc->winmsk));
1455 txda_d = (u_int)sc->hc->mem_start -
1456 (blkp->txdesc & ~sc->hc->winmsk);
1458 txbuf=blkp->txstart;
1459 for(;txbuf<blkp->txend;txbuf += AR_BUF_SIZ, txd++) {
1460 txda = (u_int)&txd[1] - txda_d;
1461 txd->cp = (u_short)(txda & 0xfffful);
1463 txd->bp = (u_short)(txbuf & 0xfffful);
1464 txd->bpb = (u_char)((txbuf >> 16) & 0xff);
1465 TRC(printf("ar%d: txbuf %x, bpb %x, bp %x\n",
1466 sc->unit, txbuf, txd->bpb, txd->bp));
1471 txd->cp = (u_short)(blkp->txdesc & 0xfffful);
1473 blkp->txtail = (u_int)txd - (u_int)sc->hc->mem_start;
1474 TRC(printf("TX Descriptors start %x, end %x.\n",
1479 if(sc->hc->bustype == AR_BUS_ISA)
1480 ARC_SET_SCA(sc->hc, sc->scano);
1482 dmac->dsr = 0; /* Disable DMA */
1483 dmac->dcr = SCA_DCR_ABRT;
1484 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF;
1485 dmac->dir = SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF;
1487 dmac->sarb = (u_char)((sc->block[0].txdesc >> 16) & 0xff);
1492 * Look through the descriptors to see if there is a complete packet
1493 * available. Stop if we get to where the sca is busy.
1495 * Return the length and status of the packet.
1496 * Return nonzero if there is a packet available.
1499 * It seems that we get the interrupt a bit early. The updateing of
1500 * descriptor values is not always completed when this is called.
1503 ar_packet_avail(struct ar_softc *sc,
1508 sca_descriptor *rxdesc;
1509 sca_descriptor *endp;
1510 sca_descriptor *cda;
1512 if(sc->hc->bustype == AR_BUS_ISA)
1513 ARC_SET_SCA(sc->hc, sc->scano);
1514 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1515 cda = (sca_descriptor *)(sc->hc->mem_start +
1516 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk));
1518 if(sc->hc->bustype == AR_BUS_ISA)
1519 ARC_SET_MEM(sc->hc, sc->rxdesc);
1520 rxdesc = (sca_descriptor *)
1521 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1523 rxdesc = &rxdesc[sc->rxhind];
1524 endp = &endp[sc->rxmax];
1528 while(rxdesc != cda) {
1529 *len += rxdesc->len;
1531 if(rxdesc->stat & SCA_DESC_EOM) {
1532 *rxstat = rxdesc->stat;
1533 TRC(printf("ar%d: PKT AVAIL len %d, %x.\n",
1534 sc->unit, *len, *rxstat));
1540 rxdesc = (sca_descriptor *)
1541 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1551 * Copy a packet from the on card memory into a provided mbuf.
1552 * Take into account that buffers wrap and that a packet may
1553 * be larger than a buffer.
1556 ar_copy_rxbuf(struct mbuf *m,
1557 struct ar_softc *sc,
1560 sca_descriptor *rxdesc;
1566 rxdata = sc->rxstart + (sc->rxhind * AR_BUF_SIZ);
1567 rxmax = sc->rxstart + (sc->rxmax * AR_BUF_SIZ);
1569 rxdesc = (sca_descriptor *)
1570 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1571 rxdesc = &rxdesc[sc->rxhind];
1574 tlen = (len < AR_BUF_SIZ) ? len : AR_BUF_SIZ;
1575 if(sc->hc->bustype == AR_BUS_ISA)
1576 ARC_SET_MEM(sc->hc, rxdata);
1577 bcopy(sc->hc->mem_start + (rxdata & sc->hc->winmsk),
1578 mtod(m, caddr_t) + off,
1584 if(sc->hc->bustype == AR_BUS_ISA)
1585 ARC_SET_MEM(sc->hc, sc->rxdesc);
1587 rxdesc->stat = 0xff;
1589 rxdata += AR_BUF_SIZ;
1591 if(rxdata == rxmax) {
1592 rxdata = sc->rxstart;
1593 rxdesc = (sca_descriptor *)
1594 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1600 * If single is set, just eat a packet. Otherwise eat everything up to
1601 * where cda points. Update pointers to point to the next packet.
1604 ar_eat_packet(struct ar_softc *sc, int single)
1607 sca_descriptor *rxdesc;
1608 sca_descriptor *endp;
1609 sca_descriptor *cda;
1613 if(sc->hc->bustype == AR_BUS_ISA)
1614 ARC_SET_SCA(sc->hc, sc->scano);
1615 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1616 cda = (sca_descriptor *)(sc->hc->mem_start +
1617 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk));
1620 * Loop until desc->stat == (0xff || EOM)
1621 * Clear the status and length in the descriptor.
1622 * Increment the descriptor.
1624 if(sc->hc->bustype == AR_BUS_ISA)
1625 ARC_SET_MEM(sc->hc, sc->rxdesc);
1626 rxdesc = (sca_descriptor *)
1627 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1629 rxdesc = &rxdesc[sc->rxhind];
1630 endp = &endp[sc->rxmax];
1632 while(rxdesc != cda) {
1634 if(loopcnt > sc->rxmax) {
1635 printf("ar%d: eat pkt %d loop, cda %p, "
1636 "rxdesc %p, stat %x.\n",
1645 stat = rxdesc->stat;
1648 rxdesc->stat = 0xff;
1652 if(rxdesc == endp) {
1653 rxdesc = (sca_descriptor *)
1654 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1658 if(single && (stat == SCA_DESC_EOM))
1663 * Update the eda to the previous descriptor.
1665 if(sc->hc->bustype == AR_BUS_ISA)
1666 ARC_SET_SCA(sc->hc, sc->scano);
1668 rxdesc = (sca_descriptor *)sc->rxdesc;
1669 rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax];
1671 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda =
1672 (u_short)((u_int)rxdesc & 0xffff);
1677 * While there is packets available in the rx buffer, read them out
1678 * into mbufs and ship them off.
1681 ar_get_packets(struct ar_softc *sc)
1683 sca_descriptor *rxdesc;
1684 struct mbuf *m = NULL;
1692 while(ar_packet_avail(sc, &len, &rxstat)) {
1693 TRC(printf("apa: len %d, rxstat %x\n", len, rxstat));
1694 if(((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) {
1695 m = m_getl(len, MB_DONTWAIT, MT_DATA, M_PKTHDR, NULL);
1697 /* eat packet if get mbuf fail!! */
1698 ar_eat_packet(sc, 1);
1702 m->m_pkthdr.rcvif = NULL;
1706 m->m_pkthdr.rcvif = &sc->ifsppp.pp_if;
1708 m->m_pkthdr.len = m->m_len = len;
1709 ar_copy_rxbuf(m, sc, len);
1711 NG_SEND_DATA_ONLY(error, sc->hook, m);
1714 BPF_MTAP(&sc->ifsppp.pp_if, m);
1715 sppp_input(&sc->ifsppp.pp_if, m);
1716 sc->ifsppp.pp_if.if_ipackets++;
1719 * Update the eda to the previous descriptor.
1721 i = (len + AR_BUF_SIZ - 1) / AR_BUF_SIZ;
1722 sc->rxhind = (sc->rxhind + i) % sc->rxmax;
1724 if(sc->hc->bustype == AR_BUS_ISA)
1725 ARC_SET_SCA(sc->hc, sc->scano);
1727 rxdesc = (sca_descriptor *)sc->rxdesc;
1729 &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax];
1731 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda =
1732 (u_short)((u_int)rxdesc & 0xffff);
1736 while((rxstat == 0xff) && --tries)
1737 ar_packet_avail(sc, &len, &rxstat);
1740 * It look like we get an interrupt early
1741 * sometimes and then the status is not
1744 if(tries && (tries != 5))
1747 ar_eat_packet(sc, 1);
1750 sc->ifsppp.pp_if.if_ierrors++;
1751 #else /* NETGRAPH */
1753 #endif /* NETGRAPH */
1755 if(sc->hc->bustype == AR_BUS_ISA)
1756 ARC_SET_SCA(sc->hc, sc->scano);
1758 TRCL(printf("ar%d: Receive error chan %d, "
1759 "stat %x, msci st3 %x,"
1760 "rxhind %d, cda %x, eda %x.\n",
1764 sc->sca->msci[sc->scachan].st3,
1767 DMAC_RXCH(sc->scachan)].cda,
1769 DMAC_RXCH(sc->scachan)].eda));
1776 * All DMA interrupts come here.
1778 * Each channel has two interrupts.
1779 * Interrupt A for errors and Interrupt B for normal stuff like end
1780 * of transmit or receive dmas.
1783 ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr1)
1786 u_char dotxstart = isr1;
1788 struct ar_softc *sc;
1792 sca = hc->sca[scano];
1795 * Shortcut if there is no interrupts for dma channel 0 or 1
1797 if((isr1 & 0x0F) == 0) {
1803 sc = &hc->sc[mch + (NCHAN * scano)];
1809 dmac = &sca->dmac[DMAC_TXCH(mch)];
1811 if(hc->bustype == AR_BUS_ISA)
1812 ARC_SET_SCA(hc, scano);
1817 /* Counter overflow */
1818 if(dsr & SCA_DSR_COF) {
1819 printf("ar%d: TX DMA Counter overflow, "
1820 "txpacket no %lu.\n",
1823 sc->ifsppp.pp_if.if_opackets);
1824 sc->ifsppp.pp_if.if_oerrors++;
1825 #else /* NETGRAPH */
1828 #endif /* NETGRAPH */
1831 /* Buffer overflow */
1832 if(dsr & SCA_DSR_BOF) {
1833 printf("ar%d: TX DMA Buffer overflow, "
1834 "txpacket no %lu, dsr %02x, "
1835 "cda %04x, eda %04x.\n",
1838 sc->ifsppp.pp_if.if_opackets,
1839 #else /* NETGRAPH */
1841 #endif /* NETGRAPH */
1846 sc->ifsppp.pp_if.if_oerrors++;
1847 #else /* NETGRAPH */
1849 #endif /* NETGRAPH */
1852 /* End of Transfer */
1853 if(dsr & SCA_DSR_EOT) {
1855 * This should be the most common case.
1857 * Clear the IFF_OACTIVE flag.
1859 * Call arstart to start a new transmit if
1860 * there is data to transmit.
1864 sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE;
1865 sc->ifsppp.pp_if.if_timer = 0;
1866 #else /* NETGRAPH */
1867 /* XXX c->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE; */
1868 sc->out_dog = 0; /* XXX */
1869 #endif /* NETGRAPH */
1871 if(sc->txb_inuse && --sc->txb_inuse)
1880 dmac = &sca->dmac[DMAC_RXCH(mch)];
1882 if(hc->bustype == AR_BUS_ISA)
1883 ARC_SET_SCA(hc, scano);
1888 TRC(printf("AR: RX DSR %x\n", dsr));
1891 if(dsr & SCA_DSR_EOM) {
1892 TRC(int tt = sc->ifsppp.pp_if.if_ipackets;)
1893 TRC(int ind = sc->rxhind;)
1897 #define IPACKETS sc->ifsppp.pp_if.if_ipackets
1898 #else /* NETGRAPH */
1899 #define IPACKETS sc->ipackets
1900 #endif /* NETGRAPH */
1901 TRC(if(tt == IPACKETS) {
1902 sca_descriptor *rxdesc;
1905 if(hc->bustype == AR_BUS_ISA)
1906 ARC_SET_SCA(hc, scano);
1907 printf("AR: RXINTR isr1 %x, dsr %x, "
1908 "no data %d pkts, orxhind %d.\n",
1913 printf("AR: rxdesc %x, rxstart %x, "
1914 "rxend %x, rxhind %d, "
1921 printf("AR: cda %x, eda %x.\n",
1925 if(sc->hc->bustype == AR_BUS_ISA)
1928 rxdesc = (sca_descriptor *)
1929 (sc->hc->mem_start +
1930 (sc->rxdesc & sc->hc->winmsk));
1931 rxdesc = &rxdesc[sc->rxhind];
1932 for(i=0;i<3;i++,rxdesc++)
1933 printf("AR: rxdesc->stat %x, "
1940 /* Counter overflow */
1941 if(dsr & SCA_DSR_COF) {
1942 printf("ar%d: RX DMA Counter overflow, "
1946 sc->ifsppp.pp_if.if_ipackets);
1947 sc->ifsppp.pp_if.if_ierrors++;
1948 #else /* NETGRAPH */
1951 #endif /* NETGRAPH */
1954 /* Buffer overflow */
1955 if(dsr & SCA_DSR_BOF) {
1956 if(hc->bustype == AR_BUS_ISA)
1957 ARC_SET_SCA(hc, scano);
1958 printf("ar%d: RX DMA Buffer overflow, "
1959 "rxpkts %lu, rxind %d, "
1960 "cda %x, eda %x, dsr %x.\n",
1963 sc->ifsppp.pp_if.if_ipackets,
1964 #else /* NETGRAPH */
1966 #endif /* NETGRAPH */
1972 * Make sure we eat as many as possible.
1973 * Then get the system running again.
1975 ar_eat_packet(sc, 0);
1977 sc->ifsppp.pp_if.if_ierrors++;
1978 #else /* NETGRAPH */
1980 #endif /* NETGRAPH */
1981 if(hc->bustype == AR_BUS_ISA)
1982 ARC_SET_SCA(hc, scano);
1983 sca->msci[mch].cmd = SCA_CMD_RXMSGREJ;
1984 dmac->dsr = SCA_DSR_DE;
1986 TRC(printf("ar%d: RX DMA Buffer overflow, "
1987 "rxpkts %lu, rxind %d, "
1988 "cda %x, eda %x, dsr %x. After\n",
1990 sc->ifsppp.pp_if.if_ipackets,
1997 /* End of Transfer */
1998 if(dsr & SCA_DSR_EOT) {
2000 * If this happen, it means that we are
2001 * receiving faster than what the processor
2004 * XXX We should enable the dma again.
2006 printf("ar%d: RX End of transfer, rxpkts %lu.\n",
2009 sc->ifsppp.pp_if.if_ipackets);
2010 sc->ifsppp.pp_if.if_ierrors++;
2011 #else /* NETGRAPH */
2014 #endif /* NETGRAPH */
2021 }while((mch<NCHAN) && isr1);
2024 * Now that we have done all the urgent things, see if we
2025 * can fill the transmit buffers.
2027 for(mch = 0; mch < NCHAN; mch++) {
2028 if(dotxstart & 0x0C) {
2029 sc = &hc->sc[mch + (NCHAN * scano)];
2031 arstart(&sc->ifsppp.pp_if);
2032 #else /* NETGRAPH */
2034 #endif /* NETGRAPH */
2041 ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr0)
2043 printf("arc%d: ARINTR: MSCI\n", hc->cunit);
2047 ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr2)
2049 printf("arc%d: ARINTR: TIMER\n", hc->cunit);
2054 /*****************************************
2055 * Device timeout/watchdog routine.
2056 * called once per second.
2057 * checks to see that if activity was expected, that it hapenned.
2058 * At present we only look to see if expected output was completed.
2061 ngar_watchdog_frame(void * arg)
2063 struct ar_softc * sc = arg;
2066 if (sc->running == 0) {
2067 return; /* if we are not running let timeouts die */
2070 lwkt_serialize_enter(&ar_serializer);
2073 * calculate the apparent throughputs
2076 speed = sc->inbytes - sc->lastinbytes;
2077 sc->lastinbytes = sc->inbytes;
2078 if ( sc->inrate < speed )
2080 speed = sc->outbytes - sc->lastoutbytes;
2081 sc->lastoutbytes = sc->outbytes;
2082 if ( sc->outrate < speed )
2083 sc->outrate = speed;
2086 if ((sc->inlast > QUITE_A_WHILE)
2087 && (sc->out_deficit > LOTS_OF_PACKETS)) {
2088 log(LOG_ERR, "ar%d: No response from remote end\n", sc->unit);
2092 sc->inlast = sc->out_deficit = 0;
2093 } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */
2094 if (sc->out_dog == 0) {
2095 log(LOG_ERR, "ar%d: Transmit failure.. no clock?\n",
2103 sc->inlast = sc->out_deficit = 0;
2108 lwkt_serialize_exit(&ar_serializer);
2109 callout_reset(&sc->timer, hz, ngar_watchdog_frame, sc);
2112 /***********************************************************************
2113 * This section contains the methods for the Netgraph interface
2114 ***********************************************************************/
2116 * It is not possible or allowable to create a node of this type.
2117 * If the hardware exists, it will already have created it.
2120 ngar_constructor(node_p *nodep)
2126 * give our ok for a hook to be added...
2127 * If we are not running this should kick the device into life.
2128 * The hook's private info points to our stash of info about that
2132 ngar_newhook(node_p node, hook_p hook, const char *name)
2134 struct ar_softc * sc = NG_NODE_PRIVATE(node);
2137 * check if it's our friend the debug hook
2139 if (strcmp(name, NG_AR_HOOK_DEBUG) == 0) {
2140 NG_HOOK_SET_PRIVATE(hook, NULL); /* paranoid */
2141 sc->debug_hook = hook;
2146 * Check for raw mode hook.
2148 if (strcmp(name, NG_AR_HOOK_RAW) != 0) {
2151 NG_HOOK_SET_PRIVATE(hook, sc);
2159 * incoming messages.
2160 * Just respond to the generic TEXT_STATUS message
2163 ngar_rcvmsg(node_p node, struct ng_mesg *msg, const char *retaddr,
2164 struct ng_mesg **rptr)
2166 struct ar_softc *sc;
2168 struct ng_mesg *resp = NULL;
2170 sc = NG_NODE_PRIVATE(node);
2171 switch (msg->header.typecookie) {
2175 case NGM_GENERIC_COOKIE:
2176 switch(msg->header.cmd) {
2177 case NGM_TEXT_STATUS: {
2181 int resplen = sizeof(struct ng_mesg) + 512;
2182 NG_MKRESPONSE(resp, msg, resplen, M_INTWAIT);
2188 pos = sprintf(arg, "%ld bytes in, %ld bytes out\n"
2189 "highest rate seen: %ld B/S in, %ld B/S out\n",
2190 sc->inbytes, sc->outbytes,
2191 sc->inrate, sc->outrate);
2192 pos += sprintf(arg + pos,
2193 "%ld output errors\n",
2195 pos += sprintf(arg + pos,
2196 "ierrors = %ld, %ld, %ld, %ld\n",
2202 (resp)->header.arglen = pos + 1;
2214 /* Take care of synchronous response, if any */
2215 NG_RESPOND_MSG(error, node, retaddr, resp, rptr);
2221 * get data from another node and transmit it to the correct channel
2224 ngar_rcvdata(hook_p hook, struct mbuf *m, meta_p meta)
2227 struct ar_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook));
2228 struct ifqueue *xmitq_p;
2231 * data doesn't come in from just anywhere (e.g control hook)
2233 if ( NG_HOOK_PRIVATE(hook) == NULL) {
2239 * Now queue the data for when it can be sent
2241 if (meta && meta->priority > 0)
2242 xmitq_p = (&sc->xmitq_hipri);
2244 xmitq_p = (&sc->xmitq);
2246 if (IF_QFULL(xmitq_p)) {
2252 IF_ENQUEUE(xmitq_p, m);
2259 * It was an error case.
2260 * check if we need to free the mbuf, and then return the error
2262 NG_FREE_DATA(m, meta);
2267 * do local shutdown processing..
2268 * this node will refuse to go away, unless the hardware says to..
2269 * don't unref the node, or remove our name. just clear our links up.
2272 ngar_shutdown(node_p node)
2274 struct ar_softc * sc = NG_NODE_PRIVATE(node);
2277 NG_NODE_UNREF(node);
2278 /* XXX need to drain the output queues! */
2280 /* The node is dead, long live the node! */
2281 /* stolen from the attach routine */
2282 if (ng_make_node_common(&typestruct, &sc->node) != 0)
2284 sprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit);
2285 if (ng_name_node(sc->node, sc->nodename)) {
2287 printf("node naming failed\n");
2288 NG_NODE_UNREF(sc->node); /* node dissappears */
2291 NG_NODE_SET_PRIVATE(sc->node, sc);
2296 /* already linked */
2298 ngar_connect(hook_p hook)
2300 /* be really amiable and just say "YUP that's OK by me! " */
2305 * notify on hook disconnection (destruction)
2307 * Invalidate the private data associated with this dlci.
2308 * For this type, removal of the last link resets tries to destroy the node.
2309 * As the device still exists, the shutdown method will not actually
2310 * destroy the node, but reset the device and leave it 'fresh' :)
2312 * The node removal code will remove all references except that owned by the
2316 ngar_disconnect(hook_p hook)
2318 struct ar_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook));
2321 * If it's the data hook, then free resources etc.
2323 if (NG_HOOK_PRIVATE(hook)) {
2325 if (sc->datahooks == 0)
2328 sc->debug_hook = NULL;
2334 * called during bootup
2335 * or LKM loading to put this type into the list of known modules
2338 ngar_init(void *ignored)
2340 if (ng_newtype(&typestruct))
2341 printf("ngar install failed\n");
2344 #endif /* NETGRAPH */
2347 ********************************* END ************************************