2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/pci/pci.c,v 1.355.2.9.2.1 2009/04/15 03:14:26 kensmith Exp $
33 #include "opt_compat_oldpci.h"
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
39 #include <sys/linker.h>
40 #include <sys/fcntl.h>
42 #include <sys/kernel.h>
43 #include <sys/queue.h>
44 #include <sys/sysctl.h>
45 #include <sys/endian.h>
49 #include <vm/vm_extern.h>
53 #include <sys/device.h>
55 #include <sys/pciio.h>
56 #include <bus/pci/pcireg.h>
57 #include <bus/pci/pcivar.h>
58 #include <bus/pci/pci_private.h>
64 #include <contrib/dev/acpica/acpi.h>
67 #define ACPI_PWR_FOR_SLEEP(x, y, z)
70 extern struct dev_ops pcic_ops; /* XXX */
72 typedef void (*pci_read_cap_t)(device_t, int, int, pcicfgregs *);
74 static uint32_t pci_mapbase(unsigned mapreg);
75 static const char *pci_maptype(unsigned mapreg);
76 static int pci_mapsize(unsigned testval);
77 static int pci_maprange(unsigned mapreg);
78 static void pci_fixancient(pcicfgregs *cfg);
80 static int pci_porten(device_t pcib, int b, int s, int f);
81 static int pci_memen(device_t pcib, int b, int s, int f);
82 static void pci_assign_interrupt(device_t bus, device_t dev,
84 static int pci_add_map(device_t pcib, device_t bus, device_t dev,
85 int b, int s, int f, int reg,
86 struct resource_list *rl, int force, int prefetch);
87 static int pci_probe(device_t dev);
88 static int pci_attach(device_t dev);
89 static void pci_child_detached(device_t, device_t);
90 static void pci_load_vendor_data(void);
91 static int pci_describe_parse_line(char **ptr, int *vendor,
92 int *device, char **desc);
93 static char *pci_describe_device(device_t dev);
94 static int pci_modevent(module_t mod, int what, void *arg);
95 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
97 static void pci_read_capabilities(device_t pcib, pcicfgregs *cfg);
98 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
99 int reg, uint32_t *data);
101 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
102 int reg, uint32_t data);
104 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
105 static void pci_disable_msi(device_t dev);
106 static void pci_enable_msi(device_t dev, uint64_t address,
108 static void pci_enable_msix(device_t dev, u_int index,
109 uint64_t address, uint32_t data);
110 static void pci_mask_msix(device_t dev, u_int index);
111 static void pci_unmask_msix(device_t dev, u_int index);
112 static int pci_msi_blacklisted(void);
113 static void pci_resume_msi(device_t dev);
114 static void pci_resume_msix(device_t dev);
115 static int pcie_slotimpl(const pcicfgregs *);
116 static void pci_print_verbose_expr(const pcicfgregs *);
118 static void pci_read_cap_pmgt(device_t, int, int, pcicfgregs *);
119 static void pci_read_cap_ht(device_t, int, int, pcicfgregs *);
120 static void pci_read_cap_msi(device_t, int, int, pcicfgregs *);
121 static void pci_read_cap_msix(device_t, int, int, pcicfgregs *);
122 static void pci_read_cap_vpd(device_t, int, int, pcicfgregs *);
123 static void pci_read_cap_subvendor(device_t, int, int,
125 static void pci_read_cap_pcix(device_t, int, int, pcicfgregs *);
126 static void pci_read_cap_express(device_t, int, int, pcicfgregs *);
128 static device_method_t pci_methods[] = {
129 /* Device interface */
130 DEVMETHOD(device_probe, pci_probe),
131 DEVMETHOD(device_attach, pci_attach),
132 DEVMETHOD(device_detach, bus_generic_detach),
133 DEVMETHOD(device_shutdown, bus_generic_shutdown),
134 DEVMETHOD(device_suspend, pci_suspend),
135 DEVMETHOD(device_resume, pci_resume),
138 DEVMETHOD(bus_print_child, pci_print_child),
139 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
140 DEVMETHOD(bus_read_ivar, pci_read_ivar),
141 DEVMETHOD(bus_write_ivar, pci_write_ivar),
142 DEVMETHOD(bus_driver_added, pci_driver_added),
143 DEVMETHOD(bus_child_detached, pci_child_detached),
144 DEVMETHOD(bus_setup_intr, pci_setup_intr),
145 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
147 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
148 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
149 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
150 DEVMETHOD(bus_delete_resource, pci_delete_resource),
151 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
152 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
153 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
154 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
155 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
156 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
159 DEVMETHOD(pci_read_config, pci_read_config_method),
160 DEVMETHOD(pci_write_config, pci_write_config_method),
161 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
162 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
163 DEVMETHOD(pci_enable_io, pci_enable_io_method),
164 DEVMETHOD(pci_disable_io, pci_disable_io_method),
165 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
166 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
167 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
168 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
169 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
170 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
171 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
172 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
173 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
174 DEVMETHOD(pci_release_msi, pci_release_msi_method),
175 DEVMETHOD(pci_msi_count, pci_msi_count_method),
176 DEVMETHOD(pci_msix_count, pci_msix_count_method),
181 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
183 static devclass_t pci_devclass;
184 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
185 MODULE_VERSION(pci, 1);
187 static char *pci_vendordata;
188 static size_t pci_vendordata_size;
191 static const struct pci_read_cap {
193 pci_read_cap_t read_cap;
194 } pci_read_caps[] = {
195 { PCIY_PMG, pci_read_cap_pmgt },
196 { PCIY_HT, pci_read_cap_ht },
197 { PCIY_MSI, pci_read_cap_msi },
198 { PCIY_MSIX, pci_read_cap_msix },
199 { PCIY_VPD, pci_read_cap_vpd },
200 { PCIY_SUBVENDOR, pci_read_cap_subvendor },
201 { PCIY_PCIX, pci_read_cap_pcix },
202 { PCIY_EXPRESS, pci_read_cap_express },
203 { 0, NULL } /* required last entry */
207 uint32_t devid; /* Vendor/device of the card */
209 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
210 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
215 struct pci_quirk pci_quirks[] = {
216 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
217 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
218 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
219 /* As does the Serverworks OSB4 (the SMBus mapping register) */
220 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
223 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
224 * or the CMIC-SL (AKA ServerWorks GC_LE).
226 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
227 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
230 * MSI doesn't work on earlier Intel chipsets including
231 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
233 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
234 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
235 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
236 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
237 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
238 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
239 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
242 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
245 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
250 /* map register information */
251 #define PCI_MAPMEM 0x01 /* memory map */
252 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
253 #define PCI_MAPPORT 0x04 /* port map */
255 struct devlist pci_devq;
256 uint32_t pci_generation;
257 uint32_t pci_numdevs = 0;
258 static int pcie_chipset, pcix_chipset;
261 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
263 static int pci_enable_io_modes = 1;
264 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
265 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
266 &pci_enable_io_modes, 1,
267 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
268 enable these bits correctly. We'd like to do this all the time, but there\n\
269 are some peripherals that this causes problems with.");
271 static int pci_do_power_nodriver = 0;
272 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
273 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
274 &pci_do_power_nodriver, 0,
275 "Place a function into D3 state when no driver attaches to it. 0 means\n\
276 disable. 1 means conservatively place devices into D3 state. 2 means\n\
277 aggressively place devices into D3 state. 3 means put absolutely everything\n\
280 static int pci_do_power_resume = 1;
281 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
282 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
283 &pci_do_power_resume, 1,
284 "Transition from D3 -> D0 on resume.");
286 static int pci_do_msi = 1;
287 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
288 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
289 "Enable support for MSI interrupts");
291 static int pci_do_msix = 1;
292 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
293 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
294 "Enable support for MSI-X interrupts");
296 static int pci_honor_msi_blacklist = 1;
297 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
298 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
299 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
301 /* Find a device_t by bus/slot/function in domain 0 */
304 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
307 return (pci_find_dbsf(0, bus, slot, func));
310 /* Find a device_t by domain/bus/slot/function */
313 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
315 struct pci_devinfo *dinfo;
317 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
318 if ((dinfo->cfg.domain == domain) &&
319 (dinfo->cfg.bus == bus) &&
320 (dinfo->cfg.slot == slot) &&
321 (dinfo->cfg.func == func)) {
322 return (dinfo->cfg.dev);
329 /* Find a device_t by vendor/device ID */
332 pci_find_device(uint16_t vendor, uint16_t device)
334 struct pci_devinfo *dinfo;
336 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
337 if ((dinfo->cfg.vendor == vendor) &&
338 (dinfo->cfg.device == device)) {
339 return (dinfo->cfg.dev);
346 /* return base address of memory or port map */
349 pci_mapbase(uint32_t mapreg)
352 if (PCI_BAR_MEM(mapreg))
353 return (mapreg & PCIM_BAR_MEM_BASE);
355 return (mapreg & PCIM_BAR_IO_BASE);
358 /* return map type of memory or port map */
361 pci_maptype(unsigned mapreg)
364 if (PCI_BAR_IO(mapreg))
366 if (mapreg & PCIM_BAR_MEM_PREFETCH)
367 return ("Prefetchable Memory");
371 /* return log2 of map size decoded for memory or port map */
374 pci_mapsize(uint32_t testval)
378 testval = pci_mapbase(testval);
381 while ((testval & 1) == 0)
390 /* return log2 of address range supported by map register */
393 pci_maprange(unsigned mapreg)
397 if (PCI_BAR_IO(mapreg))
400 switch (mapreg & PCIM_BAR_MEM_TYPE) {
401 case PCIM_BAR_MEM_32:
404 case PCIM_BAR_MEM_1MB:
407 case PCIM_BAR_MEM_64:
414 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
417 pci_fixancient(pcicfgregs *cfg)
419 if (cfg->hdrtype != 0)
422 /* PCI to PCI bridges use header type 1 */
423 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
427 /* extract header type specific config data */
430 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
432 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
433 switch (cfg->hdrtype) {
435 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
436 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
437 cfg->nummaps = PCI_MAXMAPS_0;
440 cfg->nummaps = PCI_MAXMAPS_1;
442 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
446 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
447 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
448 cfg->nummaps = PCI_MAXMAPS_2;
450 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
457 /* read configuration header into pcicfgregs structure */
459 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
461 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
462 pcicfgregs *cfg = NULL;
463 struct pci_devinfo *devlist_entry;
464 struct devlist *devlist_head;
466 devlist_head = &pci_devq;
468 devlist_entry = NULL;
470 if (REG(PCIR_DEVVENDOR, 4) != -1) {
471 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
473 cfg = &devlist_entry->cfg;
479 cfg->vendor = REG(PCIR_VENDOR, 2);
480 cfg->device = REG(PCIR_DEVICE, 2);
481 cfg->cmdreg = REG(PCIR_COMMAND, 2);
482 cfg->statreg = REG(PCIR_STATUS, 2);
483 cfg->baseclass = REG(PCIR_CLASS, 1);
484 cfg->subclass = REG(PCIR_SUBCLASS, 1);
485 cfg->progif = REG(PCIR_PROGIF, 1);
486 cfg->revid = REG(PCIR_REVID, 1);
487 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
488 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
489 cfg->lattimer = REG(PCIR_LATTIMER, 1);
490 cfg->intpin = REG(PCIR_INTPIN, 1);
491 cfg->intline = REG(PCIR_INTLINE, 1);
493 cfg->mingnt = REG(PCIR_MINGNT, 1);
494 cfg->maxlat = REG(PCIR_MAXLAT, 1);
496 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
497 cfg->hdrtype &= ~PCIM_MFDEV;
500 pci_hdrtypedata(pcib, b, s, f, cfg);
502 pci_read_capabilities(pcib, cfg);
504 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
506 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
507 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
508 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
509 devlist_entry->conf.pc_sel.pc_func = cfg->func;
510 devlist_entry->conf.pc_hdr = cfg->hdrtype;
512 devlist_entry->conf.pc_subvendor = cfg->subvendor;
513 devlist_entry->conf.pc_subdevice = cfg->subdevice;
514 devlist_entry->conf.pc_vendor = cfg->vendor;
515 devlist_entry->conf.pc_device = cfg->device;
517 devlist_entry->conf.pc_class = cfg->baseclass;
518 devlist_entry->conf.pc_subclass = cfg->subclass;
519 devlist_entry->conf.pc_progif = cfg->progif;
520 devlist_entry->conf.pc_revid = cfg->revid;
525 return (devlist_entry);
530 pci_fixup_nextptr(int *nextptr0)
532 int nextptr = *nextptr0;
534 /* "Next pointer" is only one byte */
535 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
539 * PCI local bus spec 3.0:
541 * "... The bottom two bits of all pointers are reserved
542 * and must be implemented as 00b although software must
543 * mask them to allow for future uses of these bits ..."
546 kprintf("Illegal PCI extended capability "
547 "offset, fixup 0x%02x -> 0x%02x\n",
548 nextptr, nextptr & ~0x3);
554 if (nextptr < 0x40) {
556 kprintf("Illegal PCI extended capability "
557 "offset 0x%02x", nextptr);
565 pci_read_cap_pmgt(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
568 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
570 struct pcicfg_pp *pp = &cfg->pp;
575 pp->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
576 pp->pp_status = ptr + PCIR_POWER_STATUS;
577 pp->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
579 if ((nextptr - ptr) > PCIR_POWER_DATA) {
582 * We should write to data_select and read back from
583 * data_scale to determine whether data register is
587 pp->pp_data = ptr + PCIR_POWER_DATA;
597 pci_read_cap_ht(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
600 #if defined(__i386__) || defined(__x86_64__)
603 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
605 struct pcicfg_ht *ht = &cfg->ht;
609 /* Determine HT-specific capability type. */
610 val = REG(ptr + PCIR_HT_COMMAND, 2);
612 if ((val & PCIM_HTCMD_CAP_MASK) != PCIM_HTCAP_MSI_MAPPING)
615 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
616 /* Sanity check the mapping window. */
617 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 4);
619 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 4);
620 if (addr != MSI_INTEL_ADDR_BASE) {
621 device_printf(pcib, "HT Bridge at pci%d:%d:%d:%d "
622 "has non-default MSI window 0x%llx\n",
623 cfg->domain, cfg->bus, cfg->slot, cfg->func,
627 addr = MSI_INTEL_ADDR_BASE;
631 ht->ht_msictrl = val;
632 ht->ht_msiaddr = addr;
636 #endif /* __i386__ || __x86_64__ */
641 pci_read_cap_msi(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
644 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
646 struct pcicfg_msi *msi = &cfg->msi;
648 msi->msi_location = ptr;
649 msi->msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
650 msi->msi_msgnum = 1 << ((msi->msi_ctrl & PCIM_MSICTRL_MMC_MASK) >> 1);
656 pci_read_cap_msix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
659 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
661 struct pcicfg_msix *msix = &cfg->msix;
664 msix->msix_location = ptr;
665 msix->msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
666 msix->msix_msgnum = (msix->msix_ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
668 val = REG(ptr + PCIR_MSIX_TABLE, 4);
669 msix->msix_table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
670 msix->msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
672 val = REG(ptr + PCIR_MSIX_PBA, 4);
673 msix->msix_pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
674 msix->msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
680 pci_read_cap_vpd(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
682 cfg->vpd.vpd_reg = ptr;
686 pci_read_cap_subvendor(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
689 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
691 /* Should always be true. */
692 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
695 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
696 cfg->subvendor = val & 0xffff;
697 cfg->subdevice = val >> 16;
704 pci_read_cap_pcix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
707 * Assume we have a PCI-X chipset if we have
708 * at least one PCI-PCI bridge with a PCI-X
709 * capability. Note that some systems with
710 * PCI-express or HT chipsets might match on
711 * this check as well.
713 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
716 cfg->pcix.pcix_ptr = ptr;
720 pcie_slotimpl(const pcicfgregs *cfg)
722 const struct pcicfg_expr *expr = &cfg->expr;
726 * Only version 1 can be parsed currently
728 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
732 * - Slot implemented bit is meaningful iff current port is
733 * root port or down stream port.
734 * - Testing for root port or down stream port is meanningful
735 * iff PCI configure has type 1 header.
738 if (cfg->hdrtype != 1)
741 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
742 if (port_type != PCIE_ROOT_PORT && port_type != PCIE_DOWN_STREAM_PORT)
745 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
752 pci_read_cap_express(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
755 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
757 struct pcicfg_expr *expr = &cfg->expr;
760 * Assume we have a PCI-express chipset if we have
761 * at least one PCI-express device.
765 expr->expr_ptr = ptr;
766 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2);
769 * Only version 1 can be parsed currently
771 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
775 * Read slot capabilities. Slot capabilities exists iff
776 * current port's slot is implemented
778 if (pcie_slotimpl(cfg))
779 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4);
785 pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
787 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
788 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
793 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
794 /* No capabilities */
798 switch (cfg->hdrtype & PCIM_HDRTYPE) {
801 ptrptr = PCIR_CAP_PTR;
804 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
807 return; /* no capabilities support */
809 nextptr = REG(ptrptr, 1); /* sanity check? */
812 * Read capability entries.
814 while (pci_fixup_nextptr(&nextptr)) {
815 const struct pci_read_cap *rc;
818 /* Find the next entry */
819 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
821 /* Process this entry */
822 val = REG(ptr + PCICAP_ID, 1);
823 for (rc = pci_read_caps; rc->read_cap != NULL; ++rc) {
824 if (rc->cap == val) {
825 rc->read_cap(pcib, ptr, nextptr, cfg);
830 /* REG and WREG use carry through to next functions */
834 * PCI Vital Product Data
837 #define PCI_VPD_TIMEOUT 1000000
840 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
842 int count = PCI_VPD_TIMEOUT;
844 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
846 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
848 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
851 DELAY(1); /* limit looping */
853 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
860 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
862 int count = PCI_VPD_TIMEOUT;
864 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
866 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
867 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
868 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
871 DELAY(1); /* limit looping */
878 #undef PCI_VPD_TIMEOUT
880 struct vpd_readstate {
890 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
895 if (vrs->bytesinval == 0) {
896 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
898 vrs->val = le32toh(reg);
900 byte = vrs->val & 0xff;
903 vrs->val = vrs->val >> 8;
904 byte = vrs->val & 0xff;
914 pcie_slot_implemented(device_t dev)
916 struct pci_devinfo *dinfo = device_get_ivars(dev);
918 return pcie_slotimpl(&dinfo->cfg);
922 pcie_set_max_readrq(device_t dev, uint16_t rqsize)
927 rqsize &= PCIEM_DEVCTL_MAX_READRQ_MASK;
928 if (rqsize > PCIEM_DEVCTL_MAX_READRQ_4096) {
929 panic("%s: invalid max read request size 0x%02x\n",
930 device_get_nameunit(dev), rqsize);
933 expr_ptr = pci_get_pciecap_ptr(dev);
935 panic("%s: not PCIe device\n", device_get_nameunit(dev));
937 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
938 if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) != rqsize) {
940 device_printf(dev, "adjust device control 0x%04x", val);
942 val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK;
944 pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2);
947 kprintf(" -> 0x%04x\n", val);
952 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
954 struct vpd_readstate vrs;
959 int alloc, off; /* alloc/off for RO/W arrays */
965 /* init vpd reader */
973 name = remain = i = 0; /* shut up stupid gcc */
974 alloc = off = 0; /* shut up stupid gcc */
975 dflen = 0; /* shut up stupid gcc */
978 if (vpd_nextbyte(&vrs, &byte)) {
983 kprintf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
984 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
985 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
988 case 0: /* item name */
990 if (vpd_nextbyte(&vrs, &byte2)) {
995 if (vpd_nextbyte(&vrs, &byte2)) {
999 remain |= byte2 << 8;
1000 if (remain > (0x7f*4 - vrs.off)) {
1003 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
1004 cfg->domain, cfg->bus, cfg->slot,
1009 remain = byte & 0x7;
1010 name = (byte >> 3) & 0xf;
1013 case 0x2: /* String */
1014 cfg->vpd.vpd_ident = kmalloc(remain + 1,
1015 M_DEVBUF, M_WAITOK);
1022 case 0x10: /* VPD-R */
1025 cfg->vpd.vpd_ros = kmalloc(alloc *
1026 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
1030 case 0x11: /* VPD-W */
1033 cfg->vpd.vpd_w = kmalloc(alloc *
1034 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
1038 default: /* Invalid data, abort */
1044 case 1: /* Identifier String */
1045 cfg->vpd.vpd_ident[i++] = byte;
1048 cfg->vpd.vpd_ident[i] = '\0';
1053 case 2: /* VPD-R Keyword Header */
1055 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1056 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
1057 M_DEVBUF, M_WAITOK | M_ZERO);
1059 cfg->vpd.vpd_ros[off].keyword[0] = byte;
1060 if (vpd_nextbyte(&vrs, &byte2)) {
1064 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
1065 if (vpd_nextbyte(&vrs, &byte2)) {
1071 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
1074 * if this happens, we can't trust the rest
1078 "pci%d:%d:%d:%d: bad keyword length: %d\n",
1079 cfg->domain, cfg->bus, cfg->slot,
1084 } else if (dflen == 0) {
1085 cfg->vpd.vpd_ros[off].value = kmalloc(1 *
1086 sizeof(*cfg->vpd.vpd_ros[off].value),
1087 M_DEVBUF, M_WAITOK);
1088 cfg->vpd.vpd_ros[off].value[0] = '\x00';
1090 cfg->vpd.vpd_ros[off].value = kmalloc(
1092 sizeof(*cfg->vpd.vpd_ros[off].value),
1093 M_DEVBUF, M_WAITOK);
1096 /* keep in sync w/ state 3's transistions */
1097 if (dflen == 0 && remain == 0)
1099 else if (dflen == 0)
1105 case 3: /* VPD-R Keyword Value */
1106 cfg->vpd.vpd_ros[off].value[i++] = byte;
1107 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1108 "RV", 2) == 0 && cksumvalid == -1) {
1114 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
1115 cfg->domain, cfg->bus,
1116 cfg->slot, cfg->func,
1125 /* keep in sync w/ state 2's transistions */
1127 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1128 if (dflen == 0 && remain == 0) {
1129 cfg->vpd.vpd_rocnt = off;
1130 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1131 off * sizeof(*cfg->vpd.vpd_ros),
1132 M_DEVBUF, M_WAITOK | M_ZERO);
1134 } else if (dflen == 0)
1144 case 5: /* VPD-W Keyword Header */
1146 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1147 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1148 M_DEVBUF, M_WAITOK | M_ZERO);
1150 cfg->vpd.vpd_w[off].keyword[0] = byte;
1151 if (vpd_nextbyte(&vrs, &byte2)) {
1155 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1156 if (vpd_nextbyte(&vrs, &byte2)) {
1160 cfg->vpd.vpd_w[off].len = dflen = byte2;
1161 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1162 cfg->vpd.vpd_w[off].value = kmalloc((dflen + 1) *
1163 sizeof(*cfg->vpd.vpd_w[off].value),
1164 M_DEVBUF, M_WAITOK);
1167 /* keep in sync w/ state 6's transistions */
1168 if (dflen == 0 && remain == 0)
1170 else if (dflen == 0)
1176 case 6: /* VPD-W Keyword Value */
1177 cfg->vpd.vpd_w[off].value[i++] = byte;
1180 /* keep in sync w/ state 5's transistions */
1182 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1183 if (dflen == 0 && remain == 0) {
1184 cfg->vpd.vpd_wcnt = off;
1185 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1186 off * sizeof(*cfg->vpd.vpd_w),
1187 M_DEVBUF, M_WAITOK | M_ZERO);
1189 } else if (dflen == 0)
1194 kprintf("pci%d:%d:%d:%d: invalid state: %d\n",
1195 cfg->domain, cfg->bus, cfg->slot, cfg->func,
1202 if (cksumvalid == 0 || state < -1) {
1203 /* read-only data bad, clean up */
1204 if (cfg->vpd.vpd_ros != NULL) {
1205 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1206 kfree(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1207 kfree(cfg->vpd.vpd_ros, M_DEVBUF);
1208 cfg->vpd.vpd_ros = NULL;
1212 /* I/O error, clean up */
1213 kprintf("pci%d:%d:%d:%d: failed to read VPD data.\n",
1214 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1215 if (cfg->vpd.vpd_ident != NULL) {
1216 kfree(cfg->vpd.vpd_ident, M_DEVBUF);
1217 cfg->vpd.vpd_ident = NULL;
1219 if (cfg->vpd.vpd_w != NULL) {
1220 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1221 kfree(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1222 kfree(cfg->vpd.vpd_w, M_DEVBUF);
1223 cfg->vpd.vpd_w = NULL;
1226 cfg->vpd.vpd_cached = 1;
1232 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1234 struct pci_devinfo *dinfo = device_get_ivars(child);
1235 pcicfgregs *cfg = &dinfo->cfg;
1237 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1238 pci_read_vpd(device_get_parent(dev), cfg);
1240 *identptr = cfg->vpd.vpd_ident;
1242 if (*identptr == NULL)
1249 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1252 struct pci_devinfo *dinfo = device_get_ivars(child);
1253 pcicfgregs *cfg = &dinfo->cfg;
1256 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1257 pci_read_vpd(device_get_parent(dev), cfg);
1259 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1260 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1261 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1262 *vptr = cfg->vpd.vpd_ros[i].value;
1265 if (i != cfg->vpd.vpd_rocnt)
1273 * Return the offset in configuration space of the requested extended
1274 * capability entry or 0 if the specified capability was not found.
1277 pci_find_extcap_method(device_t dev, device_t child, int capability,
1280 struct pci_devinfo *dinfo = device_get_ivars(child);
1281 pcicfgregs *cfg = &dinfo->cfg;
1286 * Check the CAP_LIST bit of the PCI status register first.
1288 status = pci_read_config(child, PCIR_STATUS, 2);
1289 if (!(status & PCIM_STATUS_CAPPRESENT))
1293 * Determine the start pointer of the capabilities list.
1295 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1301 ptr = PCIR_CAP_PTR_2;
1305 return (ENXIO); /* no extended capabilities support */
1307 ptr = pci_read_config(child, ptr, 1);
1310 * Traverse the capabilities list.
1313 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1318 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1325 * Support for MSI-X message interrupts.
1328 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1330 struct pci_devinfo *dinfo = device_get_ivars(dev);
1331 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1334 KASSERT(msix->msix_table_len > index, ("bogus index"));
1335 offset = msix->msix_table_offset + index * 16;
1336 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1337 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1338 bus_write_4(msix->msix_table_res, offset + 8, data);
1340 /* Enable MSI -> HT mapping. */
1341 pci_ht_map_msi(dev, address);
1345 pci_mask_msix(device_t dev, u_int index)
1347 struct pci_devinfo *dinfo = device_get_ivars(dev);
1348 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1349 uint32_t offset, val;
1351 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1352 offset = msix->msix_table_offset + index * 16 + 12;
1353 val = bus_read_4(msix->msix_table_res, offset);
1354 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1355 val |= PCIM_MSIX_VCTRL_MASK;
1356 bus_write_4(msix->msix_table_res, offset, val);
1361 pci_unmask_msix(device_t dev, u_int index)
1363 struct pci_devinfo *dinfo = device_get_ivars(dev);
1364 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1365 uint32_t offset, val;
1367 KASSERT(msix->msix_table_len > index, ("bogus index"));
1368 offset = msix->msix_table_offset + index * 16 + 12;
1369 val = bus_read_4(msix->msix_table_res, offset);
1370 if (val & PCIM_MSIX_VCTRL_MASK) {
1371 val &= ~PCIM_MSIX_VCTRL_MASK;
1372 bus_write_4(msix->msix_table_res, offset, val);
1377 pci_pending_msix(device_t dev, u_int index)
1379 struct pci_devinfo *dinfo = device_get_ivars(dev);
1380 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1381 uint32_t offset, bit;
1383 KASSERT(msix->msix_table_len > index, ("bogus index"));
1384 offset = msix->msix_pba_offset + (index / 32) * 4;
1385 bit = 1 << index % 32;
1386 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1390 * Restore MSI-X registers and table during resume. If MSI-X is
1391 * enabled then walk the virtual table to restore the actual MSI-X
1395 pci_resume_msix(device_t dev)
1397 struct pci_devinfo *dinfo = device_get_ivars(dev);
1398 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1399 struct msix_table_entry *mte;
1400 struct msix_vector *mv;
1403 if (msix->msix_alloc > 0) {
1404 /* First, mask all vectors. */
1405 for (i = 0; i < msix->msix_msgnum; i++)
1406 pci_mask_msix(dev, i);
1408 /* Second, program any messages with at least one handler. */
1409 for (i = 0; i < msix->msix_table_len; i++) {
1410 mte = &msix->msix_table[i];
1411 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1413 mv = &msix->msix_vectors[mte->mte_vector - 1];
1414 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1415 pci_unmask_msix(dev, i);
1418 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1419 msix->msix_ctrl, 2);
1423 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1424 * returned in *count. After this function returns, each message will be
1425 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1428 pci_alloc_msix_method(device_t dev, device_t child, int *count)
1430 struct pci_devinfo *dinfo = device_get_ivars(child);
1431 pcicfgregs *cfg = &dinfo->cfg;
1432 struct resource_list_entry *rle;
1433 int actual, error, i, irq, max;
1435 /* Don't let count == 0 get us into trouble. */
1439 /* If rid 0 is allocated, then fail. */
1440 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1441 if (rle != NULL && rle->res != NULL)
1444 /* Already have allocated messages? */
1445 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1448 /* If MSI is blacklisted for this system, fail. */
1449 if (pci_msi_blacklisted())
1452 /* MSI-X capability present? */
1453 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1456 /* Make sure the appropriate BARs are mapped. */
1457 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1458 cfg->msix.msix_table_bar);
1459 if (rle == NULL || rle->res == NULL ||
1460 !(rman_get_flags(rle->res) & RF_ACTIVE))
1462 cfg->msix.msix_table_res = rle->res;
1463 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1464 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1465 cfg->msix.msix_pba_bar);
1466 if (rle == NULL || rle->res == NULL ||
1467 !(rman_get_flags(rle->res) & RF_ACTIVE))
1470 cfg->msix.msix_pba_res = rle->res;
1473 device_printf(child,
1474 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1475 *count, cfg->msix.msix_msgnum);
1476 max = min(*count, cfg->msix.msix_msgnum);
1477 for (i = 0; i < max; i++) {
1478 /* Allocate a message. */
1479 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1482 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1489 device_printf(child,
1490 "could not allocate any MSI-X vectors\n");
1496 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1498 device_printf(child, "using IRQ %lu for MSI-X\n",
1504 * Be fancy and try to print contiguous runs of
1505 * IRQ values as ranges. 'irq' is the previous IRQ.
1506 * 'run' is true if we are in a range.
1508 device_printf(child, "using IRQs %lu", rle->start);
1511 for (i = 1; i < actual; i++) {
1512 rle = resource_list_find(&dinfo->resources,
1513 SYS_RES_IRQ, i + 1);
1515 /* Still in a run? */
1516 if (rle->start == irq + 1) {
1522 /* Finish previous range. */
1524 kprintf("-%d", irq);
1528 /* Start new range. */
1529 kprintf(",%lu", rle->start);
1533 /* Unfinished range? */
1535 kprintf("-%d", irq);
1536 kprintf(" for MSI-X\n");
1540 /* Mask all vectors. */
1541 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1542 pci_mask_msix(child, i);
1544 /* Allocate and initialize vector data and virtual table. */
1545 cfg->msix.msix_vectors = kmalloc(sizeof(struct msix_vector) * actual,
1546 M_DEVBUF, M_WAITOK | M_ZERO);
1547 cfg->msix.msix_table = kmalloc(sizeof(struct msix_table_entry) * actual,
1548 M_DEVBUF, M_WAITOK | M_ZERO);
1549 for (i = 0; i < actual; i++) {
1550 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1551 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1552 cfg->msix.msix_table[i].mte_vector = i + 1;
1555 /* Update control register to enable MSI-X. */
1556 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1557 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1558 cfg->msix.msix_ctrl, 2);
1560 /* Update counts of alloc'd messages. */
1561 cfg->msix.msix_alloc = actual;
1562 cfg->msix.msix_table_len = actual;
1568 * By default, pci_alloc_msix() will assign the allocated IRQ
1569 * resources consecutively to the first N messages in the MSI-X table.
1570 * However, device drivers may want to use different layouts if they
1571 * either receive fewer messages than they asked for, or they wish to
1572 * populate the MSI-X table sparsely. This method allows the driver
1573 * to specify what layout it wants. It must be called after a
1574 * successful pci_alloc_msix() but before any of the associated
1575 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1577 * The 'vectors' array contains 'count' message vectors. The array
1578 * maps directly to the MSI-X table in that index 0 in the array
1579 * specifies the vector for the first message in the MSI-X table, etc.
1580 * The vector value in each array index can either be 0 to indicate
1581 * that no vector should be assigned to a message slot, or it can be a
1582 * number from 1 to N (where N is the count returned from a
1583 * succcessful call to pci_alloc_msix()) to indicate which message
1584 * vector (IRQ) to be used for the corresponding message.
1586 * On successful return, each message with a non-zero vector will have
1587 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1588 * 1. Additionally, if any of the IRQs allocated via the previous
1589 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1590 * will be kfreed back to the system automatically.
1592 * For example, suppose a driver has a MSI-X table with 6 messages and
1593 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1594 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1595 * C. After the call to pci_alloc_msix(), the device will be setup to
1596 * have an MSI-X table of ABC--- (where - means no vector assigned).
1597 * If the driver ten passes a vector array of { 1, 0, 1, 2, 0, 2 },
1598 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1599 * be kfreed back to the system. This device will also have valid
1600 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1602 * In any case, the SYS_RES_IRQ rid X will always map to the message
1603 * at MSI-X table index X - 1 and will only be valid if a vector is
1604 * assigned to that table entry.
1607 pci_remap_msix_method(device_t dev, device_t child, int count,
1608 const u_int *vectors)
1610 struct pci_devinfo *dinfo = device_get_ivars(child);
1611 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1612 struct resource_list_entry *rle;
1613 int i, irq, j, *used;
1616 * Have to have at least one message in the table but the
1617 * table can't be bigger than the actual MSI-X table in the
1620 if (count == 0 || count > msix->msix_msgnum)
1623 /* Sanity check the vectors. */
1624 for (i = 0; i < count; i++)
1625 if (vectors[i] > msix->msix_alloc)
1629 * Make sure there aren't any holes in the vectors to be used.
1630 * It's a big pain to support it, and it doesn't really make
1631 * sense anyway. Also, at least one vector must be used.
1633 used = kmalloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1635 for (i = 0; i < count; i++)
1636 if (vectors[i] != 0)
1637 used[vectors[i] - 1] = 1;
1638 for (i = 0; i < msix->msix_alloc - 1; i++)
1639 if (used[i] == 0 && used[i + 1] == 1) {
1640 kfree(used, M_DEVBUF);
1644 kfree(used, M_DEVBUF);
1648 /* Make sure none of the resources are allocated. */
1649 for (i = 0; i < msix->msix_table_len; i++) {
1650 if (msix->msix_table[i].mte_vector == 0)
1652 if (msix->msix_table[i].mte_handlers > 0)
1654 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1655 KASSERT(rle != NULL, ("missing resource"));
1656 if (rle->res != NULL)
1660 /* Free the existing resource list entries. */
1661 for (i = 0; i < msix->msix_table_len; i++) {
1662 if (msix->msix_table[i].mte_vector == 0)
1664 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1668 * Build the new virtual table keeping track of which vectors are
1671 kfree(msix->msix_table, M_DEVBUF);
1672 msix->msix_table = kmalloc(sizeof(struct msix_table_entry) * count,
1673 M_DEVBUF, M_WAITOK | M_ZERO);
1674 for (i = 0; i < count; i++)
1675 msix->msix_table[i].mte_vector = vectors[i];
1676 msix->msix_table_len = count;
1678 /* Free any unused IRQs and resize the vectors array if necessary. */
1679 j = msix->msix_alloc - 1;
1681 struct msix_vector *vec;
1683 while (used[j] == 0) {
1684 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1685 msix->msix_vectors[j].mv_irq);
1688 vec = kmalloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
1690 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1692 kfree(msix->msix_vectors, M_DEVBUF);
1693 msix->msix_vectors = vec;
1694 msix->msix_alloc = j + 1;
1696 kfree(used, M_DEVBUF);
1698 /* Map the IRQs onto the rids. */
1699 for (i = 0; i < count; i++) {
1700 if (vectors[i] == 0)
1702 irq = msix->msix_vectors[vectors[i]].mv_irq;
1703 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1708 device_printf(child, "Remapped MSI-X IRQs as: ");
1709 for (i = 0; i < count; i++) {
1712 if (vectors[i] == 0)
1716 msix->msix_vectors[vectors[i]].mv_irq);
1725 pci_release_msix(device_t dev, device_t child)
1727 struct pci_devinfo *dinfo = device_get_ivars(child);
1728 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1729 struct resource_list_entry *rle;
1732 /* Do we have any messages to release? */
1733 if (msix->msix_alloc == 0)
1736 /* Make sure none of the resources are allocated. */
1737 for (i = 0; i < msix->msix_table_len; i++) {
1738 if (msix->msix_table[i].mte_vector == 0)
1740 if (msix->msix_table[i].mte_handlers > 0)
1742 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1743 KASSERT(rle != NULL, ("missing resource"));
1744 if (rle->res != NULL)
1748 /* Update control register to disable MSI-X. */
1749 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1750 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1751 msix->msix_ctrl, 2);
1753 /* Free the resource list entries. */
1754 for (i = 0; i < msix->msix_table_len; i++) {
1755 if (msix->msix_table[i].mte_vector == 0)
1757 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1759 kfree(msix->msix_table, M_DEVBUF);
1760 msix->msix_table_len = 0;
1762 /* Release the IRQs. */
1763 for (i = 0; i < msix->msix_alloc; i++)
1764 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1765 msix->msix_vectors[i].mv_irq);
1766 kfree(msix->msix_vectors, M_DEVBUF);
1767 msix->msix_alloc = 0;
1772 * Return the max supported MSI-X messages this device supports.
1773 * Basically, assuming the MD code can alloc messages, this function
1774 * should return the maximum value that pci_alloc_msix() can return.
1775 * Thus, it is subject to the tunables, etc.
1778 pci_msix_count_method(device_t dev, device_t child)
1780 struct pci_devinfo *dinfo = device_get_ivars(child);
1781 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1783 if (pci_do_msix && msix->msix_location != 0)
1784 return (msix->msix_msgnum);
1789 * HyperTransport MSI mapping control
1792 pci_ht_map_msi(device_t dev, uint64_t addr)
1794 struct pci_devinfo *dinfo = device_get_ivars(dev);
1795 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1800 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1801 ht->ht_msiaddr >> 20 == addr >> 20) {
1802 /* Enable MSI -> HT mapping. */
1803 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1804 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1808 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
1809 /* Disable MSI -> HT mapping. */
1810 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1811 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1817 * Support for MSI message signalled interrupts.
1820 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1822 struct pci_devinfo *dinfo = device_get_ivars(dev);
1823 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1825 /* Write data and address values. */
1826 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1827 address & 0xffffffff, 4);
1828 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1829 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1831 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1834 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1837 /* Enable MSI in the control register. */
1838 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1839 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1842 /* Enable MSI -> HT mapping. */
1843 pci_ht_map_msi(dev, address);
1847 pci_disable_msi(device_t dev)
1849 struct pci_devinfo *dinfo = device_get_ivars(dev);
1850 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1852 /* Disable MSI -> HT mapping. */
1853 pci_ht_map_msi(dev, 0);
1855 /* Disable MSI in the control register. */
1856 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1857 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1862 * Restore MSI registers during resume. If MSI is enabled then
1863 * restore the data and address registers in addition to the control
1867 pci_resume_msi(device_t dev)
1869 struct pci_devinfo *dinfo = device_get_ivars(dev);
1870 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1874 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1875 address = msi->msi_addr;
1876 data = msi->msi_data;
1877 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1878 address & 0xffffffff, 4);
1879 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1880 pci_write_config(dev, msi->msi_location +
1881 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1882 pci_write_config(dev, msi->msi_location +
1883 PCIR_MSI_DATA_64BIT, data, 2);
1885 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1888 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1893 pci_remap_msi_irq(device_t dev, u_int irq)
1895 struct pci_devinfo *dinfo = device_get_ivars(dev);
1896 pcicfgregs *cfg = &dinfo->cfg;
1897 struct resource_list_entry *rle;
1898 struct msix_table_entry *mte;
1899 struct msix_vector *mv;
1905 bus = device_get_parent(dev);
1908 * Handle MSI first. We try to find this IRQ among our list
1909 * of MSI IRQs. If we find it, we request updated address and
1910 * data registers and apply the results.
1912 if (cfg->msi.msi_alloc > 0) {
1914 /* If we don't have any active handlers, nothing to do. */
1915 if (cfg->msi.msi_handlers == 0)
1917 for (i = 0; i < cfg->msi.msi_alloc; i++) {
1918 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
1920 if (rle->start == irq) {
1921 error = PCIB_MAP_MSI(device_get_parent(bus),
1922 dev, irq, &addr, &data);
1925 pci_disable_msi(dev);
1926 dinfo->cfg.msi.msi_addr = addr;
1927 dinfo->cfg.msi.msi_data = data;
1928 pci_enable_msi(dev, addr, data);
1936 * For MSI-X, we check to see if we have this IRQ. If we do,
1937 * we request the updated mapping info. If that works, we go
1938 * through all the slots that use this IRQ and update them.
1940 if (cfg->msix.msix_alloc > 0) {
1941 for (i = 0; i < cfg->msix.msix_alloc; i++) {
1942 mv = &cfg->msix.msix_vectors[i];
1943 if (mv->mv_irq == irq) {
1944 error = PCIB_MAP_MSI(device_get_parent(bus),
1945 dev, irq, &addr, &data);
1948 mv->mv_address = addr;
1950 for (j = 0; j < cfg->msix.msix_table_len; j++) {
1951 mte = &cfg->msix.msix_table[j];
1952 if (mte->mte_vector != i + 1)
1954 if (mte->mte_handlers == 0)
1956 pci_mask_msix(dev, j);
1957 pci_enable_msix(dev, j, addr, data);
1958 pci_unmask_msix(dev, j);
1969 * Returns true if the specified device is blacklisted because MSI
1973 pci_msi_device_blacklisted(device_t dev)
1975 struct pci_quirk *q;
1977 if (!pci_honor_msi_blacklist)
1980 for (q = &pci_quirks[0]; q->devid; q++) {
1981 if (q->devid == pci_get_devid(dev) &&
1982 q->type == PCI_QUIRK_DISABLE_MSI)
1989 * Determine if MSI is blacklisted globally on this sytem. Currently,
1990 * we just check for blacklisted chipsets as represented by the
1991 * host-PCI bridge at device 0:0:0. In the future, it may become
1992 * necessary to check other system attributes, such as the kenv values
1993 * that give the motherboard manufacturer and model number.
1996 pci_msi_blacklisted(void)
2000 if (!pci_honor_msi_blacklist)
2003 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
2004 if (!(pcie_chipset || pcix_chipset))
2007 dev = pci_find_bsf(0, 0, 0);
2009 return (pci_msi_device_blacklisted(dev));
2014 * Attempt to allocate *count MSI messages. The actual number allocated is
2015 * returned in *count. After this function returns, each message will be
2016 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
2019 pci_alloc_msi_method(device_t dev, device_t child, int *count)
2021 struct pci_devinfo *dinfo = device_get_ivars(child);
2022 pcicfgregs *cfg = &dinfo->cfg;
2023 struct resource_list_entry *rle;
2024 int actual, error, i, irqs[32];
2027 /* Don't let count == 0 get us into trouble. */
2031 /* If rid 0 is allocated, then fail. */
2032 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
2033 if (rle != NULL && rle->res != NULL)
2036 /* Already have allocated messages? */
2037 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
2040 /* If MSI is blacklisted for this system, fail. */
2041 if (pci_msi_blacklisted())
2044 /* MSI capability present? */
2045 if (cfg->msi.msi_location == 0 || !pci_do_msi)
2049 device_printf(child,
2050 "attempting to allocate %d MSI vectors (%d supported)\n",
2051 *count, cfg->msi.msi_msgnum);
2053 /* Don't ask for more than the device supports. */
2054 actual = min(*count, cfg->msi.msi_msgnum);
2056 /* Don't ask for more than 32 messages. */
2057 actual = min(actual, 32);
2059 /* MSI requires power of 2 number of messages. */
2060 if (!powerof2(actual))
2064 /* Try to allocate N messages. */
2065 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
2066 cfg->msi.msi_msgnum, irqs);
2077 * We now have N actual messages mapped onto SYS_RES_IRQ
2078 * resources in the irqs[] array, so add new resources
2079 * starting at rid 1.
2081 for (i = 0; i < actual; i++)
2082 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
2083 irqs[i], irqs[i], 1);
2087 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
2092 * Be fancy and try to print contiguous runs
2093 * of IRQ values as ranges. 'run' is true if
2094 * we are in a range.
2096 device_printf(child, "using IRQs %d", irqs[0]);
2098 for (i = 1; i < actual; i++) {
2100 /* Still in a run? */
2101 if (irqs[i] == irqs[i - 1] + 1) {
2106 /* Finish previous range. */
2108 kprintf("-%d", irqs[i - 1]);
2112 /* Start new range. */
2113 kprintf(",%d", irqs[i]);
2116 /* Unfinished range? */
2118 kprintf("-%d", irqs[actual - 1]);
2119 kprintf(" for MSI\n");
2123 /* Update control register with actual count. */
2124 ctrl = cfg->msi.msi_ctrl;
2125 ctrl &= ~PCIM_MSICTRL_MME_MASK;
2126 ctrl |= (ffs(actual) - 1) << 4;
2127 cfg->msi.msi_ctrl = ctrl;
2128 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2130 /* Update counts of alloc'd messages. */
2131 cfg->msi.msi_alloc = actual;
2132 cfg->msi.msi_handlers = 0;
2137 /* Release the MSI messages associated with this device. */
2139 pci_release_msi_method(device_t dev, device_t child)
2141 struct pci_devinfo *dinfo = device_get_ivars(child);
2142 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2143 struct resource_list_entry *rle;
2144 int error, i, irqs[32];
2146 /* Try MSI-X first. */
2147 error = pci_release_msix(dev, child);
2148 if (error != ENODEV)
2151 /* Do we have any messages to release? */
2152 if (msi->msi_alloc == 0)
2154 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2156 /* Make sure none of the resources are allocated. */
2157 if (msi->msi_handlers > 0)
2159 for (i = 0; i < msi->msi_alloc; i++) {
2160 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2161 KASSERT(rle != NULL, ("missing MSI resource"));
2162 if (rle->res != NULL)
2164 irqs[i] = rle->start;
2167 /* Update control register with 0 count. */
2168 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2169 ("%s: MSI still enabled", __func__));
2170 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2171 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2174 /* Release the messages. */
2175 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
2176 for (i = 0; i < msi->msi_alloc; i++)
2177 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2179 /* Update alloc count. */
2187 * Return the max supported MSI messages this device supports.
2188 * Basically, assuming the MD code can alloc messages, this function
2189 * should return the maximum value that pci_alloc_msi() can return.
2190 * Thus, it is subject to the tunables, etc.
2193 pci_msi_count_method(device_t dev, device_t child)
2195 struct pci_devinfo *dinfo = device_get_ivars(child);
2196 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2198 if (pci_do_msi && msi->msi_location != 0)
2199 return (msi->msi_msgnum);
2203 /* kfree pcicfgregs structure and all depending data structures */
2206 pci_freecfg(struct pci_devinfo *dinfo)
2208 struct devlist *devlist_head;
2211 devlist_head = &pci_devq;
2213 if (dinfo->cfg.vpd.vpd_reg) {
2214 kfree(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2215 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2216 kfree(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2217 kfree(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2218 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2219 kfree(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2220 kfree(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2222 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2223 kfree(dinfo, M_DEVBUF);
2225 /* increment the generation count */
2228 /* we're losing one device */
2234 * PCI power manangement
2237 pci_set_powerstate_method(device_t dev, device_t child, int state)
2239 struct pci_devinfo *dinfo = device_get_ivars(child);
2240 pcicfgregs *cfg = &dinfo->cfg;
2242 int result, oldstate, highest, delay;
2244 if (cfg->pp.pp_cap == 0)
2245 return (EOPNOTSUPP);
2248 * Optimize a no state change request away. While it would be OK to
2249 * write to the hardware in theory, some devices have shown odd
2250 * behavior when going from D3 -> D3.
2252 oldstate = pci_get_powerstate(child);
2253 if (oldstate == state)
2257 * The PCI power management specification states that after a state
2258 * transition between PCI power states, system software must
2259 * guarantee a minimal delay before the function accesses the device.
2260 * Compute the worst case delay that we need to guarantee before we
2261 * access the device. Many devices will be responsive much more
2262 * quickly than this delay, but there are some that don't respond
2263 * instantly to state changes. Transitions to/from D3 state require
2264 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2265 * is done below with DELAY rather than a sleeper function because
2266 * this function can be called from contexts where we cannot sleep.
2268 highest = (oldstate > state) ? oldstate : state;
2269 if (highest == PCI_POWERSTATE_D3)
2271 else if (highest == PCI_POWERSTATE_D2)
2275 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2276 & ~PCIM_PSTAT_DMASK;
2279 case PCI_POWERSTATE_D0:
2280 status |= PCIM_PSTAT_D0;
2282 case PCI_POWERSTATE_D1:
2283 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2284 return (EOPNOTSUPP);
2285 status |= PCIM_PSTAT_D1;
2287 case PCI_POWERSTATE_D2:
2288 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2289 return (EOPNOTSUPP);
2290 status |= PCIM_PSTAT_D2;
2292 case PCI_POWERSTATE_D3:
2293 status |= PCIM_PSTAT_D3;
2301 "pci%d:%d:%d:%d: Transition from D%d to D%d\n",
2302 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2303 dinfo->cfg.func, oldstate, state);
2305 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2312 pci_get_powerstate_method(device_t dev, device_t child)
2314 struct pci_devinfo *dinfo = device_get_ivars(child);
2315 pcicfgregs *cfg = &dinfo->cfg;
2319 if (cfg->pp.pp_cap != 0) {
2320 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2321 switch (status & PCIM_PSTAT_DMASK) {
2323 result = PCI_POWERSTATE_D0;
2326 result = PCI_POWERSTATE_D1;
2329 result = PCI_POWERSTATE_D2;
2332 result = PCI_POWERSTATE_D3;
2335 result = PCI_POWERSTATE_UNKNOWN;
2339 /* No support, device is always at D0 */
2340 result = PCI_POWERSTATE_D0;
2346 * Some convenience functions for PCI device drivers.
2349 static __inline void
2350 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2354 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2356 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2359 static __inline void
2360 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2364 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2366 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2370 pci_enable_busmaster_method(device_t dev, device_t child)
2372 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2377 pci_disable_busmaster_method(device_t dev, device_t child)
2379 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2384 pci_enable_io_method(device_t dev, device_t child, int space)
2394 case SYS_RES_IOPORT:
2395 bit = PCIM_CMD_PORTEN;
2398 case SYS_RES_MEMORY:
2399 bit = PCIM_CMD_MEMEN;
2405 pci_set_command_bit(dev, child, bit);
2406 /* Some devices seem to need a brief stall here, what do to? */
2407 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2410 device_printf(child, "failed to enable %s mapping!\n", error);
2415 pci_disable_io_method(device_t dev, device_t child, int space)
2425 case SYS_RES_IOPORT:
2426 bit = PCIM_CMD_PORTEN;
2429 case SYS_RES_MEMORY:
2430 bit = PCIM_CMD_MEMEN;
2436 pci_clear_command_bit(dev, child, bit);
2437 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2438 if (command & bit) {
2439 device_printf(child, "failed to disable %s mapping!\n", error);
2446 * New style pci driver. Parent device is either a pci-host-bridge or a
2447 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2451 pci_print_verbose(struct pci_devinfo *dinfo)
2455 pcicfgregs *cfg = &dinfo->cfg;
2457 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2458 cfg->vendor, cfg->device, cfg->revid);
2459 kprintf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2460 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2461 kprintf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2462 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2464 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2465 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2466 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2467 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2468 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2469 if (cfg->intpin > 0)
2470 kprintf("\tintpin=%c, irq=%d\n",
2471 cfg->intpin +'a' -1, cfg->intline);
2472 if (cfg->pp.pp_cap) {
2475 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2476 kprintf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2477 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2478 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2479 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2480 status & PCIM_PSTAT_DMASK);
2482 if (cfg->msi.msi_location) {
2485 ctrl = cfg->msi.msi_ctrl;
2486 kprintf("\tMSI supports %d message%s%s%s\n",
2487 cfg->msi.msi_msgnum,
2488 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2489 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2490 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2492 if (cfg->msix.msix_location) {
2493 kprintf("\tMSI-X supports %d message%s ",
2494 cfg->msix.msix_msgnum,
2495 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2496 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2497 kprintf("in map 0x%x\n",
2498 cfg->msix.msix_table_bar);
2500 kprintf("in maps 0x%x and 0x%x\n",
2501 cfg->msix.msix_table_bar,
2502 cfg->msix.msix_pba_bar);
2504 pci_print_verbose_expr(cfg);
2509 pci_print_verbose_expr(const pcicfgregs *cfg)
2511 const struct pcicfg_expr *expr = &cfg->expr;
2512 const char *port_name;
2518 if (expr->expr_ptr == 0) /* No PCI Express capability */
2521 kprintf("\tPCI Express ver.%d cap=0x%04x",
2522 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap);
2523 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
2526 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
2528 switch (port_type) {
2529 case PCIE_END_POINT:
2530 port_name = "DEVICE";
2532 case PCIE_LEG_END_POINT:
2533 port_name = "LEGDEV";
2535 case PCIE_ROOT_PORT:
2538 case PCIE_UP_STREAM_PORT:
2539 port_name = "UPSTREAM";
2541 case PCIE_DOWN_STREAM_PORT:
2542 port_name = "DOWNSTRM";
2544 case PCIE_PCIE2PCI_BRIDGE:
2545 port_name = "PCIE2PCI";
2547 case PCIE_PCI2PCIE_BRIDGE:
2548 port_name = "PCI2PCIE";
2554 if ((port_type == PCIE_ROOT_PORT ||
2555 port_type == PCIE_DOWN_STREAM_PORT) &&
2556 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
2558 if (port_name != NULL)
2559 kprintf("[%s]", port_name);
2561 if (pcie_slotimpl(cfg)) {
2562 kprintf(", slotcap=0x%08x", expr->expr_slotcap);
2563 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP)
2564 kprintf("[HOTPLUG]");
2571 pci_porten(device_t pcib, int b, int s, int f)
2573 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2574 & PCIM_CMD_PORTEN) != 0;
2578 pci_memen(device_t pcib, int b, int s, int f)
2580 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2581 & PCIM_CMD_MEMEN) != 0;
2585 * Add a resource based on a pci map register. Return 1 if the map
2586 * register is a 32bit map register or 2 if it is a 64bit register.
2589 pci_add_map(device_t pcib, device_t bus, device_t dev,
2590 int b, int s, int f, int reg, struct resource_list *rl, int force,
2595 pci_addr_t start, end, count;
2602 struct resource *res;
2604 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2605 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
2606 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2607 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
2609 if (PCI_BAR_MEM(map)) {
2610 type = SYS_RES_MEMORY;
2611 if (map & PCIM_BAR_MEM_PREFETCH)
2614 type = SYS_RES_IOPORT;
2615 ln2size = pci_mapsize(testval);
2616 ln2range = pci_maprange(testval);
2617 base = pci_mapbase(map);
2618 barlen = ln2range == 64 ? 2 : 1;
2621 * For I/O registers, if bottom bit is set, and the next bit up
2622 * isn't clear, we know we have a BAR that doesn't conform to the
2623 * spec, so ignore it. Also, sanity check the size of the data
2624 * areas to the type of memory involved. Memory must be at least
2625 * 16 bytes in size, while I/O ranges must be at least 4.
2627 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2629 if ((type == SYS_RES_MEMORY && ln2size < 4) ||
2630 (type == SYS_RES_IOPORT && ln2size < 2))
2634 /* Read the other half of a 64bit map register */
2635 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
2637 kprintf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2638 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
2639 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2640 kprintf(", port disabled\n");
2641 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2642 kprintf(", memory disabled\n");
2644 kprintf(", enabled\n");
2648 * If base is 0, then we have problems. It is best to ignore
2649 * such entries for the moment. These will be allocated later if
2650 * the driver specifically requests them. However, some
2651 * removable busses look better when all resources are allocated,
2652 * so allow '0' to be overriden.
2654 * Similarly treat maps whose values is the same as the test value
2655 * read back. These maps have had all f's written to them by the
2656 * BIOS in an attempt to disable the resources.
2658 if (!force && (base == 0 || map == testval))
2660 if ((u_long)base != base) {
2662 "pci%d:%d:%d:%d bar %#x too many address bits",
2663 pci_get_domain(dev), b, s, f, reg);
2668 * This code theoretically does the right thing, but has
2669 * undesirable side effects in some cases where peripherals
2670 * respond oddly to having these bits enabled. Let the user
2671 * be able to turn them off (since pci_enable_io_modes is 1 by
2674 if (pci_enable_io_modes) {
2675 /* Turn on resources that have been left off by a lazy BIOS */
2676 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
2677 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2678 cmd |= PCIM_CMD_PORTEN;
2679 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2681 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
2682 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2683 cmd |= PCIM_CMD_MEMEN;
2684 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2687 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2689 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2693 count = 1 << ln2size;
2694 if (base == 0 || base == pci_mapbase(testval)) {
2695 start = 0; /* Let the parent decide. */
2699 end = base + (1 << ln2size) - 1;
2701 resource_list_add(rl, type, reg, start, end, count);
2704 * Try to allocate the resource for this BAR from our parent
2705 * so that this resource range is already reserved. The
2706 * driver for this device will later inherit this resource in
2707 * pci_alloc_resource().
2709 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
2710 prefetch ? RF_PREFETCHABLE : 0);
2713 * If the allocation fails, delete the resource list
2714 * entry to force pci_alloc_resource() to allocate
2715 * resources from the parent.
2717 resource_list_delete(rl, type, reg);
2718 #ifdef PCI_BAR_CLEAR
2721 #else /* !PCI_BAR_CLEAR */
2723 * Don't clear BAR here. Some BIOS lists HPET as a
2724 * PCI function, clearing the BAR causes HPET timer
2728 kprintf("pci:%d:%d:%d: resource reservation failed "
2729 "%#jx - %#jx\n", b, s, f,
2730 (intmax_t)start, (intmax_t)end);
2733 #endif /* PCI_BAR_CLEAR */
2735 start = rman_get_start(res);
2737 pci_write_config(dev, reg, start, 4);
2739 pci_write_config(dev, reg + 4, start >> 32, 4);
2744 * For ATA devices we need to decide early what addressing mode to use.
2745 * Legacy demands that the primary and secondary ATA ports sits on the
2746 * same addresses that old ISA hardware did. This dictates that we use
2747 * those addresses and ignore the BAR's if we cannot set PCI native
2751 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
2752 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask)
2754 int rid, type, progif;
2756 /* if this device supports PCI native addressing use it */
2757 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2758 if ((progif & 0x8a) == 0x8a) {
2759 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2760 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2761 kprintf("Trying ATA native PCI addressing mode\n");
2762 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2766 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2767 type = SYS_RES_IOPORT;
2768 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2769 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force,
2770 prefetchmask & (1 << 0));
2771 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force,
2772 prefetchmask & (1 << 1));
2775 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
2776 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
2779 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
2780 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
2783 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2784 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force,
2785 prefetchmask & (1 << 2));
2786 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force,
2787 prefetchmask & (1 << 3));
2790 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
2791 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
2794 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
2795 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
2798 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force,
2799 prefetchmask & (1 << 4));
2800 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force,
2801 prefetchmask & (1 << 5));
2805 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2807 struct pci_devinfo *dinfo = device_get_ivars(dev);
2808 pcicfgregs *cfg = &dinfo->cfg;
2809 char tunable_name[64];
2812 /* Has to have an intpin to have an interrupt. */
2813 if (cfg->intpin == 0)
2816 /* Let the user override the IRQ with a tunable. */
2817 irq = PCI_INVALID_IRQ;
2818 ksnprintf(tunable_name, sizeof(tunable_name),
2819 "hw.pci%d.%d.%d.INT%c.irq",
2820 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2821 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2822 irq = PCI_INVALID_IRQ;
2825 * If we didn't get an IRQ via the tunable, then we either use the
2826 * IRQ value in the intline register or we ask the bus to route an
2827 * interrupt for us. If force_route is true, then we only use the
2828 * value in the intline register if the bus was unable to assign an
2831 if (!PCI_INTERRUPT_VALID(irq)) {
2832 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2833 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2834 if (!PCI_INTERRUPT_VALID(irq))
2838 /* If after all that we don't have an IRQ, just bail. */
2839 if (!PCI_INTERRUPT_VALID(irq))
2842 /* Update the config register if it changed. */
2843 if (irq != cfg->intline) {
2845 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2848 /* Add this IRQ as rid 0 interrupt resource. */
2849 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
2853 pci_add_resources(device_t pcib, device_t bus, device_t dev, int force, uint32_t prefetchmask)
2855 struct pci_devinfo *dinfo = device_get_ivars(dev);
2856 pcicfgregs *cfg = &dinfo->cfg;
2857 struct resource_list *rl = &dinfo->resources;
2858 struct pci_quirk *q;
2865 /* ATA devices needs special map treatment */
2866 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2867 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
2868 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2869 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2870 !pci_read_config(dev, PCIR_BAR(2), 4))) )
2871 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask);
2873 for (i = 0; i < cfg->nummaps;)
2874 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
2875 rl, force, prefetchmask & (1 << i));
2878 * Add additional, quirked resources.
2880 for (q = &pci_quirks[0]; q->devid; q++) {
2881 if (q->devid == ((cfg->device << 16) | cfg->vendor)
2882 && q->type == PCI_QUIRK_MAP_REG)
2883 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl,
2887 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2889 * Try to re-route interrupts. Sometimes the BIOS or
2890 * firmware may leave bogus values in these registers.
2891 * If the re-route fails, then just stick with what we
2894 pci_assign_interrupt(bus, dev, 1);
2899 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
2901 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
2902 device_t pcib = device_get_parent(dev);
2903 struct pci_devinfo *dinfo;
2905 int s, f, pcifunchigh;
2908 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2909 ("dinfo_size too small"));
2910 maxslots = PCIB_MAXSLOTS(pcib);
2911 for (s = 0; s <= maxslots; s++) {
2915 hdrtype = REG(PCIR_HDRTYPE, 1);
2916 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2918 if (hdrtype & PCIM_MFDEV)
2919 pcifunchigh = PCI_FUNCMAX;
2920 for (f = 0; f <= pcifunchigh; f++) {
2921 dinfo = pci_read_device(pcib, domain, busno, s, f,
2923 if (dinfo != NULL) {
2924 pci_add_child(dev, dinfo);
2932 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2936 pcib = device_get_parent(bus);
2937 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2938 device_set_ivars(dinfo->cfg.dev, dinfo);
2939 resource_list_init(&dinfo->resources);
2940 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2941 pci_cfg_restore(dinfo->cfg.dev, dinfo);
2942 pci_print_verbose(dinfo);
2943 pci_add_resources(pcib, bus, dinfo->cfg.dev, 0, 0);
2947 pci_probe(device_t dev)
2949 device_set_desc(dev, "PCI bus");
2951 /* Allow other subclasses to override this driver. */
2956 pci_attach(device_t dev)
2961 * Since there can be multiple independantly numbered PCI
2962 * busses on systems with multiple PCI domains, we can't use
2963 * the unit number to decide which bus we are probing. We ask
2964 * the parent pcib what our domain and bus numbers are.
2966 domain = pcib_get_domain(dev);
2967 busno = pcib_get_bus(dev);
2969 device_printf(dev, "domain=%d, physical bus=%d\n",
2972 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
2974 return (bus_generic_attach(dev));
2978 pci_suspend(device_t dev)
2980 int dstate, error, i, numdevs;
2981 device_t acpi_dev, child, *devlist;
2982 struct pci_devinfo *dinfo;
2985 * Save the PCI configuration space for each child and set the
2986 * device in the appropriate power state for this sleep state.
2989 if (pci_do_power_resume)
2990 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2991 device_get_children(dev, &devlist, &numdevs);
2992 for (i = 0; i < numdevs; i++) {
2994 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2995 pci_cfg_save(child, dinfo, 0);
2998 /* Suspend devices before potentially powering them down. */
2999 error = bus_generic_suspend(dev);
3001 kfree(devlist, M_TEMP);
3006 * Always set the device to D3. If ACPI suggests a different
3007 * power state, use it instead. If ACPI is not present, the
3008 * firmware is responsible for managing device power. Skip
3009 * children who aren't attached since they are powered down
3010 * separately. Only manage type 0 devices for now.
3012 for (i = 0; acpi_dev && i < numdevs; i++) {
3014 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3015 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
3016 dstate = PCI_POWERSTATE_D3;
3017 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
3018 pci_set_powerstate(child, dstate);
3021 kfree(devlist, M_TEMP);
3026 pci_resume(device_t dev)
3029 device_t acpi_dev, child, *devlist;
3030 struct pci_devinfo *dinfo;
3033 * Set each child to D0 and restore its PCI configuration space.
3036 if (pci_do_power_resume)
3037 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
3038 device_get_children(dev, &devlist, &numdevs);
3039 for (i = 0; i < numdevs; i++) {
3041 * Notify ACPI we're going to D0 but ignore the result. If
3042 * ACPI is not present, the firmware is responsible for
3043 * managing device power. Only manage type 0 devices for now.
3046 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3047 if (acpi_dev && device_is_attached(child) &&
3048 dinfo->cfg.hdrtype == 0) {
3049 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
3050 pci_set_powerstate(child, PCI_POWERSTATE_D0);
3053 /* Now the device is powered up, restore its config space. */
3054 pci_cfg_restore(child, dinfo);
3056 kfree(devlist, M_TEMP);
3057 return (bus_generic_resume(dev));
3061 pci_load_vendor_data(void)
3063 caddr_t vendordata, info;
3065 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
3066 info = preload_search_info(vendordata, MODINFO_ADDR);
3067 pci_vendordata = *(char **)info;
3068 info = preload_search_info(vendordata, MODINFO_SIZE);
3069 pci_vendordata_size = *(size_t *)info;
3070 /* terminate the database */
3071 pci_vendordata[pci_vendordata_size] = '\n';
3076 pci_driver_added(device_t dev, driver_t *driver)
3081 struct pci_devinfo *dinfo;
3085 device_printf(dev, "driver added\n");
3086 DEVICE_IDENTIFY(driver, dev);
3087 device_get_children(dev, &devlist, &numdevs);
3088 for (i = 0; i < numdevs; i++) {
3090 if (device_get_state(child) != DS_NOTPRESENT)
3092 dinfo = device_get_ivars(child);
3093 pci_print_verbose(dinfo);
3095 kprintf("pci%d:%d:%d:%d: reprobing on driver added\n",
3096 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
3098 pci_cfg_restore(child, dinfo);
3099 if (device_probe_and_attach(child) != 0)
3100 pci_cfg_save(child, dinfo, 1);
3102 kfree(devlist, M_TEMP);
3106 pci_child_detached(device_t parent __unused, device_t child)
3108 /* Turn child's power off */
3109 pci_cfg_save(child, device_get_ivars(child), 1);
3113 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
3114 driver_intr_t *intr, void *arg, void **cookiep, lwkt_serialize_t serializer)
3117 struct pci_devinfo *dinfo;
3118 struct msix_table_entry *mte;
3119 struct msix_vector *mv;
3126 error = bus_generic_setup_intr(dev, child, irq, flags, intr,
3127 arg, &cookie, serializer);
3131 /* If this is not a direct child, just bail out. */
3132 if (device_get_parent(child) != dev) {
3137 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3139 rid = rman_get_rid(irq);
3141 /* Make sure that INTx is enabled */
3142 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3145 * Check to see if the interrupt is MSI or MSI-X.
3146 * Ask our parent to map the MSI and give
3147 * us the address and data register values.
3148 * If we fail for some reason, teardown the
3149 * interrupt handler.
3151 dinfo = device_get_ivars(child);
3152 if (dinfo->cfg.msi.msi_alloc > 0) {
3153 if (dinfo->cfg.msi.msi_addr == 0) {
3154 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
3155 ("MSI has handlers, but vectors not mapped"));
3156 error = PCIB_MAP_MSI(device_get_parent(dev),
3157 child, rman_get_start(irq), &addr, &data);
3160 dinfo->cfg.msi.msi_addr = addr;
3161 dinfo->cfg.msi.msi_data = data;
3162 pci_enable_msi(child, addr, data);
3164 dinfo->cfg.msi.msi_handlers++;
3166 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3167 ("No MSI or MSI-X interrupts allocated"));
3168 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3169 ("MSI-X index too high"));
3170 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3171 KASSERT(mte->mte_vector != 0, ("no message vector"));
3172 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
3173 KASSERT(mv->mv_irq == rman_get_start(irq),
3175 if (mv->mv_address == 0) {
3176 KASSERT(mte->mte_handlers == 0,
3177 ("MSI-X table entry has handlers, but vector not mapped"));
3178 error = PCIB_MAP_MSI(device_get_parent(dev),
3179 child, rman_get_start(irq), &addr, &data);
3182 mv->mv_address = addr;
3185 if (mte->mte_handlers == 0) {
3186 pci_enable_msix(child, rid - 1, mv->mv_address,
3188 pci_unmask_msix(child, rid - 1);
3190 mte->mte_handlers++;
3193 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3194 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3197 (void)bus_generic_teardown_intr(dev, child, irq,
3208 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3212 struct msix_table_entry *mte;
3213 struct resource_list_entry *rle;
3214 struct pci_devinfo *dinfo;
3219 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3222 /* If this isn't a direct child, just bail out */
3223 if (device_get_parent(child) != dev)
3224 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3226 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3228 rid = rman_get_rid(irq);
3231 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3234 * Check to see if the interrupt is MSI or MSI-X. If so,
3235 * decrement the appropriate handlers count and mask the
3236 * MSI-X message, or disable MSI messages if the count
3239 dinfo = device_get_ivars(child);
3240 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
3241 if (rle->res != irq)
3243 if (dinfo->cfg.msi.msi_alloc > 0) {
3244 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
3245 ("MSI-X index too high"));
3246 if (dinfo->cfg.msi.msi_handlers == 0)
3248 dinfo->cfg.msi.msi_handlers--;
3249 if (dinfo->cfg.msi.msi_handlers == 0)
3250 pci_disable_msi(child);
3252 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3253 ("No MSI or MSI-X interrupts allocated"));
3254 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3255 ("MSI-X index too high"));
3256 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3257 if (mte->mte_handlers == 0)
3259 mte->mte_handlers--;
3260 if (mte->mte_handlers == 0)
3261 pci_mask_msix(child, rid - 1);
3264 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3267 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3269 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3274 pci_print_child(device_t dev, device_t child)
3276 struct pci_devinfo *dinfo;
3277 struct resource_list *rl;
3280 dinfo = device_get_ivars(child);
3281 rl = &dinfo->resources;
3283 retval += bus_print_child_header(dev, child);
3285 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3286 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3287 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3288 if (device_get_flags(dev))
3289 retval += kprintf(" flags %#x", device_get_flags(dev));
3291 retval += kprintf(" at device %d.%d", pci_get_slot(child),
3292 pci_get_function(child));
3294 retval += bus_print_child_footer(dev, child);
3304 } pci_nomatch_tab[] = {
3305 {PCIC_OLD, -1, "old"},
3306 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3307 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3308 {PCIC_STORAGE, -1, "mass storage"},
3309 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3310 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3311 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3312 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3313 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3314 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3315 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3316 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3317 {PCIC_NETWORK, -1, "network"},
3318 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3319 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3320 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3321 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3322 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3323 {PCIC_DISPLAY, -1, "display"},
3324 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3325 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3326 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3327 {PCIC_MULTIMEDIA, -1, "multimedia"},
3328 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3329 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3330 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3331 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3332 {PCIC_MEMORY, -1, "memory"},
3333 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3334 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3335 {PCIC_BRIDGE, -1, "bridge"},
3336 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3337 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3338 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3339 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3340 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3341 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3342 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3343 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3344 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3345 {PCIC_SIMPLECOMM, -1, "simple comms"},
3346 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3347 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3348 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3349 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3350 {PCIC_BASEPERIPH, -1, "base peripheral"},
3351 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3352 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3353 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3354 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3355 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3356 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3357 {PCIC_INPUTDEV, -1, "input device"},
3358 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3359 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3360 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3361 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3362 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3363 {PCIC_DOCKING, -1, "docking station"},
3364 {PCIC_PROCESSOR, -1, "processor"},
3365 {PCIC_SERIALBUS, -1, "serial bus"},
3366 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3367 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3368 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3369 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3370 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3371 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3372 {PCIC_WIRELESS, -1, "wireless controller"},
3373 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3374 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3375 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3376 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3377 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3378 {PCIC_SATCOM, -1, "satellite communication"},
3379 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3380 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3381 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3382 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3383 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3384 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3385 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3386 {PCIC_DASP, -1, "dasp"},
3387 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3392 pci_probe_nomatch(device_t dev, device_t child)
3395 char *cp, *scp, *device;
3398 * Look for a listing for this device in a loaded device database.
3400 if ((device = pci_describe_device(child)) != NULL) {
3401 device_printf(dev, "<%s>", device);
3402 kfree(device, M_DEVBUF);
3405 * Scan the class/subclass descriptions for a general
3410 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3411 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3412 if (pci_nomatch_tab[i].subclass == -1) {
3413 cp = pci_nomatch_tab[i].desc;
3414 } else if (pci_nomatch_tab[i].subclass ==
3415 pci_get_subclass(child)) {
3416 scp = pci_nomatch_tab[i].desc;
3420 device_printf(dev, "<%s%s%s>",
3422 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3425 kprintf(" (vendor 0x%04x, dev 0x%04x) at device %d.%d",
3426 pci_get_vendor(child), pci_get_device(child),
3427 pci_get_slot(child), pci_get_function(child));
3428 if (pci_get_intpin(child) > 0) {
3431 irq = pci_get_irq(child);
3432 if (PCI_INTERRUPT_VALID(irq))
3433 kprintf(" irq %d", irq);
3437 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
3441 * Parse the PCI device database, if loaded, and return a pointer to a
3442 * description of the device.
3444 * The database is flat text formatted as follows:
3446 * Any line not in a valid format is ignored.
3447 * Lines are terminated with newline '\n' characters.
3449 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3452 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3453 * - devices cannot be listed without a corresponding VENDOR line.
3454 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3455 * another TAB, then the device name.
3459 * Assuming (ptr) points to the beginning of a line in the database,
3460 * return the vendor or device and description of the next entry.
3461 * The value of (vendor) or (device) inappropriate for the entry type
3462 * is set to -1. Returns nonzero at the end of the database.
3464 * Note that this is slightly unrobust in the face of corrupt data;
3465 * we attempt to safeguard against this by spamming the end of the
3466 * database with a newline when we initialise.
3469 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3478 left = pci_vendordata_size - (cp - pci_vendordata);
3486 ksscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3490 ksscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3493 /* skip to next line */
3494 while (*cp != '\n' && left > 0) {
3503 /* skip to next line */
3504 while (*cp != '\n' && left > 0) {
3508 if (*cp == '\n' && left > 0)
3515 pci_describe_device(device_t dev)
3518 char *desc, *vp, *dp, *line;
3520 desc = vp = dp = NULL;
3523 * If we have no vendor data, we can't do anything.
3525 if (pci_vendordata == NULL)
3529 * Scan the vendor data looking for this device
3531 line = pci_vendordata;
3532 if ((vp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3535 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3537 if (vendor == pci_get_vendor(dev))
3540 if ((dp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3543 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3551 if (device == pci_get_device(dev))
3555 ksnprintf(dp, 80, "0x%x", pci_get_device(dev));
3556 if ((desc = kmalloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3558 ksprintf(desc, "%s, %s", vp, dp);
3561 kfree(vp, M_DEVBUF);
3563 kfree(dp, M_DEVBUF);
3568 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3570 struct pci_devinfo *dinfo;
3573 dinfo = device_get_ivars(child);
3577 case PCI_IVAR_ETHADDR:
3579 * The generic accessor doesn't deal with failure, so
3580 * we set the return value, then return an error.
3582 *((uint8_t **) result) = NULL;
3584 case PCI_IVAR_SUBVENDOR:
3585 *result = cfg->subvendor;
3587 case PCI_IVAR_SUBDEVICE:
3588 *result = cfg->subdevice;
3590 case PCI_IVAR_VENDOR:
3591 *result = cfg->vendor;
3593 case PCI_IVAR_DEVICE:
3594 *result = cfg->device;
3596 case PCI_IVAR_DEVID:
3597 *result = (cfg->device << 16) | cfg->vendor;
3599 case PCI_IVAR_CLASS:
3600 *result = cfg->baseclass;
3602 case PCI_IVAR_SUBCLASS:
3603 *result = cfg->subclass;
3605 case PCI_IVAR_PROGIF:
3606 *result = cfg->progif;
3608 case PCI_IVAR_REVID:
3609 *result = cfg->revid;
3611 case PCI_IVAR_INTPIN:
3612 *result = cfg->intpin;
3615 *result = cfg->intline;
3617 case PCI_IVAR_DOMAIN:
3618 *result = cfg->domain;
3624 *result = cfg->slot;
3626 case PCI_IVAR_FUNCTION:
3627 *result = cfg->func;
3629 case PCI_IVAR_CMDREG:
3630 *result = cfg->cmdreg;
3632 case PCI_IVAR_CACHELNSZ:
3633 *result = cfg->cachelnsz;
3635 case PCI_IVAR_MINGNT:
3636 *result = cfg->mingnt;
3638 case PCI_IVAR_MAXLAT:
3639 *result = cfg->maxlat;
3641 case PCI_IVAR_LATTIMER:
3642 *result = cfg->lattimer;
3644 case PCI_IVAR_PCIXCAP_PTR:
3645 *result = cfg->pcix.pcix_ptr;
3647 case PCI_IVAR_PCIECAP_PTR:
3648 *result = cfg->expr.expr_ptr;
3650 case PCI_IVAR_VPDCAP_PTR:
3651 *result = cfg->vpd.vpd_reg;
3660 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3662 struct pci_devinfo *dinfo;
3664 dinfo = device_get_ivars(child);
3667 case PCI_IVAR_INTPIN:
3668 dinfo->cfg.intpin = value;
3670 case PCI_IVAR_ETHADDR:
3671 case PCI_IVAR_SUBVENDOR:
3672 case PCI_IVAR_SUBDEVICE:
3673 case PCI_IVAR_VENDOR:
3674 case PCI_IVAR_DEVICE:
3675 case PCI_IVAR_DEVID:
3676 case PCI_IVAR_CLASS:
3677 case PCI_IVAR_SUBCLASS:
3678 case PCI_IVAR_PROGIF:
3679 case PCI_IVAR_REVID:
3681 case PCI_IVAR_DOMAIN:
3684 case PCI_IVAR_FUNCTION:
3685 return (EINVAL); /* disallow for now */
3692 #include "opt_ddb.h"
3694 #include <ddb/ddb.h>
3695 #include <sys/cons.h>
3698 * List resources based on pci map registers, used for within ddb
3701 DB_SHOW_COMMAND(pciregs, db_pci_dump)
3703 struct pci_devinfo *dinfo;
3704 struct devlist *devlist_head;
3707 int i, error, none_count;
3710 /* get the head of the device queue */
3711 devlist_head = &pci_devq;
3714 * Go through the list of devices and print out devices
3716 for (error = 0, i = 0,
3717 dinfo = STAILQ_FIRST(devlist_head);
3718 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3719 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3721 /* Populate pd_name and pd_unit */
3724 name = device_get_name(dinfo->cfg.dev);
3727 db_kprintf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3728 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3729 (name && *name) ? name : "none",
3730 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3732 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3733 p->pc_sel.pc_func, (p->pc_class << 16) |
3734 (p->pc_subclass << 8) | p->pc_progif,
3735 (p->pc_subdevice << 16) | p->pc_subvendor,
3736 (p->pc_device << 16) | p->pc_vendor,
3737 p->pc_revid, p->pc_hdr);
3743 static struct resource *
3744 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3745 u_long start, u_long end, u_long count, u_int flags)
3747 struct pci_devinfo *dinfo = device_get_ivars(child);
3748 struct resource_list *rl = &dinfo->resources;
3749 struct resource_list_entry *rle;
3750 struct resource *res;
3751 pci_addr_t map, testval;
3755 * Weed out the bogons, and figure out how large the BAR/map
3756 * is. Bars that read back 0 here are bogus and unimplemented.
3757 * Note: atapci in legacy mode are special and handled elsewhere
3758 * in the code. If you have a atapci device in legacy mode and
3759 * it fails here, that other code is broken.
3762 map = pci_read_config(child, *rid, 4);
3763 pci_write_config(child, *rid, 0xffffffff, 4);
3764 testval = pci_read_config(child, *rid, 4);
3765 if (pci_maprange(testval) == 64)
3766 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
3767 if (pci_mapbase(testval) == 0)
3771 * Restore the original value of the BAR. We may have reprogrammed
3772 * the BAR of the low-level console device and when booting verbose,
3773 * we need the console device addressable.
3775 pci_write_config(child, *rid, map, 4);
3777 if (PCI_BAR_MEM(testval)) {
3778 if (type != SYS_RES_MEMORY) {
3781 "child %s requested type %d for rid %#x,"
3782 " but the BAR says it is an memio\n",
3783 device_get_nameunit(child), type, *rid);
3787 if (type != SYS_RES_IOPORT) {
3790 "child %s requested type %d for rid %#x,"
3791 " but the BAR says it is an ioport\n",
3792 device_get_nameunit(child), type, *rid);
3797 * For real BARs, we need to override the size that
3798 * the driver requests, because that's what the BAR
3799 * actually uses and we would otherwise have a
3800 * situation where we might allocate the excess to
3801 * another driver, which won't work.
3803 mapsize = pci_mapsize(testval);
3804 count = 1UL << mapsize;
3805 if (RF_ALIGNMENT(flags) < mapsize)
3806 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3807 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3808 flags |= RF_PREFETCHABLE;
3811 * Allocate enough resource, and then write back the
3812 * appropriate bar for that resource.
3814 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
3815 start, end, count, flags);
3817 device_printf(child,
3818 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3819 count, *rid, type, start, end);
3822 resource_list_add(rl, type, *rid, start, end, count);
3823 rle = resource_list_find(rl, type, *rid);
3825 panic("pci_alloc_map: unexpectedly can't find resource.");
3827 rle->start = rman_get_start(res);
3828 rle->end = rman_get_end(res);
3831 device_printf(child,
3832 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3833 count, *rid, type, rman_get_start(res));
3834 map = rman_get_start(res);
3836 pci_write_config(child, *rid, map, 4);
3837 if (pci_maprange(testval) == 64)
3838 pci_write_config(child, *rid + 4, map >> 32, 4);
3844 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
3845 u_long start, u_long end, u_long count, u_int flags)
3847 struct pci_devinfo *dinfo = device_get_ivars(child);
3848 struct resource_list *rl = &dinfo->resources;
3849 struct resource_list_entry *rle;
3850 pcicfgregs *cfg = &dinfo->cfg;
3853 * Perform lazy resource allocation
3855 if (device_get_parent(child) == dev) {
3859 * Can't alloc legacy interrupt once MSI messages
3860 * have been allocated.
3863 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3864 cfg->msix.msix_alloc > 0))
3868 * If the child device doesn't have an
3869 * interrupt routed and is deserving of an
3870 * interrupt, try to assign it one.
3872 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3874 pci_assign_interrupt(dev, child, 0);
3876 case SYS_RES_IOPORT:
3877 case SYS_RES_MEMORY:
3878 if (*rid < PCIR_BAR(cfg->nummaps)) {
3880 * Enable the I/O mode. We should
3881 * also be assigning resources too
3882 * when none are present. The
3883 * resource_list_alloc kind of sorta does
3886 if (PCI_ENABLE_IO(dev, child, type))
3889 rle = resource_list_find(rl, type, *rid);
3891 return (pci_alloc_map(dev, child, type, rid,
3892 start, end, count, flags));
3896 * If we've already allocated the resource, then
3897 * return it now. But first we may need to activate
3898 * it, since we don't allocate the resource as active
3899 * above. Normally this would be done down in the
3900 * nexus, but since we short-circuit that path we have
3901 * to do its job here. Not sure if we should kfree the
3902 * resource if it fails to activate.
3904 rle = resource_list_find(rl, type, *rid);
3905 if (rle != NULL && rle->res != NULL) {
3907 device_printf(child,
3908 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
3909 rman_get_size(rle->res), *rid, type,
3910 rman_get_start(rle->res));
3911 if ((flags & RF_ACTIVE) &&
3912 bus_generic_activate_resource(dev, child, type,
3913 *rid, rle->res) != 0)
3918 return (resource_list_alloc(rl, dev, child, type, rid,
3919 start, end, count, flags));
3923 pci_delete_resource(device_t dev, device_t child, int type, int rid)
3925 struct pci_devinfo *dinfo;
3926 struct resource_list *rl;
3927 struct resource_list_entry *rle;
3929 if (device_get_parent(child) != dev)
3932 dinfo = device_get_ivars(child);
3933 rl = &dinfo->resources;
3934 rle = resource_list_find(rl, type, rid);
3937 if (rman_get_device(rle->res) != dev ||
3938 rman_get_flags(rle->res) & RF_ACTIVE) {
3939 device_printf(dev, "delete_resource: "
3940 "Resource still owned by child, oops. "
3941 "(type=%d, rid=%d, addr=%lx)\n",
3942 rle->type, rle->rid,
3943 rman_get_start(rle->res));
3946 bus_release_resource(dev, type, rid, rle->res);
3948 resource_list_delete(rl, type, rid);
3951 * Why do we turn off the PCI configuration BAR when we delete a
3954 pci_write_config(child, rid, 0, 4);
3955 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
3958 struct resource_list *
3959 pci_get_resource_list (device_t dev, device_t child)
3961 struct pci_devinfo *dinfo = device_get_ivars(child);
3966 return (&dinfo->resources);
3970 pci_read_config_method(device_t dev, device_t child, int reg, int width)
3972 struct pci_devinfo *dinfo = device_get_ivars(child);
3973 pcicfgregs *cfg = &dinfo->cfg;
3975 return (PCIB_READ_CONFIG(device_get_parent(dev),
3976 cfg->bus, cfg->slot, cfg->func, reg, width));
3980 pci_write_config_method(device_t dev, device_t child, int reg,
3981 uint32_t val, int width)
3983 struct pci_devinfo *dinfo = device_get_ivars(child);
3984 pcicfgregs *cfg = &dinfo->cfg;
3986 PCIB_WRITE_CONFIG(device_get_parent(dev),
3987 cfg->bus, cfg->slot, cfg->func, reg, val, width);
3991 pci_child_location_str_method(device_t dev, device_t child, char *buf,
3995 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
3996 pci_get_function(child));
4001 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
4004 struct pci_devinfo *dinfo;
4007 dinfo = device_get_ivars(child);
4009 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
4010 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
4011 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
4017 pci_assign_interrupt_method(device_t dev, device_t child)
4019 struct pci_devinfo *dinfo = device_get_ivars(child);
4020 pcicfgregs *cfg = &dinfo->cfg;
4022 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
4027 pci_modevent(module_t mod, int what, void *arg)
4029 static struct cdev *pci_cdev;
4033 STAILQ_INIT(&pci_devq);
4035 pci_cdev = make_dev(&pcic_ops, 0, UID_ROOT, GID_WHEEL, 0644,
4037 pci_load_vendor_data();
4041 destroy_dev(pci_cdev);
4049 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
4054 * Only do header type 0 devices. Type 1 devices are bridges,
4055 * which we know need special treatment. Type 2 devices are
4056 * cardbus bridges which also require special treatment.
4057 * Other types are unknown, and we err on the side of safety
4060 if (dinfo->cfg.hdrtype != 0)
4064 * Restore the device to full power mode. We must do this
4065 * before we restore the registers because moving from D3 to
4066 * D0 will cause the chip's BARs and some other registers to
4067 * be reset to some unknown power on reset values. Cut down
4068 * the noise on boot by doing nothing if we are already in
4071 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
4072 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4074 for (i = 0; i < dinfo->cfg.nummaps; i++)
4075 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
4076 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
4077 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
4078 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
4079 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
4080 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
4081 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
4082 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
4083 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
4084 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
4085 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
4087 /* Restore MSI and MSI-X configurations if they are present. */
4088 if (dinfo->cfg.msi.msi_location != 0)
4089 pci_resume_msi(dev);
4090 if (dinfo->cfg.msix.msix_location != 0)
4091 pci_resume_msix(dev);
4095 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
4102 * Only do header type 0 devices. Type 1 devices are bridges, which
4103 * we know need special treatment. Type 2 devices are cardbus bridges
4104 * which also require special treatment. Other types are unknown, and
4105 * we err on the side of safety by ignoring them. Powering down
4106 * bridges should not be undertaken lightly.
4108 if (dinfo->cfg.hdrtype != 0)
4110 for (i = 0; i < dinfo->cfg.nummaps; i++)
4111 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
4112 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
4115 * Some drivers apparently write to these registers w/o updating our
4116 * cached copy. No harm happens if we update the copy, so do so here
4117 * so we can restore them. The COMMAND register is modified by the
4118 * bus w/o updating the cache. This should represent the normally
4119 * writable portion of the 'defined' part of type 0 headers. In
4120 * theory we also need to save/restore the PCI capability structures
4121 * we know about, but apart from power we don't know any that are
4124 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
4125 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4126 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
4127 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
4128 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
4129 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
4130 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
4131 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
4132 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
4133 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
4134 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
4135 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
4136 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
4137 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
4138 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
4141 * don't set the state for display devices, base peripherals and
4142 * memory devices since bad things happen when they are powered down.
4143 * We should (a) have drivers that can easily detach and (b) use
4144 * generic drivers for these devices so that some device actually
4145 * attaches. We need to make sure that when we implement (a) we don't
4146 * power the device down on a reattach.
4148 cls = pci_get_class(dev);
4151 switch (pci_do_power_nodriver)
4153 case 0: /* NO powerdown at all */
4155 case 1: /* Conservative about what to power down */
4156 if (cls == PCIC_STORAGE)
4159 case 2: /* Agressive about what to power down */
4160 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
4161 cls == PCIC_BASEPERIPH)
4164 case 3: /* Power down everything */
4168 * PCI spec says we can only go into D3 state from D0 state.
4169 * Transition from D[12] into D0 before going to D3 state.
4171 ps = pci_get_powerstate(dev);
4172 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
4173 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4174 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
4175 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
4178 #ifdef COMPAT_OLDPCI
4181 * Locate the parent of a PCI device by scanning the PCI devlist
4182 * and return the entry for the parent.
4183 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
4184 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
4187 pci_devlist_get_parent(pcicfgregs *cfg)
4189 struct devlist *devlist_head;
4190 struct pci_devinfo *dinfo;
4191 pcicfgregs *bridge_cfg;
4194 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
4196 /* If the device is on PCI bus 0, look for the host */
4197 if (cfg->bus == 0) {
4198 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
4199 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4200 bridge_cfg = &dinfo->cfg;
4201 if (bridge_cfg->baseclass == PCIC_BRIDGE
4202 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
4203 && bridge_cfg->bus == cfg->bus) {
4209 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
4211 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
4212 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4213 bridge_cfg = &dinfo->cfg;
4214 if (bridge_cfg->baseclass == PCIC_BRIDGE
4215 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
4216 && bridge_cfg->secondarybus == cfg->bus) {
4225 #endif /* COMPAT_OLDPCI */