2 * Copyright (c) 1991 The Regents of the University of California.
3 * Copyright (c) 1996, by Steve Passe. All rights reserved.
4 * Copyright (c) 2005,2008 The DragonFly Project. All rights reserved.
7 * This code is derived from software contributed to The DragonFly Project
8 * by Matthew Dillon <dillon@backplane.com>
10 * This code is derived from software contributed to Berkeley by
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
23 * 3. Neither the name of The DragonFly Project nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific, prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
31 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
32 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
35 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
37 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * $DragonFly: src/sys/platform/pc64/apic/apic_abi.c,v 1.1 2008/08/29 17:07:12 dillon Exp $
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
46 #include <sys/machintr.h>
47 #include <sys/interrupt.h>
50 #include <machine/smp.h>
51 #include <machine/segments.h>
52 #include <machine/md_var.h>
53 #include <machine/intr_machdep.h>
54 #include <machine_base/icu/icu.h>
55 #include <machine/globaldata.h>
57 #include <sys/thread2.h>
59 #include <machine_base/icu/icu_var.h>
60 #include <machine_base/apic/ioapic_abi.h>
61 #include <machine_base/apic/ioapic_ipl.h>
63 #ifdef SMP /* APIC-IO */
76 IDTVEC(ioapic_intr10),
77 IDTVEC(ioapic_intr11),
78 IDTVEC(ioapic_intr12),
79 IDTVEC(ioapic_intr13),
80 IDTVEC(ioapic_intr14),
81 IDTVEC(ioapic_intr15),
82 IDTVEC(ioapic_intr16),
83 IDTVEC(ioapic_intr17),
84 IDTVEC(ioapic_intr18),
85 IDTVEC(ioapic_intr19),
86 IDTVEC(ioapic_intr20),
87 IDTVEC(ioapic_intr21),
88 IDTVEC(ioapic_intr22),
89 IDTVEC(ioapic_intr23),
90 IDTVEC(ioapic_intr24),
91 IDTVEC(ioapic_intr25),
92 IDTVEC(ioapic_intr26),
93 IDTVEC(ioapic_intr27),
94 IDTVEC(ioapic_intr28),
95 IDTVEC(ioapic_intr29),
96 IDTVEC(ioapic_intr30),
97 IDTVEC(ioapic_intr31),
98 IDTVEC(ioapic_intr32),
99 IDTVEC(ioapic_intr33),
100 IDTVEC(ioapic_intr34),
101 IDTVEC(ioapic_intr35),
102 IDTVEC(ioapic_intr36),
103 IDTVEC(ioapic_intr37),
104 IDTVEC(ioapic_intr38),
105 IDTVEC(ioapic_intr39),
106 IDTVEC(ioapic_intr40),
107 IDTVEC(ioapic_intr41),
108 IDTVEC(ioapic_intr42),
109 IDTVEC(ioapic_intr43),
110 IDTVEC(ioapic_intr44),
111 IDTVEC(ioapic_intr45),
112 IDTVEC(ioapic_intr46),
113 IDTVEC(ioapic_intr47),
114 IDTVEC(ioapic_intr48),
115 IDTVEC(ioapic_intr49),
116 IDTVEC(ioapic_intr50),
117 IDTVEC(ioapic_intr51),
118 IDTVEC(ioapic_intr52),
119 IDTVEC(ioapic_intr53),
120 IDTVEC(ioapic_intr54),
121 IDTVEC(ioapic_intr55),
122 IDTVEC(ioapic_intr56),
123 IDTVEC(ioapic_intr57),
124 IDTVEC(ioapic_intr58),
125 IDTVEC(ioapic_intr59),
126 IDTVEC(ioapic_intr60),
127 IDTVEC(ioapic_intr61),
128 IDTVEC(ioapic_intr62),
129 IDTVEC(ioapic_intr63),
130 IDTVEC(ioapic_intr64),
131 IDTVEC(ioapic_intr65),
132 IDTVEC(ioapic_intr66),
133 IDTVEC(ioapic_intr67),
134 IDTVEC(ioapic_intr68),
135 IDTVEC(ioapic_intr69),
136 IDTVEC(ioapic_intr70),
137 IDTVEC(ioapic_intr71),
138 IDTVEC(ioapic_intr72),
139 IDTVEC(ioapic_intr73),
140 IDTVEC(ioapic_intr74),
141 IDTVEC(ioapic_intr75),
142 IDTVEC(ioapic_intr76),
143 IDTVEC(ioapic_intr77),
144 IDTVEC(ioapic_intr78),
145 IDTVEC(ioapic_intr79),
146 IDTVEC(ioapic_intr80),
147 IDTVEC(ioapic_intr81),
148 IDTVEC(ioapic_intr82),
149 IDTVEC(ioapic_intr83),
150 IDTVEC(ioapic_intr84),
151 IDTVEC(ioapic_intr85),
152 IDTVEC(ioapic_intr86),
153 IDTVEC(ioapic_intr87),
154 IDTVEC(ioapic_intr88),
155 IDTVEC(ioapic_intr89),
156 IDTVEC(ioapic_intr90),
157 IDTVEC(ioapic_intr91),
158 IDTVEC(ioapic_intr92),
159 IDTVEC(ioapic_intr93),
160 IDTVEC(ioapic_intr94),
161 IDTVEC(ioapic_intr95),
162 IDTVEC(ioapic_intr96),
163 IDTVEC(ioapic_intr97),
164 IDTVEC(ioapic_intr98),
165 IDTVEC(ioapic_intr99),
166 IDTVEC(ioapic_intr100),
167 IDTVEC(ioapic_intr101),
168 IDTVEC(ioapic_intr102),
169 IDTVEC(ioapic_intr103),
170 IDTVEC(ioapic_intr104),
171 IDTVEC(ioapic_intr105),
172 IDTVEC(ioapic_intr106),
173 IDTVEC(ioapic_intr107),
174 IDTVEC(ioapic_intr108),
175 IDTVEC(ioapic_intr109),
176 IDTVEC(ioapic_intr110),
177 IDTVEC(ioapic_intr111),
178 IDTVEC(ioapic_intr112),
179 IDTVEC(ioapic_intr113),
180 IDTVEC(ioapic_intr114),
181 IDTVEC(ioapic_intr115),
182 IDTVEC(ioapic_intr116),
183 IDTVEC(ioapic_intr117),
184 IDTVEC(ioapic_intr118),
185 IDTVEC(ioapic_intr119),
186 IDTVEC(ioapic_intr120),
187 IDTVEC(ioapic_intr121),
188 IDTVEC(ioapic_intr122),
189 IDTVEC(ioapic_intr123),
190 IDTVEC(ioapic_intr124),
191 IDTVEC(ioapic_intr125),
192 IDTVEC(ioapic_intr126),
193 IDTVEC(ioapic_intr127),
194 IDTVEC(ioapic_intr128),
195 IDTVEC(ioapic_intr129),
196 IDTVEC(ioapic_intr130),
197 IDTVEC(ioapic_intr131),
198 IDTVEC(ioapic_intr132),
199 IDTVEC(ioapic_intr133),
200 IDTVEC(ioapic_intr134),
201 IDTVEC(ioapic_intr135),
202 IDTVEC(ioapic_intr136),
203 IDTVEC(ioapic_intr137),
204 IDTVEC(ioapic_intr138),
205 IDTVEC(ioapic_intr139),
206 IDTVEC(ioapic_intr140),
207 IDTVEC(ioapic_intr141),
208 IDTVEC(ioapic_intr142),
209 IDTVEC(ioapic_intr143),
210 IDTVEC(ioapic_intr144),
211 IDTVEC(ioapic_intr145),
212 IDTVEC(ioapic_intr146),
213 IDTVEC(ioapic_intr147),
214 IDTVEC(ioapic_intr148),
215 IDTVEC(ioapic_intr149),
216 IDTVEC(ioapic_intr150),
217 IDTVEC(ioapic_intr151),
218 IDTVEC(ioapic_intr152),
219 IDTVEC(ioapic_intr153),
220 IDTVEC(ioapic_intr154),
221 IDTVEC(ioapic_intr155),
222 IDTVEC(ioapic_intr156),
223 IDTVEC(ioapic_intr157),
224 IDTVEC(ioapic_intr158),
225 IDTVEC(ioapic_intr159),
226 IDTVEC(ioapic_intr160),
227 IDTVEC(ioapic_intr161),
228 IDTVEC(ioapic_intr162),
229 IDTVEC(ioapic_intr163),
230 IDTVEC(ioapic_intr164),
231 IDTVEC(ioapic_intr165),
232 IDTVEC(ioapic_intr166),
233 IDTVEC(ioapic_intr167),
234 IDTVEC(ioapic_intr168),
235 IDTVEC(ioapic_intr169),
236 IDTVEC(ioapic_intr170),
237 IDTVEC(ioapic_intr171),
238 IDTVEC(ioapic_intr172),
239 IDTVEC(ioapic_intr173),
240 IDTVEC(ioapic_intr174),
241 IDTVEC(ioapic_intr175),
242 IDTVEC(ioapic_intr176),
243 IDTVEC(ioapic_intr177),
244 IDTVEC(ioapic_intr178),
245 IDTVEC(ioapic_intr179),
246 IDTVEC(ioapic_intr180),
247 IDTVEC(ioapic_intr181),
248 IDTVEC(ioapic_intr182),
249 IDTVEC(ioapic_intr183),
250 IDTVEC(ioapic_intr184),
251 IDTVEC(ioapic_intr185),
252 IDTVEC(ioapic_intr186),
253 IDTVEC(ioapic_intr187),
254 IDTVEC(ioapic_intr188),
255 IDTVEC(ioapic_intr189),
256 IDTVEC(ioapic_intr190),
257 IDTVEC(ioapic_intr191);
259 static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = {
260 &IDTVEC(ioapic_intr0),
261 &IDTVEC(ioapic_intr1),
262 &IDTVEC(ioapic_intr2),
263 &IDTVEC(ioapic_intr3),
264 &IDTVEC(ioapic_intr4),
265 &IDTVEC(ioapic_intr5),
266 &IDTVEC(ioapic_intr6),
267 &IDTVEC(ioapic_intr7),
268 &IDTVEC(ioapic_intr8),
269 &IDTVEC(ioapic_intr9),
270 &IDTVEC(ioapic_intr10),
271 &IDTVEC(ioapic_intr11),
272 &IDTVEC(ioapic_intr12),
273 &IDTVEC(ioapic_intr13),
274 &IDTVEC(ioapic_intr14),
275 &IDTVEC(ioapic_intr15),
276 &IDTVEC(ioapic_intr16),
277 &IDTVEC(ioapic_intr17),
278 &IDTVEC(ioapic_intr18),
279 &IDTVEC(ioapic_intr19),
280 &IDTVEC(ioapic_intr20),
281 &IDTVEC(ioapic_intr21),
282 &IDTVEC(ioapic_intr22),
283 &IDTVEC(ioapic_intr23),
284 &IDTVEC(ioapic_intr24),
285 &IDTVEC(ioapic_intr25),
286 &IDTVEC(ioapic_intr26),
287 &IDTVEC(ioapic_intr27),
288 &IDTVEC(ioapic_intr28),
289 &IDTVEC(ioapic_intr29),
290 &IDTVEC(ioapic_intr30),
291 &IDTVEC(ioapic_intr31),
292 &IDTVEC(ioapic_intr32),
293 &IDTVEC(ioapic_intr33),
294 &IDTVEC(ioapic_intr34),
295 &IDTVEC(ioapic_intr35),
296 &IDTVEC(ioapic_intr36),
297 &IDTVEC(ioapic_intr37),
298 &IDTVEC(ioapic_intr38),
299 &IDTVEC(ioapic_intr39),
300 &IDTVEC(ioapic_intr40),
301 &IDTVEC(ioapic_intr41),
302 &IDTVEC(ioapic_intr42),
303 &IDTVEC(ioapic_intr43),
304 &IDTVEC(ioapic_intr44),
305 &IDTVEC(ioapic_intr45),
306 &IDTVEC(ioapic_intr46),
307 &IDTVEC(ioapic_intr47),
308 &IDTVEC(ioapic_intr48),
309 &IDTVEC(ioapic_intr49),
310 &IDTVEC(ioapic_intr50),
311 &IDTVEC(ioapic_intr51),
312 &IDTVEC(ioapic_intr52),
313 &IDTVEC(ioapic_intr53),
314 &IDTVEC(ioapic_intr54),
315 &IDTVEC(ioapic_intr55),
316 &IDTVEC(ioapic_intr56),
317 &IDTVEC(ioapic_intr57),
318 &IDTVEC(ioapic_intr58),
319 &IDTVEC(ioapic_intr59),
320 &IDTVEC(ioapic_intr60),
321 &IDTVEC(ioapic_intr61),
322 &IDTVEC(ioapic_intr62),
323 &IDTVEC(ioapic_intr63),
324 &IDTVEC(ioapic_intr64),
325 &IDTVEC(ioapic_intr65),
326 &IDTVEC(ioapic_intr66),
327 &IDTVEC(ioapic_intr67),
328 &IDTVEC(ioapic_intr68),
329 &IDTVEC(ioapic_intr69),
330 &IDTVEC(ioapic_intr70),
331 &IDTVEC(ioapic_intr71),
332 &IDTVEC(ioapic_intr72),
333 &IDTVEC(ioapic_intr73),
334 &IDTVEC(ioapic_intr74),
335 &IDTVEC(ioapic_intr75),
336 &IDTVEC(ioapic_intr76),
337 &IDTVEC(ioapic_intr77),
338 &IDTVEC(ioapic_intr78),
339 &IDTVEC(ioapic_intr79),
340 &IDTVEC(ioapic_intr80),
341 &IDTVEC(ioapic_intr81),
342 &IDTVEC(ioapic_intr82),
343 &IDTVEC(ioapic_intr83),
344 &IDTVEC(ioapic_intr84),
345 &IDTVEC(ioapic_intr85),
346 &IDTVEC(ioapic_intr86),
347 &IDTVEC(ioapic_intr87),
348 &IDTVEC(ioapic_intr88),
349 &IDTVEC(ioapic_intr89),
350 &IDTVEC(ioapic_intr90),
351 &IDTVEC(ioapic_intr91),
352 &IDTVEC(ioapic_intr92),
353 &IDTVEC(ioapic_intr93),
354 &IDTVEC(ioapic_intr94),
355 &IDTVEC(ioapic_intr95),
356 &IDTVEC(ioapic_intr96),
357 &IDTVEC(ioapic_intr97),
358 &IDTVEC(ioapic_intr98),
359 &IDTVEC(ioapic_intr99),
360 &IDTVEC(ioapic_intr100),
361 &IDTVEC(ioapic_intr101),
362 &IDTVEC(ioapic_intr102),
363 &IDTVEC(ioapic_intr103),
364 &IDTVEC(ioapic_intr104),
365 &IDTVEC(ioapic_intr105),
366 &IDTVEC(ioapic_intr106),
367 &IDTVEC(ioapic_intr107),
368 &IDTVEC(ioapic_intr108),
369 &IDTVEC(ioapic_intr109),
370 &IDTVEC(ioapic_intr110),
371 &IDTVEC(ioapic_intr111),
372 &IDTVEC(ioapic_intr112),
373 &IDTVEC(ioapic_intr113),
374 &IDTVEC(ioapic_intr114),
375 &IDTVEC(ioapic_intr115),
376 &IDTVEC(ioapic_intr116),
377 &IDTVEC(ioapic_intr117),
378 &IDTVEC(ioapic_intr118),
379 &IDTVEC(ioapic_intr119),
380 &IDTVEC(ioapic_intr120),
381 &IDTVEC(ioapic_intr121),
382 &IDTVEC(ioapic_intr122),
383 &IDTVEC(ioapic_intr123),
384 &IDTVEC(ioapic_intr124),
385 &IDTVEC(ioapic_intr125),
386 &IDTVEC(ioapic_intr126),
387 &IDTVEC(ioapic_intr127),
388 &IDTVEC(ioapic_intr128),
389 &IDTVEC(ioapic_intr129),
390 &IDTVEC(ioapic_intr130),
391 &IDTVEC(ioapic_intr131),
392 &IDTVEC(ioapic_intr132),
393 &IDTVEC(ioapic_intr133),
394 &IDTVEC(ioapic_intr134),
395 &IDTVEC(ioapic_intr135),
396 &IDTVEC(ioapic_intr136),
397 &IDTVEC(ioapic_intr137),
398 &IDTVEC(ioapic_intr138),
399 &IDTVEC(ioapic_intr139),
400 &IDTVEC(ioapic_intr140),
401 &IDTVEC(ioapic_intr141),
402 &IDTVEC(ioapic_intr142),
403 &IDTVEC(ioapic_intr143),
404 &IDTVEC(ioapic_intr144),
405 &IDTVEC(ioapic_intr145),
406 &IDTVEC(ioapic_intr146),
407 &IDTVEC(ioapic_intr147),
408 &IDTVEC(ioapic_intr148),
409 &IDTVEC(ioapic_intr149),
410 &IDTVEC(ioapic_intr150),
411 &IDTVEC(ioapic_intr151),
412 &IDTVEC(ioapic_intr152),
413 &IDTVEC(ioapic_intr153),
414 &IDTVEC(ioapic_intr154),
415 &IDTVEC(ioapic_intr155),
416 &IDTVEC(ioapic_intr156),
417 &IDTVEC(ioapic_intr157),
418 &IDTVEC(ioapic_intr158),
419 &IDTVEC(ioapic_intr159),
420 &IDTVEC(ioapic_intr160),
421 &IDTVEC(ioapic_intr161),
422 &IDTVEC(ioapic_intr162),
423 &IDTVEC(ioapic_intr163),
424 &IDTVEC(ioapic_intr164),
425 &IDTVEC(ioapic_intr165),
426 &IDTVEC(ioapic_intr166),
427 &IDTVEC(ioapic_intr167),
428 &IDTVEC(ioapic_intr168),
429 &IDTVEC(ioapic_intr169),
430 &IDTVEC(ioapic_intr170),
431 &IDTVEC(ioapic_intr171),
432 &IDTVEC(ioapic_intr172),
433 &IDTVEC(ioapic_intr173),
434 &IDTVEC(ioapic_intr174),
435 &IDTVEC(ioapic_intr175),
436 &IDTVEC(ioapic_intr176),
437 &IDTVEC(ioapic_intr177),
438 &IDTVEC(ioapic_intr178),
439 &IDTVEC(ioapic_intr179),
440 &IDTVEC(ioapic_intr180),
441 &IDTVEC(ioapic_intr181),
442 &IDTVEC(ioapic_intr182),
443 &IDTVEC(ioapic_intr183),
444 &IDTVEC(ioapic_intr184),
445 &IDTVEC(ioapic_intr185),
446 &IDTVEC(ioapic_intr186),
447 &IDTVEC(ioapic_intr187),
448 &IDTVEC(ioapic_intr188),
449 &IDTVEC(ioapic_intr189),
450 &IDTVEC(ioapic_intr190),
451 &IDTVEC(ioapic_intr191)
454 #define IOAPIC_HWI_SYSCALL (IDT_OFFSET_SYSCALL - IDT_OFFSET)
456 static struct ioapic_irqmap {
457 int im_type; /* IOAPIC_IMT_ */
458 enum intr_trigger im_trig;
459 enum intr_polarity im_pola;
461 uint32_t im_flags; /* IOAPIC_IMF_ */
462 } ioapic_irqmaps[MAX_HARDINTS]; /* XXX MAX_HARDINTS may not be correct */
464 #define IOAPIC_IMT_UNUSED 0
465 #define IOAPIC_IMT_RESERVED 1
466 #define IOAPIC_IMT_LINE 2
467 #define IOAPIC_IMT_SYSCALL 3
469 #define IOAPIC_IMF_CONF 0x1
471 extern void IOAPIC_INTREN(int);
472 extern void IOAPIC_INTRDIS(int);
474 static int ioapic_setvar(int, const void *);
475 static int ioapic_getvar(int, void *);
476 static int ioapic_vectorctl(int, int, int);
477 static void ioapic_finalize(void);
478 static void ioapic_cleanup(void);
479 static void ioapic_setdefault(void);
480 static void ioapic_stabilize(void);
481 static void ioapic_initmap(void);
482 static void ioapic_intr_config(int, enum intr_trigger, enum intr_polarity);
484 struct machintr_abi MachIntrABI_IOAPIC = {
486 .intrdis = IOAPIC_INTRDIS,
487 .intren = IOAPIC_INTREN,
488 .vectorctl = ioapic_vectorctl,
489 .setvar = ioapic_setvar,
490 .getvar = ioapic_getvar,
491 .finalize = ioapic_finalize,
492 .cleanup = ioapic_cleanup,
493 .setdefault = ioapic_setdefault,
494 .stabilize = ioapic_stabilize,
495 .initmap = ioapic_initmap,
496 .intr_config = ioapic_intr_config
499 static int ioapic_abi_extint_irq = -1;
502 ioapic_setvar(int varid, const void *buf)
508 ioapic_getvar(int varid, void *buf)
514 ioapic_finalize(void)
516 KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC);
517 KKASSERT(apic_io_enable);
520 * If an IMCR is present, program bit 0 to disconnect the 8259
524 outb(0x22, 0x70); /* select IMCR */
525 outb(0x23, 0x01); /* disconnect 8259 */
530 * This routine is called after physical interrupts are enabled but before
531 * the critical section is released. We need to clean out any interrupts
532 * that had already been posted to the cpu.
537 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
540 /* Must never be called */
542 ioapic_stabilize(void)
544 panic("ioapic_stabilize is called\n");
548 ioapic_vectorctl(int op, int intr, int flags)
556 if (intr < 0 || intr >= IOAPIC_HWI_VECTORS ||
557 intr == IOAPIC_HWI_SYSCALL)
565 case MACHINTR_VECTOR_SETUP:
566 vector = IDT_OFFSET + intr;
567 setidt(vector, ioapic_intr[intr], SDT_SYSIGT, SEL_KPL, 0);
570 * Now reprogram the vector in the IO APIC. In order to avoid
571 * losing an EOI for a level interrupt, which is vector based,
572 * make sure that the IO APIC is programmed for edge-triggering
573 * first, then reprogrammed with the new vector. This should
576 if (int_to_apicintpin[intr].ioapic >= 0) {
579 select = int_to_apicintpin[intr].redirindex;
580 value = ioapic_read(int_to_apicintpin[intr].apic_address,
582 value |= IOART_INTMSET;
584 ioapic_write(int_to_apicintpin[intr].apic_address,
585 select, (value & ~APIC_TRIGMOD_MASK));
586 ioapic_write(int_to_apicintpin[intr].apic_address,
587 select, (value & ~IOART_INTVEC) | vector);
592 machintr_intren(intr);
595 case MACHINTR_VECTOR_TEARDOWN:
597 * Teardown an interrupt vector. The vector should already be
598 * installed in the cpu's IDT, but make sure.
600 machintr_intrdis(intr);
602 vector = IDT_OFFSET + intr;
603 setidt(vector, ioapic_intr[intr], SDT_SYSIGT, SEL_KPL, 0);
606 * In order to avoid losing an EOI for a level interrupt, which
607 * is vector based, make sure that the IO APIC is programmed for
608 * edge-triggering first, then reprogrammed with the new vector.
609 * This should clear the IRR bit.
611 if (int_to_apicintpin[intr].ioapic >= 0) {
614 select = int_to_apicintpin[intr].redirindex;
615 value = ioapic_read(int_to_apicintpin[intr].apic_address,
618 ioapic_write(int_to_apicintpin[intr].apic_address,
619 select, (value & ~APIC_TRIGMOD_MASK));
620 ioapic_write(int_to_apicintpin[intr].apic_address,
621 select, (value & ~IOART_INTVEC) | vector);
637 ioapic_setdefault(void)
641 for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) {
642 if (intr == IOAPIC_HWI_SYSCALL)
644 setidt(IDT_OFFSET + intr, ioapic_intr[intr], SDT_SYSIGT,
654 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i)
655 ioapic_irqmaps[i].im_gsi = -1;
656 ioapic_irqmaps[IOAPIC_HWI_SYSCALL].im_type = IOAPIC_IMT_SYSCALL;
660 ioapic_abi_set_irqmap(int irq, int gsi, enum intr_trigger trig,
661 enum intr_polarity pola)
663 struct apic_intmapinfo *info;
664 struct ioapic_irqmap *map;
668 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
669 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
671 KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
672 map = &ioapic_irqmaps[irq];
674 KKASSERT(map->im_type == IOAPIC_IMT_UNUSED);
675 map->im_type = IOAPIC_IMT_LINE;
682 kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n",
684 intr_str_trigger(map->im_trig),
685 intr_str_polarity(map->im_pola));
688 pin = ioapic_gsi_pin(map->im_gsi);
689 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
691 info = &int_to_apicintpin[irq];
695 info->ioapic = 0; /* XXX unused */
697 info->apic_address = ioaddr;
698 info->redirindex = IOAPIC_REDTBL + (2 * pin);
699 info->flags = IOAPIC_IM_FLAG_MASKED;
700 if (map->im_trig == INTR_TRIGGER_LEVEL)
701 info->flags |= IOAPIC_IM_FLAG_LEVEL;
703 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
704 map->im_trig, map->im_pola);
710 ioapic_abi_fixup_irqmap(void)
714 for (i = 0; i < 16; ++i) {
715 struct ioapic_irqmap *map = &ioapic_irqmaps[i];
717 if (map->im_type == IOAPIC_IMT_UNUSED) {
718 map->im_type = IOAPIC_IMT_RESERVED;
720 kprintf("IOAPIC: irq %d reserved\n", i);
726 ioapic_abi_find_gsi(int gsi, enum intr_trigger trig, enum intr_polarity pola)
730 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
731 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
733 for (irq = 0; irq < IOAPIC_HWI_VECTORS; ++irq) {
734 const struct ioapic_irqmap *map = &ioapic_irqmaps[irq];
736 if (map->im_gsi == gsi) {
737 KKASSERT(map->im_type == IOAPIC_IMT_LINE);
739 if (map->im_flags & IOAPIC_IMF_CONF) {
740 if (map->im_trig != trig ||
741 map->im_pola != pola)
751 ioapic_abi_find_irq(int irq, enum intr_trigger trig, enum intr_polarity pola)
753 const struct ioapic_irqmap *map;
755 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
756 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
758 if (irq < 0 || irq >= IOAPIC_HWI_VECTORS)
760 map = &ioapic_irqmaps[irq];
762 if (map->im_type != IOAPIC_IMT_LINE)
765 if (map->im_flags & IOAPIC_IMF_CONF) {
766 if (map->im_trig != trig || map->im_pola != pola)
773 ioapic_intr_config(int irq, enum intr_trigger trig, enum intr_polarity pola)
775 struct apic_intmapinfo *info;
776 struct ioapic_irqmap *map;
780 if (ioapic_use_old) {
782 kprintf("irq %d, trig %c\n", irq,
783 trig == INTR_TRIGGER_EDGE ? 'E' : 'L');
788 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
789 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
791 KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
792 map = &ioapic_irqmaps[irq];
794 KKASSERT(map->im_type == IOAPIC_IMT_LINE);
797 if (map->im_flags & IOAPIC_IMF_CONF) {
798 if (trig != map->im_trig) {
799 panic("ioapic_intr_config: trig %s -> %s\n",
800 intr_str_trigger(map->im_trig),
801 intr_str_trigger(trig));
803 if (pola != map->im_pola) {
804 panic("ioapic_intr_config: pola %s -> %s\n",
805 intr_str_polarity(map->im_pola),
806 intr_str_polarity(pola));
811 map->im_flags |= IOAPIC_IMF_CONF;
813 if (trig == map->im_trig && pola == map->im_pola)
817 kprintf("IOAPIC: irq %d, gsi %d %s/%s -> %s/%s\n",
819 intr_str_trigger(map->im_trig),
820 intr_str_polarity(map->im_pola),
821 intr_str_trigger(trig),
822 intr_str_polarity(pola));
827 pin = ioapic_gsi_pin(map->im_gsi);
828 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
830 info = &int_to_apicintpin[irq];
834 info->flags &= ~IOAPIC_IM_FLAG_LEVEL;
835 if (map->im_trig == INTR_TRIGGER_LEVEL)
836 info->flags |= IOAPIC_IM_FLAG_LEVEL;
838 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
839 map->im_trig, map->im_pola);
845 ioapic_abi_extint_irqmap(int irq)
847 struct apic_intmapinfo *info;
848 struct ioapic_irqmap *map;
852 vec = IDT_OFFSET + irq;
854 if (ioapic_abi_extint_irq == irq)
856 else if (ioapic_abi_extint_irq >= 0)
859 error = icu_ioapic_extint(irq, vec);
863 map = &ioapic_irqmaps[irq];
865 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED ||
866 map->im_type == IOAPIC_IMT_LINE);
867 if (map->im_type == IOAPIC_IMT_LINE) {
868 if (map->im_flags & IOAPIC_IMF_CONF)
871 ioapic_abi_extint_irq = irq;
873 map->im_type = IOAPIC_IMT_LINE;
874 map->im_trig = INTR_TRIGGER_EDGE;
875 map->im_pola = INTR_POLARITY_HIGH;
876 map->im_flags = IOAPIC_IMF_CONF;
878 map->im_gsi = ioapic_extpin_gsi();
879 KKASSERT(map->im_gsi >= 0);
882 kprintf("IOAPIC: irq %d -> extint gsi %d %s/%s\n",
884 intr_str_trigger(map->im_trig),
885 intr_str_polarity(map->im_pola));
888 pin = ioapic_gsi_pin(map->im_gsi);
889 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
891 info = &int_to_apicintpin[irq];
895 info->ioapic = 0; /* XXX unused */
897 info->apic_address = ioaddr;
898 info->redirindex = IOAPIC_REDTBL + (2 * pin);
899 info->flags = IOAPIC_IM_FLAG_MASKED;
901 ioapic_extpin_setup(ioaddr, pin, vec);