2 * Copyright (c) 1993 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * $FreeBSD: src/sys/i386/include/cpufunc.h,v 1.96.2.3 2002/04/28 22:50:54 dwmalone Exp $
34 * $DragonFly: src/sys/cpu/i386/include/cpufunc.h,v 1.21 2007/04/27 23:23:59 dillon Exp $
38 * Functions to provide access to special i386 instructions.
41 #ifndef _CPU_CPUFUNC_H_
42 #define _CPU_CPUFUNC_H_
45 #include <sys/types.h>
48 #include <sys/cdefs.h>
52 #define readb(va) (*(volatile u_int8_t *) (va))
53 #define readw(va) (*(volatile u_int16_t *) (va))
54 #define readl(va) (*(volatile u_int32_t *) (va))
56 #define writeb(va, d) (*(volatile u_int8_t *) (va) = (d))
57 #define writew(va, d) (*(volatile u_int16_t *) (va) = (d))
58 #define writel(va, d) (*(volatile u_int32_t *) (va) = (d))
63 #include <machine/lock.h> /* XXX */
66 #ifdef SWTCH_OPTIM_STATS
67 extern int tlb_flush_count; /* XXX */
73 __asm __volatile("int $3");
79 __asm __volatile("pause");
83 * Find the first 1 in mask, starting with bit 0 and return the
84 * bit number. If mask is 0 the result is undefined.
91 __asm __volatile("bsfl %0,%0" : "=r" (result) : "0" (mask));
96 * Find the last 1 in mask, starting with bit 31 and return the
97 * bit number. If mask is 0 the result is undefined.
104 __asm __volatile("bsrl %0,%0" : "=r" (result) : "0" (mask));
109 * Test and set the specified bit (1 << bit) in the integer. The
110 * previous value of the bit is returned (0 or 1).
113 btsl(u_int *mask, int bit)
117 __asm __volatile("btsl %2,%1; movl $0,%0; adcl $0,%0" :
118 "=r"(result), "=m"(*mask) : "r" (bit));
123 * Test and clear the specified bit (1 << bit) in the integer. The
124 * previous value of the bit is returned (0 or 1).
127 btrl(u_int *mask, int bit)
131 __asm __volatile("btrl %2,%1; movl $0,%0; adcl $0,%0" :
132 "=r"(result), "=m"(*mask) : "r" (bit));
137 do_cpuid(u_int ax, u_int *p)
139 __asm __volatile("cpuid"
140 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
145 cpuid_count(u_int ax, u_int cx, u_int *p)
147 __asm __volatile("cpuid"
148 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
149 : "0" (ax), "c" (cx));
152 #ifndef _CPU_DISABLE_INTR_DEFINED
155 cpu_disable_intr(void)
157 __asm __volatile("cli" : : : "memory");
162 #ifndef _CPU_ENABLE_INTR_DEFINED
165 cpu_enable_intr(void)
167 __asm __volatile("sti");
173 * Cpu and compiler memory ordering fence. mfence ensures strong read and
176 * A serializing or fence instruction is required here. A locked bus
177 * cycle on data for which we already own cache mastership is the most
184 __asm __volatile("lock; addl $0,(%%esp)" : : : "memory");
186 __asm __volatile("" : : : "memory");
191 * cpu_lfence() ensures strong read ordering for reads issued prior
192 * to the instruction verses reads issued afterwords.
194 * A serializing or fence instruction is required here. A locked bus
195 * cycle on data for which we already own cache mastership is the most
202 __asm __volatile("lock; addl $0,(%%esp)" : : : "memory");
204 __asm __volatile("" : : : "memory");
209 * cpu_sfence() ensures strong write ordering for writes issued prior
210 * to the instruction verses writes issued afterwords. Writes are
211 * ordered on intel cpus so we do not actually have to do anything.
216 __asm __volatile("" : : : "memory");
220 * cpu_ccfence() prevents the compiler from reordering instructions, in
221 * particular stores, relative to the current cpu. Use cpu_sfence() if
222 * you need to guarentee ordering by both the compiler and by the cpu.
224 * This also prevents the compiler from caching memory loads into local
225 * variables across the routine.
230 __asm __volatile("" : : : "memory");
235 #define HAVE_INLINE_FFS
241 * Note that gcc-2's builtin ffs would be used if we didn't declare
242 * this inline or turn off the builtin. The builtin is faster but
243 * broken in gcc-2.4.5 and slower but working in gcc-2.5 and later
246 return (mask == 0 ? mask : (int)bsfl((u_int)mask) + 1);
249 #define HAVE_INLINE_FLS
254 return (mask == 0 ? mask : (int) bsrl((u_int)mask) + 1);
260 * The following complications are to get around gcc not having a
261 * constraint letter for the range 0..255. We still put "d" in the
262 * constraint because "i" isn't a valid constraint when the port
263 * isn't constant. This only matters for -O0 because otherwise
264 * the non-working version gets optimized away.
266 * Use an expression-statement instead of a conditional expression
267 * because gcc-2.6.0 would promote the operands of the conditional
268 * and produce poor code for "if ((inb(var) & const1) == const2)".
270 * The unnecessary test `(port) < 0x10000' is to generate a warning if
271 * the `port' has type u_short or smaller. Such types are pessimal.
272 * This actually only works for signed types. The range check is
273 * careful to avoid generating warnings.
275 #define inb(port) __extension__ ({ \
277 if (__builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
278 && (port) < 0x10000) \
279 _data = inbc(port); \
281 _data = inbv(port); \
284 #define outb(port, data) ( \
285 __builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
286 && (port) < 0x10000 \
287 ? outbc(port, data) : outbv(port, data))
289 static __inline u_char
294 __asm __volatile("inb %1,%0" : "=a" (data) : "id" ((u_short)(port)));
299 outbc(u_int port, u_char data)
301 __asm __volatile("outb %0,%1" : : "a" (data), "id" ((u_short)(port)));
304 static __inline u_char
309 * We use %%dx and not %1 here because i/o is done at %dx and not at
310 * %edx, while gcc generates inferior code (movw instead of movl)
311 * if we tell it to load (u_short) port.
313 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
317 static __inline u_int
322 __asm __volatile("inl %%dx,%0" : "=a" (data) : "d" (port));
327 insb(u_int port, void *addr, size_t cnt)
329 __asm __volatile("cld; rep; insb"
330 : "=D" (addr), "=c" (cnt)
331 : "0" (addr), "1" (cnt), "d" (port)
336 insw(u_int port, void *addr, size_t cnt)
338 __asm __volatile("cld; rep; insw"
339 : "=D" (addr), "=c" (cnt)
340 : "0" (addr), "1" (cnt), "d" (port)
345 insl(u_int port, void *addr, size_t cnt)
347 __asm __volatile("cld; rep; insl"
348 : "=D" (addr), "=c" (cnt)
349 : "0" (addr), "1" (cnt), "d" (port)
356 __asm __volatile("invd");
362 * If we are not a true-SMP box then smp_invltlb() is a NOP. Note that this
363 * will cause the invl*() functions to be equivalent to the cpu_invl*()
367 void smp_invltlb(void);
369 #define smp_invltlb()
372 #ifndef _CPU_INVLPG_DEFINED
375 * Invalidate a patricular VA on this cpu only
378 cpu_invlpg(void *addr)
380 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
385 #ifndef _CPU_INVLTLB_DEFINED
388 * Invalidate the TLB on this cpu only
395 * This should be implemented as load_cr3(rcr3()) when load_cr3()
398 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3" : "=r" (temp)
400 #if defined(SWTCH_OPTIM_STATS)
410 __asm __volatile("rep; nop");
415 static __inline u_short
420 __asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
424 static __inline u_int
425 loadandclear(volatile u_int *addr)
429 __asm __volatile("xorl %0,%0; xchgl %1,%0"
430 : "=&r" (result) : "m" (*addr));
435 outbv(u_int port, u_char data)
439 * Use an unnecessary assignment to help gcc's register allocator.
440 * This make a large difference for gcc-1.40 and a tiny difference
441 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
442 * best results. gcc-2.6.0 can't handle this.
445 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
449 outl(u_int port, u_int data)
452 * outl() and outw() aren't used much so we haven't looked at
453 * possible micro-optimizations such as the unnecessary
454 * assignment for them.
456 __asm __volatile("outl %0,%%dx" : : "a" (data), "d" (port));
460 outsb(u_int port, const void *addr, size_t cnt)
462 __asm __volatile("cld; rep; outsb"
463 : "=S" (addr), "=c" (cnt)
464 : "0" (addr), "1" (cnt), "d" (port));
468 outsw(u_int port, const void *addr, size_t cnt)
470 __asm __volatile("cld; rep; outsw"
471 : "=S" (addr), "=c" (cnt)
472 : "0" (addr), "1" (cnt), "d" (port));
476 outsl(u_int port, const void *addr, size_t cnt)
478 __asm __volatile("cld; rep; outsl"
479 : "=S" (addr), "=c" (cnt)
480 : "0" (addr), "1" (cnt), "d" (port));
484 outw(u_int port, u_short data)
486 __asm __volatile("outw %0,%%dx" : : "a" (data), "d" (port));
489 static __inline u_int
494 __asm __volatile("movl %%cr2,%0" : "=r" (data));
498 static __inline u_int
503 __asm __volatile("pushfl; popl %0" : "=r" (ef));
507 static __inline u_int64_t
512 __asm __volatile(".byte 0x0f, 0x32" : "=A" (rv) : "c" (msr));
516 static __inline u_int64_t
521 __asm __volatile(".byte 0x0f, 0x33" : "=A" (rv) : "c" (pmc));
525 #define _RDTSC_SUPPORTED_
527 static __inline u_int64_t
532 __asm __volatile(".byte 0x0f, 0x31" : "=A" (rv));
539 __asm __volatile("wbinvd");
543 write_eflags(u_int ef)
545 __asm __volatile("pushl %0; popfl" : : "r" (ef));
549 wrmsr(u_int msr, u_int64_t newval)
551 __asm __volatile(".byte 0x0f, 0x30" : : "A" (newval), "c" (msr));
554 static __inline u_int
558 __asm __volatile("movw %%fs,%0" : "=rm" (sel));
562 static __inline u_int
566 __asm __volatile("movw %%gs,%0" : "=rm" (sel));
573 __asm __volatile("movw %0,%%fs" : : "rm" (sel));
579 __asm __volatile("movw %0,%%gs" : : "rm" (sel));
582 static __inline u_int
586 __asm __volatile("movl %%dr0,%0" : "=r" (data));
593 __asm __volatile("movl %0,%%dr0" : : "r" (sel));
596 static __inline u_int
600 __asm __volatile("movl %%dr1,%0" : "=r" (data));
607 __asm __volatile("movl %0,%%dr1" : : "r" (sel));
610 static __inline u_int
614 __asm __volatile("movl %%dr2,%0" : "=r" (data));
621 __asm __volatile("movl %0,%%dr2" : : "r" (sel));
624 static __inline u_int
628 __asm __volatile("movl %%dr3,%0" : "=r" (data));
635 __asm __volatile("movl %0,%%dr3" : : "r" (sel));
638 static __inline u_int
642 __asm __volatile("movl %%dr4,%0" : "=r" (data));
649 __asm __volatile("movl %0,%%dr4" : : "r" (sel));
652 static __inline u_int
656 __asm __volatile("movl %%dr5,%0" : "=r" (data));
663 __asm __volatile("movl %0,%%dr5" : : "r" (sel));
666 static __inline u_int
670 __asm __volatile("movl %%dr6,%0" : "=r" (data));
677 __asm __volatile("movl %0,%%dr6" : : "r" (sel));
680 static __inline u_int
684 __asm __volatile("movl %%dr7,%0" : "=r" (data));
691 __asm __volatile("movl %0,%%dr7" : : "r" (sel));
694 #else /* !__GNUC__ */
696 int breakpoint (void);
697 void cpu_pause (void);
698 u_int bsfl (u_int mask);
699 u_int bsrl (u_int mask);
700 void cpu_disable_intr (void);
701 void do_cpuid (u_int ax, u_int *p);
702 void cpu_enable_intr (void);
703 u_char inb (u_int port);
704 u_int inl (u_int port);
705 void insb (u_int port, void *addr, size_t cnt);
706 void insl (u_int port, void *addr, size_t cnt);
707 void insw (u_int port, void *addr, size_t cnt);
709 u_short inw (u_int port);
710 u_int loadandclear (u_int *addr);
711 void outb (u_int port, u_char data);
712 void outl (u_int port, u_int data);
713 void outsb (u_int port, void *addr, size_t cnt);
714 void outsl (u_int port, void *addr, size_t cnt);
715 void outsw (u_int port, void *addr, size_t cnt);
716 void outw (u_int port, u_short data);
718 u_int64_t rdmsr (u_int msr);
719 u_int64_t rdpmc (u_int pmc);
720 u_int64_t rdtsc (void);
721 u_int read_eflags (void);
723 void write_eflags (u_int ef);
724 void wrmsr (u_int msr, u_int64_t newval);
727 void load_fs (u_int sel);
728 void load_gs (u_int sel);
730 #endif /* __GNUC__ */
732 void load_cr0 (u_int cr0);
733 void load_cr3 (u_int cr3);
734 void load_cr4 (u_int cr4);
735 void ltr (u_short sel);
739 void reset_dbregs (void);
742 #endif /* !_CPU_CPUFUNC_H_ */