2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
34 * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.64 2007/03/31 09:31:57 sephe Exp $
39 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
41 * Written by Bill Paul <wpaul@windriver.com>
42 * Senior Engineer, Wind River Systems
46 * The Broadcom BCM5700 is based on technology originally developed by
47 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
48 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
49 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
50 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
51 * frames, highly configurable RX filtering, and 16 RX and TX queues
52 * (which, along with RX filter rules, can be used for QOS applications).
53 * Other features, such as TCP segmentation, may be available as part
54 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
55 * firmware images can be stored in hardware and need not be compiled
58 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
59 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
61 * The BCM5701 is a single-chip solution incorporating both the BCM5700
62 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
63 * does not support external SSRAM.
65 * Broadcom also produces a variation of the BCM5700 under the "Altima"
66 * brand name, which is functionally similar but lacks PCI-X support.
68 * Without external SSRAM, you can only have at most 4 TX rings,
69 * and the use of the mini RX ring is disabled. This seems to imply
70 * that these features are simply not available on the BCM5701. As a
71 * result, this driver does not implement any support for the mini RX
75 #include <sys/param.h>
76 #include <sys/systm.h>
77 #include <sys/sockio.h>
79 #include <sys/malloc.h>
80 #include <sys/kernel.h>
81 #include <sys/socket.h>
82 #include <sys/queue.h>
83 #include <sys/serialize.h>
84 #include <sys/thread2.h>
87 #include <net/ifq_var.h>
88 #include <net/if_arp.h>
89 #include <net/ethernet.h>
90 #include <net/if_dl.h>
91 #include <net/if_media.h>
95 #include <net/if_types.h>
96 #include <net/vlan/if_vlan_var.h>
98 #include <netinet/in_systm.h>
99 #include <netinet/in.h>
100 #include <netinet/ip.h>
102 #include <vm/vm.h> /* for vtophys */
103 #include <vm/pmap.h> /* for vtophys */
105 #include <sys/rman.h>
107 #include <dev/netif/mii_layer/mii.h>
108 #include <dev/netif/mii_layer/miivar.h>
109 #include <dev/netif/mii_layer/miidevs.h>
110 #include <dev/netif/mii_layer/brgphyreg.h>
112 #include <bus/pci/pcidevs.h>
113 #include <bus/pci/pcireg.h>
114 #include <bus/pci/pcivar.h>
116 #include "if_bgereg.h"
118 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
120 /* "controller miibus0" required. See GENERIC if you get errors here. */
121 #include "miibus_if.h"
124 * Various supported device vendors/types and their names. Note: the
125 * spec seems to indicate that the hardware still has Alteon's vendor
126 * ID burned into it, though it will always be overriden by the vendor
127 * ID in the EEPROM. Just to be safe, we cover all possibilities.
129 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */
131 static struct bge_type bge_devs[] = {
132 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
133 "Alteon BCM5700 Gigabit Ethernet" },
134 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
135 "Alteon BCM5701 Gigabit Ethernet" },
136 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
137 "Broadcom BCM5700 Gigabit Ethernet" },
138 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
139 "Broadcom BCM5701 Gigabit Ethernet" },
140 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
141 "Broadcom BCM5702X Gigabit Ethernet" },
142 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
143 "Broadcom BCM5702 Gigabit Ethernet" },
144 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
145 "Broadcom BCM5703X Gigabit Ethernet" },
146 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
147 "Broadcom BCM5703 Gigabit Ethernet" },
148 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
149 "Broadcom BCM5704C Dual Gigabit Ethernet" },
150 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
151 "Broadcom BCM5704S Dual Gigabit Ethernet" },
152 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
153 "Broadcom BCM5705 Gigabit Ethernet" },
154 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
155 "Broadcom BCM5705K Gigabit Ethernet" },
156 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
157 "Broadcom BCM5705M Gigabit Ethernet" },
158 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
159 "Broadcom BCM5705M Gigabit Ethernet" },
160 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
161 "Broadcom BCM5714C Gigabit Ethernet" },
162 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
163 "Broadcom BCM5721 Gigabit Ethernet" },
164 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
165 "Broadcom BCM5750 Gigabit Ethernet" },
166 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
167 "Broadcom BCM5750M Gigabit Ethernet" },
168 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
169 "Broadcom BCM5751 Gigabit Ethernet" },
170 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
171 "Broadcom BCM5751M Gigabit Ethernet" },
172 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
173 "Broadcom BCM5752 Gigabit Ethernet" },
174 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
175 "Broadcom BCM5782 Gigabit Ethernet" },
176 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
177 "Broadcom BCM5788 Gigabit Ethernet" },
178 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
179 "Broadcom BCM5789 Gigabit Ethernet" },
180 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
181 "Broadcom BCM5901 Fast Ethernet" },
182 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
183 "Broadcom BCM5901A2 Fast Ethernet" },
184 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
185 "SysKonnect Gigabit Ethernet" },
186 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
187 "Altima AC1000 Gigabit Ethernet" },
188 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
189 "Altima AC1002 Gigabit Ethernet" },
190 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
191 "Altima AC9100 Gigabit Ethernet" },
195 static int bge_probe(device_t);
196 static int bge_attach(device_t);
197 static int bge_detach(device_t);
198 static void bge_release_resources(struct bge_softc *);
199 static void bge_txeof(struct bge_softc *);
200 static void bge_rxeof(struct bge_softc *);
202 static void bge_tick(void *);
203 static void bge_tick_serialized(void *);
204 static void bge_stats_update(struct bge_softc *);
205 static void bge_stats_update_regs(struct bge_softc *);
206 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *);
208 static void bge_intr(void *);
209 static void bge_start(struct ifnet *);
210 static int bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
211 static void bge_init(void *);
212 static void bge_stop(struct bge_softc *);
213 static void bge_watchdog(struct ifnet *);
214 static void bge_shutdown(device_t);
215 static int bge_suspend(device_t);
216 static int bge_resume(device_t);
217 static int bge_ifmedia_upd(struct ifnet *);
218 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
220 static uint8_t bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
221 static int bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
223 static void bge_setmulti(struct bge_softc *);
224 static void bge_setpromisc(struct bge_softc *);
226 static void bge_handle_events(struct bge_softc *);
227 static int bge_alloc_jumbo_mem(struct bge_softc *);
228 static void bge_free_jumbo_mem(struct bge_softc *);
229 static struct bge_jslot
230 *bge_jalloc(struct bge_softc *);
231 static void bge_jfree(void *);
232 static void bge_jref(void *);
233 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
234 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
235 static int bge_init_rx_ring_std(struct bge_softc *);
236 static void bge_free_rx_ring_std(struct bge_softc *);
237 static int bge_init_rx_ring_jumbo(struct bge_softc *);
238 static void bge_free_rx_ring_jumbo(struct bge_softc *);
239 static void bge_free_tx_ring(struct bge_softc *);
240 static int bge_init_tx_ring(struct bge_softc *);
242 static int bge_chipinit(struct bge_softc *);
243 static int bge_blockinit(struct bge_softc *);
246 static uint8_t bge_vpd_readbyte(struct bge_softc *, uint32_t);
247 static void bge_vpd_read_res(struct bge_softc *, struct vpd_res *, uint32_t);
248 static void bge_vpd_read(struct bge_softc *);
251 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
252 static void bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
254 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
256 static void bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
258 static int bge_miibus_readreg(device_t, int, int);
259 static int bge_miibus_writereg(device_t, int, int, int);
260 static void bge_miibus_statchg(device_t);
262 static void bge_reset(struct bge_softc *);
265 * Set following tunable to 1 for some IBM blade servers with the DNLK
266 * switch module. Auto negotiation is broken for those configurations.
268 static int bge_fake_autoneg = 0;
269 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
271 static device_method_t bge_methods[] = {
272 /* Device interface */
273 DEVMETHOD(device_probe, bge_probe),
274 DEVMETHOD(device_attach, bge_attach),
275 DEVMETHOD(device_detach, bge_detach),
276 DEVMETHOD(device_shutdown, bge_shutdown),
277 DEVMETHOD(device_suspend, bge_suspend),
278 DEVMETHOD(device_resume, bge_resume),
281 DEVMETHOD(bus_print_child, bus_generic_print_child),
282 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
285 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
286 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
287 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
292 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
293 static devclass_t bge_devclass;
295 DECLARE_DUMMY_MODULE(if_bge);
296 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
297 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
300 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
302 device_t dev = sc->bge_dev;
304 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
305 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4));
309 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
311 device_t dev = sc->bge_dev;
313 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
314 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
319 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
321 device_t dev = sc->bge_dev;
323 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
324 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
329 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
331 device_t dev = sc->bge_dev;
333 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
334 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
339 bge_vpd_readbyte(struct bge_softc *sc, uint32_t addr)
341 device_t dev = sc->bge_dev;
345 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2);
346 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
348 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG)
352 if (i == BGE_TIMEOUT) {
353 device_printf(sc->bge_dev, "VPD read timed out\n");
357 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4);
359 return((val >> ((addr % 4) * 8)) & 0xFF);
363 bge_vpd_read_res(struct bge_softc *sc, struct vpd_res *res, uint32_t addr)
368 ptr = (uint8_t *)res;
369 for (i = 0; i < sizeof(struct vpd_res); i++)
370 ptr[i] = bge_vpd_readbyte(sc, i + addr);
376 bge_vpd_read(struct bge_softc *sc)
381 if (sc->bge_vpd_prodname != NULL)
382 kfree(sc->bge_vpd_prodname, M_DEVBUF);
383 if (sc->bge_vpd_readonly != NULL)
384 kfree(sc->bge_vpd_readonly, M_DEVBUF);
385 sc->bge_vpd_prodname = NULL;
386 sc->bge_vpd_readonly = NULL;
388 bge_vpd_read_res(sc, &res, pos);
390 if (res.vr_id != VPD_RES_ID) {
391 device_printf(sc->bge_dev,
392 "bad VPD resource id: expected %x got %x\n",
393 VPD_RES_ID, res.vr_id);
398 sc->bge_vpd_prodname = kmalloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT);
399 for (i = 0; i < res.vr_len; i++)
400 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos);
401 sc->bge_vpd_prodname[i] = '\0';
404 bge_vpd_read_res(sc, &res, pos);
406 if (res.vr_id != VPD_RES_READ) {
407 device_printf(sc->bge_dev,
408 "bad VPD resource id: expected %x got %x\n",
409 VPD_RES_READ, res.vr_id);
414 sc->bge_vpd_readonly = kmalloc(res.vr_len, M_DEVBUF, M_INTWAIT);
415 for (i = 0; i < res.vr_len + 1; i++)
416 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos);
421 * Read a byte of data stored in the EEPROM at address 'addr.' The
422 * BCM570x supports both the traditional bitbang interface and an
423 * auto access interface for reading the EEPROM. We use the auto
427 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
433 * Enable use of auto EEPROM access so we can avoid
434 * having to use the bitbang method.
436 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
438 /* Reset the EEPROM, load the clock period. */
439 CSR_WRITE_4(sc, BGE_EE_ADDR,
440 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
443 /* Issue the read EEPROM command. */
444 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
446 /* Wait for completion */
447 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
449 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
453 if (i == BGE_TIMEOUT) {
454 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
459 byte = CSR_READ_4(sc, BGE_EE_DATA);
461 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
467 * Read a sequence of bytes from the EEPROM.
470 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
476 for (byte = 0, err = 0, i = 0; i < len; i++) {
477 err = bge_eeprom_getbyte(sc, off + i, &byte);
487 bge_miibus_readreg(device_t dev, int phy, int reg)
489 struct bge_softc *sc;
491 uint32_t val, autopoll;
494 sc = device_get_softc(dev);
495 ifp = &sc->arpcom.ac_if;
498 * Broadcom's own driver always assumes the internal
499 * PHY is at GMII address 1. On some chips, the PHY responds
500 * to accesses at all addresses, which could cause us to
501 * bogusly attach the PHY 32 times at probe type. Always
502 * restricting the lookup to address 1 is simpler than
503 * trying to figure out which chips revisions should be
509 /* Reading with autopolling on may trigger PCI errors */
510 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
511 if (autopoll & BGE_MIMODE_AUTOPOLL) {
512 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
516 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
517 BGE_MIPHY(phy)|BGE_MIREG(reg));
519 for (i = 0; i < BGE_TIMEOUT; i++) {
520 val = CSR_READ_4(sc, BGE_MI_COMM);
521 if (!(val & BGE_MICOMM_BUSY))
525 if (i == BGE_TIMEOUT) {
526 if_printf(ifp, "PHY read timed out\n");
531 val = CSR_READ_4(sc, BGE_MI_COMM);
534 if (autopoll & BGE_MIMODE_AUTOPOLL) {
535 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
539 if (val & BGE_MICOMM_READFAIL)
542 return(val & 0xFFFF);
546 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
548 struct bge_softc *sc;
552 sc = device_get_softc(dev);
554 /* Reading with autopolling on may trigger PCI errors */
555 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
556 if (autopoll & BGE_MIMODE_AUTOPOLL) {
557 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
561 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
562 BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
564 for (i = 0; i < BGE_TIMEOUT; i++) {
565 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
569 if (autopoll & BGE_MIMODE_AUTOPOLL) {
570 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
574 if (i == BGE_TIMEOUT) {
575 if_printf(&sc->arpcom.ac_if, "PHY read timed out\n");
583 bge_miibus_statchg(device_t dev)
585 struct bge_softc *sc;
586 struct mii_data *mii;
588 sc = device_get_softc(dev);
589 mii = device_get_softc(sc->bge_miibus);
591 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
592 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
593 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
595 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
598 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
599 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
601 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
606 * Handle events that have triggered interrupts.
609 bge_handle_events(struct bge_softc *sc)
614 * Memory management for jumbo frames.
617 bge_alloc_jumbo_mem(struct bge_softc *sc)
619 struct bge_jslot *entry;
623 /* Grab a big chunk o' storage. */
624 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF,
625 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
627 if (sc->bge_cdata.bge_jumbo_buf == NULL) {
628 if_printf(&sc->arpcom.ac_if, "no memory for jumbo buffers!\n");
632 SLIST_INIT(&sc->bge_jfree_listhead);
635 * Now divide it up into 9K pieces and save the addresses
636 * in an array. Note that we play an evil trick here by using
637 * the first few bytes in the buffer to hold the the address
638 * of the softc structure for this interface. This is because
639 * bge_jfree() needs it, but it is called by the mbuf management
640 * code which will not pass it to us explicitly.
642 ptr = sc->bge_cdata.bge_jumbo_buf;
643 for (i = 0; i < BGE_JSLOTS; i++) {
644 entry = &sc->bge_cdata.bge_jslots[i];
646 entry->bge_buf = ptr;
647 entry->bge_inuse = 0;
649 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
657 bge_free_jumbo_mem(struct bge_softc *sc)
659 if (sc->bge_cdata.bge_jumbo_buf)
660 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF);
664 * Allocate a jumbo buffer.
666 static struct bge_jslot *
667 bge_jalloc(struct bge_softc *sc)
669 struct bge_jslot *entry;
671 lwkt_serialize_enter(&sc->bge_jslot_serializer);
672 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
674 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
675 entry->bge_inuse = 1;
677 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
679 lwkt_serialize_exit(&sc->bge_jslot_serializer);
684 * Adjust usage count on a jumbo buffer.
689 struct bge_jslot *entry = (struct bge_jslot *)arg;
690 struct bge_softc *sc = entry->bge_sc;
693 panic("bge_jref: can't find softc pointer!");
695 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
696 panic("bge_jref: asked to reference buffer "
697 "that we don't manage!");
698 } else if (entry->bge_inuse == 0) {
699 panic("bge_jref: buffer already free!");
701 atomic_add_int(&entry->bge_inuse, 1);
706 * Release a jumbo buffer.
711 struct bge_jslot *entry = (struct bge_jslot *)arg;
712 struct bge_softc *sc = entry->bge_sc;
715 panic("bge_jfree: can't find softc pointer!");
717 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
718 panic("bge_jfree: asked to free buffer that we don't manage!");
719 } else if (entry->bge_inuse == 0) {
720 panic("bge_jfree: buffer already free!");
723 * Possible MP race to 0, use the serializer. The atomic insn
724 * is still needed for races against bge_jref().
726 lwkt_serialize_enter(&sc->bge_jslot_serializer);
727 atomic_subtract_int(&entry->bge_inuse, 1);
728 if (entry->bge_inuse == 0) {
729 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
732 lwkt_serialize_exit(&sc->bge_jslot_serializer);
738 * Intialize a standard receive ring descriptor.
741 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
743 struct mbuf *m_new = NULL;
747 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
750 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
753 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
754 m_new->m_data = m_new->m_ext.ext_buf;
757 if (!sc->bge_rx_alignment_bug)
758 m_adj(m_new, ETHER_ALIGN);
759 sc->bge_cdata.bge_rx_std_chain[i] = m_new;
760 r = &sc->bge_rdata->bge_rx_std_ring[i];
761 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t)));
762 r->bge_flags = BGE_RXBDFLAG_END;
763 r->bge_len = m_new->m_len;
770 * Initialize a jumbo receive ring descriptor. This allocates
771 * a jumbo buffer from the pool managed internally by the driver.
774 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
776 struct mbuf *m_new = NULL;
780 struct bge_jslot *buf;
782 /* Allocate the mbuf. */
783 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
787 /* Allocate the jumbo buffer */
788 buf = bge_jalloc(sc);
791 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
792 "-- packet dropped!\n");
796 /* Attach the buffer to the mbuf. */
797 m_new->m_ext.ext_arg = buf;
798 m_new->m_ext.ext_buf = buf->bge_buf;
799 m_new->m_ext.ext_free = bge_jfree;
800 m_new->m_ext.ext_ref = bge_jref;
801 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
803 m_new->m_data = m_new->m_ext.ext_buf;
804 m_new->m_flags |= M_EXT;
805 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
808 m_new->m_data = m_new->m_ext.ext_buf;
809 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
812 if (!sc->bge_rx_alignment_bug)
813 m_adj(m_new, ETHER_ALIGN);
814 /* Set up the descriptor. */
815 r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
816 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
817 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t)));
818 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
819 r->bge_len = m_new->m_len;
826 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
827 * that's 1MB or memory, which is a lot. For now, we fill only the first
828 * 256 ring entries and hope that our CPU is fast enough to keep up with
832 bge_init_rx_ring_std(struct bge_softc *sc)
836 for (i = 0; i < BGE_SSLOTS; i++) {
837 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
842 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
848 bge_free_rx_ring_std(struct bge_softc *sc)
852 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
853 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
854 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
855 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
857 bzero(&sc->bge_rdata->bge_rx_std_ring[i],
858 sizeof(struct bge_rx_bd));
863 bge_init_rx_ring_jumbo(struct bge_softc *sc)
868 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
869 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
873 sc->bge_jumbo = i - 1;
875 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
876 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
877 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
879 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
885 bge_free_rx_ring_jumbo(struct bge_softc *sc)
889 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
890 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
891 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
892 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
894 bzero(&sc->bge_rdata->bge_rx_jumbo_ring[i],
895 sizeof(struct bge_rx_bd));
900 bge_free_tx_ring(struct bge_softc *sc)
904 if (sc->bge_rdata->bge_tx_ring == NULL)
907 for (i = 0; i < BGE_TX_RING_CNT; i++) {
908 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
909 m_freem(sc->bge_cdata.bge_tx_chain[i]);
910 sc->bge_cdata.bge_tx_chain[i] = NULL;
912 bzero(&sc->bge_rdata->bge_tx_ring[i],
913 sizeof(struct bge_tx_bd));
918 bge_init_tx_ring(struct bge_softc *sc)
921 sc->bge_tx_saved_considx = 0;
923 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
925 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
926 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
928 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
930 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
931 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
937 bge_setmulti(struct bge_softc *sc)
940 struct ifmultiaddr *ifma;
941 uint32_t hashes[4] = { 0, 0, 0, 0 };
944 ifp = &sc->arpcom.ac_if;
946 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
947 for (i = 0; i < 4; i++)
948 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
952 /* First, zot all the existing filters. */
953 for (i = 0; i < 4; i++)
954 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
956 /* Now program new ones. */
957 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
958 if (ifma->ifma_addr->sa_family != AF_LINK)
961 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
962 ETHER_ADDR_LEN) & 0x7f;
963 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
966 for (i = 0; i < 4; i++)
967 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
971 * Do endian, PCI and DMA initialization. Also check the on-board ROM
975 bge_chipinit(struct bge_softc *sc)
980 /* Set endianness before we access any non-PCI registers. */
981 #if BYTE_ORDER == BIG_ENDIAN
982 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
983 BGE_BIGENDIAN_INIT, 4);
985 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
986 BGE_LITTLEENDIAN_INIT, 4);
990 * Check the 'ROM failed' bit on the RX CPU to see if
993 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
994 if_printf(&sc->arpcom.ac_if,
995 "RX CPU self-diagnostics failed!\n");
999 /* Clear the MAC control register */
1000 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1003 * Clear the MAC statistics block in the NIC's
1006 for (i = BGE_STATS_BLOCK;
1007 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1008 BGE_MEMWIN_WRITE(sc, i, 0);
1010 for (i = BGE_STATUS_BLOCK;
1011 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1012 BGE_MEMWIN_WRITE(sc, i, 0);
1014 /* Set up the PCI DMA control register. */
1017 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1018 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1019 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1020 } else if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1021 BGE_PCISTATE_PCI_BUSMODE) {
1022 /* Conventional PCI bus */
1023 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1024 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1025 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1030 * The 5704 uses a different encoding of read/write
1033 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1034 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1035 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1036 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1038 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1039 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1040 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1044 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1045 * for hardware bugs.
1047 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1048 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1051 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1052 if (tmp == 0x6 || tmp == 0x7)
1053 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1057 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1058 sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1059 sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1060 sc->bge_asicrev == BGE_ASICREV_BCM5750)
1061 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1062 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1065 * Set up general mode register.
1067 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|
1068 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1069 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1070 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM);
1073 * Disable memory write invalidate. Apparently it is not supported
1074 * properly by these devices.
1076 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1078 /* Set the timer prescaler (always 66Mhz) */
1079 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1085 bge_blockinit(struct bge_softc *sc)
1087 struct bge_rcb *rcb;
1088 volatile struct bge_rcb *vrcb;
1092 * Initialize the memory window pointer register so that
1093 * we can access the first 32K of internal NIC RAM. This will
1094 * allow us to set up the TX send ring RCBs and the RX return
1095 * ring RCBs, plus other things which live in NIC memory.
1097 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1099 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1101 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1102 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1103 /* Configure mbuf memory pool */
1104 if (sc->bge_extram) {
1105 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1107 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1108 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1110 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1112 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1114 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1115 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1117 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1120 /* Configure DMA resource pool */
1121 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1122 BGE_DMA_DESCRIPTORS);
1123 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1126 /* Configure mbuf pool watermarks */
1127 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1128 sc->bge_asicrev == BGE_ASICREV_BCM5750) {
1129 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1130 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1132 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1133 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1135 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1137 /* Configure DMA resource watermarks */
1138 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1139 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1141 /* Enable buffer manager */
1142 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1143 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1144 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1145 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1147 /* Poll for buffer manager start indication */
1148 for (i = 0; i < BGE_TIMEOUT; i++) {
1149 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1154 if (i == BGE_TIMEOUT) {
1155 if_printf(&sc->arpcom.ac_if,
1156 "buffer manager failed to start\n");
1161 /* Enable flow-through queues */
1162 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1163 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1165 /* Wait until queue initialization is complete */
1166 for (i = 0; i < BGE_TIMEOUT; i++) {
1167 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1172 if (i == BGE_TIMEOUT) {
1173 if_printf(&sc->arpcom.ac_if,
1174 "flow-through queue init failed\n");
1178 /* Initialize the standard RX ring control block */
1179 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
1180 BGE_HOSTADDR(rcb->bge_hostaddr,
1181 vtophys(&sc->bge_rdata->bge_rx_std_ring));
1182 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1183 sc->bge_asicrev == BGE_ASICREV_BCM5750)
1184 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1186 rcb->bge_maxlen_flags =
1187 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1189 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
1191 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1192 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1193 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1194 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1195 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1198 * Initialize the jumbo RX ring control block
1199 * We set the 'ring disabled' bit in the flags
1200 * field until we're actually ready to start
1201 * using this ring (i.e. once we set the MTU
1202 * high enough to require it).
1204 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1205 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1206 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
1207 BGE_HOSTADDR(rcb->bge_hostaddr,
1208 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring));
1209 rcb->bge_maxlen_flags =
1210 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1211 BGE_RCB_FLAG_RING_DISABLED);
1213 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
1215 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1216 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1217 rcb->bge_hostaddr.bge_addr_hi);
1218 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1219 rcb->bge_hostaddr.bge_addr_lo);
1220 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1221 rcb->bge_maxlen_flags);
1222 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1224 /* Set up dummy disabled mini ring RCB */
1225 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
1226 rcb->bge_maxlen_flags =
1227 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1228 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1229 rcb->bge_maxlen_flags);
1233 * Set the BD ring replentish thresholds. The recommended
1234 * values are 1/8th the number of descriptors allocated to
1237 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
1238 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1241 * Disable all unused send rings by setting the 'ring disabled'
1242 * bit in the flags field of all the TX send ring control blocks.
1243 * These are located in NIC memory.
1245 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1247 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1248 vrcb->bge_maxlen_flags =
1249 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1250 vrcb->bge_nicaddr = 0;
1254 /* Configure TX RCB 0 (we use only the first ring) */
1255 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1257 vrcb->bge_hostaddr.bge_addr_hi = 0;
1258 BGE_HOSTADDR(vrcb->bge_hostaddr, vtophys(&sc->bge_rdata->bge_tx_ring));
1259 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT);
1260 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1261 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1262 vrcb->bge_maxlen_flags =
1263 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0);
1265 /* Disable all unused RX return rings */
1266 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1267 BGE_RX_RETURN_RING_RCB);
1268 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1269 vrcb->bge_hostaddr.bge_addr_hi = 0;
1270 vrcb->bge_hostaddr.bge_addr_lo = 0;
1271 vrcb->bge_maxlen_flags =
1272 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1273 BGE_RCB_FLAG_RING_DISABLED);
1274 vrcb->bge_nicaddr = 0;
1275 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1276 (i * (sizeof(uint64_t))), 0);
1280 /* Initialize RX ring indexes */
1281 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1282 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1283 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1286 * Set up RX return ring 0
1287 * Note that the NIC address for RX return rings is 0x00000000.
1288 * The return rings live entirely within the host, so the
1289 * nicaddr field in the RCB isn't used.
1291 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1292 BGE_RX_RETURN_RING_RCB);
1293 vrcb->bge_hostaddr.bge_addr_hi = 0;
1294 BGE_HOSTADDR(vrcb->bge_hostaddr,
1295 vtophys(&sc->bge_rdata->bge_rx_return_ring));
1296 vrcb->bge_nicaddr = 0x00000000;
1297 vrcb->bge_maxlen_flags =
1298 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0);
1300 /* Set random backoff seed for TX */
1301 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1302 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1303 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1304 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1305 BGE_TX_BACKOFF_SEED_MASK);
1307 /* Set inter-packet gap */
1308 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1311 * Specify which ring to use for packets that don't match
1314 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1317 * Configure number of RX lists. One interrupt distribution
1318 * list, sixteen active lists, one bad frames class.
1320 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1322 /* Inialize RX list placement stats mask. */
1323 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1324 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1326 /* Disable host coalescing until we get it set up */
1327 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1329 /* Poll to make sure it's shut down. */
1330 for (i = 0; i < BGE_TIMEOUT; i++) {
1331 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1336 if (i == BGE_TIMEOUT) {
1337 if_printf(&sc->arpcom.ac_if,
1338 "host coalescing engine failed to idle\n");
1342 /* Set up host coalescing defaults */
1343 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1344 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1345 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1346 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1347 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1348 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1349 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1350 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1352 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
1353 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
1355 /* Set up address of statistics block */
1356 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1357 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1358 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0);
1359 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1360 vtophys(&sc->bge_rdata->bge_info.bge_stats));
1362 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1363 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1364 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1367 /* Set up address of status block */
1368 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0);
1369 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1370 vtophys(&sc->bge_rdata->bge_status_block));
1372 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
1373 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
1375 /* Turn on host coalescing state machine */
1376 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1378 /* Turn on RX BD completion state machine and enable attentions */
1379 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1380 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1382 /* Turn on RX list placement state machine */
1383 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1385 /* Turn on RX list selector state machine. */
1386 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1387 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1388 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1390 /* Turn on DMA, clear stats */
1391 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1392 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1393 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1394 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1395 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1397 /* Set misc. local control, enable interrupts on attentions */
1398 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1401 /* Assert GPIO pins for PHY reset */
1402 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1403 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1404 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1405 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1408 /* Turn on DMA completion state machine */
1409 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1410 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1411 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1413 /* Turn on write DMA state machine */
1414 CSR_WRITE_4(sc, BGE_WDMA_MODE,
1415 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
1417 /* Turn on read DMA state machine */
1418 CSR_WRITE_4(sc, BGE_RDMA_MODE,
1419 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1421 /* Turn on RX data completion state machine */
1422 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1424 /* Turn on RX BD initiator state machine */
1425 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1427 /* Turn on RX data and RX BD initiator state machine */
1428 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1430 /* Turn on Mbuf cluster free state machine */
1431 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1432 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1433 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1435 /* Turn on send BD completion state machine */
1436 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1438 /* Turn on send data completion state machine */
1439 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1441 /* Turn on send data initiator state machine */
1442 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1444 /* Turn on send BD initiator state machine */
1445 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1447 /* Turn on send BD selector state machine */
1448 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1450 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1451 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1452 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1454 /* ack/clear link change events */
1455 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1456 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1457 BGE_MACSTAT_LINK_CHANGED);
1459 /* Enable PHY auto polling (for MII/GMII only) */
1461 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1463 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1464 if (sc->bge_asicrev == BGE_ASICREV_BCM5700)
1465 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1466 BGE_EVTENB_MI_INTERRUPT);
1469 /* Enable link state change attentions. */
1470 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1476 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1477 * against our list and return its name if we find a match. Note
1478 * that since the Broadcom controller contains VPD support, we
1479 * can get the device name string from the controller itself instead
1480 * of the compiled-in string. This is a little slow, but it guarantees
1481 * we'll always announce the right product name.
1484 bge_probe(device_t dev)
1486 struct bge_softc *sc;
1489 uint16_t product, vendor;
1491 product = pci_get_device(dev);
1492 vendor = pci_get_vendor(dev);
1494 for (t = bge_devs; t->bge_name != NULL; t++) {
1495 if (vendor == t->bge_vid && product == t->bge_did)
1499 if (t->bge_name == NULL)
1502 sc = device_get_softc(dev);
1507 device_set_desc(dev, sc->bge_vpd_prodname);
1509 descbuf = kmalloc(BGE_DEVDESC_MAX, M_TEMP, M_WAITOK);
1510 ksnprintf(descbuf, BGE_DEVDESC_MAX, "%s, ASIC rev. %#04x", t->bge_name,
1511 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);
1512 device_set_desc_copy(dev, descbuf);
1513 if (pci_get_subvendor(dev) == PCI_VENDOR_DELL)
1514 sc->bge_no_3_led = 1;
1515 kfree(descbuf, M_TEMP);
1520 bge_attach(device_t dev)
1523 struct bge_softc *sc;
1525 uint32_t mac_addr = 0;
1527 uint8_t ether_addr[ETHER_ADDR_LEN];
1529 sc = device_get_softc(dev);
1531 callout_init(&sc->bge_stat_timer);
1532 lwkt_serialize_init(&sc->bge_jslot_serializer);
1535 * Map control/status registers.
1537 pci_enable_busmaster(dev);
1540 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1543 if (sc->bge_res == NULL) {
1544 device_printf(dev, "couldn't map memory\n");
1549 sc->bge_btag = rman_get_bustag(sc->bge_res);
1550 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1551 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res);
1553 /* Allocate interrupt */
1556 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1557 RF_SHAREABLE | RF_ACTIVE);
1559 if (sc->bge_irq == NULL) {
1560 device_printf(dev, "couldn't map interrupt\n");
1565 /* Save ASIC rev. */
1567 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1568 BGE_PCIMISCCTL_ASICREV;
1569 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1570 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1573 * Treat the 5714 and the 5752 like the 5750 until we have more info
1576 if (sc->bge_asicrev == BGE_ASICREV_BCM5714 ||
1577 sc->bge_asicrev == BGE_ASICREV_BCM5752)
1578 sc->bge_asicrev = BGE_ASICREV_BCM5750;
1581 * XXX: Broadcom Linux driver. Not in specs or eratta.
1584 if (sc->bge_asicrev == BGE_ASICREV_BCM5750) {
1587 v = pci_read_config(dev, BGE_PCI_MSI_CAPID, 4);
1588 if (((v >> 8) & 0xff) == BGE_PCIE_MSI_CAPID) {
1589 v = pci_read_config(dev, BGE_PCIE_MSI_CAPID, 4);
1590 if ((v & 0xff) == BGE_PCIE_MSI_CAPID_VAL)
1595 ifp = &sc->arpcom.ac_if;
1596 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1598 /* Try to reset the chip. */
1601 if (bge_chipinit(sc)) {
1602 device_printf(dev, "chip initialization failed\n");
1608 * Get station address from the EEPROM.
1610 mac_addr = bge_readmem_ind(sc, 0x0c14);
1611 if ((mac_addr >> 16) == 0x484b) {
1612 ether_addr[0] = (uint8_t)(mac_addr >> 8);
1613 ether_addr[1] = (uint8_t)mac_addr;
1614 mac_addr = bge_readmem_ind(sc, 0x0c18);
1615 ether_addr[2] = (uint8_t)(mac_addr >> 24);
1616 ether_addr[3] = (uint8_t)(mac_addr >> 16);
1617 ether_addr[4] = (uint8_t)(mac_addr >> 8);
1618 ether_addr[5] = (uint8_t)mac_addr;
1619 } else if (bge_read_eeprom(sc, ether_addr,
1620 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1621 device_printf(dev, "failed to read station address\n");
1626 /* Allocate the general information block and ring buffers. */
1627 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF,
1628 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
1630 if (sc->bge_rdata == NULL) {
1632 device_printf(dev, "no memory for list buffers!\n");
1636 bzero(sc->bge_rdata, sizeof(struct bge_ring_data));
1639 * Try to allocate memory for jumbo buffers.
1640 * The 5705/5750 does not appear to support jumbo frames.
1642 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1643 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1644 if (bge_alloc_jumbo_mem(sc)) {
1645 device_printf(dev, "jumbo buffer allocation failed\n");
1651 /* Set default tuneable values. */
1652 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1653 sc->bge_rx_coal_ticks = 150;
1654 sc->bge_tx_coal_ticks = 150;
1655 sc->bge_rx_max_coal_bds = 64;
1656 sc->bge_tx_max_coal_bds = 128;
1658 /* 5705/5750 limits RX return ring to 512 entries. */
1659 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1660 sc->bge_asicrev == BGE_ASICREV_BCM5750)
1661 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1663 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1665 /* Set up ifnet structure */
1667 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1668 ifp->if_ioctl = bge_ioctl;
1669 ifp->if_start = bge_start;
1670 ifp->if_watchdog = bge_watchdog;
1671 ifp->if_init = bge_init;
1672 ifp->if_mtu = ETHERMTU;
1673 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1674 ifq_set_ready(&ifp->if_snd);
1675 ifp->if_hwassist = BGE_CSUM_FEATURES;
1676 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
1678 ifp->if_capenable = ifp->if_capabilities;
1681 * Figure out what sort of media we have by checking the
1682 * hardware config word in the first 32k of NIC internal memory,
1683 * or fall back to examining the EEPROM if necessary.
1684 * Note: on some BCM5700 cards, this value appears to be unset.
1685 * If that's the case, we have to rely on identifying the NIC
1686 * by its PCI subsystem ID, as we do below for the SysKonnect
1689 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1690 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1692 bge_read_eeprom(sc, (caddr_t)&hwcfg,
1693 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg));
1694 hwcfg = ntohl(hwcfg);
1697 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1700 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1701 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
1705 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1706 bge_ifmedia_upd, bge_ifmedia_sts);
1707 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1708 ifmedia_add(&sc->bge_ifmedia,
1709 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1710 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1711 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1712 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
1715 * Do transceiver setup.
1717 if (mii_phy_probe(dev, &sc->bge_miibus,
1718 bge_ifmedia_upd, bge_ifmedia_sts)) {
1719 device_printf(dev, "MII without any PHY!\n");
1726 * When using the BCM5701 in PCI-X mode, data corruption has
1727 * been observed in the first few bytes of some received packets.
1728 * Aligning the packet buffer in memory eliminates the corruption.
1729 * Unfortunately, this misaligns the packet payloads. On platforms
1730 * which do not support unaligned accesses, we will realign the
1731 * payloads by copying the received packets.
1733 switch (sc->bge_chipid) {
1734 case BGE_CHIPID_BCM5701_A0:
1735 case BGE_CHIPID_BCM5701_B0:
1736 case BGE_CHIPID_BCM5701_B2:
1737 case BGE_CHIPID_BCM5701_B5:
1738 /* If in PCI-X mode, work around the alignment bug. */
1739 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
1740 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) ==
1741 BGE_PCISTATE_PCI_BUSSPEED)
1742 sc->bge_rx_alignment_bug = 1;
1747 * Call MI attach routine.
1749 ether_ifattach(ifp, ether_addr, NULL);
1751 error = bus_setup_intr(dev, sc->bge_irq, INTR_NETSAFE,
1752 bge_intr, sc, &sc->bge_intrhand,
1753 ifp->if_serializer);
1755 ether_ifdetach(ifp);
1756 device_printf(dev, "couldn't set up irq\n");
1769 bge_detach(device_t dev)
1771 struct bge_softc *sc = device_get_softc(dev);
1772 struct ifnet *ifp = &sc->arpcom.ac_if;
1774 if (device_is_attached(dev)) {
1775 lwkt_serialize_enter(ifp->if_serializer);
1778 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
1779 lwkt_serialize_exit(ifp->if_serializer);
1781 ether_ifdetach(ifp);
1784 ifmedia_removeall(&sc->bge_ifmedia);
1786 device_delete_child(dev, sc->bge_miibus);
1787 bus_generic_detach(dev);
1789 bge_release_resources(sc);
1791 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1792 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1793 bge_free_jumbo_mem(sc);
1799 bge_release_resources(struct bge_softc *sc)
1805 if (sc->bge_vpd_prodname != NULL)
1806 kfree(sc->bge_vpd_prodname, M_DEVBUF);
1808 if (sc->bge_vpd_readonly != NULL)
1809 kfree(sc->bge_vpd_readonly, M_DEVBUF);
1811 if (sc->bge_irq != NULL)
1812 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
1814 if (sc->bge_res != NULL)
1815 bus_release_resource(dev, SYS_RES_MEMORY,
1816 BGE_PCI_BAR0, sc->bge_res);
1818 if (sc->bge_rdata != NULL)
1819 contigfree(sc->bge_rdata, sizeof(struct bge_ring_data),
1826 bge_reset(struct bge_softc *sc)
1829 uint32_t cachesize, command, pcistate, reset;
1834 /* Save some important PCI state. */
1835 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
1836 command = pci_read_config(dev, BGE_PCI_CMD, 4);
1837 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
1839 pci_write_config(dev, BGE_PCI_MISC_CTL,
1840 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1841 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1843 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
1845 /* XXX: Broadcom Linux driver. */
1847 if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */
1848 CSR_WRITE_4(sc, 0x7e2c, 0x20);
1849 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
1850 /* Prevent PCIE link training during global reset */
1851 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
1856 /* Issue global reset */
1857 bge_writereg_ind(sc, BGE_MISC_CFG, reset);
1861 /* XXX: Broadcom Linux driver. */
1863 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
1866 DELAY(500000); /* wait for link training to complete */
1867 v = pci_read_config(dev, 0xc4, 4);
1868 pci_write_config(dev, 0xc4, v | (1<<15), 4);
1870 /* Set PCIE max payload size and clear error status. */
1871 pci_write_config(dev, 0xd8, 0xf5000, 4);
1874 /* Reset some of the PCI state that got zapped by reset */
1875 pci_write_config(dev, BGE_PCI_MISC_CTL,
1876 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1877 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1878 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
1879 pci_write_config(dev, BGE_PCI_CMD, command, 4);
1880 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
1882 /* Enable memory arbiter. */
1883 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1884 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
1887 * Prevent PXE restart: write a magic number to the
1888 * general communications memory at 0xB50.
1890 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1892 * Poll the value location we just wrote until
1893 * we see the 1's complement of the magic number.
1894 * This indicates that the firmware initialization
1897 for (i = 0; i < BGE_TIMEOUT; i++) {
1898 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
1899 if (val == ~BGE_MAGIC_NUMBER)
1904 if (i == BGE_TIMEOUT) {
1905 if_printf(&sc->arpcom.ac_if, "firmware handshake timed out\n");
1910 * XXX Wait for the value of the PCISTATE register to
1911 * return to its original pre-reset state. This is a
1912 * fairly good indicator of reset completion. If we don't
1913 * wait for the reset to fully complete, trying to read
1914 * from the device's non-PCI registers may yield garbage
1917 for (i = 0; i < BGE_TIMEOUT; i++) {
1918 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
1923 /* Fix up byte swapping */
1924 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME|
1925 BGE_MODECTL_BYTESWAP_DATA);
1927 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1930 * The 5704 in TBI mode apparently needs some special
1931 * adjustment to insure the SERDES drive level is set
1934 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && sc->bge_tbi) {
1937 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
1938 serdescfg = (serdescfg & ~0xFFF) | 0x880;
1939 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
1942 /* XXX: Broadcom Linux driver. */
1943 if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
1946 v = CSR_READ_4(sc, 0x7c00);
1947 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
1954 * Frame reception handling. This is called if there's a frame
1955 * on the receive return list.
1957 * Note: we have to be able to handle two possibilities here:
1958 * 1) the frame is from the jumbo recieve ring
1959 * 2) the frame is from the standard receive ring
1963 bge_rxeof(struct bge_softc *sc)
1966 int stdcnt = 0, jumbocnt = 0;
1968 ifp = &sc->arpcom.ac_if;
1970 while(sc->bge_rx_saved_considx !=
1971 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) {
1972 struct bge_rx_bd *cur_rx;
1974 struct mbuf *m = NULL;
1975 uint16_t vlan_tag = 0;
1979 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx];
1981 rxidx = cur_rx->bge_idx;
1982 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
1984 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
1986 vlan_tag = cur_rx->bge_vlan_tag;
1989 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
1990 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1991 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
1992 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
1994 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
1996 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
1999 if (bge_newbuf_jumbo(sc,
2000 sc->bge_jumbo, NULL) == ENOBUFS) {
2002 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2006 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2007 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2008 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2010 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2012 bge_newbuf_std(sc, sc->bge_std, m);
2015 if (bge_newbuf_std(sc, sc->bge_std,
2018 bge_newbuf_std(sc, sc->bge_std, m);
2026 * The i386 allows unaligned accesses, but for other
2027 * platforms we must make sure the payload is aligned.
2029 if (sc->bge_rx_alignment_bug) {
2030 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2032 m->m_data += ETHER_ALIGN;
2035 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2036 m->m_pkthdr.rcvif = ifp;
2038 #if 0 /* currently broken for some packets, possibly related to TCP options */
2039 if (ifp->if_hwassist) {
2040 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2041 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2042 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2043 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2044 m->m_pkthdr.csum_data =
2045 cur_rx->bge_tcp_udp_csum;
2046 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
2052 * If we received a packet with a vlan tag, pass it
2053 * to vlan_input() instead of ether_input().
2056 VLAN_INPUT_TAG(m, vlan_tag);
2057 have_tag = vlan_tag = 0;
2059 ifp->if_input(ifp, m);
2063 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2065 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2067 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2071 bge_txeof(struct bge_softc *sc)
2073 struct bge_tx_bd *cur_tx = NULL;
2076 ifp = &sc->arpcom.ac_if;
2079 * Go through our tx ring and free mbufs for those
2080 * frames that have been sent.
2082 while (sc->bge_tx_saved_considx !=
2083 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) {
2086 idx = sc->bge_tx_saved_considx;
2087 cur_tx = &sc->bge_rdata->bge_tx_ring[idx];
2088 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2090 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2091 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2092 sc->bge_cdata.bge_tx_chain[idx] = NULL;
2095 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2100 ifp->if_flags &= ~IFF_OACTIVE;
2106 struct bge_softc *sc = xsc;
2107 struct ifnet *ifp = &sc->arpcom.ac_if;
2108 uint32_t status, statusword, mimode;
2111 statusword = loadandclear(&sc->bge_rdata->bge_status_block.bge_status);
2114 /* Avoid this for now -- checking this register is expensive. */
2115 /* Make sure this is really our interrupt. */
2116 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE))
2119 /* Ack interrupt and stop others from occuring. */
2120 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2123 * Process link state changes.
2124 * Grrr. The link status word in the status block does
2125 * not work correctly on the BCM5700 rev AX and BX chips,
2126 * according to all available information. Hence, we have
2127 * to enable MII interrupts in order to properly obtain
2128 * async link changes. Unfortunately, this also means that
2129 * we have to read the MAC status register to detect link
2130 * changes, thereby adding an additional register access to
2131 * the interrupt handler.
2134 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) {
2135 status = CSR_READ_4(sc, BGE_MAC_STS);
2136 if (status & BGE_MACSTAT_MI_INTERRUPT) {
2138 callout_stop(&sc->bge_stat_timer);
2139 bge_tick_serialized(sc);
2140 /* Clear the interrupt */
2141 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2142 BGE_EVTENB_MI_INTERRUPT);
2143 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
2144 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
2148 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) {
2150 * Sometimes PCS encoding errors are detected in
2151 * TBI mode (on fiber NICs), and for some reason
2152 * the chip will signal them as link changes.
2153 * If we get a link change event, but the 'PCS
2154 * encoding error' bit in the MAC status register
2155 * is set, don't bother doing a link check.
2156 * This avoids spurious "gigabit link up" messages
2157 * that sometimes appear on fiber NICs during
2158 * periods of heavy traffic. (There should be no
2159 * effect on copper NICs.)
2161 * If we do have a copper NIC (bge_tbi == 0) then
2162 * check that the AUTOPOLL bit is set before
2163 * processing the event as a real link change.
2164 * Turning AUTOPOLL on and off in the MII read/write
2165 * functions will often trigger a link status
2166 * interrupt for no reason.
2168 status = CSR_READ_4(sc, BGE_MAC_STS);
2169 mimode = CSR_READ_4(sc, BGE_MI_MODE);
2170 if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR |
2171 BGE_MACSTAT_MI_COMPLETE)) &&
2172 (!sc->bge_tbi && (mimode & BGE_MIMODE_AUTOPOLL))) {
2174 callout_stop(&sc->bge_stat_timer);
2175 bge_tick_serialized(sc);
2178 callout_stop(&sc->bge_stat_timer);
2179 bge_tick_serialized(sc);
2180 /* Clear the interrupt */
2181 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
2182 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
2183 BGE_MACSTAT_LINK_CHANGED);
2185 /* Force flush the status block cached by PCI bridge */
2186 CSR_READ_4(sc, BGE_MBX_IRQ0_LO);
2190 if (ifp->if_flags & IFF_RUNNING) {
2191 /* Check RX return ring producer/consumer */
2194 /* Check TX ring producer/consumer */
2198 bge_handle_events(sc);
2200 /* Re-enable interrupts. */
2201 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2203 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
2204 (*ifp->if_start)(ifp);
2210 struct bge_softc *sc = xsc;
2211 struct ifnet *ifp = &sc->arpcom.ac_if;
2213 lwkt_serialize_enter(ifp->if_serializer);
2214 bge_tick_serialized(xsc);
2215 lwkt_serialize_exit(ifp->if_serializer);
2219 bge_tick_serialized(void *xsc)
2221 struct bge_softc *sc = xsc;
2222 struct ifnet *ifp = &sc->arpcom.ac_if;
2223 struct mii_data *mii = NULL;
2224 struct ifmedia *ifm = NULL;
2226 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
2227 sc->bge_asicrev == BGE_ASICREV_BCM5750)
2228 bge_stats_update_regs(sc);
2230 bge_stats_update(sc);
2232 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2239 ifm = &sc->bge_ifmedia;
2240 if (CSR_READ_4(sc, BGE_MAC_STS) &
2241 BGE_MACSTAT_TBI_PCS_SYNCHED) {
2243 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2244 BGE_CLRBIT(sc, BGE_MAC_MODE,
2245 BGE_MACMODE_TBI_SEND_CFGS);
2247 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
2248 if_printf(ifp, "gigabit link up\n");
2249 if (!ifq_is_empty(&ifp->if_snd))
2250 (*ifp->if_start)(ifp);
2255 mii = device_get_softc(sc->bge_miibus);
2258 if (!sc->bge_link) {
2260 if (mii->mii_media_status & IFM_ACTIVE &&
2261 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2263 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
2264 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
2265 if_printf(ifp, "gigabit link up\n");
2266 if (!ifq_is_empty(&ifp->if_snd))
2267 (*ifp->if_start)(ifp);
2273 bge_stats_update_regs(struct bge_softc *sc)
2275 struct ifnet *ifp = &sc->arpcom.ac_if;
2276 struct bge_mac_stats_regs stats;
2280 s = (uint32_t *)&stats;
2281 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2282 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2286 ifp->if_collisions +=
2287 (stats.dot3StatsSingleCollisionFrames +
2288 stats.dot3StatsMultipleCollisionFrames +
2289 stats.dot3StatsExcessiveCollisions +
2290 stats.dot3StatsLateCollisions) -
2295 bge_stats_update(struct bge_softc *sc)
2297 struct ifnet *ifp = &sc->arpcom.ac_if;
2298 struct bge_stats *stats;
2300 stats = (struct bge_stats *)(sc->bge_vhandle +
2301 BGE_MEMWIN_START + BGE_STATS_BLOCK);
2303 ifp->if_collisions +=
2304 (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo +
2305 stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo +
2306 stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo +
2307 stats->txstats.dot3StatsLateCollisions.bge_addr_lo) -
2311 ifp->if_collisions +=
2312 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2313 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2314 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2315 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2321 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2322 * pointers to descriptors.
2325 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
2327 struct bge_tx_bd *f = NULL;
2329 uint32_t frag, cur, cnt = 0;
2330 uint16_t csum_flags = 0;
2331 struct ifvlan *ifv = NULL;
2333 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2334 m_head->m_pkthdr.rcvif != NULL &&
2335 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2336 ifv = m_head->m_pkthdr.rcvif->if_softc;
2339 cur = frag = *txidx;
2341 if (m_head->m_pkthdr.csum_flags) {
2342 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2343 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2344 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2345 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2346 if (m_head->m_flags & M_LASTFRAG)
2347 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2348 else if (m_head->m_flags & M_FRAG)
2349 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2352 * Start packing the mbufs in this chain into
2353 * the fragment pointers. Stop when we run out
2354 * of fragments or hit the end of the mbuf chain.
2356 for (m = m_head; m != NULL; m = m->m_next) {
2357 if (m->m_len != 0) {
2358 f = &sc->bge_rdata->bge_tx_ring[frag];
2359 if (sc->bge_cdata.bge_tx_chain[frag] != NULL)
2361 BGE_HOSTADDR(f->bge_addr,
2362 vtophys(mtod(m, vm_offset_t)));
2363 f->bge_len = m->m_len;
2364 f->bge_flags = csum_flags;
2366 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2367 f->bge_vlan_tag = ifv->ifv_tag;
2369 f->bge_vlan_tag = 0;
2372 * Sanity check: avoid coming within 16 descriptors
2373 * of the end of the ring.
2375 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16)
2378 BGE_INC(frag, BGE_TX_RING_CNT);
2386 if (frag == sc->bge_tx_saved_considx)
2389 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END;
2390 sc->bge_cdata.bge_tx_chain[cur] = m_head;
2391 sc->bge_txcnt += cnt;
2399 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2400 * to the mbuf data regions directly in the transmit descriptors.
2403 bge_start(struct ifnet *ifp)
2405 struct bge_softc *sc;
2406 struct mbuf *m_head = NULL;
2407 uint32_t prodidx = 0;
2415 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO);
2418 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2419 m_head = ifq_poll(&ifp->if_snd);
2425 * safety overkill. If this is a fragmented packet chain
2426 * with delayed TCP/UDP checksums, then only encapsulate
2427 * it if we have enough descriptors to handle the entire
2429 * (paranoia -- may not actually be needed)
2431 if (m_head->m_flags & M_FIRSTFRAG &&
2432 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2433 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2434 m_head->m_pkthdr.csum_data + 16) {
2435 ifp->if_flags |= IFF_OACTIVE;
2441 * Pack the data into the transmit ring. If we
2442 * don't have room, set the OACTIVE flag and wait
2443 * for the NIC to drain the ring.
2445 if (bge_encap(sc, m_head, &prodidx)) {
2446 ifp->if_flags |= IFF_OACTIVE;
2449 ifq_dequeue(&ifp->if_snd, m_head);
2452 BPF_MTAP(ifp, m_head);
2459 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2460 /* 5700 b2 errata */
2461 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2462 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2465 * Set a timeout in case the chip goes out to lunch.
2473 struct bge_softc *sc = xsc;
2474 struct ifnet *ifp = &sc->arpcom.ac_if;
2477 ASSERT_SERIALIZED(ifp->if_serializer);
2479 if (ifp->if_flags & IFF_RUNNING)
2482 /* Cancel pending I/O and flush buffers. */
2488 * Init the various state machines, ring
2489 * control blocks and firmware.
2491 if (bge_blockinit(sc)) {
2492 if_printf(ifp, "initialization failure\n");
2497 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2498 ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2500 /* Load our MAC address. */
2501 m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2502 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2503 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2505 /* Enable or disable promiscuous mode as needed. */
2508 /* Program multicast filter. */
2512 bge_init_rx_ring_std(sc);
2515 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2516 * memory to insure that the chip has in fact read the first
2517 * entry of the ring.
2519 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
2521 for (i = 0; i < 10; i++) {
2523 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
2524 if (v == (MCLBYTES - ETHER_ALIGN))
2528 if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
2531 /* Init jumbo RX ring. */
2532 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2533 bge_init_rx_ring_jumbo(sc);
2535 /* Init our RX return ring index */
2536 sc->bge_rx_saved_considx = 0;
2539 bge_init_tx_ring(sc);
2541 /* Turn on transmitter */
2542 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2544 /* Turn on receiver */
2545 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2547 /* Tell firmware we're alive. */
2548 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2550 /* Enable host interrupts. */
2551 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2552 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2553 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2555 bge_ifmedia_upd(ifp);
2557 ifp->if_flags |= IFF_RUNNING;
2558 ifp->if_flags &= ~IFF_OACTIVE;
2560 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2564 * Set media options.
2567 bge_ifmedia_upd(struct ifnet *ifp)
2569 struct bge_softc *sc = ifp->if_softc;
2570 struct ifmedia *ifm = &sc->bge_ifmedia;
2571 struct mii_data *mii;
2573 /* If this is a 1000baseX NIC, enable the TBI port. */
2575 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2577 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2580 * The BCM5704 ASIC appears to have a special
2581 * mechanism for programming the autoneg
2582 * advertisement registers in TBI mode.
2584 if (!bge_fake_autoneg &&
2585 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2588 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
2589 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
2590 sgdig |= BGE_SGDIGCFG_AUTO |
2591 BGE_SGDIGCFG_PAUSE_CAP |
2592 BGE_SGDIGCFG_ASYM_PAUSE;
2593 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
2594 sgdig | BGE_SGDIGCFG_SEND);
2596 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
2600 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2601 BGE_CLRBIT(sc, BGE_MAC_MODE,
2602 BGE_MACMODE_HALF_DUPLEX);
2604 BGE_SETBIT(sc, BGE_MAC_MODE,
2605 BGE_MACMODE_HALF_DUPLEX);
2614 mii = device_get_softc(sc->bge_miibus);
2616 if (mii->mii_instance) {
2617 struct mii_softc *miisc;
2618 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2619 mii_phy_reset(miisc);
2627 * Report current media status.
2630 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2632 struct bge_softc *sc = ifp->if_softc;
2633 struct mii_data *mii;
2636 ifmr->ifm_status = IFM_AVALID;
2637 ifmr->ifm_active = IFM_ETHER;
2638 if (CSR_READ_4(sc, BGE_MAC_STS) &
2639 BGE_MACSTAT_TBI_PCS_SYNCHED)
2640 ifmr->ifm_status |= IFM_ACTIVE;
2641 ifmr->ifm_active |= IFM_1000_SX;
2642 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
2643 ifmr->ifm_active |= IFM_HDX;
2645 ifmr->ifm_active |= IFM_FDX;
2649 mii = device_get_softc(sc->bge_miibus);
2651 ifmr->ifm_active = mii->mii_media_active;
2652 ifmr->ifm_status = mii->mii_media_status;
2656 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2658 struct bge_softc *sc = ifp->if_softc;
2659 struct ifreq *ifr = (struct ifreq *) data;
2660 int mask, error = 0;
2661 struct mii_data *mii;
2663 ASSERT_SERIALIZED(ifp->if_serializer);
2667 /* Disallow jumbo frames on 5705/5750. */
2668 if (((sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
2669 sc->bge_asicrev == BGE_ASICREV_BCM5750) &&
2670 ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU)
2673 ifp->if_mtu = ifr->ifr_mtu;
2674 ifp->if_flags &= ~IFF_RUNNING;
2679 if (ifp->if_flags & IFF_UP) {
2680 if (ifp->if_flags & IFF_RUNNING) {
2681 int flags = ifp->if_flags & sc->bge_if_flags;
2684 * If only the state of the PROMISC flag
2685 * changed, then just use the 'set promisc
2686 * mode' command instead of reinitializing
2687 * the entire NIC. Doing a full re-init
2688 * means reloading the firmware and waiting
2689 * for it to start up, which may take a
2690 * second or two. Similarly for ALLMULTI.
2692 if (flags & IFF_PROMISC)
2694 if (flags & IFF_ALLMULTI)
2700 if (ifp->if_flags & IFF_RUNNING)
2703 sc->bge_if_flags = ifp->if_flags;
2708 if (ifp->if_flags & IFF_RUNNING) {
2716 error = ifmedia_ioctl(ifp, ifr,
2717 &sc->bge_ifmedia, command);
2719 mii = device_get_softc(sc->bge_miibus);
2720 error = ifmedia_ioctl(ifp, ifr,
2721 &mii->mii_media, command);
2725 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2726 if (mask & IFCAP_HWCSUM) {
2727 if (IFCAP_HWCSUM & ifp->if_capenable)
2728 ifp->if_capenable &= ~IFCAP_HWCSUM;
2730 ifp->if_capenable |= IFCAP_HWCSUM;
2735 error = ether_ioctl(ifp, command, data);
2742 bge_watchdog(struct ifnet *ifp)
2744 struct bge_softc *sc = ifp->if_softc;
2746 if_printf(ifp, "watchdog timeout -- resetting\n");
2748 ifp->if_flags &= ~IFF_RUNNING;
2753 if (!ifq_is_empty(&ifp->if_snd))
2758 * Stop the adapter and free any mbufs allocated to the
2762 bge_stop(struct bge_softc *sc)
2764 struct ifnet *ifp = &sc->arpcom.ac_if;
2765 struct ifmedia_entry *ifm;
2766 struct mii_data *mii = NULL;
2769 ASSERT_SERIALIZED(ifp->if_serializer);
2772 mii = device_get_softc(sc->bge_miibus);
2774 callout_stop(&sc->bge_stat_timer);
2777 * Disable all of the receiver blocks
2779 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2780 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2781 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2782 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2783 sc->bge_asicrev != BGE_ASICREV_BCM5750)
2784 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2785 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
2786 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2787 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
2790 * Disable all of the transmit blocks
2792 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2793 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2794 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2795 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
2796 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
2797 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2798 sc->bge_asicrev != BGE_ASICREV_BCM5750)
2799 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2800 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2803 * Shut down all of the memory managers and related
2806 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
2807 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
2808 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2809 sc->bge_asicrev != BGE_ASICREV_BCM5750)
2810 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2811 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2812 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2813 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2814 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
2815 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
2816 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2819 /* Disable host interrupts. */
2820 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2821 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2824 * Tell firmware we're shutting down.
2826 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2828 /* Free the RX lists. */
2829 bge_free_rx_ring_std(sc);
2831 /* Free jumbo RX list. */
2832 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2833 sc->bge_asicrev != BGE_ASICREV_BCM5750)
2834 bge_free_rx_ring_jumbo(sc);
2836 /* Free TX buffers. */
2837 bge_free_tx_ring(sc);
2840 * Isolate/power down the PHY, but leave the media selection
2841 * unchanged so that things will be put back to normal when
2842 * we bring the interface back up.
2845 itmp = ifp->if_flags;
2846 ifp->if_flags |= IFF_UP;
2847 ifm = mii->mii_media.ifm_cur;
2848 mtmp = ifm->ifm_media;
2849 ifm->ifm_media = IFM_ETHER|IFM_NONE;
2851 ifm->ifm_media = mtmp;
2852 ifp->if_flags = itmp;
2857 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
2859 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2863 * Stop all chip I/O so that the kernel's probe routines don't
2864 * get confused by errant DMAs when rebooting.
2867 bge_shutdown(device_t dev)
2869 struct bge_softc *sc = device_get_softc(dev);
2870 struct ifnet *ifp = &sc->arpcom.ac_if;
2872 lwkt_serialize_enter(ifp->if_serializer);
2875 lwkt_serialize_exit(ifp->if_serializer);
2879 bge_suspend(device_t dev)
2881 struct bge_softc *sc = device_get_softc(dev);
2882 struct ifnet *ifp = &sc->arpcom.ac_if;
2884 lwkt_serialize_enter(ifp->if_serializer);
2886 lwkt_serialize_exit(ifp->if_serializer);
2892 bge_resume(device_t dev)
2894 struct bge_softc *sc = device_get_softc(dev);
2895 struct ifnet *ifp = &sc->arpcom.ac_if;
2897 lwkt_serialize_enter(ifp->if_serializer);
2899 if (ifp->if_flags & IFF_UP) {
2902 if (ifp->if_flags & IFF_RUNNING)
2906 lwkt_serialize_exit(ifp->if_serializer);
2912 bge_setpromisc(struct bge_softc *sc)
2914 struct ifnet *ifp = &sc->arpcom.ac_if;
2916 if (ifp->if_flags & IFF_PROMISC)
2917 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2919 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);