2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
3 * and Duncan Barclay<dmlb@dmlb.org>
4 * Modifications for FreeBSD-stable by Edwin Groothuis
5 * <edwin at mavetju.org
6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v
32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.40 2008/09/17 08:51:29 sephe Exp $
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sockio.h>
39 #include <sys/malloc.h>
40 #include <sys/interrupt.h>
41 #include <sys/kernel.h>
42 #include <sys/socket.h>
43 #include <sys/queue.h>
46 #include <sys/thread2.h>
49 #include <net/ifq_var.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
57 #include <net/if_types.h>
58 #include <net/vlan/if_vlan_var.h>
60 #include <netinet/in_systm.h>
61 #include <netinet/in.h>
62 #include <netinet/ip.h>
64 #include <bus/pci/pcireg.h>
65 #include <bus/pci/pcivar.h>
66 #include <bus/pci/pcidevs.h>
68 #include <dev/netif/mii_layer/mii.h>
69 #include <dev/netif/mii_layer/miivar.h>
71 #include <dev/netif/bfe/if_bfereg.h>
73 MODULE_DEPEND(bfe, pci, 1, 1, 1);
74 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
76 /* "controller miibus0" required. See GENERIC if you get errors here. */
77 #include "miibus_if.h"
79 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */
81 static struct bfe_type bfe_devs[] = {
82 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401,
83 "Broadcom BCM4401 Fast Ethernet" },
84 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0,
85 "Broadcom BCM4401-B0 Fast Ethernet" },
86 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4402,
87 "Broadcom BCM4402 Fast Ethernet" },
91 static int bfe_probe(device_t);
92 static int bfe_attach(device_t);
93 static int bfe_detach(device_t);
94 static void bfe_intr(void *);
95 static void bfe_start(struct ifnet *);
96 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
97 static void bfe_init(void *);
98 static void bfe_stop(struct bfe_softc *);
99 static void bfe_watchdog(struct ifnet *);
100 static void bfe_shutdown(device_t);
101 static void bfe_tick(void *);
102 static void bfe_txeof(struct bfe_softc *);
103 static void bfe_rxeof(struct bfe_softc *);
104 static void bfe_set_rx_mode(struct bfe_softc *);
105 static int bfe_list_rx_init(struct bfe_softc *);
106 static int bfe_list_newbuf(struct bfe_softc *, int, struct mbuf*);
107 static void bfe_rx_ring_free(struct bfe_softc *);
109 static void bfe_pci_setup(struct bfe_softc *, uint32_t);
110 static int bfe_ifmedia_upd(struct ifnet *);
111 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
112 static int bfe_miibus_readreg(device_t, int, int);
113 static int bfe_miibus_writereg(device_t, int, int, int);
114 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t,
116 static void bfe_get_config(struct bfe_softc *sc);
117 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *);
118 static void bfe_stats_update(struct bfe_softc *);
119 static void bfe_clear_stats (struct bfe_softc *);
120 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*);
121 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t);
122 static int bfe_resetphy(struct bfe_softc *);
123 static int bfe_setupphy(struct bfe_softc *);
124 static void bfe_chip_reset(struct bfe_softc *);
125 static void bfe_chip_halt(struct bfe_softc *);
126 static void bfe_core_reset(struct bfe_softc *);
127 static void bfe_core_disable(struct bfe_softc *);
128 static int bfe_dma_alloc(device_t);
129 static void bfe_dma_free(struct bfe_softc *);
130 static void bfe_dma_map_desc(void *, bus_dma_segment_t *, int, int);
131 static void bfe_dma_map(void *, bus_dma_segment_t *, int, int);
132 static void bfe_cam_write(struct bfe_softc *, u_char *, int);
134 static device_method_t bfe_methods[] = {
135 /* Device interface */
136 DEVMETHOD(device_probe, bfe_probe),
137 DEVMETHOD(device_attach, bfe_attach),
138 DEVMETHOD(device_detach, bfe_detach),
139 DEVMETHOD(device_shutdown, bfe_shutdown),
142 DEVMETHOD(bus_print_child, bus_generic_print_child),
143 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
146 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
147 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
152 static driver_t bfe_driver = {
155 sizeof(struct bfe_softc)
158 static devclass_t bfe_devclass;
160 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
161 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
164 * Probe for a Broadcom 4401 chip.
167 bfe_probe(device_t dev)
170 uint16_t vendor, product;
172 vendor = pci_get_vendor(dev);
173 product = pci_get_device(dev);
175 for (t = bfe_devs; t->bfe_name != NULL; t++) {
176 if (vendor == t->bfe_vid && product == t->bfe_did) {
177 device_set_desc(dev, t->bfe_name);
186 bfe_dma_alloc(device_t dev)
188 struct bfe_softc *sc = device_get_softc(dev);
189 int error, i, tx_pos, rx_pos;
192 * parent tag. Apparently the chip cannot handle any DMA address
195 error = bus_dma_tag_create(NULL, /* parent */
196 4096, 0, /* alignment, boundary */
197 0x3FFFFFFF, /* lowaddr */
198 BUS_SPACE_MAXADDR, /* highaddr */
199 NULL, NULL, /* filter, filterarg */
200 MAXBSIZE, /* maxsize */
201 BUS_SPACE_UNRESTRICTED, /* num of segments */
202 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */
204 &sc->bfe_parent_tag);
206 device_printf(dev, "could not allocate parent dma tag\n");
210 /* tag for TX ring */
211 error = bus_dma_tag_create(sc->bfe_parent_tag, 4096, 0,
212 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
215 BUS_SPACE_MAXSIZE_32BIT,
218 device_printf(dev, "could not allocate dma tag for TX list\n");
222 /* tag for RX ring */
223 error = bus_dma_tag_create(sc->bfe_parent_tag, 4096, 0,
224 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
227 BUS_SPACE_MAXSIZE_32BIT,
230 device_printf(dev, "could not allocate dma tag for RX list\n");
235 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0,
236 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
238 MCLBYTES, 1, BUS_SPACE_MAXSIZE_32BIT,
239 BUS_DMA_ALLOCNOW, &sc->bfe_tag);
241 device_printf(dev, "could not allocate dma tag for mbufs\n");
247 /* pre allocate dmamaps for RX list */
248 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
249 error = bus_dmamap_create(sc->bfe_tag, 0,
250 &sc->bfe_rx_ring[i].bfe_map);
253 device_printf(dev, "cannot create DMA map for RX\n");
257 rx_pos = BFE_RX_LIST_CNT;
259 /* pre allocate dmamaps for TX list */
260 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
261 error = bus_dmamap_create(sc->bfe_tag, 0,
262 &sc->bfe_tx_ring[i].bfe_map);
265 device_printf(dev, "cannot create DMA map for TX\n");
270 /* Alloc dma for rx ring */
271 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
272 BUS_DMA_WAITOK | BUS_DMA_ZERO,
275 device_printf(dev, "cannot allocate DMA mem for RX\n");
279 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
280 sc->bfe_rx_list, sizeof(struct bfe_desc),
281 bfe_dma_map, &sc->bfe_rx_dma, BUS_DMA_WAITOK);
283 device_printf(dev, "cannot load DMA map for RX\n");
287 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
289 /* Alloc dma for tx ring */
290 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
291 BUS_DMA_WAITOK | BUS_DMA_ZERO,
294 device_printf(dev, "cannot allocate DMA mem for TX\n");
298 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
299 sc->bfe_tx_list, sizeof(struct bfe_desc),
300 bfe_dma_map, &sc->bfe_tx_dma, BUS_DMA_WAITOK);
302 device_printf(dev, "cannot load DMA map for TX\n");
306 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE);
311 for (i = 0; i < rx_pos; ++i)
312 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_rx_ring[i].bfe_map);
313 for (i = 0; i < tx_pos; ++i)
314 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_tx_ring[i].bfe_map);
316 bus_dma_tag_destroy(sc->bfe_tag);
322 bfe_attach(device_t dev)
325 struct bfe_softc *sc;
328 sc = device_get_softc(dev);
331 callout_init(&sc->bfe_stat_timer);
335 * Handle power management nonsense.
337 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
338 uint32_t membase, irq;
340 /* Save important PCI config data. */
341 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4);
342 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4);
344 /* Reset the power state. */
345 device_printf(dev, "chip is in D%d power mode"
346 " -- setting to D0\n", pci_get_powerstate(dev));
348 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
350 /* Restore PCI config data. */
351 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4);
352 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4);
354 #endif /* !BURN_BRIDGE */
357 * Map control/status registers.
359 pci_enable_busmaster(dev);
362 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
364 if (sc->bfe_res == NULL) {
365 device_printf(dev, "couldn't map memory\n");
369 sc->bfe_btag = rman_get_bustag(sc->bfe_res);
370 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res);
372 /* Allocate interrupt */
375 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
376 RF_SHAREABLE | RF_ACTIVE);
377 if (sc->bfe_irq == NULL) {
378 device_printf(dev, "couldn't map interrupt\n");
383 error = bfe_dma_alloc(dev);
385 device_printf(dev, "failed to allocate DMA resources\n");
389 /* Set up ifnet structure */
390 ifp = &sc->arpcom.ac_if;
392 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
393 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
394 ifp->if_ioctl = bfe_ioctl;
395 ifp->if_start = bfe_start;
396 ifp->if_watchdog = bfe_watchdog;
397 ifp->if_init = bfe_init;
398 ifp->if_mtu = ETHERMTU;
399 ifp->if_baudrate = 100000000;
400 ifp->if_capabilities |= IFCAP_VLAN_MTU;
401 ifp->if_capenable |= IFCAP_VLAN_MTU;
402 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
403 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN);
404 ifq_set_ready(&ifp->if_snd);
408 /* Reset the chip and turn on the PHY */
411 if (mii_phy_probe(dev, &sc->bfe_miibus,
412 bfe_ifmedia_upd, bfe_ifmedia_sts)) {
413 device_printf(dev, "MII without any PHY!\n");
418 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
421 * Hook interrupt last to avoid having to lock softc
423 error = bus_setup_intr(dev, sc->bfe_irq, INTR_MPSAFE,
424 bfe_intr, sc, &sc->bfe_intrhand,
425 sc->arpcom.ac_if.if_serializer);
429 device_printf(dev, "couldn't set up irq\n");
433 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bfe_irq));
434 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
442 bfe_detach(device_t dev)
444 struct bfe_softc *sc = device_get_softc(dev);
445 struct ifnet *ifp = &sc->arpcom.ac_if;
447 if (device_is_attached(dev)) {
448 lwkt_serialize_enter(ifp->if_serializer);
451 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand);
452 lwkt_serialize_exit(ifp->if_serializer);
456 if (sc->bfe_miibus != NULL)
457 device_delete_child(dev, sc->bfe_miibus);
458 bus_generic_detach(dev);
460 if (sc->bfe_irq != NULL)
461 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq);
463 if (sc->bfe_res != NULL) {
464 bus_release_resource(dev, SYS_RES_MEMORY, BFE_PCI_MEMLO,
473 * Stop all chip I/O so that the kernel's probe routines don't
474 * get confused by errant DMAs when rebooting.
477 bfe_shutdown(device_t dev)
479 struct bfe_softc *sc = device_get_softc(dev);
480 struct ifnet *ifp = &sc->arpcom.ac_if;
482 lwkt_serialize_enter(ifp->if_serializer);
484 lwkt_serialize_exit(ifp->if_serializer);
488 bfe_miibus_readreg(device_t dev, int phy, int reg)
490 struct bfe_softc *sc;
493 sc = device_get_softc(dev);
494 if (phy != sc->bfe_phyaddr)
496 bfe_readphy(sc, reg, &ret);
502 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
504 struct bfe_softc *sc;
506 sc = device_get_softc(dev);
507 if (phy != sc->bfe_phyaddr)
509 bfe_writephy(sc, reg, val);
515 bfe_tx_ring_free(struct bfe_softc *sc)
519 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
520 bus_dmamap_unload(sc->bfe_tag,
521 sc->bfe_tx_ring[i].bfe_map);
522 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
523 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
524 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
527 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
528 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE);
532 bfe_rx_ring_free(struct bfe_softc *sc)
536 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
537 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
538 bus_dmamap_unload(sc->bfe_tag,
539 sc->bfe_rx_ring[i].bfe_map);
540 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
541 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
544 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
545 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
549 bfe_list_rx_init(struct bfe_softc *sc)
553 for (i = 0; i < BFE_RX_LIST_CNT; i++)
554 if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS)
557 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
558 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
566 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m)
568 struct bfe_rxheader *rx_header;
573 if ((c < 0) || (c >= BFE_RX_LIST_CNT))
577 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
580 m->m_len = m->m_pkthdr.len = MCLBYTES;
583 m->m_data = m->m_ext.ext_buf;
585 rx_header = mtod(m, struct bfe_rxheader *);
587 rx_header->flags = 0;
589 /* Map the mbuf into DMA */
591 d = &sc->bfe_rx_list[c];
592 r = &sc->bfe_rx_ring[c];
594 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *),
595 MCLBYTES, bfe_dma_map_desc, d, BUS_DMA_NOWAIT);
596 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE);
598 ctrl = ETHER_MAX_LEN + 32;
600 if(c == BFE_RX_LIST_CNT - 1)
601 ctrl |= BFE_DESC_EOT;
605 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
610 bfe_get_config(struct bfe_softc *sc)
614 bfe_read_eeprom(sc, eeprom);
616 sc->arpcom.ac_enaddr[0] = eeprom[79];
617 sc->arpcom.ac_enaddr[1] = eeprom[78];
618 sc->arpcom.ac_enaddr[2] = eeprom[81];
619 sc->arpcom.ac_enaddr[3] = eeprom[80];
620 sc->arpcom.ac_enaddr[4] = eeprom[83];
621 sc->arpcom.ac_enaddr[5] = eeprom[82];
623 sc->bfe_phyaddr = eeprom[90] & 0x1f;
624 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
626 sc->bfe_core_unit = 0;
627 sc->bfe_dma_offset = BFE_PCI_DMA;
631 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores)
633 uint32_t bar_orig, pci_rev, val;
635 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
636 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
637 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
639 val = CSR_READ_4(sc, BFE_SBINTVEC);
641 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
643 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
644 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
645 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
647 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
651 bfe_clear_stats(struct bfe_softc *sc)
655 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
656 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
658 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
663 bfe_resetphy(struct bfe_softc *sc)
667 bfe_writephy(sc, 0, BMCR_RESET);
669 bfe_readphy(sc, 0, &val);
670 if (val & BMCR_RESET) {
671 if_printf(&sc->arpcom.ac_if,
672 "PHY Reset would not complete.\n");
679 bfe_chip_halt(struct bfe_softc *sc)
681 /* disable interrupts - not that it actually does..*/
682 CSR_WRITE_4(sc, BFE_IMASK, 0);
683 CSR_READ_4(sc, BFE_IMASK);
685 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
686 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
688 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
689 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
694 bfe_chip_reset(struct bfe_softc *sc)
698 /* Set the interrupt vector for the enet core */
699 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
702 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK);
703 if (val == BFE_CLOCK) {
704 /* It is, so shut it down */
705 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
706 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
707 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
708 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
709 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
710 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
711 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0);
712 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
713 sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
720 * We want the phy registers to be accessible even when
721 * the driver is "downed" so initialize MDC preamble, frequency,
722 * and whether internal or external phy here.
725 /* 4402 has 62.5Mhz SB clock and internal phy */
726 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
728 /* Internal or external PHY? */
729 val = CSR_READ_4(sc, BFE_DEVCTRL);
730 if (!(val & BFE_IPP))
731 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
732 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
733 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
737 /* Enable CRC32 generation and set proper LED modes */
738 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
740 /* Reset or clear powerdown control bit */
741 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
743 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
747 * We don't want lazy interrupts, so just send them at the end of a
750 BFE_OR(sc, BFE_RCV_LAZY, 0);
752 /* Set max lengths, accounting for VLAN tags */
753 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
754 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
756 /* Set watermark XXX - magic */
757 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
760 * Initialise DMA channels - not forgetting dma addresses need to be
761 * added to BFE_PCI_DMA
763 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
764 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
766 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
768 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
775 bfe_core_disable(struct bfe_softc *sc)
777 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
781 * Set reject, wait for it set, then wait for the core to stop being busy
782 * Then set reset and reject and enable the clocks
784 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
785 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
786 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
787 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
789 CSR_READ_4(sc, BFE_SBTMSLOW);
791 /* Leave reset and reject set */
792 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
797 bfe_core_reset(struct bfe_softc *sc)
801 /* Disable the core */
802 bfe_core_disable(sc);
804 /* and bring it back up */
805 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
806 CSR_READ_4(sc, BFE_SBTMSLOW);
809 /* Chip bug, clear SERR, IB and TO if they are set. */
810 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
811 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
812 val = CSR_READ_4(sc, BFE_SBIMSTATE);
813 if (val & (BFE_IBE | BFE_TO))
814 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
816 /* Clear reset and allow it to move through the core */
817 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
818 CSR_READ_4(sc, BFE_SBTMSLOW);
821 /* Leave the clock set */
822 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
823 CSR_READ_4(sc, BFE_SBTMSLOW);
828 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
832 val = ((uint32_t) data[2]) << 24;
833 val |= ((uint32_t) data[3]) << 16;
834 val |= ((uint32_t) data[4]) << 8;
835 val |= ((uint32_t) data[5]);
836 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
837 val = (BFE_CAM_HI_VALID |
838 (((uint32_t) data[0]) << 8) |
839 (((uint32_t) data[1])));
840 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
841 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
842 ((uint32_t)index << BFE_CAM_INDEX_SHIFT)));
843 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
847 bfe_set_rx_mode(struct bfe_softc *sc)
849 struct ifnet *ifp = &sc->arpcom.ac_if;
850 struct ifmultiaddr *ifma;
854 val = CSR_READ_4(sc, BFE_RXCONF);
856 if (ifp->if_flags & IFF_PROMISC)
857 val |= BFE_RXCONF_PROMISC;
859 val &= ~BFE_RXCONF_PROMISC;
861 if (ifp->if_flags & IFF_BROADCAST)
862 val &= ~BFE_RXCONF_DBCAST;
864 val |= BFE_RXCONF_DBCAST;
867 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
868 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++);
870 if (ifp->if_flags & IFF_ALLMULTI) {
871 val |= BFE_RXCONF_ALLMULTI;
873 val &= ~BFE_RXCONF_ALLMULTI;
874 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
875 if (ifma->ifma_addr->sa_family != AF_LINK)
878 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++);
882 CSR_WRITE_4(sc, BFE_RXCONF, val);
883 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
887 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
892 *ptr = segs->ds_addr;
896 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error)
901 /* The chip needs all addresses to be added to BFE_PCI_DMA */
902 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA;
906 bfe_dma_free(struct bfe_softc *sc)
908 if (sc->bfe_tx_tag != NULL) {
909 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
910 if (sc->bfe_tx_list != NULL) {
911 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
913 sc->bfe_tx_list = NULL;
915 bus_dma_tag_destroy(sc->bfe_tx_tag);
916 sc->bfe_tx_tag = NULL;
919 if (sc->bfe_rx_tag != NULL) {
920 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
921 if (sc->bfe_rx_list != NULL) {
922 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
924 sc->bfe_rx_list = NULL;
926 bus_dma_tag_destroy(sc->bfe_rx_tag);
927 sc->bfe_rx_tag = NULL;
930 if (sc->bfe_tag != NULL) {
933 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
934 bus_dmamap_destroy(sc->bfe_tag,
935 sc->bfe_tx_ring[i].bfe_map);
937 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
938 bus_dmamap_destroy(sc->bfe_tag,
939 sc->bfe_rx_ring[i].bfe_map);
942 bus_dma_tag_destroy(sc->bfe_tag);
946 if (sc->bfe_parent_tag != NULL) {
947 bus_dma_tag_destroy(sc->bfe_parent_tag);
948 sc->bfe_parent_tag = NULL;
953 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data)
956 uint16_t *ptr = (uint16_t *)data;
958 for (i = 0; i < 128; i += 2)
959 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
963 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit,
964 u_long timeout, const int clear)
968 for (i = 0; i < timeout; i++) {
969 uint32_t val = CSR_READ_4(sc, reg);
971 if (clear && !(val & bit))
973 if (!clear && (val & bit))
978 if_printf(&sc->arpcom.ac_if,
979 "BUG! Timeout waiting for bit %08x of register "
980 "%x to %s.\n", bit, reg,
981 (clear ? "clear" : "set"));
988 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val)
993 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
994 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
995 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
996 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
997 (reg << BFE_MDIO_RA_SHIFT) |
998 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
999 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1000 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
1005 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val)
1009 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1010 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1011 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1012 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1013 (reg << BFE_MDIO_RA_SHIFT) |
1014 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1015 (val & BFE_MDIO_DATA_DATA)));
1016 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1022 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1026 bfe_setupphy(struct bfe_softc *sc)
1030 /* Enable activity LED */
1031 bfe_readphy(sc, 26, &val);
1032 bfe_writephy(sc, 26, val & 0x7fff);
1033 bfe_readphy(sc, 26, &val);
1035 /* Enable traffic meter LED mode */
1036 bfe_readphy(sc, 27, &val);
1037 bfe_writephy(sc, 27, val | (1 << 6));
1043 bfe_stats_update(struct bfe_softc *sc)
1048 val = &sc->bfe_hwstats.tx_good_octets;
1049 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1050 *val++ += CSR_READ_4(sc, reg);
1051 val = &sc->bfe_hwstats.rx_good_octets;
1052 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1053 *val++ += CSR_READ_4(sc, reg);
1057 bfe_txeof(struct bfe_softc *sc)
1059 struct ifnet *ifp = &sc->arpcom.ac_if;
1060 uint32_t i, chipidx;
1062 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1063 chipidx /= sizeof(struct bfe_desc);
1065 i = sc->bfe_tx_cons;
1066 /* Go through the mbufs and free those that have been transmitted */
1067 while (i != chipidx) {
1068 struct bfe_data *r = &sc->bfe_tx_ring[i];
1070 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1071 if (r->bfe_mbuf != NULL) {
1073 m_freem(r->bfe_mbuf);
1077 BFE_INC(i, BFE_TX_LIST_CNT);
1080 if (i != sc->bfe_tx_cons) {
1081 /* we freed up some mbufs */
1082 sc->bfe_tx_cons = i;
1083 ifp->if_flags &= ~IFF_OACTIVE;
1085 if (sc->bfe_tx_cnt == 0)
1091 /* Pass a received packet up the stack */
1093 bfe_rxeof(struct bfe_softc *sc)
1095 struct ifnet *ifp = &sc->arpcom.ac_if;
1097 struct bfe_rxheader *rxheader;
1099 uint32_t cons, status, current, len, flags;
1100 struct mbuf_chain chain[MAXCPU];
1102 cons = sc->bfe_rx_cons;
1103 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1104 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1106 ether_input_chain_init(chain);
1108 while (current != cons) {
1109 r = &sc->bfe_rx_ring[cons];
1111 rxheader = mtod(m, struct bfe_rxheader*);
1112 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTREAD);
1113 len = rxheader->len;
1116 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1117 flags = rxheader->flags;
1119 len -= ETHER_CRC_LEN;
1121 /* flag an error and try again */
1122 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
1124 if (flags & BFE_RX_FLAG_SERR)
1125 ifp->if_collisions++;
1126 bfe_list_newbuf(sc, cons, m);
1127 BFE_INC(cons, BFE_RX_LIST_CNT);
1131 /* Go past the rx header */
1132 if (bfe_list_newbuf(sc, cons, NULL) != 0) {
1133 bfe_list_newbuf(sc, cons, m);
1134 BFE_INC(cons, BFE_RX_LIST_CNT);
1139 m_adj(m, BFE_RX_OFFSET);
1140 m->m_len = m->m_pkthdr.len = len;
1143 m->m_pkthdr.rcvif = ifp;
1145 ether_input_chain(ifp, m, chain);
1146 BFE_INC(cons, BFE_RX_LIST_CNT);
1149 ether_input_dispatch(chain);
1151 sc->bfe_rx_cons = cons;
1157 struct bfe_softc *sc = xsc;
1158 struct ifnet *ifp = &sc->arpcom.ac_if;
1159 uint32_t istat, imask, flag;
1161 istat = CSR_READ_4(sc, BFE_ISTAT);
1162 imask = CSR_READ_4(sc, BFE_IMASK);
1165 * Defer unsolicited interrupts - This is necessary because setting the
1166 * chips interrupt mask register to 0 doesn't actually stop the
1170 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1171 CSR_READ_4(sc, BFE_ISTAT);
1173 /* not expecting this interrupt, disregard it */
1178 if (istat & BFE_ISTAT_ERRORS) {
1179 flag = CSR_READ_4(sc, BFE_DMATX_STAT);
1180 if (flag & BFE_STAT_EMASK)
1183 flag = CSR_READ_4(sc, BFE_DMARX_STAT);
1184 if (flag & BFE_RX_FLAG_ERRORS)
1187 ifp->if_flags &= ~IFF_RUNNING;
1191 /* A packet was received */
1192 if (istat & BFE_ISTAT_RX)
1195 /* A packet was sent */
1196 if (istat & BFE_ISTAT_TX)
1199 /* We have packets pending, fire them out */
1200 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
1205 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, uint32_t *txidx)
1207 struct bfe_desc *d = NULL;
1208 struct bfe_data *r = NULL;
1210 uint32_t frag, cur, cnt = 0;
1211 int error, chainlen = 0;
1213 KKASSERT(BFE_TX_LIST_CNT >= (2 + sc->bfe_tx_cnt));
1216 * Count the number of frags in this chain to see if
1217 * we need to m_defrag. Since the descriptor list is shared
1218 * by all packets, we'll m_defrag long chains so that they
1219 * do not use up the entire list, even if they would fit.
1221 for (m = *m_head; m != NULL; m = m->m_next)
1224 if (chainlen > (BFE_TX_LIST_CNT / 4) ||
1225 BFE_TX_LIST_CNT < (2 + chainlen + sc->bfe_tx_cnt)) {
1226 m = m_defrag(*m_head, MB_DONTWAIT);
1235 * Start packing the mbufs in this chain into
1236 * the fragment pointers. Stop when we run out
1237 * of fragments or hit the end of the mbuf chain.
1239 cur = frag = *txidx;
1242 for (m = *m_head; m != NULL; m = m->m_next) {
1243 if (m->m_len != 0) {
1244 KKASSERT(BFE_TX_LIST_CNT >= (2 + sc->bfe_tx_cnt + cnt));
1246 d = &sc->bfe_tx_list[cur];
1247 r = &sc->bfe_tx_ring[cur];
1248 d->bfe_ctrl = BFE_DESC_LEN & m->m_len;
1249 /* always intterupt on completion */
1250 d->bfe_ctrl |= BFE_DESC_IOC;
1252 /* Set start of frame */
1253 d->bfe_ctrl |= BFE_DESC_SOF;
1255 if (cur == BFE_TX_LIST_CNT - 1) {
1257 * Tell the chip to wrap to the start of the
1260 d->bfe_ctrl |= BFE_DESC_EOT;
1263 error = bus_dmamap_load(sc->bfe_tag, r->bfe_map,
1264 mtod(m, void *), m->m_len,
1265 bfe_dma_map_desc, d,
1268 /* XXX This should be a fatal error. */
1269 if_printf(&sc->arpcom.ac_if,
1270 "%s bus_dmamap_load failed: %d",
1276 bus_dmamap_sync(sc->bfe_tag, r->bfe_map,
1277 BUS_DMASYNC_PREWRITE);
1280 BFE_INC(cur, BFE_TX_LIST_CNT);
1285 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF;
1286 sc->bfe_tx_ring[frag].bfe_mbuf = *m_head;
1287 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE);
1290 sc->bfe_tx_cnt += cnt;
1295 * Set up to transmit a packet
1298 bfe_start(struct ifnet *ifp)
1300 struct bfe_softc *sc = ifp->if_softc;
1301 struct mbuf *m_head = NULL;
1302 int idx, need_trans;
1304 ASSERT_SERIALIZED(ifp->if_serializer);
1307 * Not much point trying to send if the link is down
1308 * or we have nothing to send.
1310 if (!sc->bfe_link) {
1311 ifq_purge(&ifp->if_snd);
1315 if (ifp->if_flags & IFF_OACTIVE)
1318 idx = sc->bfe_tx_prod;
1321 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) {
1322 if (BFE_TX_LIST_CNT < (2 + sc->bfe_tx_cnt)) {
1323 ifp->if_flags |= IFF_OACTIVE;
1327 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1332 * Pack the data into the tx ring. If we don't have
1333 * enough room, let the chip drain the ring.
1335 if (bfe_encap(sc, &m_head, &idx)) {
1336 ifp->if_flags |= IFF_OACTIVE;
1342 * If there's a BPF listener, bounce a copy of this frame
1345 BPF_MTAP(ifp, m_head);
1351 sc->bfe_tx_prod = idx;
1352 /* Transmit - twice due to apparent hardware bug */
1353 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1354 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1357 * Set a timeout in case the chip goes out to lunch.
1365 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1366 struct ifnet *ifp = &sc->arpcom.ac_if;
1368 ASSERT_SERIALIZED(ifp->if_serializer);
1370 if (ifp->if_flags & IFF_RUNNING)
1376 if (bfe_list_rx_init(sc) == ENOBUFS) {
1377 if_printf(ifp, "bfe_init failed. "
1378 " Not enough memory for list buffers\n");
1383 bfe_set_rx_mode(sc);
1385 /* Enable the chip and core */
1386 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1387 /* Enable interrupts */
1388 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1390 bfe_ifmedia_upd(ifp);
1391 ifp->if_flags |= IFF_RUNNING;
1392 ifp->if_flags &= ~IFF_OACTIVE;
1394 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1398 * Set media options.
1401 bfe_ifmedia_upd(struct ifnet *ifp)
1403 struct bfe_softc *sc = ifp->if_softc;
1404 struct mii_data *mii;
1406 ASSERT_SERIALIZED(ifp->if_serializer);
1408 mii = device_get_softc(sc->bfe_miibus);
1410 if (mii->mii_instance) {
1411 struct mii_softc *miisc;
1412 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1413 miisc = LIST_NEXT(miisc, mii_list))
1414 mii_phy_reset(miisc);
1424 * Report current media status.
1427 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1429 struct bfe_softc *sc = ifp->if_softc;
1430 struct mii_data *mii;
1432 ASSERT_SERIALIZED(ifp->if_serializer);
1434 mii = device_get_softc(sc->bfe_miibus);
1436 ifmr->ifm_active = mii->mii_media_active;
1437 ifmr->ifm_status = mii->mii_media_status;
1441 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1443 struct bfe_softc *sc = ifp->if_softc;
1444 struct ifreq *ifr = (struct ifreq *) data;
1445 struct mii_data *mii;
1448 ASSERT_SERIALIZED(ifp->if_serializer);
1452 if (ifp->if_flags & IFF_UP)
1453 if (ifp->if_flags & IFF_RUNNING)
1454 bfe_set_rx_mode(sc);
1457 else if (ifp->if_flags & IFF_RUNNING)
1462 if (ifp->if_flags & IFF_RUNNING)
1463 bfe_set_rx_mode(sc);
1467 mii = device_get_softc(sc->bfe_miibus);
1468 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1472 error = ether_ioctl(ifp, command, data);
1479 bfe_watchdog(struct ifnet *ifp)
1481 struct bfe_softc *sc = ifp->if_softc;
1483 ASSERT_SERIALIZED(ifp->if_serializer);
1485 if_printf(ifp, "watchdog timeout -- resetting\n");
1487 ifp->if_flags &= ~IFF_RUNNING;
1496 struct bfe_softc *sc = xsc;
1497 struct mii_data *mii;
1498 struct ifnet *ifp = &sc->arpcom.ac_if;
1500 mii = device_get_softc(sc->bfe_miibus);
1502 lwkt_serialize_enter(ifp->if_serializer);
1504 bfe_stats_update(sc);
1505 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1507 if (sc->bfe_link == 0) {
1509 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE &&
1510 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1516 lwkt_serialize_exit(ifp->if_serializer);
1520 * Stop the adapter and free any mbufs allocated to the
1524 bfe_stop(struct bfe_softc *sc)
1526 struct ifnet *ifp = &sc->arpcom.ac_if;
1528 ASSERT_SERIALIZED(ifp->if_serializer);
1530 callout_stop(&sc->bfe_stat_timer);
1533 bfe_tx_ring_free(sc);
1534 bfe_rx_ring_free(sc);
1536 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);