2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $
29 * $DragonFly: src/sys/dev/netif/fxp/if_fxp.c,v 1.61 2008/09/17 08:51:29 sephe Exp $
33 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
36 #include "opt_polling.h"
38 #include <sys/param.h>
39 #include <sys/systm.h>
41 #include <sys/malloc.h>
42 #include <sys/kernel.h>
43 #include <sys/interrupt.h>
44 #include <sys/socket.h>
45 #include <sys/sysctl.h>
46 #include <sys/thread2.h>
49 #include <net/ifq_var.h>
50 #include <net/if_dl.h>
51 #include <net/if_media.h>
54 #include <sys/sockio.h>
58 #include <net/ethernet.h>
59 #include <net/if_arp.h>
61 #include <vm/vm.h> /* for vtophys */
62 #include <vm/pmap.h> /* for vtophys */
64 #include <net/if_types.h>
65 #include <net/vlan/if_vlan_var.h>
67 #include <bus/pci/pcivar.h>
68 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */
70 #include "../mii_layer/mii.h"
71 #include "../mii_layer/miivar.h"
73 #include "if_fxpreg.h"
74 #include "if_fxpvar.h"
77 #include "miibus_if.h"
80 * NOTE! On the Alpha, we have an alignment constraint. The
81 * card DMAs the packet immediately following the RFA. However,
82 * the first thing in the packet is a 14-byte Ethernet header.
83 * This means that the packet is misaligned. To compensate,
84 * we actually offset the RFA 2 bytes into the cluster. This
85 * alignes the packet after the Ethernet header at a 32-bit
86 * boundary. HOWEVER! This means that the RFA is misaligned!
88 #define RFA_ALIGNMENT_FUDGE 2
91 * Set initial transmit threshold at 64 (512 bytes). This is
92 * increased by 64 (512 bytes) at a time, to maximum of 192
93 * (1536 bytes), if an underrun occurs.
95 static int tx_threshold = 64;
98 * The configuration byte map has several undefined fields which
99 * must be one or must be zero. Set up a template for these bits
100 * only, (assuming a 82557 chip) leaving the actual configuration
103 * See struct fxp_cb_config for the bit definitions.
105 static u_char fxp_cb_config_template[] = {
106 0x0, 0x0, /* cb_status */
107 0x0, 0x0, /* cb_command */
108 0x0, 0x0, 0x0, 0x0, /* link_addr */
135 int16_t revid; /* -1 matches anything */
140 * Claim various Intel PCI device identifiers for this driver. The
141 * sub-vendor and sub-device field are extensively used to identify
142 * particular variants, but we don't currently differentiate between
145 static struct fxp_ident fxp_ident_table[] = {
146 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" },
147 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" },
148 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
149 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
150 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
151 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
152 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
153 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
154 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
155 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
156 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
157 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
158 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
159 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
160 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
161 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
162 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
163 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
164 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" },
165 { 0x1064, -1, "Intel 82562ET/EZ/GT/GZ (ICH6/ICH6R) Pro/100 VE Ethernet" },
166 { 0x1065, -1, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" },
167 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" },
168 { 0x1069, -1, "Intel 82562EM/EX/GX Pro/100 Ethernet" },
169 { 0x1091, -1, "Intel 82562GX Pro/100 Ethernet" },
170 { 0x1092, -1, "Intel Pro/100 VE Network Connection" },
171 { 0x1093, -1, "Intel Pro/100 VM Network Connection" },
172 { 0x1094, -1, "Intel Pro/100 946GZ (ICH7) Network Connection" },
173 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" },
174 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" },
175 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" },
176 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" },
177 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" },
178 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" },
179 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" },
180 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" },
181 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" },
182 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" },
183 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" },
184 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" },
185 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" },
186 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" },
187 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" },
188 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" },
189 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
190 { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" },
194 static int fxp_probe(device_t dev);
195 static int fxp_attach(device_t dev);
196 static int fxp_detach(device_t dev);
197 static int fxp_shutdown(device_t dev);
198 static int fxp_suspend(device_t dev);
199 static int fxp_resume(device_t dev);
201 static void fxp_intr(void *xsc);
202 static void fxp_intr_body(struct fxp_softc *sc,
203 u_int8_t statack, int count);
205 static void fxp_init(void *xsc);
206 static void fxp_tick(void *xsc);
207 static void fxp_powerstate_d0(device_t dev);
208 static void fxp_start(struct ifnet *ifp);
209 static void fxp_stop(struct fxp_softc *sc);
210 static void fxp_release(device_t dev);
211 static int fxp_ioctl(struct ifnet *ifp, u_long command,
212 caddr_t data, struct ucred *);
213 static void fxp_watchdog(struct ifnet *ifp);
214 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm);
215 static int fxp_mc_addrs(struct fxp_softc *sc);
216 static void fxp_mc_setup(struct fxp_softc *sc);
217 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
219 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
221 static void fxp_autosize_eeprom(struct fxp_softc *sc);
222 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
223 int offset, int words);
224 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
225 int offset, int words);
226 static int fxp_ifmedia_upd(struct ifnet *ifp);
227 static void fxp_ifmedia_sts(struct ifnet *ifp,
228 struct ifmediareq *ifmr);
229 static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
230 static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
231 struct ifmediareq *ifmr);
232 static int fxp_miibus_readreg(device_t dev, int phy, int reg);
233 static void fxp_miibus_writereg(device_t dev, int phy, int reg,
235 static void fxp_load_ucode(struct fxp_softc *sc);
236 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
237 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
238 #ifdef DEVICE_POLLING
239 static poll_handler_t fxp_poll;
242 static void fxp_lwcopy(volatile u_int32_t *src,
243 volatile u_int32_t *dst);
244 static void fxp_scb_wait(struct fxp_softc *sc);
245 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
246 static void fxp_dma_wait(volatile u_int16_t *status,
247 struct fxp_softc *sc);
249 static device_method_t fxp_methods[] = {
250 /* Device interface */
251 DEVMETHOD(device_probe, fxp_probe),
252 DEVMETHOD(device_attach, fxp_attach),
253 DEVMETHOD(device_detach, fxp_detach),
254 DEVMETHOD(device_shutdown, fxp_shutdown),
255 DEVMETHOD(device_suspend, fxp_suspend),
256 DEVMETHOD(device_resume, fxp_resume),
259 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
260 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
265 static driver_t fxp_driver = {
268 sizeof(struct fxp_softc),
271 static devclass_t fxp_devclass;
273 DECLARE_DUMMY_MODULE(if_fxp);
274 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1);
275 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0);
276 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0);
277 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0);
280 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events");
283 * Copy a 16-bit aligned 32-bit quantity.
286 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst)
291 volatile u_int16_t *a = (volatile u_int16_t *)src;
292 volatile u_int16_t *b = (volatile u_int16_t *)dst;
300 * Wait for the previous command to be accepted (but not necessarily
304 fxp_scb_wait(struct fxp_softc *sc)
308 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
311 if_printf(&sc->arpcom.ac_if,
312 "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
313 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
314 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
315 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
316 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
321 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
324 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
325 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
328 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
332 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc)
336 while (!(*status & FXP_CB_STATUS_C) && --i)
339 if_printf(&sc->arpcom.ac_if, "DMA timeout\n");
343 * Return identification string if this is device is ours.
346 fxp_probe(device_t dev)
350 struct fxp_ident *ident;
352 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
353 devid = pci_get_device(dev);
354 revid = pci_get_revid(dev);
355 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
356 if (ident->devid == devid &&
357 (ident->revid == revid || ident->revid == -1)) {
358 device_set_desc(dev, ident->name);
367 fxp_powerstate_d0(device_t dev)
369 u_int32_t iobase, membase, irq;
371 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
372 /* Save important PCI config data. */
373 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4);
374 membase = pci_read_config(dev, FXP_PCI_MMBA, 4);
375 irq = pci_read_config(dev, PCIR_INTLINE, 4);
377 /* Reset the power state. */
378 device_printf(dev, "chip is in D%d power mode "
379 "-- setting to D0\n", pci_get_powerstate(dev));
381 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
383 /* Restore PCI config data. */
384 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4);
385 pci_write_config(dev, FXP_PCI_MMBA, membase, 4);
386 pci_write_config(dev, PCIR_INTLINE, irq, 4);
391 fxp_attach(device_t dev)
394 struct fxp_softc *sc = device_get_softc(dev);
398 int i, rid, m1, m2, prefer_iomap;
400 callout_init(&sc->fxp_stat_timer);
401 sysctl_ctx_init(&sc->sysctl_ctx);
404 * Enable bus mastering. Enable memory space too, in case
405 * BIOS/Prom forgot about it.
407 pci_enable_busmaster(dev);
408 pci_enable_io(dev, SYS_RES_MEMORY);
409 val = pci_read_config(dev, PCIR_COMMAND, 2);
411 fxp_powerstate_d0(dev);
414 * Figure out which we should try first - memory mapping or i/o mapping?
415 * We default to memory mapping. Then we accept an override from the
416 * command line. Then we check to see which one is enabled.
419 m2 = PCIM_CMD_PORTEN;
421 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
422 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) {
423 m1 = PCIM_CMD_PORTEN;
429 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
430 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
431 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd,
434 if (sc->mem == NULL && (val & m2)) {
436 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
437 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
438 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd,
443 device_printf(dev, "could not map device registers\n");
448 device_printf(dev, "using %s space register mapping\n",
449 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
452 sc->sc_st = rman_get_bustag(sc->mem);
453 sc->sc_sh = rman_get_bushandle(sc->mem);
456 * Allocate our interrupt.
459 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
460 RF_SHAREABLE | RF_ACTIVE);
461 if (sc->irq == NULL) {
462 device_printf(dev, "could not map interrupt\n");
468 * Reset to a stable state.
470 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
473 sc->cbl_base = kmalloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
474 M_DEVBUF, M_WAITOK | M_ZERO);
476 sc->fxp_stats = kmalloc(sizeof(struct fxp_stats), M_DEVBUF,
479 sc->mcsp = kmalloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK);
482 * Pre-allocate our receive buffers.
484 for (i = 0; i < FXP_NRFABUFS; i++) {
485 if (fxp_add_rfabuf(sc, NULL) != 0) {
491 * Find out how large of an SEEPROM we have.
493 fxp_autosize_eeprom(sc);
496 * Determine whether we must use the 503 serial interface.
498 fxp_read_eeprom(sc, &data, 6, 1);
499 if ((data & FXP_PHY_DEVICE_MASK) != 0 &&
500 (data & FXP_PHY_SERIAL_ONLY))
501 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
504 * Create the sysctl tree
506 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
507 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
508 device_get_nameunit(dev), CTLFLAG_RD, 0, "");
509 if (sc->sysctl_tree == NULL)
511 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
512 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
513 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I",
514 "FXP driver receive interrupt microcode bundling delay");
515 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
516 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
517 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I",
518 "FXP driver receive interrupt microcode bundle size limit");
521 * Pull in device tunables.
523 sc->tunable_int_delay = TUNABLE_INT_DELAY;
524 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
525 resource_int_value(device_get_name(dev), device_get_unit(dev),
526 "int_delay", &sc->tunable_int_delay);
527 resource_int_value(device_get_name(dev), device_get_unit(dev),
528 "bundle_max", &sc->tunable_bundle_max);
531 * Find out the chip revision; lump all 82557 revs together.
533 fxp_read_eeprom(sc, &data, 5, 1);
534 if ((data >> 8) == 1)
535 sc->revision = FXP_REV_82557;
537 sc->revision = pci_get_revid(dev);
540 * Enable workarounds for certain chip revision deficiencies.
542 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
543 * some systems based a normal 82559 design, have a defect where
544 * the chip can cause a PCI protocol violation if it receives
545 * a CU_RESUME command when it is entering the IDLE state. The
546 * workaround is to disable Dynamic Standby Mode, so the chip never
547 * deasserts CLKRUN#, and always remains in an active state.
549 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
551 i = pci_get_device(dev);
552 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) ||
553 sc->revision >= FXP_REV_82559_A0) {
554 fxp_read_eeprom(sc, &data, 10, 1);
555 if (data & 0x02) { /* STB enable */
560 "Disabling dynamic standby mode in EEPROM\n");
562 fxp_write_eeprom(sc, &data, 10, 1);
563 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
565 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
566 fxp_read_eeprom(sc, &data, i, 1);
569 i = (1 << sc->eeprom_size) - 1;
570 cksum = 0xBABA - cksum;
571 fxp_read_eeprom(sc, &data, i, 1);
572 fxp_write_eeprom(sc, &cksum, i, 1);
574 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
578 * If the user elects to continue, try the software
579 * workaround, as it is better than nothing.
581 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
587 * If we are not a 82557 chip, we can enable extended features.
589 if (sc->revision != FXP_REV_82557) {
591 * If MWI is enabled in the PCI configuration, and there
592 * is a valid cacheline size (8 or 16 dwords), then tell
593 * the board to turn on MWI.
595 if (val & PCIM_CMD_MWRICEN &&
596 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
597 sc->flags |= FXP_FLAG_MWI_ENABLE;
599 /* turn on the extended TxCB feature */
600 sc->flags |= FXP_FLAG_EXT_TXCB;
602 /* enable reception of long frames for VLAN */
603 sc->flags |= FXP_FLAG_LONG_PKT_EN;
609 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3);
610 if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
611 device_printf(dev, "10Mbps\n");
613 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
614 pci_get_vendor(dev), pci_get_device(dev),
615 pci_get_subvendor(dev), pci_get_subdevice(dev),
617 fxp_read_eeprom(sc, &data, 10, 1);
618 device_printf(dev, "Dynamic Standby mode is %s\n",
619 data & 0x02 ? "enabled" : "disabled");
623 * If this is only a 10Mbps device, then there is no MII, and
624 * the PHY will use a serial interface instead.
626 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
627 * doesn't have a programming interface of any sort. The
628 * media is sensed automatically based on how the link partner
629 * is configured. This is, in essence, manual configuration.
631 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
632 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
633 fxp_serial_ifmedia_sts);
634 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
635 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
637 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
639 device_printf(dev, "MII without any PHY!\n");
645 ifp = &sc->arpcom.ac_if;
646 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
647 ifp->if_baudrate = 100000000;
648 ifp->if_init = fxp_init;
650 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
651 ifp->if_ioctl = fxp_ioctl;
652 ifp->if_start = fxp_start;
653 #ifdef DEVICE_POLLING
654 ifp->if_poll = fxp_poll;
656 ifp->if_watchdog = fxp_watchdog;
659 * Attach the interface.
661 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
664 * Tell the upper layer(s) we support long frames.
666 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
669 * Let the system queue as many packets as we have available
672 ifq_set_maxlen(&ifp->if_snd, FXP_USABLE_TXCB);
673 ifq_set_ready(&ifp->if_snd);
675 error = bus_setup_intr(dev, sc->irq, INTR_MPSAFE,
676 fxp_intr, sc, &sc->ih,
680 if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
681 ifmedia_removeall(&sc->sc_media);
682 device_printf(dev, "could not setup irq\n");
686 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->irq));
687 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
692 device_printf(dev, "Failed to malloc memory\n");
700 * release all resources
703 fxp_release(device_t dev)
705 struct fxp_softc *sc = device_get_softc(dev);
708 device_delete_child(dev, sc->miibus);
709 bus_generic_detach(dev);
712 kfree(sc->cbl_base, M_DEVBUF);
714 kfree(sc->fxp_stats, M_DEVBUF);
716 kfree(sc->mcsp, M_DEVBUF);
718 m_freem(sc->rfa_headm);
721 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
723 bus_release_resource(dev, sc->rtp, sc->rgd, sc->mem);
725 sysctl_ctx_free(&sc->sysctl_ctx);
732 fxp_detach(device_t dev)
734 struct fxp_softc *sc = device_get_softc(dev);
736 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
739 * Stop DMA and drop transmit queue.
744 * Disable interrupts.
746 * NOTE: This should be done after fxp_stop(), because software
747 * resetting in fxp_stop() may leave interrupts turned on.
749 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
752 * Free all media structures.
754 if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
755 ifmedia_removeall(&sc->sc_media);
758 bus_teardown_intr(dev, sc->irq, sc->ih);
760 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
763 * Close down routes etc.
765 ether_ifdetach(&sc->arpcom.ac_if);
767 /* Release our allocated resources. */
774 * Device shutdown routine. Called at system shutdown after sync. The
775 * main purpose of this routine is to shut off receiver DMA so that
776 * kernel memory doesn't get clobbered during warmboot.
779 fxp_shutdown(device_t dev)
781 struct fxp_softc *sc = device_get_softc(dev);
782 struct ifnet *ifp = &sc->arpcom.ac_if;
784 lwkt_serialize_enter(ifp->if_serializer);
786 * Make sure that DMA is disabled prior to reboot. Not doing
787 * do could allow DMA to corrupt kernel memory during the
788 * reboot before the driver initializes.
791 lwkt_serialize_exit(ifp->if_serializer);
796 * Device suspend routine. Stop the interface and save some PCI
797 * settings in case the BIOS doesn't restore them properly on
801 fxp_suspend(device_t dev)
803 struct fxp_softc *sc = device_get_softc(dev);
806 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
810 for (i = 0; i < 5; i++)
811 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4);
812 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
813 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
814 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
815 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
819 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
824 * Device resume routine. Restore some PCI settings in case the BIOS
825 * doesn't, re-enable busmastering, and restart the interface if
829 fxp_resume(device_t dev)
831 struct fxp_softc *sc = device_get_softc(dev);
832 struct ifnet *ifp = &sc->arpcom.ac_if;
835 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
837 fxp_powerstate_d0(dev);
839 /* better way to do this? */
840 for (i = 0; i < 5; i++)
841 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4);
842 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
843 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
844 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
845 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
847 /* reenable busmastering and memory space */
848 pci_enable_busmaster(dev);
849 pci_enable_io(dev, SYS_RES_MEMORY);
851 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
854 /* reinitialize interface if necessary */
855 if (ifp->if_flags & IFF_UP)
860 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
865 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
873 for (x = 1 << (length - 1); x; x >>= 1) {
875 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
877 reg = FXP_EEPROM_EECS;
878 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
880 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
882 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
888 * Read from the serial EEPROM. Basically, you manually shift in
889 * the read opcode (one bit at a time) and then shift in the address,
890 * and then you shift out the data (all of this one bit at a time).
891 * The word size is 16 bits, so you have to provide the address for
892 * every 16 bits of data.
895 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
900 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
902 * Shift in read opcode.
904 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
909 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
911 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
913 reg = FXP_EEPROM_EECS;
914 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
916 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
918 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
920 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
922 if (autosize && reg == 0) {
923 sc->eeprom_size = data;
931 reg = FXP_EEPROM_EECS;
932 for (x = 1 << 15; x; x >>= 1) {
933 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
935 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
937 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
940 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
947 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
952 * Erase/write enable.
954 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
955 fxp_eeprom_shiftin(sc, 0x4, 3);
956 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
957 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
960 * Shift in write opcode, address, data.
962 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
963 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
964 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
965 fxp_eeprom_shiftin(sc, data, 16);
966 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
969 * Wait for EEPROM to finish up.
971 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
973 for (i = 0; i < 1000; i++) {
974 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
978 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
981 * Erase/write disable.
983 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
984 fxp_eeprom_shiftin(sc, 0x4, 3);
985 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
986 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
993 * Figure out EEPROM size.
995 * 559's can have either 64-word or 256-word EEPROMs, the 558
996 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
997 * talks about the existance of 16 to 256 word EEPROMs.
999 * The only known sizes are 64 and 256, where the 256 version is used
1000 * by CardBus cards to store CIS information.
1002 * The address is shifted in msb-to-lsb, and after the last
1003 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1004 * after which follows the actual data. We try to detect this zero, by
1005 * probing the data-out bit in the EEPROM control register just after
1006 * having shifted in a bit. If the bit is zero, we assume we've
1007 * shifted enough address bits. The data-out should be tri-state,
1008 * before this, which should translate to a logical one.
1011 fxp_autosize_eeprom(struct fxp_softc *sc)
1014 /* guess maximum size of 256 words */
1015 sc->eeprom_size = 8;
1018 fxp_eeprom_getword(sc, 0, 1);
1022 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1026 for (i = 0; i < words; i++)
1027 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1031 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1035 for (i = 0; i < words; i++)
1036 fxp_eeprom_putword(sc, offset + i, data[i]);
1040 * Start packet transmission on the interface.
1043 fxp_start(struct ifnet *ifp)
1045 struct fxp_softc *sc = ifp->if_softc;
1046 struct fxp_cb_tx *txp;
1048 ASSERT_SERIALIZED(ifp->if_serializer);
1051 * See if we need to suspend xmit until the multicast filter
1052 * has been reprogrammed (which can only be done at the head
1053 * of the command chain).
1055 if (sc->need_mcsetup) {
1056 ifq_purge(&ifp->if_snd);
1060 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1066 * We're finished if there is nothing more to add to the list or if
1067 * we're all filled up with buffers to transmit.
1068 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1069 * a NOP command when needed.
1071 while (!ifq_is_empty(&ifp->if_snd) && sc->tx_queued < FXP_USABLE_TXCB) {
1072 struct mbuf *m, *mb_head;
1073 int segment, ntries = 0;
1076 * Grab a packet to transmit.
1078 mb_head = ifq_dequeue(&ifp->if_snd, NULL);
1079 if (mb_head == NULL)
1083 * Make sure that the packet fits into one TX desc
1086 for (m = mb_head; m != NULL; m = m->m_next) {
1087 if (m->m_len != 0) {
1089 if (segment >= FXP_NTXSEG)
1093 if (segment >= FXP_NTXSEG) {
1098 * Packet is excessively fragmented,
1099 * and will never fit into one TX
1107 mn = m_dup(mb_head, MB_DONTWAIT);
1121 * Get pointer to next available tx desc.
1123 txp = sc->cbl_last->next;
1126 * Go through each of the mbufs in the chain and initialize
1127 * the transmit buffer descriptors with the physical address
1128 * and size of the mbuf.
1130 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
1131 if (m->m_len != 0) {
1132 KKASSERT(segment < FXP_NTXSEG);
1134 txp->tbd[segment].tb_addr =
1135 vtophys(mtod(m, vm_offset_t));
1136 txp->tbd[segment].tb_size = m->m_len;
1140 KKASSERT(m == NULL);
1142 txp->tbd_number = segment;
1143 txp->mb_head = mb_head;
1145 if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1147 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1151 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1152 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
1154 txp->tx_threshold = tx_threshold;
1157 * Advance the end of list forward.
1159 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
1163 * Advance the beginning of the list forward if there are
1164 * no other packets queued (when nothing is queued, cbl_first
1165 * sits on the last TxCB that was sent out).
1167 if (sc->tx_queued == 0)
1168 sc->cbl_first = txp;
1172 * Set a 5 second timer just in case we don't hear
1173 * from the card again.
1177 BPF_MTAP(ifp, mb_head);
1180 if (sc->tx_queued >= FXP_USABLE_TXCB)
1181 ifp->if_flags |= IFF_OACTIVE;
1184 * We're finished. If we added to the list, issue a RESUME to get DMA
1185 * going again if suspended.
1189 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1193 #ifdef DEVICE_POLLING
1196 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1198 struct fxp_softc *sc = ifp->if_softc;
1201 ASSERT_SERIALIZED(ifp->if_serializer);
1205 /* disable interrupts */
1206 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1208 case POLL_DEREGISTER:
1209 /* enable interrupts */
1210 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1213 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1215 if (cmd == POLL_AND_CHECK_STATUS) {
1218 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1219 if (tmp == 0xff || tmp == 0)
1220 return; /* nothing to do */
1222 /* ack what we can */
1224 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1227 fxp_intr_body(sc, statack, count);
1232 #endif /* DEVICE_POLLING */
1235 * Process interface interrupts.
1240 struct fxp_softc *sc = xsc;
1243 ASSERT_SERIALIZED(sc->arpcom.ac_if.if_serializer);
1245 if (sc->suspended) {
1249 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1251 * It should not be possible to have all bits set; the
1252 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1253 * all bits are set, this may indicate that the card has
1254 * been physically ejected, so ignore it.
1256 if (statack == 0xff)
1260 * First ACK all the interrupts in this pass.
1262 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1263 fxp_intr_body(sc, statack, -1);
1268 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count)
1270 struct ifnet *ifp = &sc->arpcom.ac_if;
1272 struct fxp_rfa *rfa;
1273 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1274 struct mbuf_chain chain[MAXCPU];
1278 #ifdef DEVICE_POLLING
1279 /* Pick up a deferred RNR condition if `count' ran out last time. */
1280 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1281 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1287 * Free any finished transmit mbuf chains.
1289 * Handle the CNA event likt a CXTNO event. It used to
1290 * be that this event (control unit not ready) was not
1291 * encountered, but it is now with the SMPng modifications.
1292 * The exact sequence of events that occur when the interface
1293 * is brought up are different now, and if this event
1294 * goes unhandled, the configuration/rxfilter setup sequence
1295 * can stall for several seconds. The result is that no
1296 * packets go out onto the wire for about 5 to 10 seconds
1297 * after the interface is ifconfig'ed for the first time.
1299 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) {
1300 struct fxp_cb_tx *txp;
1302 for (txp = sc->cbl_first; sc->tx_queued &&
1303 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1305 if ((m = txp->mb_head) != NULL) {
1306 txp->mb_head = NULL;
1313 sc->cbl_first = txp;
1315 if (sc->tx_queued < FXP_USABLE_TXCB)
1316 ifp->if_flags &= ~IFF_OACTIVE;
1318 if (sc->tx_queued == 0) {
1320 if (sc->need_mcsetup)
1325 * Try to start more packets transmitting.
1327 if (!ifq_is_empty(&ifp->if_snd))
1332 * Just return if nothing happened on the receive side.
1334 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1337 ether_input_chain_init(chain);
1340 * Process receiver interrupts. If a no-resource (RNR)
1341 * condition exists, get whatever packets we can and
1342 * re-start the receiver.
1344 * When using polling, we do not process the list to completion,
1345 * so when we get an RNR interrupt we must defer the restart
1346 * until we hit the last buffer with the C bit set.
1347 * If we run out of cycles and rfa_headm has the C bit set,
1348 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1349 * that the info will be used in the subsequent polling cycle.
1353 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1354 RFA_ALIGNMENT_FUDGE);
1356 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1357 if (count >= 0 && count-- == 0) {
1359 /* Defer RNR processing until the next time. */
1360 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1365 #endif /* DEVICE_POLLING */
1367 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0)
1371 * Remove first packet from the chain.
1373 sc->rfa_headm = m->m_next;
1374 if (sc->rfa_headm == NULL)
1375 sc->rfa_tailm = NULL;
1379 * Add a new buffer to the receive chain.
1380 * If this fails, the old buffer is recycled
1383 if (fxp_add_rfabuf(sc, m) == 0) {
1387 * Fetch packet length (the top 2 bits of
1388 * actual_size are flags set by the controller
1389 * upon completion), and drop the packet in case
1390 * of bogus length or CRC errors.
1392 total_len = rfa->actual_size & 0x3fff;
1393 if (total_len < sizeof(struct ether_header) ||
1394 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE -
1395 sizeof(struct fxp_rfa) ||
1396 (rfa->rfa_status & FXP_RFA_STATUS_CRC)) {
1400 m->m_pkthdr.len = m->m_len = total_len;
1401 ether_input_chain(ifp, m, NULL, chain);
1405 ether_input_dispatch(chain);
1409 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1410 vtophys(sc->rfa_headm->m_ext.ext_buf) +
1411 RFA_ALIGNMENT_FUDGE);
1412 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1417 * Update packet in/out/collision statistics. The i82557 doesn't
1418 * allow you to access these counters without doing a fairly
1419 * expensive DMA to get _all_ of the statistics it maintains, so
1420 * we do this operation here only once per second. The statistics
1421 * counters in the kernel are updated from the previous dump-stats
1422 * DMA and then a new dump-stats DMA is started. The on-chip
1423 * counters are zeroed when the DMA completes. If we can't start
1424 * the DMA immediately, we don't wait - we just prepare to read
1425 * them again next time.
1430 struct fxp_softc *sc = xsc;
1431 struct ifnet *ifp = &sc->arpcom.ac_if;
1432 struct fxp_stats *sp = sc->fxp_stats;
1433 struct fxp_cb_tx *txp;
1436 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1438 ifp->if_opackets += sp->tx_good;
1439 ifp->if_collisions += sp->tx_total_collisions;
1441 ifp->if_ipackets += sp->rx_good;
1442 sc->rx_idle_secs = 0;
1445 * Receiver's been idle for another second.
1451 sp->rx_alignment_errors +
1453 sp->rx_overrun_errors;
1455 * If any transmit underruns occured, bump up the transmit
1456 * threshold by another 512 bytes (64 * 8).
1458 if (sp->tx_underruns) {
1459 ifp->if_oerrors += sp->tx_underruns;
1460 if (tx_threshold < 192)
1465 * Release any xmit buffers that have completed DMA. This isn't
1466 * strictly necessary to do here, but it's advantagous for mbufs
1467 * with external storage to be released in a timely manner rather
1468 * than being defered for a potentially long time. This limits
1469 * the delay to a maximum of one second.
1471 for (txp = sc->cbl_first; sc->tx_queued &&
1472 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1474 if ((m = txp->mb_head) != NULL) {
1475 txp->mb_head = NULL;
1482 sc->cbl_first = txp;
1484 if (sc->tx_queued < FXP_USABLE_TXCB)
1485 ifp->if_flags &= ~IFF_OACTIVE;
1486 if (sc->tx_queued == 0)
1490 * Try to start more packets transmitting.
1492 if (!ifq_is_empty(&ifp->if_snd))
1496 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1497 * then assume the receiver has locked up and attempt to clear
1498 * the condition by reprogramming the multicast filter. This is
1499 * a work-around for a bug in the 82557 where the receiver locks
1500 * up if it gets certain types of garbage in the syncronization
1501 * bits prior to the packet header. This bug is supposed to only
1502 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
1503 * mode as well (perhaps due to a 10/100 speed transition).
1505 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1506 sc->rx_idle_secs = 0;
1510 * If there is no pending command, start another stats
1511 * dump. Otherwise punt for now.
1513 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1515 * Start another stats dump.
1517 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1520 * A previous command is still waiting to be accepted.
1521 * Just zero our copy of the stats and wait for the
1522 * next timer event to update them.
1525 sp->tx_underruns = 0;
1526 sp->tx_total_collisions = 0;
1529 sp->rx_crc_errors = 0;
1530 sp->rx_alignment_errors = 0;
1531 sp->rx_rnr_errors = 0;
1532 sp->rx_overrun_errors = 0;
1534 if (sc->miibus != NULL)
1535 mii_tick(device_get_softc(sc->miibus));
1537 * Schedule another timeout one second from now.
1539 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc);
1541 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1545 * Stop the interface. Cancels the statistics updater and resets
1549 fxp_stop(struct fxp_softc *sc)
1551 struct ifnet *ifp = &sc->arpcom.ac_if;
1552 struct fxp_cb_tx *txp;
1555 ASSERT_SERIALIZED(ifp->if_serializer);
1557 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1561 * Cancel stats updater.
1563 callout_stop(&sc->fxp_stat_timer);
1566 * Issue software reset, which also unloads the microcode.
1568 sc->flags &= ~FXP_FLAG_UCODE;
1569 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
1573 * Release any xmit buffers.
1577 for (i = 0; i < FXP_NTXCB; i++) {
1578 if (txp[i].mb_head != NULL) {
1579 m_freem(txp[i].mb_head);
1580 txp[i].mb_head = NULL;
1587 * Free all the receive buffers then reallocate/reinitialize
1589 if (sc->rfa_headm != NULL)
1590 m_freem(sc->rfa_headm);
1591 sc->rfa_headm = NULL;
1592 sc->rfa_tailm = NULL;
1593 for (i = 0; i < FXP_NRFABUFS; i++) {
1594 if (fxp_add_rfabuf(sc, NULL) != 0) {
1596 * This "can't happen" - we're at splimp()
1597 * and we just freed all the buffers we need
1600 panic("fxp_stop: no buffers!");
1606 * Watchdog/transmission transmit timeout handler. Called when a
1607 * transmission is started on the interface, but no interrupt is
1608 * received before the timeout. This usually indicates that the
1609 * card has wedged for some reason.
1612 fxp_watchdog(struct ifnet *ifp)
1614 ASSERT_SERIALIZED(ifp->if_serializer);
1616 if_printf(ifp, "device timeout\n");
1618 fxp_init(ifp->if_softc);
1624 struct fxp_softc *sc = xsc;
1625 struct ifnet *ifp = &sc->arpcom.ac_if;
1626 struct fxp_cb_config *cbp;
1627 struct fxp_cb_ias *cb_ias;
1628 struct fxp_cb_tx *txp;
1629 struct fxp_cb_mcs *mcsp;
1632 ASSERT_SERIALIZED(ifp->if_serializer);
1635 * Cancel any pending I/O
1639 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1642 * Initialize base of CBL and RFA memory. Loading with zero
1643 * sets it up for regular linear addressing.
1645 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1646 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
1649 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
1652 * Initialize base of dump-stats buffer.
1655 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats));
1656 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
1659 * Attempt to load microcode if requested.
1661 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0)
1665 * Initialize the multicast address list.
1667 if (fxp_mc_addrs(sc)) {
1669 mcsp->cb_status = 0;
1670 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL;
1671 mcsp->link_addr = -1;
1673 * Start the multicast setup command.
1676 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
1677 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1678 /* ...and wait for it to complete. */
1679 fxp_dma_wait(&mcsp->cb_status, sc);
1683 * We temporarily use memory that contains the TxCB list to
1684 * construct the config CB. The TxCB list memory is rebuilt
1687 cbp = (struct fxp_cb_config *) sc->cbl_base;
1690 * This bcopy is kind of disgusting, but there are a bunch of must be
1691 * zero and must be one bits in this structure and this is the easiest
1692 * way to initialize them all to proper values.
1694 bcopy(fxp_cb_config_template,
1695 (void *)(uintptr_t)(volatile void *)&cbp->cb_status,
1696 sizeof(fxp_cb_config_template));
1699 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL;
1700 cbp->link_addr = -1; /* (no) next command */
1701 cbp->byte_count = 22; /* (22) bytes to config */
1702 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
1703 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
1704 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
1705 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
1706 cbp->type_enable = 0; /* actually reserved */
1707 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
1708 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
1709 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
1710 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
1711 cbp->dma_mbce = 0; /* (disable) dma max counters */
1712 cbp->late_scb = 0; /* (don't) defer SCB update */
1713 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
1714 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
1715 cbp->ci_int = 1; /* interrupt on CU idle */
1716 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
1717 cbp->ext_stats_dis = 1; /* disable extended counters */
1718 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
1719 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm;
1720 cbp->disc_short_rx = !prm; /* discard short packets */
1721 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
1722 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
1723 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */
1724 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
1725 cbp->csma_dis = 0; /* (don't) disable link */
1726 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */
1727 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
1728 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
1729 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
1730 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
1731 cbp->nsai = 1; /* (don't) disable source addr insert */
1732 cbp->preamble_length = 2; /* (7 byte) preamble */
1733 cbp->loopback = 0; /* (don't) loopback */
1734 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
1735 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
1736 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
1737 cbp->promiscuous = prm; /* promiscuous mode */
1738 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
1739 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
1740 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
1741 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
1742 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
1744 cbp->stripping = !prm; /* truncate rx packet to byte count */
1745 cbp->padding = 1; /* (do) pad short tx packets */
1746 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
1747 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
1748 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
1749 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */
1750 /* must set wake_en in PMCSR also */
1751 cbp->force_fdx = 0; /* (don't) force full duplex */
1752 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
1753 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
1754 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
1756 if (sc->revision == FXP_REV_82557) {
1758 * The 82557 has no hardware flow control, the values
1759 * below are the defaults for the chip.
1761 cbp->fc_delay_lsb = 0;
1762 cbp->fc_delay_msb = 0x40;
1763 cbp->pri_fc_thresh = 3;
1765 cbp->rx_fc_restop = 0;
1766 cbp->rx_fc_restart = 0;
1768 cbp->pri_fc_loc = 1;
1770 cbp->fc_delay_lsb = 0x1f;
1771 cbp->fc_delay_msb = 0x01;
1772 cbp->pri_fc_thresh = 3;
1773 cbp->tx_fc_dis = 0; /* enable transmit FC */
1774 cbp->rx_fc_restop = 1; /* enable FC restop frames */
1775 cbp->rx_fc_restart = 1; /* enable FC restart frames */
1776 cbp->fc_filter = !prm; /* drop FC frames to host */
1777 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
1781 * Start the config command/DMA.
1784 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
1785 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1786 /* ...and wait for it to complete. */
1787 fxp_dma_wait(&cbp->cb_status, sc);
1790 * Now initialize the station address. Temporarily use the TxCB
1791 * memory area like we did above for the config CB.
1793 cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
1794 cb_ias->cb_status = 0;
1795 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL;
1796 cb_ias->link_addr = -1;
1797 bcopy(sc->arpcom.ac_enaddr,
1798 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr,
1799 sizeof(sc->arpcom.ac_enaddr));
1802 * Start the IAS (Individual Address Setup) command/DMA.
1805 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1806 /* ...and wait for it to complete. */
1807 fxp_dma_wait(&cb_ias->cb_status, sc);
1810 * Initialize transmit control block (TxCB) list.
1814 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
1815 for (i = 0; i < FXP_NTXCB; i++) {
1816 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK;
1817 txp[i].cb_command = FXP_CB_COMMAND_NOP;
1819 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status);
1820 if (sc->flags & FXP_FLAG_EXT_TXCB)
1821 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]);
1823 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
1824 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
1827 * Set the suspend flag on the first TxCB and start the control
1828 * unit. It will execute the NOP and then suspend.
1830 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S;
1831 sc->cbl_first = sc->cbl_last = txp;
1835 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1838 * Initialize receiver buffer area - RFA.
1841 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1842 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE);
1843 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1846 * Set current media.
1848 if (sc->miibus != NULL)
1849 mii_mediachg(device_get_softc(sc->miibus));
1851 ifp->if_flags |= IFF_RUNNING;
1852 ifp->if_flags &= ~IFF_OACTIVE;
1855 * Enable interrupts.
1857 #ifdef DEVICE_POLLING
1859 * ... but only do that if we are not polling. And because (presumably)
1860 * the default is interrupts on, we need to disable them explicitly!
1862 if ( ifp->if_flags & IFF_POLLING )
1863 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1865 #endif /* DEVICE_POLLING */
1866 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1869 * Start stats updater.
1871 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc);
1875 fxp_serial_ifmedia_upd(struct ifnet *ifp)
1877 ASSERT_SERIALIZED(ifp->if_serializer);
1882 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1884 ASSERT_SERIALIZED(ifp->if_serializer);
1885 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
1889 * Change media according to request.
1892 fxp_ifmedia_upd(struct ifnet *ifp)
1894 struct fxp_softc *sc = ifp->if_softc;
1895 struct mii_data *mii;
1897 ASSERT_SERIALIZED(ifp->if_serializer);
1899 mii = device_get_softc(sc->miibus);
1905 * Notify the world which media we're using.
1908 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1910 struct fxp_softc *sc = ifp->if_softc;
1911 struct mii_data *mii;
1913 ASSERT_SERIALIZED(ifp->if_serializer);
1915 mii = device_get_softc(sc->miibus);
1917 ifmr->ifm_active = mii->mii_media_active;
1918 ifmr->ifm_status = mii->mii_media_status;
1920 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG)
1921 sc->cu_resume_bug = 1;
1923 sc->cu_resume_bug = 0;
1927 * Add a buffer to the end of the RFA buffer list.
1928 * Return 0 if successful, 1 for failure. A failure results in
1929 * adding the 'oldm' (if non-NULL) on to the end of the list -
1930 * tossing out its old contents and recycling it.
1931 * The RFA struct is stuck at the beginning of mbuf cluster and the
1932 * data pointer is fixed up to point just past it.
1935 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm)
1939 struct fxp_rfa *rfa, *p_rfa;
1941 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1942 if (m == NULL) { /* try to recycle the old mbuf instead */
1946 m->m_data = m->m_ext.ext_buf;
1950 * Move the data pointer up so that the incoming data packet
1951 * will be 32-bit aligned.
1953 m->m_data += RFA_ALIGNMENT_FUDGE;
1956 * Get a pointer to the base of the mbuf cluster and move
1957 * data start past it.
1959 rfa = mtod(m, struct fxp_rfa *);
1960 m->m_data += sizeof(struct fxp_rfa);
1961 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) -
1962 RFA_ALIGNMENT_FUDGE);
1965 * Initialize the rest of the RFA. Note that since the RFA
1966 * is misaligned, we cannot store values directly. Instead,
1967 * we use an optimized, inline copy.
1970 rfa->rfa_status = 0;
1971 rfa->rfa_control = FXP_RFA_CONTROL_EL;
1972 rfa->actual_size = 0;
1975 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr);
1976 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr);
1979 * If there are other buffers already on the list, attach this
1980 * one to the end by fixing up the tail to point to this one.
1982 if (sc->rfa_headm != NULL) {
1983 p_rfa = (struct fxp_rfa *)(sc->rfa_tailm->m_ext.ext_buf +
1984 RFA_ALIGNMENT_FUDGE);
1985 sc->rfa_tailm->m_next = m;
1987 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr);
1988 p_rfa->rfa_control = 0;
1998 fxp_miibus_readreg(device_t dev, int phy, int reg)
2000 struct fxp_softc *sc = device_get_softc(dev);
2004 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2005 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2007 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2012 device_printf(dev, "fxp_miibus_readreg: timed out\n");
2014 return (value & 0xffff);
2018 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2020 struct fxp_softc *sc = device_get_softc(dev);
2023 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2024 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2027 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2032 device_printf(dev, "fxp_miibus_writereg: timed out\n");
2036 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2038 struct fxp_softc *sc = ifp->if_softc;
2039 struct ifreq *ifr = (struct ifreq *)data;
2040 struct mii_data *mii;
2043 ASSERT_SERIALIZED(ifp->if_serializer);
2048 if (ifp->if_flags & IFF_ALLMULTI)
2049 sc->flags |= FXP_FLAG_ALL_MCAST;
2051 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2054 * If interface is marked up and not running, then start it.
2055 * If it is marked down and running, stop it.
2056 * XXX If it's up then re-initialize it. This is so flags
2057 * such as IFF_PROMISC are handled.
2059 if (ifp->if_flags & IFF_UP) {
2062 if (ifp->if_flags & IFF_RUNNING)
2069 if (ifp->if_flags & IFF_ALLMULTI)
2070 sc->flags |= FXP_FLAG_ALL_MCAST;
2072 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2074 * Multicast list has changed; set the hardware filter
2077 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2080 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2081 * again rather than else {}.
2083 if (sc->flags & FXP_FLAG_ALL_MCAST)
2090 if (sc->miibus != NULL) {
2091 mii = device_get_softc(sc->miibus);
2092 error = ifmedia_ioctl(ifp, ifr,
2093 &mii->mii_media, command);
2095 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2100 error = ether_ioctl(ifp, command, data);
2107 * Fill in the multicast address list and return number of entries.
2110 fxp_mc_addrs(struct fxp_softc *sc)
2112 struct fxp_cb_mcs *mcsp = sc->mcsp;
2113 struct ifnet *ifp = &sc->arpcom.ac_if;
2114 struct ifmultiaddr *ifma;
2118 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2119 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2120 if (ifma->ifma_addr->sa_family != AF_LINK)
2122 if (nmcasts >= MAXMCADDR) {
2123 sc->flags |= FXP_FLAG_ALL_MCAST;
2127 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2128 (void *)(uintptr_t)(volatile void *)
2129 &sc->mcsp->mc_addr[nmcasts][0], 6);
2133 mcsp->mc_cnt = nmcasts * 6;
2138 * Program the multicast filter.
2140 * We have an artificial restriction that the multicast setup command
2141 * must be the first command in the chain, so we take steps to ensure
2142 * this. By requiring this, it allows us to keep up the performance of
2143 * the pre-initialized command ring (esp. link pointers) by not actually
2144 * inserting the mcsetup command in the ring - i.e. its link pointer
2145 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2146 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2147 * lead into the regular TxCB ring when it completes.
2149 * This function must be called at splimp.
2152 fxp_mc_setup(struct fxp_softc *sc)
2154 struct fxp_cb_mcs *mcsp = sc->mcsp;
2155 struct ifnet *ifp = &sc->arpcom.ac_if;
2159 * If there are queued commands, we must wait until they are all
2160 * completed. If we are already waiting, then add a NOP command
2161 * with interrupt option so that we're notified when all commands
2162 * have been completed - fxp_start() ensures that no additional
2163 * TX commands will be added when need_mcsetup is true.
2165 if (sc->tx_queued) {
2166 struct fxp_cb_tx *txp;
2169 * need_mcsetup will be true if we are already waiting for the
2170 * NOP command to be completed (see below). In this case, bail.
2172 if (sc->need_mcsetup)
2174 sc->need_mcsetup = 1;
2177 * Add a NOP command with interrupt so that we are notified
2178 * when all TX commands have been processed.
2180 txp = sc->cbl_last->next;
2181 txp->mb_head = NULL;
2183 txp->cb_command = FXP_CB_COMMAND_NOP |
2184 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2186 * Advance the end of list forward.
2188 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
2192 * Issue a resume in case the CU has just suspended.
2195 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2197 * Set a 5 second timer just in case we don't hear from the
2204 sc->need_mcsetup = 0;
2207 * Initialize multicast setup descriptor.
2209 mcsp->next = sc->cbl_base;
2210 mcsp->mb_head = NULL;
2211 mcsp->cb_status = 0;
2212 mcsp->cb_command = FXP_CB_COMMAND_MCAS |
2213 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2214 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status);
2216 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp;
2220 * Wait until command unit is not active. This should never
2221 * be the case when nothing is queued, but make sure anyway.
2224 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2225 FXP_SCB_CUS_ACTIVE && --count)
2228 if_printf(&sc->arpcom.ac_if, "command queue timeout\n");
2233 * Start the multicast setup command.
2236 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
2237 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2243 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
2244 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
2245 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
2246 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
2247 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
2248 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
2250 #define UCODE(x) x, sizeof(x)
2256 u_short int_delay_offset;
2257 u_short bundle_max_offset;
2259 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
2260 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
2261 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
2262 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
2263 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
2264 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
2265 { FXP_REV_82550, UCODE(fxp_ucode_d102),
2266 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
2267 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
2268 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
2269 { 0, NULL, 0, 0, 0 }
2273 fxp_load_ucode(struct fxp_softc *sc)
2276 struct fxp_cb_ucode *cbp;
2278 for (uc = ucode_table; uc->ucode != NULL; uc++)
2279 if (sc->revision == uc->revision)
2281 if (uc->ucode == NULL)
2283 cbp = (struct fxp_cb_ucode *)sc->cbl_base;
2285 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL;
2286 cbp->link_addr = -1; /* (no) next command */
2287 memcpy(cbp->ucode, uc->ucode, uc->length);
2288 if (uc->int_delay_offset)
2289 *(u_short *)&cbp->ucode[uc->int_delay_offset] =
2290 sc->tunable_int_delay + sc->tunable_int_delay / 2;
2291 if (uc->bundle_max_offset)
2292 *(u_short *)&cbp->ucode[uc->bundle_max_offset] =
2293 sc->tunable_bundle_max;
2295 * Download the ucode to the chip.
2298 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
2299 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2300 /* ...and wait for it to complete. */
2301 fxp_dma_wait(&cbp->cb_status, sc);
2302 if_printf(&sc->arpcom.ac_if,
2303 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
2304 sc->tunable_int_delay,
2305 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
2306 sc->flags |= FXP_FLAG_UCODE;
2310 * Interrupt delay is expressed in microseconds, a multiplier is used
2311 * to convert this to the appropriate clock ticks before using.
2314 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
2316 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
2320 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
2322 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));