2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $Id: ah_eeprom_v3.h,v 1.2 2008/11/10 04:08:00 sam Exp $
20 #ifndef _ATH_AH_EEPROM_V3_H_
21 #define _ATH_AH_EEPROM_V3_H_
23 #include "ah_eeprom.h"
25 /* EEPROM defines for Version 2 & 3 AR5211 chips */
26 #define AR_EEPROM_RFSILENT 0x0f /* RF Silent/Clock Run Enable */
27 #define AR_EEPROM_MAC(i) (0x1d+(i)) /* MAC address word */
28 #define AR_EEPROM_MAGIC 0x3d /* magic number */
29 #define AR_EEPROM_PROTECT 0x3f /* EEPROM protect bits */
30 #define AR_EEPROM_PROTECT_PCIE 0x01 /* EEPROM protect bits for Condor/Swan*/
31 #define AR_EEPROM_REG_DOMAIN 0xbf /* current regulatory domain */
32 #define AR_EEPROM_ATHEROS_BASE 0xc0 /* Base of Atheros-specific data */
33 #define AR_EEPROM_ATHEROS(i) (AR_EEPROM_ATHEROS_BASE+(i))
34 #define AR_EEPROM_ATHEROS_MAX (0x400-AR_EEPROM_ATHEROS_BASE)
35 #define AR_EEPROM_VERSION AR_EEPROM_ATHEROS(1)
37 /* FLASH(EEPROM) Defines for AR531X chips */
38 #define AR_EEPROM_SIZE_LOWER 0x1b /* size info -- lower */
39 #define AR_EEPROM_SIZE_UPPER 0x1c /* size info -- upper */
40 #define AR_EEPROM_SIZE_UPPER_MASK 0xfff0
41 #define AR_EEPROM_SIZE_UPPER_SHIFT 4
42 #define AR_EEPROM_SIZE_ENDLOC_SHIFT 12
43 #define AR_EEPROM_ATHEROS_MAX_LOC 0x400
44 #define AR_EEPROM_ATHEROS_MAX_OFF (AR_EEPROM_ATHEROS_MAX_LOC-AR_EEPROM_ATHEROS_BASE)
46 /* regulatory capabilities offsets */
47 #define AR_EEPROM_REG_CAPABILITIES_OFFSET 0xCA
48 #define AR_EEPROM_REG_CAPABILITIES_OFFSET_PRE4_0 0xCF /* prior to 4.0 */
50 /* regulatory capabilities */
51 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
52 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
53 #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
54 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
55 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
56 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
58 /* regulatory capabilities prior to eeprom version 4.0 */
59 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
60 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
63 * AR2413 (includes AR5413)
65 #define AR_EEPROM_SERIAL_NUM_OFFSET 0xB0 /* EEPROM serial number */
66 #define AR_EEPROM_SERIAL_NUM_SIZE 12 /* EEPROM serial number size */
67 #define AR_EEPROM_CAPABILITIES_OFFSET 0xC9 /* EEPROM Location of capabilities */
69 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
70 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002
71 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
72 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
73 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
74 #define AR_EEPROM_EEPCAP_MAXQCU_S 4
75 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
76 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
77 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
79 /* XXX used to index various EEPROM-derived data structures */
86 #define GROUPS_OFFSET3_2 0x100 /* groups offset for ver3.2 and earlier */
87 #define GROUPS_OFFSET3_3 0x150 /* groups offset for ver3.3 */
88 /* relative offset of GROUPi to GROUPS_OFFSET */
89 #define GROUP1_OFFSET 0x0
90 #define GROUP2_OFFSET 0x5
91 #define GROUP3_OFFSET 0x37
92 #define GROUP4_OFFSET 0x46
93 #define GROUP5_OFFSET 0x55
94 #define GROUP6_OFFSET 0x65
95 #define GROUP7_OFFSET 0x69
96 #define GROUP8_OFFSET 0x6f
98 /* RF silent fields in EEPROM */
99 #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
100 #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
101 #define AR_EEPROM_RFSILENT_POLARITY 0x0002
102 #define AR_EEPROM_RFSILENT_POLARITY_S 1
104 /* Protect Bits RP is read protect, WP is write protect */
105 #define AR_EEPROM_PROTECT_RP_0_31 0x0001
106 #define AR_EEPROM_PROTECT_WP_0_31 0x0002
107 #define AR_EEPROM_PROTECT_RP_32_63 0x0004
108 #define AR_EEPROM_PROTECT_WP_32_63 0x0008
109 #define AR_EEPROM_PROTECT_RP_64_127 0x0010
110 #define AR_EEPROM_PROTECT_WP_64_127 0x0020
111 #define AR_EEPROM_PROTECT_RP_128_191 0x0040
112 #define AR_EEPROM_PROTECT_WP_128_191 0x0080
113 #define AR_EEPROM_PROTECT_RP_192_207 0x0100
114 #define AR_EEPROM_PROTECT_WP_192_207 0x0200
115 #define AR_EEPROM_PROTECT_RP_208_223 0x0400
116 #define AR_EEPROM_PROTECT_WP_208_223 0x0800
117 #define AR_EEPROM_PROTECT_RP_224_239 0x1000
118 #define AR_EEPROM_PROTECT_WP_224_239 0x2000
119 #define AR_EEPROM_PROTECT_RP_240_255 0x4000
120 #define AR_EEPROM_PROTECT_WP_240_255 0x8000
122 #define AR_EEPROM_MODAL_SPURS 5
123 #define AR_SPUR_5413_1 1640 /* Freq 2464 */
124 #define AR_SPUR_5413_2 1200 /* Freq 2420 */
127 * EEPROM fixed point conversion scale factors.
128 * NB: if you change one be sure to keep the other in sync.
130 #define EEP_SCALE 100 /* conversion scale to avoid fp arith */
131 #define EEP_DELTA 10 /* SCALE/10, to avoid arith divide */
134 #define PWR_MAX 3150 /* 31.5 * SCALE */
135 #define PWR_STEP 50 /* 0.5 * SCALE */
136 /* Keep 2 above defines together */
138 #define NUM_11A_EEPROM_CHANNELS 10
139 #define NUM_2_4_EEPROM_CHANNELS 3
140 #define NUM_PCDAC_VALUES 11
141 #define NUM_TEST_FREQUENCIES 8
143 #define NUM_INTERCEPTS 11
144 #define FREQ_MASK 0x7f
145 #define FREQ_MASK_3_3 0xff /* expanded in version 3.3 */
146 #define PCDAC_MASK 0x3f
147 #define POWER_MASK 0x3f
148 #define NON_EDGE_FLAG_MASK 0x40
149 #define CHANNEL_POWER_INFO 8
150 #define OBDB_UNSET 0xffff
151 #define CHANNEL_UNUSED 0xff
152 #define SCALE_OC_DELTA(_x) (((_x) * 2) / 10)
154 /* Used during pcdac table construction */
155 #define PCDAC_START 1
156 #define PCDAC_STOP 63
158 #define PWR_TABLE_SIZE 64
159 #define MAX_RATE_POWER 63
161 /* Used during power/rate table construction */
163 #define NUM_CTLS_3_3 32 /* expanded in version 3.3 */
164 #define NUM_CTLS_MAX NUM_CTLS_3_3
166 typedef struct fullPcdacStruct {
167 uint16_t channelValue;
170 uint16_t numPcdacValues;
171 uint16_t PcdacValues[64];
172 /* power is 32bit since in dest it is scaled */
173 int16_t PwrValues[64];
176 typedef struct dataPerChannel {
177 uint16_t channelValue;
180 uint16_t numPcdacValues;
181 uint16_t PcdacValues[NUM_PCDAC_VALUES];
182 /* NB: power is 32bit since in dest it is scaled */
183 int16_t PwrValues[NUM_PCDAC_VALUES];
186 /* points to the appropriate pcdac structs in the above struct based on mode */
187 typedef struct pcdacsEeprom {
188 const uint16_t *pChannelList;
189 uint16_t numChannels;
190 const DATA_PER_CHANNEL *pDataPerChannel;
193 typedef struct trgtPowerInfo {
197 uint16_t twicePwr6_24;
198 uint16_t testChannel;
201 typedef struct trgtPowerAllModes {
202 uint16_t numTargetPwr_11a;
203 TRGT_POWER_INFO trgtPwr_11a[NUM_TEST_FREQUENCIES];
204 uint16_t numTargetPwr_11g;
205 TRGT_POWER_INFO trgtPwr_11g[3];
206 uint16_t numTargetPwr_11b;
207 TRGT_POWER_INFO trgtPwr_11b[2];
208 } TRGT_POWER_ALL_MODES;
210 typedef struct cornerCalInfo {
218 * EEPROM version 4 definitions
220 #define NUM_XPD_PER_CHANNEL 4
221 #define NUM_POINTS_XPD0 4
222 #define NUM_POINTS_XPD3 3
223 #define IDEAL_10dB_INTERCEPT_2G 35
224 #define IDEAL_10dB_INTERCEPT_5G 55
226 #define TENX_OFDM_CCK_DELTA_INIT 15 /* power 1.5 dbm */
227 #define TENX_CH14_FILTER_CCK_DELTA_INIT 15 /* power 1.5 dbm */
228 #define CCK_OFDM_GAIN_DELTA 15
230 #define NUM_TARGET_POWER_LOCATIONS_11B 4
231 #define NUM_TARGET_POWER_LOCATIONS_11G 6
237 uint16_t pcdac[NUM_POINTS_XPD0];
238 int16_t pwr_t4[NUM_POINTS_XPD0]; /* or gainF */
239 } EXPN_DATA_PER_XPD_5112;
242 uint16_t channelValue;
244 EXPN_DATA_PER_XPD_5112 pDataPerXPD[NUM_XPD_PER_CHANNEL];
245 } EXPN_DATA_PER_CHANNEL_5112;
249 uint16_t numChannels;
250 uint16_t xpdMask; /* mask of permitted xpd_gains */
251 EXPN_DATA_PER_CHANNEL_5112 *pDataPerChannel;
252 } EEPROM_POWER_EXPN_5112;
255 uint16_t channelValue;
258 uint16_t pcd2_delta_xg0;
260 uint16_t pcd3_delta_xg0;
262 uint16_t pcd4_delta_xg0;
265 int16_t pwr1_xg3; /* pcdac = 20 */
266 int16_t pwr2_xg3; /* pcdac = 35 */
267 int16_t pwr3_xg3; /* pcdac = 63 */
268 /* XXX - Should be pwr1_xg2, etc to agree with documentation */
269 } EEPROM_DATA_PER_CHANNEL_5112;
272 uint16_t pChannels[NUM_11A_EEPROM_CHANNELS];
273 uint16_t numChannels;
274 uint16_t xpdMask; /* mask of permitted xpd_gains */
275 EEPROM_DATA_PER_CHANNEL_5112 pDataPerChannel[NUM_11A_EEPROM_CHANNELS];
279 * EEPROM version 5 definitions (Griffin, et. al.).
281 #define NUM_2_4_EEPROM_CHANNELS_2413 4
282 #define NUM_11A_EEPROM_CHANNELS_2413 10
283 #define PWR_TABLE_SIZE_2413 128
285 /* Used during pdadc construction */
286 #define MAX_NUM_PDGAINS_PER_CHANNEL 4
287 #define NUM_PDGAINS_PER_CHANNEL 2
288 #define NUM_POINTS_LAST_PDGAIN 5
289 #define NUM_POINTS_OTHER_PDGAINS 4
290 #define XPD_GAIN1_GEN5 3
291 #define XPD_GAIN2_GEN5 1
292 #define MAX_PWR_RANGE_IN_HALF_DB 64
293 #define PD_GAIN_BOUNDARY_STRETCH_IN_HALF_DB 4
298 uint16_t Vpd[NUM_POINTS_LAST_PDGAIN];
299 int16_t pwr_t4[NUM_POINTS_LAST_PDGAIN]; /* or gainF */
300 } RAW_DATA_PER_PDGAIN_2413;
303 uint16_t channelValue;
305 uint16_t numPdGains; /* # Pd Gains per channel */
306 RAW_DATA_PER_PDGAIN_2413 pDataPerPDGain[MAX_NUM_PDGAINS_PER_CHANNEL];
307 } RAW_DATA_PER_CHANNEL_2413;
309 /* XXX: assumes NUM_11A_EEPROM_CHANNELS_2413 >= NUM_2_4_EEPROM_CHANNELS_2413 ??? */
311 uint16_t pChannels[NUM_11A_EEPROM_CHANNELS_2413];
312 uint16_t numChannels;
313 uint16_t xpd_mask; /* mask of permitted xpd_gains */
314 RAW_DATA_PER_CHANNEL_2413 pDataPerChannel[NUM_11A_EEPROM_CHANNELS_2413];
315 } RAW_DATA_STRUCT_2413;
318 uint16_t channelValue;
320 uint16_t Vpd_I[MAX_NUM_PDGAINS_PER_CHANNEL];
321 int16_t pwr_I[MAX_NUM_PDGAINS_PER_CHANNEL];
322 uint16_t Vpd_delta[NUM_POINTS_LAST_PDGAIN]
323 [MAX_NUM_PDGAINS_PER_CHANNEL];
324 int16_t pwr_delta_t2[NUM_POINTS_LAST_PDGAIN]
325 [MAX_NUM_PDGAINS_PER_CHANNEL];
327 } EEPROM_DATA_PER_CHANNEL_2413;
330 uint16_t pChannels[NUM_11A_EEPROM_CHANNELS_2413];
331 uint16_t numChannels;
332 uint16_t xpd_mask; /* mask of permitted xpd_gains */
333 EEPROM_DATA_PER_CHANNEL_2413 pDataPerChannel[NUM_11A_EEPROM_CHANNELS_2413];
334 } EEPROM_DATA_STRUCT_2413;
337 * Information retrieved from EEPROM.
340 uint16_t ee_version; /* Version field */
341 uint16_t ee_protect; /* EEPROM protect field */
342 uint16_t ee_regdomain; /* Regulatory domain */
344 /* General Device Parameters */
345 uint16_t ee_turbo5Disable;
346 uint16_t ee_turbo2Disable;
348 uint16_t ee_deviceType;
349 uint16_t ee_turbo2WMaxPower5;
350 uint16_t ee_turbo2WMaxPower2;
351 uint16_t ee_xrTargetPower5;
352 uint16_t ee_xrTargetPower2;
357 int8_t ee_antennaGainMax[2];
358 uint16_t ee_xtnd5GSupport;
359 uint8_t ee_cckOfdmPwrDelta;
360 uint8_t ee_exist32kHzCrystal;
361 uint16_t ee_targetPowersStart;
362 uint16_t ee_fixedBias5;
363 uint16_t ee_fixedBias2;
364 uint16_t ee_cckOfdmGainDelta;
365 uint16_t ee_scaledCh14FilterCckDelta;
367 uint16_t ee_earStart;
369 /* 5 GHz / 2.4 GHz CKK / 2.4 GHz OFDM common parameters */
370 uint16_t ee_switchSettling[3];
371 uint16_t ee_txrxAtten[3];
372 uint16_t ee_txEndToXLNAOn[3];
373 uint16_t ee_thresh62[3];
374 uint16_t ee_txEndToXPAOff[3];
375 uint16_t ee_txFrameToXPAOn[3];
376 int8_t ee_adcDesiredSize[3]; /* 8-bit signed value */
377 int8_t ee_pgaDesiredSize[3]; /* 8-bit signed value */
378 int16_t ee_noiseFloorThresh[3];
379 uint16_t ee_xlnaGain[3];
380 uint16_t ee_xgain[3];
382 uint16_t ee_antennaControl[11][3];
383 uint16_t ee_falseDetectBackoff[3];
384 uint16_t ee_gainI[3];
385 uint16_t ee_rxtxMargin[3];
387 /* new parameters added for the AR2413 */
388 HAL_BOOL ee_disableXr5;
389 HAL_BOOL ee_disableXr2;
390 uint16_t ee_eepMap2PowerCalStart;
391 uint16_t ee_capField;
393 uint16_t ee_switchSettlingTurbo[2];
394 uint16_t ee_txrxAttenTurbo[2];
395 int8_t ee_adcDesiredSizeTurbo[2];
396 int8_t ee_pgaDesiredSizeTurbo[2];
397 uint16_t ee_rxtxMarginTurbo[2];
399 /* 5 GHz parameters */
409 /* 2.4 GHz parameters */
412 uint16_t ee_obFor24g;
413 uint16_t ee_dbFor24g;
414 uint16_t ee_ob2GHz[2];
415 uint16_t ee_db2GHz[2];
417 uint16_t ee_ctl[NUM_CTLS_MAX];
418 uint16_t ee_iqCalI[2];
419 uint16_t ee_iqCalQ[2];
420 uint16_t ee_calPier11g[NUM_2_4_EEPROM_CHANNELS];
421 uint16_t ee_calPier11b[NUM_2_4_EEPROM_CHANNELS];
423 /* corner calibration information */
424 CORNER_CAL_INFO ee_cornerCal;
429 uint16_t ee_channels11a[NUM_11A_EEPROM_CHANNELS];
430 uint16_t ee_numChannels11a;
431 DATA_PER_CHANNEL ee_dataPerChannel11a[NUM_11A_EEPROM_CHANNELS];
433 uint16_t ee_numChannels2_4;
434 uint16_t ee_channels11g[NUM_2_4_EEPROM_CHANNELS];
435 uint16_t ee_channels11b[NUM_2_4_EEPROM_CHANNELS];
436 uint16_t ee_spurChans[AR_EEPROM_MODAL_SPURS][2];
439 DATA_PER_CHANNEL ee_dataPerChannel11g[NUM_2_4_EEPROM_CHANNELS];
442 DATA_PER_CHANNEL ee_dataPerChannel11b[NUM_2_4_EEPROM_CHANNELS];
444 TRGT_POWER_ALL_MODES ee_tpow;
446 RD_EDGES_POWER ee_rdEdgesPower[NUM_EDGES*NUM_CTLS_MAX];
449 EEPROM_POWER_EXPN_5112 eu_modePowerArray5112[3];
450 RAW_DATA_STRUCT_2413 eu_rawDataset2413[3];
454 /* write-around defines */
455 #define ee_numTargetPwr_11a ee_tpow.numTargetPwr_11a
456 #define ee_trgtPwr_11a ee_tpow.trgtPwr_11a
457 #define ee_numTargetPwr_11g ee_tpow.numTargetPwr_11g
458 #define ee_trgtPwr_11g ee_tpow.trgtPwr_11g
459 #define ee_numTargetPwr_11b ee_tpow.numTargetPwr_11b
460 #define ee_trgtPwr_11b ee_tpow.trgtPwr_11b
461 #define ee_modePowerArray5112 ee_u.eu_modePowerArray5112
462 #define ee_rawDataset2413 ee_u.eu_rawDataset2413
463 #endif /* _ATH_AH_EEPROM_V3_H_ */