83bf0e59ae361516acf9d444aeb5a4f896ca65ee
[dragonfly.git] / sys / dev / netif / bge / if_bge.c
1 /*
2  * Copyright (c) 2001 Wind River Systems
3  * Copyright (c) 1997, 1998, 1999, 2001
4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *      This product includes software developed by Bill Paul.
17  * 4. Neither the name of the author nor the names of any co-contributors
18  *    may be used to endorse or promote products derived from this software
19  *    without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31  * THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
34  */
35
36 /*
37  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
38  * 
39  * Written by Bill Paul <wpaul@windriver.com>
40  * Senior Engineer, Wind River Systems
41  */
42
43 /*
44  * The Broadcom BCM5700 is based on technology originally developed by
45  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
46  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
47  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
48  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
49  * frames, highly configurable RX filtering, and 16 RX and TX queues
50  * (which, along with RX filter rules, can be used for QOS applications).
51  * Other features, such as TCP segmentation, may be available as part
52  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
53  * firmware images can be stored in hardware and need not be compiled
54  * into the driver.
55  *
56  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
57  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
58  * 
59  * The BCM5701 is a single-chip solution incorporating both the BCM5700
60  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
61  * does not support external SSRAM.
62  *
63  * Broadcom also produces a variation of the BCM5700 under the "Altima"
64  * brand name, which is functionally similar but lacks PCI-X support.
65  *
66  * Without external SSRAM, you can only have at most 4 TX rings,
67  * and the use of the mini RX ring is disabled. This seems to imply
68  * that these features are simply not available on the BCM5701. As a
69  * result, this driver does not implement any support for the mini RX
70  * ring.
71  */
72
73 #include "opt_polling.h"
74
75 #include <sys/param.h>
76 #include <sys/bus.h>
77 #include <sys/endian.h>
78 #include <sys/kernel.h>
79 #include <sys/ktr.h>
80 #include <sys/interrupt.h>
81 #include <sys/mbuf.h>
82 #include <sys/malloc.h>
83 #include <sys/queue.h>
84 #include <sys/rman.h>
85 #include <sys/serialize.h>
86 #include <sys/socket.h>
87 #include <sys/sockio.h>
88 #include <sys/sysctl.h>
89
90 #include <net/bpf.h>
91 #include <net/ethernet.h>
92 #include <net/if.h>
93 #include <net/if_arp.h>
94 #include <net/if_dl.h>
95 #include <net/if_media.h>
96 #include <net/if_types.h>
97 #include <net/ifq_var.h>
98 #include <net/vlan/if_vlan_var.h>
99 #include <net/vlan/if_vlan_ether.h>
100
101 #include <dev/netif/mii_layer/mii.h>
102 #include <dev/netif/mii_layer/miivar.h>
103 #include <dev/netif/mii_layer/brgphyreg.h>
104
105 #include <bus/pci/pcidevs.h>
106 #include <bus/pci/pcireg.h>
107 #include <bus/pci/pcivar.h>
108
109 #include <dev/netif/bge/if_bgereg.h>
110 #include <dev/netif/bge/if_bgevar.h>
111
112 /* "device miibus" required.  See GENERIC if you get errors here. */
113 #include "miibus_if.h"
114
115 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP)
116
117 static const struct bge_type {
118         uint16_t                bge_vid;
119         uint16_t                bge_did;
120         char                    *bge_name;
121 } bge_devs[] = {
122         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
123                 "3COM 3C996 Gigabit Ethernet" },
124
125         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
126                 "Alteon BCM5700 Gigabit Ethernet" },
127         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
128                 "Alteon BCM5701 Gigabit Ethernet" },
129
130         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
131                 "Altima AC1000 Gigabit Ethernet" },
132         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
133                 "Altima AC1002 Gigabit Ethernet" },
134         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
135                 "Altima AC9100 Gigabit Ethernet" },
136
137         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
138                 "Apple BCM5701 Gigabit Ethernet" },
139
140         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
141                 "Broadcom BCM5700 Gigabit Ethernet" },
142         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
143                 "Broadcom BCM5701 Gigabit Ethernet" },
144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
145                 "Broadcom BCM5702 Gigabit Ethernet" },
146         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
147                 "Broadcom BCM5702X Gigabit Ethernet" },
148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
149                 "Broadcom BCM5702 Gigabit Ethernet" },
150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
151                 "Broadcom BCM5703 Gigabit Ethernet" },
152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
153                 "Broadcom BCM5703X Gigabit Ethernet" },
154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
155                 "Broadcom BCM5703 Gigabit Ethernet" },
156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
157                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
159                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
160         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
161                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
163                 "Broadcom BCM5705 Gigabit Ethernet" },
164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
165                 "Broadcom BCM5705F Gigabit Ethernet" },
166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
167                 "Broadcom BCM5705K Gigabit Ethernet" },
168         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
169                 "Broadcom BCM5705M Gigabit Ethernet" },
170         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
171                 "Broadcom BCM5705M Gigabit Ethernet" },
172         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
173                 "Broadcom BCM5714C Gigabit Ethernet" },
174         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
175                 "Broadcom BCM5714S Gigabit Ethernet" },
176         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
177                 "Broadcom BCM5715 Gigabit Ethernet" },
178         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
179                 "Broadcom BCM5715S Gigabit Ethernet" },
180         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
181                 "Broadcom BCM5720 Gigabit Ethernet" },
182         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
183                 "Broadcom BCM5721 Gigabit Ethernet" },
184         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
185                 "Broadcom BCM5722 Gigabit Ethernet" },
186         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723,
187                 "Broadcom BCM5723 Gigabit Ethernet" },
188         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
189                 "Broadcom BCM5750 Gigabit Ethernet" },
190         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
191                 "Broadcom BCM5750M Gigabit Ethernet" },
192         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
193                 "Broadcom BCM5751 Gigabit Ethernet" },
194         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
195                 "Broadcom BCM5751F Gigabit Ethernet" },
196         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
197                 "Broadcom BCM5751M Gigabit Ethernet" },
198         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
199                 "Broadcom BCM5752 Gigabit Ethernet" },
200         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
201                 "Broadcom BCM5752M Gigabit Ethernet" },
202         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
203                 "Broadcom BCM5753 Gigabit Ethernet" },
204         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
205                 "Broadcom BCM5753F Gigabit Ethernet" },
206         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
207                 "Broadcom BCM5753M Gigabit Ethernet" },
208         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
209                 "Broadcom BCM5754 Gigabit Ethernet" },
210         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
211                 "Broadcom BCM5754M Gigabit Ethernet" },
212         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
213                 "Broadcom BCM5755 Gigabit Ethernet" },
214         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
215                 "Broadcom BCM5755M Gigabit Ethernet" },
216         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
217                 "Broadcom BCM5756 Gigabit Ethernet" },
218         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761,
219                 "Broadcom BCM5761 Gigabit Ethernet" },
220         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E,
221                 "Broadcom BCM5761E Gigabit Ethernet" },
222         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S,
223                 "Broadcom BCM5761S Gigabit Ethernet" },
224         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE,
225                 "Broadcom BCM5761SE Gigabit Ethernet" },
226         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764,
227                 "Broadcom BCM5764 Gigabit Ethernet" },
228         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
229                 "Broadcom BCM5780 Gigabit Ethernet" },
230         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
231                 "Broadcom BCM5780S Gigabit Ethernet" },
232         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
233                 "Broadcom BCM5781 Gigabit Ethernet" },
234         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
235                 "Broadcom BCM5782 Gigabit Ethernet" },
236         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784,
237                 "Broadcom BCM5784 Gigabit Ethernet" },
238         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F,
239                 "Broadcom BCM5785F Gigabit Ethernet" },
240         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G,
241                 "Broadcom BCM5785G Gigabit Ethernet" },
242         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
243                 "Broadcom BCM5786 Gigabit Ethernet" },
244         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
245                 "Broadcom BCM5787 Gigabit Ethernet" },
246         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
247                 "Broadcom BCM5787F Gigabit Ethernet" },
248         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
249                 "Broadcom BCM5787M Gigabit Ethernet" },
250         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
251                 "Broadcom BCM5788 Gigabit Ethernet" },
252         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
253                 "Broadcom BCM5789 Gigabit Ethernet" },
254         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
255                 "Broadcom BCM5901 Fast Ethernet" },
256         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
257                 "Broadcom BCM5901A2 Fast Ethernet" },
258         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
259                 "Broadcom BCM5903M Fast Ethernet" },
260         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
261                 "Broadcom BCM5906 Fast Ethernet"},
262         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
263                 "Broadcom BCM5906M Fast Ethernet"},
264         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760,
265                 "Broadcom BCM57760 Gigabit Ethernet"},
266         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780,
267                 "Broadcom BCM57780 Gigabit Ethernet"},
268         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788,
269                 "Broadcom BCM57788 Gigabit Ethernet"},
270         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790,
271                 "Broadcom BCM57790 Gigabit Ethernet"},
272         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
273                 "SysKonnect Gigabit Ethernet" },
274
275         { 0, 0, NULL }
276 };
277
278 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
279 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
280 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
281 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
282 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
283 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
284 #define BGE_IS_5788(sc)                 ((sc)->bge_flags & BGE_FLAG_5788)
285
286 #define BGE_IS_CRIPPLED(sc)             \
287         (BGE_IS_5788((sc)) || (sc)->bge_asicrev == BGE_ASICREV_BCM5700)
288
289 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
290
291 static int      bge_probe(device_t);
292 static int      bge_attach(device_t);
293 static int      bge_detach(device_t);
294 static void     bge_txeof(struct bge_softc *, uint16_t);
295 static void     bge_rxeof(struct bge_softc *, uint16_t);
296
297 static void     bge_tick(void *);
298 static void     bge_stats_update(struct bge_softc *);
299 static void     bge_stats_update_regs(struct bge_softc *);
300 static struct mbuf *
301                 bge_defrag_shortdma(struct mbuf *);
302 static int      bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
303
304 #ifdef DEVICE_POLLING
305 static void     bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
306 #endif
307 static void     bge_intr_crippled(void *);
308 static void     bge_intr_legacy(void *);
309 static void     bge_msi(void *);
310 static void     bge_msi_oneshot(void *);
311 static void     bge_intr(struct bge_softc *);
312 static void     bge_enable_intr(struct bge_softc *);
313 static void     bge_disable_intr(struct bge_softc *);
314 static void     bge_start(struct ifnet *);
315 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
316 static void     bge_init(void *);
317 static void     bge_stop(struct bge_softc *);
318 static void     bge_watchdog(struct ifnet *);
319 static void     bge_shutdown(device_t);
320 static int      bge_suspend(device_t);
321 static int      bge_resume(device_t);
322 static int      bge_ifmedia_upd(struct ifnet *);
323 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
324
325 static uint8_t  bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
326 static int      bge_read_nvram(struct bge_softc *, caddr_t, int, int);
327
328 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
329 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
330
331 static void     bge_setmulti(struct bge_softc *);
332 static void     bge_setpromisc(struct bge_softc *);
333 static void     bge_enable_msi(struct bge_softc *sc);
334
335 static int      bge_alloc_jumbo_mem(struct bge_softc *);
336 static void     bge_free_jumbo_mem(struct bge_softc *);
337 static struct bge_jslot
338                 *bge_jalloc(struct bge_softc *);
339 static void     bge_jfree(void *);
340 static void     bge_jref(void *);
341 static int      bge_newbuf_std(struct bge_softc *, int, int);
342 static int      bge_newbuf_jumbo(struct bge_softc *, int, int);
343 static void     bge_setup_rxdesc_std(struct bge_softc *, int);
344 static void     bge_setup_rxdesc_jumbo(struct bge_softc *, int);
345 static int      bge_init_rx_ring_std(struct bge_softc *);
346 static void     bge_free_rx_ring_std(struct bge_softc *);
347 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
348 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
349 static void     bge_free_tx_ring(struct bge_softc *);
350 static int      bge_init_tx_ring(struct bge_softc *);
351
352 static int      bge_chipinit(struct bge_softc *);
353 static int      bge_blockinit(struct bge_softc *);
354 static void     bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
355
356 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
357 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
358 #ifdef notdef
359 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
360 #endif
361 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
362 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
363 static void     bge_writembx(struct bge_softc *, int, int);
364
365 static int      bge_miibus_readreg(device_t, int, int);
366 static int      bge_miibus_writereg(device_t, int, int, int);
367 static void     bge_miibus_statchg(device_t);
368 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
369 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
370 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
371 static void     bge_autopoll_link_upd(struct bge_softc *, uint32_t);
372 static void     bge_link_poll(struct bge_softc *);
373
374 static void     bge_reset(struct bge_softc *);
375
376 static int      bge_dma_alloc(struct bge_softc *);
377 static void     bge_dma_free(struct bge_softc *);
378 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
379                                     bus_dma_tag_t *, bus_dmamap_t *,
380                                     void **, bus_addr_t *);
381 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
382
383 static int      bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
384 static int      bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
385 static int      bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
386 static int      bge_get_eaddr(struct bge_softc *, uint8_t[]);
387
388 static void     bge_coal_change(struct bge_softc *);
389 static int      bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
390 static int      bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
391 static int      bge_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
392 static int      bge_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
393 static int      bge_sysctl_rx_coal_ticks_int(SYSCTL_HANDLER_ARGS);
394 static int      bge_sysctl_tx_coal_ticks_int(SYSCTL_HANDLER_ARGS);
395 static int      bge_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
396 static int      bge_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
397 static int      bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
398                     int, int, uint32_t);
399
400 /*
401  * Set following tunable to 1 for some IBM blade servers with the DNLK
402  * switch module. Auto negotiation is broken for those configurations.
403  */
404 static int      bge_fake_autoneg = 0;
405 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
406
407 static int      bge_msi_enable = 1;
408 TUNABLE_INT("hw.bge.msi.enable", &bge_msi_enable);
409
410 #if !defined(KTR_IF_BGE)
411 #define KTR_IF_BGE      KTR_ALL
412 #endif
413 KTR_INFO_MASTER(if_bge);
414 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr");
415 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt");
416 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt");
417 #define logif(name)     KTR_LOG(if_bge_ ## name)
418
419 static device_method_t bge_methods[] = {
420         /* Device interface */
421         DEVMETHOD(device_probe,         bge_probe),
422         DEVMETHOD(device_attach,        bge_attach),
423         DEVMETHOD(device_detach,        bge_detach),
424         DEVMETHOD(device_shutdown,      bge_shutdown),
425         DEVMETHOD(device_suspend,       bge_suspend),
426         DEVMETHOD(device_resume,        bge_resume),
427
428         /* bus interface */
429         DEVMETHOD(bus_print_child,      bus_generic_print_child),
430         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
431
432         /* MII interface */
433         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
434         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
435         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
436
437         { 0, 0 }
438 };
439
440 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
441 static devclass_t bge_devclass;
442
443 DECLARE_DUMMY_MODULE(if_bge);
444 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL);
445 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL);
446
447 static uint32_t
448 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
449 {
450         device_t dev = sc->bge_dev;
451         uint32_t val;
452
453         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
454             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
455                 return 0;
456
457         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
458         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
459         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
460         return (val);
461 }
462
463 static void
464 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
465 {
466         device_t dev = sc->bge_dev;
467
468         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
469             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
470                 return;
471
472         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
473         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
474         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
475 }
476
477 #ifdef notdef
478 static uint32_t
479 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
480 {
481         device_t dev = sc->bge_dev;
482
483         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
484         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
485 }
486 #endif
487
488 static void
489 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
490 {
491         device_t dev = sc->bge_dev;
492
493         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
494         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
495 }
496
497 static void
498 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
499 {
500         CSR_WRITE_4(sc, off, val);
501 }
502
503 static void
504 bge_writembx(struct bge_softc *sc, int off, int val)
505 {
506         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
507                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
508
509         CSR_WRITE_4(sc, off, val);
510         if (sc->bge_mbox_reorder)
511                 CSR_READ_4(sc, off);
512 }
513
514 static uint8_t
515 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
516 {
517         uint32_t access, byte = 0;
518         int i;
519
520         /* Lock. */
521         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
522         for (i = 0; i < 8000; i++) {
523                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
524                         break;
525                 DELAY(20);
526         }
527         if (i == 8000)
528                 return (1);
529
530         /* Enable access. */
531         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
532         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
533
534         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
535         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
536         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
537                 DELAY(10);
538                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
539                         DELAY(10);
540                         break;
541                 }
542         }
543
544         if (i == BGE_TIMEOUT * 10) {
545                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
546                 return (1);
547         }
548
549         /* Get result. */
550         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
551
552         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
553
554         /* Disable access. */
555         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
556
557         /* Unlock. */
558         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
559         CSR_READ_4(sc, BGE_NVRAM_SWARB);
560
561         return (0);
562 }
563
564 /*
565  * Read a sequence of bytes from NVRAM.
566  */
567 static int
568 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
569 {
570         int err = 0, i;
571         uint8_t byte = 0;
572
573         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
574                 return (1);
575
576         for (i = 0; i < cnt; i++) {
577                 err = bge_nvram_getbyte(sc, off + i, &byte);
578                 if (err)
579                         break;
580                 *(dest + i) = byte;
581         }
582
583         return (err ? 1 : 0);
584 }
585
586 /*
587  * Read a byte of data stored in the EEPROM at address 'addr.' The
588  * BCM570x supports both the traditional bitbang interface and an
589  * auto access interface for reading the EEPROM. We use the auto
590  * access method.
591  */
592 static uint8_t
593 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
594 {
595         int i;
596         uint32_t byte = 0;
597
598         /*
599          * Enable use of auto EEPROM access so we can avoid
600          * having to use the bitbang method.
601          */
602         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
603
604         /* Reset the EEPROM, load the clock period. */
605         CSR_WRITE_4(sc, BGE_EE_ADDR,
606             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
607         DELAY(20);
608
609         /* Issue the read EEPROM command. */
610         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
611
612         /* Wait for completion */
613         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
614                 DELAY(10);
615                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
616                         break;
617         }
618
619         if (i == BGE_TIMEOUT) {
620                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
621                 return(1);
622         }
623
624         /* Get result. */
625         byte = CSR_READ_4(sc, BGE_EE_DATA);
626
627         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
628
629         return(0);
630 }
631
632 /*
633  * Read a sequence of bytes from the EEPROM.
634  */
635 static int
636 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
637 {
638         size_t i;
639         int err;
640         uint8_t byte;
641
642         for (byte = 0, err = 0, i = 0; i < len; i++) {
643                 err = bge_eeprom_getbyte(sc, off + i, &byte);
644                 if (err)
645                         break;
646                 *(dest + i) = byte;
647         }
648
649         return(err ? 1 : 0);
650 }
651
652 static int
653 bge_miibus_readreg(device_t dev, int phy, int reg)
654 {
655         struct bge_softc *sc = device_get_softc(dev);
656         uint32_t val;
657         int i;
658
659         KASSERT(phy == sc->bge_phyno,
660             ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
661
662         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
663         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
664                 CSR_WRITE_4(sc, BGE_MI_MODE,
665                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
666                 DELAY(80);
667         }
668
669         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
670             BGE_MIPHY(phy) | BGE_MIREG(reg));
671
672         /* Poll for the PHY register access to complete. */
673         for (i = 0; i < BGE_TIMEOUT; i++) {
674                 DELAY(10);
675                 val = CSR_READ_4(sc, BGE_MI_COMM);
676                 if ((val & BGE_MICOMM_BUSY) == 0) {
677                         DELAY(5);
678                         val = CSR_READ_4(sc, BGE_MI_COMM);
679                         break;
680                 }
681         }
682         if (i == BGE_TIMEOUT) {
683                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
684                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
685                 val = 0;
686         }
687
688         /* Restore the autopoll bit if necessary. */
689         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
690                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
691                 DELAY(80);
692         }
693
694         if (val & BGE_MICOMM_READFAIL)
695                 return 0;
696
697         return (val & 0xFFFF);
698 }
699
700 static int
701 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
702 {
703         struct bge_softc *sc = device_get_softc(dev);
704         int i;
705
706         KASSERT(phy == sc->bge_phyno,
707             ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
708
709         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
710             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
711                return 0;
712
713         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
714         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
715                 CSR_WRITE_4(sc, BGE_MI_MODE,
716                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
717                 DELAY(80);
718         }
719
720         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
721             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
722
723         for (i = 0; i < BGE_TIMEOUT; i++) {
724                 DELAY(10);
725                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
726                         DELAY(5);
727                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
728                         break;
729                 }
730         }
731         if (i == BGE_TIMEOUT) {
732                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
733                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
734         }
735
736         /* Restore the autopoll bit if necessary. */
737         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
738                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
739                 DELAY(80);
740         }
741
742         return 0;
743 }
744
745 static void
746 bge_miibus_statchg(device_t dev)
747 {
748         struct bge_softc *sc;
749         struct mii_data *mii;
750
751         sc = device_get_softc(dev);
752         mii = device_get_softc(sc->bge_miibus);
753
754         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
755             (IFM_ACTIVE | IFM_AVALID)) {
756                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
757                 case IFM_10_T:
758                 case IFM_100_TX:
759                         sc->bge_link = 1;
760                         break;
761                 case IFM_1000_T:
762                 case IFM_1000_SX:
763                 case IFM_2500_SX:
764                         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
765                                 sc->bge_link = 1;
766                         else
767                                 sc->bge_link = 0;
768                         break;
769                 default:
770                         sc->bge_link = 0;
771                         break;
772                 }
773         } else {
774                 sc->bge_link = 0;
775         }
776         if (sc->bge_link == 0)
777                 return;
778
779         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
780         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
781             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
782                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
783         } else {
784                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
785         }
786
787         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
788                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
789         } else {
790                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
791         }
792 }
793
794 /*
795  * Memory management for jumbo frames.
796  */
797 static int
798 bge_alloc_jumbo_mem(struct bge_softc *sc)
799 {
800         struct ifnet *ifp = &sc->arpcom.ac_if;
801         struct bge_jslot *entry;
802         uint8_t *ptr;
803         bus_addr_t paddr;
804         int i, error;
805
806         /*
807          * Create tag for jumbo mbufs.
808          * This is really a bit of a kludge. We allocate a special
809          * jumbo buffer pool which (thanks to the way our DMA
810          * memory allocation works) will consist of contiguous
811          * pages. This means that even though a jumbo buffer might
812          * be larger than a page size, we don't really need to
813          * map it into more than one DMA segment. However, the
814          * default mbuf tag will result in multi-segment mappings,
815          * so we have to create a special jumbo mbuf tag that
816          * lets us get away with mapping the jumbo buffers as
817          * a single segment. I think eventually the driver should
818          * be changed so that it uses ordinary mbufs and cluster
819          * buffers, i.e. jumbo frames can span multiple DMA
820          * descriptors. But that's a project for another day.
821          */
822
823         /*
824          * Create DMA stuffs for jumbo RX ring.
825          */
826         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
827                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
828                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
829                                     (void *)&sc->bge_ldata.bge_rx_jumbo_ring,
830                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
831         if (error) {
832                 if_printf(ifp, "could not create jumbo RX ring\n");
833                 return error;
834         }
835
836         /*
837          * Create DMA stuffs for jumbo buffer block.
838          */
839         error = bge_dma_block_alloc(sc, BGE_JMEM,
840                                     &sc->bge_cdata.bge_jumbo_tag,
841                                     &sc->bge_cdata.bge_jumbo_map,
842                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
843                                     &paddr);
844         if (error) {
845                 if_printf(ifp, "could not create jumbo buffer\n");
846                 return error;
847         }
848
849         SLIST_INIT(&sc->bge_jfree_listhead);
850
851         /*
852          * Now divide it up into 9K pieces and save the addresses
853          * in an array. Note that we play an evil trick here by using
854          * the first few bytes in the buffer to hold the the address
855          * of the softc structure for this interface. This is because
856          * bge_jfree() needs it, but it is called by the mbuf management
857          * code which will not pass it to us explicitly.
858          */
859         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
860                 entry = &sc->bge_cdata.bge_jslots[i];
861                 entry->bge_sc = sc;
862                 entry->bge_buf = ptr;
863                 entry->bge_paddr = paddr;
864                 entry->bge_inuse = 0;
865                 entry->bge_slot = i;
866                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
867
868                 ptr += BGE_JLEN;
869                 paddr += BGE_JLEN;
870         }
871         return 0;
872 }
873
874 static void
875 bge_free_jumbo_mem(struct bge_softc *sc)
876 {
877         /* Destroy jumbo RX ring. */
878         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
879                            sc->bge_cdata.bge_rx_jumbo_ring_map,
880                            sc->bge_ldata.bge_rx_jumbo_ring);
881
882         /* Destroy jumbo buffer block. */
883         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
884                            sc->bge_cdata.bge_jumbo_map,
885                            sc->bge_ldata.bge_jumbo_buf);
886 }
887
888 /*
889  * Allocate a jumbo buffer.
890  */
891 static struct bge_jslot *
892 bge_jalloc(struct bge_softc *sc)
893 {
894         struct bge_jslot *entry;
895
896         lwkt_serialize_enter(&sc->bge_jslot_serializer);
897         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
898         if (entry) {
899                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
900                 entry->bge_inuse = 1;
901         } else {
902                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
903         }
904         lwkt_serialize_exit(&sc->bge_jslot_serializer);
905         return(entry);
906 }
907
908 /*
909  * Adjust usage count on a jumbo buffer.
910  */
911 static void
912 bge_jref(void *arg)
913 {
914         struct bge_jslot *entry = (struct bge_jslot *)arg;
915         struct bge_softc *sc = entry->bge_sc;
916
917         if (sc == NULL)
918                 panic("bge_jref: can't find softc pointer!");
919
920         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
921                 panic("bge_jref: asked to reference buffer "
922                     "that we don't manage!");
923         } else if (entry->bge_inuse == 0) {
924                 panic("bge_jref: buffer already free!");
925         } else {
926                 atomic_add_int(&entry->bge_inuse, 1);
927         }
928 }
929
930 /*
931  * Release a jumbo buffer.
932  */
933 static void
934 bge_jfree(void *arg)
935 {
936         struct bge_jslot *entry = (struct bge_jslot *)arg;
937         struct bge_softc *sc = entry->bge_sc;
938
939         if (sc == NULL)
940                 panic("bge_jfree: can't find softc pointer!");
941
942         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
943                 panic("bge_jfree: asked to free buffer that we don't manage!");
944         } else if (entry->bge_inuse == 0) {
945                 panic("bge_jfree: buffer already free!");
946         } else {
947                 /*
948                  * Possible MP race to 0, use the serializer.  The atomic insn
949                  * is still needed for races against bge_jref().
950                  */
951                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
952                 atomic_subtract_int(&entry->bge_inuse, 1);
953                 if (entry->bge_inuse == 0) {
954                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 
955                                           entry, jslot_link);
956                 }
957                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
958         }
959 }
960
961
962 /*
963  * Intialize a standard receive ring descriptor.
964  */
965 static int
966 bge_newbuf_std(struct bge_softc *sc, int i, int init)
967 {
968         struct mbuf *m_new = NULL;
969         bus_dma_segment_t seg;
970         bus_dmamap_t map;
971         int error, nsegs;
972
973         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
974         if (m_new == NULL)
975                 return ENOBUFS;
976         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
977
978         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
979                 m_adj(m_new, ETHER_ALIGN);
980
981         error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag,
982                         sc->bge_cdata.bge_rx_tmpmap, m_new,
983                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
984         if (error) {
985                 m_freem(m_new);
986                 return error;
987         }
988
989         if (!init) {
990                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
991                                 sc->bge_cdata.bge_rx_std_dmamap[i],
992                                 BUS_DMASYNC_POSTREAD);
993                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
994                         sc->bge_cdata.bge_rx_std_dmamap[i]);
995         }
996
997         map = sc->bge_cdata.bge_rx_tmpmap;
998         sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i];
999         sc->bge_cdata.bge_rx_std_dmamap[i] = map;
1000
1001         sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new;
1002         sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr;
1003
1004         bge_setup_rxdesc_std(sc, i);
1005         return 0;
1006 }
1007
1008 static void
1009 bge_setup_rxdesc_std(struct bge_softc *sc, int i)
1010 {
1011         struct bge_rxchain *rc;
1012         struct bge_rx_bd *r;
1013
1014         rc = &sc->bge_cdata.bge_rx_std_chain[i];
1015         r = &sc->bge_ldata.bge_rx_std_ring[i];
1016
1017         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1018         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1019         r->bge_len = rc->bge_mbuf->m_len;
1020         r->bge_idx = i;
1021         r->bge_flags = BGE_RXBDFLAG_END;
1022 }
1023
1024 /*
1025  * Initialize a jumbo receive ring descriptor. This allocates
1026  * a jumbo buffer from the pool managed internally by the driver.
1027  */
1028 static int
1029 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init)
1030 {
1031         struct mbuf *m_new = NULL;
1032         struct bge_jslot *buf;
1033         bus_addr_t paddr;
1034
1035         /* Allocate the mbuf. */
1036         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1037         if (m_new == NULL)
1038                 return ENOBUFS;
1039
1040         /* Allocate the jumbo buffer */
1041         buf = bge_jalloc(sc);
1042         if (buf == NULL) {
1043                 m_freem(m_new);
1044                 return ENOBUFS;
1045         }
1046
1047         /* Attach the buffer to the mbuf. */
1048         m_new->m_ext.ext_arg = buf;
1049         m_new->m_ext.ext_buf = buf->bge_buf;
1050         m_new->m_ext.ext_free = bge_jfree;
1051         m_new->m_ext.ext_ref = bge_jref;
1052         m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1053
1054         m_new->m_flags |= M_EXT;
1055
1056         m_new->m_data = m_new->m_ext.ext_buf;
1057         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1058
1059         paddr = buf->bge_paddr;
1060         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
1061                 m_adj(m_new, ETHER_ALIGN);
1062                 paddr += ETHER_ALIGN;
1063         }
1064
1065         /* Save necessary information */
1066         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new;
1067         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr;
1068
1069         /* Set up the descriptor. */
1070         bge_setup_rxdesc_jumbo(sc, i);
1071         return 0;
1072 }
1073
1074 static void
1075 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i)
1076 {
1077         struct bge_rx_bd *r;
1078         struct bge_rxchain *rc;
1079
1080         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1081         rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1082
1083         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1084         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1085         r->bge_len = rc->bge_mbuf->m_len;
1086         r->bge_idx = i;
1087         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1088 }
1089
1090 static int
1091 bge_init_rx_ring_std(struct bge_softc *sc)
1092 {
1093         int i, error;
1094
1095         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1096                 error = bge_newbuf_std(sc, i, 1);
1097                 if (error)
1098                         return error;
1099         };
1100
1101         sc->bge_std = BGE_STD_RX_RING_CNT - 1;
1102         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1103
1104         return(0);
1105 }
1106
1107 static void
1108 bge_free_rx_ring_std(struct bge_softc *sc)
1109 {
1110         int i;
1111
1112         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1113                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i];
1114
1115                 if (rc->bge_mbuf != NULL) {
1116                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1117                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
1118                         m_freem(rc->bge_mbuf);
1119                         rc->bge_mbuf = NULL;
1120                 }
1121                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
1122                     sizeof(struct bge_rx_bd));
1123         }
1124 }
1125
1126 static int
1127 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1128 {
1129         struct bge_rcb *rcb;
1130         int i, error;
1131
1132         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1133                 error = bge_newbuf_jumbo(sc, i, 1);
1134                 if (error)
1135                         return error;
1136         };
1137
1138         sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
1139
1140         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1141         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1142         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1143
1144         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1145
1146         return(0);
1147 }
1148
1149 static void
1150 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1151 {
1152         int i;
1153
1154         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1155                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1156
1157                 if (rc->bge_mbuf != NULL) {
1158                         m_freem(rc->bge_mbuf);
1159                         rc->bge_mbuf = NULL;
1160                 }
1161                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1162                     sizeof(struct bge_rx_bd));
1163         }
1164 }
1165
1166 static void
1167 bge_free_tx_ring(struct bge_softc *sc)
1168 {
1169         int i;
1170
1171         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1172                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1173                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1174                                           sc->bge_cdata.bge_tx_dmamap[i]);
1175                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1176                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1177                 }
1178                 bzero(&sc->bge_ldata.bge_tx_ring[i],
1179                     sizeof(struct bge_tx_bd));
1180         }
1181 }
1182
1183 static int
1184 bge_init_tx_ring(struct bge_softc *sc)
1185 {
1186         sc->bge_txcnt = 0;
1187         sc->bge_tx_saved_considx = 0;
1188         sc->bge_tx_prodidx = 0;
1189
1190         /* Initialize transmit producer index for host-memory send ring. */
1191         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1192
1193         /* 5700 b2 errata */
1194         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1195                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1196
1197         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1198         /* 5700 b2 errata */
1199         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1200                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1201
1202         return(0);
1203 }
1204
1205 static void
1206 bge_setmulti(struct bge_softc *sc)
1207 {
1208         struct ifnet *ifp;
1209         struct ifmultiaddr *ifma;
1210         uint32_t hashes[4] = { 0, 0, 0, 0 };
1211         int h, i;
1212
1213         ifp = &sc->arpcom.ac_if;
1214
1215         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1216                 for (i = 0; i < 4; i++)
1217                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1218                 return;
1219         }
1220
1221         /* First, zot all the existing filters. */
1222         for (i = 0; i < 4; i++)
1223                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1224
1225         /* Now program new ones. */
1226         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1227                 if (ifma->ifma_addr->sa_family != AF_LINK)
1228                         continue;
1229                 h = ether_crc32_le(
1230                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1231                     ETHER_ADDR_LEN) & 0x7f;
1232                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1233         }
1234
1235         for (i = 0; i < 4; i++)
1236                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1237 }
1238
1239 /*
1240  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1241  * self-test results.
1242  */
1243 static int
1244 bge_chipinit(struct bge_softc *sc)
1245 {
1246         int i;
1247         uint32_t dma_rw_ctl;
1248         uint16_t val;
1249
1250         /* Set endian type before we access any non-PCI registers. */
1251         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
1252             BGE_INIT | sc->bge_pci_miscctl, 4);
1253
1254         /* Clear the MAC control register */
1255         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1256
1257         /*
1258          * Clear the MAC statistics block in the NIC's
1259          * internal memory.
1260          */
1261         for (i = BGE_STATS_BLOCK;
1262             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1263                 BGE_MEMWIN_WRITE(sc, i, 0);
1264
1265         for (i = BGE_STATUS_BLOCK;
1266             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1267                 BGE_MEMWIN_WRITE(sc, i, 0);
1268
1269         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1270                 /*
1271                  * Fix data corruption caused by non-qword write with WB.
1272                  * Fix master abort in PCI mode.
1273                  * Fix PCI latency timer.
1274                  */
1275                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1276                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1277                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1278         }
1279
1280         /* Set up the PCI DMA control register. */
1281         dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD;
1282         if (sc->bge_flags & BGE_FLAG_PCIE) {
1283                 /* PCI-E bus */
1284                 /* DMA read watermark not used on PCI-E */
1285                 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1286         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1287                 /* PCI-X bus */
1288                 if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1289                         dma_rw_ctl |= (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1290                             (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1291                         dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1292                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5714) {
1293                         dma_rw_ctl |= (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1294                             (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1295                         dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1296                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1297                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1298                         uint32_t rd_wat = 0x7;
1299                         uint32_t clkctl;
1300
1301                         clkctl = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1302                         if ((sc->bge_flags & BGE_FLAG_MAXADDR_40BIT) &&
1303                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1304                                 dma_rw_ctl |=
1305                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1306                         } else if (clkctl == 0x6 || clkctl == 0x7) {
1307                                 dma_rw_ctl |=
1308                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1309                         }
1310                         if (sc->bge_asicrev == BGE_ASICREV_BCM5703)
1311                                 rd_wat = 0x4;
1312
1313                         dma_rw_ctl |= (rd_wat << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1314                             (3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1315                         dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1316                 } else {
1317                         dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1318                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1319                         dma_rw_ctl |= 0xf;
1320                 }
1321         } else {
1322                 /* Conventional PCI bus */
1323                 dma_rw_ctl |= (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1324                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1325                 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1326                     sc->bge_asicrev != BGE_ASICREV_BCM5750)
1327                         dma_rw_ctl |= 0xf;
1328         }
1329
1330         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1331             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1332                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1333         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1334             sc->bge_asicrev == BGE_ASICREV_BCM5701) {
1335                 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1336                     BGE_PCIDMARWCTL_ASRT_ALL_BE;
1337         }
1338         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1339
1340         /*
1341          * Set up general mode register.
1342          */
1343         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1344             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1345             BGE_MODECTL_TX_NO_PHDR_CSUM);
1346
1347         /*
1348          * BCM5701 B5 have a bug causing data corruption when using
1349          * 64-bit DMA reads, which can be terminated early and then
1350          * completed later as 32-bit accesses, in combination with
1351          * certain bridges.
1352          */
1353         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1354             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1355                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1356
1357         /*
1358          * Disable memory write invalidate.  Apparently it is not supported
1359          * properly by these devices.  Also ensure that INTx isn't disabled,
1360          * as these chips need it even when using MSI.
1361          */
1362         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1363             (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1364
1365         /* Set the timer prescaler (always 66Mhz) */
1366         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1367
1368         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1369                 DELAY(40);      /* XXX */
1370
1371                 /* Put PHY into ready state */
1372                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1373                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1374                 DELAY(40);
1375         }
1376
1377         return(0);
1378 }
1379
1380 static int
1381 bge_blockinit(struct bge_softc *sc)
1382 {
1383         struct bge_rcb *rcb;
1384         bus_size_t vrcb;
1385         bge_hostaddr taddr;
1386         uint32_t val;
1387         int i, limit;
1388
1389         /*
1390          * Initialize the memory window pointer register so that
1391          * we can access the first 32K of internal NIC RAM. This will
1392          * allow us to set up the TX send ring RCBs and the RX return
1393          * ring RCBs, plus other things which live in NIC memory.
1394          */
1395         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1396
1397         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1398
1399         if (!BGE_IS_5705_PLUS(sc)) {
1400                 /* Configure mbuf memory pool */
1401                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1402                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1403                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1404                 else
1405                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1406
1407                 /* Configure DMA resource pool */
1408                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1409                     BGE_DMA_DESCRIPTORS);
1410                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1411         }
1412
1413         /* Configure mbuf pool watermarks */
1414         if (!BGE_IS_5705_PLUS(sc)) {
1415                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1416                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1417                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1418         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1419                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1420                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1421                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1422         } else {
1423                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1424                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1425                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1426         }
1427
1428         /* Configure DMA resource watermarks */
1429         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1430         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1431
1432         /* Enable buffer manager */
1433         CSR_WRITE_4(sc, BGE_BMAN_MODE,
1434             BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1435
1436         /* Poll for buffer manager start indication */
1437         for (i = 0; i < BGE_TIMEOUT; i++) {
1438                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1439                         break;
1440                 DELAY(10);
1441         }
1442
1443         if (i == BGE_TIMEOUT) {
1444                 if_printf(&sc->arpcom.ac_if,
1445                           "buffer manager failed to start\n");
1446                 return(ENXIO);
1447         }
1448
1449         /* Enable flow-through queues */
1450         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1451         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1452
1453         /* Wait until queue initialization is complete */
1454         for (i = 0; i < BGE_TIMEOUT; i++) {
1455                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1456                         break;
1457                 DELAY(10);
1458         }
1459
1460         if (i == BGE_TIMEOUT) {
1461                 if_printf(&sc->arpcom.ac_if,
1462                           "flow-through queue init failed\n");
1463                 return(ENXIO);
1464         }
1465
1466         /*
1467          * Summary of rings supported by the controller:
1468          *
1469          * Standard Receive Producer Ring
1470          * - This ring is used to feed receive buffers for "standard"
1471          *   sized frames (typically 1536 bytes) to the controller.
1472          *
1473          * Jumbo Receive Producer Ring
1474          * - This ring is used to feed receive buffers for jumbo sized
1475          *   frames (i.e. anything bigger than the "standard" frames)
1476          *   to the controller.
1477          *
1478          * Mini Receive Producer Ring
1479          * - This ring is used to feed receive buffers for "mini"
1480          *   sized frames to the controller.
1481          * - This feature required external memory for the controller
1482          *   but was never used in a production system.  Should always
1483          *   be disabled.
1484          *
1485          * Receive Return Ring
1486          * - After the controller has placed an incoming frame into a
1487          *   receive buffer that buffer is moved into a receive return
1488          *   ring.  The driver is then responsible to passing the
1489          *   buffer up to the stack.  Many versions of the controller
1490          *   support multiple RR rings.
1491          *
1492          * Send Ring
1493          * - This ring is used for outgoing frames.  Many versions of
1494          *   the controller support multiple send rings.
1495          */
1496
1497         /* Initialize the standard receive producer ring control block. */
1498         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1499         rcb->bge_hostaddr.bge_addr_lo =
1500             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1501         rcb->bge_hostaddr.bge_addr_hi =
1502             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1503         if (BGE_IS_5705_PLUS(sc)) {
1504                 /*
1505                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1506                  * Bits 15-2 : Reserved (should be 0)
1507                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1508                  * Bit 0     : Reserved
1509                  */
1510                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1511         } else {
1512                 /*
1513                  * Ring size is always XXX entries
1514                  * Bits 31-16: Maximum RX frame size
1515                  * Bits 15-2 : Reserved (should be 0)
1516                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1517                  * Bit 0     : Reserved
1518                  */
1519                 rcb->bge_maxlen_flags =
1520                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1521         }
1522         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1523         /* Write the standard receive producer ring control block. */
1524         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1525         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1526         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1527         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1528         /* Reset the standard receive producer ring producer index. */
1529         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1530
1531         /*
1532          * Initialize the jumbo RX producer ring control
1533          * block.  We set the 'ring disabled' bit in the
1534          * flags field until we're actually ready to start
1535          * using this ring (i.e. once we set the MTU
1536          * high enough to require it).
1537          */
1538         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1539                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1540                 /* Get the jumbo receive producer ring RCB parameters. */
1541                 rcb->bge_hostaddr.bge_addr_lo =
1542                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1543                 rcb->bge_hostaddr.bge_addr_hi =
1544                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1545                 rcb->bge_maxlen_flags =
1546                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1547                     BGE_RCB_FLAG_RING_DISABLED);
1548                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1549                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1550                     rcb->bge_hostaddr.bge_addr_hi);
1551                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1552                     rcb->bge_hostaddr.bge_addr_lo);
1553                 /* Program the jumbo receive producer ring RCB parameters. */
1554                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1555                     rcb->bge_maxlen_flags);
1556                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1557                 /* Reset the jumbo receive producer ring producer index. */
1558                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1559         }
1560
1561         /* Disable the mini receive producer ring RCB. */
1562         if (BGE_IS_5700_FAMILY(sc)) {
1563                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1564                 rcb->bge_maxlen_flags =
1565                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1566                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1567                     rcb->bge_maxlen_flags);
1568                 /* Reset the mini receive producer ring producer index. */
1569                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1570         }
1571
1572         /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
1573         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1574             (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
1575              sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
1576              sc->bge_chipid == BGE_CHIPID_BCM5906_A2)) {
1577                 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
1578                     (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
1579         }
1580
1581         /*
1582          * The BD ring replenish thresholds control how often the
1583          * hardware fetches new BD's from the producer rings in host
1584          * memory.  Setting the value too low on a busy system can
1585          * starve the hardware and recue the throughpout.
1586          *
1587          * Set the BD ring replentish thresholds. The recommended
1588          * values are 1/8th the number of descriptors allocated to
1589          * each ring.
1590          */
1591         if (BGE_IS_5705_PLUS(sc))
1592                 val = 8;
1593         else
1594                 val = BGE_STD_RX_RING_CNT / 8;
1595         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1596         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1597                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1598                     BGE_JUMBO_RX_RING_CNT/8);
1599         }
1600
1601         /*
1602          * Disable all send rings by setting the 'ring disabled' bit
1603          * in the flags field of all the TX send ring control blocks,
1604          * located in NIC memory.
1605          */
1606         if (!BGE_IS_5705_PLUS(sc)) {
1607                 /* 5700 to 5704 had 16 send rings. */
1608                 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
1609         } else {
1610                 limit = 1;
1611         }
1612         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1613         for (i = 0; i < limit; i++) {
1614                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1615                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1616                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1617                 vrcb += sizeof(struct bge_rcb);
1618         }
1619
1620         /* Configure send ring RCB 0 (we use only the first ring) */
1621         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1622         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1623         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1624         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1625         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1626             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1627         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1628             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1629
1630         /*
1631          * Disable all receive return rings by setting the
1632          * 'ring diabled' bit in the flags field of all the receive
1633          * return ring control blocks, located in NIC memory.
1634          */
1635         if (!BGE_IS_5705_PLUS(sc))
1636                 limit = BGE_RX_RINGS_MAX;
1637         else if (sc->bge_asicrev == BGE_ASICREV_BCM5755)
1638                 limit = 4;
1639         else
1640                 limit = 1;
1641         /* Disable all receive return rings. */
1642         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1643         for (i = 0; i < limit; i++) {
1644                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1645                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1646                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1647                     BGE_RCB_FLAG_RING_DISABLED);
1648                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1649                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1650                     (i * (sizeof(uint64_t))), 0);
1651                 vrcb += sizeof(struct bge_rcb);
1652         }
1653
1654         /*
1655          * Set up receive return ring 0.  Note that the NIC address
1656          * for RX return rings is 0x0.  The return rings live entirely
1657          * within the host, so the nicaddr field in the RCB isn't used.
1658          */
1659         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1660         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1661         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1662         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1663         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1664         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1665             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1666
1667         /* Set random backoff seed for TX */
1668         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1669             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1670             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1671             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1672             BGE_TX_BACKOFF_SEED_MASK);
1673
1674         /* Set inter-packet gap */
1675         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1676
1677         /*
1678          * Specify which ring to use for packets that don't match
1679          * any RX rules.
1680          */
1681         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1682
1683         /*
1684          * Configure number of RX lists. One interrupt distribution
1685          * list, sixteen active lists, one bad frames class.
1686          */
1687         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1688
1689         /* Inialize RX list placement stats mask. */
1690         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1691         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1692
1693         /* Disable host coalescing until we get it set up */
1694         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1695
1696         /* Poll to make sure it's shut down. */
1697         for (i = 0; i < BGE_TIMEOUT; i++) {
1698                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1699                         break;
1700                 DELAY(10);
1701         }
1702
1703         if (i == BGE_TIMEOUT) {
1704                 if_printf(&sc->arpcom.ac_if,
1705                           "host coalescing engine failed to idle\n");
1706                 return(ENXIO);
1707         }
1708
1709         /* Set up host coalescing defaults */
1710         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1711         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1712         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_coal_bds);
1713         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_coal_bds);
1714         if (!BGE_IS_5705_PLUS(sc)) {
1715                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT,
1716                     sc->bge_rx_coal_ticks_int);
1717                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT,
1718                     sc->bge_tx_coal_ticks_int);
1719         }
1720         /*
1721          * NOTE:
1722          * The datasheet (57XX-PG105-R) says BCM5705+ do not
1723          * have following two registers; obviously it is wrong.
1724          */
1725         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bge_rx_coal_bds_int);
1726         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bge_tx_coal_bds_int);
1727
1728         /* Set up address of statistics block */
1729         if (!BGE_IS_5705_PLUS(sc)) {
1730                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1731                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1732                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1733                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1734
1735                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1736                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1737                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1738         }
1739
1740         /* Set up address of status block */
1741         bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
1742         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1743             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1744         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1745             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1746
1747         /*
1748          * Set up status block partail update size.
1749          *
1750          * Because only single TX ring, RX produce ring and Rx return ring
1751          * are used, ask device to update only minimum part of status block
1752          * except for BCM5700 AX/BX, whose status block partial update size
1753          * can't be configured.
1754          */
1755         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1756             sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
1757                 /* XXX Actually reserved on BCM5700 AX/BX */
1758                 val = BGE_STATBLKSZ_FULL;
1759         } else {
1760                 val = BGE_STATBLKSZ_32BYTE;
1761         }
1762 #if 0
1763         /*
1764          * Does not seem to have visible effect in both
1765          * bulk data (1472B UDP datagram) and tiny data
1766          * (18B UDP datagram) TX tests.
1767          */
1768         if (!BGE_IS_CRIPPLED(sc))
1769                 val |= BGE_HCCMODE_CLRTICK_TX;
1770 #endif
1771
1772         /* Turn on host coalescing state machine */
1773         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1774
1775         /* Turn on RX BD completion state machine and enable attentions */
1776         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1777             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1778
1779         /* Turn on RX list placement state machine */
1780         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1781
1782         /* Turn on RX list selector state machine. */
1783         if (!BGE_IS_5705_PLUS(sc))
1784                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1785
1786         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1787             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1788             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1789             BGE_MACMODE_FRMHDR_DMA_ENB;
1790
1791         if (sc->bge_flags & BGE_FLAG_TBI)
1792                 val |= BGE_PORTMODE_TBI;
1793         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1794                 val |= BGE_PORTMODE_GMII;
1795         else
1796                 val |= BGE_PORTMODE_MII;
1797
1798         /* Turn on DMA, clear stats */
1799         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1800
1801         /* Set misc. local control, enable interrupts on attentions */
1802         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1803
1804 #ifdef notdef
1805         /* Assert GPIO pins for PHY reset */
1806         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1807             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1808         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1809             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1810 #endif
1811
1812         /* Turn on DMA completion state machine */
1813         if (!BGE_IS_5705_PLUS(sc))
1814                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1815
1816         /* Turn on write DMA state machine */
1817         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1818         if (BGE_IS_5755_PLUS(sc)) {
1819                 /* Enable host coalescing bug fix. */
1820                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1821         }
1822         if (sc->bge_asicrev == BGE_ASICREV_BCM5785) {
1823                 /* Request larger DMA burst size to get better performance. */
1824                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1825         }
1826         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1827         DELAY(40);
1828
1829         if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
1830             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1831             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1832             sc->bge_asicrev == BGE_ASICREV_BCM57780) {
1833                 /*
1834                  * Enable fix for read DMA FIFO overruns.
1835                  * The fix is to limit the number of RX BDs
1836                  * the hardware would fetch at a fime.
1837                  */
1838                 val = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
1839                 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
1840                     val| BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1841         }
1842
1843         /* Turn on read DMA state machine */
1844         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1845         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1846             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1847             sc->bge_asicrev == BGE_ASICREV_BCM57780)
1848                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1849                   BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1850                   BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1851         if (sc->bge_flags & BGE_FLAG_PCIE)
1852                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1853         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1854         DELAY(40);
1855
1856         /* Turn on RX data completion state machine */
1857         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1858
1859         /* Turn on RX BD initiator state machine */
1860         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1861
1862         /* Turn on RX data and RX BD initiator state machine */
1863         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1864
1865         /* Turn on Mbuf cluster free state machine */
1866         if (!BGE_IS_5705_PLUS(sc))
1867                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1868
1869         /* Turn on send BD completion state machine */
1870         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1871
1872         /* Turn on send data completion state machine */
1873         val = BGE_SDCMODE_ENABLE;
1874         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1875                 val |= BGE_SDCMODE_CDELAY; 
1876         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1877
1878         /* Turn on send data initiator state machine */
1879         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1880
1881         /* Turn on send BD initiator state machine */
1882         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1883
1884         /* Turn on send BD selector state machine */
1885         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1886
1887         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1888         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1889             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1890
1891         /* ack/clear link change events */
1892         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1893             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1894             BGE_MACSTAT_LINK_CHANGED);
1895         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1896
1897         /*
1898          * Enable attention when the link has changed state for
1899          * devices that use auto polling.
1900          */
1901         if (sc->bge_flags & BGE_FLAG_TBI) {
1902                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1903         } else {
1904                 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
1905                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1906                         DELAY(80);
1907                 }
1908                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1909                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1910                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1911                             BGE_EVTENB_MI_INTERRUPT);
1912                 }
1913         }
1914
1915         /*
1916          * Clear any pending link state attention.
1917          * Otherwise some link state change events may be lost until attention
1918          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1919          * It's not necessary on newer BCM chips - perhaps enabling link
1920          * state change attentions implies clearing pending attention.
1921          */
1922         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1923             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1924             BGE_MACSTAT_LINK_CHANGED);
1925
1926         /* Enable link state change attentions. */
1927         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1928
1929         return(0);
1930 }
1931
1932 /*
1933  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1934  * against our list and return its name if we find a match. Note
1935  * that since the Broadcom controller contains VPD support, we
1936  * can get the device name string from the controller itself instead
1937  * of the compiled-in string. This is a little slow, but it guarantees
1938  * we'll always announce the right product name.
1939  */
1940 static int
1941 bge_probe(device_t dev)
1942 {
1943         const struct bge_type *t;
1944         uint16_t product, vendor;
1945
1946         product = pci_get_device(dev);
1947         vendor = pci_get_vendor(dev);
1948
1949         for (t = bge_devs; t->bge_name != NULL; t++) {
1950                 if (vendor == t->bge_vid && product == t->bge_did)
1951                         break;
1952         }
1953         if (t->bge_name == NULL)
1954                 return(ENXIO);
1955
1956         device_set_desc(dev, t->bge_name);
1957         return(0);
1958 }
1959
1960 static int
1961 bge_attach(device_t dev)
1962 {
1963         struct ifnet *ifp;
1964         struct bge_softc *sc;
1965         uint32_t hwcfg = 0, misccfg;
1966         int error = 0, rid, capmask;
1967         uint8_t ether_addr[ETHER_ADDR_LEN];
1968         uint16_t product, vendor;
1969         driver_intr_t *intr_func;
1970         uintptr_t mii_priv = 0;
1971         u_int intr_flags;
1972         int msi_enable;
1973
1974         sc = device_get_softc(dev);
1975         sc->bge_dev = dev;
1976         callout_init(&sc->bge_stat_timer);
1977         lwkt_serialize_init(&sc->bge_jslot_serializer);
1978
1979 #ifndef BURN_BRIDGES
1980         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1981                 uint32_t irq, mem;
1982
1983                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1984                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1985
1986                 device_printf(dev, "chip is in D%d power mode "
1987                     "-- setting to D0\n", pci_get_powerstate(dev));
1988
1989                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1990
1991                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1992                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1993         }
1994 #endif  /* !BURN_BRIDGE */
1995
1996         /*
1997          * Map control/status registers.
1998          */
1999         pci_enable_busmaster(dev);
2000
2001         rid = BGE_PCI_BAR0;
2002         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2003             RF_ACTIVE);
2004
2005         if (sc->bge_res == NULL) {
2006                 device_printf(dev, "couldn't map memory\n");
2007                 return ENXIO;
2008         }
2009
2010         sc->bge_btag = rman_get_bustag(sc->bge_res);
2011         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
2012
2013         /* Save various chip information */
2014         sc->bge_chipid =
2015             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2016             BGE_PCIMISCCTL_ASICREV_SHIFT;
2017         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) {
2018                 /* All chips, which use BGE_PCI_PRODID_ASICREV, have CPMU */
2019                 sc->bge_flags |= BGE_FLAG_CPMU;
2020                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
2021         }
2022         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2023         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2024
2025         /* Save chipset family. */
2026         switch (sc->bge_asicrev) {
2027         case BGE_ASICREV_BCM5755:
2028         case BGE_ASICREV_BCM5761:
2029         case BGE_ASICREV_BCM5784:
2030         case BGE_ASICREV_BCM5785:
2031         case BGE_ASICREV_BCM5787:
2032         case BGE_ASICREV_BCM57780:
2033             sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2034                 BGE_FLAG_5705_PLUS;
2035             break;
2036
2037         case BGE_ASICREV_BCM5700:
2038         case BGE_ASICREV_BCM5701:
2039         case BGE_ASICREV_BCM5703:
2040         case BGE_ASICREV_BCM5704:
2041                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2042                 break;
2043
2044         case BGE_ASICREV_BCM5714_A0:
2045         case BGE_ASICREV_BCM5780:
2046         case BGE_ASICREV_BCM5714:
2047                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
2048                 /* Fall through */
2049
2050         case BGE_ASICREV_BCM5750:
2051         case BGE_ASICREV_BCM5752:
2052         case BGE_ASICREV_BCM5906:
2053                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2054                 /* Fall through */
2055
2056         case BGE_ASICREV_BCM5705:
2057                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2058                 break;
2059         }
2060
2061         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
2062                 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
2063
2064         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
2065         if (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2066             (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2067              misccfg == BGE_MISCCFG_BOARD_ID_5788M))
2068                 sc->bge_flags |= BGE_FLAG_5788;
2069
2070         /* BCM5755 or higher and BCM5906 have short DMA bug. */
2071         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
2072                 sc->bge_flags |= BGE_FLAG_SHORTDMA;
2073
2074         /*
2075          * Check if this is a PCI-X or PCI Express device.
2076          */
2077         if (BGE_IS_5705_PLUS(sc)) {
2078                 if (pci_is_pcie(dev)) {
2079                         sc->bge_flags |= BGE_FLAG_PCIE;
2080                         sc->bge_pciecap = pci_get_pciecap_ptr(sc->bge_dev);
2081                         pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
2082                 }
2083         } else {
2084                 /*
2085                  * Check if the device is in PCI-X Mode.
2086                  * (This bit is not valid on PCI Express controllers.)
2087                  */
2088                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
2089                     BGE_PCISTATE_PCI_BUSMODE) == 0) {
2090                         sc->bge_flags |= BGE_FLAG_PCIX;
2091                         sc->bge_pcixcap = pci_get_pcixcap_ptr(sc->bge_dev);
2092                         sc->bge_mbox_reorder = device_getenv_int(sc->bge_dev,
2093                             "mbox_reorder", 0);
2094                 }
2095         }
2096         device_printf(dev, "CHIP ID 0x%08x; "
2097                       "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
2098                       sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
2099                       (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
2100                       : ((sc->bge_flags & BGE_FLAG_PCIE) ?
2101                         "PCI-E" : "PCI"));
2102
2103         /*
2104          * The 40bit DMA bug applies to the 5714/5715 controllers and is
2105          * not actually a MAC controller bug but an issue with the embedded
2106          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2107          */
2108         if ((sc->bge_flags & BGE_FLAG_PCIX) &&
2109             (BGE_IS_5714_FAMILY(sc) || device_getenv_int(dev, "dma40b", 0)))
2110                 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT;
2111
2112         /*
2113          * When using the BCM5701 in PCI-X mode, data corruption has
2114          * been observed in the first few bytes of some received packets.
2115          * Aligning the packet buffer in memory eliminates the corruption.
2116          * Unfortunately, this misaligns the packet payloads.  On platforms
2117          * which do not support unaligned accesses, we will realign the
2118          * payloads by copying the received packets.
2119          */
2120         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2121             (sc->bge_flags & BGE_FLAG_PCIX))
2122                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2123
2124         if (!BGE_IS_CRIPPLED(sc)) {
2125                 if (device_getenv_int(dev, "status_tag", 1)) {
2126                         sc->bge_flags |= BGE_FLAG_STATUS_TAG;
2127                         sc->bge_pci_miscctl = BGE_PCIMISCCTL_TAGGED_STATUS;
2128                         if (bootverbose)
2129                                 device_printf(dev, "enable status tag\n");
2130                 }
2131         }
2132
2133         /*
2134          * Set various PHY quirk flags.
2135          */
2136         product = pci_get_device(dev);
2137         vendor = pci_get_vendor(dev);
2138
2139         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2140              sc->bge_asicrev == BGE_ASICREV_BCM5701) &&
2141             pci_get_subvendor(dev) == PCI_VENDOR_DELL)
2142                 mii_priv |= BRGPHY_FLAG_NO_3LED;
2143
2144         capmask = MII_CAPMASK_DEFAULT;
2145         if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
2146              (misccfg == 0x4000 || misccfg == 0x8000)) ||
2147             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2148              vendor == PCI_VENDOR_BROADCOM &&
2149              (product == PCI_PRODUCT_BROADCOM_BCM5901 ||
2150               product == PCI_PRODUCT_BROADCOM_BCM5901A2 ||
2151               product == PCI_PRODUCT_BROADCOM_BCM5705F)) ||
2152             (vendor == PCI_VENDOR_BROADCOM &&
2153              (product == PCI_PRODUCT_BROADCOM_BCM5751F ||
2154               product == PCI_PRODUCT_BROADCOM_BCM5753F ||
2155               product == PCI_PRODUCT_BROADCOM_BCM5787F)) ||
2156             product == PCI_PRODUCT_BROADCOM_BCM57790 ||
2157             sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2158                 /* 10/100 only */
2159                 capmask &= ~BMSR_EXTSTAT;
2160         }
2161
2162         mii_priv |= BRGPHY_FLAG_WIRESPEED;
2163         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2164             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2165              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2166               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
2167             sc->bge_asicrev == BGE_ASICREV_BCM5906)
2168                 mii_priv &= ~BRGPHY_FLAG_WIRESPEED;
2169
2170         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2171             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2172                 mii_priv |= BRGPHY_FLAG_CRC_BUG;
2173
2174         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2175             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2176                 mii_priv |= BRGPHY_FLAG_ADC_BUG;
2177
2178         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2179                 mii_priv |= BRGPHY_FLAG_5704_A0;
2180
2181         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
2182                 mii_priv |= BRGPHY_FLAG_5906;
2183
2184         if (BGE_IS_5705_PLUS(sc) &&
2185             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2186             /* sc->bge_asicrev != BGE_ASICREV_BCM5717 && */
2187             sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2188             /* sc->bge_asicrev != BGE_ASICREV_BCM57765 && */
2189             sc->bge_asicrev != BGE_ASICREV_BCM57780) {
2190                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2191                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2192                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2193                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2194                         if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
2195                             product != PCI_PRODUCT_BROADCOM_BCM5756)
2196                                 mii_priv |= BRGPHY_FLAG_JITTER_BUG;
2197                         if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
2198                                 mii_priv |= BRGPHY_FLAG_ADJUST_TRIM;
2199                 } else {
2200                         mii_priv |= BRGPHY_FLAG_BER_BUG;
2201                 }
2202         }
2203
2204         /*
2205          * Allocate interrupt
2206          */
2207         msi_enable = bge_msi_enable;
2208         if ((sc->bge_flags & BGE_FLAG_STATUS_TAG) == 0) {
2209                 /* If "tagged status" is disabled, don't enable MSI */
2210                 msi_enable = 0;
2211         } else if (msi_enable) {
2212                 msi_enable = 0; /* Disable by default */
2213                 if (BGE_IS_575X_PLUS(sc)) {
2214                         msi_enable = 1;
2215                         /* XXX we filter all 5714 chips */
2216                         if (sc->bge_asicrev == BGE_ASICREV_BCM5714 ||
2217                             (sc->bge_asicrev == BGE_ASICREV_BCM5750 &&
2218                              (sc->bge_chiprev == BGE_CHIPREV_5750_AX ||
2219                               sc->bge_chiprev == BGE_CHIPREV_5750_BX)))
2220                                 msi_enable = 0;
2221                         else if (BGE_IS_5755_PLUS(sc) ||
2222                             sc->bge_asicrev == BGE_ASICREV_BCM5906)
2223                                 sc->bge_flags |= BGE_FLAG_ONESHOT_MSI;
2224                 }
2225         }
2226         if (msi_enable) {
2227                 if (pci_find_extcap(dev, PCIY_MSI, &sc->bge_msicap)) {
2228                         device_printf(dev, "no MSI capability\n");
2229                         msi_enable = 0;
2230                 }
2231         }
2232
2233         sc->bge_irq_type = pci_alloc_1intr(dev, msi_enable, &sc->bge_irq_rid,
2234             &intr_flags);
2235
2236         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->bge_irq_rid,
2237             intr_flags);
2238         if (sc->bge_irq == NULL) {
2239                 device_printf(dev, "couldn't map interrupt\n");
2240                 error = ENXIO;
2241                 goto fail;
2242         }
2243
2244         if (sc->bge_irq_type == PCI_INTR_TYPE_MSI)
2245                 bge_enable_msi(sc);
2246         else
2247                 sc->bge_flags &= ~BGE_FLAG_ONESHOT_MSI;
2248
2249         /* Initialize if_name earlier, so if_printf could be used */
2250         ifp = &sc->arpcom.ac_if;
2251         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2252
2253         /* Try to reset the chip. */
2254         bge_reset(sc);
2255
2256         if (bge_chipinit(sc)) {
2257                 device_printf(dev, "chip initialization failed\n");
2258                 error = ENXIO;
2259                 goto fail;
2260         }
2261
2262         /*
2263          * Get station address
2264          */
2265         error = bge_get_eaddr(sc, ether_addr);
2266         if (error) {
2267                 device_printf(dev, "failed to read station address\n");
2268                 goto fail;
2269         }
2270
2271         /* 5705/5750 limits RX return ring to 512 entries. */
2272         if (BGE_IS_5705_PLUS(sc))
2273                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2274         else
2275                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2276
2277         error = bge_dma_alloc(sc);
2278         if (error)
2279                 goto fail;
2280
2281         /* Set default tuneable values. */
2282         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2283         sc->bge_rx_coal_ticks = BGE_RX_COAL_TICKS_DEF;
2284         sc->bge_tx_coal_ticks = BGE_TX_COAL_TICKS_DEF;
2285         sc->bge_rx_coal_bds = BGE_RX_COAL_BDS_DEF;
2286         sc->bge_tx_coal_bds = BGE_TX_COAL_BDS_DEF;
2287         if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2288                 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_DEF;
2289                 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_DEF;
2290                 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_DEF;
2291                 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_DEF;
2292         } else {
2293                 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_MIN;
2294                 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_MIN;
2295                 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_MIN;
2296                 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_MIN;
2297         }
2298
2299         /* Set up ifnet structure */
2300         ifp->if_softc = sc;
2301         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2302         ifp->if_ioctl = bge_ioctl;
2303         ifp->if_start = bge_start;
2304 #ifdef DEVICE_POLLING
2305         ifp->if_poll = bge_poll;
2306 #endif
2307         ifp->if_watchdog = bge_watchdog;
2308         ifp->if_init = bge_init;
2309         ifp->if_mtu = ETHERMTU;
2310         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2311         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2312         ifq_set_ready(&ifp->if_snd);
2313
2314         /*
2315          * 5700 B0 chips do not support checksumming correctly due
2316          * to hardware bugs.
2317          */
2318         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
2319                 ifp->if_capabilities |= IFCAP_HWCSUM;
2320                 ifp->if_hwassist = BGE_CSUM_FEATURES;
2321         }
2322         ifp->if_capenable = ifp->if_capabilities;
2323
2324         /*
2325          * Figure out what sort of media we have by checking the
2326          * hardware config word in the first 32k of NIC internal memory,
2327          * or fall back to examining the EEPROM if necessary.
2328          * Note: on some BCM5700 cards, this value appears to be unset.
2329          * If that's the case, we have to rely on identifying the NIC
2330          * by its PCI subsystem ID, as we do below for the SysKonnect
2331          * SK-9D41.
2332          */
2333         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
2334                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2335         } else {
2336                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2337                                     sizeof(hwcfg))) {
2338                         device_printf(dev, "failed to read EEPROM\n");
2339                         error = ENXIO;
2340                         goto fail;
2341                 }
2342                 hwcfg = ntohl(hwcfg);
2343         }
2344
2345         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2346         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2347             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
2348                 if (BGE_IS_5714_FAMILY(sc))
2349                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
2350                 else
2351                         sc->bge_flags |= BGE_FLAG_TBI;
2352         }
2353
2354         /* Setup MI MODE */
2355         if (sc->bge_flags & BGE_FLAG_CPMU)
2356                 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
2357         else
2358                 sc->bge_mi_mode = BGE_MIMODE_BASE;
2359         if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) {
2360                 /* Enable auto polling for BCM570[0-5]. */
2361                 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
2362         }
2363
2364         /* Setup link status update stuffs */
2365         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2366             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2367                 sc->bge_link_upd = bge_bcm5700_link_upd;
2368                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
2369         } else if (sc->bge_flags & BGE_FLAG_TBI) {
2370                 sc->bge_link_upd = bge_tbi_link_upd;
2371                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2372         } else if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2373                 sc->bge_link_upd = bge_autopoll_link_upd;
2374                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2375         } else {
2376                 sc->bge_link_upd = bge_copper_link_upd;
2377                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2378         }
2379
2380         /*
2381          * Broadcom's own driver always assumes the internal
2382          * PHY is at GMII address 1.  On some chips, the PHY responds
2383          * to accesses at all addresses, which could cause us to
2384          * bogusly attach the PHY 32 times at probe type.  Always
2385          * restricting the lookup to address 1 is simpler than
2386          * trying to figure out which chips revisions should be
2387          * special-cased.
2388          */
2389         sc->bge_phyno = 1;
2390
2391         if (sc->bge_flags & BGE_FLAG_TBI) {
2392                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
2393                     bge_ifmedia_upd, bge_ifmedia_sts);
2394                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2395                 ifmedia_add(&sc->bge_ifmedia,
2396                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2397                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2398                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2399                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2400         } else {
2401                 struct mii_probe_args mii_args;
2402
2403                 mii_probe_args_init(&mii_args, bge_ifmedia_upd, bge_ifmedia_sts);
2404                 mii_args.mii_probemask = 1 << sc->bge_phyno;
2405                 mii_args.mii_capmask = capmask;
2406                 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2407                 mii_args.mii_priv = mii_priv;
2408
2409                 error = mii_probe(dev, &sc->bge_miibus, &mii_args);
2410                 if (error) {
2411                         device_printf(dev, "MII without any PHY!\n");
2412                         goto fail;
2413                 }
2414         }
2415
2416         /*
2417          * Create sysctl nodes.
2418          */
2419         sysctl_ctx_init(&sc->bge_sysctl_ctx);
2420         sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2421                                               SYSCTL_STATIC_CHILDREN(_hw),
2422                                               OID_AUTO,
2423                                               device_get_nameunit(dev),
2424                                               CTLFLAG_RD, 0, "");
2425         if (sc->bge_sysctl_tree == NULL) {
2426                 device_printf(dev, "can't add sysctl node\n");
2427                 error = ENXIO;
2428                 goto fail;
2429         }
2430
2431         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2432                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2433                         OID_AUTO, "rx_coal_ticks",
2434                         CTLTYPE_INT | CTLFLAG_RW,
2435                         sc, 0, bge_sysctl_rx_coal_ticks, "I",
2436                         "Receive coalescing ticks (usec).");
2437         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2438                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2439                         OID_AUTO, "tx_coal_ticks",
2440                         CTLTYPE_INT | CTLFLAG_RW,
2441                         sc, 0, bge_sysctl_tx_coal_ticks, "I",
2442                         "Transmit coalescing ticks (usec).");
2443         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2444                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2445                         OID_AUTO, "rx_coal_bds",
2446                         CTLTYPE_INT | CTLFLAG_RW,
2447                         sc, 0, bge_sysctl_rx_coal_bds, "I",
2448                         "Receive max coalesced BD count.");
2449         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2450                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2451                         OID_AUTO, "tx_coal_bds",
2452                         CTLTYPE_INT | CTLFLAG_RW,
2453                         sc, 0, bge_sysctl_tx_coal_bds, "I",
2454                         "Transmit max coalesced BD count.");
2455         if (sc->bge_flags & BGE_FLAG_PCIE) {
2456                 /*
2457                  * A common design characteristic for many Broadcom
2458                  * client controllers is that they only support a
2459                  * single outstanding DMA read operation on the PCIe
2460                  * bus. This means that it will take twice as long to
2461                  * fetch a TX frame that is split into header and
2462                  * payload buffers as it does to fetch a single,
2463                  * contiguous TX frame (2 reads vs. 1 read). For these
2464                  * controllers, coalescing buffers to reduce the number
2465                  * of memory reads is effective way to get maximum
2466                  * performance(about 940Mbps).  Without collapsing TX
2467                  * buffers the maximum TCP bulk transfer performance
2468                  * is about 850Mbps. However forcing coalescing mbufs
2469                  * consumes a lot of CPU cycles, so leave it off by
2470                  * default.
2471                  */
2472                 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx,
2473                                SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2474                                OID_AUTO, "force_defrag", CTLFLAG_RW,
2475                                &sc->bge_force_defrag, 0,
2476                                "Force defragment on TX path");
2477         }
2478         if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2479                 if (!BGE_IS_5705_PLUS(sc)) {
2480                         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2481                             SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2482                             "rx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW,
2483                             sc, 0, bge_sysctl_rx_coal_ticks_int, "I",
2484                             "Receive coalescing ticks "
2485                             "during interrupt (usec).");
2486                         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2487                             SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2488                             "tx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW,
2489                             sc, 0, bge_sysctl_tx_coal_ticks_int, "I",
2490                             "Transmit coalescing ticks "
2491                             "during interrupt (usec).");
2492                 }
2493                 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2494                     SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2495                     "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2496                     sc, 0, bge_sysctl_rx_coal_bds_int, "I",
2497                     "Receive max coalesced BD count during interrupt.");
2498                 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2499                     SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2500                     "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2501                     sc, 0, bge_sysctl_tx_coal_bds_int, "I",
2502                     "Transmit max coalesced BD count during interrupt.");
2503         }
2504
2505         /*
2506          * Call MI attach routine.
2507          */
2508         ether_ifattach(ifp, ether_addr, NULL);
2509
2510         if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) {
2511                 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) {
2512                         intr_func = bge_msi_oneshot;
2513                         if (bootverbose)
2514                                 device_printf(dev, "oneshot MSI\n");
2515                 } else {
2516                         intr_func = bge_msi;
2517                 }
2518         } else if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2519                 intr_func = bge_intr_legacy;
2520         } else {
2521                 intr_func = bge_intr_crippled;
2522         }
2523         error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE, intr_func, sc,
2524             &sc->bge_intrhand, ifp->if_serializer);
2525         if (error) {
2526                 ether_ifdetach(ifp);
2527                 device_printf(dev, "couldn't set up irq\n");
2528                 goto fail;
2529         }
2530
2531         ifp->if_cpuid = rman_get_cpuid(sc->bge_irq);
2532         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2533
2534         return(0);
2535 fail:
2536         bge_detach(dev);
2537         return(error);
2538 }
2539
2540 static int
2541 bge_detach(device_t dev)
2542 {
2543         struct bge_softc *sc = device_get_softc(dev);
2544
2545         if (device_is_attached(dev)) {
2546                 struct ifnet *ifp = &sc->arpcom.ac_if;
2547
2548                 lwkt_serialize_enter(ifp->if_serializer);
2549                 bge_stop(sc);
2550                 bge_reset(sc);
2551                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2552                 lwkt_serialize_exit(ifp->if_serializer);
2553
2554                 ether_ifdetach(ifp);
2555         }
2556
2557         if (sc->bge_flags & BGE_FLAG_TBI)
2558                 ifmedia_removeall(&sc->bge_ifmedia);
2559         if (sc->bge_miibus)
2560                 device_delete_child(dev, sc->bge_miibus);
2561         bus_generic_detach(dev);
2562
2563         if (sc->bge_irq != NULL) {
2564                 bus_release_resource(dev, SYS_RES_IRQ, sc->bge_irq_rid,
2565                     sc->bge_irq);
2566         }
2567         if (sc->bge_irq_type == PCI_INTR_TYPE_MSI)
2568                 pci_release_msi(dev);
2569
2570         if (sc->bge_res != NULL) {
2571                 bus_release_resource(dev, SYS_RES_MEMORY,
2572                     BGE_PCI_BAR0, sc->bge_res);
2573         }
2574
2575         if (sc->bge_sysctl_tree != NULL)
2576                 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2577
2578         bge_dma_free(sc);
2579
2580         return 0;
2581 }
2582
2583 static void
2584 bge_reset(struct bge_softc *sc)
2585 {
2586         device_t dev;
2587         uint32_t cachesize, command, pcistate, reset;
2588         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2589         int i, val = 0;
2590
2591         dev = sc->bge_dev;
2592
2593         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2594             sc->bge_asicrev != BGE_ASICREV_BCM5906) {
2595                 if (sc->bge_flags & BGE_FLAG_PCIE)
2596                         write_op = bge_writemem_direct;
2597                 else
2598                         write_op = bge_writemem_ind;
2599         } else {
2600                 write_op = bge_writereg_ind;
2601         }
2602
2603         /* Save some important PCI state. */
2604         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2605         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2606         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2607
2608         pci_write_config(dev, BGE_PCI_MISC_CTL,
2609             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2610             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2611             sc->bge_pci_miscctl, 4);
2612
2613         /* Disable fastboot on controllers that support it. */
2614         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2615             BGE_IS_5755_PLUS(sc)) {
2616                 if (bootverbose)
2617                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2618                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2619         }
2620
2621         /*
2622          * Write the magic number to SRAM at offset 0xB50.
2623          * When firmware finishes its initialization it will
2624          * write ~BGE_MAGIC_NUMBER to the same location.
2625          */
2626         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2627
2628         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2629
2630         /* XXX: Broadcom Linux driver. */
2631         if (sc->bge_flags & BGE_FLAG_PCIE) {
2632                 /* Force PCI-E 1.0a mode */
2633                 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2634                     CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2635                     (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2636                      BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2637                         CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2638                             BGE_PCIE_PHY_TSTCTL_PSCRAM);
2639                 }
2640                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2641                         /* Prevent PCIE link training during global reset */
2642                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2643                         reset |= (1<<29);
2644                 }
2645         }
2646
2647         /* 
2648          * Set GPHY Power Down Override to leave GPHY
2649          * powered up in D0 uninitialized.
2650          */
2651         if (BGE_IS_5705_PLUS(sc) && (sc->bge_flags & BGE_FLAG_CPMU) == 0)
2652                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2653
2654         /* Issue global reset */
2655         write_op(sc, BGE_MISC_CFG, reset);
2656
2657         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2658                 uint32_t status, ctrl;
2659
2660                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2661                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2662                     status | BGE_VCPU_STATUS_DRV_RESET);
2663                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2664                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2665                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2666         }
2667
2668         DELAY(1000);
2669
2670         /* XXX: Broadcom Linux driver. */
2671         if (sc->bge_flags & BGE_FLAG_PCIE) {
2672                 uint16_t devctl;
2673
2674                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2675                         uint32_t v;
2676
2677                         DELAY(500000); /* wait for link training to complete */
2678                         v = pci_read_config(dev, 0xc4, 4);
2679                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
2680                 }
2681
2682                 devctl = pci_read_config(dev,
2683                     sc->bge_pciecap + PCIER_DEVCTRL, 2);
2684
2685                 /* Disable no snoop and disable relaxed ordering. */
2686                 devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2687
2688                 /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2689                 if ((sc->bge_flags & BGE_FLAG_CPMU) == 0) {
2690                         devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2691                         devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2692                 }
2693
2694                 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVCTRL,
2695                     devctl, 2);
2696
2697                 /* Clear error status. */
2698                 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVSTS,
2699                     PCIEM_DEVSTS_CORR_ERR |
2700                     PCIEM_DEVSTS_NFATAL_ERR |
2701                     PCIEM_DEVSTS_FATAL_ERR |
2702                     PCIEM_DEVSTS_UNSUPP_REQ, 2);
2703         }
2704
2705         /* Reset some of the PCI state that got zapped by reset */
2706         pci_write_config(dev, BGE_PCI_MISC_CTL,
2707             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2708             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2709             sc->bge_pci_miscctl, 4);
2710         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2711         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2712         write_op(sc, BGE_MISC_CFG, (65 << 1));
2713
2714         /*
2715          * Disable PCI-X relaxed ordering to ensure status block update
2716          * comes first then packet buffer DMA. Otherwise driver may
2717          * read stale status block.
2718          */
2719         if (sc->bge_flags & BGE_FLAG_PCIX) {
2720                 uint16_t devctl;
2721
2722                 devctl = pci_read_config(dev,
2723                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
2724                 devctl &= ~PCIXM_COMMAND_ERO;
2725                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
2726                         devctl &= ~PCIXM_COMMAND_MAX_READ;
2727                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2728                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2729                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
2730                             PCIXM_COMMAND_MAX_READ);
2731                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2732                 }
2733                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
2734                     devctl, 2);
2735         }
2736
2737         /*
2738          * Enable memory arbiter and re-enable MSI if necessary.
2739          */
2740         if (BGE_IS_5714_FAMILY(sc)) {
2741                 uint32_t val;
2742
2743                 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) {
2744                         /*
2745                          * Resetting BCM5714 family will clear MSI
2746                          * enable bit; restore it after resetting.
2747                          */
2748                         PCI_SETBIT(sc->bge_dev, sc->bge_msicap + PCIR_MSI_CTRL,
2749                             PCIM_MSICTRL_MSI_ENABLE, 2);
2750                         BGE_SETBIT(sc, BGE_MSI_MODE, BGE_MSIMODE_ENABLE);
2751                 }
2752                 val = CSR_READ_4(sc, BGE_MARB_MODE);
2753                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2754         } else {
2755                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2756         }
2757
2758         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2759                 for (i = 0; i < BGE_TIMEOUT; i++) {
2760                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2761                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2762                                 break;
2763                         DELAY(100);
2764                 }
2765                 if (i == BGE_TIMEOUT) {
2766                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2767                         return;
2768                 }
2769         } else {
2770                 /*
2771                  * Poll until we see the 1's complement of the magic number.
2772                  * This indicates that the firmware initialization
2773                  * is complete.
2774                  */
2775                 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
2776                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2777                         if (val == ~BGE_MAGIC_NUMBER)
2778                                 break;
2779                         DELAY(10);
2780                 }
2781                 if (i == BGE_FIRMWARE_TIMEOUT) {
2782                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2783                                   "timed out, found 0x%08x\n", val);
2784                 }
2785         }
2786
2787         /*
2788          * XXX Wait for the value of the PCISTATE register to
2789          * return to its original pre-reset state. This is a
2790          * fairly good indicator of reset completion. If we don't
2791          * wait for the reset to fully complete, trying to read
2792          * from the device's non-PCI registers may yield garbage
2793          * results.
2794          */
2795         for (i = 0; i < BGE_TIMEOUT; i++) {
2796                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2797                         break;
2798                 DELAY(10);
2799         }
2800
2801         /* Fix up byte swapping */
2802         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2803             BGE_MODECTL_BYTESWAP_DATA);
2804
2805         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2806
2807         /*
2808          * The 5704 in TBI mode apparently needs some special
2809          * adjustment to insure the SERDES drive level is set
2810          * to 1.2V.
2811          */
2812         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2813             (sc->bge_flags & BGE_FLAG_TBI)) {
2814                 uint32_t serdescfg;
2815
2816                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2817                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2818                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2819         }
2820
2821         /* XXX: Broadcom Linux driver. */
2822         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2823             sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
2824             sc->bge_asicrev != BGE_ASICREV_BCM5785) {
2825                 uint32_t v;
2826
2827                 /* Enable Data FIFO protection. */
2828                 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
2829                 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
2830         }
2831
2832         DELAY(10000);
2833 }
2834
2835 /*
2836  * Frame reception handling. This is called if there's a frame
2837  * on the receive return list.
2838  *
2839  * Note: we have to be able to handle two possibilities here:
2840  * 1) the frame is from the jumbo recieve ring
2841  * 2) the frame is from the standard receive ring
2842  */
2843
2844 static void
2845 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod)
2846 {
2847         struct ifnet *ifp;
2848         int stdcnt = 0, jumbocnt = 0;
2849
2850         ifp = &sc->arpcom.ac_if;
2851
2852         while (sc->bge_rx_saved_considx != rx_prod) {
2853                 struct bge_rx_bd        *cur_rx;
2854                 uint32_t                rxidx;
2855                 struct mbuf             *m = NULL;
2856                 uint16_t                vlan_tag = 0;
2857                 int                     have_tag = 0;
2858
2859                 cur_rx =
2860             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2861
2862                 rxidx = cur_rx->bge_idx;
2863                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2864                 logif(rx_pkt);
2865
2866                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2867                         have_tag = 1;
2868                         vlan_tag = cur_rx->bge_vlan_tag;
2869                 }
2870
2871                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2872                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2873                         jumbocnt++;
2874
2875                         if (rxidx != sc->bge_jumbo) {
2876                                 ifp->if_ierrors++;
2877                                 if_printf(ifp, "sw jumbo index(%d) "
2878                                     "and hw jumbo index(%d) mismatch, drop!\n",
2879                                     sc->bge_jumbo, rxidx);
2880                                 bge_setup_rxdesc_jumbo(sc, rxidx);
2881                                 continue;
2882                         }
2883
2884                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf;
2885                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2886                                 ifp->if_ierrors++;
2887                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2888                                 continue;
2889                         }
2890                         if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) {
2891                                 ifp->if_ierrors++;
2892                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2893                                 continue;
2894                         }
2895                 } else {
2896                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2897                         stdcnt++;
2898
2899                         if (rxidx != sc->bge_std) {
2900                                 ifp->if_ierrors++;
2901                                 if_printf(ifp, "sw std index(%d) "
2902                                     "and hw std index(%d) mismatch, drop!\n",
2903                                     sc->bge_std, rxidx);
2904                                 bge_setup_rxdesc_std(sc, rxidx);
2905                                 continue;
2906                         }
2907
2908                         m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf;
2909                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2910                                 ifp->if_ierrors++;
2911                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2912                                 continue;
2913                         }
2914                         if (bge_newbuf_std(sc, sc->bge_std, 0)) {
2915                                 ifp->if_ierrors++;
2916                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2917                                 continue;
2918                         }
2919                 }
2920
2921                 ifp->if_ipackets++;
2922 #if !defined(__i386__) && !defined(__x86_64__)
2923                 /*
2924                  * The x86 allows unaligned accesses, but for other
2925                  * platforms we must make sure the payload is aligned.
2926                  */
2927                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2928                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2929                             cur_rx->bge_len);
2930                         m->m_data += ETHER_ALIGN;
2931                 }
2932 #endif
2933                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2934                 m->m_pkthdr.rcvif = ifp;
2935
2936                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2937                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2938                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2939                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2940                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2941                         }
2942                         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2943                             m->m_pkthdr.len >= BGE_MIN_FRAMELEN) {
2944                                 m->m_pkthdr.csum_data =
2945                                         cur_rx->bge_tcp_udp_csum;
2946                                 m->m_pkthdr.csum_flags |=
2947                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2948                         }
2949                 }
2950
2951                 /*
2952                  * If we received a packet with a vlan tag, pass it
2953                  * to vlan_input() instead of ether_input().
2954                  */
2955                 if (have_tag) {
2956                         m->m_flags |= M_VLANTAG;
2957                         m->m_pkthdr.ether_vlantag = vlan_tag;
2958                         have_tag = vlan_tag = 0;
2959                 }
2960                 ifp->if_input(ifp, m);
2961         }
2962
2963         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2964         if (stdcnt)
2965                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2966         if (jumbocnt)
2967                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2968 }
2969
2970 static void
2971 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
2972 {
2973         struct bge_tx_bd *cur_tx = NULL;
2974         struct ifnet *ifp;
2975
2976         ifp = &sc->arpcom.ac_if;
2977
2978         /*
2979          * Go through our tx ring and free mbufs for those
2980          * frames that have been sent.
2981          */
2982         while (sc->bge_tx_saved_considx != tx_cons) {
2983                 uint32_t idx = 0;
2984
2985                 idx = sc->bge_tx_saved_considx;
2986                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2987                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2988                         ifp->if_opackets++;
2989                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2990                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
2991                             sc->bge_cdata.bge_tx_dmamap[idx]);
2992                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2993                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2994                 }
2995                 sc->bge_txcnt--;
2996                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2997                 logif(tx_pkt);
2998         }
2999
3000         if (cur_tx != NULL &&
3001             (BGE_TX_RING_CNT - sc->bge_txcnt) >=
3002             (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
3003                 ifp->if_flags &= ~IFF_OACTIVE;
3004
3005         if (sc->bge_txcnt == 0)
3006                 ifp->if_timer = 0;
3007
3008         if (!ifq_is_empty(&ifp->if_snd))
3009                 if_devstart(ifp);
3010 }
3011
3012 #ifdef DEVICE_POLLING
3013
3014 static void
3015 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3016 {
3017         struct bge_softc *sc = ifp->if_softc;
3018         struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3019         uint16_t rx_prod, tx_cons;
3020
3021         switch(cmd) {
3022         case POLL_REGISTER:
3023                 bge_disable_intr(sc);
3024                 break;
3025         case POLL_DEREGISTER:
3026                 bge_enable_intr(sc);
3027                 break;
3028         case POLL_AND_CHECK_STATUS:
3029                 /*
3030                  * Process link state changes.
3031                  */
3032                 bge_link_poll(sc);
3033                 /* Fall through */
3034         case POLL_ONLY:
3035                 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
3036                         sc->bge_status_tag = sblk->bge_status_tag;
3037                         /*
3038                          * Use a load fence to ensure that status_tag
3039                          * is saved  before rx_prod and tx_cons.
3040                          */
3041                         cpu_lfence();
3042                 }
3043                 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
3044                 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
3045                 if (ifp->if_flags & IFF_RUNNING) {
3046                         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
3047                         if (sc->bge_rx_saved_considx != rx_prod)
3048                                 bge_rxeof(sc, rx_prod);
3049
3050                         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
3051                         if (sc->bge_tx_saved_considx != tx_cons)
3052                                 bge_txeof(sc, tx_cons);
3053                 }
3054                 break;
3055         }
3056 }
3057
3058 #endif
3059
3060 static void
3061 bge_intr_crippled(void *xsc)
3062 {
3063         struct bge_softc *sc = xsc;
3064         struct ifnet *ifp = &sc->arpcom.ac_if;
3065
3066         logif(intr);
3067
3068         /*
3069          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
3070          * disable interrupts by writing nonzero like we used to, since with
3071          * our current organization this just gives complications and
3072          * pessimizations for re-enabling interrupts.  We used to have races
3073          * instead of the necessary complications.  Disabling interrupts
3074          * would just reduce the chance of a status update while we are
3075          * running (by switching to the interrupt-mode coalescence
3076          * parameters), but this chance is already very low so it is more
3077          * efficient to get another interrupt than prevent it.
3078          *
3079          * We do the ack first to ensure another interrupt if there is a
3080          * status update after the ack.  We don't check for the status
3081          * changing later because it is more efficient to get another
3082          * interrupt than prevent it, not quite as above (not checking is
3083          * a smaller optimization than not toggling the interrupt enable,
3084          * since checking doesn't involve PCI accesses and toggling require
3085          * the status check).  So toggling would probably be a pessimization
3086          * even with MSI.  It would only be needed for using a task queue.
3087          */
3088         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3089
3090         /*
3091          * Process link state changes.
3092          */
3093         bge_link_poll(sc);
3094
3095         if (ifp->if_flags & IFF_RUNNING) {
3096                 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3097                 uint16_t rx_prod, tx_cons;
3098
3099                 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
3100                 if (sc->bge_rx_saved_considx != rx_prod)
3101                         bge_rxeof(sc, rx_prod);
3102
3103                 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
3104                 if (sc->bge_tx_saved_considx != tx_cons)
3105                         bge_txeof(sc, tx_cons);
3106         }
3107
3108         if (sc->bge_coal_chg)
3109                 bge_coal_change(sc);
3110 }
3111
3112 static void
3113 bge_intr_legacy(void *xsc)
3114 {
3115         struct bge_softc *sc = xsc;
3116         struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3117
3118         if (sc->bge_status_tag == sblk->bge_status_tag) {
3119                 uint32_t val;
3120
3121                 val = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3122                 if (val & BGE_PCISTAT_INTR_NOTACT)
3123                         return;
3124         }
3125
3126         /*
3127          * NOTE:
3128          * Interrupt will have to be disabled if tagged status
3129          * is used, else interrupt will always be asserted on
3130          * certain chips (at least on BCM5750 AX/BX).
3131          */
3132         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3133
3134         bge_intr(sc);
3135 }
3136
3137 static void
3138 bge_msi(void *xsc)
3139 {
3140         struct bge_softc *sc = xsc;
3141
3142         /* Disable interrupt first */
3143         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3144         bge_intr(sc);
3145 }
3146
3147 static void
3148 bge_msi_oneshot(void *xsc)
3149 {
3150         bge_intr(xsc);
3151 }
3152
3153 static void
3154 bge_intr(struct bge_softc *sc)
3155 {
3156         struct ifnet *ifp = &sc->arpcom.ac_if;
3157         struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3158         uint16_t rx_prod, tx_cons;
3159         uint32_t status;
3160
3161         sc->bge_status_tag = sblk->bge_status_tag;
3162         /*
3163          * Use a load fence to ensure that status_tag is saved 
3164          * before rx_prod, tx_cons and status.
3165          */
3166         cpu_lfence();
3167
3168         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
3169         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
3170         status = sblk->bge_status;
3171
3172         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bge_link_evt)
3173                 bge_link_poll(sc);
3174
3175         if (ifp->if_flags & IFF_RUNNING) {
3176                 if (sc->bge_rx_saved_considx != rx_prod)
3177                         bge_rxeof(sc, rx_prod);
3178
3179                 if (sc->bge_tx_saved_considx != tx_cons)
3180                         bge_txeof(sc, tx_cons);
3181         }
3182
3183         bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
3184
3185         if (sc->bge_coal_chg)
3186                 bge_coal_change(sc);
3187 }
3188
3189 static void
3190 bge_tick(void *xsc)
3191 {
3192         struct bge_softc *sc = xsc;
3193         struct ifnet *ifp = &sc->arpcom.ac_if;
3194
3195         lwkt_serialize_enter(ifp->if_serializer);
3196
3197         if (BGE_IS_5705_PLUS(sc))
3198                 bge_stats_update_regs(sc);
3199         else
3200                 bge_stats_update(sc);
3201
3202         if (sc->bge_flags & BGE_FLAG_TBI) {
3203                 /*
3204                  * Since in TBI mode auto-polling can't be used we should poll
3205                  * link status manually. Here we register pending link event
3206                  * and trigger interrupt.
3207                  */
3208                 sc->bge_link_evt++;
3209                 if (BGE_IS_CRIPPLED(sc))
3210                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3211                 else
3212                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3213         } else if (!sc->bge_link) {
3214                 mii_tick(device_get_softc(sc->bge_miibus));
3215         }
3216
3217         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3218
3219         lwkt_serialize_exit(ifp->if_serializer);
3220 }
3221
3222 static void
3223 bge_stats_update_regs(struct bge_softc *sc)
3224 {
3225         struct ifnet *ifp = &sc->arpcom.ac_if;
3226         struct bge_mac_stats_regs stats;
3227         uint32_t *s;
3228         int i;
3229
3230         s = (uint32_t *)&stats;
3231         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
3232                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
3233                 s++;
3234         }
3235
3236         ifp->if_collisions +=
3237            (stats.dot3StatsSingleCollisionFrames +
3238            stats.dot3StatsMultipleCollisionFrames +
3239            stats.dot3StatsExcessiveCollisions +
3240            stats.dot3StatsLateCollisions) -
3241            ifp->if_collisions;
3242 }
3243
3244 static void
3245 bge_stats_update(struct bge_softc *sc)
3246 {
3247         struct ifnet *ifp = &sc->arpcom.ac_if;
3248         bus_size_t stats;
3249
3250         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3251
3252 #define READ_STAT(sc, stats, stat)      \
3253         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3254
3255         ifp->if_collisions +=
3256            (READ_STAT(sc, stats,
3257                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
3258             READ_STAT(sc, stats,
3259                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
3260             READ_STAT(sc, stats,
3261                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
3262             READ_STAT(sc, stats,
3263                 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
3264            ifp->if_collisions;
3265
3266 #undef READ_STAT
3267
3268 #ifdef notdef
3269         ifp->if_collisions +=
3270            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
3271            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
3272            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
3273            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
3274            ifp->if_collisions;
3275 #endif
3276 }
3277
3278 /*
3279  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
3280  * pointers to descriptors.
3281  */
3282 static int
3283 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
3284 {
3285         struct bge_tx_bd *d = NULL;
3286         uint16_t csum_flags = 0;
3287         bus_dma_segment_t segs[BGE_NSEG_NEW];
3288         bus_dmamap_t map;
3289         int error, maxsegs, nsegs, idx, i;
3290         struct mbuf *m_head = *m_head0, *m_new;
3291
3292         if (m_head->m_pkthdr.csum_flags) {
3293                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3294                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3295                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
3296                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3297                 if (m_head->m_flags & M_LASTFRAG)
3298                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3299                 else if (m_head->m_flags & M_FRAG)
3300                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3301         }
3302
3303         idx = *txidx;
3304         map = sc->bge_cdata.bge_tx_dmamap[idx];
3305
3306         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
3307         KASSERT(maxsegs >= BGE_NSEG_SPARE,
3308                 ("not enough segments %d", maxsegs));
3309
3310         if (maxsegs > BGE_NSEG_NEW)
3311                 maxsegs = BGE_NSEG_NEW;
3312
3313         /*
3314          * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
3315          * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
3316          * but when such padded frames employ the bge IP/TCP checksum
3317          * offload, the hardware checksum assist gives incorrect results
3318          * (possibly from incorporating its own padding into the UDP/TCP
3319          * checksum; who knows).  If we pad such runts with zeros, the
3320          * onboard checksum comes out correct.
3321          */
3322         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
3323             m_head->m_pkthdr.len < BGE_MIN_FRAMELEN) {
3324                 error = m_devpad(m_head, BGE_MIN_FRAMELEN);
3325                 if (error)
3326                         goto back;
3327         }
3328
3329         if ((sc->bge_flags & BGE_FLAG_SHORTDMA) && m_head->m_next != NULL) {
3330                 m_new = bge_defrag_shortdma(m_head);
3331                 if (m_new == NULL) {
3332                         error = ENOBUFS;
3333                         goto back;
3334                 }
3335                 *m_head0 = m_head = m_new;
3336         }
3337         if (sc->bge_force_defrag && (sc->bge_flags & BGE_FLAG_PCIE) &&
3338             m_head->m_next != NULL) {
3339                 /*
3340                  * Forcefully defragment mbuf chain to overcome hardware
3341                  * limitation which only support a single outstanding
3342                  * DMA read operation.  If it fails, keep moving on using
3343                  * the original mbuf chain.
3344                  */
3345                 m_new = m_defrag(m_head, MB_DONTWAIT);
3346                 if (m_new != NULL)
3347                         *m_head0 = m_head = m_new;
3348         }
3349
3350         error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map,
3351                         m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3352         if (error)
3353                 goto back;
3354
3355         m_head = *m_head0;
3356         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3357
3358         for (i = 0; ; i++) {
3359                 d = &sc->bge_ldata.bge_tx_ring[idx];
3360
3361                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3362                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3363                 d->bge_len = segs[i].ds_len;
3364                 d->bge_flags = csum_flags;
3365
3366                 if (i == nsegs - 1)
3367                         break;
3368                 BGE_INC(idx, BGE_TX_RING_CNT);
3369         }
3370         /* Mark the last segment as end of packet... */
3371         d->bge_flags |= BGE_TXBDFLAG_END;
3372
3373         /* Set vlan tag to the first segment of the packet. */
3374         d = &sc->bge_ldata.bge_tx_ring[*txidx];
3375         if (m_head->m_flags & M_VLANTAG) {
3376                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3377                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
3378         } else {
3379                 d->bge_vlan_tag = 0;
3380         }
3381
3382         /*
3383          * Insure that the map for this transmission is placed at
3384          * the array index of the last descriptor in this chain.
3385          */
3386         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
3387         sc->bge_cdata.bge_tx_dmamap[idx] = map;
3388         sc->bge_cdata.bge_tx_chain[idx] = m_head;
3389         sc->bge_txcnt += nsegs;
3390
3391         BGE_INC(idx, BGE_TX_RING_CNT);
3392         *txidx = idx;
3393 back:
3394         if (error) {
3395                 m_freem(*m_head0);
3396                 *m_head0 = NULL;
3397         }
3398         return error;
3399 }
3400
3401 /*
3402  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3403  * to the mbuf data regions directly in the transmit descriptors.
3404  */
3405 static void
3406 bge_start(struct ifnet *ifp)
3407 {
3408         struct bge_softc *sc = ifp->if_softc;
3409         struct mbuf *m_head = NULL;
3410         uint32_t prodidx;
3411         int need_trans;
3412
3413         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
3414                 return;
3415
3416         prodidx = sc->bge_tx_prodidx;
3417
3418         need_trans = 0;
3419         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
3420                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3421                 if (m_head == NULL)
3422                         break;
3423
3424                 /*
3425                  * XXX
3426                  * The code inside the if() block is never reached since we
3427                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
3428                  * requests to checksum TCP/UDP in a fragmented packet.
3429                  * 
3430                  * XXX
3431                  * safety overkill.  If this is a fragmented packet chain
3432                  * with delayed TCP/UDP checksums, then only encapsulate
3433                  * it if we have enough descriptors to handle the entire
3434                  * chain at once.
3435                  * (paranoia -- may not actually be needed)
3436                  */
3437                 if ((m_head->m_flags & M_FIRSTFRAG) &&
3438                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
3439                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3440                             m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
3441                                 ifp->if_flags |= IFF_OACTIVE;
3442                                 ifq_prepend(&ifp->if_snd, m_head);
3443                                 break;
3444                         }
3445                 }
3446
3447                 /*
3448                  * Sanity check: avoid coming within BGE_NSEG_RSVD
3449                  * descriptors of the end of the ring.  Also make
3450                  * sure there are BGE_NSEG_SPARE descriptors for
3451                  * jumbo buffers' defragmentation.
3452                  */
3453                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3454                     (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
3455                         ifp->if_flags |= IFF_OACTIVE;
3456                         ifq_prepend(&ifp->if_snd, m_head);
3457                         break;
3458                 }
3459
3460                 /*
3461                  * Pack the data into the transmit ring. If we
3462                  * don't have room, set the OACTIVE flag and wait
3463                  * for the NIC to drain the ring.
3464                  */
3465                 if (bge_encap(sc, &m_head, &prodidx)) {
3466                         ifp->if_flags |= IFF_OACTIVE;
3467                         ifp->if_oerrors++;
3468                         break;
3469                 }
3470                 need_trans = 1;
3471
3472                 ETHER_BPF_MTAP(ifp, m_head);
3473         }
3474
3475         if (!need_trans)
3476                 return;
3477
3478         /* Transmit */
3479         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3480         /* 5700 b2 errata */
3481         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
3482                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3483
3484         sc->bge_tx_prodidx = prodidx;
3485
3486         /*
3487          * Set a timeout in case the chip goes out to lunch.
3488          */
3489         ifp->if_timer = 5;
3490 }
3491
3492 static void
3493 bge_init(void *xsc)
3494 {
3495         struct bge_softc *sc = xsc;
3496         struct ifnet *ifp = &sc->arpcom.ac_if;
3497         uint16_t *m;
3498         uint32_t mode;
3499
3500         ASSERT_SERIALIZED(ifp->if_serializer);
3501
3502         /* Cancel pending I/O and flush buffers. */
3503         bge_stop(sc);
3504         bge_reset(sc);
3505         bge_chipinit(sc);
3506
3507         /*
3508          * Init the various state machines, ring
3509          * control blocks and firmware.
3510          */
3511         if (bge_blockinit(sc)) {
3512                 if_printf(ifp, "initialization failure\n");
3513                 bge_stop(sc);
3514                 return;
3515         }
3516
3517         /* Specify MTU. */
3518         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3519             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3520
3521         /* Load our MAC address. */
3522         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3523         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3524         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3525
3526         /* Enable or disable promiscuous mode as needed. */
3527         bge_setpromisc(sc);
3528
3529         /* Program multicast filter. */
3530         bge_setmulti(sc);
3531
3532         /* Init RX ring. */
3533         if (bge_init_rx_ring_std(sc)) {
3534                 if_printf(ifp, "RX ring initialization failed\n");
3535                 bge_stop(sc);
3536                 return;
3537         }
3538
3539         /*
3540          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3541          * memory to insure that the chip has in fact read the first
3542          * entry of the ring.
3543          */
3544         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3545                 uint32_t                v, i;
3546                 for (i = 0; i < 10; i++) {
3547                         DELAY(20);
3548                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3549                         if (v == (MCLBYTES - ETHER_ALIGN))
3550                                 break;
3551                 }
3552                 if (i == 10)
3553                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
3554         }
3555
3556         /* Init jumbo RX ring. */
3557         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3558                 if (bge_init_rx_ring_jumbo(sc)) {
3559                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
3560                         bge_stop(sc);
3561                         return;
3562                 }
3563         }
3564
3565         /* Init our RX return ring index */
3566         sc->bge_rx_saved_considx = 0;
3567
3568         /* Init TX ring. */
3569         bge_init_tx_ring(sc);
3570
3571         /* Enable TX MAC state machine lockup fix. */
3572         mode = CSR_READ_4(sc, BGE_TX_MODE);
3573         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3574                 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3575         /* Turn on transmitter */
3576         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3577
3578         /* Turn on receiver */
3579         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3580
3581         /*
3582          * Set the number of good frames to receive after RX MBUF
3583          * Low Watermark has been reached.  After the RX MAC receives
3584          * this number of frames, it will drop subsequent incoming
3585          * frames until the MBUF High Watermark is reached.
3586          */
3587         CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3588
3589         if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) {
3590                 if (bootverbose) {
3591                         if_printf(ifp, "MSI_MODE: %#x\n",
3592                             CSR_READ_4(sc, BGE_MSI_MODE));
3593                 }
3594
3595                 /*
3596                  * XXX
3597                  * Linux driver turns it on for all chips supporting MSI?!
3598                  */
3599                 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) {
3600                         /*
3601                          * XXX
3602                          * According to 5722-PG101-R,
3603                          * BGE_PCIE_TRANSACT_ONESHOT_MSI applies only to
3604                          * BCM5906.
3605                          */
3606                         BGE_SETBIT(sc, BGE_PCIE_TRANSACT,
3607                             BGE_PCIE_TRANSACT_ONESHOT_MSI);
3608                 }
3609         }
3610
3611         /* Tell firmware we're alive. */
3612         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3613
3614         /* Enable host interrupts if polling(4) is not enabled. */
3615         PCI_SETBIT(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3616 #ifdef DEVICE_POLLING
3617         if (ifp->if_flags & IFF_POLLING)
3618                 bge_disable_intr(sc);
3619         else
3620 #endif
3621         bge_enable_intr(sc);
3622
3623         bge_ifmedia_upd(ifp);
3624
3625         ifp->if_flags |= IFF_RUNNING;
3626         ifp->if_flags &= ~IFF_OACTIVE;
3627
3628         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3629 }
3630
3631 /*
3632  * Set media options.
3633  */
3634 static int
3635 bge_ifmedia_upd(struct ifnet *ifp)
3636 {
3637         struct bge_softc *sc = ifp->if_softc;
3638
3639         /* If this is a 1000baseX NIC, enable the TBI port. */
3640         if (sc->bge_flags & BGE_FLAG_TBI) {
3641                 struct ifmedia *ifm = &sc->bge_ifmedia;
3642
3643                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3644                         return(EINVAL);
3645
3646                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3647                 case IFM_AUTO:
3648                         /*
3649                          * The BCM5704 ASIC appears to have a special
3650                          * mechanism for programming the autoneg
3651                          * advertisement registers in TBI mode.
3652                          */
3653                         if (!bge_fake_autoneg &&
3654                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3655                                 uint32_t sgdig;
3656
3657                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3658                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3659                                 sgdig |= BGE_SGDIGCFG_AUTO |
3660                                          BGE_SGDIGCFG_PAUSE_CAP |
3661                                          BGE_SGDIGCFG_ASYM_PAUSE;
3662                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3663                                             sgdig | BGE_SGDIGCFG_SEND);
3664                                 DELAY(5);
3665                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3666                         }
3667                         break;
3668                 case IFM_1000_SX:
3669                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3670                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3671                                     BGE_MACMODE_HALF_DUPLEX);
3672                         } else {
3673                                 BGE_SETBIT(sc, BGE_MAC_MODE,
3674                                     BGE_MACMODE_HALF_DUPLEX);
3675                         }
3676                         break;
3677                 default:
3678                         return(EINVAL);
3679                 }
3680         } else {
3681                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3682
3683                 sc->bge_link_evt++;
3684                 sc->bge_link = 0;
3685                 if (mii->mii_instance) {
3686                         struct mii_softc *miisc;
3687
3688                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3689                                 mii_phy_reset(miisc);
3690                 }
3691                 mii_mediachg(mii);
3692
3693                 /*
3694                  * Force an interrupt so that we will call bge_link_upd
3695                  * if needed and clear any pending link state attention.
3696                  * Without this we are not getting any further interrupts
3697                  * for link state changes and thus will not UP the link and
3698                  * not be able to send in bge_start.  The only way to get
3699                  * things working was to receive a packet and get an RX
3700                  * intr.
3701                  *
3702                  * bge_tick should help for fiber cards and we might not
3703                  * need to do this here if BGE_FLAG_TBI is set but as
3704                  * we poll for fiber anyway it should not harm.
3705                  */
3706                 if (BGE_IS_CRIPPLED(sc))
3707                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3708                 else
3709                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3710         }
3711         return(0);
3712 }
3713
3714 /*
3715  * Report current media status.
3716  */
3717 static void
3718 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3719 {
3720         struct bge_softc *sc = ifp->if_softc;
3721
3722         if (sc->bge_flags & BGE_FLAG_TBI) {
3723                 ifmr->ifm_status = IFM_AVALID;
3724                 ifmr->ifm_active = IFM_ETHER;
3725                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3726                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3727                         ifmr->ifm_status |= IFM_ACTIVE;
3728                 } else {
3729                         ifmr->ifm_active |= IFM_NONE;
3730                         return;
3731                 }
3732
3733                 ifmr->ifm_active |= IFM_1000_SX;
3734                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3735                         ifmr->ifm_active |= IFM_HDX;    
3736                 else
3737                         ifmr->ifm_active |= IFM_FDX;
3738         } else {
3739                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3740
3741                 mii_pollstat(mii);
3742                 ifmr->ifm_active = mii->mii_media_active;
3743                 ifmr->ifm_status = mii->mii_media_status;
3744         }
3745 }
3746
3747 static int
3748 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3749 {
3750         struct bge_softc *sc = ifp->if_softc;
3751         struct ifreq *ifr = (struct ifreq *)data;
3752         int mask, error = 0;
3753
3754         ASSERT_SERIALIZED(ifp->if_serializer);
3755
3756         switch (command) {
3757         case SIOCSIFMTU:
3758                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3759                     (BGE_IS_JUMBO_CAPABLE(sc) &&
3760                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3761                         error = EINVAL;
3762                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3763                         ifp->if_mtu = ifr->ifr_mtu;
3764                         if (ifp->if_flags & IFF_RUNNING)
3765                                 bge_init(sc);
3766                 }
3767                 break;
3768         case SIOCSIFFLAGS:
3769                 if (ifp->if_flags & IFF_UP) {
3770                         if (ifp->if_flags & IFF_RUNNING) {
3771                                 mask = ifp->if_flags ^ sc->bge_if_flags;
3772
3773                                 /*
3774                                  * If only the state of the PROMISC flag
3775                                  * changed, then just use the 'set promisc
3776                                  * mode' command instead of reinitializing
3777                                  * the entire NIC. Doing a full re-init
3778                                  * means reloading the firmware and waiting
3779                                  * for it to start up, which may take a
3780                                  * second or two.  Similarly for ALLMULTI.
3781                                  */
3782                                 if (mask & IFF_PROMISC)
3783                                         bge_setpromisc(sc);
3784                                 if (mask & IFF_ALLMULTI)
3785                                         bge_setmulti(sc);
3786                         } else {
3787                                 bge_init(sc);
3788                         }
3789                 } else if (ifp->if_flags & IFF_RUNNING) {
3790                         bge_stop(sc);
3791                 }
3792                 sc->bge_if_flags = ifp->if_flags;
3793                 break;
3794         case SIOCADDMULTI:
3795         case SIOCDELMULTI:
3796                 if (ifp->if_flags & IFF_RUNNING)
3797                         bge_setmulti(sc);
3798                 break;
3799         case SIOCSIFMEDIA:
3800         case SIOCGIFMEDIA:
3801                 if (sc->bge_flags & BGE_FLAG_TBI) {
3802                         error = ifmedia_ioctl(ifp, ifr,
3803                             &sc->bge_ifmedia, command);
3804                 } else {
3805                         struct mii_data *mii;
3806
3807                         mii = device_get_softc(sc->bge_miibus);
3808                         error = ifmedia_ioctl(ifp, ifr,
3809                                               &mii->mii_media, command);
3810                 }
3811                 break;
3812         case SIOCSIFCAP:
3813                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3814                 if (mask & IFCAP_HWCSUM) {
3815                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3816                         if (IFCAP_HWCSUM & ifp->if_capenable)
3817                                 ifp->if_hwassist = BGE_CSUM_FEATURES;
3818                         else
3819                                 ifp->if_hwassist = 0;
3820                 }
3821                 break;
3822         default:
3823                 error = ether_ioctl(ifp, command, data);
3824                 break;
3825         }
3826         return error;
3827 }
3828
3829 static void
3830 bge_watchdog(struct ifnet *ifp)
3831 {
3832         struct bge_softc *sc = ifp->if_softc;
3833
3834         if_printf(ifp, "watchdog timeout -- resetting\n");
3835
3836         bge_init(sc);
3837
3838         ifp->if_oerrors++;
3839
3840         if (!ifq_is_empty(&ifp->if_snd))
3841                 if_devstart(ifp);
3842 }
3843
3844 /*
3845  * Stop the adapter and free any mbufs allocated to the
3846  * RX and TX lists.
3847  */
3848 static void
3849 bge_stop(struct bge_softc *sc)
3850 {
3851         struct ifnet *ifp = &sc->arpcom.ac_if;
3852
3853         ASSERT_SERIALIZED(ifp->if_serializer);
3854
3855         callout_stop(&sc->bge_stat_timer);
3856
3857         /*
3858          * Disable all of the receiver blocks
3859          */
3860         bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3861         bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3862         bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3863         if (BGE_IS_5700_FAMILY(sc))
3864                 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3865         bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3866         bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3867         bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3868
3869         /*
3870          * Disable all of the transmit blocks
3871          */
3872         bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3873         bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3874         bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3875         bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3876         bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3877         if (BGE_IS_5700_FAMILY(sc))
3878                 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3879         bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3880
3881         /*
3882          * Shut down all of the memory managers and related
3883          * state machines.
3884          */
3885         bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3886         bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3887         if (BGE_IS_5700_FAMILY(sc))
3888                 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3889         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3890         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3891         if (!BGE_IS_5705_PLUS(sc)) {
3892                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3893                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3894         }
3895
3896         /* Disable host interrupts. */
3897         bge_disable_intr(sc);
3898
3899         /*
3900          * Tell firmware we're shutting down.
3901          */
3902         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3903
3904         /* Free the RX lists. */
3905         bge_free_rx_ring_std(sc);
3906
3907         /* Free jumbo RX list. */
3908         if (BGE_IS_JUMBO_CAPABLE(sc))
3909                 bge_free_rx_ring_jumbo(sc);
3910
3911         /* Free TX buffers. */
3912         bge_free_tx_ring(sc);
3913
3914         sc->bge_status_tag = 0;
3915         sc->bge_link = 0;
3916         sc->bge_coal_chg = 0;